CHANDIGARH UNIVERSITY

UNIVERSITY INSTITUTE OF ENGINEERING

Department of Electronics and Communication
Semester:2nd (ME)

Course Course Title Course Coordinator Lectu Tuto Prac Cr

Code res rials
ECT 664 SYSTEM VERILOG FOR Prof. Gurinder pal Singh, 4.0 0.0 0.0 4.0
DESIGN AND VERIFICATION E-code:-E1709

TextBooks
Sr No Title Author Edition Year Publisher Name
T-1 System Verilog for Chris Spear 2nd 2006 Springer
Verification

T-2 SystemVerilog for Stuart Sutherland 2nd 2010 Springer

Design

Reference Books
Sr No Title Author Edition Year Publisher Name
R-1 System Verilog Primer J.Bhaskar 1st 2010 Star Glaxy Publisher.

R-2 System Verilog Ashok B. Mehta 1st 2014 Springer

Assertions and
Functional Coverage

Schedule No. of Weeks No. of Scheduled Lectures: No. of Scheduled Tutorials

Weeks before 1st MST 5 20 N.A
Weeks before 2nd MST 5 20 N.A

Weeks before 3rd MST 4 16 N.A

Total 24 56 N.A

Detailed Plan for Lectures

Week Lecture Broad Topic(Sub Chapters/ Other Lecture Learning Pedagogical

Number Number Topic) Sections Readi Description Outcomes Tool
of ngs, Demonstrati
Text/refer Relev on/ Case
ence ant Study /
Week 1 Lecture 1 Fundamentals of books
T-1:1 Webs Definition of The Students will Images /
PPT
Test bench ites, Verification know What is animation /
Components Audi Process the goal of ppt etc.
o verification Planned
Visua
l
Week 1 Testing at T-1:1.1 Aids, Various types of Students will
Different Levels softw bugs are lurking various type
are in the design of problem
and related to
Virtu DUT
al
Labs
 Lecture 2 Basic Testbench T-1:3 Steps used in test Students will Ppt
Functionality bench understand
The purpose
of a testbench

Testbench T-1.9 Introduction to all Students will Ppt

Components components of understand
test bench importance of
each and every
component of
test bench
Layered Testbench T-1:10 How to make Students will Ppt
testing task easier be able to to
make task
easier by
dividing the
code into
smaller pieces
Week 1 Lecture 3 Built-In Data T- Introduction to Students will Ppt
Types 1:2.1 modification in be able to
Verilog data types understand
improved data
structures
compared
with Verilog.
Fixed-Size Arrays T- Declaring Students will Ppt
1:2.2 and study the Ppt
Initializing enhancement
Fixed-Size s that have
Arrays been made to
Lecture 4 Basic Array T- most classic
Operations 1:2.2. common way arrays
3 to manipulate
an array

Week .2 Lecture 5 Packed Arrays and T- How declare and Students will Ppt
unpacked arrays 1:2.2.. use Packed array be able to
6 handle data in
packed array
and unpacked
array

Dynamic Arrays T- Using a dynamic Students will Ppt

1:2.3 array for an be able to
uncounted list manage array
at run time

Lecture 6 Queues and T- Using a Queues Students will Ppt

Queues operations 1:2.4 array for an be able to
uncounted list manage array
at run time
and able to
increase and
decrease size
at run time
Associative Arrays T1:2.5 Using a Queues Students will Ppt
array for an be able to
uncounted list manage and
store entries
in a sparse
matrix
 Lecture 7 Array Methods T1:2.7 Array Reduction Students will Ppt
Methods, be able to
Array Locator search
Methods through an
array

Lecture 8 Array Methods T1:2.7 Array Sorting Students will Ppt

.3 and Ordering, be able to
Building a creates a
Scoreboard with scoreboard
Array Locator made from a
Methods queue of these
structures

Week 3 Lecture 9 Choosing a T1:2.8 guidelines for Students will Ppt

Storage Type choosing the be able to
right storage reduce the
type based on simulation
flexibility memory
usage

Lecture Creating New T1:2.9 How to combine Students will Ppt

10 Types with , several variables be able to
typedef T1:2.1 into a structure create new
Creating User- 0 data types
Defined Structures according to
testing
requirement

Lecture Type Conversion T1:2.1 The Static Cast Students will Ppt
10 1 Dynamic Cast be able to type
conversion of
test vetors

Enumerated Types T1:2.1 Various to add Ppt

2 Routines for additional
Enumerated controls to
Types your code but
not break
existing
codeto use
text macros
Week 3 Lecture Procedural T1:3.1 improvement Where to use Ppt
11 Statements, Task , 3.3 you may notice Procedural
and Function in statements
Overview SystemVerilog
routines.

Lecture Routine T1:3.4 C-Style Routine to add Ppt

12 Arguments Arguments, additional
Advanced controls to
Argument Types, your code but
Default Value for not break
an Argument existing code
to add
additional
controls to
your code but
not break
existing code
 Routine T1:3.4 Passing Ppt
Arguments Arguments by
Name, Common
Coding Errors,
Binding
arguments by
name

Week.4 Lecture The Interface T1:3.5 Using an Students will Ppt

13 Construct Interface to be able to do
Simplify improvement
Connections, to the DUT
Connecting
Interfaces and
Ports, Interface
with modports

Week 4 Lecture Using Modports T1:4.1 Creating an Students will Ppt

14 with a Bus Design Interface be able create
Monitor, a bus monitor
Interface Trade- using the
Offs MONITOR
modport
Lecture Driving Interface T1:4.4 Bidirectional Students will Ppt
15 Signals Through a .4 Signals in the be able to
Clocking Block Interface manage clock
in interface

Lecture The Clock T1:44. clock generator Students will Ppt

16 Generator .7 in program be able to
block manage clock
in Program
block
Week 5 Lecture Connecting It All T1:4.5 clock generator Students will Ppt
17 Together and , 4.6 in program be able to
Top-Level Scope block create things
in your
simulation
that are
outside of a
program
Lecture18 OOPS in System T1:5.1 Creating object, or module will
Students Ppt
Verilog and -5.6 classes , virtual be able to
various loops classes automate test
bench

Lecture Polymorphism and T1:5.7 Shallow copy, Student will Ppt

19 dynamic object -5.9 and deep copy able to link
creation from one class to layered test
other, managing bench concept
and utilizing with oops
resources of two terminology
different classes

Lecture Working with T1:7.1 Fork-join none, Student will Ppt

20 Threads Fork-join any to implement
parallelism in
test bench
Week 1st MST
XX

Week 6 Lecture Interprocess T1:7.4 Events, Students will Ppt

21 Communication .1- Blocking on the be able to
7.4.3 Edge of an control the
Event, flow of events
Waiting for an in a testbench
Event Triggers

Lecture Interprocess T1:7.4 Passing Events, Ppt

22 Communication .4 Waiting for
Multiple
Events,
Waiting for
multiple threads
by counting
triggers

Lecture Semaphores T1:7.5 Semaphore Students will Ppt

23 .1- Operations, be for mixing
7.5.2 Semaphores with different-
Multiple Keys sized requests
in parallel
Lecture Mailboxes T1:7.6 mailbox with Students will Ppt
24 - 7.6.1 multiple handles be able to
to multiple make
objects, Mailbox communicate
in a Testbench various
testbench
components.
Week 7 Lecture Mailboxes T1:7.6 Bounded Students will Ppt
25 .2- Mailboxes, be to when the
7.6.3 Unsynchronized input stimuli
Threads is complete by
Communicating waiting for
with a Mailbox, any of the
Producer threads.
consumer
without
synchronization
Lecture Threads T1:7.6 Synchronized Students will Ppt
26 synchronization .5- Threads Using a be able to
7.6.6 Mailbox and synchronize
Event, the two threads
Synchronized And able to
Threads Using control the
Two Mailboxes flow of test
vectors from
random class
Lecture Building a T1:7.7 Basic Transactor, Students will Ppt
27 Testbench with Environment class, be able to
Threads and IPC Test Programs model as
many
independent
blocks
running in
parallel
Lecture Down casting and T1:8.3 Copying a base Students will Ppt
28 Virtual Methods handle to an be
extended handle, comfortable
Virtual Methods using handles
with extended
classes
Week 8 Lecture Abstract Classes T1:8.6 Abstract class Abstract Ppt
29 and Pure Virtual with pure virtual classes and
Methods methods, Bodies pure virtual
for Transaction methods let
methods students to
build
testbenches
that have a
common
Look.
Lecture Parameterized T1:8.8 A Simple Stack, This Ppt
30 Classes Parameterized Technique
generator class helps students
using blueprint to learn how
pattern to reduces
your debug
effort.
Lecture Functions and T1:8.9 Difference Students will Ppt
31 tasks between be able to
functions of develop their
verilog and subprogram
system verilog for large tasks
and same for to reduce
tasks efforts of
repetitive
work.
Lecture Randomization T1:6.1 Randomization Students will Ppt
32 in be able to
SystemVerilog create a class
to hold a
group of
related
random
variables, and
then
have the
random-
solver fill
them with
random
values
Week 9 Lecture Simple Class with T1:6.2 Randomization Ppt
33 Random in
Variables SystemVerilog
Lecture The Constraint T1:6.3 process of Students will Ppt
34 Solver solving trie to assign
constraint new values to
expressions random
variables and
to
make sure all
constraints are
satisfied
Lecture Weighted T1:6.4 Students will Ppt
35 Distributions learn the
technique for
creating
weighted
distributions
so that some
values are
chosen more
often than
others
 Lecture Set Membership T1:6.4 Use of inside Students will Ppt
36 and the Inside .5 operator, and learn how to
Operator solver function bound random
vector.

Week 10 Lecture Conditional T1:6.4 If-else Students will Ppt

37 Constraints .7 constraints and learn the use
bidirectional of Right
constraints Arithmetic
Operator to
Boost
Efficiency

Lecture Solution T1:6.5 Unconstrained, Students will Ppt

38 Probabilities Class with learn how to
implication calculate the
probability for
counting the
probability of
random test
vector

Lecture Guiding T1:6.5 Class with Students will Ppt

39 Distribution with .4-6.6 implication and learn how to
solve...before solve...before, validate
Controlling transaction,
Multiple
Constraint
Blocks
Lecture In-line T1:6.8 The randomize () Students will ppt
40 Constraints with statement learn how to
write more
tests, you can
end up with
many
2nd MST constraints

Week 11 Lecture Functional T1.9 Introduction and Students will Ppt

41 Coverage need of learn why
Functional coverage is
Coverage required in
test benches

Lecture Various type of T1.9.1 Code Coverage, Various types Ppt

42 coverages Functional of coverage
Coverage, will be
Assertion introduced to
Coverage students

Lecture Functional T1.9.2 Gather Students will Ppt

43 Coverage Information, Not learn relation
Strategies Data, Only between
Measure What functional and
You Are Going code coverage
to Use,
Measuring
Completeness

Lecture Simple Functional T1:9.3 Functional Students will Ppt

44 Coverage coverage of a learn how to
Example simple object develop
variation plan
for writing
functional
coverage
Week 12 Lecture Anatomy of a T1:9.4 Defining and Student will Ppt
45 Cover Group -9.5 using a Cover be able to
Group in a Class. define end
Triggering a trigger
Cover Group coverage of a
test bench
with the help
of cover
groups

Lecture Data Sampling T1:9.6 Individual Bins Student will Ppt

46 .1 and Total learn How is
Coverage coverage
information
gathered

Lecture Creating Bins T1:9.6 Limiting the Student will Ppt

47 Automatically .2 Number of be able to
Automatic Bins manage bins.
Created

Lecture User-Defined T1:9.6 bins Ppt

48 Bins Find a Bug .5 development for
transaction
length
Week 13 Lecture Conditional T1:9.6 Conditional Student will Ppt
49 Coverage .7 coverage learn use of
disable during iff keyword to
reset, add a
Using stop and condition to a
start functions cover point

Lecture Creating Bins for T1:9.6 Functional Ppt

50 Enumerated .8 coverage for an
Types enumerated type
Lecture Transition T1:9.6 Specifying Student will Ppt
51 Coverage .9 - transitions for a able to create
9.10 cover point, multiple states
Wildcard States and
and Transitions transitions
Lecture Ignoring Values T1:9.6 Cover point with Student will Ppt
52 and Illegal Bins .11-12 auto_bin_max learn use of
and ignore_bins illegal_bins to
catch states
that were
missed by the
tests error
checking
Week 14 Lecture Cross Coverage T1:9.7 Basic Cross Student will Ppt
53 Coverage define bins
Example, that contain
Specifying cross multiple
coverage bin values, the
names coverage
statistics
change

Lecture SystemVerilog T1:4.8 Immediate Student will Ppt

54 Assertions .1-2 Assertions learn use of
assertions
Lecture SystemVerilog T1:4.8 Concurrent Ppt
55 Assertions .3 Assertions
Lecture SystemVerilog T1:9.1 Assertion Students will Ppt
56 Assertions .4 Coverage learn to
calculate the
coverage of
an assertion

3rd MST
 Schedule of Assignment

Assignment No. Date of Allotment Last date of Submission Content of Assignment

(Assignment to be allotted
group-wise)
01 02-Feb-17 20-Feb-17 G1: Data types
Covering Unit-1 G2: Arrays, Dynamic Arrays
02 16-03-2017 03-04-2017 G1: Oops in SVM
Covering Unit-2 G2: Interface and Clocking
block, Threads
03 17-04-2017 01-05-2017 G1: Randomization
Covering Unit-3 G2: Functional Coverage,
Assertions

Details of Academic Task(s)

AT Objective Topic of the Academic Nature of Evaluati All Date of
No. Task Academic on Mode ot uploading
Task me of Model
(group/ind nt / Answer
ividuals/ submissi Sheet on
field work on Week UIMS/
Notice
Board with
marking
scheme
MST-1 To check the Data types, Arrays, Individual Step 13/02/17 Within week
conceptual Interface, clocking block, Marking - after the
ability of type casting. Functions and 15/02/17 conduct of
students for new tasks, Mdports exam
data types in
system verilog
and check their
understanding
towards the
concept of
interface and
clocking block

MST-2 To test the Threads. Events, OOPs in Individual Step 14/03/17 Within week after
'Fundamentals SVM, Randomization Marking. - the conduct of
of 23/03/17 exam
Refrigeration'
of students,
gain of
knowledge of
'Air
Refrigeration
Cycles' and
MST-3 'Single
To test Stage
the Functional Coverage, Individual Step 26/04/17 Within week after
Vapour
conceptual & Assertions Marking - the conduct of
Compression
analytical 28/04/17 exam
System'.
skills of
students based
on
'types of
Refrigerants',
'Vapour
Absorption
Assignment To checkand
system', the Data types, Arrays, Individual Step 02-02-
No.-1 understanding
'Psychrometry'. Interface, clocking Marking 17---20-
(Element-1) of students for block, type casting. 02-2017
the topics Functions and tasks,
mentioned in Mod-ports (Details of
Assignment All sub topics are given
sections in lecture plan ; Lecture
1- lecture 20 )
Assignment To check the Threads. Events, OOPs Individual Step 16-03-
No.-2 understanding in SVM, Randomization Marking 17--03-
of students for (Details of All sub topics 04-2017
the topics are given in lecture plan ;
mentioned in Lecture 21- lecture 40)
Assignment Assignment
To check the Functional Coverage, Individual Step 28-04-
No.-3 sections
understanding Assertions (Details of Marking 17--01-
of students for All sub topics are given 05-2017
the topics in lecture plan ; Lecture
mentioned in 41- lecture 56 )
Assignment
sections

Element-2 To evaluate Topics are mentioned in Individual Step

(Surprise the student Curriculum Marking
Test) performance
and topic
understanding
from the
topics
mentioned in
curriculum

Element-3 To evaluate Topics are mentioned in Individual Step

(Quiz) the student Curriculum Marking
performance
and topic
understanding
from the
topics
mentioned in
curriculum

Signature of Course Coordinator

E-Code:

Signature of HoD with Stamp