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ICT (In Circuit Test)

ICT Agilent 3070


ICT GenRad 228x
ICT Teradyne
Spectrum
ICT

PCB

Fixture

ICT TESTER
ICT FT
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ICT5
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Agilent ICT Tester
Agilent 307x Series 3 Architecture
Testhead Layout

BRC:Bank,Row,Column :20378,203178
Configuring a Four-Module System
Cards
HybridPlus Pin Card ASRU - Rev A,B or C
Double Density Hybrid Control
ChannelPlus Pin Card ControlPlus
AccessPlus Pin card ControlXT
Analog Pin Card
Double Density Analog Pin Card
Serial Test Pin Card
System config file
PATH:/hp3070/diagnostic/th1/config
testhead name "testhead1"
line frequency 50
relay 1 controls vacuum 2,3
relay 2 controls vacuum 0,1
bank 1
module 0
cards 1 asru
cards 2 hybrid advanced ! double density
cards 3 hybrid advanced ! double density
cards 4 hybrid advanced ! double density
cards 5 hybrid advanced ! double density
cards 6 control plus
cards 7 hybrid advanced ! double density
cards 8 hybrid advanced ! double density
cards 9 hybrid advanced ! double density
cards 10 hybrid advanced ! double density
cards 11 hybrid advanced ! double density
supplies hp6624 13 to 16 ! asru channels 1 to 4
ports ext7, ext8
end module
module 1
.
End module
end bank
bank 2

end bank
Board level config file
module 2
cards 1 asru c revision
cards 2 hybrid standard double density
cards 3 hybrid standard double density
cards 4 hybrid standard double density
cards 5 hybrid standard double density
cards 6 control plus
cards 7 hybrid standard double density
!@ cards 8 hybrid standard double density
!@ cards 9 hybrid standard double density
!@ cards 10 hybrid standard double density
!@ cards 11 hybrid standard double density
supplies 5 to 8
end module

module 3
cards 1 asru c revision
!@ cards 2 hybrid standard double density
!@ cards 3 hybrid standard double density
!@ cards 4 hybrid standard double density
!@ cards 5 hybrid standard double density
cards 6 control plus
cards 7 hybrid standard double density
cards 8 hybrid standard double density
cards 9 hybrid standard double density
cards 10 hybrid standard double density
cards 11 hybrid standard double density
supplies 1 to 4
end module
Short Wire Fixture Architecture
Command control testhead

Testhead power on
fix lock, fix unlock-----compressed air
faon,faoff ------Vacuum
vacuum well is

faon fbon

Vacuum well a is 2,3 Vacuum well b is 0,1


GenRad 2287 tester
GenRad Hardware Overview

Windows NT Fixture

GenRad RECEIVER
MXI Bus

DSM BOARD

AFTM CARD
IEE-488

REFERENCE

PIN CARD
PIN CARD

PIN CARD

PIN CARD
RST

C/S/T
MTG

ICA
0 1 3 3 4 5 6 31 32 33 34
UUT PS
PIN BAY
MXI to GenRad board
MTG Functional blocks are MXI to GR businterface

Run Time Controller


Bus interface for the analog subsystem directs & coordinaes pin
RTC board activities; data transfers between cpu and the digital
subsystem

Clock/synchronus/trigger board
CST Privides event timing and event detection

Driver/Sensor reference
Reference Supplies programmed dc reference voltages for the D/S pin
boards

DSM Deep Serial Memory


D

AFTM Analog Functional Test Module

In-Circuit Analog Module


ICA
GenRad
228x Series
Architecture

Solectron Confidential
TESTPLAN
Sub Pre_Shorts
call Pre_shorts
Subend
call Shorts Sub Shorts
. Test shorts
Call Analog_tests Subend
Sub Analog_Tests
Call testjet Test analog/c4
Test analog/r56
Call digital
subend

Sub Characterize Sub Digital_Tests
learn capacitance on Test digital/u1
learn capacitance off Test digital/u2
subend
subend

Typical Example of Analog Test
disconnect all
connect s to N1
Resistor typical test program: connect I to N2
connect g to N100
resistor 10k, 5.5,5,re5,ar0.1
1. S bus 4. A bus
2. I bus 5. B bus
3. G bus 6. L bus
enhancement
Capacitor Test

Capacitor test: Inductor test:

Zc=1/2fc C=1/2 f Zc ZL =2fL


Capacitor test file

!!!! 2 0 1 1002945327 0000


! IPG: rev B.03.42 Sat Oct 13 11:55:28 2001
! Common Lead Resistance 100m, Common Lead Inductance 1.00u
! Fixture: EXPRESS
on failure
report parallel devices
report "r1 15.0k"
end on failure
disconnect all
connect s to "GND"; a to "GND"
connect i to "TREE__1022"
connect g to "+5"
capacitor 100n, 13.4, 8.66, fr1024, re3, wb, ar100m, sa, en,
nocomp
off failure
Diode & Zener Test
Diode Test File

!!!! 2 0 1 885232159 0000


! IPG: rev B.02.54 Mon Jan 19 09:49:20 1998
! Common Lead Resistance 500m, Common Lead Inductance
1.00u
! Fixture: EXPRESS
disconnect all
connect s to "VCC"
connect i to "$34"
diode 728m, 413m, idc5.0m, co3.0, ar828m
FET Test Configuration
FET Test File

!!!! 2 0 1 924217662 0000


! IPG: rev B.03.13 Wed Mar 31 11:25:15 1999
! Common Lead Resistance 500m, Common Lead Inductance 1.00u
! Fixture: EXPRESS
on failure
report parallel devices
report "q23 q23:fet 100, 20.0"
end on failure
disconnect all
connect s to "TREE89"
connect i to "B0"
connect g to "VF"
nfetr 81.6, 10.0, re1, ar50.0m
Test Options

am amplitude sa use the A bus to sense the S bus


ar ASRU range sb use the B bus to sense the I bus
idc DC current sl use the L bus to sense the G bus
comp ---- capacitor compensation en enhancement
nocomp----No compensation ed extra digit
fr frequency co voltage compliance
re reference element ico current compliance
wa wait wb wideband
TESTPLAN
Sub Pre_Shorts
call Pre_shorts
Subend
call Shorts Sub Shorts
. Test shorts
Call Analog_tests Subend
Sub Analog_Tests
Call testjet Test analog/c4
Test analog/r56
Call digital
subend

Sub Characterize Sub Digital_Tests
learn capacitance on Test digital/u1
learn capacitance off Test digital/u2
subend
subend

The parts of a Digital Test

! Declaration Section
! Device Type
! assignment section
! Timing Section
Details are covered
in Advanced Digital
Class
! Vector Definition Section
Vector Initial_State
set Reset to 0
set CS_bar to 0
...
! Vector Execution section
unit Test Reset
execute Initial_State
execute Assert_reset
.
1 Input 1 Input2 Output
3
2
E1 0 0 1
4
6 E1 0 1 1
5
E1 1 0 1
9
8 E1 1 1 0
10

12
13
11 Truth Table

NAND GATE
Digital library (Declaration Section)
! 7400
! NAND, 2-Input, Quad
! revision A.01.00

combinatorial
vector cycle 500n
receive delay 400n
assign VCC to pins 14
assign GND to pins 7

assign E1_Inputs to pins 1,2


assign E2_Inputs to pins 4,5
assign E3_Inputs to pins 9,10
assign E4_Inputs to pins 12,13

assign E1_Output to pins 3


assign E2_Output to pins 6
assign E3_Output to pins 8
assign E4_Output to pins 11

power VCC, GND

family TTL

inputs E1_Inputs,E2_Inputs,E3_Inputs,E4_Inputs
outputs E1_Output,E2_Output,E3_Output,E4_Output
Digital library test (Vector Definition Section)
vector E1_Input_00 vector E4_Input_00
set E1_Inputs to "00" set E4_Inputs to "00"
set E1_Output to "1" set E4_Output to "1"
end vector end vector

vector E1_Input_01 vector E4_Input_01


set E1_Inputs to "01" set E4_Inputs to "01"
set E1_Output to "1" set E4_Output to "1"
end vector end vector

vector E1_Input_10 vector E4_Input_10


set E1_Inputs to "10" set E4_Inputs to "10"
set E1_Output to "1" set E4_Output to "1"
end vector end vector

vector E1_Input_11 vector E4_Input_11


set E1_Inputs to "11" set E4_Inputs to "11"
set E1_Output to "0" set E4_Output to "0"
end vector end vector

0 set a logic low on the node.
1 set a logic high on the node.
K keep the previous state.
T toggle from the previous state.
Z set the device to a high impedance state.
X dont care this receiver.
Digital library (unit section)
unit "Element number 1"
execute E1_Input_11
execute E1_Input_01
execute E1_Input_00
execute E1_Input_10
end unit

unit "Element number 2"


execute E2_Input_11
execute E2_Input_01
execute E2_Input_00
execute E2_Input_10
end unit

unit "Element number 3"


execute E3_Input_11
execute E3_Input_01
execute E3_Input_00
execute E3_Input_10
end unit

unit "Element number 4"


execute E4_Input_11
execute E4_Input_01
execute E4_Input_00
execute E4_Input_10
end unit
Overdrive and Backdrive
VCC

Vector E1_Input_11
A set A to 1
C
set B to 1
B
set C to 0
end vector

VCC

Back drive current


standard_cmos safeguard file

PATH:/hp3070/standard/safeguard/standard_cmos

!!!! 8 0 1 591688800 0000


parameters "standard_cmos"
!
! subfamily : standard CMOS
!
! characteristics : low level output current <= 3 mA
! Vcc = 5 V
!
backdrive current of 0.005 for "0" , 0.050 for "1"
overdrive power 0.02 , 0.02 dissipated by heat source
heat source 100 by 10 , 1 per output
operating temperature 40
thermal resistance 60
package ceramic
end parameters
Library level Safeguard File
! Standard Safeguard Template

include "standard_cmos"

use parameters "standard_cmos" for "TL7702AH_1"


use parameters "standard_cmos" for "28SCID0490CH_1"
use parameters "standard_cmos" for "74ABT244H_3"
use parameters "standard_cmos" for "74F08H_1"
use parameters "standard_cmos" for "S02F"
use parameters "standard_cmos" for "358H_2"
use parameters "standard_cmos" for "74F112H_2"
use parameters "standard_cmos" for "74F175H_1"
use parameters "standard_cmos" for "74F74H_2"
use parameters "standard_cmos" for "74F163H_1"
use parameters "standard_cmos" for "74F32H_1"
use parameters "standard_cmos" for "10H125P_3"
use parameters "standard_cmos" for "74F38H_1"
Board level Safeguard File
parameters "standard_cmos"
backdrive current of 5m for "0", 50m for "1"
bond wire 2540 by 25.4
heat source 100 by 10, 1 per output
operating temperature 40
overdrive power 20m, 20m dissipated by heat source
package ceramic
thermal resistance 60
end parameters

use parameters "standard_cmos" for "u1"


use parameters "standard_cmos" for "u2"
use parameters "standard_cmos" for "u3"
use parameters "standard_cmos" for "u4"
use parameters "standard_cmos" for "u5"
use parameters "standard_cmos" for "u6"
use parameters "standard_cmos" for "u8"
use parameters "standard_cmos" for "u9"
use parameters "standard_cmos" for "u10"
use parameters "standard_cmos" for "u11"
use parameters "standard_cmos" for "u12"
Digital compiler safeguard check
Digital/u15
--------------------------------------------------------------
C O M P I L A T I O N S U M M A R Y
-------------------------------------
31 vectors executed
19 vector Ram slots used ,0% full
32 sequence ram slots used,0% full
13 directory ram slots used, 0% full

S A F E G U A R D S U M M A R Y
--------------------------------
safeguard status :Not Inhibited
Estimated test time:3.60e-05
Safe Test time(device):5.99e-01(u16)

201 lines,0 errers,0 warnings,object produced


The Setup_Power_Supplies Routine
sub Setup_Power_Supplies
global Pslimit
cps
sps 1,5.00,0.50;optimize |rps 1 ,V,I|print V,I
sps 2,5.00,2.00;optimize
Pslimit = pslimit
pass device
if Pslimit then
dps
fail device
I=1
for Pscount=1 to 2
if binand(Pslimit,I) then
report Power Supply Number
report Pscount
report In Current Limit
end if
I=2*I
next Pscount
report ------------------------------------
report Check for backwards
report ICs or Capacitors.
report ------------------------------------
end if
subend
Disable issue

cs
Upsteam UUT1
device U1

U21

Input

UUT2 output
U2
Disable description in library
! QMV288 U21 Library
! setup only
! revision A.01.00

vector cycle 500n


receive delay 400n

assign VCC to pins 1,2,3,4,5


assign GND to pins 25,26,27,29,30

assign IO to pins 5,6,7,8,9,10,11,12,13,14,15,16


assign IO to pins 17,18,19,20,21,22,23,24
assign CS to pins 28

family TTL
power VCC,GND

inputs CS
bidirectional IO
disable IO with CS to "0"
Disable in execute test
!U2 executable test
assign Disablegroup to nodes "TREE__1343 default "0"
inputs Disablegroup

assign DisableFamilyTTL to nodes "TREE__1343"

family TTL on DisableFamilyTTL


inputs DisableFamilyTTL

!IPG: Safeguard will ignore disabled outputs


disabled device "u21" pins 5,6,7,8,9,10,11,12
disabled device "u21" pins 13,14,15,16,17,18,19
disabled device "u21" pins 20,21,22,23,24
!IPG: with pin 28 on node "TREE__1343"

The node TREE__1343(U21 Pin CS) keep at low level during U2 Test
Analog Functional Resource

s :Source

a:auxiliary source

i: detector high
l: detector low

rcva,rcvb,rcvc:frequency detector
Resource specification
Source range unit
------------------------------------------------------------
DCV -10 - +10 Vdc
SINE 0 - 7.0 Vrms
SQUARE 0 - 10 Vpk
TRIANGLE 0 - 10 Vpk

Auxiliary source : -10 - +10 Vdc

Frequency detector: 1 - 60 MHz


Analog Function Test File

!IPG: rev B.03.42 Sat Oct 13 11:56:05 2001


! Quad TTL-ECL Translator

test powered analog


power pins "8", "9","16"
nonanalog pins 6
connect l to ground
test "TRANSLATOR1_4"
test "TRANSLATOR1_2"
end test
!-----------------------------------------------------------------------
subtest "TRANSLATOR1_4"
connect s to pins 5
connect i to pins 4
source dcv, amplitude 2.5, icompliance 1, on
detector dcv, expect -2
measure -1.6,-2
wait 50m
source dcv, amplitude 0.3,icompliance 1, on
detector dcv, expect -1
measure -0.7,-1
end subtest

subtest "TRANSLATOR1_2"
......
end subtest
Frequency Test

test powered analog


power pins 7,14
nonanalog pins 1
test "OUTPUT"

end test

subtest"OUTPUT"

connect rcvc to pins 8


detector frequency, expect 49.152M
measure 49.152M * 1.0005,49.152M * 0.9995

end subtest
How Testjet do?

Devices HP TestJet HP Connect Check

devices with an internal lead frame


(most digital and hybrid devices) X

devices with an internal ground plane


(usually ceramic packages) X

most Ball Grid Arrays (BGAs)


(except ceramic and stadium packages) X
some Ball Grid Arrays (CBGAs)
(ceramic and stadium packages only) X
connectors and sockets X
devices with grounded heat sink X
flip chip devices or chip-on-board (COB) X
dip switches X
pushbuttons X
HP TestJet Architecture

HP TestJet is an unpowered test of the connectivity from each pin on a


device to the circuit board. The system uses the HP TestJet hardware to
measure the capacitance from a pin of a device to the HP TestJet probe.
The measurement is repeated for each pin on the device, except power and
ground pins. Pins that are tied together are tested as one pin.

Remark:The S (source) bus to the pin being tested,the I (input) bus to the HP TestJet probe,and the
G(guard) bus to all other pins on the device.
The "testjet" File
The "testjet" file is the test file for all devices to be tested with HP TestJet; this
one test file includes the tests for all HP TestJet devices.
default threshold low 200 high 10000
default throughput adjustment 1!throughput adjustment 0
device "u101;threshold low100 high 10000
test pins 1
test pins 2,3
test pins 4,5,6
! test pins 7 ! Ground pins commented by HP IPG.
test pins 8
test pins 11;threshold low 20 high 10000
test pins 12
test pins 13
! test pins 14 ! Fixed pins commented by HP IPG.
inaccessible pins 9,10
end device
The "default threshold" statement sets the test thresholds for all the devices in the file.
The "default throughput adjustment" statement enables or disables throughput
adjustment for all the devices in the file.
There is a "device/end device" block for each device to be tested. The "device" statement
specifies the device designator. If the device is mounted on the bottom side of the board,
the "device statement includes the "bottom" keyword.
The "test pins" statement specifies the pin or pins to be tested. Pins that are tied together in
the circuit are specified and are tested together.
The "inaccessible pins" statement declares pins that are not tested because they are not
accessible.This statement always appears at the end of the device block.
Testjet Probe Assemble
Testjet Probe Assemble
HP TestJet Probe and Mux Card Connections.
Pin Numbers for the Right-Angle Connector.

Mux Card Jumpers J4 and J5.


An Example of HP TestJet Wiring in the Top Side of the Fixture.
TESTPLAN
Sub Pre_Shorts
call Pre_shorts
Subend
call Shorts Sub Shorts
. test shorts
Call Analog_tests Subend
Sub Analog_Tests
Call testjet Test analog/c4
Test analog/r56
Call digital
subend

Sub Characterize Sub Digital_Tests
learn capacitance on Test digital/u1
learn capacitance off Test digital/u2
subend
subend

A Short is an impedance, between two nodes, that is less than or equal
to the threshold impedance.

An Open is an impedance, between two nodes, that is greater than the


threshold impedance.

A Shorts Test is testing for unexpected shorts on the board; it requires the
impedance between nodes to be greater than the threshold (open) to give a
PASS indication.

An Opens Test is testing for unexpected opens on the board; it requires


impedance between nodes to be less than or equal to the threshold (short)
to give a PASS indication.
Shorts Test file
!!!! 9 0 1 974538053 0000
!IPG: rev B.03.42 Sat Nov 18 17:00:54 2000
threshold 8
settling delay 50.00u
short "#:N6" to "#:N90"
short "#:2V5" to "#:N142"
short "#:N9" to "#:2V5"
short "#:3V3" to "#:N4" Open test
!short "#:N213" to "#:N7" ! A node is not accessible
!short "#:-48V" to "#:N212" ! A node is not accessible
report phantoms
threshold 1000
nodes "#:-48V"
nodes "#:N7"
nodes "#:N213"
nodes "#:N254"
nodes "#:N143"
!nodes "#:N146" ! Node not accessible
settling delay 3.740m Shorts test
nodes "#:5V"
settling delay 50.00u
nodes "#:N10"
!nodes "#:N11" ! Node not accessible
nodes "#:N13"
Open test

short A to D

source
S
A
B
C
detector
D
D
Shorts test

Detection:Detection selects the first node in the "shorts" file to


connect to a source; it connects all the following nodes in
the shorts list to a detector.

Isolation:If detection find shorts the isolation is invoked to find


the exact shorted nodes by a process of bisection .
Isolate a short

3.isolation
1.Check node A

2.Check node B 4.find A short to D

find short
Phantom shorts

Phantom short :detection find short but isolation cant find


Shorts test report options

report netlist
report netlist, common devices
report common devices
report common devices, netlist
report phantoms
report limit <# of nodes>
ICT Fixture Software Develop Process

Collect Material Cad Translate Generate Test Program Debug

HP3070
SOFTWARE
Fixture File &
Test program
FABMASTER GENRAD
CAD File SOFTWARE

TAKAYA
Test program

GC-PLACE
Gerber File
TEST DEVELOPMENT PROCESS
First : Gather the materials
(Schem.,BOM,CAD,Datasheet,loaded board)
Second: Describe the board to the HP 3070.(Fabmaster,board
consultant)
Third : Let the HP 3070 generate tests and fixture files(IPG).
Third: Evaluate the files the HP 3070 generated.Is the test
sufficient? Are there details omitted? Should changes
be made and the Test Generation process be re-run?
Fourth: Build a fixture
Fifth : Turn on each test.Are there tests that require debug? If
so,debug those tests.
Sixth : Release test to production.
Seventh: Perform an ECO(Engineering Change Order)as needed.
Gathering
Materials

The Materials
Schematic Diagram
CAD Data(contain x-y information,netlist)
BOM
Part Datasheet
Blank PC board
Loaded PC board(known good)
knowledge of Board Test Consideration
Describing the PC board to the System
What does the HP 3070 software need and what
tools are available?
The software needs a description of the testhead hardware.
For the HP 3070 software to accomplish this,it needs a clear,concise
clear,concise
picture of the PC board.This includes the physical characteristics
characteristics of
the board,the locations of the components on the board,the locations
locations of
vias and testpads.It
testpads.It also needs the value of the analog parts on the
board and the tolerance of each device.The generic part number of
of the
digital devices on the board is also needed.Given this information,the
information,the
HP 3070 will create tests for the analog devices and use libraries
libraries of
tests for the digital devices.
For the testhead configuration,you will use BT-
BT-BASIC editor to create
the config
configfile.This describes the testhead hardware to be used when
creating the fixture and test files for this board.
HP Board Consultant

even if a complete description of the PC board is available from CAD data,you


still need to use HP Board Consultant to describe details about the test that
CAD data was never intended to include.
Board Description Column
View/Edit Physical Board Data
Board Outline
Board Tooling Holes
View/Edit Board Description entries.
View/Edit Test System Data
Entering a Power Node
Entering a Fixed Node
Entering Board Level Disable/Conditions
Entering the Integrated Program Generator Global Options
Family Options
The Fixture Options
Enter General Purpose Relays
The Keepout Area
Enter Groups
Extra Probing Locations
Test System Data Compile and Verify
Configuration File Instructions
Verify Fixture Type
Verify Configuration Size
Verify Node Probing
Verify Power Probing
Verify Ground Probing
A description of the probe location attributes

mandatory
This forces the system software to locate the probe at the specified location.
preferred
This marks the specified location as the one you would like to see probed if there
are no other considerations that would prevent this location from being used.
unreliable
This marks the location as one to use but only if no others are available.
no_access
This flags the given location as being one that cannot be probed.
no_probe
This tells the software that the associated location is prohibited from being a valid
probe location.
Inputs Running IPG Outputs
board.o pins file

analog directory
board_xy
board_xy.o
.o
digital directory

library tests IPG functional directory


(Integrated Program Generator)
mixed directory

Config.o
Config.o testorder file

ipg/summary
ipg/summary file

ipg/details
ipg/details file

ipg/dependencies.o
ipg/dependencies.o
Final Compile/Verify & Generate Testability Report

Save Files
Compile Files
Generate a testability.rpt

The Testability Report will summarize all the


information presented so far,make
comparisons,verifications,check for source
files,etc.The end result will be a summary of
what the system finds is missing,incorrect or a
potential problem for HP IPG Test Consultant.
Fixture Files Structure
details drill

wirestop.p drillsup

drilltop
wires.p

fixture.o
wires Fixture

inserts
trace
probes.p
testjet_mux
summary probesyop.p
Explanation of all fixtures files

details file
The Details Report contains all the information provided by the Summary
Report with detailed explanations. When the Fixture Generation Software is
run in incremental mode (for ECOs) the Details Reports also contains
information about wiring that needs to be added or deleted from the existing
fixture.
drill file
The drill files contain drill tool and X-Y coordinate information for the probe
plate . The information is in a common format for numerically controlled
machines.
drillsup file
Drilling information for the support plate.
drilltop file
Drilling information for the top probe plate.
fixture.o file
The placement is specified in the fixture.o file, and includes the board outline
coordinates, tooling pin hole and locations, board placement specifications,
fixture part number, and fixture options.
insert file
The Fixture Inserts Report contains information for inserting pins, receptacles,
and probes.
Revolutionizing PCB
Testing

WHY
Boundary Scan
PCB Testing is Challenging

High Density
Device
Complexity
SMD
BGA
MCM
Multi-Layer

Traditional In-Circuit Test mandates Test Point for every


net.
Test inaccessibility is the major problem.
Boundary Scan Test is the only solution.
Power of Boundary Scan Test
Boundary Scan Test eliminates Test
Probes.

A Boundary Scan
Device
IEEE 1149.1
Architecture
Engineers turn to technologies like boundary scan
which dont need physical access to perform design
debug, manufacturing and field test, as well as in-
system configuration for programmable devices.

- Bode Enterprises, Inc. A market research


firm
Benefit of Boundary Scan Test
l Reduces test points on board.
Minimizes board area.
Simplifies routing layout.
Preserves signal integrity for high speed
communication design.
Access complex IC such as BGA.

Test Case Nets BS Components Test points may be


reduced
Lennon 9932 106 1634
Nimain 2482 10 197
Crux 5999 30 2664
The Market
$Billions

15

10

0
1999 2000 2001 2002 2003
The total U.S. demand for printed circuit boards,
estimated at $9.194 billion in 1998, is projected to
increase at an annual average growth rate of 7.2% to
reach $13 billion in 2003.
Source: BUSINESS COMMUNICATIONS CO., INC.,
The Market -Continue

Boundary Scan Market Growth


(%)

300
250
200
150
100
50
0
2001 2002 2003 2004

The boundary-scan market will grow at more than 40 percent


each year through 2004.
Source: Bode Enterprises, Inc., a California market research firm.
Revolutionizing PCB
Testing

HOW
Boundary Scan
Introduction to Boundary-
IEEE StandardScan
1149.1-1990
Background
Current in-circuit and functional testing techniques are becoming less effective because of node access
problems and the inability of testers to cover all nodes. Conventional techniques are becoming less
efficient because test development requires longer time investments; time-to-market lengthens and test
costs increase.
These problems were viewed with such a concern that, in 1985, several European companies formed a
group called JETAG (Joint European Test Action Group). Later several American companies joined this
group, which was renamed JTAG (Joint Test Action Group). JTAG conceived the boundary-scan technique
to address these problems; it was finally documented in the JTAG Rev 2.0 proposal in 1988.
A proposal to develop this technique was handed off to the Institute of Electrical and Electronics
Engineers (IEEE) and was refined by the IEEE working group. During 1989, IEEE P1149.1 went out to
ballot, and in early 1990 it became IEEE Standard 1149.1-1990, IEEE Standard Test Access Port and
Boundary-Scan Architecture. The standard defines how to design testability features into digital devices,
which will simplify testing. These features can be used in device testing, incoming inspection, board test,
system test, and field maintenance and repair.
What is Boundary-Scan?
Boundary-Scan is a test technique that involves devices designed with shift registers placed between
each device pin and the internal logic as shown in Figure 1. Each shift register is called a cell. These cells
allow you to control and observe what happens at each input and output pin. When these cells are
connected together, they form a data register chain, called the Boundary Register.
Boundary-Scan devices have a dedicated port, called the Test Access Port (TAP), that routes input
signals to a controller, called the TAP Controller.

Test Data In (TDI) the serial input for test data and instruction bits
Test Data Out (TDO) the serial output for test data
Test Clock (TCK) an independent clock used to drive the device
Test Mode Select (TMS) provides the logic levels needed to
change the TAP Controller from state to state
Test Reset (TRST*) an optional input signal used to reset the
device (the * indicates that this is an active-low input signal)
The Manufacturing Fault Spectrum and Boundary-
Scan Boundary-Scan addresses the fault spectrum by providing a variety of test options that focus on
each of the failures mentioned. For example, the mandatory EXTEST provides excellent fault coverage,
which addresses opens, shorts, missing or wrong components, and dead ICs. The optional RUNBIST
instruction checks the internal logic of a device and provides fault coverage for missing or wrong
components, dead ICs, and fixture problems. IDCODE checks for wrong devices mounted on the board.
Boundary-Scan In the Circuit (1)
Boundary-Scan In the Circuit
(2)
Boundary-Scan In the Circuit (3)
Boundary-Scan In the Circuit (3)
Moving Through the TAP Controller State
Diagram
IEEE BSDL
Boundary-Scan Description Language (BSDL) is the standard description language for boundary scan
devices complying with IEEE Standard 1149.1-1990. It is intended to be used by test developers, device
manufacturers, ASIC designers and foundries, and ATE manufacturers to promote consistency
throughout the industry. It is also intended to specify those characteristics necessarily unique to a given
boundary-scan device.
In September of 1994 IEEE Standard 1149.1b-1994 was released and with it the potential for there
being devices compliant with IEEE 1149.1 and 1149.1b existing on the same board.