© NAL, ae | QUADRAMHO | Static Distance Protection RelayThe ‘top’ or ‘reactance’ line of the quadrilateral characteristic ‘automatically tts to compensate for ‘any pre-fault power flow to avoid the Overreach or underreach problems associated with fixed resistance characteristics, Synchronous polarising, (an advanced Gigital memory system), is provided on Zones 1 and 2 to allow correct, response to forward and reverse ‘three-phase close-up faults. Level detectors To avoid maloperation when a transmission line is de-energised, phase current level detectors are Provided. These have a very fast operate and reset time and are connected so as to block comparator operation. In addition, pole-dead signals are generated by current and voltage level detectors which cause the comparators to reset. Single pole tripping Following a single-phase-to-ground fault and a single pole trip, the output ‘of the ground fault comparator is viocked by the resetting of the relevant phase current level detector and the comparator is forced to reset by the relevant pole-dead signal. Thus the comparator resets correctly even Figure ial Zones 1 and 2 parial\y-eross-polarsed ‘nha Zone 3 offset creuise mina though the presence of residual current due to load and sound-phase —— ross-polarising may appear as an | impedance within the mho characteristic. level detectors are provided. The | ee are also blocked for phase-phase or | Seamaster | Soe, | coe | a Figure 2(b): Zanes 1 and 2 partaly-erass polarised mho. Zone 3 ofeet ions.Numbers ae S1.'s (SiR = Source impedancetelay seting), 24 {ke Operation with capacitor voltage transformers Although CVT transient errors can have serious effects on other distance relays. especially at high values of system impedance ratio, the design of (QUADRAMHO’ has allowed: 4. Complete elimination of maloperation for reverse faults. 2. Reduction of transient overreach to a negigible level 3. Slowing of operating speed only to the extent necessary to prevent reverse maloperation and transient, averreach, The following design techniques have been used to meet these objectives: 4, Maintenance of a true directional reference signal, (or polarising signal), at all times by the use of an adequate proportion of square-wave cross- olarising or synchronous polarising signals, 2. The use of a phase sequence Comparator, which, though capable of fast operation, has builtin safeguards against maloperation caused by non-power system, frequency components, 3, Fitting a fast directional comparator for each phase of Zones 1 and 2 which uses current and polarising voltage as measuring quantities, both of which are independent of CVT errors. Figure 3: Resistive expansion of partly cross polused mha 4. The use of a switched filter to Precondition the voltage signal to the ‘measuring units. Operation with saturated CT's “QUADRAMHO' incorporates circuits which permit smaller and more economical line current transformers to be used in most applications, compared with other distance relays. These circuits are as follows: 4. The transphasor current input circuit, (an electromagnetic coupling device), differentiates the current input waveform to produce the IZ vector, The effect of saturation is much less on the zero-crossings of IZ then on the average current level. 2. The signal preconditioning filters ‘reduce the distortion in the IZ signals caused by saturation, 3. The comparator can tolerate some timing errors in one or more of its input signals and still respond correctly,‘Scheme logic ‘QUADRAMHO’ is equipped with integral microprocessor-based scheme logic which provides 5 ‘schemes as standard, selected by a Pair of push-button code selector ‘Switches, X and Y, on the front pane! Of the relay. The standard schemes are: 1. Basic 3-zone distance scheme incorporating: 2) Variable time delayed Zone 2 and 3 tripping. b) Switch-on-to-fault logic to provide instantaneous tripping of close-up Solid 3 phase faults occurring on’ line energisation. ©) Voltage transformer supervision logic. di Power swing blocking logic. ) Block to auto reciose logic. #) Voltage memory for the synchronous polarising, gi Control of output contacts, Fi) Logic to control various internal relay functions, This scheme is included in all the other schemes, 2, Permissive underreach scheme. The signal-aided trip is sealed in until the Zone 2 unit resets, 3.Permissive overreach scheme incorporating current reversal guard feature with variable pick-up and drop-off time settings. Also includes an ‘echo’ feature for rapid clearance of feults near the remote end of the line when the remote breaker is open, A switch is provided to select a ‘week infeed’ feature, if required, to allow fauit clearance when the infeed to the fault is too weak for the relay measuring elements to operate, 4, Blocking scheme using reverse- ooking Zone-3 elements with Variable aided-trip delay timer and current reversal guard feature with variable time setting. A guard feature for low-infeed through faults is also incorporated. An optically-coupled isolator is used as a ‘channel in service’ input which, if not energised, causes the blocking scheme to revert to the basic scheme, 5.Zone 1 extension scheme. This, does not require a signalling channel. The extension of Zone 1 is controlled by an input from the autoreciose equipment via an optically-coupied isolator, Each scheme also provides a choice Of three:pole tripping or single-and- three-pole tripping, Visual indications of faulted phase and zone, etc, are given by 9 latched light emitting diodes, (LED's), which are feset by 9 pushbutton on the front of the module, or at the next trip. | za z.i2 | R 23" — Figure 4 Zones J, 2nd 3 quadriataral sath fouls105 33 @e ff e ae ee eee gS 2 | — (0 Peon aaa 105 SF 82 wo 3 0 |aa Tao faa gi | 2F | 2 (0) Phase-pnase faults ‘Fou 5: Keel impedance rach sccuracycharsctastis lor Zone 1 Phase ground voltage Prase-phas wattage Qptical isolators and output contacts Test facilities {See Figure 10) The five optically coupled isolators are used to transfer signals from external equipment, ie, signalling channel, circuit breaker, etc, to the contacts are provided by 18 auxiliary gaa armature lays controlled by the scheme logic, (QUADRAMHO’ includes continuous switchrorea circuits of the relay. The voltage {ansformer supervision unit, (VTS), energised. In'& of test options Giguits within the relay as well as the the code asiean, Supply voltage to the relay. The VTS. These allow oll Scheme logic to be ais; indications LED's ani socket during off jn Further test options enat output to be tested. A tr Circuit breaker or channel can be {Gigy and can be read by a test option Conveniently by this method, ‘An additional 9-way test socket, Continuously monitors the voltage ‘can be set, via SW3, to block the Felay tripping if required. Periodic self-testing of all 18 relay Comparators is done automatically ‘every two weeks or on demand. In the case of a comparator failure, diagnostic information is stored in the facility to simplify fault finding. A comprehensive monitoring system 's provided to enable the features of the relay to be thoroughly tested during commissioning, routine ‘maintenance and fault finding scheme logic. The 24 output operations. The monitoring system includes a 'S-way test socket from which ower supply voltages, clock {built supervision and self testing frequency synchronous polarising, ‘o-fault and many more Greurs oF he easeTtal supplies and internal features can be crete Whilst the relay and the line are sddition, a large number may be selected by ‘or switches X and ¥. the inputs to the splayed on eight id the 25-way tests, ble each relay rip test of the test of the signalling performed Faictating can be disabled by sws fitted tothe scheme logic module, if itis not required. enables the code selector switches ‘and the pushbutton to be overridden incheevent ofa failure detected by stecancah nee permitting the use of BF. Gontinuous supervision or periodic 3 progamees Secondary injection Selftesting circuits, the ‘relay avail. feet a able’ LED is extinguished and the ‘relay inoperative alarm’ contact is closed,a 0 | 70 | 70 60. 0 euay sg news say | Skee 90 Siehare so oe || fae wae fea ae x0 | 0. fee 0 | $ Ey | | : % o Fault position 1% of Relay Setting). a Fault position 1% of Relay Setting). a. hy —maxnnum fanane || — 0 i 20 1» (| 1 ty 60 7 oo neway seus ! OPERATE 50. aoe OPERATE 50. ee oat Sie ae oO | o 3 % 3 % bo Figure 6 1 igure 7: Zonet Tyacal operaong tines fora shaped mho characteristic. eons Zone I Typical operating times fr a shaped eho charactenstie60 | | 70 | | 60. seuay 7 sn.30 { Pie She | inos ,o | i ° 50 wo | | too | Fault postion (% of Relay Setting | Faut positon % of Relay Serong) | | | | | —axnnun | sxe | ; <=hinune i “Zann | 2 \ 704 i iH : i 2 SIRT seu acuay i ' OPERATE 504 bated Sate it 0 3 = bo | | 3 = be Foul postion of Rly Setingh | Foul postion 8 of Rly Sete Faure 8 figure Zone ies ground fut operating times fora | | leet tite ground taut operating snes fora Test injection Modular features ‘Two heavy duty connectors 1Y and The relay employs a modular 12 are fitted on the right-hand side of |—_construction using plug-in modules the relay. There is an interlock so that which are individually tested one POmodules can be removed without calibrated in the factory using first removing the connectors, automatic test equipment. Modules thereby isolating supplies, inhibiting can be exchanged, if necessary, all output contacts except the Relay without any need to recalibrate the Inoperative alarm contact and short- relay. The relay case has standard circutting current transformer wiring using a multilayer printed connections, circuit board, Heavy-duty test plugs may be connected for secondary injection Purposes. The terminal blocks on the rear of the relay have additional connections to allow injection of supplies to optically- coupied isolators without the need to disconnect panel wiring. Monitoring of output contacts can also be done via these connections,AC. voltage, Vr: AC. current, ki: Frequency, fy: Operative frequency range: DC. supply, Veit: DC. supply for optically Coupled isolators, Vs 2) Burdens AC. voltage circuits: AC. current circuits: DC. supply: Setting ranges Distance measurement: Overall range, all zones forward Reverse Zone 3 Notes on reach settings: Coarse settings, all zones: Residual compensation: Fine settings (multiples of coarse settings}: TECHNICAL DATA ings 100V to 120V rms phase-phase ‘Wor 8A rms per phase SOHz or 6OHz 47 Hz to 51 Hz or 56.4 He to 61.2 He 3 versions are available: Operative Maximum Nominat range withstand 48/54V37.5V t0. 60V 64.8V Mon26v— B7.5V10137.5V 150V 220/250V178Vt0.275y 300v The supply is a switched mode de/ac/d.c. unit ‘operated from the station battery. ‘Supply options for the optically coupled isolators are the same as for V.(1), \Vs(2) need not be the same as V(t) Less than 0.1VA, 0.4 legging power factor at 63.5V phase to neutral. O.26VA (1A relay) | O.68VA (5A relay) | O.34VA (1A relay) O.75VA (6A relay) 25W under healthy live-line conditions ‘50W under tripping conditions ho version ‘quadriateral version 1A relay: 0.2 ohms to 240 ohms ) 5A relay: 0.04 ohms to 48 ohms } 1A relay: 0.05 ohms to 240 ohms! 5A relay: 0.01 ohms to 48 ohms) Switched attenuators are used for all relay (each settings. Each switch is labelied as 4 K factor for identification. K1, 2, 4, Sand 6 are attenuators of the IZ (operating! signal whereas all other K-factors are attenuators of the V (restraint) signal. The reac is calculated a5 follows: Coarse reach ZPh = Kl + K2 ohm jgPh? I Residual compensation 2N = KS*KS + K6ohm,oue approximately whore lis the nominal current rating of the current input module. Residual compensation factor ny Hos Za = 2N — 1A relay: 0.2 ohms to 4.8 ohms in 0.2 ohm steps 5A relay: 0.04 ohms to 0.96 ohms in 0.04 ohm steps. 1A relay: 0.02 ohms to 5.98 ohms in 0.02 ohm steps 5A relay: 0.004 ohms to 1.196 ohms n 0.004 ohm steps Zone 1: 1 to 9.98 in 0.02 steps Zone 2: 1 t0 9.9 in 0. steps Zone 3: 1 10.9.9 in 01 steps Zone 3 reverse: 1 to 9,9 in 0.1 steps NOTE: Zone 3 reverse only may be altered by a Multiplier with 0.25x, 0.5x and 1x settings. Art additional multiplier with tx and 5x settings ‘May be used to adjust all four fine settingsCharacteristic angle: Lenticular aspect ratio a/b: (Lenticular relay only) Resistive setting range: (Quadrilateral earth fault unit only) Power swing blocking: Time delays: Extended Zone 1: 1x to 2x normal Zone 1 in O11 steps. Zone 1 positive sequence Z1 = (KN+KI2+K13) K14xZPH Extended Zone 1 ZX = Z1xKI5 Zone 2:22 = (K21+K22) K24xZPh Zone 3: 23 = (K31+K32) K33%ZPh Zone 3: reverse 23" = (K35+K36) K33xK37xZPh (Above values are in ohms) ‘Summary of K-factors KI Oto4 step 1 K2 01008 step 0.2, K3_ 8 16, 32, 40, 48 (if fitted) k4 0105 step 1 KS 0100.9 step 01 K6 0100.08 step 0.02 Kil 1109 step 1 and infinity) KI2 0100.9 step 01 K13_ 0100.08 step 0.02 K14/24 11, 15, 5/5 KIS) 1102 step 0.1 (and infinity) K21 109 step 1 (and infinity) K22 01009 step 01 K31 109 step 1 K32 01009 step O41 K33 4.5 K35. 1t09 step} K36 0200.9 step 01 K37_ 0.25, 0.5, 10 The infinity positions of K11, K15 and K21 are used for on-load directional checks. Phase (OPh): 85° to 45° in 5° steps Residual (@N): 85° to 45° in 5° steps For Zone 3 and power swing blocking: 0.41, 0.67 and 1.0 (setting of 1.0 gives circular characteristic) The resistive reach in both the forward and reverse directions for Zones 1, 2 and 3 is set by ‘switch K3 K3 Resistive reach R, = |, ohms Power swing blocking zone (Zone 6) has mhoi lenticular characteristic. Aspect ratio of lens is same as that of Zone 3. Power swing blocking may be enabledidisabled by switch SWS. Settings: Zone 6 forward = Zone 3 forward + 0.3 x Zone 3 forward Zone 6 reverse = Zone 3 reverse + 0.3 x Zone 3 forward Timer = 50ms Blocking: Individual blocking of Zone 1 andlor Zone 2 and/or Zone 3 andior indication/alarm as selected by ‘switches on the scheme logic ‘module. Blocking is remioved if a (ground fault occurs during a power swing. Zone 2 {tea}: Oto 2.56 in 10ms steps Zone 3 (tea): Oto 5.1s in 40ms steps and infinity ‘Scheme timer (te): 0 to 90ms in 6ms steps Scheme timer (tol: 0 to 90ms in 6ms stepsOperating times Mo characteristic: Quadrilateral characteristic Reset time: Polarising Phase-earth faults: \ Phase-phase-earth faults: Phase-phase faults: Three-phase fauits: Current sensitivity ~ impedance measuring units Returning ratio— impedance measuring units Accuracy Impedance measurement Timer settings are by a series of switches arranged in a binary series. The time delay associated with each switch is effective only when the switch is set to the right-hand position. Zone 1 operating time characteristics are shown in Figures 6, 7, 8 and 9. These are summarised below. Times quoted include the ‘operating time of the electromechanical tripping output relays, Minimum: 50 Hz: 14ms 60 Hz: 13ms Typical 50 Hz: 18-25ms 60 Hz: 16-23ms Minimum: 50 Hz: 19ms 60H: 7ms Typical: 50 Hz: 25-33ms 60 He: 22-23ms Maximum: 36ms (NOTE: The main trip contacts, Tip A, Tip 8, ‘Tip C, Trip 3ph and Any Trip, are sealed in for a minimum of 6Oms following the initial trip} Proportion and type of cross-poiarising for Zones 1 and 2 partially cross-polarised mho and Zones 1 and 2 directional lines: 16% square wave from healthy phases. 16% square wave from synchronous polarising system, (NOTE: Synchronous polarising start-up time is 440ms from energisation of line and it remains effective for 8 cycles after fault incidence.) Determined by low-set current level detectors. The sensitivity varies inversely with coarse reach setting ZPh and is nominally 5% In at 2Ph = 4.8/lhohms. Returning ratio is the impedance value at which the relay just returns to a reset condition divided by the impedance value at which ‘comparator just operates. Returning ratio measured on the characteristic angle of the relay is less than 110%. ‘The accurcey is unaffected by the ZPh and ZN settings, the characteristic angle setting or the de. supply within the operative range) ‘The following accuracy claims apply under reference conditions: Fine reach multiplier set to unity, ambient temperature 20°C, nominal input frequency fo Zone 1 accuracy +5% upto SIR = 3 Zone | accuracy +10% SIR = 3010 SIR = 60 Zone 2 accuracy +10% up to SIR = 60 Zone 3 accuracy +10% up to SIR = 60 SIR is the system impedance ratio defined as the total source impedance divided by the relay setting |ZPh + ZN for ground faults or 22Ph for phase faults), At reference settings and at a Nominal source voltage of T1OV phase-phase, SIR = 30 corresponds to 2.08V'0.213In for ground fault measurement and 3.55V/0.3701, for phase fault measurement and SIR = 60 corresponds to .04V/0.108!, for ground fault ‘measurement and 1.80V/0.188I, for phase fault measurement.Characteristic angle: Effect of dc. supply variations: Overload ratings AC. voltage: AG. current Output contact ratings Environmental withstand Environmental classification: Temperature! Humidity: Salt mist: Enclosure protection: Vibration: Mechanical durability: Voltage withstan Insulation: ‘The effective accuracy range at any setting is applicable up to 1.2 times rated voltage and 56 times rated current. ‘Teansient overreach is less than 1%. The additional error, caused by a departure from reference conditions within the operative anges, is not more than the error allowed at reference conditions. ‘The accuracy of phase setting is +29 independent of relay reach setting. The impedance reach accuracy does not vary with characteristic angle setting The effect on relay accuracy of a variation within the operative dc. supply voltage range is, negiigibie Withstands: 1.5 Vp continuously 2.5 Va for 10s Withstands: 2.4 t, continuously 400A for 1s (1A version! 400A for Is (5A version) Make and carry: 7500 VA for 0.2s with maxima of 30A and 300V, ac. or de. Carry continuously: 5A ac. or de. Break: ac: 1250 VA ac. dc: SOW resistive 25W LUR=0.04s With maxima of SA, 300V, For storage only: 25:070/56 lec 68 8S 2011 Operative range -25°C to +85°C Storage and transport ~25°C to +70°C Long term damp heat: 56 day severity in accordance with: IEC 88.2.3 BS 2011 Part 2.1Ca BS 2011 Part 2.1Kb PSO (dust protected) in accordance with lec 529 S540 The relay complies with BS 142 1982 suction 2.2 Category $2 0.59 between 10 and 300Hz The relay will perform more than 10¢ operations The relay complies with: IEC 255-5, BS 142 1982 section 1.3 2kV rms for 1 minute between all case terminals connected together and the case 2kV rms for 1 minute between independent Circuits of the scheme, including contact circuits 1kV rms for 1 minute across the contacts of the normally open outgoing contact pairsHigh voltage impulse The relay complies with: withstand IEC 255~5, BS 142 1982 Section 1.3 5KV peak, 1.2/50us, 0.5 joules High frequency ‘The relay complies with disturbance test. IEC 255-6 Class Ill, BS 142 1982 Section 1.4. 2.5KV peak between independent circuits and between circuits and case earth LOKY peak across input circuits MHz bursts decaying to 50% of peak value after 310 6 cycles Repetition rate 400 per second Nationaliinternational The relay complies with relevant clauses in the specifications following specifications: BS 142, IEC 265 Voltage transformer (fuse The voltage transformer supervision (VTS) failure) supervision operates when zero sequence voltage is detected without the presence of zero sequence current, detected by the ‘low-set’ neutral level detector. The VTS does not limit the distance relay current sensitivity or operating times for line faults, even when the VTS iis set to block relay tripping, Nominal V> detector setting 9.5 [15% of 63.8Vi Blocking action of VTS on distance ‘comparators can be removed by switch SW3, An optically coupled isolator can be provided 10 monitor an auxiliary contact of a miniature circuit breaker (MCB) if this is being used instead of fuses, Monitoring and self-test There is inbuilt continuous monitoring of power Supplies, clock pulses, scheme logic and ac. voltage supplies and a selectable periodic self- test of all 18 measuring elements (selected via ‘SW5) every 2 weeks. Time taken to do self-test = 0.085s Switch-on-to-fautt system The switch-on-to-fault system is enabled either 200ms of 110s (as selected by switch SW2, after all poles of the line have been de- ‘energised and remains active for 240ms after the line has been energised. ‘Switch-on-to-fauit tripping is by any 2122/23, comparators or voltage and current level detectors (as selected by a switch SW1 on the front of the relay) Voltage level detector setting 44.5V phase- earth (70% of 63.5VI. Current fevel detector setting 0.051, x_4.8 A, IKT+K2) Condition for fault detection: current level detector operated and voltage level detector not operated, on corresponding phase, for 20ms. CASES ‘The relays are housed in internationally accepted 483mm cases for rack or panel ‘mounting finished in yellow and black with module frant plates finished in black. Weight - 23kg. Overall size—rack mounted case, height 266mm, width 483mm, depth 315mm. panel mounted case, height 291mm, width 444mm, depth 315mm.INFORMATION REQUIRED WITH ORDER Nominal current rating, ly: 1A or SA. Frequency, f,: SOH2 or 6OH2, Voltage of dc. supply, Vs: 48/54V, NOM25y, or 220/250V. Voltage of auxiliary de. supply Vx(2): 48/54V, MONZBV, or 220/250V. Characteristic: shaped mho or quadrilateral, (see ‘QUAORAMHO’ models available) ‘Mounting arrangements: rack or flush panel Advice on applications is available when the information requested above is dificult to specify. Requests for advice should include the following details; Voltage transformer ratio. Current transformer ratio. Positive and zero sequence impedances of the protected feeder or full details of feeder lengths and construction. ‘Source impedances or fault levels for both minimum and maximum plant conditions IN a, NoTES 1. Heavy duty connectors 2) KZ Closes when heavy duty connector is removed. 5) LP Opens when heavy duty connector is removed. ©) <2 Opens after operation of a) and bl when heavy duty connector is removed, 2. Breaker open opto must be connected if busbar VT's are sed or if the weak infeed or echo feature of the sermissive veereach scheme are required, CB auxiliary contacts must be Connected in series to indicate ‘al poles open’ Figure 10: xcema connection diagram: Quecramno state distance arotecton relay Fane Jonase pong 3. Un ety soma conan tis att it all open 4. Renovo hem ty ceed dane a aun ey ube ala ane cerns seme ot | 5 Comactors own ee pc oy | 5. When sta Ts nt a age pase ong sae fenprang boe ied OS eon ee rg 7 Winn ghane oping sche und Vo A Yo 8c area TYTERMINAL BLOCK DETAIL : | 28 way max. EACH WAY ACCEPTING:— | 315, 2-MsRING TEMANALS 2 lex08 SNAP ON TERMINALS 1-RING, 1~SNAP ON TERMINAL | | i ‘TOP VIEW | : | CF 5 | ta||rallta. i | aieye i - | "|S | eomensuerer 3 | | REO} | fee a | | lo | le 1 | 1 Si fee M5 EARTH FRONT VIEW REAR VIEW ‘STUD i SESCRETON MOSER | 7 [PHASE AND NEUTRAL fanz? | STizowe TaN En | Seon [pave] Alidimensions in mm | Te soeeve Tears | TOCRGE NE [eT Tawaaar nea ur poiey s one of continuous product cevelonment and the nght is reserved so sunply squlomant which may vary slightly fem shat desorbed GEC Measurements the General Electric Company p.lic., of England St. Leonards Works Stafford ST17 4LX England Telephone: 0785 223251 Fax: 0785 212232 Telex: 36240 Cables: Measurements Stafford Publication R-5580F (088830 CPS Printed in EngianaMAY 1985 DISK No: RE1O40 R5888P DESCRIPTION OF MODULAR DISTANCE PROTECTION SCHEME WITH MICROPROCESSOR BASED SCHEME LocIC TYPE SHPM 101 {QUADRAMHO)DESCRIPTION AND TECHNICAL DATA 1a 1.2 3.1 3.2 3.3 3.5 3.6 3.7 3.7.1 3.7.2 3.7.3 3.7.4 INTRODUCTION MAIN FEATURES QUADRAMHO MODELS AVAILABLE MECHANICAL LAYOUT MODULE DESCRIPTION RELAY BLOCK DIAGRAM VOLTAGE INPUT MODULE RFVOS CURRENT INPUT MODULE RFC15 THE PHASE AND NEUTRAL MODULE RRZO7 ZONE 1/20NE 2 MODULE RRMOB ZONE 3 MODULE RRMOQ SCHEME LOGIC MODULE RCL10 General Scheme Logic Funct tons Scheme Logic Settings and Indications General Description of Microcontroller Associated Hardware Microcontroller and Program Memory Programmable Peripheral Interface Multiplexed Port Hardware Reset of Microcontroller and Peripherals +5 V Rat] Monitor Monitoring of Scheme Logic Software Inoperative Alarm Zone 1 Interrupt Gating Logic Synchronous Polarising (Memory) Hardware Indications... eS a Opto Isolators Zero Sequence Voltage Level Detector R-5888 PA CHAPTER 2 CONTENTS 12z 15 2 30 38 38 38 39 41 al 43 43 44 44 44 45 45 45 47 ACC PUB3.7.17 3.7.18 3.7.19 3.7.20 3.8 39 4d 4.11 4.1.2 4.1.3 4.1.4 4.2 4.2.1 4.2.2 4.2.3 4.2.4 4.2.5 4.2.6 4.2.7 43 4.361 4.3.2 4.3.3 4.3.4 44 45 High Set Current Level Detectors Power Swing Blocking Hardware Scheme Logic Hoftware Scheme Logic Test Program THE AUXILIARY RELAY MODULE RYCS3 POWER SUPPLY UNIT ZREOL PRINCIPLES OF OPERATION THE COMPARATOR Fundamentals of the Comparator Action of Comparator Counter Exclusive of Notse Phase Shifting Circuit POLARISING ARRANGEMENTS Partially Cross-polarised Mho Synchronous Polarising Offset Mho Characteristic The Lenticular Characteristic The Quadrilateral Characteristic Two-Phase-to~Ground Faults (Quadrilateral Characteristic) The Offset Quadrilateral LEVEL DETECTORS Inhibition of the Comparators Single Pole Tripping Phase Selection Other Level Detectors POWER SWING BLOCKING CURRENT INPUT CIRCUITS OPERATION WITH SATURATED CTs VOLTAGE TRANSFORMER SUPERVISION (FUSE FAILURE) Principle R-588B PA CHAPTER 2 CONTENTS. 47 49 49 59 67 69 72 72 72 14 76 79 80 80 90 92 92 95 97 64 201 iol 103 103 104 106 109 ua 112 112 ACC : PUB4.7.2 4.7.3 4.7.4 4.7.5 4.7.6 427 47.8 4.7.9 4.7.10 4.7.11 4.7.12 4.7.13 4.8 4.8.1 4.8.2 4.8.3 4.8.4 4.8.5 4.8.6 4.8.7 4.8.8 4.8.9 4.8.10 4.8.11 4.8.12 4.8.13 4.8.14 4.8.16 4.8.17 FEB 68 Scheme Logic Montrol | Outputs Level Detector Settings Speed of Operation Implementation Output Seal-in Operation for Indication and Alarm only Resetting Line De-energisation Bus Bar Voltage Transformers Single Pole Tripping Switch On To Fault Weak Infeed (POR Scheme Option) During Fuse Fat] Conditions SCHEME LOGIC MODULE . Level Detector Pole Dead Logic Comparator Level Detector Checks Voltage Bandpass Filter Switching Control of Hysteresis in Impedance Measurement Self Testing Operation of Standard Schemes and Input/Output Interfaces Standard Scheme Options Basic Schemes Permissive Underreaching Scheme (PUR) Permissive Overreaching Scheme (POR) Weak Infeed Feature (POR Scheme Only) Blocking Scheme with Reverse Looking Zone 3 Elements Zone 1 Extension Scheme (Z1 EXT) Opto-isolator Inputs to Scheme Logic Module f Auxiliary Relay Outputs _ Trip A» Trip By and Trip C Contacts Trip Three Phase Contacts R-5888 PA CHAPTER 2 CONTENTS 112 113 113 13 113 114 lla lla 115 1s 1s 1s 47 uly 117 ay 47 12. 122 122 123 123 126 12 130 132 133 135 135 135 ACC4.8.18 4.8.18 4.8.19 4.8.20 4.8.21 4.8.22 4.8 23 4.8.24 4.8.25 4.8.25 4.8.27 49 4.10 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.10 5.1L 5.12 5.13 5.14 5.15, 5.16 FEB 88 Any Trip Contacts Block Auto Reclose Contact Fault Locator Start Contacts Zone 2 Trip Contact Zone 2 Trip Contact Zone 3 Trip Contact Aided Trip Contact Switch On To Fault Contact Relay Inoperative Alarm Scheme Logic Control of Indications Test Facilities OPERATION OF QUADRAMHO WITH CAPACITOR VOLTAGE TRANSFORMER LOGIC SYMBOLS USED . TECHNICAL DATA INPUT RATINGS IMPEDANCE SETTING RANGES RESISTIVE REACH SETTING (QUAD) LENTICULAR ASPECT RATIO SETTING SUMMARY OF K FACTORS ACCURACY OF IMPEDANCE MEASUREMENT CURRENT SENSITIVITY OF IMPEDANCE MEASURING UNITS RETURNING RATIO OF IMPEDANCE MEASURING UNITS CHARACTERISTIC ANGLE SETTING RANGES AND ACCURACY TIMER SETTING CONTROL POLARTSING : SWITCH ON TO FAULT OPERATING AND RESET TIMES VOLTAGE. TRANSFORMER (FUSE FAIL) SUPERVISION POWER SWING BLOCKING OPERATIVE AMBIENT TEMPERATURE RANGE R-5888 PA CHAPTER 2 CONTENTS 135 137 137 140 140 140 14o aan 143 145 147 150 1si 152 152 152 153 153 153 154 155 155 155 155 156 156 156 156 17 157 ACC: PusFEB 88 OPERATIVE FREQUENCY RANGE BURDENS AND CURRENT TRANSFORMER REQUIREMENTS OUTPUT CONTACT RATINGS OC SUPPLY RATINGS AND OPERATIVE RANGES AUXILIARY DC SUPPLY FOR OPTICALLY-COUPLED ISOLATORS DC POWER CONSUMPTION INBUILT CONTINUOUS MONITORING AND PERIODIC SELF TEST ENVIRONMENTAL WITHSTAND DIMENSIONS R-5888 PA CHAPTER 2 CONTENTS 157 157 159 159 160 160 160 160 161 ACC : PUBla 1.2 MAIN FEATURES * Full scheme 3-Zone distance relay with 18 measuring elenents. “ Characterietic shapes to suic all line lengths and fault Leveis. * Fast operating times over a very wide range of fault conditions. * Digital synchronous polarising for close-up 3-phase faults. * Microprocessor schene logic with wide range of built-in schenes selected by code selection switches. * ample input/output facilities - 24 output contacts, 5 opticaliy-coupled inputs, 10 light-enitting diodes. “Full range of test features for easy commissioning, routine testing and problem analysis. Built-in interfacing enabling automatic field test equipment to be used if required. * Continuous self-monitoring, on-demand and periodic self-test {f required. * Bulltein Voltage Transformer Supervision and Power Swing Blocking feature as gtandard. QUADRAMHO MODELS AVAILABLE Two types of characteristic are availabl (4) Zone 1 and 2: shaped partially cross-polarised sho with partially cross-polarised directional line Zone 3 i offset lens (can be set as offset circular aho) (44) Zone 1 and 2 ground faule: Quadrilateral with partially cross-pola: directional line Zone 1 and 2 phase fault: shaped partially cross-polarised aho with partially cross polarised directional line Zone 3 ground faults: offset quadrilateral Zone 3 phase faults: offset circular aho Each type includes Voltage Transformer Supervision and Power Sving Blocking feature as standard and is suitable for both three-pole aad single-and-three-pole tripping of the circuit breaker.MECHANICAL LavouT 2) Separation of interfac aodules. The interfac. She outside vorld and the measuring and control sedaice which tnee near left hand side of the subrack (see fig 1). The paterface modules provide galvanic isolation to 2 ky peak and E{1ber out high-frequency comnon-node and transverse-seak noise Stgnals. The measuring and control modules therefore operate in a elstively quiet electrical environment. The need for Sea te eeneson on circles iutchelailer spacey cic | ng so the relay internal d.c. supply centre fall is connscned to phe case, Tha case earth stud 1s ia turn connected te the relay room earth, 5) Within the interface aodules, isolating traneforuers have screens seeennantSe Primary-to-secondary capacitance coupling, thereby. Sifggueting conmon-node interference. The efficiency of any screen is defined gore by the electrical strength of the sores reer? The common rail or earth than by the design of the siacee iegelf, so the larger transformers are mounted on metal plates and che transfomer screens are connected directly co che pares by short thick wires. A special 4 mm heavy-duty plug and Socket atrangenent allovs each plate to be connected to chevescch efod of the case by aultistrand wire of thick cross-section (50/0.2 am wire). This ensures a low inductance between che perigee and earth. A low induetance is more importent than low resistance because of the high rates of rise of currents that exist in sereen connections under interference condition ©) Three different categories of currents flow to earth. These are signal currents, pover supply currents and screen surge curcents Jo eliminate cross-coupling effects, these are conducted by separate wires to the case earth stud. For convenience, the signal and power supply earths are connected to a common ground Plane on the four layer pcb backplane which 1s employed te provide interconnection of module signals. The ground plane also affords good screening of the intermodule connections The Ground plane 1s connected to the relay case at each mounting point and 1s also connected to the case earth stud by a short thick wire. Fig 2 shows the basic schematic of the relay earthing and Screening arrangements and paths of current flow for some typical common mode surges.“QUIET” AREA | INTERFACE AREA QUADRAMHO Fig1Signal and power commons to modules F Ground plane on relay ‘multilayer PCB backplane CURRENT \ INPUT MODULE | \ —— == Ue | | ( VOLTAGE INPUT MODULE / | es J POWER SUPPLY i { in I i AELAY case Gaze earn sua | Relay room earth | ¥ } fy to AC voltage terminals Source A: Common mode surge trom AC currel Source B: Common mode surge from DC supply to case te! Fig 2 QUADRAMHO MODULE EARTHING ARRANGEMENT.Bal MODULE DESCRIPTIONS Fo Provide the user with a thorough understanding of the operating principle of the relay and the function of the individual uodules Lencetonne relays the following subsections describe the operating functions of each module. where necessary, references to more detailed descriptions in section 4 are given. RELAY BLOCK DIAGRAM Fig 3 shows the relative positions of the modules within the relay case and fig 4 shows the overall relay block diagram. TERMINAL BLOCK DETAIL L— 282 28 way Max. EACH Way ACCEPTING — 2 Ma RING TERMINALS on 27418 +0.8 SNAP ON TERMINALS on RING. 1=SNAP ON TERMINAL TOP view aor 7] at l lal 1 raljraljze | allele ' Power suey | ~ EEE ss it Na MS EARTH FRONT VIEW REAR VIEW ‘STUD REF TDescReTION TMOOULE REF 7 Tacase ano METAR aRDOT ONE TENG ARO spon > aoe All dimensions in mm [scree OSE ato STwouace WUT mevOr S_[AURIIARY RELAY aves STCuRRENT PUT mec Outine erawing and mode layout FIGURE 3“243 LN3WdIND3 ONTITYNOIS [OHWWHavnd| wouboig 401g |3.2 -8- THE VOLTAGE INPUT MODULE RFV 04 The voltage input module isolates and filters the AC inputs from fhe transmission line voltage transformers. Reference to fig $ Teveals that the sodule has three phase-neutral connected isolating transformers insulated to 5 kV peak. These have intervinding Scteens to attenuate common-mode high-frequency interference’ The output from each transformer is passed through an overvoltage surge Protection circuit which linits overvoltages due to Lightning strikes, cross country faults and other high voltage transiects to within limits which are safe for the electronic circuitry contained within the relay. The signals are then filtered by lov-pase filters with cut-off frequencies of 300 Hz. The purpose of the filters is to remove unvanted high-frequency signals such as line reflections following the incidence of a fault and also interference induced on substation wiring by switching operations. Each output is then passed to a calibrated atteauator and a band pass filter. The filters are of second order with centre frequencies equal to the nominal supply frequency and Q values of 0.5. This type of filter is very effective in eliminating unvanted exponential and high frequency components of the {aput voltage. Under normal conditions the distance measuring elements use the voltage signel produced by the attenuator. However, the measuring elements are automaticably switched to the filtered output of the band-pass circuits after a predetermined interval of tine from the incidence of a fault. This ensures that, 1f the comparator operating time has been slowed by abnormally severe exponential or high frequency components of the voltage signal, the comparators have the opportunity of reneasuring on a relatively uncontaminated voltage signal. This arrangement prevents any possibility of excessively long comparator operating times which aight otherwise occur under certain extreme conditions, such as (a) severe CVT transient errors with high SIR and high fault position, (b) severe travelling wave distortion on a long line at high fault position (c) large mismatch between source and line time constants with high SIR and high fault position. An example is shown in fig 6. The voltage level detectors are used as fault detectors for the Purpose of controlling the transfer from normal to band pass filtered voltage signal. Solid state switches are used under the control of input "ENF" for the signal transfer circuits. The reset time of the voltage level detectors is approximately 12 to 22 ms depending on point-on-wave of fault incidence and a further delay of 14 ma is introduced by a software timer. Resetting of any voltage level detector causes all three phases of voltage signal to be transferred to the band-pass filter outputs. The time delay of 26 to 36 ms between fault inception and signal transfer 1s sufficient to allow fast tripping to occur, if electrical conditions permit, before the intervention of the filters. If fast tripping does not occur, the 26 to 36 ms delay 1s long enough for the transient errors of the band pass filters caused by the collapsing voltage to have decayed away before signal transfer to the band-pass outputs.-9- At the instant of svitching in the band pass filters, a step in the voltage vaveform say arise and co ensure that this causes no confusion to the comparators a momentary inhibit pulse is sent to all the comparators. The voltage supply is switched back to normal when (a) the fault is removed by a remote breaker so that the voltage is restored to normal and the voltage level detectors pick up again (b) when the fault is cleared by de-energising the line Such that one or more pole-dead level detectors operate. This control logic is performed by software in the scheme logic module (see section 4.8.3 and fig 66). When the relay trips the circuit breaker, a logical signal is sent from the scheme logic module to the input labelled “TRIP” to instruct the relay reach to be increased by 5% by reducing the gain of the voltage buffer amplifiers, which produce outputs V4, Vp and Vo by 5%. This hysteresis control defines the reset ratio of the relay and prevents chatter of relay output contacts for faults on the boundary of operation (see section 4.8.4). The outputs Va, Vp and Vo are buffered by operational amplifiers which produce outputs V4" and Vg' and Vc! respectively. The C phase output from the bandpass filter is buffered to drive he memory facility of the relay, see section 3.7.13, on output "nen* The overall transfer functions for the voltage input module with healthy line conditions at the nominal pover system frequencies are:~ Your = 0.066304 /- 10° (50 Hz models) Van Your = 0.065854 Vin 12° (60 Hz models)= 10 = wW -1W NW +i SAN ANT WON 4 HEAVY CURRENT JUADRAMHO EARTH Fig 5 VOLTAGE INPUT MODULE RFVO4Waveforms represent fault in Zone 1 close to boundary of operation with large exponential component in voltage No zero crossings comparator cannot operate V-1Z (with switched filter) Zero crossings restored comparator can operate 26-36 mS delay before switching to filtered supply | Inhibit pulse Fig 6 ACTION OF SWITCHED BANDPASS FILTER IN VOLTAGE SUPPLY3.3 -Re- THE CURRENT INPUT MODULE RFC 15 This module receives current from the line current transformers on iaputs Iq, Ig, Ic and Ty via the heavy duty plug bridge piece 1Y on fhe side of the sodule and produces the replica impedance signals Fol and 12, Ipl and 132, Icl and 1¢2, Iyl and Iy2 and Iy3 (see block diagram fig 7). Replica impedance signals are generated by the mixing of nagnetic fluxes in the transphasor units, as described in detail in section ‘:4- Each transphasor arrangement produces an output voltage of 0.34 V/A (1A relay) across a 5K ohm load located in the phase and Reutral module. The residual compensation arrangenent produces an extra output on Iyl - Iy2 of 0.068 V/A (1A relay) across a 1K ohn toad, also located tn the phase and ncutral module. Each output is calibrated at the factory by use of the trimpot T. The replica phase angles are set by avitches “/@ Ph” and “/@ x" on the relay facia (see fig 8) which have a setting range of 25°*to 85° in 5° steps. These switches control the variable resistors shown in fig 7. The angle setting for currents I4, Ip and Ic are ganged. The quadrilateral version of Quadramho requires additional signals of IR, , IRg and IRc . These are derived from three current transformers placed in weries with the three phase transphasors, as shown in figure 7. They have a transfer ratio of 0.544 V/A (1A relay). All transphasor and current transformer primaries are electrically isolated, to a level of 5 kV peak from their corresponding secondaries and the relay case. In addition each device is fitted with a screen which helps to couple any common mode electrical noise, present on the relay current input terminals, to ground. This noise is further reduced for outputs 14, Ig and Io by the capacitors labelled C, which couple the noise to ground on I4, Tg and Ic COMMON. These capacitors and those shown in the neutral circuit, also attenuate high frequency transverse noise present on the transphasor secondaries. Zener diodes, labelled D on the diagram, limit the circuit voltages at the module outputs and across the angle setting potentiometers (/8) to non damaging levels when heavy surges of current are present on the transmission line.= $= zon ~ 12 TRaw TRe COMMON far — CIRCUIT SAME ao T AS . ABOVE fm Be? }——amn TR, 2 ot J—m TRaCOMMON 8 oy }—em Te! CIRCUIT SAME [+m Ic COMMON, j Ic AS ABOVE ae TRe~ TRe COMMON 5 o4 visk2 HEAVY CURRENT an L TERMINALS FIG. 7 A.C. CURRENT INPUT MODULE RFCIS-lbe 4550 so Ph | as C 80.75 70 | 4550 60 AN 65 30 75 70 (AME Fig 8 Nameplate details RFC15364 -15- THE PHASE AND NEUTRAL MODULE RRZO7 INTRODUCTION This {s a two board module which contains the level detectors and the coarse reach settings. The two versions available are a quadrilateral and a lenticular, both in 50 and 60 Rz- The two nameplates are shown in fig 11 and the switch functions in table 1. LEVEL DETECTOR BOARD 2HO729 The left hand board contains seven level detectors and three clock divider circuits as shown in fig 9. A detailed description of the level detector function and operation is given in section 4.3. The main clock MCK is generated in the Zone 1/2 module (see section 3.5) and divider circuits on this board produce MCK/7, MCK/14 and MCK/28. These signals are used by the level detectors on this board and also those in the Zone 3 module. As part of the continuous monitoring the MCK/28 signal is monitored and an alarm via LDALARM is given {f it should fail. The seven identical level detector elements are designed to pick up for an input voltage of*2.933 V rms. This level is set by the magnitude of the positive voltage reference which is calibrated by GECM and the length of the pick up time t;. As part of the continuous monitoring the negative reference 1s monitored and an alarm given if it is not within the required tolerance. Three level detectors are used as overvoltage detectors LDOVA, LDOVB and LDOVC with a setting of 70% V,. The pick up timer t, 1s 0.275 cycle and the drop off tine tz ts 1.1 cycles Three level detectors are used as low set phase current detectors with a setting of 5% of I, at KL+K2 = 4.8, This setting is obtained by amplifying the input signals LDIA, LDIB and LDIC by gain Gj. Timers ty and tz are both 0.275 cycle. The seventh level detector is the high set neutral LDHSN. The neutral current is produced by summing and amplifying by C3 the three phase currents. This gives a setting of 16% I, at Ki + K2 = 4.8. Timer t) 1s 0-155 cycle and time to (1.1 cycles). The reference for the high set neutral and the low set neutral (see Zone 3 module) is modified by the phase-phase currents to give a variable pick up level, as described in section 4.3.3. The reference is the largest instantaneous value of the three precision rectified phase-phase currents. The signal, smoothed by the R and C and limited by zener diode D ts buffered and split into two signals for the high set and low set level detectors. In each case the negative reference is obtained by inverting the positive. To prevent chatter each level detector has 10% hysteresis. This is achieved by reducing the reference on individual level detectors when they operate. The hysteresis for the low set neutral is also on this board controlled by the level detector in the Zone 3 module.-16- PHASE AND NEUTRAL AND IR SETTING BOARD ZHO730 The right hand board sets the basic reach of the relay in conjunction with the zone multiplier modules. In addition, for the quadrilateral relay, it sets the relay resistive reach. See fig 10. The signals present on inputs I,l, 1,2, Ipl, Ip2, Icl and Ic2 are attenuated by the resistor networks controlled by switches Kl and K2 on the relay facta, to produce the relay phase setting Zpy (ganged for all phases). Similarly the signals on Iyl, Iy2 and Iy3 are attenuated under the control of K4, K5 and K6 to produce the neutral compensation factor setting, Zy. A summary of the function and resolution of each of the switches above is given in table 1. Each of the attenuated signals are passed through a low pass filter and a band pass filter. The first order low pase filter has a cut-off frequency of 300 Hz and the bandpass filter has a centre frequency equal to the power system frequency and a Q factor of 0.5. The resulting signals, -I, ZpyU, -Ip Zpy, Ic Zpy and + ly ZyV are output from the peb directly and also further processed by the squaring operational amplifiers which mixes the + Iy ZyUwith each of the other ZpyUsignals to produce square waves labelled -I, Zpyft, ~Ip Zpystand -Ic¢ Zpys. Sinusoidal signals LDI,, LDIg and LDIg which are used by the level detectors are extracted after the low pass filters and before the band pass filters. For the quadrilateral relay only, signals V4", Vg! and Vo! are attenuated by the resistor networks controlled by K3 to produce the relay resistive reach (see table 1). These signals are mixed vith the signals IR, IRg~V and IRc~\V which have been filtered as above to produce the (V + IR), (V IR) and IRSLvoltage vectors for each phase. The neutral IR sinusoid is produced by summing the three phase IR sinusoids. When the relay carries out a self checking procedure it ts necessary for the IR/t, IRg/t, IRc sland IRysLetgnals to be replaced by the Ya CP, Vg CP, Vc CP and V, CP signals respectively. This is achieved using digital switches controlled by the scheme logic.The respective output volrages ari 50 He -la2pa = KL+K2 x (1g1 ~ 142) x0.9848 /= 10° +1y2y = (KS + K6) x (Iyl = 1y2) + Ke x 3 (Iy3 ~ IN coMMON)) X0.9848 /- 10! rr,’ = (IRq - IRq COMMON) X0.9781 /- 13° 60 He -1y2pn 7 BLE HD x Cyl ~ 12) 0.9781 foe = ((KS +6) y (Iyl = Iy2) + kA Xx 5 (Zy3 ~ IN comMon)) x0.9781 /- 12° IRy " GR, = IR, common) x0.9636 J= 15.5" NOTE: Phases B and C output voltages are derived similarly Relay facta Funct ion Range switch reference covered by switch kL Coarse Zpq 0 to 4 in steps of 1 K2 Fine Zpy 0 to 0.8 in steps of 0.2 K3 Rg 8, 16, 32, 40 and 48 Ka Coarse Zy © to 4 in steps of 1 ks Fine 2y 0 to 0.9 in steps of 0.1 x6 Very fine Zy 0 to 0.08 in steps of .02 Table 1 Phase and Neutral module switch functionsia NCKI7 sMcK MoKsIe MCKI 5 NEGATE VONAGE — REFERENCE si¢ ee -vRer Cowman REE roto > Ta COMMON Loss EDR reer aan Va COMMON Love “ULB Te COMMON Poe Ve Ve COMMON Loove “LLoie Te COMMON ee ans Ve COMMON ae wrsTeRESs LoLsN FOR -LSNREF LOLSN +1SNREF FIG. 9 LEVEL DETECTORS 7HO729 —s -12v ——= ov —e -12V MOK IG LOHSN-19- K2(a)-FINE SETTING a) == to, St} y= -Ia2py © t i : tet 4 COMMON — Kia) COARSE SETTING —= LDIg K2(b)=FINE_ SETTING ————= -Iszen © Ig! 783 = -IpZpu Te COMMON = COaRSE SETTING LOIe K2fe)= FINE SETTING aa | Icley Ich = Ic2 bas -1ed | >—— TeZpq Xile]- COARSE SETTING Ke- VERY EME SETTING ry &Y wes In2y COARSE SETTING ——= s12v —= ow —= +12 In3 ——= SiG COMMON I, MON ete CIRCUIT BELOW APPLIES TO QUADRILATERAL RELAY ONLY Ww 2 Gusta RESISTIVE RESCH cng (VsIR)y Va COHN, AND | ae -TR)g ia eae Ry -y uence pt et aaa os = TRA | een nr ih & PHASE A [> Le! TR,coMMON te) a vw f>4 K3(b)~ MIXING =(V-22 le Ve COMMON Reve | AND \V-IR)g VpCP = SQUARING Ree Re ——_ Piast 8 IRe a. rt K3(c)- MIXING a(V+IR)c COMMON I AND a : VeCP = REACH T SQUARING iia F _ ial ohn oe ei ; ‘TRe COMMON Sleteaen FIG. 10 BOARD _ZHO730_ PHASE _AND NEUTRAL AND 1R SE-20- a OKI 4 oz _ fF o8 K2 ~ oa ZPhicne KE KZ Zo-ly aN h ZPhIO)= ne Zu-ty | My TP cy ngion- on O02 O ‘s Ks (os Fig 11 Nameplate details RRZO73.5 ae 2ONE/ZONE 2 MODULE RRMO8 INTRODUCTION This is a two board module which contains the reach settings, the polarising circuits and the comparators for Zone 1 (21), 2eme 1 extension (Z1X) and Zone 2 (22). The phase fault elements have shaped sho characteristics. The ground fault elements can be either shaped who or quadrilateral. This godule is power system frequency dependant and is available in either 50 or 60Hz versions. The nameplates are shom in fig 17. SETTING BOARD (2HO732) The right hand board contains the fine reach settings for Zl, 71X and 22. The settings are obtained by attenuating each of the phase-neutral voltages with switches and resistor networks. A block diagram is shown in fig 12. The switches for each of the three phases are ganged together. The switches labelled K11, K12, K13 and K14 set the Zl reach. K2i, K22 and K24 set the 22 reach. The Z1X reach, which is a multiple of Zl, is controlled by K15. An analogue switch, controlled by the scheme logic, is used to select the voltage from Zl or Z1X as appropriate. The attemated voltages are mixed with the appropriate 12 signals (from the phase and neutral module). The resultant IZ signals are squared up and level shifted to generate the (V-IZ) signals. These form one input to the comparator. Three additional squaring auplifiers are required to generate three phase-phase IZ square waves. These are used in the directional line for the phase-phase elements. The guard zone for the quadrilateral version (described in section 4.2.6) requires a forward setting which is twice that of the 21 ground fault setting. This 1s obtained by attenuating the Z1 voltages, after the Z1/Zix selector, by a factor of two, mixing with the appropriate IZ signal and squaring to produce three (V-IZ) square waves. COMPARATOR BOARD 2HO731 A block diagram for the mho version of this board is shown in fig 13 and for the quadrilateral version in fig 14. The functions of the left hand board of this module are as follows:- a) The Clock Signals A total of seven clocks at different frequencies are required by the various circuits (i.e. level detectors, polarising and comparators). These are all derived from one clock, labelled MCK, by a number of divider circuits.») ) -22- The main clock is divided by 4,5 and 9 to derive three other frequencies, and a further three are generated on the level detectors board. As part of the continuous aonitoring of the Teley the MCK/5 and MCK/8 are monitored, and an alarm given tf either should fail. The Polarising Circuits The polarising signals required for the shaped aho characteristics ate described in section 4.2. They consist of mixing the sheee phage"neutral voltages and the memory signals and digitally phase shifting. The exact proportions are given in section 4-2-1." The Renory {s deseribed in section 4.2.2. when the menory is noe available it is replaced vith a small percentage of -1Z signal. This provides a restraining influence in the polarising for close up three phase faults after the memory has expired. This prevents Qperation of Zi and 22 elements for close up 3 phase reverse faults. Comparators The comparators required for Z1 and 22 are located on this board. The principle on which the sequence comparator operates 1s described in section 4.1. The comparator 1s implenented in a CECH customer designed ULA (uncommitted logic array). Each ULA contains two main comparators and two inhibit comparators as shown in fig 15. In addition each ULA has nine inhibit inputs which when active force a aain comparator to restrain. Inhibits 1-4 act on main comparator 1, inhibits 8-9 on main comparator 2, and inhibits 5-7 are common to both. Two clocks (MCK and MCK/5) are required and the tvo main comparators may be reset by a signal from the scheme logic (MRI). Each ULA has a self checking feature controlled by the scheue logic using inputs SC and MRI. This is described in Section 4.8.5. The tvelve comparators required for 21 and 22 are arranged as shown in fig 16. Each ULA is used for a ground fault element and a phase-phase fault element. One inhibit comparator per ULA is used for a directional line. The quadrilateral version also requires the two side lines as described in section 4.2.5. The remaining inhibit comparators are used for this. The side lines are also sent co the 23 comparators. The additional circuits required to generate the guard zone logic are described in Section 4.2.6.EXTEN ZI = = EER) BETNER! fee ours Ying WNarreviqixis TONE EXT | ioiecac tou || suman “6 me! ! ime EY “UG - aTTEWaTOR [Ty pa) (viz iez1 ce oe bee) | MEN | a ee ested i | (vias gE sre | 3 aise cma TT 1: fom [7 souing -—A > tice fai te Ma reer] | | corcurs’ t I I aa veer i ESrees it Teas] | [ey ve mraz bo) 2g erreur --____} =e ze i... zane 2 0-21 Hi a 1 ' AND ae mast | cuarenT | 1} erremuston xn | seuinie | ‘CIRCUTS, Ke (V- iZ)4822 P=) - nacre es Wve i2ieaz2 1 ov = Go FIG 12 ZONE1/ZONE2 SETTING BOARD ZH0732Sag ee ee 1230 me Je site c ~ || fae et FIG 13 ZONE1/ZONE2 COMPARATORS [MHO version]- 356 = +5 aaa T tT IRN Comm], Ae me vo a t—Jon cont} Coy saecr kv-re ee: Com QA conpanaros one cs v POL AB se are | + 1) BEL oe I] : renory sro teaey Com——_—__] i] (0-208 Cm + Sar oC azz [~~ tu-re eee i¢ oo 18 Com conrana " meats Let aa om = SAG a Jee can_ cere) =| aneroe IE eA conparro 2 Com ee oR Dane 30 C—_——— (UTR eee . — wR G gare “120 | vurm com b conpearan 88 CommgTL INES ea © tee > pet rom CoagsE_8€A0| GUARD |2wz029) FE a CoH SZUrNE) gone [zmnzerr Livro pseu, fe svmnel pore [zmnzezs/ = ’ a DIRECTION cu-TE3802t Come + gto oa 50 Cop IN oad Seare|_ || ERE roe Cobgue_2e00] GUARD [2wz81) 2a a iter “cu sZsanl zone fame | Ih See RM S/2NEh Gro [ENMEEET a $ eeRecrra cu-rmare ¢ 1 Lr Contanaron 1k (— by ae Spice | roc. Conse 0€R0| GuaRO |zwre2 srBCtPH = a coms | ¢ MS/CINE] gone [awererT eee $3 SULA conpanaton an s/unel ogre [ENHzOrT 2 or Decee 7 oe e cto (u-1m8 2 gam| v'rou"ca ae 77 > wexs+ = +0 Py TT ene conpanaton a (uorzca fe cas aii ma) nce Pan rey Er 35 alah exes > iz «exavents Com th LA conraneran = om oo oe Lo aan G ox > 20 aLann ear emo (ose A It Ress | wetercee Come ae conpanaron ae IRE Ci Det a Pouersuzwo eLocK 22 Cam ———— | swnzezrs been POvERSuENG Lock 28 Come fag TERE G + ox cams Sonrmoe, SELF cnecK Comm | CONTROL 5 2uLA conranaron nasten resi < 1% ane| Senee orsaave ca ey fee ~ peat FIG 14. Z0NE1 / ZONE2 COMPARATORS (Quad version)—pnal INHIBIT INPUTS be, «COMPARATOR T= ut} S| ——ai INPUTS MAIN oi ae COMPARATOR 1 INHIBIT } 2 I 3 [cd SS 5 6 ols 7 4 8 7) MAIN ag COMPARATOR 2 INPUTS out 2-— — B62 —-a2 INPUTS INHIBIT pout e FIG. D2 COMPARATOR 2 CONTROL HT MCK ye ‘SC MRI 15 LAYOUT OF ULA-27- FIG 16 COMPARATOR INPUTS FUNCTION, {wa | mpurs | x0 1 quap Zone iA Comp | 1 al (W=I2) 421 (W-TZ) 422 BL Vv Pol A Ry, Zone 1 A-B Comp | 1 2 (V-12) 4321 (12) q p22 82 V Pol AB Vv Pol AB Zone 1B Comp | 2 al (V-12)g22 (Wo1Z) 321 BL v Pol B Ry, Zone 1 B-C Comp | 2 2 (WIZ) geza (WoIZ)gc22 32 Vv Pol BC V Pol BC | Zone 1C Comp | 3 AL (12) 621 (Woz) 22, aL v Pol C IRy Zone 1C-A Comp | 3 | a2 (W-I2) e421 (W-1Z)gg2d 82 V Pol CA Vv Pol CA Zone 24 Comp | 4 al (W-I2) 422 (¥=12)422 | BL v Pol A Ry Zone 2.A-B Comp | & a2 > | (voIZ) 4572 (WIZ) gg22 B2 V Pol AB V Pol AB Zone 2B Comp 5 AL | (vetz) 322 (V-1Z) 322 Biv pers IRg Zone 2.B-C Comp | 5 2 (W-12)go22 (W-1Z) gc22 B2 V Pol BC V Pol BC Zone 2C Comp 6 al (W-12)¢22 (W=12)¢22 BL Vv Pol C IRe Zone 2 C-A Comp 6 A2 | (WIZ) e422 (WIZ) 422 32 Vv Pol CA v Pol Ca A Directional : DAL | -IyZpq -TyZeq DBL v'Pol & V'Pol A A Left hand 1 DA2 | Not used -Iy2pq side line DB2 WHIR) 4 B Directional 2 DAL -IpZpy ~TpZpq DBL v'Pol B ¥ Pol B B Left hand 2 DA2 | Not used -Tp2py side line DBZ (WIR) C Directional 3 DAL | ~I¢Zpq -To2py DBL v'Pol ¢ vePol c —-¢.Left hand___|_3|.pa2 | wot-used. -=leZpq, side line DB2 CHER)FUNCTION = 28 - A-B Directional A Right hand side line B-C Directional B Right hand side line C-A Directional C Right hand side line Inhibits all ULA's Power swing block Common pole Dead Pole Dead Directional P/F Pover swing blocking Common pole dead Pole dead Directional P/F via |_rxpurs 810 ! Quap ee [ "ABSPH 2 pat | v Pol AB viPoL AB 6 | pag Not used (VIR), DB2 ~Iy2H Se mtyez 3c oat Tees | TR ag 5 | pag Not used | (WIR)g | ~IsZoy 6 | DAL | -Ta2en ~Tey2 cazPa | DBL | v'Pol ca v°Pol cA 6 Daz Not used (WIR) ¢ DB2 | -I¢2pq 1-6 | Ne ) | Left hand side Iine | |} Moe uses | Right hand side Line / | ) | Guard zone | Directional G/F | Directional G/F DIco | 0tco | | | |= 29 - ZAs(KI 6 K12+K13)K14x2Ph ZIKHTIRKIS Z2=(K21+K22)K24xZPH eli 2 2 19 13 KIS oo 02 og O 03 K22 08 04 0 07 9605 fo" Me Fig 17 Nameplate details RRMO83.6 = 30- 20NE 3 MODULE RRMO9 INTRODUCTION This {s a two board aodule which contains the forvard and reverse Teach settings, polarising, and comparators for Zone 3 (23) and Zone 6 (Z6) the Power Swing Blocking zone. The two versions available are offset lenticular for phase and ground faults, or offset ho for phase faults with offset quadrilateral for ground faults. The two nameplates showing the setting details are shown in fg 22. SETTING BOARD 2HO734 The right hand board is common to both versions except the addition of a switch labelled a/b for the lenticular version. This switch controls the aspect ratio. A block diagram {s shown in fig 18. The forvard Z3 reach is obtained by attenuating each of the Phase~neutral voltages by switches and resistor networks. The switches labelled K31, K32 and K33 set the forvard reach. The attenuated voltages are mixed with the appropriate IZ signals and the Fesultant squared and level shifted to produce the six (V-IZ) square vaves. The reverse 23 reach 1s similarly obtained by switches labelled X33, K35 and K36 and resistor networks. An additional switch K37 controls an amplifie# to give fractional settings. The six (¥+IZ) square vaves required for 23 polarising are obtained by aixing the attentuated voltages with the appropriate IZ signals and squaring the resultant and level shifting. The Power Swing Blocking zone (26) surrounds the 23 A-B phase~phase elenent. The forvard reach is set to 130% of 23 forward reach by attenuating the 23 voltage and mixing vith the appropriate current to give (V-1Z),326. The reverse 26 reach is set to be 23 reverse + 30% of 23 forvard. The (V + IZ),3 26 square wave is obtained by scaling and mixing appropriate voltages and currents. This requires extra switches ganged to the 23 setting switches. The low set neutral level detector is located on this board. It operates in conjunction vith the reference level and hysterisis circuits on the level detector board in the same vay as the high set neutral which as been described in Section 3.4. For this level detector ty = 0.155 cycle and tz = 1.1 cycles. COMPARATOR BOARD ZHO733 A block diagram for the lenticular version of this board 1s shown in fig 19 and for the quadrilateral version in fig 20. The functions of the left hand board can be divided into two areas. a) The Polarising Circuit The polarising signals required to produce the offset lenticular and circular characteristics are described in Section 4.2.4. The V +12 signals are phase shifted by the appropriate angles using digital shift registers») -ae Pigital muleiplexers are used to select the appropriate signals for the aspect ratio selected by the switch a/b. Comparator jhe couparators used for 23 and 26 are of the same design as those described in section 3.5 used for Z1 and 72” Four ULA's are settee eeor rhe, Lenticular version and five foc the fosdTilaceral. The ULAs are arranged as shown ic fig 21. The TAND"ing the outputs of a forvard aain comperstor ony a reverse main comparator.T20NE 3 FORWARD 7 : SETTING ‘ Nour =" isien32)! K33 i +} sae ae | ae ea) i % @ Hf arteweroa [77 2ove 5g CR 23 common a | vourse FN BES ! 280 % one conto Lev 2iaars Ya @ atTewuaTor [7 BORING) [== 2)8c73 one H ] ' | Sausaing -—=9 1. rics ee re ! aiecng ATTENUATOR: | =) (Vo IZ )AZ3 ‘ i = v.71 AT Pe rs Se 3 REVERSE SETTING Vin7(03504341) || UKS34K35) : | i [| || a | rh Hip | [var i attenuator [7 [| UL par Sa strenaroe a a Lt errewuartoat sucha common o> Netraa eve siren | Con = USAF meKieG MCK/o—_—_ sIV @ oo = FIG18 6S | + USNREE, {tow set DLDLSN == (a i2)4823 n) (We 12 8CZ3 ==) ve i217 p= ei a8%6 ZONE 3 SETTING BOARD ZHO734-33- vezars oa (wverziaga WoT TaB B TRI verewaza consenaror oy ea ee ve ees - comessaroa oS TET sy aaa yeitees aie AOR Werte ee ea 1 | =} 7 earn tweens pre a a Ge | Venige TA} wo meas comeaneToR | [over ar ay ae a T amt | : : 21sec, | [se TELE 87 ee a eiZ1B826 penis oe pe WIE Bes Ps me os om acon ocoom permet meee MOK Ome mt | CONTROL rose 4 scam 81 me FIG 19 ZONE 3 COMPARATORS [Lenticular]a a [_| sa Te eT pee a “ | pose] RL | TT ] ES | Come ee | a a a [eesernee mS i Ive Tiss. / (el > Ve zao ve«3 om FIG 20 ZONE 3 COMPARATORS [QUAD Version]FIG 21 COMPARATOR INPUTS = 35 - FUNCTION | va {_inpts: I MO. + QUAD 23.4 Comp | 1 al (V-12)423 (V-12) 423 BL (W#I1Z) 4/-(180-6) TR, 23 A-B Comp ‘i a2 (WIZ) 4323 (W=12) 4323 32 (W4T2)gn/-(180-0) | (Iz) p5/= 90 23.2 Comp 2 a (v-12)g23 (V-12) 323 BL (V+I2)p/=(180-9) IRg 23 B-C Comp 2 2 V~12) yoZ3 (V=12) g¢23 B2 (V#1Z)gq/-(180-9) (V#1Z)g¢/= 90 23.¢ Comp 3 al (¥-12)¢23 (¥-1Z) 23 BL (V#1Z)¢/=(180-6) IR 23 C-A Comp J 3 a2 (W=12) 6423 (12) ¢423 B2 (V+12) ¢q/=(180-9) (V4IZ)eq/= 90 Z3R A Comp 4 al Not used IR, BL (WHIZ) 423 26 A=B Comp | « a2 (V>12) 4526 (V=12) 4525 32 (V+IZ) 4326 /-(180-0) | (V+IZ)qn/- 90 Z3R B Comp {5 at) IR | ay (WIZ) 323, ) Not applicable Z3RC Comp 5 2 7 IR 82 ) (W#12)¢23 23.4 INH Comp 1 DAL (V-12) 423 ) DBL (WHIZ) l= 0 ) ) 23 A-B INH Comp a Daz (VIZ) 4323 ) DB (W+IZ)ap/= 0 ) ) 23.8 INH Comp 2 DAL (V=12)523 ) DBL (WHIZ) g/= 9 ) ) Not used 23 B-C INH Comp 2 DA2 (W=1Z) 5623 ) DB (W#IZ)ac/= ) ) 23.¢ INH Comp 3 DAL (W-12) 623 ) DBL (WHIZ) ¢/= o ) ) 23 C-A INH Comp 3 Da2 (V=12) 0423 ) DBZ (V+IZz)ea/- 6 )36 - FUNCTION | uta | rpurs | x0 Quap A Guard Zone 4 | par ) Not used (W-12) AG DBL TR, 26 A-B INE Comp 4 | paz (W=12) 4326 ) Not used ‘DB2 (V+IZ)an/- o d B Guard zone s | pat (v-1z) a6 DBL ) IRg ) Not applicable C Guard zone S| Aa >) (v-1Z) co DB2 IR INHIBITS [i-3 | INA. G/F Lenticular QINH 23 side lines 2 a > 3 ) Not used ) Not used 4 ) ) 5 DIco DICo 6 PSB23 PSB23 2 Common pole dead |Conmon pole dead 8 Pole dead Pole dead | 9 P/P lenticular [Not used INHIBITS }oa | om, D QLNH 234 2 ) Not used PSBZ3 3 ) ) Not used 4 ) 2] 5 pico DIco 6 Not used Not used 7 Pole dead A Pole dead A 8 Pole dead B Pole dead 3 9 26 lenticular [Noe used INRIBITS s | INR ) QINH 238 2 5) Pole dead B 3 ) ) Not used 4 7 ) 5 ) Not applicable [DICO 6 . PSBZ3 i ) Not used 8 > Pole dead C oi QINH 23 C-37- = (eee is i 3 3 4K 4 Kt : 5 : 5 ae 78 oo oo 02 oz os 03 K32 | os 03 K32 os 04 im 4 | 07 96 05 07 9408 Vs of? | k33 - K33 oi a 10 b a) | | (on VV 23=(131-K321K3307en 23 (K31+K92IK3907Ph 23 +(K35-K38)NI3AKI7«2PH 1335 -K30IKI3«K37«ZPh 12 iF | | 3 a | 4 K35 4 KIS 8 5 8 s aye O40 Oo oo 02 2 0 03 K36 o 03 K36 os o o 04 07 9908 07 9408 205 wos 10 ear Ki : Ka7 - = Fig 22 Nameplate details RRMO937 37 36702 -38- SCHEME LOGIC MODULE RCL 10 GENERAL The complete QUADRAMHO scheme logic is contained in one 10" x 2” module. This module consists of two circuit boards and one interboard screen. (a) The left hand board is the scheme logic mtcrocontroller board which contains the microcontroller, expansion input and outputs, four svitch banks, eight LED indications, the interconnecting wiring on the two code switches and the socket SKl. See fig 23. (>) The right hand board contains the five opto-isolators, three high set phase current level detectors, the zero Sequence voltage level detector used by the VTS and also the Power swing components which consist of the four way switch bank and the PSB LED. See fig 24. (c) The centre board ts a blank board with copper plating on one side, this board is earthed and forms a screen between the opto inputs and the scheme logic. SCHEME LOGIC FUNCTIONS The schene logic performs the following funct/ons:~ a) Provides five standard schemes, these are Basic, Permissive Underreach, Permissive Overreach, Blocking and Zone 1 extension which are selectable by using the code switches. >) Switch onto fault logic. ¢) Voltage Transformer Supervision. 4) Selectable Power Swing Blocking logic. e) Synchronous polarising. £) Time delayed Zone 2 and Zone 3 tripping. 8) Block auto reclose logic. h) Indications logic. 1) Fault locator logic. J) Pole dead logic. k) Comparator level detector checks. 1) Bandpass filter switching logic. =) Amplitude and angular hysteresis control. n) Tripping and latching logic. 0) “Selectable atnor options. p) Self test features.3.7.3 - 39 - 9) Processor fail monitor, r) Relay inoperative alarm. 8) Comprehensive test options. The majority of these features are described in section 48. SCHEME LOGIC SETTINGS AND INDICATIONS an illustration of the frontplate layout is shown in fig 26. INDICATIONS ihe, Scheme logic provides nine indications, the function of each indication is described below:- INDICATION NAME FUNCTION oF PLATE LEGEND INDICATION A Fault involving "A" phase 3 Fault involving “B” phase c Fault involving “C™ phase 22 Zone 2 time delayed trip 23 Zone 3 time delayed trip AIDED TRIP ignal aided trip (PUR, POR or BLOCK) SOTF Line 1s energised onto a fault VAUFAIL Fuse failure condition POWER SWING Power swing condition CODE SWITCHES The code switches allow selection of the five standard schenes vith associated tripping modes and also the test options (see section 4.8.7 and 3.7.20 respectively). The left hand code suitch {s labelled X hile the right hand suitch is labelled ¥. SWITCH BANKS qhe top switch bank tz2 (see fig 26) 18 used to set the Zone 2 tine delayed trip time. The tiner has a range of 0 to 2550 mS in imerenents of 10 aS. The tiner is set by setting the required syttches to the right hand position. The total time ts the summation of all the individual switches. The Second switch bank ¢73 {8 used to set the Zone 3 tiae delayed foie time. The timer has a range from 0 to 5080 mS in increnents of fo mS, The timer also has an infinity position which 1s selectable via the top switch. Setting of the timer {s similar to the Zone 2 tioer.The third switch bank (tp and tp) is used to set the tp and tp current reversal guard timers. The top four switches correspond to tp while the lover four switches correspond to tp. Both t, and tp can be set in che range 0 to 90 a§ in increments of 6 aS. "Setting of the timers is simtlar to Zone 2 timer. The fourth switch bank contains the minor options that are available (see table 2). The switch bank at the top right hand side of the module {s used for the Power Swing Blocking circuitry. The top three switches are used to block Zones 1, 2 and 3 individually. Blocking is performed with the switches in the right hand positions. The bottom switch , SW9, 1s used to select the PSB option when in the right hand position (see section 4.4). TABLE 2 OPTION SWITCHES TCH WOMBER | LEFT WAND FUNCTION | RIGHT HAND FUNCTION | | ! 69 | power suing blocking | rover aving blocking | disabled | enabled | | ' SWB | Disable weak infeed | Enable weak infeed option | opeion | (or) only i | su7 | Disable weak infeed | Enable weak infeed trip if | | trip | weak infeed option selected | Sa6 | Normal A/R action | Block A/R if CIS not ! | | energised for schemes 02 to | | | 07 inclusive sis | Disable setf- | Enable self-checking checking | | sua Normal A/R action | Block A/R for 3Ph Z1/AT | | Faults | | Sw3 VTS Indication only | VTS Indication and Block | sw2 SOTF dead tine 110 | SOTF dead tine 200 as | Suh SOTF for any | SOTF for current and no | comparator operation | volts on any phase PUSH BUTTON The push button {s used to clear the indications, manually rua the comparator self check and in the test option routine. TEST SOCKET The test socket SK on the front of the aodule {s provided so that the code switches and push bucton can be overridden electrically for use with automatic cest equipment.3.764 3.765 -a- Pins 1 to 8 of SKI allow the Code Selection Number (XY) to be overridden. The number XY is in binary coded decimal form vith one input of SKl corresponding to each bit (see table 3). Any code selected with the exception of 58 (see page 64) can be overridden by applying the Correct Code to SKl. Any of the input pins which require a "0" should be connected to SK2 pin 2 (OV). The normal state of the socket (No input present) is FF Hexadecimal (All inputs at high state '1'). TABLE 3 SKI INPUTS SK1 PIN NO. OVERRIDE FUNCTION 1 cw ¥ bit 0 2 csw ¥ bit l 3 csw ¥ bit 2 4 cw Y bit 3 5 cw X bit 0 6 csWw xX bit 7 csw xX bit 2 a csw xX bit 3 9 PUSHBUTTON For example to select Code 41 (01000001) Connect SK2-2 to the following pins of SKl; 2,3,4,5,6,8. In addition co this the pushbutton can be electrically driven by connecting SKI-9 to SK2-2- GENERAL DESCRIPTION OF MICROCONTROLLER ASSOCIATED HARDWARE The scheme logic {s implemented using an 8 bit atcrocontroller operating under software control. The microcontroller used is the 8039 HL member of the MCS 48 family. This device has 27 Input/Output (1/0) lines. Further 1/0 expansion is obtained by using three 8255 A programmable peripheral interfaces (PPL). Each PPI has 24 1/0 lines nade up of 3X 8 bit ports and is addressed under software control. An extra six outputs were obtained by using a Hex "D" type flip flop. A functional diagram of the scheme logic 1s given in fig 23. The scheme logic software is stored in 4k bytes of standard EPROM type D2732 A. The microcontroller operates using a 10.7 Miz crystal which gives a cycle time of approximately 1.40 uS. MICROCONTROLLER AND PROGRAM MEMORY Each byte of program has a specific address within the EPROM. This address has 12 bits and {s generated by the microcontroller. The lower 8 bits of the address are present on the mferocontrollers 8 bit data bus which ie multiplexed with other data. The address is denultiplexed using an 8 bit latch. The higher 4 bits of the address are present on the lover half of the afcrocontroller port 2. When the complete address has been established and latched, the aicrocontroller reads the EPROM data and is then able to perfor the instruction contained in the dataCOMé GUO WUISUTG MUU It! Se ILS eveitee ERRRREREERED teeeeeRe EL ERE? i ! 2 atte ae lh Bentetepereer 3 H a J|eteeeerter-43- 3.7.6 PROGRAMMABLE PERIPHERAL INTERFACES 3.747 Each PPI has to be programmed to the required mode of operation before data can be transferred between the PPI and the microcontroller, Data is written to each PPI to specify the configuration required. The configuration used for three PPIs is shown below. PPI O has 24 input lines (3 X 8 bit input ports) PPI 1 has 24 output lines (3 X 8 bit output ports) PPI 2 has 8 input lines and 16 output lines (1X8 bit input port, 2X 8 bit output ports) Data can only be transferred between the microcontroller and any one pore of the PPI at any given instant. Also, because there are three PPIs on the data bus (as well as other devices) only one of these PPIs must be enabled at any one tise. Each PPI port (A, B or Cc) ts selected using tvo address lines, vhile the PPI is selected by usiag another address line to produce the required state on the CS (chip select) pin. The address 1s generated by the microcontroller when a tead or write operation is performed. A "D" type flip-flop is used to obtain an extra six outputs and {s addressed in a similar way to the PPIs. . MULTIPLEXED PORT Port 1 of the microcontroller is an 8 bit port which is used to read the data from the following:~ a) 4 switch banks b) 2 code switches ©) SOCKET 1 4) 4 other inputs The data from the above is multiplexed onto the port in the following vay. Each of the 4 switch banks 1s enabled by an output line froa PPI 1 port A. See fig 23. This output allows the data on each switch to be read by the sicrocontroller via port 1. The code switches are also enabled by an output line from PPI 1 port A. Each code switch produces the BCD equivalent of the selected aumber and requires 4 input lines to be read. The code svitch ¥ is aultiplexed onto the lower 4 bits of port 1, while code switch X is multiplexed onto the higher 4 bits of port 1. The tvo code switches are enabled together. The test socket ts also enabled by an output from PPI 1 port A, when selected data is transferred from the test socket inputs to port 1.3.7.8 3.7.9 3.7.10 = 46 = The 4 other inputs operate similarly to the above. These inputs are Fouted to the higher 4 bits of port 1 vhen they are enabled by microcontroller port 2 bit 7. For all of the above only 1 of these functions is enabled at any given instant. The data from the switches and other inputs to port } are read during the running of the softuare main loop (see section 3.7.19). The enable 1s generated by the microcontroller. HARDWARE RESET OF MICROCONTROLLER AND PERIPHERALS In order to ensure correct operation of the schene logic, the microcontroller and peripherals aust be correctly initialised after power supply rails have stabilised. A reset pulse of duration 50 aS is applied to the microcontroller and peripherals after power up Procedure. After power reset, the initialisation of software registers begins (see section 3.7.19). The reset pulse is also applied if any of the following conditions occur. a) +5 -V rail drops below approximately 4.5 v. b) Microcontroller fails to execute the software. These are described in mere detail below. + 5.V RAIL MONITOR The microcontroller PPIs and other devices operate on +5 V. If this rail drops in voltage then a partial reset may occur. To ensure a full reset the + 5 V rail is monitored. when this drops below approximately 4.5 V, a continuous reset is applied to the Bicrocontroller and PPIs. If the voltage rises above this level then a power up reset is performed. Thus ensuring all devices are reset completely for interruptions in the D.C. supply. The loss of the + 5 V rail will cause the “Relay Inoperative” alarm contacts to close (see 4.8.25). MONITORING OF SCHEME LOGIC SOFTWARE The scheme logic softvare executed by the aicrocontroller ‘s monitored to detect and correct any maloperation that aay occur. When the intended software loop is being run, the code switches are always read at the beginning of the loop regardless of the schene selected (see section 3.7.19). As mentioned in section 3.7.7, an enable output is sent to allow the microcontroller to read the code switches. This enable is monitored by the code switch monitor circuit which decects if the enable ceases to occur. If so, the reset circuit {ts activated which resets and allows re-initialising of the PPIs and the microcontroller. Failure of the microcontroller or software will cause the “Relay Inoperative” alarm contacts to close.3.711 367412 3.7413 = 45 - INOPERATIVE ALARM The Relay Inoperative alarm circuit on the scheme logic board monitors a pulse which is normally present on port 2 bit 6 of the microcontroller. If the microncontroller fails to execute the normal scheme loop, the pulse ceases to be present causing the Relay Inoperative alarm to operate. Removal of the pulse is caused by the following :- a) Failure of the microcontroller. b) Selection of a non valid scheme option (see test option section 3.7.20). c) Failure of the +5 V rail. 4) Operation of VIS with SW3 set to right hand position. e) Failure of comparator during self test routine. £) Energisation of the miniature circuit breaker open opto coupler (MCB version only). The inoperative alarm circuit also monitors the + 12 V rails if this drops below approximately 7.5 V then the Relay Inoperative alarm will be given. 20NE 1 INTERRUPT GATING LOGIC The Zone 1 interrupt gating logic is a hardware gating of the Zone ] comparators outputs with the corresponding low set current level detectors (LDLS) and the high set neutral level detector (LDHSN). This ensures that an interrupt can only take place when a trip condition occurs on Zone 1. SYNCHRONOUS POLARISING (MEMORY) HARDWARE The operation of the synchronous polarising (digital memory) is described in section 4.2.2. The basic hardware associated with the memory is as follows. The memory uses one phase (Vc) of the input 3 phase volts to the relay. This input is squared and then level shifted before being input to the microcontroller. Only 1 phase of the memory output (Vyc) is produced by the microcontroller, the other two (Vyq and Vyg) are derived from this using external hardvare coaponents. Voltage Vy, is produced by first shifting Vyc by - 90° and then by a further 30° to give Vyc /=120° (Vya)- Voltage Vyp is produced by inverting Vyc (giving Vyc /-180°) and then shifting by - 60° to give Vc /-240° (Vyp)s3.7.14 3.7.15 ee INDICATIONS The indications of the scheme logic are given by aine LEDs. All these indications are driven by the scheme logic microcontroller: Eight of the indications are controlled by PPI port 3 and ere contained on the scheme logic processor board. The ninth LED is controlled by PPI 2 port B bit 5 and is contained on the opto isolator board. All nine indication LEDs are buffered by transistors to enable sufficient current to be provided for a good level of illumination. The eight indications of the scheme logic processor board alse supply external outputs which are available on socket 2 on the mintature relay nodule (see also 4.8.26 and 4.8.27). OPTO ZSOLATORS There are three different operating voltages as given in the following table:- NOMINAL OPERATIVE RANGE ABSOLUTE MAK 48/34 v 37.5 = Gov 64.8 ¥ 210/125 v 87.5 = 137.54 150 220/250 V WS = as 300 v There are five opto isolator inputs available in the scheme logic godule, all of these are fitted on all voltage versions of the board. The opto isolator inputs are used in the schemes and the functions of these are described in section 4.8.14. The opto tsolators have a defined minimum operating voltage of greater than 10 V (all voltage versions). Transient suppressors are Fitted on the inputs to prevent damage to the opto-isolators. A tine delay of between 0.3 and 1.1 mS is incorporated into the output cireuit of each opto-isolator, this {s to prevent transient operation of the scheme logic inputs. A guard ring (earthed) 1s used to protect the output side of the opto isolator from noise that may be Present on the input side.ane 3.7.16 ZERO SEQUENCE VOLTAGE LEVEL DETECTOR 3.7.17 The zero sequence voltage level detector (LDVO) ts used by the VTS to detect an imbalance in the system voltage. This level detector is designed to operate for a voltage drop of 45% or greater in any one phase, The level detector is designed to operate over the frequency range 47 to 61 Hz. The input level of pick up voltage for the frequency range ts as follow 50 Hz (47 - 51) P/U = 38 ~ 52% of rated volts 60 Hz (56 - 61) P/U = 40 57% of rated volts A block diagram of the level detector is shown in the main block diagram of the scheme logic opto board (see fig 24). OPERATION AND CIRCUIT DESCRIPTION The three phase voltages V4", Vg', Vc! are added together to produce the zero sequence voltage (if all phase voltages are present then this summation will be zero). This {s then passed through an input aaplifier and low pass filter. The input amplifier matches the faput signal level to the reference level of the voltage comparator while the low pass filter is used to reject harmonics. The voltage comparator detects if the input voltage exceeds the reference level, Af this occurs, the output of the level detector is set high. The voltage conparator uses two reference levels, one for che positive half cycle and one for the negative half cycle. Hysteresis is added to ensure no chatter exists on the output which could occur if the input signal level is on the threshold of operation of the level detector. A drop off timer (9 - 12 aS) is used to hold the output high when the input signal level drops below the reference level, thus filling in the gaps between the half cycles. . HIGH SET CURRENT LEVEL DETECTORS The high set phase current level detectors (LDHSA, B, C) are used to improve stability of operation tn the Blocking and Permissive Overreach (with Weak Infeed) schene: The operating principle 1s identical to the zero sequence voltage level detector (LDVO). The only difference is that the sunning amplifier has been replaced by a high gain input stage to match the low input signal levels produced by the current measuring circuitry (see fig 24) to the level required by the level detector. The taput levels to operate the level detectors are as foliows:- 50 Hz (47 - $1) P/U = 10.1 - 14.0% of rated current at reference setting 80 Hz (56 - 61) P/U = 10.7 - 15,27 of rated current at reference The high set current level detector lowest setting (tolerance) is designed to be 10% greater than the highest pick up level of the low set current level detector.oe if. zNeur 28: BHOSE | sunmane |! anmezeter |_| vorrace ERO SEQUENCE VOL Tage TES BNREET] ctrcurtey 1] “ano cau I+] conpanaor EVEL DETECTOR OUTPUT '[enss rit ten r INPUT — renuzen sar | nrc carn || anatcezer || vorrace | | RP Ti on. ouase uzcu ser cumnens fiace Ameczezen [1] “ano aE” 4 conpaastor Tevet pereeras buteus ilesvestren ree | nemczen -ar_| sxsw carn vourace || 92" [1 og. puase erase saeuzesen conpanaran ; : INPUT, : waa sarw [1] arden | | ourase |] 280? |i c+ once AMPLIFIER [7]__ANO WOW COMPARATOR |) fe LeveL || pass FILreR| TIMER: 7 ogtetreo ——_]__sweur_ |} erzcacee | | one FauLr oerecren ev per eyecne protectzon |] SOURED ceay OPTICAL IScUATOR OUTEUT ezecurt oprzcauiy es : input tne crRcurT aeeaKer cPeN ed provecrzoy | t SOURCES. F} oetay optsea. zsocaron GuTPUT SS) eee avock zxeur || cprzcmusy | | sone Lock 227 ano est Bat AND 23T protection | | ) Hysteresis is sent ¢) Correct tripping contacts are closed (see tripping logic section 4.8.16). 4) Carrier is transmitted if PUR schene ‘s selected e) The trip drop off timer is run After the above the software ts executed from the beginning of the main loop. LOAD SUBROUTINE The LOAD routine perforas che following:- Firstly the Code Switch Number (CSN) and the code switch qumber override (CSN 0/R) (pins 1 to 8 of socket 1) are stored in two Tegisters. The CSN O/R is tested to determine if an override {s required. If an override ts required then the CSN 0/R will decersine which scheme ts run. If no override is required then the CSN will determine the schene. The CSN or CSN 0/R is then tested to see {fa valid schene option is selected (00 -08). If this {s not true, thea the test option software is run (see section 3.7.20). LLAD SUBROUTINE The LOAD routine now runs another routine called LLAD. This reads all the input ports of the microcontroller and peripherals and stores all these input in internal memory for use later on in the program. The taputs loaded consist of the following. 4) tp and tp svitch bank settings Zbne 2 suitch bank settings Zone 3 switch bank settings OPTION switch bank settings >) All level detector outputs €) Push button stare This routine also clears all the registers that are designated output registers (described earlier). PDTIM SUBROUTINE The PDTIM subroutine runs the pole dead pick up timers and sets the pole dead outputs and internal flags. These flags are used by several subroutines within the main loop. The pole dead logic ts explained 1a section 4.3.1. VTS SUBROUTINE The Voltage Transformer Supervision (VTS) is described ia section 4.7,-53- LOAD 1 SUBROUTINE The LOAD 1 subroutine reads the Zone 1, 2 and 3 comparators and Perforas level detector checks on then (see 4.3). The couparator § Die format (A, By Cy A-B, BC, CA) ds converted to 4 bit forme (A, B, C, N). It also sets internal flags to indicate that a fault has occurred in a particular zone. If the VIS has issued « “block comparator” signal then the comparators will be software inhibited within this routine. FLOC SUBROUTINE The FLOC subroutine generates the fault locator outputs (see Fig 74 for the logical equivalent). For all schemes the fault locators normally operate based on the Zone 1 and Zone 2 comparators (Zone 3 is aot used), but this can be overriden by the SOTF (SWITCH ONTO FAULT) feature (see 4.8.24), The FLOC subroutine also sets an internal flag which indicates that any comparator has operated. SOTF SUBROUTINE The SOTF operation is described in section 4.8.24. SOTF FAULT LocaToRS = + Under normal scheme operation the fault locators operate on the comparator information as mentioned earlier. Iz the SOTF feature is selected to operate on current and no volts (CNV) during the SOTF enable time the fault locators vill operate oa the CNV condition that has caused the trip. The fault locators will follow the CNV condition for the SOTF enable time (240 mS after all poles established) or until the CNV condition has been removed whichever ts the longest. The SOTF feature disables the Basic scheme and prevents the carrier schemes from issuing a trip. It should be noted that if a SOTF trip is still present after che SOTF enable timer has run out, the SOTF will remain enabled until ‘the fault has been cleared. BASIC SUBROUTINE The Basic scheme ts not run if SOTF is enabled. The Basic scheme is run for all valid scheme options and is descripted in section 4.8.8. OPT SUBROUTINE The OPT subroutine allows selection of any of the five standard tripping schemes available via the code switches. If the Basic schene is selected then the program bypasses the scheme options. The schemes are described in sections 4.8.7 - 4.8.13.The Carrier Aided schemes (PUR, POR and BLOCK) all use a smaller subroutine called AT (Aided Tripping). This small subroutine sets indications based on the Zone 2 comparators. Ir also sets the tripping mode, depending on the CSN. The Carrier Aided schenes alsc use another subroutine called BCIS. This subroutine performs the following if the channel in service (CIS) opto isolator input is not energised. a) Allows only 3 phase tripping. b) Blocks the auto reclose equipment if SW6 is set to right hand position. MFAST SUBROUTINE The purpose of this subroutine is to re-enable the synchronous polarising as soon as possible after all conditions for re-start are satisfied. The synchronous polarising is described in section 4.2.2. Under normal operating conditions the synchronous memory can lock onto aa input stgnal at 80.75°/second @ 50 Hz. This would mean that for a 180° (inverted) maximum phase difference between input and output, the locking on time vould be 2.23 seconds. The locking rate at 60 Hz 1s 116.28*/second. The above vould mean that unless further action was taken the synchronous polarising would be unlikely to be enabled until vell after the SOTF enable tine had elapsed. However, the MFAST subroutine solves this problem and operates in the following vay. If the syachronous polarising has run out and is ao longer required to run (see section 4.2.2) then a timer of length 140 mS is run to allow several cycles of synchronous polarising input to be established. When the tiner runs out the synchronous polarising enable flag 1s reset, the tiner interrupt (described later) is delayed by approxizatley 80 uS, so that synchronous polarising registers can be pre-set. The synchronous polarising output 1s delayed by 4 interrupt cycles (4 ¥ 179 uS) .rom the input waveform, so that when an interrupt occurs the output can follow any changes of state that occur in the input. If this was not done the output aay get out of phase with the input and would only phase lock at the normal synchronous polarising run lock-on rate. PSMIS SUBROUTINE The PSHIS subroutine runs several functions, the main feature beiag the Power Swing Blocking (PSB) scheme. PSB is described in section 4.4, The functions performed by the PSMIS subroutine are shown below. a) Runs Power Swing Blocking scheme (PSB). >) Reset VTS blocking and indication latches and Power Swing indicator latch {£ the push button 1s operated. Perforas trip latching logic and runs trip drop off tiner. 4) Runs the BAR drop off tiner.-55- e) Sets various output register flags. £) Re-enables Zone 1 interrupt feature after previous interrupt has been terminated. 8) Sends a uaster reset pulse to the comparators after an “All Poles Dead” condition is detected. EXOP SUBROUTINE This subroutine performs several functions, these are listed below:- a) Clearing and latching of the scheme logic indications (see 4.8.26). b) Runs the comparator self check routine (see 4.8.5). ENF SUBROUTINE ‘The ENF subroutine performs the bandpass switching logic. This logic is used to improve performance of the relay and is explained in ection 3.2 and 4.8.3, OP SUBROUTINE The OP subroutine transfers the data that is stored in the output registers to the correct output ports. The OP subroutine also runs a test to determine if the timer interrupt is running, if not, the interrupt is re~enabled. LTIM TIMER INTERRUPT ROUTINE The timer interrupt is an internal interrupt that 1s generated within the aicrocontroller. The digital synchronous polarising and software timers are contained within the timer interrupt routine. The timer {aterrupt occurs at regular intervals of approximately 179 uS. The synchronous polarising is serviced on every timer interrupt which gives a resolution (jitter) of the menory output Vyc of + 3.2° (for a detailed description of the menory see section 4.2.2). The timers are serviced in six groups which contain two or three timers. Each group of timers is serviced once in every eleven timer interrupts which gives a timer resolution of 11 X 179.44 = 1.974 aS.= 56 = BASIC INTERRUPT PRINCIPLE When an external or timer interrupt request 1s aade, the asin loop continues executing the current instruction. After this has finished, the address of the next instruction to be executed within the main loop is stored automatically by the microcontroller. The interrupt routine is chen entered and the data being processed vithin the main loop at the point of interrupt is then stored temporarily. This allows restoration of data when the interrupt returns from the main loop. Normally the interrupt returns to the address stored when the interrupt occurred. This is true for the timer interrupt, but within the schene logic the external (Zone 1) interrupt {s sonetines “forced” to return to the beginning of the loop (see Z1 INT routine). PRINCIPLE OF TIMER OPERATION There are 16 timer interrupt timers which all operate using the sane principle. The basic operation is as follows. Four internal alcrocontroller registers are allocated for use by the tiners, tvo of these are designated tiner start registers (TSR) which contain 16 tiner start bits (one for each tizer). dmilarly the other two registers are designated tiger run out registers (TROR) and contain the timer run out bits. The timer start bit {s set in the main loop when the timer is required co run similarly this bit is reset vhen the timer is to be reset. When the appropriate tiner 1s serviced by the timer interrupt, the timer start bit vill be tested to see if the timer 1s to be run. If a rua condition ts required chen che timer vill perform a counting sequence in a tegister that has been designated a timer register. The count within this register 1s incremented every time the timer is serviced by the timer interrupt routine (every 1.974 a$). When the timer has reached the required count, the tiner routine sets a bit in the timer run out register, this is the timer run o bit. Every time the program executes the main loop the timer run out bit Will be cested to see if the timer has finished. If a reset condition {3 required, the timer rua out bit and the timer register are reset when the timer is next serviced by the interrupt routine. Thus the timer is ready to be run vhen required. A list of all the interrupt timers is given in table 4. Each of the 16 timers 1s allocated at least one tiner register, long tiners such as the VIS 5.5 S timer require more than one timer register. The settable Zone 2 and Zone 3 delayed trip timers use multiples of a basic timer lengeh (e.g. 22 basic length ts 10 aS). The appropriate switches are used to provide the multiplication factor. There is a l7th interrupt tiner which 1s used to generate the 2 week automatic self check delay. LOOP TIMERS Several of the shorter timers used within the scheme logic are LOOP timers. These timers are run completely within the main loop. The operating principle of these timers is described below. When the timer {s required to run, a register which ts designated a tier register is incremented once every time the main loop is executed. This {s then tested to determine if the timer has finished, if it has, then the timer register {3 reset. A list of all the lcop timers is given in table 5.TABLE 4 INTERRUPT TIMERS (REN FNcTIOW T SIGNAL RECEIVE DROP OFF 1 Tp BLOCK AUTO RECLOSE DROP OFF ANY POLE DEAD DROP OFF | VIS ACCELERATED | ICATION PICK UP | SYNCHRONOUS POLARISING (MEMORY) ENABLE PICK UP | | (20R) CIRCUIT BREAKER | OPEN PICK UP SOTP DEAD TIE SOTF ENABLE TIME SOTF CURRENT NO VOLTS PICK UP ZONE 2 DELAYED TRIP PICK UP ZONE 3 DELAYED TRIP PICK UP TRIP DROP OFF VTS PICK UP | Psp PICK UP SELF CHECK ENABLE (CONTINUOUSLY RUN) Sore TIMER LENGTH 100 as 0 - 90 as 0-90 as 100 as 240 ms 20 as 140 as 60 as 200 mS or 110s 240 aS 20 as 0 - 2550 as 0 - 5080 as 60 as 5.58 50 as 2 weeks | THER | RESOLUTION loms | 40 asone TABLE 5 LOOP TIMERS TIMER FUNCTION TIMER LENGTH PICK UP TIMER ZONE 1 PHASE 35 us COMPARATOR BLOCK ZONE 2 PHASE 35 as COMPARATOR BLOCK “| pong DEAD ‘A’ PRASE 20 as PICK UP POLE DEAD 'B' PHASE 20 as PICK UP | | rove oes ‘cr mance =| co as | etek uP | BANDPASS FILTER 14 as | VOLTAGE DROP OFF : | wea sn wot | to es | CompakaToR DROP OFF | | | | POR/WEAK INFEED | 100 as CARRIER ECHO TIME | ern ee | ! |ag 3.7.20 SCHEME LOGIC TEST PROGRAM ThE scheme logic cest program 1s « group of options that are selectable via the code switches. These options are divided inte tus group: a) Input test options. >) Output test options. Lape chit peat coatone erariesced nieatle 6: tndtcctlag) (a gcc ca 0 Tipe (4s BC. 22, 23, AIDED TRIP SOTF, VA FAIL) when the chrvece GSh'ts sets The 8 LED outputs are available on socket 2 (see 4.8.2)), The output test options are listed in table 7. To set any output, firstly the correct CSN corresponding to the test option Feguired sust be selected. The appropriate option switch gust be set co che rpane hand position and the push button should be operated. Only one group of outputs (one test option number) can be energised at any one sine All the TRIP contact output test options are put in a separate option (88) aay from the others to prevent inadvertent operation of circuit breakers, etc. When a test option is selected (or an invalid schene) the “Relay Tnoperative” alarm contact will close and the RELAY AVAILABLE LED will extinguish. The full schenes do not run when a test option is selected, belov is a list of the features that are run when a test option is selected. a) Digital synchronous polarising. >) Pole dead logic. ©) Master reset pulse on “All Pole Dead” condition: 4) Bandpass filter switching logic.aS INPUT TEST OPTIONS TABLE 6 Test | Test and Method T LED. 1 Commence Option | | Indications 1 No I I | 1 1 i 30 _| Zone 1 comparators ear | Amplitude and | Gated with low set \ | angular hysteresis I current level detectors BN | 8 | operate on any I cu ioc | Zone 1 comparator 1 (Secondary Inject AB | 22 1 No tripping will | Zone 1 Fault) BC | 23 i occur I CA | AIDED I I | TRIP i 1 ' \ | Breaker open opto input i ' | (Apply rated volts to 1 SoTF \ | A3 = 44) I 1 ' ! 1 | Reset Zone 1 extension opto | I { input (Apply rated volts to | VWFAIL | 1 al = a2) 1 1 | The "Zone 1 extension" opto is! 1 | redesignated as "miniature | I | circuit breaker open" opto | ! | when this version has-been | I | supplied. 1 \ 1 i ! ar | Zone 2 comparators NT x | Amplitude and | Gated with lowset I 1 angular hysteresis | current level detectors B-N | B | operate on any I i c | Zone 2 comparator | (Secondary inject AB | 22 1 | Zone 2 fault) BC I 23 I 1 CA | AIDED | No tripping will 1 1 TRIP | occur 1 1 I | Signal receive opto input \ 1 | (Apply rated volts to A9~Al0) | SOTF 1 1 1 1 | Channel in service opto input | VW FAIL 1 | (Apply rated volts to A7-A8) | 1 | The "signal receive" opto also! 1 | can be used to "reset Zone 1 | 1 | extension" for the I 1 | appropriate thumbwheel 1 1 | selection option. 1 1 i 1 i w I"Zone 3 comparators ele | Amplitude hysteresis | Gated with low-set | | operates on | current level detectors B-N | B | any Zone 3 | cu c 1 comparator | (Secondary inject eee 22) 1 | Zone 3 Fault) Bec zs 1 I CHA | AIDED | No tripping will I ie ree, | occur | Zero Sequence voltage 1 SOT 1 | Level detector 1 I | (secondary inject) I i i ! I | Inhibit PSB opto input | i | (Apply rated volts to AS-A6) | V/V FAIL 1TABLE 6 (CONTINUED) Sele Test Test and Method LED Comments Option Indications No 43 Overvoltage level AN a | detectors Bw 3 (secondary inject C-N c voltage) Pushbutton & push= 22 button override (operate push- button or apply OV to Ski Pin 9) Low set current A 23 level detectors B AIDED TRIP (Secondary inject c SOTP current) N VOVFAIL 45 Self check of AN A The LED lights Zone 1 comparators * B-N B for the appropriate C-N c comparator if it AB 2 passed the last BC 3 self check. If all cA AIDED TRIP 8 LEDs are illuminated self check has not occurred. | ~ 46 Self check of ACN A As option 45 Zone 2 comparators BN B | cn c AB 22 B-C 23 CHA AIDED TRIP= 62- TABLE 6 (CONTINUED) input (Apply rated volts to A7-A8). The "signal receive" opto also can be used to "reset Zone 1 extension” for the appropriate thumbwheel selection option. Test | Test and Method 1 LED. | Comments Option | | Indications 1 No i 1 I I I \ a7 Self cheek of NI + H 1 Zone 3 BN OT OB 1 | comparators cyoi oc 1 As option 45. \ ee I 1 BC | 23 1 1 CA | AIDED TRIP | I 1 I 1 Self check of Zone 6 A-B | — SOTF 1 | comparator I \ 1 1 \ “301 Zone 1 comparators A-N | > 1 | (Secondary Inject BN | B I | Zone 1 fault) cr oT oc ! 1 AB} 22 1 ! BC | 23 1 1 CA {| AIDED TRIP | As option 40. I I \ | Breaker open opto = | SOTF \ | input (Apply rated 1 1 | volts to A3-a4) 1 I I 1 i 1 Reset Zone 1 extension 1 VA FAIL I 1 opto input \ I | (Apply rated volts to 1 1 1 Al= a2) i 1 | The "Zone 1 extension opto | i | 4s redesignated as 1 1 | “miniature circuit breaker | \ | open" opto when this version| 1 {has been supplied. \ 1 1 1 H aT | Zone 2 comparators A-N | A 1 1 (Secondary inject BN |B I 1 one 2 Fault) cw 1 oc 1 As option 41. 1 AB} 22 1 I BC | Z3 1 I CA | AIDED TRIP | \ 1 1 | Signal receive opto input | SOTF 1 1 (Apply rated volts to A9- | I 1 alo) 1 1 I I 1 | Channel in service opto = | = VW FAIL 1 I I i I 1 i I 1 1 \ \ 1 1 1 1 1 i 1 1 1 1 L i \TABLE 6 (CONTINUED) - 635 Test Test and Method LED Comments Option Indications No | T 52 Zone 3 comparators A-N a As option 42. (secondary inject B-N B | one 3 faule) cA I AB 22 Bec 23 cA AIDED TRIP Zero sequence voltage SOTF level detector (Apply low voltage and increase to piek up) | Inhibit PSB opto VOUFAIL input (Apply rated volts to AS=A6) 33 Memory input volts vc 8 Provides a squared (Apply rated volts monitor output on to C Phase) | socket 2 pin 24. Zone 6 comparator AB c (secondary inject AB Zone 6 fault) | Option setting svitch suo | = 22. LED on vhen | High set current A 23 switches in right | level detectors B AIDED TRIP hand position. (secondary inject ¢ SOTF current) N | vOuFAIL 54 Zone 2 Timer 1280 a Indications lit Switch setting 640 B when svitches in 320 c right hand 160 22 position 80 23 40 AIDED TRIP 20 SOTP 10 VV FAIL 35 Zone 3 Timer oo a As option 54 sviteh setting 2560 B 1280 c 640 22 320 23 160 AIDED TRIP 80 SOTF 40 VOU FAIL= 6a TABLE 6 (CONTINUED) T Test Test and Method | te Conese Option Indications No 1s 1 T 56 Tp tier avitch ry a Pera ch seceing 26 3 2 c 6 z Tp timer switch | | setting 26 AIDED TRIP 12 SOTF 6 VVFaIL T 37 Option switch sw8 ry As option 54 setting sw7 3 sH6 c SHS 2 swe 23 sia | AtDeD tRIP sH2 SOTF . sil VOUFAIL | ! = } | 38 SOCKET 1 INPUTS PIN 8 a This option | PIN 7 3 vill override i PIN 6 c the normal PIN 5 2. function of the PIN & 23 test socket PIN 3 AIDED TRIP | except when PIN 2 SOTF option FO PIN 1 VVFAIL 1s selected. 99 EPROM Identifier 8 A ‘The EPROM Nunber 4 3 Identifier ne. (Press push button) 2 c | 4s indicated in 1 22 binary coded 8 2B decinal form. 4 AIDED TRIP | Informacion 2 SOTF given ts 1 VVFAIL intended for GECM use. Fo CODE SELECTION cSIK 8 A [the binary NUMBER 4 3 coded decinal (ENTER FO TO 2 c form of each SOCKET 1) a 2 code switch csny 8 2B number 4 AIDED TRIP given. 2 SOTF 1 VVFAIL iOUTPUT TEST OPTIONS TABLE 7 Seo. — T TEST | OUTPUT TESTED AND SWITCH OUTPUT GIVEN ON THE REAR TERMINALS OPTION | TO BE SET TO THE RIGHT AND/OR THE MONITOR POINT BOX xo. | oot Tndication SWB | Pressing the reset SKIS | . sw7 | Button causes the SK2-24 [ re" - Sw6 voltage on the monitor SK2-23 | “22° : SWS | point box terminals SK2-22 “23° : SWs | (2 4s OV reference) to SK2-21 Lea ceR ance aerccccae SW3 | fall from 24V to zero. $K2-20 | Use high tmpedance SK2-19 | "soTr” . sw2 | voltmeter. SK2-18 | “VV FAIL” sul 1] Fault Locator A Sue CI=cz Ee . B sw7 c3-c4 : c swe | 19c-1 — c5-c6 | 28 N sws | 19E-1 — c7-c8 | Power swing timer sWs | As for 60 SK2-7 | Hysteresis sW1 | Internal 62] Signal send | SWS] 85K-1, 854-2, BI-B2, BS-Bs SKI-IT | CRX annunciate swe SK2-9 | Zone 2 trip alarm sus | 22-1 69-10 Zone 3 trip alara sw | 23-1 cil-ciz | Aided ceip alam sw3 | 9ay-1 — ci3-cia | Switch on to faule sw2 | 98-1 c1s-c16, | trip alarm | Fuse fai) alam sw | 97x-1 — cl7-c18 os] RT Su8__|Taternal | Self check sw? | Internal | “POWER SWING"indication sw6 | | Any Zl, 22, 23 sw5 | SK2-6 | Block A/R sw 96-1 B25-826 3 | Extend Zone 1 sw3 | Tnternal Power swing alarm sw2 | 95-1 c19-c20 oa Pole Dead © SW6 | Tnternal Pole Dead 5 sws | Internal Pole Dead A sw | Internal SOTF ENABLE sw3 SK2-5 Drco sw2 | Internal ENF sw | Internal oy ANY TRIP Sus | 9u-1, 94-2 _ B21-B22,BI3-B24 SKI-TL ‘TRIP 3PH swe | 94T-1,96T-2 B17-B18,B19-820 SK2-12, TRIP A sW3 | 94A-1,944-2 B5~B6,B7-B8 TRIP B sw2 | 94B-1,94B-2 B9-B10, BL1-B12 TRIP C sul | 940-1,94C-2 B13-B14,B15-B16 Note: Mo contact will close until the appropriate SW switch is to the right and the reset button is pressed.=e a POWER SWING . ® c ie 2 . RESET TEST sore ska | v~ FAIL 6 trZtma 6 ox Eme & to Eteme % torZteme OPTION SELECT x y Fig26 Nameplate details RCL103.8 See THE AUXILIARY RELAY MODULE Rvc 53 srepce caain functions of this module are to produce all the relay output contacts and to produce @ number of test signals ar the rect socket SK2 on the relay facia. These functions are illustrated an fhe right and left of the block diagram, fig 27, respectively, The eighteen auxiliary relay units contained in this module are fre rolled directly by the schene logic module. The majority of ihe contacts are single normally open type, hovever, CTi, TRIP A, TRIP 5, TRIP C, TRIP 3 PH and ANY TRIP each provide two normally ‘open contacts. The Relay Inoperative alarm contact is a single normally closed type. All contacts have the following rating: Make and carry for 0.2 s 7500 VA with maxtma of 30 A and 300 V AC or Dc. Carry continuously 5 4 AC or DC Break: AC 1250 VA ) DC 50 W resistive ) with maxima 5 A, 300 25.W L/R = 0.04 s) Fach contact is electrically {solated from all other contacts and ground to a proof voltage of 2 kV rms for 1 minute and can withstand 1 kV for 1 minute across its noraally open terminals During commissioning of the QUADRAMHO it 1s possible to inhibit the operation of the contacts in two ways. The first 1s to replace the heavy duty test plug 12 vith a plug with an open circuit on 1210. This breaks the “output relays common” connection to the relay coils, The second way 1s to connect pin 1 to pin 2 of the test Socket SK2 via a wire link. This opens the solid state switches in the module which operate the relay coils. On the diagram these elements are represented by a set of normally closed contacts Linked to pin 1 of SK2. Whenever the relays are inhibited the LED labelled “Relay Available” on the relay facia and D on the diagram, is extinguished and the Relay Inoperative alarm contact closed. This also happens when the relay is set to a test option or when an internal fault in the relay is detected by the continuous monitoring circuits. Further details of this feature are given in section 4.8.25. Etghteen of the pins on the test socket, SK2, take outputs via a buffer circuit, labelled “B” on the diagram, from the scheme logic module. Each output consists of a pull down transistor and a pull up resistor of 22K ohm. The logic levels of these outputs is either OV or + 24 V. These outputs are not inhibited with the auxiliary relay. Five other outputs are taken to the test socket via 10K ohm resistors. These are used to monitor the d.c. rails of the relay and the highest division of the master clock frequency, MCK/28« Since all the pins on the socket, except OV on pin 2, have resistors connected in series with them then it is impossible to Gamage the QUADRAMHO by inadvertently shorting together any number of pins via a wire link.- 68 - PONTTOR FacrLzTy TRIPPING FUNCTION psa a ee eon POOULE Test soceT PUTS To pce BH0739 CONNECTIONS = Ruy > 2S ————_ A INO (am —{EJS (Ske & IND or sy Ruse 24 ae i _RLa=1 > 8 NO mE Gke 8 DO Bic (PHBE) — ee ea — ze (PH) Gj SS gureur C Do Ge cre ¢ Do 22 (6) @e Ep cantncts 22 2No Gm Ke 2 OD Bs (PH) ej BS | Boras TRIP (oe | 23 No GEE Gee os (EE J : 1 —=> AT =NO Gm EH ccke. 1 too | SUTRUT . . | of ReLay Em | SELSE SOTF INO (am —BE 2 ¢sxe | COILS D feRon Pee e Le DJ bores Ino BEE CsKe FF IND TRIP 8G me 5 Re crx Gm 2 Coxe ER a [Ret > a LARD Ce ——a) 13 Bar t T ear EP xe BR 1 ov oa an. 12 5 SS ee Riot D Fro pce TRIP 3°H Gam —{BH2 Coxe TRIP SPH PSB AN Gee BHO743 a: —- . SOTF eens fey TRIP (emf Coxe aw TRIP coed es Ret 10 — Rise PSE PAN Gm —{B}? Coxe PSB AR a 9 an 1 to >| aed RX ANN Gem IE} Coxe Ca 4 oF ReLay ) | as 2 an 1 pO LED Dees nen en Ge —}E (sxe ren EN ! DJ Bere es be Rusa 1s Gm fe} Cake TPS TRIP 3G mares ai 21 22 23 mB} Ke AY Bees 7 eS ana s oR ee CONTACTS SOTF EN (am —{B}S_(sx2 SOTF EN Ae FROM PCB G 22 ee f PE ney ime siey 2 eS met : fe TRIP G Re > 120 @o eS xe -120 Ee 14 ore | RELAY out +80 @e tee sy carcurt } OF eemenoe 4 ox/28 (ot (Ske HK 28 1 G any RELAY IN 428 ee we te CIRCUIT [SERVICE we 2 x2 ov we we wG FIG. 27 AUXILIARY RELAY MODULE RUC 533.9 ~69- POWER SUPPLY UNIT ZRE 01 qhe single pcb power supply unit 1s contained vithin a ventilaced gnclosure vhich is mounted on the back of the QUADRAMHO. Tr ose’ be detached from the main relay case by renoving six screws and releasing evo plugs. Upon replacing the backpack the silicon Tubber dust sealant must be renewed. Three versions of the pover supply are available, for nominal input voltage ratings 48/54, 110/125 and 220/250 volts DC. These versions have operating ranges of 37.5 - 60, 87.5 - 137.5 and 175 Lege votts d:€+ respectively. All three versions prowuce regulated output voltage rails of + 24V, +12 Vand 5 V at a current of up to 1 A, and - 12 V at a current of up to - 0.5 A. Any output can be short-circuited for a brief time vith no resultant power supply damage. Ghe CPeration of the unit 1s now described with the ald of block diagram, fig 28:- The DC supply from the secure station battery, 1s used as a power Source for the production of the isolated smooth and regulated paternal supply rails. The OC ts firstly passed through a filtering section which attenuates electrical noise ena voltage spikes and ensures that the QUADRAMHO 1s immune to interference generated by other equipment connected to the station battery. Tt also prevents the pover supply from transmitting interference to this same equipment. The filtered voltage 1s sensed by the voltage detector and when ris exceeds a sininum value the {aternal voleage rail of the pover supply electronics ts energised. This elininates the danger of Power supply aaloperacion for input voltages less than che ainiaua operating voltages given above. The “feed forvard” principle is used in the pulse width aodulator section to produce a 40 KHz square wave with a aark to space racio (duty factor) which varies inversely with the filtered supply voltage. This ensures that the pover supply output voltages renain relatively constant despite differing or changing input supply voltages. The switching transistor ts driven “on” and “off” by the pulse width modulator to energise the primary of the transformer vith current from the filtered voltage supply. The transformer electrically tsolates the station supply from the relay electronics (2 kW for 1 minute) and transforms the primary voltage to a level suitable for the outputs. Screens are incorporated on the transformer to render the relay insensitive to common mode interference between the station battery supply and the relay case/ground. A pulsed voltage waveform is produced at each of the transformer Secondaries which are smoothed by L - C low pass filters to produce near constant DC voltages. It is then necessary to regulate fhese voltages since suall variations in them occur due to ripple, input voltage variation and load regulation. This is accomplished by the use of solid state regulator devices which also feature overcurrent and thermal overload protection. Tf ‘sone part of the power supply fails such that a large current is drawn from the station battery then a fusible resistor, connected-70- in series vith the station battery volcage supply, operates and qifsounects the battery voltage. Before replacing or repairing this device the faule resulting in its operation must be investigated.-n- WveSvId SOOT AlddnS WIMOd Be Od E Anu | . BOWBOEN YL NeBHOS zara 16092 89g W042 40 NOW IOS! HLA Jonts Hiewa A734 OL AyaLiva Nouwis4a 222 PRINCIPLES OF OPERATION THE COMPARATOR fhe important requirenents of high speed and high stability have both been satisfied in the comparator design. Usually these two tne sreaac® ate im contention because the faster the operating speed, fhe greater the risk of false operation caused by contaninated relay iuput signals. Signal contaminations include harmonic coaponents, guitching surges, lightning impulses, travelling vaves, exponential decays, saturated current transformer vaveforas, coupling capacitor voltage transformer transient errors and interference voltages Laduced on low-voltage wiring due to switching on the high-voltage systen. The compatator resolves the speed/stability contention by checking its own input signals to verify that they are dominated by componente consistent with pover-systen-frequency waveforms. If verification {s obtained, full operating speed is allowed. If verification 19 aoc obtained, the comparator demands more data before trippiag can be alloved, thereby autonatically extending the signal processing tine sufficiently to ensure that no maloperation can occur. By suttable filtering and preconditioning of the comparator input stguals, the ay design ensures that the comparator is able to operate a¢ its highest speed for the majority of transuission line faults. FUNDAMENTALS OF THE COMPARATOR The comparators in QUADRAMHO are used to produce a variety of different characteristic shapes, such as quadrilateral, aho, offset sho, lenticular ete. The easiest to explain is the mho (or circular) characteristic, so this will be described first. For simplicity describing a self-polarising characteristic, the comparator inputs are as shown in fig 29, such that A= ver B= v /-900 and the condition for operation is that A lags 8 by 0 to 180°. As the operation of the comparator must be independent of the magnitude of A and B, these two quantities are changed to square vaves using high-gain amplifiers before being supplied to the comparator. The Squared-up signals convey only the phase angle information of the original signa: The comparator treats the input square waves as logic variables vhich gan each have a high or a low logic state at any tine. To facilitace the following explanation, signal A vill be described as A or & depending on its logic state at a particular instant of time and signal 8 will be described as 3 or B. There are four possible combinations of state, A.B, A-B, A.B, and A.B. If both signals have unity aatk-space ratios and equal pertods but different phases, then the four combinations occur in a cyclic manner.-1- | [(QUADRAMHO VIZ rout outside characteristic Fault on boundary Fault inside characteristic IR Voor = V 90° Fig 29 SEQUENCE COMPARATOR VOLTAGES FOR MHO CHARACTERISTIC afrLil yp sr uty Logic states “ABABABABAB. "A BABABABAB Restrain condition Operate condition Fig 30 COMPARATOR LOGIC VARIABLES42.2 IR*FE SFe only two possible sequences of these coubinations as shown in fig 30. These are:- 1+ If signal A leads signal . 2. Tf signal 4 lags signal 8 x A +B, A.B, +B, ALB, pit A.B, KB, 2B, a AB, A.B, A.B) a From these the following logic stacesencs can be deduced. 1, Tf signal A leads signal 3, when A changes it gains the opposite state from B, while when B changes it gains the 3 signal A lags signal B, when A changes it gains the same state as B, while vhen B changes it gains the opposite scace from A. The, COnParator has a logic circuit which examines the {aput signals at gach change of state to see which of the tuo statenents is trae sad fhus deteraines vhether the sequence is progressing {a a restraie or a tripping direction, The circuit can identify the direction of the progression from a single change of logic state of either input ead from any starting point in the logic sequence. Because the presence of noise can introduce false changes of state waconnected with the true ‘signals at the pover systen frequency, « single change of state satching the trip sequence does not necessarily represent a fault condition within the protected section of line. Greater security 1s obtained if the criterion for tripping is to receive a number of successive changes of state each of which satches che tripping sequence. The comparator therefore has a counter for determining whether one, two, three or four such changes have beea observed. Each acceptable change matching the tripping sequence adds fo the total count (up to a maxizum of four) while every change patching the restrain sequence subtracts from the total count (down to a mininum of zero). The criterion for operation is a count of three. The action of the counter for a typical fault within Zone 1 is shown in fig 31. ACTION OF THE COMPARATOR COUNTER Figs. 30 and 31 show pure power-frequency signals, but it 4s obvious that the presence of noise would change the situation. To illustrate the point, fig 32 shows a restrain condition of the pover-frequency signals, with a burst of high-frequency noise superimposed on a comparator input. Because the noise happens to coincide with a change of state of the other couparator input, a count-up sitvation occure st hgh frequency. To prevent the comparator from tripping wrongly, the Fate of ccunting-up is deliberately limited, preventing a couat of Bore than one from being registered. The device for restricting the rate of counting-up is a tlaing circuit. This is initiated by any change of state which fics the tripping sequence and runs for a nominal tine period of 0.15 cycle. If another change of state in che operate sequence occurs vhile the timer {s running, the tiner is restarted. While the tier ts running, the counter cannot be incremented further. Each change of state in the Festrain sequence decrements the counter and terminates any tizing period running, so there is no restriction on the rate of counting down.ose oe Occurs 2 Counter | Fig 31 ACTION OF COUNTER IN COMPARATOR SSN UF COUNTER IN COMPARATOR4.1.3 a6 The restriction on the rate of counting-up effectively limits the operating bandwidth of the comparator, eliminating maloperation on high-frequency interference. The same restriction also preveats che possibility of transient overreach occuring when the V-I2 conparator input has an exponential offset which distorts the mark/space ratio of the square vave, as shown in fig 33. Note that the exponential component of the current does not cause a significant exponential offset in IZ, because the signal is differentiated vith a short cine constant by the current input devices (transphasors) described later. The voltage supply can have an exponential component which is reflected in V-1Z but not in Vpoy because the latter is noraally dominated by healthy-phase component: The distance relay contains a total of eighteen full comparators, that ig, three ground fault and three phase fault comparators per zone. Each full comparator contains its own logic circuits, counter, constraint timer etc. fig 34 shows a flowchart of the sequence comparator logic process. EXCLUSION OF NOISE The following interfacing and preconditioning measures ensure that the full high speed performance potential of the comparator 1s achieved even with severely contaminated relay input signals. 1. Good physical layout and electrical filtering has been used to exclude high-frequency noise generated in the substation. The relay terminals and all of the relay modules which interface with the outside world are concentrated in the right-hand side of the relay case. The interface modules provide electrical isolation to 5kV peak, using isolating transformers with screens to shunt high-frequency currents to earth and so attenuate comnon-aode interference. Transverse-mode interference is attenuated by low-pass filters. The measuring and control aodules which occupy the left-hand side of the relay case, therefore operate in a quiet electrical environment. Other high frequency signals, such as travelling-wave effects and high harmonic frequencies, are attenuated by low-pass filters which cut off at about 120Hz. 3. Exponential components of the current supply are attentuated vith a short time constant (typically less than lus) by the main current input devices of the relay, known as transphasors, described later. Tn the quadrilateral version of QUADRAMIO, current transformers are also used, together with band-pass filters to remove exponential components. Coupling capacitor voltage transformer (CVT) transients are prevented from having any effect on the polarising signal by the dominant effect of sound-phase or synchronous polarising, described later. Switched band-pass filters are used to eliminate excessive effects of CVT transients in other relay signals derived from the voltage supply.SINUSOIDAL V-IZ INPUT ] I Fig 32 i EFFECT OF V-IZ A u HIGH - FREQUENCY a os INTERFERENCE Veo. 8 t —e Ld a COUNTER of . NO SECOND UP- COUNT AS CHANGES SPACED <0-I5 CYCLE FAULT OCCURS OUTSIDE BOUNDARY OF OPERATION SINUSOIDAL asa INPUT. Fig 33 EFFECT OF EXPONENTIAL OFFSET [al LI ‘SQUARED J i ee et a COUNTER H Sees NO SECOND UP~-COUNT. AS CHANGES SPACED <0-ISCYCLEi ser no PEGISTER 1 4 ves ser = j ECISTER ? Sl, Toes 4 nenistes iio ourout ves 1 oo eee] | scien 2 es A ares sesisten 3 | ves 4 Reser acoistene Fig 34 | Flowchart of Sequence Comparator-79- 4.1.4 PEASE SHIFTING crrcurT Zo develop impedance characteristics such as the ho, the phase Lageing angina tees pedatsing quantity to be phase shitten bya 20sinE angle (see f1g 35). Because the compareras operates at high Speed 4 has been important to avoid energy Storing phase shift circuits, for instance capacitor-resistor Networks, which have poor fransient response. As the comparator deals wich square waves which pasnegenift Fegister logic circuits driven by a clock pulse generator. Each shift register introduces a time delay vhich depends on the pecven ce tastebles (or bite)lin chelcwclaces saa the cise pulse mreivency. The required clock pulee frequency depende ce the nominal W902 ia) 63 BIT SHIFT REGISTER CLOCK PULSE GENERATOR POLARISING PHASE SHIFT AG. 354.2 42d = 80- POLARISING ARRANGEMENTS To simplify the description, the mho characteristic has been described in section 4.1.1 as if it were self-polarised. In fact, partial healthy-phase cross-polarising and partial synchronous polarising components are used. The term synchronous polarising refers to an advanced digital memory system which will be described in section 2.2.2. These extra polarising components are used in order to satisfy the following requirenent: 1. To maintain a correct polarising (i.e. directional reference) signal for the relay comparators under conditions of close-up faults of all types even in the presence of large transient voltage errors from CVT's, so that correct directional response can be ensured. 2. To enable fast operating time to be obtained for close-up faults of all types in the forward direction of the relay. 3. To provide expansion of the resistive coverage of the sho for faults with low infeed currents, vhere arc resistance aay be large. Both the healthy-phase and synchronous components are square-wave signals of amplitude 16% of the peak prefault voltage supply. Under unbalanced fault conditions, the proportion of healthy-phase polarising is enough to overcome the effects of normal CVT transients. Under 3-phase faule conditions, the synchronous polarising vorks in a similar vay. Fig 36 shows that by adding a 16% square wave to the CVT error, the correct zero-crossings of the polarising voltage are restored. The polarising signal is squared-up and phase retarded by 90° to become input B of the comparator as described in section beled. The unique shapes of the partially cross-polarised aho practical polar characteristics, shown in fig 37, have been achieved by suitable choice of che wave-shape of the signals involved in the polarising mixing circuits. In conventional polarising mixing circuits all the signals are sinevaves, but in the QUADRAMHO the synchronous polarising and sound phase crose-polarising components are Square waves. The advantages of the unique polar characteristics are obtained with only one tvo-input comparator, enabling optimum operating time to be obtained. Due to the partial synchronous polarising component, the resistive expansion is maintained for 3 phase faults. The top line of the expanded characteristic is part of a fully cross-polarised circle and soves with prefault power flow $0 as to avoid overreach or underreach. Operating tines contours over the area of the characteristic are shown in fig 38. PARTIALLY CROSS-POLARISED MHO The polarising quantity, Vpo,, is formed by squaring and summing circuits supplied with the phase-ground voltages and the synchronous polarising signal. The circuits are so arranged that the effect of synchronous polarising only becomes significant when the phase-ground voltages are reduced under low voltage three-phase fault conditions. This ts explained by reference to fig 39 and 40, which show circuit details for tvo typical phases of the polarising mixing circuits.FAULT FAULTY INCIDENCE PHASE VOLTAGE CVT ERROR 16% SYNCHRONOUS POLARISING POLARISING VOLTAGE (BEFORE SQUARING AND 90° PHASE SHIFT) Fig 36 ACTION OF SYNCHRONOUS POLARISINGFig RESISTIVE EXPANSION OF PARTIALLY GROSS - POLARISED MHO = 82- FIGURES ARE S.1Rs 37 ' [se ee a fee ae) - Saas HH | { | PS SHH t iz | {I { TPT fee (esse fea = 2ims_|!30ms | TT ison tives | dm LT Tsone Tei |e Ee Fem EI \ CEH AAT { ete ey Her Fh PPT 1 oe 4 ao) en 8 MINIMUM OPERATNS TIME CONTOURS SiR = 6 FIG. 38 TYPICA L_MHO ZONE | OPERATING TIMES,-83- qeeee toeee thea a Cophaea; fig G9) che sie Vg and We aFe summed using tvo equal value resistors Ri asd R2 aad supplied SpocnesmeTting imput of a high-gain amplifier ICl: The sqeaterance Supshronous polarising voltage Vy, is potentially divided sen R3, Ra and supplied to the non inverting input. se eke aeer Walues ate chosen so that the peak value of the vavefora ere Renee imverting input is 16% of the peak value of the waveface va see ccher input wader healthy supply condicions. The squareeeese output Vkq from IC1 retains the phase information of tne zero-voleage Grossings of the sum of the input vave-forms. The phase of Vxq ts dominantly controlled by the cross-polarising signal Vg + Vo for nost L7Pes of fault, the exceptions being low-voltage three=phase acd perones ake BrC~G faults, where the synchronous polarising sisal Tua becomes the controlling quantity, : geProportion of Vkq is chen added to the self voltage V, using RS and Ré and a second high-gain amplifier IC2. The values of RS act he oof same voltage ac che input of 1C2 as 16% of che peak tive of che sidervaye Wa under healthy supply conditions. The squared outpat Yon from IC2 is phase shifted 90° by a shift register (which is ast shott in fig. 39) and the resultant signal Vpo, 1s then supplied to the fpaperacor. The phase of Vo, is dominated by input V, throughout all types of fault excepe ground fault conditions favoivitg thee ohees and three-phase faults which cause the supply to collapse. For these conditions of low V4 voltage the Vx, input predominate sortapses to less than 16% of rated ‘voltage, V, ceases to have any influence at all on the polarising signal and the comparator becones effectively fully cross-polarised. The resistive expansion of the chatacteristte for low-voltage ground faules is, therefore, auch egzonger than for a conventional partially cross-polarised sho relay. (See fig 41). The synchronous polarising also causes siailar large resistive expansion for low voltage three-phase faults. The BoC polarising aixing circuit is explained with the ald of fig. 40. Under B-C and three-phase fault conditions, Vy, has the sane phase as the memory signal Va and as explained the square-vave voltage Vx, 1s aixed with the sine-vave Va on resistors RS and RS. The values of these resistors are selected so that under a state of healthy supply voltage, the peak value of Vyq has 162 cf che effect of the peak value of Va at the input of the amplifier IC2. The resultant square wave at the output of IC3 ts phase-retarded by 90° using a ahift register to produce a square-vave Vyq. A set of resistors 29, R1O, R11, R12 are used to aix Yyq with Vg and Vo in such proportions Epae the peak value of Vxq corresponds to 16% of the peak value of Vp seege ging tUPE Of squaring amplifier IC. “The ouput Vgg¢ of Ic6 ts phase shifted through a lagging angle of 90° by a shift register (not Shown) and is then supplied to the comparator.ga srg Phase of Vonc is determined largely by the zero crossings of Varvg under all types of faule conditions except B-C, B-C-G and three=phase Stites shich cause the BC voltage to collapse. For these condicrane of low BoC voltage the Vxq input dominates the phase of che polarising seeee rg MA 18 ture is controlled by V, 1f this fault involves ene ane Therefocer sett? OF BY Vay if the faule involves all three phasece Therefore, 1£ Vg-Vc collapses below 16%, the B-C unit te effectively see croserPolarised and consequently the resistive expansion of toe iapedance characteristic is greater than for a conventional partially crose"polarised relay. Furthermore, the resistive expansion cise applies to three-phase fauits. see onbiaation of the sine-vave faulty-phase voltage vith the square whee dr eeeiarising (or synchronous polarising) voltage results ina Phase displacement of the resultant polarising signal from tes prevfault position which is different from that of a conventional partially cross~polarised sho. Fig 41 shows the relationship of the phase displacements of the faulty-phase and polarising signals for che QUADRAMHO and conventionally polarised comparators, drava for a typical fault volrage amplitude. In the QUADRAMHO the displacement of the polarising signal ts zero until the faulted phase 1s displaced by gore chan a critical angle $*, the capture angle. Once the critical angle ts exceeded, the polarising voltage phase displacenent rises linearly with the faulted-phase voltage displacenenc. The explanation for this behaviour ts shown in f1g 42 and 43. Fig. 42, shows an example of the composition of the polarising signal ta the QUADRAMHO. The faulted phased sine vave is dram here for a fault voltage of 252, displaced by 30° lagging, relative to the precfaule values. | This signal is suamed vith the square wave cross-polarising signal vhose magnitude 1s 16% of the pre-fault sine vave peak voltage. The zero crossings of the resultant signal renain in phase vith those of the cross-polarising signal, that is, a0 displaceneat from che pre-fault position. Fig 43 shows conditions siailar to fig 42, but with the faulted-phase voltage displaced by 60°. Under these conditions the Fesultant polarising signal {s displaced by about 20° from its Pre-fault position, because the faulted-phase displacenent exceeds the captive angle by this azount. When the displacement of che faulted phase voltage is just equal to the captive angle 6°, Ype 80 8 = Vooy captive angle §* = sin-l y re Provided that Vox > Vogt Tey, pos the sine-vave has no effect on the polarising signal, i 01 characteristic becomes fully cross-polarised.-85- QUADRAMHO, RO| PARTIALLY CROSS- POLARTSED SIGNAL lan= Var 0-16 Va, Fe, pe RI > ~ Ne Ve asl ]+e V; ae VA FIG. 39 A-G POLARISING MIXING CIRCUIT FEE Vea Vwa = (Va +0-16 Vka ) £900 Vy R6 > -90° Soe VA PARTIALLY CROSS-POLARISED SIGNAL VopceVe - Ve+0-16 Vina FIG 40 B-C POLARISING MIXING CIRCUITfully cross-polarised For high values of displacement of the faulty phase, the eu: ultane porartsing signal for @ conventional partially ence “polarised sho and QuaDRMnn ADAMO are asyuptotic. This meang the seare tt the ee ., — ES for a Felay with 16% sinewave crose-polarising (nee fie itr Although fig 41 is drawn for a constant fault voltage, the principles Ieealt the same for constant SIR conditions. The higher the SIR the lover the faule voltage and the larger the capture angle. Hence the relay becones progressively nore cross-polasived « the SIR rises, as Previously shown in fig 37, pote sey eePhical Rethod showing how to determine the practical polar plots aay be found in the application notes.BS | + of] = Faulted voltage m25% zs 7 4 + es | 22 j 100% Seit-poianisee s2 eiect Fo 5 ez ve 18% Sinewave i Grosmpelorsee 18% Saucrewave Crosapoicree a 190% Cross-polariseg ae 120 100 140 SISPLACEMENT OF FA ULTED-PHASE VOLTAGE 1 °LaGi RELATIVE TD PRE-FAULT POSITION 4 Fig 41 | ANGLE OF PRE-FAULT voLTAGE i CONVENTIONAL 169% PARTIALLY CROSS Fo COMPARISON OF POLARISED CHARACTERISTICS16% 16%. > 88 - ae QUADRAMHO {o) ! 1 1, I t 90° 180° 270° 360° ete. @® Fauited Phase voltage [-30°displacement] Cross-polarising voltage © @+® © Resultant Polarising (before -90" phase shift] Fig42= 89 - —> 60°! 16% } 16 %-— ] 16%, ©. J) if XT I \ { i |! | | | \! ! tl i i i! ly [Ne 2 ] L ! | i | | 90° 180° 270° 360° ete, Faulted Phase voltage [-60°displacement! Cross- polarising voltage @+® Resultant Polarising [-20°displacement] [before -90° phase shift] ORORORC) Fig 434.2.2 SYNCHRONOUS POLARISING The synchronous polarising signal 1s available for 8 cycles following a cophase close-up fault. This time is sufficient to co p the Zone 1 fe Cleared bevothee ee comdttion for a reverse fault, until the faust is cleared by other protection. In the case of a forace fault, 8 cycles 18 gore than sufficient to allow rhe QUADRAMNO eo trip and clear the fault. , _-_-,-_-=—__=_—s— Afeae Beceeg ne, S7BchFonous polarising signal Yus (see fag 36), Afcer & cycles this pover~systen-frequency signalts replaced by 0.3% shea AycPhe ints limits the directional sensitivity of the concarcecr once {the ‘synchronous polarising has expired to approximately inet ae rated voltage, for 3 phase faults. Fee pcmnchtonous polarising system is taplenented as a software control feature of the aicroprocessor in the scheme logic aodule (se and the basis of the systen is a set of 32 registers of 8 bits each, ghich may be imagined as being arranged in a carousel as shown fa fig. pes ihe carousel may be regarded as rotating anti-clockwise onder healthy live conditions on the transmission line. Phase C voltage i used as a reference signal for pre-fault phase Ssformacion, after being squared by a high gain amplifier. the length of one half cycle ts measured tn units of 179 us (che tiner interrupt period of the microprocessor schene logic) and the number of units ta stored in a register. When chis half-cycle finishes, che carousel 1a Focated anticlockwise by one register and the length of the next falfccycle measured and stored. This process continues indefiaitely, with new data overwriting the old when all 32 registers are full. To generate the synchronous polarising output signal, an examination ts sade of the data held in the 8th register anticlockwise fron the present input register. This number is then used to determine the dength of the output haif-cycle required. when the output half-cycle has been produced the polarity of the output is reversed and another examination is made of the data held in te register which {s at the present 8th position. The next half-cycle ts generated accordingly. This process is repeated indefinitely, producing the synchronous polarising output wave. This method allows the reproduction of the frequency of the input Signal Vc. The output is phase-locked with the input by effectively adjusting the oumber in the output register by plus or atnus one, every fourth output edge, to bring the output into phase with Vc as closely as possible. ‘hen any voltage level detector resets, or any comparator operates, this 1s deemed to be a faulty or dead-line condition and the memory is allowed to run out. Under these circumstances, the direction of rotation of the carousel is reversed (see fig 45) and the ourput is aaintained from data previously stored, for 16 half-cycles, after which the synchronous polarising output is disconnected from the polarising mixing circuits. The data in the most-recently recorded Tegisters are not used, because distorted voltage may be present in the period just before the voltage level detector resets, or the comparator operates. During the 16 half-cycles of memory run-out, the phase lock is disabled to protect the synchronous polarising from any vadesirable change in frequency (see also 4.8.4 note 2).-91- UADRAMHO Q ELAPSED TIME ——- INPUT fs 155 [so 35 Loe | | SYNCHRONISM CHECKED | SEVERY Im EDGE AND ADJUSTED <1 BIT ROTATION ANTICLOCKWISE FIG. 44 SYNCHRONOUS POLARISING HEALTHY LIVE LINE CONDITIONS OUTPUT) ss [56 55 | {V2 CYCLE GENERATED ‘USING “DATA OUT” FIG 45 SYNCHRONOUS POLARISING FAULTY LINE CONDITIONS4.2.3 4.2.6 = 92 - terete ee gio te 2 allowed to tize out after all voltage level SHeEneeng become operated and ali coaparacors are resce, Sets the ee -_—_——™ Eietiagia es fa ech Nesithy phase lictoraatiseamincuiaiesee 7) ERs ded BS expires, & comparison is aade between the mecseency oat Repent {pe register (equivalent to the elapsed tine of che conceng {eaufvalent to the length of the previous half-cycie). “ine difference in tine is effectively put into the ouput register, so chee when the synchronous polarising is reconnected, the output is iamediately in Phase with the input. Ar this instant of Feconnection, several cycles of ‘accurate syachronous polarising are already avatlavie ter Zone 1 Comparator operation, this being an advantage over other methods. Pasa yrchroncus polarising signals for the A and 8 phases are obtained from Wyo by phase shifting (see also 3.7.13, MFAST and LTT subroutines in 3.7.19), OFFSET MHO CHARACTERISTIC Zhe offset aho characteristic for Zone 3 is produced by the sane type of phase comparator as for Zones 1 and 2, but using different ieper quantities as shown in fig 46. fee, Ap = V-rz BL = (Vv +12) THE LENTICULAR CHARACTERISTIC An offset lenticular characteristic is available for Zone 3 for long-line applications where load impedance may encroach on to an offset who characteristic. The lenticular characteristic {s produced by the intersection of two circles as shown in fig 47. The two circles are generated by two comparators using the same signals as for 4 normal offset circular characteristic, but using different phase shifts, The inputs to the comparators then become ADs Vea ) ) comparator Cy By = (V+ IZ") ) (main comparator) AQ ve ) ) comparator Cy By = (V+ IZ") (op ) (inhivie comparator) The intersections of the tvo circles occur on the characteristic angle of the relay and determine the forvard and reverse reach of the lenticular characteristic. The reach remains independent of the comparison angles. The aspect ratio, or ratio of the length of the minor and major axes of the lenticular shape, is determined by the angle $. The aspect tatio can be set to 0.41, 0.67 and 1.00 (fig 48). The block diagram is shown in fig 49. Comparator Cy consists only of basic circuitry for determining whether changes of state of the input signals consitute an operate or a restrain sequence. There 1s no counter associated with Cz as its purpose is only to provide a signal for the inhibit terninal of the main comparator Cy. C1, therefore, only produces a trip signal for fauits withia the lenticular chatacteristic.SEQUENCE COMPARATOR VOLTAGES FOR_OFFSET MHO_ CHARACTERISTIC FIG46 (vez) A908 JIX MAIN INHIBIT COMPARATOR COMPARATOR Cl C2 FIG. 47 LENTICULAR S Wez&s CHARACTERISTIC —(y+17’Vo! 4)eae FIG 48 LENTICULAR ZONE 3 ee CONE 35 INHIBIT COMPARATOR C veiz' | PHASE PHASE FIG 49 LENTICULAR CHARACTERISTIC_BLOCK DIAGRAM-95- 4:2.5 THE QUADRILATERAL CHARACTERISTIC ee, —_-=-_===_=_,__,—_ Featicdatee Soebenat cn cefete lanl Secteauad coe ragi(ce cs Sere tat ee aeere: tines Sieh ecrong/inegedi faut g tre tstive fo coves high teyeeTtiaily crossvpolarised ahs aay aot be sersicveae Be cee eet Cotes foetten or ercund’ccucert rag iaria. Cnty 2 finele main comparator 1s needed to produce « quadrilateral Sharacteristte, thus avoiding the race problens associated with gnorgctertatics produced by muletple comparators, nc shown in [18,502 the sain comparator of Zone 1 produces she top or “reactance line of the quadrilateral from inputs: ADs ver and By os IRy, where IRy = (zRq + 18g + rag) /-3° ree rector Iw 1s obtained from the line currents by three current pransfommers supplying saall resistive burdens. The replice signals ceapeacace eg ciitered to remove exponential and high-frequency residual coreeee oeette Sized to produce an IB signal representing che ta duel Cartent component. The top line moves vith active povertlce be avoid the overreach or underreach problems associated with phase-current-polarised reactance characteristics, The oeher three sides of the Zone 1 quadrilateral are formed by three TaREPLE Goaparators, chat 1s, comparators without counter, arranged to inbsbis the cain comparator. The main comparator can oaly count ap eben the three inhibit comparators all agree that the inpedance Le within the operating zone (but see also 4.2.6). The signels used are as follows:- Ago V-IR ) right-hand “resistance” line Bp + -12, ) 43-12 ) ) left-hand “resistance” line By = verR At Iz ) ) “directional” line Be = Yeon ) Throughout, V is the faulty phase voltage, Vpor, ts the partially ctoss-polarised voltage described under “polarising mixing circetts: and 12 48 the residually-compensated vector (IpyZpy + IyZy) frou the transphasors. The IR signal for the resistance lines is derived froa the phase current only, the absence of residual conpensation Permitting good phase selection for single-pole-tripping purposes. The method of producing a quadrilateral characteristic has several advantages over other methods:~ a) independent settings for reach and resistance coverage b) relay characteristic angle can be set to line angle giving fastest operating speed for solid faults and optimea control of reach accuracy c) good operating apeed over the whole of the characteristic as shown in fig Si.- 96 - FIG. 50 QUADRILATERAL ZONE | ee EAL ZONE RN MINIMUM OPERATING TIME CONTOURS SIR=6 Fig. 51 TYPICAL QUADRILATERAL ZONE I OPERATING TIMES-97- 4.2.6 TWO-PHASE-TO-GROUND FAULTS (QUADRILATERAL CHARACTERISTIC) The operation of the quadrilaterial characteristic during two-phase-to-ground faults presents special problems. This type of fault may be measured in three ways:~ (1) operation of the corresponding phase-phase element (2) operation of the leading ground fault element (3) operation of the lagging ground fault element The operation of the phase~phase elements is practically independent of the fault resistance to ground. However, the measurement of the ground fault elements under these conditions, is affected by the resistance of the fault to ground. The effect being that the leading phase-ground element will tend to overreach and the lagging phase-ground elenent will tend to underreach. The effect of arc resistance between phase: and to ground can also have the effect of making the leading phase-ground elenent underreach and the lagging phase to ground element overreach. (See Fig. 52). The amount of overreach, or underreach, depends on the are and ground resistances, the prefault load current and the type of polarisation used for the "top" or "reactance" line. In QUADRAMHO, the polarisation of the Zone 1 reactance line is optimised for single phase faults and a technique is employed to inhibit the operation of the ground fault comparators for two=phase-to-ground faults. The phase fault comparators, with their partially cross polarised shaped characteristics, are allowed to operate on two-phase-to-ground faults. The technique used to prevent operation of the quadrilateral ground fault comparators is as follows:- The three Zone 1 ground fault comparators each have a corresponding "guard" zone, whose characteristic shape comprises the sane side and directional lines as Zone 1. The top line of the "guard" zone has twice the reach of Zone 1 and has different polarisation {Ry + IRy). The "guard" zone is generated entirely from inhibit cobparatolls and 20 its operating speed is only a fraction of a cycle. Due to the different polarisation employed for the reactance lines, under two=phase-to-ground fault conditions the reactance lines of the Zone 1 and corresponding "guard" zone tilt with respect to each other (see Figure 52), This action 1s used to advantage with the logic of figure 53 to prevent operation of the ground fault comparator. The ground fault comparators are allowed to operate if the corresponding "guard" zone, and no other, operates. For example, for the external AsB-G fault condition depicted in Fig. 52 which 1s 30% beyond Zone 1 reach setting, it can be seen that the B phase Zone 1 reach line tilts such that the measured B-G impedance appears within B-phase Zone 1 ground fault characteristic. The measured B-G impedance is also within the B-phase "guard" zone characteristic. This would cause the B-phase Zone 1 ground fault element to operate if it was not for the fact that the aeasured A-G impedance appears within the A-phase guard zone characteristic. The operation of the A-phase guard zone in conjunction with the Bephase guard zone ensures that all ground fault Zone 1 comparators are inhibited due to logic action depicted in Fig. 53.4.207 = 98 - ‘The “guard” zone system allows correct Zone 1 operation on single phase faults since the phase selection properties of the guard zone comparators ensure that only the faulty phase guard Zone comparators operate. The 2:1 ratio of the “guard” zone reach/Zone 1 reach ensures that the resistive coverage of Zone 1 is not seriously affected by any angular “droop” of the “guard” zone reactance line under load exporting conditions, caused by its non optimum polarising quantity for single phase faults. Overreach of Zones 2 and 3 under two-phase to ground fault conditions is less serious than overreach of Zone 1 and can be tolerated provided that grading problems between tine delayed Zone 2 and Zone 3 back up trips do not occur. To avoid having to provide guard zones for Zones 2 and 3, the polarising signal (IRpy + IRy) for these two zones provides a compromise between single phase and two-phase to ground fault requirements. Any consequent errors are bounded by the accuracy claims for Zones 2 and 3. THE OFFSET QUADRILATERAL The offset quadrilateral characteristic of Zone 3 is produced in a similar way to that of Zones 1 and 2, except that no directional line is involved and a further main comparator is used for the reverse reach, having vectors: As = IRpy + IRy . By = V+izt This is shown in fig 54. The outputs of the Zone 3 forvard main comparator and Zone 3 reverse main comparator are “ANDed” to obtain the complete Zone 3 characteristic shape.apparent ‘ult impedance NB apparent tilting of characteristic angle is due to residual Compensation applied whichis correct for single phase faults A-G Zonel apparent fault impedance ig O72 Behaviour for A-B-G Fault> 100 - cus 24 — g mt ZONE 16 ae |] g poms surat» { ae | 1 INMIBIT 20NE 1 8-6 rusouoe | & BOR & SuARO zone ¢ wat tec ove oeave ——er Fig53° Guard Zone Logic Al = V-IZ Bi = IRpy+IRw Ix Ac= IRpy+IRN Bs= V+IZ" FIG. 54 QUADRILATERAL ZONE 34.3 43-1 - lo = LEVEL DETECTORS Co devenergising @ transmission line, line VTs can supply one input - _-_-_== Peolacad yet? slectro-magnetic transforners are connected to she seareso de es ugrg SYOd the Fisk of false operation of the feist comparators caused by the continuing presence of synchronves pereessné om the other input of the comparators, phate corsent level sehectore are provided. These have a very fast reset tice ano ace seomected se as to block comparator operation vhen the lise te gergnersised, as shown in fig 55. The actual blocking osetacion ta Pesfomed under software control in the scheme logic module (ace 4.8.2). ee .rsts«si‘i‘C‘;COCOCOCOCOCN with the help of fig 56. If the instantaneous amplitude of the input: Repeste (Uw) exceeds a threshold setting Varp either on « perttine BER regcis oF om an inverted aegative half-cyele, a tiaer to ie Signed haa fattes nishes, before che non-toverted or the {averted iapue signe) has fallen below Vag, the input sine wave {8 known to be greater than the level detector setting and the output is set high.. cron cane, cite a6 the output is sec, a second timer tp is started, whose Purpose is to bridge the time interval between the positive and negative half-cycles. So vhile tz 1s running, the output cannoe sesgts hen the level Vagp is exceeded on the next half-cycle, the Quipue is kept i the operated state. Only if the threshold level fatls to be exceeded on the next half-cycle, is the output reset after £2 finishes, The output also resets if che tnput signal becoses aa uaidfrectional signal greater than Veep, after both ty and e) have fined out. Positive feedback is applied from output fo inpue to give § feset/operace ratio of 0.90 to prevent chatter when the input sigral ts at the pick-up level (see also 3.4). The current level detectors are designed to restrict the operative ‘nge of the relay, preventing excessive sensitivity, although because they have a low setring (5% of rated current at the relay reference setting), this restriction does not constitute any practical disadvantage. Hence the maximum SIR for ground faults {s 131 and for phase faults is 228. The operating time of the level detector circuit is fast enough not to limit the minimum operating time of the relay. The aaximum reset time of the level detector is less than the fastest practical comparator operating time. The current level detector design is such that it can only operate on signals at around the power system frequency, a characteristic which Gouplements the operating principle of the comparator. The level detector operation ts little affected by high levels of harmonic, jow frequency and exponential contamination of the power frequency input signal and therefore the input signals can be taken from before fhe bandpass filters. This eliminates the problens of stored energy slowing the level detector reset times. INHIBITION OF THE COMPARATOR With busbar VTs, the comparator returns naturally to a restrained condition when the circuit breaker is opened. However, when line WTs are used the relay must take special measures co ensure the comparators reset when the line is de-energised.