Controlling switch-node ringing in DC/DC

converters
Vijay Choudhary, Applications Engineer, Texas Instruments - February 21, 2016

The fast turn on and turn off of MOSFETs in wide-VIN DC/DC converters used in industrial,
automotive, and communication infrastructure equipment can create switch-node ringing, with
spikes exceeding the MOSFET or integrated gate-driver voltage ratings. Uncontrolled spikes can
reduce system reliability or even result in outright failure.

In this article, I cover the mechanism of switch-node ringing and spikes in DC/DC converters;
explain the origin of switch-node transient spikes in terms of MOSFET parameters, driver strength,
and parasitic elements in the circuit; discuss the implication of ringing on the limited voltage rating
of integrated gate drivers; and describe the subtle difference between buck and boost switch-node
ringing.

This paper presents different methods of controlling switch-node ringing for buck and boost power
stages, along with the pros and cons of each method. A clear understanding of the switch-node
ringing mechanism and the use of proper design techniques will enable designers to create a robust
and reliable design, saving troubleshooting and downtime at a later stage in the design process.

Introduction

DC/DC converters are moving toward higher frequencies to reduce solution size. As switching
frequency increases, DC/DC converters also employ faster power MOSFET turn on and turn off to
keep switching losses contained. But this creates steep switch-node transitions, accompanied by
switch-node ringing and spikes.

New wide-VIN DC/DC controllers and regulators are often made in integrated processes with
relatively lower voltage ratings for gate drivers. Parts rated to work with 40- to 100-V MOSFETs
have gate drivers that operate from 12 V, 8 V or even 5 V. As such, the safety margin available with
older generations of discrete drivers with 16- to 20-V ratings is reduced.

The combination of increasing switching speeds and decreasing driver-circuit voltage ratings makes
driver circuitry prone to ringing and possible damage because of switch-node spikes that can exceed
the voltage rating of the gate driver and bootstrap circuits implemented in integrated processes.
More integrated features and lower voltages are an industrywide trend and likely irreversible as
technology enables higher levels of integration and cost-effectiveness. As FET manufacturers
acknowledge this trend in integrated circuits (ICs), they are coming up with logic-level gates (4.5 V)
in MOSFETs rated for up to 100 V. Engineers designing with the new generation of DC/DC
controllers and regulators therefore need to adapt to deal with the fast transition times and low-
voltage margins in integrated gate-driver circuitry.

In this article, I explain switch-node ringing in buck and boost power stages and describe its effect
on the gate driver. I present effective methods to reduce ringing and protect gate-drive circuitry
from switch-node voltage spikes, including experimental results and the pros and cons of each
method. This article also emphasizes the importance of good layout in reducing switch-node spikes.

Switch-node ringing in buck and boost converters

The switch-node ringing in buck and boost converters is different. The switch node in a buck
converter rings the most on the switch-node rising transition coincident with the buck control (high
side) switch turn on. The switch node in a boost converter rings most on the switch-node falling
transition coincident with the boost control (low side) switch turn on. In this article, I will use the
LM5175 four-switch buck-boost converter as the test platform because the power stage consists of
both a buck leg and a boost leg.

Figure 1 shows the buck-boost power stage with synchronous buck and boost legs, which I will
consider one at a time. Figure 2 shows the buck leg with parasitic inductances and capacitances
that cause ringing.
Figure 1: The power stage of a buck-boost converter with buck (in blue) and boost (in
black) legs.
 Figure 2: The buck power stage with parasitic components shown in red and external
components shown in green.

Switch-node ringing in buck: Mechanism

Switch-node ringing in buck: Mechanism

The switch-node ringing happens in a buck converter when the high-side switch, QH1, turns on. As
the LDRV1 turns off, the inductor current starts flowing in the body diode of QL1. When the high-
side gate driver, HDRV1, starts turning on QH1, inductor current starts to transition from the low-
side body diode to the high-side switch. At this point, the parasitic inductances in series with QH1
and QL1 together will store energy from the current spike used to charge the parasitic capacitances
on the SW1 node, which includes the output capacitance of the synchronous FET. The current spike
is further increased by the extra reverse-recovery current flowing from VIN to GND. The leakage
inductances then form an LC tank circuit with the overall capacitance at SW1, causing ringing.
Figure 3 shows a typical waveform of buck switch-node (SW1) ringing when QH1 turns on.
 Figure 3: Buck switch-node ringing mechanism

Switch-node ringing in boost: Mechanism

 Figure 4: The boost power stage with parasitic components shown in red and external
components shown in green.

Switch-node ringing happens in a boost converter when the low side switch, QL2, (Figure 4) turns
on. As HDRV2 turns off, the inductor current starts flowing in the body diode of QH2. When the low-
side gate driver, LDRV2, begins to turn on QL2, inductor current starts to transition from the high-
side body diode to the low-side switch. At this point, the parasitic inductances in series with QH2
and QL2 together will store energy from the current spike used to discharge the parasitic
capacitances on the SW2 node, which includes the output capacitance of the synchronous FET. The
current spike is further increased by the extra reverse-recovery current flowing from VOUT to GND.
The leakage inductances then form an LC tank circuit, with the overall capacitance at SW2 causing
ringing. Figure 5 shows a typical waveform of boost switch-node (SW2) ringing when QL2 turns on.
Figure 5: Boost switch-node ringing mechanism. SW2 negative ringing causes the BOOT2-
SW2 voltage to exceed VCC.

Buck switch-node ringing: Implications and fix

The voltage on SW1 can spike well above the input voltage (VIN). Although this overvoltage happens
for only tens of nanoseconds, it can exceed the MOSFET drain-to-source (VDS) rating and affect
MOSFET reliability. It can also exceed the controller/driver SW1 or BOOT1 voltage rating. To avoid
damage to the controller, you can use a higher-voltage-rated FET/controller than the DC conditions
demand, or use snubbers and/or gate resistors to suppress SW1 ringing. The methods to control
buck switch-node ringing have been presented widely in literature [1].

Boost switch-node ringing: Implications and fix

The treatment of boost switch-node ringing has been sparse in literature; even when discussed,
high-side ringing has been the primary subject. As explained in the previous section, low-side
ringing is more dominant and potentially more damaging to a boost converter for two reasons. First,
low-side ringing causes the boost switch node (SW2) to swing negative (below GND). Most
integrated controllers have limited negative swing allowed on this node. Violating this pin rating due
to switch-node ringing can cause potential reliability issues. Second, low-side ringing can expose the
supply rails of the floating driver (the BOOT2 to SW2 nodes in Figure 4) to spikes beyond the rating
of the gate-driver devices.
Unlike the spikes on the high side (as shown in the buck converter example in Figure 3), you cannot
easily circumvent negative switch-node ringing issues by selecting a FET or controller with a higher
voltage rating, because a higher-voltage-rated IC does not necessarily have higher margin on the
driver circuit or a more negative switch-node rating.

Although you can apply some of the techniques in dealing with buck switch-node ringing to boost
switch-node ringing, others you cannot.

Methods of protecting against boost switch-node ringing

Methods of protecting against boost switch-node ringing

Gate resistors

Gate resistors (Figure 6) can effectively reduce the drive strength of the driver and slow down the
turn on of the control FET. A slower transition on the switch node results in lower voltage spikes and
lower ringing on the SW2 node. Figure 7 shows the reduced ringing in the presence of a gate
resistor.

The use of gate resistors is not without pitfalls. First, the slowing down of the switching event causes
extra switching losses. Second, the gate resistor can delay turn off of the control MOSFET and
increase the risk of cross-conduction between the high (synchronous)- and low (control)-side FETs.
To avoid delay in the control MOSFET turn off, a diode is often necessary, in parallel with the
resistor, for fast pull down (Figure 6).
Figure 6: Gate resistor (with a diode pull down) and snubbers can slow down the turn on of
QL2 and reduce the negative spike/ringing.
 Figure 7: A gate resistor in a boost-control FET reduces the ringing on SW2.

Snubbers

Snubbers (Figure 6) can reduce the peak of the ringing as well as damp it. Snubbers work by
damping the LC tank formed by the parasitic inductance in the switching current loop and the
output capacitance of the MOSFET. Figure 8 shows a reduction in switch-node spikes as well the
number of excursions due to a properly designed snubber. Reference [2] describes the selection of
RC snubbers for nonisolated converters.

Figure 8: Reducing SW2 node negative spikes and ringing using a well-selected snubber.

FET selection

Different MOSFET parameters can have significant impact on the frequency and peak of switch-node
ringing.

The MOSFET parameters responsible for ringing are the reverse-recovery charge of the body diode
and the output capacitance, COSS. In addition, the gate charge of the MOSFET determines the turn-on
or turn-off times of the MOSFET. A lower Qg means a faster turn off, which results in larger spikes.
Layout

The power-stage layout is one of the most important elements of a good switching-converter design.
Since parasitic inductance of the switching current loop contributes to the ringing, its minimization
is always the primary goal of DC/DC converter layout. In Figure 9, the loop area of MOSFETs QL2
and QH2, bypass capacitors COUT, and sense resistor RSENSE form the switching current path. You
should make this loop (shown in green in Figure 9) as small as possible, with thick traces on
multiple layers connecting the elements of the loop. Figure 9 shows an example layout of a buck-
boost power stage, with the high di/dt loops in buck and boost power stages highlighted.

The next most important element to optimize is the gate-driver trace length. The gate driver forward
and return traces should be thick and running together. In addition, the bootstrap bypass capacitor
should be as close to the driver IC as possible to avoid spikes across the driver BOOT and SW pins.
 Figure 9: Minimizing high di/dt switching current loops is key to minimizing the parasitic
inductance that causes switch-node ringing in buck and boost power stages.

Schottky clamp on switch nodes

An effective way to prevent the SW2 node from going negative and thus protect the gate drivers
from overvoltage across the BOOT-SW pin is to use a Schottky clamp (Figure 10). The Schottky
forward-biases when SW2 tries to swing more negative than the forward drop of the Schottky.
Figure 11 is an example of this reduction in negative spike using a Schottky clamp.

Zener clamp across BOOT-SW

A BOOT2-SW2 bypass capacitor (CBOOT2 in Figure 10) can charge above the bias voltage (VCC)
because of negative transients on SW2 (Figure 5). An effective method to prevent this overcharging
is to add a Zener clamp between BOOT2 and SW2, as shown in Figure 10. Select the Zener clamp
voltage to be slightly above the VCC regulation voltage so that it does not discharge CBOOT2 below its
nominal voltage. If the SW2 negative transients cause the CBOOT2 voltage to rise above the nominal
voltage, the Zener clamp provides a path for the extra charge to dissipate. A good place for the
Zener is close to the driver IC pins, directly across CBOOT2.
Figure 10: Ways to prevent BOOT to SW overvoltage in the integrator driver: a Zener clamp
between BOOT2 and SW2 (1); a Schottky clamp to prevent negative spikes on SW2 (2).
 Figure 11: A Schottky clamp prevents excessive negative swing on the switch node.

Conclusion

The industry trend in wide-VIN DC/DC converter ICs is to integrate gate drivers and switch faster.
Integrated gate drives have lower voltage ratings and margins than their older-generation discrete
counterparts. Power supply designers must learn new design practices to work with these lower
ratings and voltages.

In this article, I showed the causes of switch-node ringing and their implication on buck and boost
converter designs. By using gate resistors, snubbers, a Schottky clamp on the switch node, and a
Zener clamp between the driver bootstrap and switch nodes along with proper selection of FETs
and good layout practices you can effectively improve the robustness of DC/DC converters.

References

1. Controlling switch-node ringing in synchronous buck converters, Robert Taylor, Texas

Instruments Analog Applications Journal, 2Q12.
2. Ringing Reduction Techniques for NexFET High Performance MOSFETs, Texas Instruments
Application Report (SLPA010), November 2011.