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DS33M30/DS33M31/DS33M33
Ethernet Over SONET/SDH Mapper
________________________ General Description _____________________________________Features
The DS33M30 family of products provides a compact Support for EoS in One STS-3c/VC-4, EoS
and efficient solution for transporting Gigabit Ethernet Over Up to Three Concatenated STS-1/VC-3s,
traffic over OC-3/STM-1 optical networks. With the and EoPoS Over Up to Three Concatenated
addition of an optical transceiver, Ethernet PHY, DS-3s
DDR SDRAM, and host processor, a complete Two Independent 155.52Mbps SerDes Ports
solution of GbE over OC-3/STM-1 can be One 10/100/1000 IEEE 802.3 Ethernet MAC
implemented. The family supports Ethernet over Port
SONET/SDH (EoS) at VC-4, Next-Generation EoS Configurable MII/RMII/GMII MAC Interface
high-order mapping with multiple concatenated GFP/LAPS/HDLC/cHDLC Encapsulation
VC-3s, and Ethernet over PDH over SONET/SDH IEEE 802.1Q VLAN and Q-in-Q Support
(EoPoS) with up to three virtually concatenated Add/Drop OAM Frames from P Interface
DS3/E3 tributaries. The supported frame Quality of Service (QoS) Support
encapsulations include GFP-F, HDLC, cHDLC, and Traffic Policing Through CIR/CBS
X.86 (LAPS). Classification Through PCP or DSCP
Supports Up to 512Mb DDR SDRAM Buffer
_______________________________ Applications SPI and Parallel Microprocessor Interfaces
1.8V, 2.5V, 3.3V Supplies
Ethernet Service Delivery Over SONET/SDH
Multiservice Provisioning Platforms (MSPPs) Features continued in Section 1.
Transparent LAN Services
LAN Extension _________________________ Functional Diagram
DS33M30/M31/M33 1 VC-4
Advanced OAM
SERDES A
Framer A
Ethernet MAC
Traffic Mgmt
3x VC-3
High-Order
Mapper
VCAT /
LCAS
SERDES B
DS3/E3
Framer B
3 3
Framers
Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple
revisions of any device may be simultaneously available through various sales channels. For information about device
errata, go to: www.maxim-ic.com/errata. For pricing, delivery, and ordering information, please contact Maxim Direct at
1-888-629-4642, or visit Maxims website at www.maxim-ic.com.
DS33M30/M31/M33 DATA SHEET
Table of Contents
1. GENERAL DESCRIPTION AND FEATURE HIGHLIGHTS ........................................................... 4
1.1 DEVICE FEATURE OVERVIEW ........................................................................................................ 5
1.2 TDM FEATURE OVERVIEW ............................................................................................................ 6
1.3 SONET/SDH............................................................................................................................... 7
1.3.1 STS-3/STM-1 SerDes ....................................................................................................................... 7
1.3.2 STS-3/STM-1 Framer and Formatter ................................................................................................. 7
1.3.3 STS-3c/AU-4 Pointer Processing ...................................................................................................... 8
1.3.4 STS-3c SPE/VC-4 Path Termination ................................................................................................. 8
1.3.5 STS-3 Mux/Demux (DS33M31 and DS33M33 Only).......................................................................... 8
1.3.6 STS-1/AU-3/TU-3 Formatter and Framer (DS33M31 and DS33M33 Only)......................................... 9
1.3.7 STS-1/AU-3/TU-3 Pointer Processing (DS33M31 and DS33M33 only) .............................................. 9
1.3.8 STS-1/VC-3 Path Termination (DS33M31 and DS33M33 only)........................................................ 10
1.4 PDH (DS33M31 AND DS33M33 ONLY) ...................................................................................... 12
1.4.1 Add/Drop DS3/E3 Framer/Formatter (DS33M31 and DS33M33 only) .............................................. 12
1.4.2 DS3/E3 Ethernet Mapping (DS33M31 and DS33M33 only) ............................................................. 13
1.4.3 Line DS3/E3 Framer/Formatter (DS33M33 only) ............................................................................. 13
1.4.4 Loopback ........................................................................................................................................ 14
1.5 VIRTUAL CONCATENATION (VCAT) (DS33M31 AND DS33M33 ONLY) ........................................... 14
1.5.1 SONET/SDH VCAT/LCAS .............................................................................................................. 14
1.5.2 PDH VCAT/LCAS ........................................................................................................................... 15
1.6 ENCAPSULATION ........................................................................................................................ 15
1.6.1 GFP-F Encapsulation (per ITU-T G.7041) ....................................................................................... 15
1.6.2 HDLC Encapsulation ....................................................................................................................... 15
1.6.3 cHDLC Encapsulation ..................................................................................................................... 15
1.6.4 X.86 Encapsulation Support ............................................................................................................ 15
1.7 ETHERNET FEATURE OVERVIEW.................................................................................................. 15
1.7.1 Ethernet MAC Interface................................................................................................................... 16
1.7.2 Ethernet Bridging for 10/100............................................................................................................ 16
1.7.3 Ethernet Traffic Classification .......................................................................................................... 16
1.7.4 Ethernet Traffic Profiling and Policing .............................................................................................. 16
1.7.5 Ethernet Traffic Scheduling ............................................................................................................. 16
1.7.6 Ethernet Control Frame Processing................................................................................................. 16
1.7.7 Q-in-Q............................................................................................................................................. 16
1.8 SDRAM INTERFACE ................................................................................................................... 16
1.9 CLOCK RATE ADAPTER (CLAD) .................................................................................................. 16
1.10 SPI SERIAL MICROPROCESSOR FEATURES ............................................................................... 17
1.11 PARALLEL MICROPROCESSOR INTERFACE (DS33M31 AND DS33M33 ONLY) ............................. 17
1.12 TEST AND DIAGNOSTICS .......................................................................................................... 17
2. STANDARDS COMPLIANCE...................................................................................................... 18
3. APPLICATIONS .......................................................................................................................... 20
4. REVISION HISTORY ................................................................................................................... 21
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List of Figures
Figure 1-1 TDM Functional Blocks ......................................................................................................................... 6
Figure 3-1. Example Application 1: EoS for DS33M30 .......................................................................................... 20
Figure 3-2. Example Application 2: EoPoS for DS33M31 Interworking with EoP in DS33X162 Family of Devices . 20
Figure 3-3. Example Application 3: EoPoS Transport for DS33M33 with Integrated Ethernet and PDH Services... 20
List of Tables
Table 1-1. Product Selection Matrix........................................................................................................................ 5
Table 1-2. Summary of Mapping Functions ............................................................................................................ 5
Table 2-1. Standards Compliance Summary ........................................................................................................ 18
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All devices in the product family contain an Ethernet MAC port, one or two STS-3/STM-1 SerDes ports with the
LVDS/LVPECL interface, one or three GFP-F/HDLC/cHDLC/X.86 (LAPS) protocol encapsulators, one or three
higher order SONET/SDH mappers, a DDR SDRAM interface, and a local bus port for control/status. Ethernet
traffic is encapsulated with GFP-F, HDLC, cHDLC, or X.86 (LAPS) protocol to be transmitted onto the STS-3/
STM-1 interface. The family receives encapsulated Ethernet frames from the SerDes receiver interface and
transmits the de-encapsulated frames onto the Ethernet port.
With the smallest footprint, the DS33M30 contains the smallest feature set in the product family. It performs EoS
higher order mapping of Ethernet frames into a single STS-3c SPE or VC-4. The DS33M30 has one 1000Mbps
(GbE) port with GMII interface. The DS33M30 supports Ethernet OAM insert/extract capability, QoS Priority
Scheduling, VLAN processing, and committed information rate (CIR)-based policers for the delivery of carrier
Ethernet services.
The DS33M31 and DS33M33 expand on the features of the DS33M30 with additional mapping capabilities. They
support next-generation Ethernet over SONET/SDH in virtually concatenated higher order containers as well as
Ethernet-over-PDH-over-SONET/SDH (EoPoS) at the DS3/E3 level. They have an Ethernet interface that can be
configured as a 10/100Mbps MII/RMII port or a 1000Mbps (GbE) GMII port. They integrate four
mapping/demapping functions:
The DS33M33 supports all the features of the DS33M30 and DS33M31, with additional line interfaces for up to
three add/drop DS3/E3 tributaries.
The SerDes interfaces, with LVDS/LVPECL, can be seamlessly connected to commercially available optical
transceivers.
Microprocessor control can be accomplished through an 8/16-bit local bus or SPI bus. The family contains a
125MHz DDR SDRAM controller and interfaces to a 32-bit-wide 256Mb DDR SDRAM through a 16-bit data bus.
The DDR SDRAM is used to buffer data through the Ethernet and STS-3/STM-1 ports.
The power supplies consist of a 1.8V core supply, a 2.5V DDR SDRAM supply, and 3.3V I/O supply.
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10mm, 144
DS33M30 1 GbE 1 0 EoS NA Y 1 SPI
CSBGA
Note: The number of members for a VCG in the DS33M31 and DS33M33 can be 1, 2, or 3.
STS-3
SERDES Section/Line
Drop Direction to
Termination
M Encapsulated
U
X STS-3 Path Ethernet
M
STS-3 Termination
U
EoS (VC-4/STS-3c)
SERDES Section/Line (VC-4)
X
Termination STS-1 Path M
Termination EoS (VC-3/STS-1)
U
(VC-3) X Add/Drop M EoPoS
DS3/E3 DS3/E3
STS-3/STM-1 MAPPER Desync DS3/E3 U
Framer X Line
Side DS3/E3
Framer
Add Direction
B3ZS/
HDB3
line coder
Supports M23 DS3, C-bit DS3, G.751 E3, and G.832 E3 facilities
Mapping/demapping of three DS3/E3 tributaries to/from STS-3/STM-1 through STS-1 or AU-3 or TU-3/AU-4
Fully integrated and compliant DS3/E3 mapper/demapper and synchronizers/desynchronizers per
Telcordia, ANSI, and ITU standards
High speed DS3/E3/STS-1/STS-3 overhead insertion/extraction with full access to all overhead bytes
Full-featured DS3/E3/STS-1/STS-3 defect and performance monitoring (PM) support Large PM counters
for accumulation intervals up to one second
Loopback capabilities at both STS-3/STM-1 side and line DS3/E3 side
Dual STS-3/STM-1 155.52Mbps serial interfaces with receive clock recovery and transmit clock synthesis
From a single reference clock the CLAD (cLock rate adapter) generates clock references for DS3
(44.736MHz), E3 (34.368MHz), and/or STS-3/STM-1 reference (77.76/19.44MHz)
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1.3 SONET/SDH
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1.6 Encapsulation
Up to three encap/decap engines for various port configurations
1.6.1 GFP-F Encapsulation (per ITU-T G.7041)
GFP-F idle frame insertion and extraction
Null header support
cHEC-based frame delineation
X43 +1 payload scrambling and descrambling
Barker sequence scrambling and descrambling
Supports CSF frame handling
CRC-32 generation and verification
1.6.2 HDLC Encapsulation
Programmable 16/32-bit FCS insertion/extraction
Support for bit and byte stuffed operation
Programmable address/control/PID fields
Self-synchronizing X43+1 packet scrambling
Valid and invalid frame counters
Programmable inter-frame fill
Frame filtering of FCS errors
cHDLC support with SLARP extraction
1.6.3 cHDLC Encapsulation
Bit stuffing with address/control/PID/FCS fields
Programmable interframe fill length
Transparency processing
Counters: number of received valid frames and erred frames
Incoming frame discard due to FCS error, abort, or frame length longer than preset max
Default maximum frame length is associated with the maximum PDU length of MAC frame
Extract SLARP for external processor interpretation
1.6.4 X.86 Encapsulation Support
Transmit Transparency Processing
Receive rate adaptation removal
Selectable X43+1 packet scrambling
Valid and Invalid Frame counters
Frame filtering of FCS errors
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Clocks can be used for LIU, jitter attenuator, and DS3 desynchronizer reference clocks and STS-1 transmit
clocks on per port basis
Output four derived clocks for external component use, if needed
Meets jitter and wander transmission clock requirements.
Transmit (outbound) line/tributary LIU signals using internal CLAD meet Telcordia (DS3) and ITU (E3) jitter
and wander requirements
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2. Standards Compliance
The DS33M30 family of products adhere to the applicable telecommunications standards. Table 2-1 provides the
specifications and relevant sections.
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SPECIFICATION SPECIFICATION TITLE
ITU-T
G.703 11/01 Physical/Electrical Characteristics of Hierarchical Digital Interfaces
G.704 10/98 Synchronous Frame Structures Used at 1544, 6312, 2048, 8488 and 44 736 Kbit/s
Hierarchical Levels
G.707/Y.1322 Network node interface for the synchronous digital hierarchy (SDH) (10/2000)
G.751 11/88 Digital Multiplex Equipment Operating at the Third Order Bit Rate of 34,368 Kbit/s and the
Fourth Order bit Rate of 139,264 Kbit/s and Using Positive Justification
G.752 11/88 Characteristics Of Digital Multiplex Equipments Based On A Second Order Bit Rate Of 6312
Kbit/s And Using Positive Justification
G.775 11/94 Loss Of Signal (LOS) and Alarm Indication Signal (AIS) Defect Detection and Clearance
Criteria
G.783 02/04 Characteristics of synchronous digital hierarchy (SDH) equipment functional blocks
G.823 03/00 The Control of Jitter and Wander Within Digital Networks Which are Based on the 2048
Kbit/s Hierarchy
G.824 03/00 The Control of Jitter and Wander Within Digital Networks Which Are Based On The 1544
Kbit/s Hierarchy
G.825 03/00 The Control of Jitter and Wander Within Digital Networks Which Are Based On The
Synchronous Digital Hierarchy (SDH)
G.832 10/98 Transport of SDH Elements on PDH Networks Frame and Multiplexing Structures
G.7041/Y.1303 Generic Framing Procedure (GFP) (08/2005)
G.7042/Y.1305 Link Capacity Adjustment Scheme (LCAS) for Virtual Concatenated signal (03/2006)
G.7043/Y.1343 Virtual Concatenation of PDH signals (07/2004)
G.8040/Y.1340 GFP Frame Mapping into PDH (09/2005)
O.150 05/96 General Requirements for Instrumentation for Performance Measurements on Digital
Transmission Equipment
O.151 10/92 Error Performance Measuring Equipment Operating at the Primary Rate and Above
O.161 11/88 In-Service Code Violation Monitors for Digital Systems
O.162 10/92 Equipment To Perform In-Service Monitoring on 2048, 8448, 34,368 and 139,264 Kbit/s
Signals
O.171 04/97 Timing Jitter And Wander Measuring Equipment For Digital Systems Which Are Based On
The Plesiochronous Digital Hierarchy (PDH)
O.172 03/01 Timing Jitter And Wander Measuring Equipment For Digital Systems Which Are Based On
The Synchronous Digital Hierarchy (SDH)
O.181 05/02 Equipment to assess error performance on STM-N interfaces
Q.921 ISDN User-Network Interface Data Link Layer Specification (09/1997)
Y.1731 Y.1731 Ethernet OAM (05/2006)
X.86/Y.1323 Ethernet over LAPS (02/2001)
Telcordia
GR-253-CORE Synchronous Optical Network (SONET) Transport Systems: Common Generic Criteria, Issue
3, September 2000
GR-499-CORE Transport Systems Generic Requirements (TSGR): Common Requirements, Issue 2,
December 1998
GR-820-CORE Generic Digital Transmission Surveillance, Issue 1, November 1994
IEEE
802.3-2005 CSMA/CD access method and physical layer specifications.
802.1D-2004 MAC Bridge
802.1Q-2005 Virtual LANs
802.1v-2001 VLAN Classification by Protocol and port
802.1ag Ethernet OAM (extract/insert support) (draft 8.1)
IEEE Std 1149- IEEE Standard Test Access Port and Boundary-Scan Architecture, (Includes IEEE Std 1149-
1990 1993E) October 21, 1993
Other
RMII: Industry Implementation Agreement for Reduced MII Interface, Sept 1997
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3. Applications
Ethernet Service Mux over SDH (EoS)Higher Order
Ethernet Service Backhaul over PDH over SDH (EoPoS)E3/T3 STS-1/VC3
Ethernet Service Extension
Integrated Access Device (IAD)Dual Service with Data (Ethernet) and TDM (E3/DS3) Access
Ethernet Access Concentrators
MSPPs with EoS and EoP Support
Base-Station Backhaul
Microwave Radio Links
Figure 3-1. Example Application 1: EoS for DS33M30
Figure 3-2. Example Application 2: EoPoS for DS33M31 Interworking with EoP in DS33X162 Family of Devices
E/FE/ E/FE/
EoP EoPoS
GbE GbE
E3/T3 SDH STM-1 ETH
ETH DS33X11/
DS33M31
SW DS33X41 SW
1~3 LINES, ADM
1 VCG
Figure 3-3. Example Application 3: EoPoS Transport for DS33M33 with Integrated Ethernet and PDH Services
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4. Revision History
REVISION REVISION PAGES
DESCRIPTION
NUMBER DATE CHANGED
0 101508 Initial release
Removed future status in the Ordering Information table for the
1 010809 1
DS33M31 and DS33M33
Rev: 010809 21 of 21
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