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LM5165
SNVSA47A MARCH 2016 REVISED MARCH 2016
LM5165 3-V to 65-V Input, 150-mA Synchronous Buck Converter with Ultra-Low IQ
1 Features 3 Description
1 Wide Input Voltage Range of 3 V to 65 V The LM5165 is a compact, easy-to-use, 3-V to 65-V,
ultra-low IQ synchronous buck converter with high
Fixed (3.3 V, 5 V) or Adjustable Output Voltages efficiency over wide input voltage and load current
Maximum Output Current as High as 150 mA ranges. With integrated high-side and low-side power
10.5-A No Load Quiescent Current MOSFETs, up to 150-mA of output current can be
40C to 150C Junction Temperature Range delivered at fixed output voltages of 3.3 V or 5 V, or
an adjustable output. The converter is designed to
Selectable PFM or COT Mode Operation simplify implementation while providing options to
Switching Frequency as High as 600 kHz optimize the performance the target application.
Diode Emulation Mode and Pulse Skipping for Pulse Frequency Modulation (PFM) mode is selected
Ultra-High Light-Load Efficiency Performance for optimal light-load efficiency or Constant On-Time
(COT) control for nearly constant operating
Integrated 2- PMOS Buck Switch frequency. Both control schemes do not require loop
Supports 100% Duty Cycle for Low Dropout compensation while providing excellent line and load
Integrated 1- NMOS Synchronous Rectifier transient response and short PWM on-time for large
step-down conversion ratios.
Eliminates External Rectifier Diode
Programmable Current Limit Setpoint (4 Levels) The high-side p-channel MOSFET can operate at
100% duty cycle for lowest dropout voltage and does
1.223-V Internal Voltage Reference not require a bootstrap capacitor for gate drive. Also,
900-s Internal or Programmable Soft Start the current limit setpoint is adjustable to optimize
Monotonic Startup into Pre-Biased Output inductor selection for a particular output current
requirement. Selectable/adjustable startup timing
No Loop Compensation or Bootstrap Components
options include minimum delay (no soft start),
Precision Enable/Input UVLO with Hysteresis internally fixed (900 s), and externally programmable
Open-Drain Power Good Indicator soft start via an external capacitor. An open-drain
Active Slew Rate Control for Low EMI PGOOD indicator can be used for sequencing and
output voltage monitoring. The LM5165 is qualified to
Thermal Shutdown Protection with Hysteresis automotive AEC-Q100 grade 1 and is available in a
10-Lead, 3-mm x 3-mm VSON Package VSON-10 package with 0.5-mm pin pitch.
CIN
LM5165X COUT
80
Efficiency (%)
1 F EN VOUT 22 F 70
PGOOD SS 60
50
VIN = 8V
HYS ILIM VIN = 12V
VIN = 24V
40 VIN = 36V
RT GND VIN = 65V
* VOUT tracks VIN
30
if VIN < 5V 0.1 1 10 30
Output Current (mA) D101
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM5165
SNVSA47A MARCH 2016 REVISED MARCH 2016 www.ti.com
4 Revision History
Changes from Original (February 2016) to Revision A Page
Table of Contents
1 Features .................................................................. 1 7.4 Device Functional Modes........................................ 20
2 Applications ........................................................... 1 8 Applications and Implementation ...................... 21
3 Description ............................................................. 1 8.1 Application Information............................................ 21
4 Revision History..................................................... 2 8.2 Typical Applications ................................................ 21
5 Pin Configuration and Functions ......................... 4 9 Power Supply Recommendations...................... 35
6 Specifications......................................................... 5 10 PCB Layout .......................................................... 35
6.1 Absolute Maximum Ratings ...................................... 5 10.1 Layout Guidelines ................................................. 35
6.2 ESD Ratings.............................................................. 5 10.2 Layout Example .................................................... 36
6.3 Recommended Operating Conditions....................... 6 11 Device and Documentation Support ................. 38
6.4 Thermal Information .................................................. 6 11.1 Device Support .................................................... 38
6.5 Electrical Characteristics........................................... 6 11.2 Documentation Support ........................................ 38
6.6 Switching Characteristics .......................................... 7 11.3 Community Resources.......................................... 38
6.7 Typical Characteristics .............................................. 8 11.4 Trademarks ........................................................... 38
7 Detailed Description ............................................ 13 11.5 Electrostatic Discharge Caution ............................ 38
7.1 Overview ................................................................. 13 11.6 Glossary ................................................................ 38
7.2 Functional Block Diagram ....................................... 13 12 Mechanical, Packaging, and Orderable
7.3 Feature Description................................................. 14 Information ........................................................... 38
(1) For the most current package and ordering information, see the Package Option Addendum at the end
of this document, or refer to the TI website.
(2) Package drawings, thermal data and symbolization are available at www.ti.com/packaging.
DRC Package
10-Pin VSON with Exposed Thermal Pad
Top View
SW 1 10 GND SW 1 10 GND
SS 4 7 EN SS 4 7 EN
RT 5 6 PGOOD RT 5 6 PGOOD
Pin Functions
PIN
I/O (1) DESCRIPTION
NAME NO.
Switching node that is internally connected to the drain of the high-side PMOS buck switch and the drain of
SW 1 P
the low-side NMOS synchronous rectifier. Connect to the switching side of the power inductor.
Regulator supply input pin to high-side power MOSFET and internal bias rail LDO. Connect to input supply
VIN 2 P
and input capacitor CIN. Path from VIN to the input capacitor must be as short as possible.
Programming pin for current limit. Connecting the appropriate resistor from ILIM to GND selects one of four
ILIM 3 I
pre-set current limit options. Short ILIM to GND for the maximum current setting.
Programming pin for the soft-start time. If a 100-k resistor is connected from SS to GND, the internal soft-
start circuit is disabled and the FB comparator reference steps immediately from zero to full value when the
SS 4 I regulator is enabled by the EN input. If the SS pin is left open, the internal soft-start circuit ramps the FB
reference from zero to full value in 900 s. If an appropriate capacitance is connected to the SS pin, the
soft-start time can be programmed as required.
Mode selection and on-time programming pin for Constant On-Time (COT) control. Short RT to GND to
RT 5 I select PFM (pulse frequency modulation) operation. Connect a resistor from RT to GND to program the on-
time, which sets the switching frequency for COT.
Power Good output flag pin. PGOOD is connected to the drain of an NFET that holds the pin low when
PGOOD 6 O either FB or VOUT is below the regulation target. Use a pull-up resistor of 10 k to 100 k to the system
voltage rail or VOUT (no higher than 12 V).
Input pin of the precision enable / UVLO comparator. The converter is enabled when the EN voltage is
EN 7 I
greater than 1.212V.
Feedback input to voltage regulation loop. The VOUT pin connects the internal feedback resistor divider to
the regulator output voltage for fixed 3.3V and 5V options. The FB pin connects the internal feedback
VOUT/FB 8 I
comparator to an external resistor divider for the adjustable output voltage option. The FB comparator
reference voltage is nominally 1.223V.
Drain of an internal NFET that is turned off when the EN input is greater than the EN threshold. An external
HYS 9 O
resistor from HYS to the EN pin UVLO resistor divider programs the input UVLO hysteresis voltage.
GND 10 G Regulator ground return.
Exposed pad. Connect to the GND pin and system ground on PCB. Path to CIN must be as short as
PAD - P
possible.
6 Specifications
6.1 Absolute Maximum Ratings (1) (2)
Over the recommended operating junction temperature range of 40C to 150C (unless otherwise noted). (1)
PARAMETER MIN MAX UNIT
VIN to GND 0.3 68
EN to GND 0.3 VIN + 0.3
0.7 VIN + 0.3
SW to GND
20-ns transient 3 V
(3)
PGOOD, VOUT to GND Survives short to automotive battery voltage 0.3 16
HYS to GND 0.3 7
ILIM, SS, RT, FB (4) to GND 0.3 3.6
TJ Maximum junction temperature (5) 40 150 C
Tstg Storage temperature range 55 150 C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions may affect device reliability.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
(3) Fixed output versions.
(4) Adjustable output version.
(5) High junction temperatures degrade operating lifetime. Operating lifetime is derated for junction temperatures greater than 125C.
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(1) Operating Ratings are conditions under which the device is intended to be functional. For specifications and test conditions, see
Electrical Characteristics.
(2) High junction temperatures degrade operating lifetimes. Operating lifetime is derated for junction temperatures greater than 125C.
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(1) All hot and cold limits are specified by correlating the electrical characteristics to process and temperature variations and applying
statistical process control.
(2) The junction temperature (TJ in C) is calculated from the ambient temperature (TA in C) and power dissipation (PD in Watts) as follows:
TJ = TA + (PD JA) where JA (in C/W) is the package thermal impedance provided in the Thermal Information section.
6 Submit Documentation Feedback Copyright 2016, Texas Instruments Incorporated
100 100
90 90
80 80
Efficiency (%)
Efficiency (%)
70 70
60 60
50
VIN = 8V 50
VIN = 8V
VIN = 12V VIN = 12V
VIN = 24V VIN = 24V
40 VIN = 36V 40 VIN = 36V
VIN = 65V VIN = 65V
30 30
0.1 1 10 30 0.1 1 10 100 150
Output Current (mA) D101 Output Current (mA) D102
5-V, 25-mA Design LF = 470 H FSW(nom) = 100 kHz See schematic, LF = 220 H FSW(nom) = 230 kHz
COUT = 47 F RILIM 100 k Figure 37 COUT = 22 F RRT = 133 k
Figure 1. Converter Efficiency: 5 V, 25 mA, PFM Figure 2. Converter Efficiency: 5 V, 150 mA, COT
100 100
90 90
80 80
Efficiency (%)
Efficiency (%)
70 70
60 60
50
VIN = 8V 50
VIN = 8V
VIN = 12V VIN = 12V
VIN = 24V VIN = 24V
40 VIN = 36V 40 VIN = 36V
VIN = 65V VIN = 65V
30 30
0.1 1 10 50 0.1 1 10 100 150
Output Current (mA) D103 Output Current (mA) D104
See schematic, LF = 47 H FSW(nom) = 350 kHz See schematic, LF = 150 H FSW(nom) = 160 kHz
Figure 50 COUT = 10 F RILIM = 56.2 k Figure 62 COUT = 22 F RRT = 121 k
Figure 3. Converter Efficiency: 3.3 V, 50 mA, PFM Figure 4. Converter Efficiency: 3.3 V, 150 mA, COT
100 100
90 90
80 80
Efficiency (%)
Efficiency (%)
70 70
60 60
50
VIN = 18V 50
VIN = 24V VIN = 24V
VIN = 36V VIN = 36V
40 VIN = 48V 40 VIN = 48V
VIN = 65V VIN = 65V
30 30
0.1 1 10 75 0.1 1 10 100 150
Output Current (mA) D105 Output Current (mA) D106
See schematic, LF = 47 H FSW(nom) = 500 kHz See schematic, LF = 150 H FSW(nom) = 600 kHz
Figure 57 COUT = 10 F RILIM = 24.9 k Figure 65 COUT = 10 F RRT = 143 k
Figure 5. Converter Efficiency: 12 V, 75 mA, PFM Figure 6. Converter Efficiency: 15 V, 150 mA, COT
3.5
3 1.5
2.5
RDSon (:)
RDSon (:)
2 1
1.5
1 0.5
0.5
40C 25C 150C 40C 25C 150C
0 0
0 10 20 30 40 50 60 70 0 10 20 30 40 50 60 70
Input Voltage (V) D001
Input Voltage (V) D002
Figure 7. High-Side MOSFET On-state Resistance vs Input Figure 8. Low-Side MOSFET On-state Resistance vs Input
Voltage Voltage
1.24 1.25
1.245
1.22
FB Regulation Thresholds (V)
1.24
1.2
EN Thresholds (V)
1.235
1.18 1.23
1.16 1.225
1.22
1.14
1.215
1.12 Rising Rising
1.21
Falling Falling
1.1 1.205
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
Temperature (C) D004
Temperature (C) D005
Figure 9. Enable Threshold Voltage vs Temperature Figure 10. Feedback Comparator Voltage vs Temperature
5.08 3.36
5.06
VOUT Regulation Thresholds (V)
3.34
5.04
5.02 3.32
5
3.3
4.98
4.96 3.28
4.94
3.26
4.92 Rising Rising
Falling Falling
4.9 3.24
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
Temperature (C) D007
Temperature (C) D006
LM5165X LM5165Y
Figure 11. VOUT Regulation Thresholds vs Temperature Figure 12. VOUT Regulation Thresholds vs Temperature
94
250
93
92
200
91
90 150
89
100
88
87
50
86 FB Rising 60 mA 180 mA
FB Falling 120 mA 240 mA
85 0
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
Temperature (C) D008
Temperature (C) D009
Figure 13. PGOOD Thresholds vs Temperature Figure 14. Peak Current Limits vs Temperature
300 150
250
125
Pull Down Resistance (:)
Current Limit (mA)
200
100
150
75
100
50
50
60 mA 180 mA
120 mA 240 mA
0 25
0 10 20 30 40 50 60 70 -50 -25 0 25 50 75 100 125 150
Input Voltage (V) Temperature (C) D011
D010
Figure 15. Peak Current Limits vs Input Voltage Figure 16. PGOOD and HYS Pulldown RDS(on) vs
Temperature
4 3
RT = 16 k:
3.5 RT = 75 k:
2.8
VIN UVLO Thresholds (V)
3
One-Shot Time (s)
2.5 2.6
2
2.4
1.5
1
2.2
0.5 Rising
Falling
0 2
0 10 20 30 40 50 60 70 -50 -25 0 25 50 75 100 125 150
Input Voltagae (V) Temperature (C) D013
D012
Figure 17. COT One-shot Timer TON vs Input Voltage Figure 18. Internal VIN UVLO Voltage vs Temperature
10
15
8
Current (PA)
Current (PA)
10 6
4
5
2
Sleep Sleep
Shutdown Shutdown
0 0
-50 -25 0 25 50 75 100 125 150 0 10 20 30 40 50 60 70
Temperature (C) D014
Input Voltage (V) D015
Figure 19. VIN Sleep and Shutdown Supply Current vs Figure 20. VIN Sleep and Shutdown Supply Current vs Input
Temperature Voltage
400 350
350 300
300
250
250
Current (PA)
Current (PA)
200
200
150
150
100
100
50 COT 50 COT
PFM PFM
0 0
-50 -25 0 25 50 75 100 125 150 0 10 20 30 40 50 60 70
Temperature (C) D016
Input Voltage (V) D017
RRT = 75 k RRT = 75 k
Figure 21. VIN Active Mode Supply Current vs Temperature Figure 22. VIN Active Mode Supply Current vs Input Voltage
VOUT
100 mV/DIV
VOUT
100 mV/DIV
IL
50 mA/DIV
VSW
5 V/DIV
VSW
5 V/DIV
IL
2 Ps/DIV 200 mA/DIV 20 ms/DIV
Figure 23. Full Load Switching Waveforms, COT Figure 24. No Load Switching Waveforms, COT
IL 200 mA/DIV
VIN 5 V/DIV
VOUT 1 V/DIV
Figure 25. Full Load Startup, COT Figure 26. Short Circuit, COT
IL
20 mA/DIV IL 20 mA/DIV
VSW 10 V/DIV
2 ms/DIV 20 ms/DIV
Figure 27. Full Load Switching Waveforms, PFM Figure 28. No Load Switching Waveforms, PFM
VOUT 1 V/DIV
IOUT 50 mA/DIV
VSW 10 V/DIV
Figure 29. Full Load Startup, PFM Figure 30. Short Circuit, PFM
7 Detailed Description
7.1 Overview
The LM5165 converter is an easy-to-use synchronous buck DC/DC regulator that operates from a 3-V to 65-V
supply voltage. The device is intended for step-down conversions from 3.3-V, 5-V, 12-V, 24-V, and 48-V
unregulated, semi-regulated and fully-regulated supply rails. With integrated high-side and low-side power
MOSFETs, the LM5165 delivers up to 150-mA DC load current with high efficiency and ultra-low input quiescent
current in a very small solution size. Designed for simple implementation, a choice of operating modes offers
flexibility to optimize its usage according to the target application. In constant on-time (COT) mode of operation,
ideal for low-noise, high current, fast load transient requirements, the device operates with predictive on-time
switching pulse. A quasi-fixed switching frequency over the input voltage range is achieved by using an input
voltage feedforward to set the on-time. Alternatively, pulse frequency modulation (PFM) mode, complemented by
an adjustable peak current limit, achieves exceptional light-load efficiency performance. Control loop
compensation is not required with either operating mode, reducing design time and external component count.
The LM5165 incorporates other features for comprehensive system requirements, including an open-drain Power
Good circuit for power-rail sequencing and fault reporting, internally-fixed or externally-adjustable soft-start,
monotonic startup into prebiased loads, precision enable with customizable hysteresis for programmable line
undervoltage lockout (UVLO), adjustable cycle-by-cycle current limit for optimal inductor sizing, and thermal
shutdown with automatic recovery. These features enable a flexible and easy-to-use platform for a wide range of
applications. The pin arrangement is designed for simple PCB Layout, requiring only a few external components.
IN
VIN LDO BIAS
VDD
LM5165
REGULATOR
VDD UVLO THERMAL
EN VIN UVLO SHUTDOWN
1.212V
1.144V
I-LIMIT ILIM
HYS
ADJUST
ENABLE
CURRENT VIN
LIMIT
+
ON-TIME
ONE SHOT SW
Control OUT
Logic
VIN
ZERO CROSS
DETECT
VOUT/FB
+
HYSTERETIC
RT MODE ZC
R1(1)
FEEDBACK
R2(1)
+
GND
ENABLE
VOLTAGE
PGOOD
REFERENCE 1.223V UV PG
REFERENCE
SS SOFT-START
1.150V
1.064V
Note:
(1) R1, R2 are implemented in the fixed output voltage versions only.
(a) (b)
Figure 31. PFM Mode Converter Schematics: (a) Fixed Output Voltage of 5 V or 3.3 V, (b) Adjustable
Output Voltage with Programmable Soft Start, Current Limit and UVLO
(a) (b)
Figure 32. COT Mode Converter Schematics: (a) Fixed Output Voltage of 5 V or 3.3 V, (b) Adjustable
Output Voltage with Programmable Soft Start, Current Limit and UVLO
The LM5165 operates in PFM mode when RT is shorted to GND. Configured as such, the LM5165 behaves as a
hysteretic voltage regulator operating in boundary conduction mode, controlling the output voltage within upper
and lower hysteresis levels according to the PFM feedback comparator hysteresis of 10 mV. Figure 33 is a
representation of the relevant output voltage and inductor current waveforms. The LM5165 provides the required
switching pulses to recharge the output capacitor, followed by a sleep period where most of the internal circuits
are shut off. The load current is supported by the output capacitor during this time, and the LM5165 current
consumption approaches the sleep quiescent current of 10.5 A. The sleep period duration depends on load
current and output capacitance.
VIN
SW
Voltage VOUT
VREF = 1.233V
FB 10mV
Voltage
(internal)
ILIM
Inductor
Current IOUT2
IOUT1
t
When operating in PFM mode at given input and output voltages, the chosen filter inductance dictates the PFM
pulse frequency as
VOUT VOUT
FSW(PFM) 1
LF IPK(PFM) VIN (1)
where IPK(PFM) corresponds to one of the four programmable levels for peak limit of inductor current. See the
Adjustable Current Limit section for more detail.
Configured in COT mode, the LM5165 based converter turns on the high-side MOSFET with on-time inversely
proportional to VIN to operate with essentially fixed switching frequency when in continuous conduction mode
(CCM). Diode emulation mode (DEM) prevents negative inductor current, and pulse skipping maintains highest
efficiency at light load currents by decreasing the effective switching frequency. The COT-controlled LM5165
waveforms in CCM and DEM are represented in Figure 34. The PWM on-time is set by resistor RRT connected
from RT to GND as shown in Figure 32. The control loop maintains a constant output voltage by adjusting the
PWM off-time.
VIN
SW Extended
Voltage VOUT On-Time
FB
Voltage VREF 4 mV
(internal)
Inductor
DCM IOUT2
Operation
Current CCM
IOUT1 Operation t
The required on-time adjust resistance for a particular frequency is given in Equation 2 and tabulated in Table 1.
The maximum programmable on-time is 15 s.
VOUT V 104
RRT k:
FSW kHz 1.6 (2)
Table 1. On-Time Adjust Resistance (E96 EIA Values) for Various Switching
Frequencies and Output Voltages
RRT (k)
FSW (kHz)
VOUT = 1.8 V VOUT = 3.3 V VOUT = 5 V VOUT = 12 V
100 113 205 316 750
200 56.2 105 154 374
300 37.3 68.1 105 249
400 28 51.1 78.7 187
500 23.2 41.2 61.9 150
600 20 34 52.3 124
The choice of control mode and switching frequency requires a compromise between conversion efficiency,
quiescent current, and passive component size. Lower switching frequency implies reduced switching losses
(including gate charge losses, transition losses, etc.) and higher overall efficiency. Higher switching frequency, on
the other hand, implies a smaller LC output filter and hence a more compact design. Lower inductance also
helps transient response as the large-signal slew rate of inductor current increases. The ideal switching
frequency in a given application is a tradeoff and thus is determined on a case-by-case basis. It relates to the
input voltage, output voltage, most frequent load current level(s), external component choices, and circuit size
requirement. At light loads, the PFM converter has a relatively longer sleep time interval and thus operates with
lower input quiescent current and higher efficiency.
Note that in PFM mode, the inductor current ramps from zero to the chosen peak threshold every switching
cycle. Consequently, the maximum output current is equal to half the peak inductor current. Meanwhile, the
corresponding output current capability in COT mode is higher as the ripple current is determined by the input
and output voltage and the chosen inductance.
(a) (b)
Figure 35. Programmable Input Voltage UVLO with (a) Fixed Hysteresis, (b) Adjustable Hysteresis
Use Equation 6 and Equation 7 to calculate the input UVLO voltages turn-on and turn-off voltages, respectively.
RUV1
VIN(on) 1.212V 1
RUV2 (6)
RUV1
VIN(off) 1.144V 1
RUV2 RHYS (7)
There is also a low IQ shutdown mode when EN is pulled below a base-emitter voltage drop (approximately 0.6 V
at room temperature). If EN is below this hard shutdown threshold, the internal LDO regulator powers off and the
internal bias supply rail collapses, shutting down the bias currents of the LM5165. The LM5165 operates in
standby mode when the EN voltage is between the hard shutdown and precision enable thresholds.
VIN(on) = 4.50 V
VIN(off) = 3.15 V
RUV1
1M VOUT(MASTER) = 2.5 V VOUT(SLAVE) = 1.5 V
LM5165 LM5165
7 EN 7 EN
RUV2 PGOOD 6 RFB1 RPGOOD PGOOD 6 RFB3
365 k 105 k 10 k 22.6 k
9 HYS 9 HYS
FB 8 1.223 V FB 8 1.223 V
RHYS
200 k
RFB2 RFB4
100 k 100 k
Regulator #1 Regulator #2
Startup based on Sequential Startup
Input Voltage UVLO based on PGOOD
When the FB voltage exceeds 94% of the internal reference VREF1, the internal PGOOD switch turns off and
PGOOD can be pulled high by the external pull-up. If the FB voltage falls below 87% of VREF1, the internal
PGOOD switch turns on, and PGOOD is pulled low to indicate that the output voltage is out of regulation. The
rising edge of PGOOD has a built-in deglitch delay of 5 s.
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TIs customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
U1 LF
220 H
VOUT = 5 V
VIN = 5 V...65 V VIN SW
IOUT = 150 mA
LM5165X RESR
CIN
EN VOUT 1.5 :
1 F
HYS SS COUT
22 F
CSS
RT ILIM
RRT 47 nF
133 k: PGOOD GND
Figure 37. Schematic for Design 1 with VIN(nom) = 12 V, VOUT = 5 V, IOUT(max) = 150 mA, FSW(nom) = 230 kHz
Check the inductor datasheet to ensure that the inductor's saturation current is well above the current limit setting
of a particular design. Ferrite designs have low core loss and are preferred at high switching frequencies, so
design goals can then concentrate on copper loss and preventing saturation. However, ferrite core materials
exhibit a hard saturation characteristic the inductance collapses abruptly when the saturation current is
exceeded. This results in an abrupt increase in inductor ripple current, higher output voltage ripple, not to
mention reduced efficiency and compromised reliability. Note that inductor saturation current generally deceases
as the core temperature increases.
100 5.1
90
80
5.05
70
5
60
50
VIN = 8V
VIN = 12V 4.95
VIN = 24V
40 VIN = 36V VIN = 12V
VIN = 65V VIN = 24V
30 4.9
0.1 1 10 100 150
Output Current (mA) D102 0 25 50 75 100 125 150
Output Current (mA)
VOUT = 5 V
60
VOUT 100 mV/DIV
CISPR22
50
40
30
Peak detector
20
10
VSW 5 V/DIV
Average detector
-10
Start 150 kHz Stop 30 MHz 20 ms/DIV
VIN = 13.5 V LIN = 22 H
IOUT = 100 mA CIN(EXT) = 10 F VIN = 12 V IOUT = 0 mA
Figure 40. EMI Plot CISPR 22 Filtered Emissions Figure 41. SW Node and Output Ripple Voltage, No Load
VSW 2 V/DIV
Figure 42. SW Node and Output Ripple Voltage, Full Load Figure 43. SW Node and Output Ripple Voltage Showing
Frequency Foldback Near Dropout
VEN 1 V/DIV
IOUT 50 mA/DIV
IOUT 50 mA/DIV
2 ms/DIV 2 ms/DIV
Figure 44. Startup, Full Load Figure 45. Enable ON and OFF
IOUT 50 mA/DIV
IOUT 50 mA/DIV
4 ms/DIV 4 ms/DIV
Figure 46. Dropout Performance, 75-mA Resistive Load Figure 47. Dropout Performance, 150-mA Resistive Load
IOUT 50 mA/DIV
IL 50 mA/DIV
VOUT 2 V/DIV
Figure 48. Load Transient, 50 mA to 150 mA, 1 A/s Figure 49. Input Transient (Automotive Cold Crank Profile)
U1 LF
47 H
VOUT = 3.3 V
VIN = 3.5 V...65 V VIN SW
IOUT = 50 mA
LM5165Y
CIN COUT
EN VOUT
1 F 10 F
HYS SS
PGOOD ILIM
RILIM
RT GND 56.2 k:
Figure 50. Schematic for Design 2 with VIN(nom) = 12 V, VOUT = 3.3 V, IOUT(max) = 50 mA, FSW(nom) = 350 kHz
IPK(PFM) in this example is the peak current limit setting of 120 mA plus an additional 10% margin added to
include the effect of the 100-ns peak current comparator delay. An additional constraint on the inductance is the
180-ns minimum on-time of the high-side MOSFET. Therefore, in order to keep the inductor current well
controlled, choose an inductance that is larger than LF(min) using Equation 20 where VIN(max) is the maximum input
supply voltage for the application, tON(min) is 180 ns, and IL(max) is the maximum allowed peak inductor current.
VIN(max) t ON(min)
LF(min)
IL(max) (20)
Choose an inductor with saturation current rating above the peak current limit setting, and allow for derating of
the saturation current at the highest expected operating temperature.
100
80
Efficiency (%)
70
VSW 5 V/DIV
60
50
VIN = 8V
VIN = 12V
VIN = 24V
40 VIN = 36V
VIN = 65V
30
0.1 1 10 50
Output Current (mA) D103 10 Ps/DIV
VOUT = 3.3 V
VIN = 12 V IOUT = 50 mA
Figure 51. Efficiency
Figure 52. SW Node and Output Ripple Voltage, Full Load
IOUT 20 mA/DIV
IOUT 20 mA/DIV
1 ms/DIV 1 ms/DIV
Figure 53. Startup, Full Load Figure 54. Enable ON and OFF
VIN 2 V/DIV
VOUT 100 mV/DIV
VOUT 1 V/DIV
IOUT 20 mA/DIV
VIN = 12 V IOUT = 50 mA
Figure 55. Load Transient, 0 mA to 50 mA, 1 A/s Figure 56. Input Voltage Transient (Automotive Cold Crank
Profile)
Figure 57. Schematic for Design 3 with VIN(nom) = 24 V, VOUT = 12 V, IOUT(max) = 75 mA, FSW(nom) = 500 kHz
100
VOUT 2 V/DIV
90
VIN 5 V/DIV
80
Efficiency (%)
70 IOUT 20 mA/DIV
60
50
VIN = 18V
VIN = 24V
VIN = 36V
40 VIN = 48V
VIN = 65V
30
0.1 1 10 75 1 ms/DIV
Output Current (mA) D105
VSW 10 V/DIV
Figure 60. SW Node and Output Ripple Voltage, Full Load Figure 61. SW Node and Output Ripple Voltage, No Load
U1 LF
150 H
VOUT = 3.3 V *
VIN = 3 V...65 V VIN SW
IOUT = 150 mA
LM5165Y RESR
CIN
EN VOUT 0.5 :
1 F
HYS SS COUT
22 F
CSS
RT ILIM
RRT 33 nF
121 k: PGOOD GND
* VOUT tracks VIN if VIN d 3.3V
Figure 62. Schematic for Design 4 with VIN(nom) = 24 V, VOUT = 3.3 V, IOUT(max) = 150 mA, FSW(nom) = 160 kHz
100
80
Efficiency (%)
70
60
50
VIN = 8V
VIN = 12V
VIN = 24V
40 VIN = 36V
VIN = 65V
VSW 5 V/DIV 4 Ps/DIV
30
0.1 1 10 100 150 VIN = 24 V IOUT = 150 mA
Output Current (mA) D104
Figure 63. Efficiency Figure 64. SW Node and Output Ripple Voltages, Full Load
Figure 65. Schematic for Design 5 with VIN(nom) = 36 V, VOUT = 15 V, IOUT(max) = 150 mA, FSW(nom) = 600 kHz
100
90
80
Efficiency (%)
VIN 10 V/DIV
70
60
VOUT 5 V/DIV
50
VIN = 24V
VIN = 36V IOUT 100 mA/DIV
40 VIN = 48V
VIN = 65V
30
0.1 1 10 100 150 2 ms/DIV
Output Current (mA) D106
Figure 68. SW Node and Output Ripple Voltage, Full Load Figure 69. SW Node and Output Ripple Voltage, No Load
VEN 1 V/DIV
VIN 10 V/DIV
VIN = 36 V VIN = 36 V
Figure 70. Enable ON and OFF Figure 71. Short Circuit Recovery
10 PCB Layout
The performance of any switching converter depends as much upon PCB layout as it does the component
selection. The following guidelines are provided to assist with designing a PCB with the best power conversion
performance, thermal performance, and minimized generation of unwanted EMI.
VIN
VIN
2 CIN
LM5165
High
High-side di/dt
PMOS loop
Q1
gate driver LF
SW
1 VOUT
COUT
Low-side Q2
NMOS
gate driver
GND
10 GND
Figure 72. Synchronous Buck Converter with Power Stage Critical Switching Loop
The input capacitor provides the primary path for the high di/dt components of the high-side MOSFET's current.
Placing a ceramic capacitor as close as possible to the VIN and GND pins is the key to EMI reduction. Keep the
trace connecting SW to the inductor as short as possible and just wide enough to carry the load current without
excessive heating. Use short, thick traces or copper pours (shapes) for current conduction path to minimize
parasitic resistance. Place the output capacitor close to the VOUT side of the inductor, and connect the capacitor's
return terminal to the LM5165's GND pin and exposed PAD.
GND
connection
Short SW node
trace routed RESR
underneath LF
VIN VOUT
connection connection
CIN COUT
Connect ceramic
SW via RFB2 RFB1 CFF RPG
input cap close to
VIN and GND
RUV1
RILIM
EN RUV2
PGOOD
connection
CSS connection
RRT RHYS
11.4 Trademarks
E2E is a trademark of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
www.ti.com 30-Mar-2016
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
LM5165DRCR ACTIVE VSON DRC 10 3000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 150 5165
& no Sb/Br)
LM5165DRCT ACTIVE VSON DRC 10 250 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 150 5165
& no Sb/Br)
LM5165XDRCR ACTIVE VSON DRC 10 3000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 150 5165X
& no Sb/Br)
LM5165XDRCT ACTIVE VSON DRC 10 250 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 150 5165X
& no Sb/Br)
LM5165YDRCR ACTIVE VSON DRC 10 3000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 150 5165Y
& no Sb/Br)
LM5165YDRCT ACTIVE VSON DRC 10 250 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 150 5165Y
& no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 30-Mar-2016
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Automotive: LM5165-Q1
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Jun-2016
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Jun-2016
Pack Materials-Page 2
www.ti.com
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