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Clock
The proposed ANN-SPBC system.
25NMz
Fig. 3.
Coute
8bit
D(k) >
Comparator
8bit_
M-I
14
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Macrocells
Used
106/384
(280%)
X/XS
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Math
::
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2
2001nc
::
20
5
W
1
Pterms
Used
196/1344
(150%)
am
IW
Table III
FPGA Resources summary
Registers
::
Used
96/384
(250%)
Pins
Used
74/118
(630%)
W ;.. 14.
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:::
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(a)
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Function Block
Inputs Used
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197/960
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P=4W!
DIV
V=5V/
DIV
I=400mA/
DIV
P=4W!
DIV
V=5V/
DIV
In the experiment, the light source was turned on at t = Os
under light intensity of 85mW/cm2 and temperature of 400C.
The maximum power point at this environment is 8.0W. Fig.
4 (a) and (b) show the power tracking results obtained from I=400mA/
the P&O method with the fixed change in duty ratio, AD, of DIV
2/256 and 5/256, respectively. It can be seen that the settling
Math 20
time (t5) when AD = 2/256 is 200ms whereas it takes only (b)
V
lOOms when AD = 5/256. The larger AD, however, gives Fig. 4. Tracked power from P&O method under a light intensity of
larger fluctuations in output power as show in Fig. 4 (b). 85mW/cm2 and temperature of 40C (a) fixed AD at 2/256 and (b) fixed
Fig. 5 shows the results obtained from the proposed AD at 5/256
variable step-size P&O algorithm. We can obviously see that
the settling time is substantially reduced, only 85ms, and the
power fluctuations are very small throughout the course.
These system performances have been tested under more
practical scenarios. The light intensity is set to be varying
with the values of 85, 45 and 75mW/cm2 at 0 to 2s, 2 to 4s,
and 4s onward, respectively. This environment results in three
maximum power points of about 8.0, 4.0 and 6.4W,
respectively. The results obtained from fixed AD = 2/256,
5/256 and our proposed system are compared as depicted in
Fig. 6 (a), (b) and (c), receptively. Again, the maximum
power point can be tracked relatively fast and with small
fluctuations, even under such dynamic environment.
The DC-link current flowing through the battery at steady
state is shown in Fig. 7 in order to verify the efficiency of the
Math 2
overall system. The steady state power received by the battery Fig. 5.
VV
f97.65HPW
1-41 I
Ib=25OmA
/DIV
,. 1. I. 1.2;3 .v, Pi &-.' 200MV .'.
ME ..
M~ I3I -
Cnl1 I
xr I
3. I 11
V
F ig. 7. Battery current and controlled switch signal at 8.0W power from
(a) PV array
(b)
RE-FERENCES
Vbat, measured after the boost converter is 12.2V, and the pp. 507-5 10, 2005.
[6] A. D. Maksimovic, and R.W. Erickson, "Design
Prodic,
battery current is 0.63A. Hence, the output power fed into the
and implementation of a digital PWM controller for a
battery becomes 7.7W. This means the overall efficiency of
high-frequency switching dc-dc power converter," Proc.
the proposed system is more than 960o given that the output
IEEE Ind Electron. Soc. Conf vol. 2, pp. 893-898, 200 1. ,
In this paper, the development of an adaptive for a variable pp. 334-343, Jan. 2003.
perturbation step size on field programmable gate array for [8] http://www.xilinx.com/