Cmrf8sf - Design Manual A

CMOS8RF (CMRF8SF)
Design Manual
Owner: Department 9G8A

Mixed Signal Technology Development
IBM Microelectronics Division
ES Number: ES#57P9006
Version Date: November 30, 2010

Document Review Date: -
Engineering Specification Changes

EC# H74369 Oct 9, 2003
EC# H96317 May 24, 2004
EC# J82765 May 5, 2005
EC# J94538 Mar 27, 2006
EC# J95308 Aug 1, 2006
EC# J88658 April 24, 2007
EC# L91805 September 22, 2008
EC# L92814 March 25, 2009
EC# L93661 July 15, 2009
EC# L93972 August 19, 2009
EC# L85430 April 30, 2010
EC# L86842 November 30, 2010
Manufacturing TPRS Name: CMRF8SF
This document is maintained by Mixed Signal Technology Development. Users should not make unautho-
rized copies or alterations. It is the users responsibility to verify that the hard copy version date is the most
current version by contacting the document author. Instructions for verification may be found in section Doc-
ument Distribution and Ownership on page 15.
THIS HARD COPY MUST BE PROMPTLY REMOVED FROM USE WHEN OBSOLETE.
IBM Confidential -- Do Not Copy

CMOS8RF (CMRF8SF) Design Manual
Contents IBM
Notices:
WITH RESPECT TO MATERIALS AND INFORMATION PROVIDED BY IBM, NO WARRANTIES EXPRESS
OR IMPLIED, INCLUDING ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A
PARTICULAR PURPOSE, ARE OFFERED HEREIN. In no event shall IBM be liable for any actual, incidental,
consequential, or other damages, including lost profits or lost savings, even if it is given prior notice of the
same, which result from any use of the materials or information.
Copyright:
Copyright International Business Machines Corporation 2002, 2003, 2004, 2005, 2006, 2007, 2008,
2009, 2010. All rights reserved. Redistribution is not authorized without the express written permission of
IBM Mixed Signal Technology Development Solutions.
Note to U.S. Government Users Documentation related to restricted rights Use, duplication or disclosure
is subject to restrictions set forth in GSA ADP Schedule Contract with IBM Corporation.
Trademarks:
GDSII and Spectre are trademarks of Cadence Design Systems, Inc.
HSpice is a trademark of Synopsys Corporation, Inc.
V 1.8.0.0 (Version Date: November 30, 2010)

This version of the CMOS8RF (CMRF8SF) Design Manual applies to the V 1.8.0.0 version of the CMOS8RF
(CMRF8SF) models and design kit. It will also apply to all subsequent releases, versions, and modifications until other-
wise indicated in new editions or addenda. The TPRS manufacturing technology name to which this manual applies is
CMRF8SF, the FEOL specification ES. is 70P6194 and the ILETS specification ES is 70P6304.
For access to this manual. please contact your IBM Product Engineer. Any comments, questions, suggestions, or addi-
tions regarding its contents can also be addressed to:
E-mail: fdrytech@us.ibm.com
Analog and Mixed Signal Technology Development

IBM Microelectronics Division
861A
1000 River St.
Essex Junction, VT 05452-4299
IBM Corporation, 2010. All rights reserved. ES#57P9006 EC# L86842

Use is further subject to the provisions on the back of the title page.
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IBM CMOS8RF (CMRF8SF) Design Manual
Contents
Contents
1.0 Technology Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.3 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.4 Document Distribution and Ownership. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.5 Document Change Approval . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.6 Summary of Changes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.7 Chip Design Check List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.8 Change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.9 CMOS8RF (CMRF8SF) Cross Sections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.0 Physical Layout Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2.1 Design Grid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.2 Mask Level Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.3 Dummy Design Levels and Utility Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
2.4 Masks for Non-Design Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
2.5 Level Generation and Design Preparation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
2.6 Mask Metallization Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
2.7 Design Truth Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
2.8 Design Geometry Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
2.9 Important Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
2.10 Pattern Density Rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
3.0 Layout Rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

3.1 Polysilicon and Isolation Layout Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
3.2 N-well, Contact, Junction Layout Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
3.3 ZVT NFET Layout Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
3.4 Low Power Vt FET and LVT FET Layout Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
3.5 Threshold Voltage Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
3.6 BP Layout Rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
3.7 Butted Junction Layout Rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
3.8 CA, Metals and Via Layout Rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
3.9 Mask Process Control Images . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
3.10 Latchup Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
3.11 External Latchup Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
3.12 ESD Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
3.13 ESDIODE Layout Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
3.14 Forward-Biased Diode Layout Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
3.15 OP Resistor Layout Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
3.16 OP RR Resistor (RR and PD) Layout Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
3.17 OP RP Resistor (Precision Resistor) Layout Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
3.18 N-well Resistor Layout Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
3.19 Silicided Polysilicon Resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
3.20 Back-End-Of Line Resistor Layout Rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
3.21 Barrier Diode Rules (RN, NS, & BB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
3.22 BFMOAT Design Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
3.23 DG Layout Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
ES#57P9006 EC# L86842 IBM Corporation, 2010. All rights reserved.

Version Date: November 30, 2010 IBM Confidential - Do Not Copy Page 3 of 580
Contents IBM
3.24 Dual Gate 3.3V I/O Device (5.2nm) Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
3.25 Low Leakage 3.3V I/O FET Device Layout Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
3.26 nFET-in-Nwell (VAR) Device Layout Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
3.27 Triple Well (Isolated) NFET Layout Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
3.28 Electrically Programmable Fuse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
3.29 Design Services Matched-Circuit Design Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
3.30 JD Junction Varactor Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
3.31 Metal-to-Metal (MIM) Capacitor Layout Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
3.32 Vertical Natural Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
3.33 Inductor Layout Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
3.34 RF Interconnect Line and Transmission Line Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
3.35 Terminals, IO Pads, C4 and Wirebond . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
3.36 Slots in Wide Metal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
3.37 Chip Guard Ring and Chamfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
3.38 Protect Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
3.39 Crackstop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
3.40 Product Labels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
3.41 No Polyimide Final Passivation option. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
3.42 Permissible Chip (CHIPEDGE) Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
4.0 Electrical Parameters and Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335

4.1 Available Devices and Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335
4.2 Isolation Oxide (STI) Design Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
4.3 General FET Electrical Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
4.4 Regular FET Device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348
4.5 Thin Triple Well NFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
4.6 Low-Vt FET Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
4.7 LP NFET and PFET (for Low Power Applications) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
4.8 Regular-IO FET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
4.9 Thick Triple Well NFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
4.10 3.3V I/O FET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
4.11 Thick Triple Well NFET33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
4.12 3.3V High-Vt I/O FET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
4.13 Thick Triple Well High-Vt NFET33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
4.14 Thin oxide Zero-Vt NFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
4.15 Thick Oxide Zero-Vt NFET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
4.16 T3 Isolation Well . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374
4.17 Junction Diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
4.18 Resistor Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
4.19 NCAP and DGNCAP Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
4.20 Hyperabrupt (HA) Junction Varactor Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392
4.21 Differential Varactors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
4.22 MIM Capacitor Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394
4.23 HiK and Nitride Capacitors for OL BEOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397
4.24 Capacitors for AM BEOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401
4.25 VNCAP - Vertical Natural BEOL Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401
4.26 Forward-Biased Diode Device Models. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404
4.27 Schottky Barrier Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406
4.28 Substrate Contact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410
4.29 Conducting Film Thickness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412
4.30 Wire Resistance Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416

Contents
4.31 Wiring Capacitance Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421

4.32 Electrical Moat Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429
4.33 Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431
4.34 Inductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432
4.35 Bondpad Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436
4.36 Rfline Device Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439
4.37 Capacitive Loading/Transmission Line Effects for Arbitrarily Shaped Interconnects . . . . . . . . . . . . . . 440
4.38 Shielded Transmission Line (T-line) Interconnect Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443
4.39 Mixed Voltage Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450
5.0 Reliability Design Rules and Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458

5.1 Guidelines for Optimal Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458
5.2 Reliability Screening. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459
5.3 Front End Of Line (FEOL) Reliability Design Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461
5.4 Back End Of Line (BEOL) Reliability Design Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489
6.0 Latchup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504

6.1 Latchup Background and Experimental Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504
6.2 Latchup Guidelines and Layout Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508
7.0 Electrostatic Discharge (ESD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523

7.1 Salicide-blocked FETs for ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523
7.2 ESD Background and Experimental Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524
7.3 ESD Schematic level checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524
8.0 Design for Manufactureability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528

8.1 Yield Enhancement Design Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528
8.2 Design for Manufactureability Initiatives. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532
I.0 Standard and Dense SRAM Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538
J.0 Guidelines for Optimal Model-Hardware Correlation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539
K.0 Total Standby Current (Idd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540
L.0 Design Hierarchy Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542
M.0 Rule Syntax (Definitions) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543
N.0 Definitions of Process-Related Terms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546
O.0 Migration into Future Technologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547
P.0 Design Preparation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548

P.1 Complex Optical Manipulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548
P.2 Dense SRAM Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548
P.3 PC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548
P.4 Far BEOL Manipulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548
Q.0 Pattern Fill Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549

Q.1 xxFILL and xxHOLE Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549
Q.2 Recommended Design Practices Related to Generated FILL and HOLES Shapes . . . . . . . . . . . . . . . 575

Technology Introduction Features IBM
1.0 Technology Introduction

This manual covers the CMOS8RF (CMRF8SF) technology.
1.1 Features
General CMOS Process

Vdd = 1.2V with option for 1.5 V use.
Substrate resistivity of 1-2 ohm-cm.
Twin well CMOS technology on non-epi P- substrate.
Shallow trench isolation (STI).
Dual gate oxide with physical thicknesses 2.2 nm and 5.2 nm.
Minimum lithographic image = 0.12 m (gate only).
Low resistance Co salicided N+ and P+ polysilicon and diffusion areas.
5 to 8 levels of global metal with common wiring levels M1, M2, and MQ (see Section 2.6 , Mask Metal-
lization Options on page 63).
- Last Copper metal (LM) at a pitch for designs with 5 or more metal levels (see Table 11)
- Last Aluminum metal (MA) at a larger pitch for designs with 6 or more metal levels (see Table 12).
- Last Aluminum metal (LD) at a larger pitch for designs with 5 or more metal levels (see Table 13)
- Last Aluminum metal (AM) at a larger pitch for designs with 7 metal levels (see Table 14).
Thick metal wiring options:
- Two or three thick copper levels
MQ and LM
MQ and MG and LM
- One or two thick copper levels with Aluminum (LY) and thick Copper (E1) and thick Aluminum (MA)
levels
MQ (with LY, E1, MA)
MQ and MG (with LY, E1, MA)
- One or two thick copper levels with thick Copper (OL) and thick Aluminum (LD) levels
MQ (with OL, LD)
MQ and MG (with OL, LD)

Technology Introduction Features
- One thick copper level with one thick Aluminum level
MQ (with AM)
Tungsten stud contact connecting polysilicon or diffusion to the first metal level.
Common wiring level vias V1, V2, VL with additional via options related to various metal options (see
Section 2.6 , Mask Metallization Options on page 63).
Planarized passivation and interlevel dielectrics with a low-K value.
Wire-bond pads or controlled collapse chip connections (C4s)
Optional Electronic Fuse
List of supported base feature devices:

Thin oxide surface channel1 NFET and PFET with Lp 0.092 0.011 m
ESD Devices
- Vertical PNP (P+/NW diode)

- N+/SX diode
Modelled device structures, dependent on Metallization Option selected:
- Inductors
- Bondpads (C4 and Wirebond)
- RF Interconnect Lines
- Transmission Lines
List of supported devices not requiring additional masks, and are feature options:
Forward Bias (DI) Diode (2 or 3 terminal models)
Thin Oxide MOS Varactor
PCDCAP Thin Oxide (similar to Thin Oxide MOS Varactor)
N-well resistor
Vertical Natural Capacitor
Electronic Fuse
Silicided PC Resistor
1. The Lp tolerance is the 3 chip mean variation (chip-to-chip) and does not include across-chip linewidth varia-
tion (=ACLV).

Technology Introduction Features IBM
List of optional devices requiring additional masks:
Thin Oxide surface channel1 low power NFET with Lp 0.092 0.011 m (requires 1 additional derived
mask; NV)
Thin Oxide surface channel1 low power PFET with Lp 0.092 0.011 m (requires 1 additional derived
mask; PV)
Thin Oxide surface channel1 low threshold voltage NFET with Lp 0.092 0.011 m (requires 1 addi-
tional derived mask; XW)
Thin Oxide surface channel1 low threshold voltage PFET with Lp 0.092 0.011 m (requires 1 addi-
tional derived mask; LW)
Thick oxide NFET and PFET devices for native 2.5V operations, I/O and analog applications (minimum
Ldrawn=0.24m) (requires 1 additional mask DG, and 3 additional derived masks; DW, DE, DF)
Thick oxide NFET devices for 3.3V operations (minimum Ldrawn=0.40m) (requires 1 additional mask;
DG, and 2 additional derived masks; DW, XE)
Thick oxide PFET devices for 3.3V operations (minimum Ldrawn=0.40m) (requires 1 additional mask;
DG, and 1 additional derived mask; XF)
Thick oxide HiVt NFET devices for 3.3V operations (minimum Ldrawn=0.40m) (requires 4 additional
masks; DG, JN, XE, DW)
Thick oxide HiVt PFET devices for 3.3V operations (minimum Ldrawn=0.40m) (requires 3 additional
masks; DG, JP, XF)
Thin oxide zero-Vt NFET devices (minimum Ldrawn=0.42m) (requires 1 additional derived mask; DE)
Thick oxide zero-Vt device NFET (minimum Ldrawn =0.56m) (requires 1 additional mask; DG and 1 addi-
tional derived mask; DE)
Thin PI Triple Well NFET (requires 1 additional mask; PI)
Thick PI Triple Well NFET (requires 2 additional masks; PI, DG and 2 additional derived masks; DW, DE)
T3 Isolation Well that enables the placement of both NFETs and PFETs in a well isolated from the bulk
substrate (requires 1 additional mask; T3, and 1 addition design level; IBLK)
HA Varactor (requires 1 additional mask; JD, and 1 additional derived mask; VI)
Schottky Barrier Diode (requires 1 additional mask; NS)
Resistors:
- n+ diffusion (requires one additional mask; OP)
- p+ polysilicon (requires one additional mask; OP)
- OP RR PC Poly Resistor (requires two additional masks; OP and RR)
- OP RP Poly Resistor (requires two additional masks; OP and RP)
- L1 BEOL Resistor (for MA Last Metallization Option only) (requires one additional mask; L1)

Technology Introduction Features
- Kx BEOL Resistor (requires one additional mask; Kx, see Table 11 or Table 13 for details)
Thick Oxide MOS Varactor (requires one additional mask; DG)
PCDCAP Thick Oxide (similar to Thick Oxide MOS Varactor, requires one additional mask; DG)
Metal-to-Metal (MIM) Capacitor for OL with LD Last Metallization Option only, see Table 13 for details.
- Hi-K MIM Capacitor (requires 2 additional masks; QK and HK [Note: uses common design levels QT
and HT during layout])
- Single Nitride MIM Capacitor (requires 2 additional masks; QT and HT).
- Dual Nitride MIM Capacitor (requires 3 additional masks; QT, HT and KT).
Metal-to-Metal (MIM) Capacitor for MA Last Metallization Option only, see Table 12 for details
- Single HP (High Performance) MIM (requires one additional mask; QY)
- Dual HP (High Performance) MIM (requires two additional masks; QY and HY)
ESD Devices:
- Salicide Blocked ESD Regular (Thin Oxide) NFET (requires 1 additional mask, OP). See Table 1 and
select Miscellaneous FEOL feature option.
- Salicide Blocked ESD (2.5V) Thick Oxide NFET (requires 2 additional masks; DG, OP, and 2 addi-
tional derived masks; DW, DE. See Table 1 and select Thin oxide + thick oxide feature option and
Miscellaneous FEOL feature option. Note: a fifth mask; DF, is also used during processing with these
feature selections.
- Salicide Blocked ESD (3.3V) Thick Oxide NFET (requires 3 additional masks; DG, OP, XE and 1
additional derived mask; DW. See Table 1 and select Thin oxide + thick oxide feature option and Mis-
cellaneous FEOL feature option. Note: a fifth and sixth mask; DE and DF, is also used during pro-
cessing with these feature selections.
The technology operates over the following temperature and voltage ranges:
Maximum power supply voltage of1.6V for 2.2-nm oxide field-effect transistors (FETs), 2.7V for 5.2-nm
oxide FETs, 3.6V for the 5.2-nm 3.3V I/O oxide FETs
Maximum Thick Oxide MOS Varactor and PCDCAP Thick Oxide bias = 3.3V
Maximum HA Varactor use voltage = 3.6V
Maximum MIM use voltage:
- See section 4.39.9 , VMAX for Single and Dual Nitride MIM Capacitor (for MA or OL with LD Metal-
lization Options) on page 454.
- See section 4.39.10 , VMAX for Hi-K MIM (for OL with LD Metallization Option) on page 456.
Maximum VNCAP use voltage = 3.6V (3.3 +/- 0.3V power supply)
For P+ Poly, OP RR PC Poly, OP RP Poly, N-well Resistor and N+ Diffusion Resistor limits, see Section
4.18.1 , Resistor Design Specifications on page 379. Current limit vs. Temperature information for the
P+ Poly, OP RR and OP RP Poly resistors are listed in Section 5.3.7 , Resistor Reliability on page 483.

Technology Introduction Description IBM
For BEOL Kx (x = 2,3,4,5,6) resistor limitation, see Section 4.18.1 , Resistor Design Specifications on
page 379. For Current limit vs. Temperature information, see section , Back-End-Of-Line K2, K3, K4, K5,
or K6 Resistors on page 485.
For BEOL L1 resistor limitation, see Back-End-Of-Line L1 Resistor: on page 486.
Operating temperature range of -55 to 125C (junction Temp.)
Maximum burn-in voltage, 2.375 for 2.2-nm and 3.875V for 5.2-nm oxide devices, and maximum burn-in
temperature of 140C
List of CMS8SFG features or devices that are NOT equivalent or supported in the
CMRF8SF technology:
Metal-Insulator-Metal (MIM) Capacitor (QE, QT, HT) (not supported, alternate device offered in the
CMRF8SF technology using same mask levels)
High VT NFET (not supported, see CMRF8SF LP NFET which is a different device)
High VT PFET (not supported, see CMRF8SF LP PFET which is a different device)
1.7 nm MPNFET (UT/BU) (not supported)
1.7nm MPPFET (UT/PU) (not supported)
BEOL wiring using VA, ME, VM, MT, LB and VV vias or metallization (not supported)
Last Metal (Laser Blown) Fuse (not supported)
Known limitations in the CMRF8SF technology:

Inductors using viabars between 1x or 2x Mx wiring levels (x = 1,2,3,4,5,6,Q,G) or using FYBAR are not
supported when MA last metal options are used.
Inductors using viabars between 1x Mx wiring levels (x = 1,2,3,4) are not supported when OL with LD
metallization options are used.
LD or OL RF Lines, similar to LM or MA modelled devices, are not offered.
LD or OL transmission lines, similar to LM or MA modelled devices, are not offered.
1.2 Description
The CMOS8RF (CMRF8SF) technology features high density 0.13 m CMOS logic intended for RF and ana-
log and mixed signal applications.

Technology Introduction Ordering Information
1.3 Ordering Information

Designers can use Table 1 to compile a list of features and part numbers required by IBM manufacturing. For
more information, contact your IBM technical representative, or the Foundry Technical Support team by
sending an E-mail to fdrytech@us.ibm.com, or through the web at http://www.ibm.com/technologyconnect.
Feature availability and use restrictions are for reference only and may change. Requested features will be
evaluated based on current information as part of the ordering process.
Table 1. Optional Features with Feature Part numbers
Feature Group Description Additional Masks1 Feature2

and Restrictions Part number
Always included Base features for CMOS8RF - 57P9018
(CMRF8SF) 3,4
Oxide Options Thin oxide only - 75H3168
(select one) Thin oxide + thick oxide DG, DW, DE, DF 70P0331
Thin Oxide Optional Zero-Vt NFET Thin-oxide DE 75H3025
Devices Thin PI Triple Well NFET PI 70P7900
(select any)
PCDCAP (thin ox decoupling - 75H3027
capacitor)
Varactor (thin ox) - 75H3089
Thick Ox Optional Zero-Vt NFET Thick-oxide DE, DG 75H3090
Devices Thick PI Triple Well NFET DE, DG, DW, PI 70P7901
(select any)
PCDCAP25 (thick ox decou- DG 75H3219
pling capacitor)
Varactor (thick ox) DG 70P7902
HiVt 3.3V NFET DG, JN, XE, DW 70P9939
(NOT qualified)
HiVt 3.3V PFET DG, JP, XF 70P9940
(NOT qualified)
3.3V I/O PFET XF, DG 42K1506
3.3V I/O NFET XE, DG, DW 42K1507
Thin Ox Vt NFET Regular Vt NFET - 75H2982
options Low Vt NFET XW 70P7903
(select one)
Regular Vt NFET +Low Vt XW 75H2994
NFET
Low Power NFET NV 70P7904
Regular NFET +Low Power Vt NV 70P6369
NFET
Regular Vt NFET + Low Power NV, XW 70P6370
Vt NFET +Low Vt NFET

Technology Introduction Ordering Information IBM
Thin Ox Vt PFETs Regular Vt PFET - 75H3093
(select one) Low Vt PFET LW 70P7905
Regular Vt PFET +Low Vt LW 75H3170
PFET
Low Power PFET PV 70P7906
Regular PFET +Low Power Vt PV 70P6372
PFET
Regular Vt PFET + Low Power PV, LW 70P6373
Vt PFET +Low Vt PFET
Diode HA Junction Varactor JD,VI 70P7907
(select any) DI Diode5 - 70P0106
Schottky Barrier Diode NS 59Y1119
Miscellaneous ESD Devices OP 27R3217
FEOL T3 Isolation Well6 T3 49J5854
(select any)
Resistors OP N DIFF OP 75H3092
(select any) OP PPOLY OP 06K7940
PC OP RR polysilicon resistor OP, RR 70P7908
Resistor Precision OP, RP 27R6143
N-well Resistor - 17R4145
Silicided Polysilicon resistor - 44K5768
(NOT qualified)
Resistors BEOL K4
(select one)7 K5
BEOL Resistor K2 42K1817
K3
K6
L1 57P7613
MIM Capacitors Single Hi-K MIM 10 (for OL with QK, HK 58Y9419
options8,9 LD metallization option only)
(select up to one) Single Nitride MIM 11 QT, HT 58Y9420
(for OL with LD metallization
option only)
Dual Nitride MIM 11 QT, HT, KT 58Y9421
(for OL with LD metallization
option only)
Single HP MIM (for last metal QY 70P7909
MA final wire only)
Dual HP MIM (for last metal QY, HY 70P7910
MA final wire only)

Technology Introduction Ordering Information

Vertical Natural Back-end-of-line (BEOL) Mx 27R6144
Capacitor capacitor (x=1,2,3,4,5,6 and is individual
or a combination of consecu-
tive levels of thin Mx metals)
SRAM options12 Dense SRAM (w/VE) CF, D1,VE 70P6163
(select one) No dense SRAM CA, M1,V1 57P8787
Metallization Two Thick Cu levels W/ LM LM, VQ, MQ, VL, Mx 45L8956
Option, Final Wiring
(select one)
Three Thick Cu levels W/ LM LM, VG, MG, VQ, MQ, VL, Mx 45L8957
Final Wiring
One thick copper level with a MA, F1, E1, FT, LY, FY, MQ, 70P7912
last metal (MA) final wire VL, Mx
Two thick copper levels with a MA, F1, E1, FT, LY, FY, MG, 70P7913
last metal (MA) final wire VQ, MQ, VL, Mx
One thick copper level with a AM, FQ, MQ, VL, Mx 56Y9981
last metal (AM) final wire
(NOT qualified)
One thick copper level with OL LD, VV, OL, JT, MQ, VL, Mx 42K7666
second to the last metal with
LD last metal final wire
Two thick copper levels with OL LD, VV, OL, JT, MG, VQ, MQ, 42K7667
second to the last metal with VL, Mx
LD last metal final wire
Metallization Five metal levels (5LM) See Table 11, LM last metal 01L6952
scheme13 Six metal levels (6LM) Back End Of Line (BEOL) Met- 01L6953
allization Options on page 64
(select one) Seven metal levels (7LM) 29L6986
or
Eight metal levels (8LM) Table 12, MA last metal Back 45L8958
End Of Line (BEOL) Metalliza-
tion Options on page 65
or
Table 13, OL with LD last
metal Back End Of Line
(BEOL) Metallization Options
on page 66
or
Table 14, AM last metal Back
End Of Line (BEOL) Metalliza-
Fuse Electronic Fuse (eFuse) - 57P6150

Technology Introduction Ordering Information IBM
Bonding Type C4 Plated - 01L6993
(select one) (must pick one final via option)
Wirebond - 01L6995
(must pick one DV final via
option)
Not Bumped or Bonded by IBM - 21L2039
(must pick one final via option)
Final Via DV DV 29L5231
(select one) (with either last metal LD or MA
or AM final wires)
(must also pick Wirebond
(01L6995) or Not Bumped or
Bonded by IBM (21L2039)
Bonding Type)
TV-TD-FV TV, TD, FV 06K5255
(with a last metal LM final wire)
(must pick C4 Plated
(01L6993))
TV-TD-DV TV, TD, DV 06K5257
(with a last metal LM final wire)
(must also pick Wirebond
(01L6995))
LV LV 01L6998
(with either last metal LD or MA
or AM final wires)
(must pick C4 Plated
(01L6993) or Not Bumped or
Bonded by IBM (21L2039)
Bonding type)
DV - without Polyimide 14 DV 39N3035
Must also include ID shape
NOPLYMD in layout.
(must pick Not Bumped or
Bonded by IBM (21L2039))
LV - without Polyimide 14 LV 48J7330
Must also include ID shape
NOPLYMD in layout.
(must pick Not Bumped or
Bonded by IBM (21L2039))
Reliability Grade Grade 3 Grade 3 29L5234
(select one) Consumer Grade 4 Consumer Grade 4 66P7361
Industry Standard (Std) Industry Std. Foundry Screen 29L5235
Foundry Screen
1. Additional masks beyond the base feature-required levels (that is, RX, NW, PC, BP, BT, BF, BH, PH, BN, and CA).

Technology Introduction Document Distribution and Ownership
2. The base features part number represents standard processing for that technology. In order to ensure correct manufacture of each
part a list of features must be supplied to manufacturing. This table is intended to assist designers in providing the necessary
information to their IBM Technical Representative. Feature availability and limitations are shown here for reference only and may
change. Features must be evaluated based on current information as part of the ordering process.
3. All designs also require the use of Back-End-Of-Line (BEOL) mask levels M1, V1, M2, VL, MQ as well as one of the Final Via and
Bonding Type feature options. However, the M1, V1, M2, VL, MQ as well Final Via mask levels are not part of the base feature part
number for this technology. The minimum quantity of metal levels is dependent on the Metallization scheme and Metallization
option selected (LM versus MA versus OL with LD as the last wiring metal level). The minimum quantity mask levels for the Final
Via options is dependent on Metallization Option and Bonding Type selected. Selection of the SRAM options feature may affect
the use of the required mask level CA, as well as M1 and V1 mask levels.
4. Designs based on the 0.13m CMOS8RF(CMRF8SF) technology must include at least one thin-oxide NFET and one thin-oxide
PFET.
5. This feature is also to be used for the parasitic PNP device offered in this technology.
6. For a full list of what is and is not allowed to be placed inside the T3 Triple Well see T3 Isolation Well on page 374.
7. Only one BEOL resistor can be used in a chip design for any of the metallization scheme or metallization options identified. The Kx
(x=2,3,4,5,6) BEOL resistor shares a common feature part number, with rules tied to last Mx (x= 2,3,4,5,6) metal level used for the
BEOL metallization scheme feature selected. L1 BEOL resistor has its own unique Feature Part Number. Further, when the
metallization option Feature Part Number 70P7912 or 70P7913 is selected, the L1 BEOL resistor feature is prohibited from being
used if a Kx BEOL resistor feature is selected, or if a L1 BEOL resistor feature is selected, then use of a Kx BEOL resistor feature
is prohibited. L1 resistors are only available when using Feature Part Number 70P7912 or 70P7913, while at least one Kx BEOL
resistor feature option is supported for all LM, MA, AM or OL with LD metallization schemes or options. For additional information,
see Table 11 or Table 12 or Table 13 or Table 14 located in Section 2.6 , Mask Metallization Options on page 63.
8. Single MIM and Dual MIM are allowed to co-exist in a chip design with the MA metallization or the OL with LD metallization. The MIM
for the OL with LD metallization option is not allowed with the MA or LM metallization options. The LM metallization option does not
support any MIM Feature Part Number option.
9. For designs which contain both single and dual MIMs, the dual MIM feature PN should be selected. Designs which use both the Single
HP MIM (70P7909) and the Dual HP MIM (70P7910) for the MA metallization should select only the Dual HP MIM (70P7910).
Designs which use both Single Nitride MIM (58Y9420) and Dual Nitride MIM (58Y9421) for the OL with LD metallization should
select the Dual Nitride MIM only.
10. Single Hi-K MIM uses design levels QT, HT and utility level MIM_HK. The single Hi-K MIM is fabricated using mask level QK and
HK. For more information see MIM_HK in Table 6 on page 46, QK and HK in Table 9 on page 62 and these levels Table 13 on
page 66. The Single Hi-K MIM can not be used in the same chip design as a Single Nitride MIM or a Dual Nitride MIM.
11. The Single Nitride MIM uses design levels QT, HT and utility level MIM_NI. The Dual Nitride MIM uses design levels QT, HT and
KT and utility level MIM_NI. The Single Nitride MIM is built on the QT and HT mask levels. The Dual Nitride MIM is built on the QT,
HT and KT mask levels. For more information see MIM_NI in Table 6 on page 46, QT, HT and KT in Table 9 on page 62 and these
levels in Table 13 on page 66. The Single Nitride MIM and Dual Nitride MIM may co-exist in a chip design. However, the Single
Nitride MIM or the Dual Nitride MIM can not co-exist in the same design as a Single Hi-K MIM. For additional information or MPW
designs, contact your IBM Technical Representative.
12. SRAM designs must use dummy edge cells around the external perimeter of the array. Exceptions must be approved by the IBM
Waiver Review Board. Two SRAM cells have been approved, See Section I.0, Standard and Dense SRAM Designs on page 538.
13. Five levels of metal (5LM) only offered with the LM or OL with LD metallization options (MA metallization does not have a 5LM
feature option). For all metallization schemes offered, see Section 2.6 , Mask Metallization Options on page 63
14. IBMs technology level qualifications have included polyimide final passivation, but IBM sees no intrinsic impact to the wafer
reliability failure rate for foundry customers who require wafers without polyimide. The customer is responsible however to evaluate
product and packaging reliability failure rates for wafers without polyimide.
1.4 Document Distribution and Ownership

The owner of this document is the manager of Mixed Signal Technology Development.
The author, who is responsible for the organization and approval of this document, is Kevin Ogg.
The complete and current version of this document can be obtained from the author. Please contact your IBM
Product Engineer for assistance.

Technology Introduction Document Change Approval IBM
If you are on the documents distribution list and have been sent a manual directly, you will automatically be
sent updates and/or reissuances as they become available. However, to be sure that you have the latest ver-
sion or for information regarding future updates, please contact the author or your IBM Product Engineer.
Superseded versions of this document will be retained by the document owner for the life of the program.
The final version of the document will be retained according to IBM corporate guidelines.
1.5 Document Change Approval

The following people review and approve any changes to this document.
Function Name / Title Date

AMS Technology Development Kevin N. Ogg / Eng November 30, 2010
Design Services Jeanne Sucharitaves / Eng November 19, 2010
Data Preparation Michael Hulvey / Eng November 25, 2010
Technology Reliability Kim Watson / Eng November 23, 2010
Product Reliability Engineering Douglas Dewey / Eng November 04, 2010
BTV wafer fab ME Steve Williams / Eng November 19, 2010
Logic Bond, Assembly and Test Tim Daubenspeck / Eng November 10, 2010
Wafer Finishing (Bromont) Stephane Mainville/ Eng November 19, 2010
Wafer Finishing (Burlington) Gary Lines / Eng November 04, 2010
C4 Plated Terminal Metals ME Sarah Knickerbocker / Eng November 05, 2010
Wafer Probing ME Akiko Balchiunas / Eng November 15, 2010
Wirebond Packaging ME John Malinowski / Eng November 24, 2010
Mask Product Engineering Adam Smith / Eng November 15, 2010
AMS Modeling Jingdong Deng / Eng November 15, 2010
Foundry Products Paul Pfeiffer/ Eng November 23, 2010
Foundry Technology Enablement Syed Ali / Eng November 22, 2010
Electro-Static Discharge and Latchup Mujahid Muhammad / Eng November 10, 2010
Kerf & Reticle Design Mark Pouliot / Eng November 10, 2010
Approval records for the revisions listed in Document Change Approval, are available from the author.
Approvals for current versions will be retained indefinitely. Approvals for earlier versions will be retained for
no less than one year after they are superseded.

Technology Introduction Summary of Changes
1.6 Summary of Changes

The following is a history of this document and summarizes the changes made in each version and/or revi-
sion. A more complete list of changes, for the current version, can be found in the section Section 1.8
Change list on page 18.
Version Date Brief Change Description

June 2002 Alpha Kit (Not approved) Version
June 2003 Alpha2 Kit (Not approved) Version
Oct 2003 Beta Kit Version
May 2004 V 1.1.0.0 Design Kit Version
May 2005 V.1.2.0.0 Design Kit Version
March 2006 V.1.3.0.0 Design Kit Version
Aug 2006 V.1.3.1.0 Design Kit Version
April 2007 V.1.4.0.0 Design Kit Version
September 2008 V.1.5.0.0 Design Kit Version
July 2009 V.1.6.1.0 Design Kit Version
August 2009 V.1.6.2.0 Design Kit Version
November 2010 V.1.8.0.0 Design Kit Version
1.7 Chip Design Check List

The following checklist is required to be completed prior to design data submission:
1. The design passes DRC (design rule checking). Refer to the Design Kit Users Guide documentation
for information on the required checks.
2. Floating I/O pads are not allowed especially pads which are wired only to MIM Capacitors. C4s and Wire-
Bond pads must have a DC connection to a RX shape (see Rules 908 and 953, or MA908 and MA953, or
LD908 and 953LD, or AM908 and AM953).
3. The design passes layout versus schematic (LVS) checking.
4. Simulations of all circuits produce acceptable behavior over the entire operating range and range of pro-
cess variation, and produce acceptable behavior through wearout mechanisms modeled including
Burn-In and total use conditions through the product lifetime.
No hot carrier shifts result in loss of circuit function, timing skew, performance shift or increases in
standby current.
No contacts or metal lines carry more than their rated currents.
All circuits operate at the reliability screen conditions and/or at burn-in conditions (See Section 5.1 ,
Guidelines for Optimal Reliability on page 458)

Technology Introduction Change list IBM
5. To ensure chip testability is not compromised by oscillations or other undesired behavior, module testing
of RF products at IBM require chip level simulations using socket models. Socket models may be
obtained from your IBM Product Engineer.
6. Electro-static Discharge (ESD) and latchup layout and design requirements have been met (see Section
3.10 , Latchup Rules on page 176 and Section 3.11 , External Latchup Rules on page 184 and Sec-
tion 7.0 Electrostatic Discharge (ESD) on page 523)
7. No floating wells are present
8. Internal power bus networks minimize local power supply drops and deviations.
9. Power supply networks test probe and package lead impedances match those expected to ensure func-
tionality and testability.
10. Recommendations listed in Section J.0, Guidelines for Optimal Model-Hardware Correlation on
page 539 have been considered.
11. Recommendations listed in Section L.0, Design Hierarchy Guidelines on page 542 have been consid-
ered.
Note: A design kit is available through your IBM Technical Representative.
1.8 Change list

Changes from former document version, EC # L85430, dated April 30, 2010:
Cover: Updated EC# and modified version date appropriately, page 1.
Inside cover: Updated Version number to V 1.8.0.0 (Version Date: November 30, 2010) on page 2.
Section 1.1: Updated the required mask listing for the HiVT 3.3V NFET and the HiVT 3.3V PFET. Addi-
tional masks XE and DW were added to the NFET and additional mask XF was added to the PFET in List
of optional devices requiring additional masks: on page 8
Section 1.1: Added the following information to clarify that Thick Oxide PCDCAP and Thick Oxide MOS
Varactor can be used up to 3.3V. Maximum Thick Oxide MOS Varactor and PCDCAP Thick Oxide bias =
3.3V on page 9
Section 1.3: Modified two feature PNs in Table 1, Optional Features with Feature Part numbers, on
page 11, in support of updates to the HiVT 3.3V NFET and the HiVT 3.3V PFET. Additional masks XE
and DW were added to the NFET and additional mask XF was added to the PFET.
Updated the wording from Select Any to Select up to one for the MIM Capacitors options, on page 12.
Added new footnote (#9) for additional clarity on features selection for designs which contain both single
and dual MIMs.
Section 1.5: Updated approver list for Wafer Finishing (Bromont) and Kerf and Reticle Design to reflect
changes in personnel.
Section 1.5: Added date of approval information for each approver in section 1.5 , Document Change
Approval on page 16
Section 1.6: Added another row to the table in section 1.6 , Summary of Changes on page 17.

Technology Introduction Change list
Section 2.2: Added layer $XYCOORD, PAD1, and %OUTLINE to Restricted Mask or Dummy Design and
Utility Levels on page 44, per request from Al Norris. The intent is to get these levels into the technology
mapfile for future testsite work.
Section 2.2: Added layers QQ and HQ to Restricted Mask or Dummy Design and Utility Levels on page
44, in support of RL09 on page 83.
Section 2.7: Modified truth table rows for devices HIVT 3.3V NFET on page 69 and HIVT 3.3V PFET 1 on
page 69.
Section 2.8: Added rule RL09a on page 83.
Section 2.10: Updated the wirebond and C4 density rules in Table 19, Global Pattern Density Rules, on
page 87. PDDV on page 87, PDFV on page 87, and PDLV on page 87 now check for the intersection of
{DV, LV, FV} with the last metal for the appropriate area calculation. Also moved all appropriate footnotes
into the Notes column of the table.
Section 2.10: Updated rule names in section titled RX and PC General Pattern Density Requirements on
page 88. Rule names EPDL_RX, EPDG_PC, and EPDL_PC account for all of the changes.
Section 3.1: Updated rule classification for the following rules: 500 on page 133, 602 on page 141, 650a
on page 149, 655b on page 150, FT8 on page 168, and 990E1a on page 320. All rules were changed to
class a rules. Updated rule classification to d for the following recommended rules: LUP13aR on page
179 and LUP13bR on page 179.
Section 3.1: Added footnote to EPDL_RX to account for the 21% DRC checking cutpoint which is different
than the value listed in the DM.
Section 3.1: Added rule EPDL_PC to supersede rule 42aR for local PC pattern Density checking.
Changed the checking box size to reflect a relaxation to this check.
Section 3.1-3.8: Changed rule names from EPD_xx to EPDL_xx, where xx is the level name. EPD stands
for Estimated Pattern Density. EPDL stands for Estimated Pattern Density - Local and is a more accu-
rate description for the types of checking that will be done. Added additional information on exclusions
specific to these rules as well.
Section 3.1: Modified ground rule T3W594b on page 108 to include BB in the Substrate Contact Defini-
tion.
Section 3.1: Modified the wording for rules T3WQCAP24 on page 109, T3WQCAP24a on page 109,
T3WQCAP24b on page 109, and T3WQT8e on page 109 to specify that each MIM needs to be tied down
at the first wiring level above the MIM. For QCAP24 rules that is level E1. For QT8e rules that is level OL.
Section 3.8: Added new estimated pattern density checking rules for 1x Cu levels (M1-M6) which touch
(IND, IND_FILT, or BONDPAD). Rule EPDLi_M1 on page 137, EPDLi_M2 on page 143, EPDLi_M3 on
page 143, EPDLi_M4 on page 143, EPDLi_M5 on page 144, and rule EPDLi_M6 on page 144.
Section 3.8: Added new estimated pattern density checking rules for 2x Cu levels MQ and MG. Rule
EPDL_MQ on page 151 and rule EPDL_MG on page 152. Additional rule details found in the appendix:
Rule EPDL_MQ on page 573 and Rule EPDL_MG on page 574. Added new estimated pattern density
checking rules for 2x Cu levels MQ and MG which touch IND, IND_FILT, or BONDPAD. Rule EPDLi_MQ
on page 151 and rule EPDLi_MG on page 152.
Section 3.8: Added documentation for the QT exemption to rules EPDL_MQ on page 151, EPDLi_MQ on
page 151, EPDL_MG on page 152 and EPDLi_MG on page 152.

Section 3.8: Combined rules LY6 and LY6a into 1 rule. LY6a was moved into a footnote for design rule LY6
on page 167.
Section 3.8: Combined rules E2 and E3 into 1 rule. E3 was moved into a footnote for design rule E2 on
page 171.
Section 3.8: Updated design rule 782 on page 175 to include layers IND and BFMOAT.
Section 3.10: Updated the wording for rule LUP14TW on page 179.
Section 3.10: Added rule clarification note for LUP09a through LUP10b, with a specific ratio equation,
found in Section , Notes: on page 180.
Section 3.11: Add references to new rules ELUP01TW and ELUP01BTW in section JEDEC JESD78
Latchup requirements on page 184.
Section 3.11: Added three new rules in Table 60, External Latchup Rules, on page 184: ELUP00 on
page 184, ELUP01TW on page 188, and ELUP01BTW on page 188. Modified the wording for rules
ELUP01 on page 184 through ELUP10B on page 187.
Section 3.11: Updated wording in section Notes: on page 189.
Section 3.12: Deleted the following ESD rules. ESD02a on page 192, ESD03a on page 192, ESD04 on
page 192, ESD04a on page 193, ESD05 on page 193, ESD06 on page 193, ESD06a on page 193,
ESD06b on page 193, ESD06c on page 193, ESD06d on page 193, ESD06e on page 193, ESD06f on
page 193, ESD11a on page 193, ESD11bR on page 193, ESD11dR on page 193, ESD11eR on page
193, ESD12f on page 193, ESD12g on page 194, ESD15a on page 194, ESD15b on page 194,
ESD19aa on page 194, ESD19ab on page 194, ESD19ac on page 194, ESD31a on page 195, ESD31b
on page 195, ESD31c on page 195, ESD32a on page 195, ESD32b on page 195, ESD32bR on page
195, ESD32c on page 195, ESD33 on page 195, ESD34a on page 195, ESD34b on page 195, ESD34c
on page 195, ESD35a on page 195, ESD35b on page 195, ESD35c on page 195, ESD39 on page 195,
ESD40 on page 195. Updated the NOTES section by removing any references to the deleted rules.
Section 3.12: Removed Figure ESD Back-End-Of-Line Finger Methodology.
Section 3.12: Modified rule ESD16 on page 194 by updating the resistance calculation. The equation
listed in the rule now includes end resistance in the calculation. Removed a referenced to rule ESD19
from the rule wording.
Section 3.12: Reworded rule ESD30 on page 195 per request from the IBM ESD team.
Section 3.12: Add definitions for HBM double diode and CDM resistor to clarify the details associated with
reworded rule ESD30 on page 195. Also added two footnotes to rule ESD30.
Section 3.20: Modified ground rule KX9 on page 225 to remove the level QQ. This change is driven by the
obsolescence of levels QQ and HQ.
Section 3.24: Modified rule XF10 on page 235 from XF within NW to XF must be within NW.
Section 3.25: Added rule JN03 on page 236. Updated rules JN04a on page 236 and JN04b on page 236.
Removed rules JN04aR on page 236, JN04bR on page 236, and JN09 on page 236 because they have
been superseded by pre-existing XE-specific rules.

Technology Introduction Change list
Section 3.25: Added rule JP03 on page 236. Updated Rules JP04a on page 237 and JP04b on page 237.
Removed rules JP04aR on page 237, JP04bR on page 237, and JP09 on page 237 because they have
been superseded by pre-existing XF-specific rules.
Section 3.29: Added rule DS003 on page 249.
Section 3.31: Renamed sub-sections within Section 3.31 , Metal-to-Metal (MIM) Capacitor Layout
Rules on page 251 to more clearly state which MIM types are available by BEOL metallization option.
Section 3.31: Modified the wording for rules QCAP24 on page 255, QCAP24a on page 255, QCAP24b on
page 255, and QT8e on page 260 to specify that each MIM needs to be tied down at the first wiring level
above the MIM. For QCAP24 rules that is level E1. For QT8e rules that is level OL.
Section 3.31: Modified the wording of rule KT7 on page 258 to be less ambiguous. Original wording was
HT not touching MIM_HK; Updated wording is HT touching MIM_NI.
Section 3.31: Created 2 new tables to list the metallization specific QT/HT/KT specific rules. Table 92,
QT and HT and KT Layout Rules for the OL with LD metallization, on page 260.
Section 3.35: Modified the maximum number of C4s allowed for all 4on8 and 4on9 designs to 9000 from
7100 in Table 100 on page 278, Table 101 on page 284, Table 102 on page 288, and Table 103 on
page 293.
Section 3.35: Created new rule LD913 on page 289 to eliminate the use of VV vias under C4 pads.
Section 4.18: Updated the following tables NW Resistor values.
Voltage Coefficient in table Table 140, Resistor Design Specifications, on page 379 from 1.0 to 1.68.
dw (m) in table Table 141, Resistor Design Parameters, on page 382 from 0.44 to -0.02.
ksh, msh in table Table 143, Self-Heating Coefficients, on page 384 from 160, 0.63 to 120, -0.05.
respectively.
Section 4.27: Modified the value for Leakage @ -1V on page 406 for the Schottky Barrier Diode from
Nom=2V to Nom=0.1V. Also modified the Min, Nominal, and Max values for Leakage Coeff. on page 407.
Section 4.32: Updated moat resistance values, which were off by a factor of 10x. Changed all of the val-
ues in column Moat resistance (ohm-um) in Table 181, Moat Parameters, on page 430. Also modified
the following lines which are found above said table:
Width of moat =100 um; Rmoat=50,000 ohm-um on page 430
Resistance = 50,000/2224 = 22.5 ohms on page 430

Section 4.34: Added two columns to Table 185, Dual Layer Series Stacked Inductor Design Specifica-
tions on page 434. The columns include information specific to the AM and OL with LD Metallization
Options.
Section 4.34: Added one column to Table 186, Single Layer Inductor Design Specifications on
page 434. The pre-existing column was renamed to BF/M1 Standard Spiral and the new column was
named BF/M1 Symmetric Inductor.
Section 4.34: Added one column to Table 187, Parallel Stacked Inductor Design Specifications on
page 434. The pre-existing column was renamed to BF/M1 Parallel Spiral and the new column was
named BF/M1 Symmetric Inductor.

Section 4.34: Added Table 188, Parallel Stacked Inductor Design Specifications on page 435. The
pre-existing column was renamed to BF/M1 Standard Spiral and the new column was named BF/M1
Symmetric Inductor.
Section 4.39: Fixed a typo in Section 4.39.10 , VMAX for Hi-K MIM (for OL with LD Metallization Option)
on page 456. Changes the subscripts from VHQ and VQQ to VHK and VQK respectively.
Section 5.3: Changed two headings to be inclusive of the Thick Oxide 3.3V devices:
Section , Non-conducting hot carriers: Regular I/O Thick Oxide (DG, 52A) and Thick Oxide 3.3V I/O
N-channel Devices on page 469
Section , Non-conducting hot carriers: Regular I/O Thick Oxide (DG) and Thick Oxide 3.3V I/O
P-channel Devices on page 476
Section 7.3: Added Section 7.3 , ESD Schematic level checks on page 524.
Section Q.1: Updated three PCF check rules. PD2a on page 562 has an updated checking box size
(400m) and stepping size (200m). PD5c, on page 563 and PD5g 6, on page 563 both have new foot-
notes which require that failing boxes must touch another failing box in order to be reported.
Section Q.1: Updated section heading and table headings from Predictive to Estimated. Section Q.1.1,
Estimated Pattern Density Generation on page 565. Table 247, Estimated Pattern Density Rules, on
page 565.
Section Q.1: Added new equations for rules EPDL_MQ on page 573 and Rule EPDL_MG on page 574.
Section Q.1: Modified the Current Practice column for rules DS581 & DS582 from 1.80 to 1.00.
Section Q.1: Added exclusion footnotes and updated rule names for rules EPDL_RX, EPDG_PC,
EPDL_Mx (where x=1,2,3,4,5,6,Q,G). Added new alternate checking rules (EPDLi_Mx where
x=1,2,3,4,5,6,Q,G) for boxes which touch IND, IND_FILT, or BONDPAD.
Section Q.1: Added PCING to the final equation used to calculate PC pattern density in rule EPDG_PC.

Technology Introduction CMOS8RF (CMRF8SF) Cross Sections
1.9 CMOS8RF (CMRF8SF) Cross Sections

The following figures are schematic cross sections. The figures are not drawn to scale and many of the
detailed process steps have been omitted. The figures are intended to give the reader a basic picture of the
process flow and mask levels used.
1.9.1 LM Last Metal Cross Section

The allowed LM last metal BEOL options are in Table 11, LM last metal Back End Of Line (BEOL) Metalliza-
Polyimide
DV
Nitride
Oxide TD
TV
LM
VQ
MQ
VL
M4
V3
M3
V2
M2
V1
M1 M1
CA CA
salicide PC PC
RX Isolation RX
N-well
Figure 1. Cross Section of a 6 Level of Metal LM Last Metal Option (4 Thin Mx; x=1,2,3,4 and 2 Thick = MQ, LM) with
Wirebond Final Passivation (not drawn to scale).

Technology Introduction CMOS8RF (CMRF8SF) Cross Sections IBM
1.9.2 MA Last Metal Cross Section
The allowed MA last metal BEOL options are in Table 12, MA last metal Back End Of Line (BEOL) Metalliza-
tion Options on page 65.
Nitride LV (C4)
Polyimide
DV (wirebond)
Oxide
MA
F1 F1
E1
FT FT
LY LY
FY FY
MQ MQ
VL VL
M2 M2 M2
V1 salicide V1
M1 M1
salicide
CA CA
PC PC
RX Isolation RX
N-WELL
Figure 2. Cross Section of the 6 Level of Metal MA Last Metal Option (2 Thin Mx; x=1,2 and 1 Thick = MQ and RF Metal
= LY, E1, MA) with either DV or LV Final Passivation (not drawn to scale)

Technology Introduction CMOS8RF (CMRF8SF) Cross Sections
1.9.3 OL with LD Last Metal Cross Section

The allowed LD last metal BEOL options are in Table 13, OL with LD last metal Back End Of Line (BEOL)
Metallization Options on page 66.
Nitride LV (C4)
Polyimide
DV (wirebond)
Oxide
LD
VV VV
OL
JT JT
MQ MQ
VL VL
M2 M2 M2
V1 salicide V1
M1 M1
salicide
CA CA
PC PC
RX Isolation RX
N-WELL
Figure 3. Cross Section of the 5 Level of Metal LD Last Metal Option (2 Thin Mx; x=1,2 and 1 Thick = MQ and RF Metal
= OL, LD) with either DV or LV Final Passivation (not drawn to scale)

Technology Introduction CMOS8RF (CMRF8SF) Cross Sections IBM
1.9.4 AM Last Metal Cross Section
The allowed AM last metal BEOL options are in Table 14, AM last metal Back End Of Line (BEOL) Metalliza-
tion Options on page 67.
Nitride LV (C4)
Polyimide
DV (wirebond)
Oxide
AM
FQ FQ
MQ MQ
VL VL
M5 M2 M5
V4 V4
M4 M2 M4
V3 V3
M3 M2 M3
V2 V2
M2 M2 M2
V1 salicide V1
M1 M1
salicide
CA CA
PC PC
RX Isolation RX
N-WELL
Figure 4. Cross Section of the 6 Level of Metal AM Last Metal Option (5 Thin Mx; x=1,2,3,4,5 and 1 Thick = MQ and RF
Metal = AM) with either DV or LV Final Passivation (not drawn to scale)

Physical Layout Information Design Grid
2.0 Physical Layout Information
2.1 Design Grid

CMOS8RF (CMRF8SF) designs are required to be laid out on a 0.01- m grid (see Table 17, Geometry
Restrictions, on page 82 and Section 3.41 , No Polyimide Final Passivation option on page 332 for more
information).
2.2 Mask Level Definitions

Shapes drawn by a customer on any level other than those listed in Table 2 as Design Levels will not be
included in the associated Mask Level. In order to prevent level name conflicts during Design Services, Data
Preparation and Kerf Merge, the reserved design levels in Table 3, Design Service and Data Preparation
Levels (Restricted) on page 37 and Table 4, KERF Dummy Design Levels (Restricted) on page 43 can not
be used by the designer. See Rules RL01 through RL09a in Table 18, Reserved Level Layout Rules on
page 83.
Appropriate metal and via levels must be submitted with CMOS8RF (CMRF8SF) designs as presented in
Section 2.6 , Mask Metallization Options on page 63.
.
Table 2. Mask and Design Level Definitions
Mask Design CDS CDS Description

Level Level name purpose
GDSII GDSII
number type
RX RX RX dg Shape = active area (gate oxide and N+/P+ diffused regions).
2 0
NS NS NS dg Shape = N+ Subcollector for the SBD. Use is OPTIONAL.
0 0
- RN RN dg Shape = N+ diffusion used to contact NS in the SBD. Used in

data prep only (not a mask layer) to merge on to the NW
23 0 mask. Use is OPTIONAL.
JD JD JD dg Shape = ion implant area for varactor HA device(s). Use is

OPTIONAL.
12 101
T3 T3 T3 dg Shape = T3 Isolation Well implant area. Use is OPTIONAL.
3 0
NW NW NW dg1 Shape = N-well region.
4 0

Physical Layout Information Mask Level Definitions IBM

GDSII GDSII
number type
LW LW LW dg Shape = N-well region for LVT PFET. Use is OPTIONAL
12 3
PV PV PV dg Shape = N-well region for LP PFET. Use is OPTIONAL.
12 31
PI PI PI dg 1 Shape = Triple Well NFET N type isolation and Pwell implant.

Use is OPTIONAL.
6 33
XW XW XW dg Shape = P-well region for LVT NFET. Use is OPTIONAL.
12 1
NV NV NV dg Shape = P-well region for the LP NFET. Use is OPTIONAL.
12 30
- BB BB dg Shape = Bipolar Block. Used to block Nwell, Pwell,

source/drain, and halo implants from BB regions to create
91 100 regions of high resistive path.This level is used to generate
BF, BP, BT, and BH.
DG DG DG dg Shape = areas which have a thicker gate (5.2nm) oxide. Use

is OPTIONAL.
12 4
PC PC PC dg 1 Shape = polysilicon line. (PC over RX within BP) over DG will

receive the p-channel Dual Gate device mask compensation.
7 0 (PC over RX outside of BP) over DG will receive the n-chan-
nel Dual Gate device mask comp. (PC not over RX) not over
PCING PCING dg DG will receive the polysilicon wiring mask comp.
7 4
PCFUS PC fuse
E
7 44
XE XE XE dg Shape = LDD for the 3.3V I/O nFET. Use is OPTIONAL.
12 41
XF XF XF dg Shape = LDD for the 3.3V I/O pFET. Use is OPTIONAL.
12 67

Use is further subject to the provisions on the back of the title page. Version Date: November 30, 2010
Page 28 of 580 IBM Confidential - Do Not Copy
Physical Layout Information Mask Level Definitions

GDSII GDSII
number type
JN JN JN dg Shape = N-well region for the 3.3V HiVt nFET. Use is

OPTIONAL.
12 127
JP JP JP dg Shape = N-well region for the 3.3V HiVt nFET. Use is

OPTIONAL.
12 128
BP BP BP dg Shape = areas which are blocked from the n+ source/drain
implant (identifies PFETs, P+ junctions and substrate con-
10 0 tacts).
BN PD BN dev Shape = P+ implant area for contacts of high Resistance pol-

ysilicon resistor. The BN mask level is REQUIRED (see
11 1 Table 7, Masks for Non-Design Levels on page 58). Use of
design level PD is OPTIONAL (see BN row in Table 8,
Shape Manipulation Prior to Mask Write on page 59).
RR RR RR dg Shape = High value poly resistor. Use is OPTIONAL.
12 107
RP RP RP dg Shape = Precision poly resistor. Use is OPTIONAL.
7 9
OP OP OP dg Shape = areas which are blocked from silicide formation over

PC and RX, creating a resistor. Use is OPTIONAL.
37 0
CA CA CA dg 1 Shape = square stud contact. CA connects either RX or PC

CF2 to M1.
14 0
CABAR CABAR dg 1 Shape = rectangular stud contact. CABAR is allowed only in

the Chip Guard Ring and Part Number / Labels field. See
14 1/59 these rules for clarification.
M1 M1 M1 dg/vdd/ Shape = first-level thin metal lines.

D13 gnd 1
15 0/0/0
V1 V1 V1 dg 1 Shape = square vias for connecting M1 to M2.

VE4
16 0
V1BAR V1BAR dg 1 Shape = rectangular vias for connecting M1 to M2. V1BAR is

allowed only in the Chip Guard Ring.
16 1


GDSII GDSII
number type
M2 M2 M2 dg/vdd/ Shape = second-level thin metal lines.

gnd 1
17 0/0/0
V2 V2 V2 dg 1 Shape = square vias for connecting M2 to M3.

Use is REQUIRED for LM BEOL Metallization
18 0
Use is OPTIONAL for MA or OL with LD BEOL Metallization

18 1
M3 M3 M3 dg/vdd/ Shape = third-level thin metal lines.

gnd 1 Use is REQUIRED for LM BEOL Metallization
19 0/0/0 Use is OPTIONAL for MA or OL with LD BEOL Metallization
V3 V3 V3 dg 1 Shape = square vias for connecting M3 to M4. Use is

OPTIONAL.
20 0

20 1
M4 M4 M4 dg/vdd/ Shape = fourth-level thin metal lines. Use is OPTIONAL.

gnd 1
21 0/0/0
V4 V4 V4 dg 1 Shape = square vias for connecting M4 to M5 only for the LM

or OL with LD metallization options (See Table 11, LM last
22 0 metal Back End Of Line (BEOL) Metallization Options, on
page 64 or Table 13, OL with LD last metal Back End Of
Line (BEOL) Metallization Options, on page 66). Use is
OPTIONAL.

22 1
M5 M5 M5 dg/vdd/ Shape = fifth-level thin metal lines only for the LM or OL with
gnd 1 LD metallization options (See Table 11, LM last metal Back
End Of Line (BEOL) Metallization Options, on page 64 or
31 0/0/0 Table 13, OL with LD last metal Back End Of Line (BEOL)
Metallization Options, on page 66). Use is OPTIONAL.


GDSII GDSII
number type
V5 V5 V5 dg 1 Shape = square vias for connecting M5 to M6 only for the LM

metallization options (See section Table 11. , LM last metal
32 0 Back End Of Line (BEOL) Metallization Options on page 64).
Use is OPTIONAL

allowed only in the Chip Guard Ring. (See section Table 11. ,
32 1 LM last metal Back End Of Line (BEOL) Metallization
Options on page 64).
M6 M6 M6 dg/vdd/ Shape = sixth-level thin metal lines only for the LM metalliza-
gnd 1 tion options (See section Table 11. , LM last metal Back End
Of Line (BEOL) Metallization Options on page 64). Use is
44 0/0/0 OPTIONAL
Kx, Kx, Kx dg Shape = BEOL Metal Resistor contacted using the VL via.
where where Only one Kx mask is used per chip design, where x = the last
x= thin (1x) metal level specified in the BEOL stack option per
x=2 12 130 Table 11 or Table 13. Use is OPTIONAL.
2,3,4,
5 or 6 x=3 12 131
x=4 12 132
x=5 12 133
x=6 12 134
VL VL VL dg 1 Shape = square vias for connecting M2, M3, M4 to MQ for

MA metallization options (See section Table 12. , MA last
35 0 metal Back End Of Line (BEOL) Metallization Options on
page 65) or M3, M4, M5, M6 to MQ for the LM metallization
options (See section Table 11. , LM last metal Back End Of
Line (BEOL) Metallization Options on page 64).
VLBAR VLBAR dg 1 Shape = bar vias for connecting M2, M3, M4 to MQ for MA
metallization options (See section Table 12. , MA last metal
35 1 Back End Of Line (BEOL) Metallization Options on page 65)
or M3, M4, M5, M6 to MQ for the LM metallization options
(See section Table 11. , LM last metal Back End Of Line
(BEOL) Metallization Options on page 64).
MQ MQ MQ dg/vdd/ Shape = first level of thick wiring.

gnd 1
34 0/0/0


GDSII GDSII
number type
VQ VQ VQ dg 1 Shape = square vias for connecting MQ to MG for MA metal-

lization options (See section Table 12. , MA last metal Back
33 0 End Of Line (BEOL) Metallization Options on page 65) Use
is OPTIONAL for MA metallization option; or
Shape = square vias for connecting MQ to (MG or LM) for the
LM metallization options (See section Table 11. , LM last
metal Back End Of Line (BEOL) Metallization Options on
page 64).
VQBAR VQBAR dg 1 Shape = rectangular vias for connecting MQ to MG for MA

metallization options (See section Table 12. , MA last metal
33 1 Back End Of Line (BEOL) Metallization Options on page 65)
or MQ to (MG or LM) for the LM metallization options (See
section Table 11. , LM last metal Back End Of Line (BEOL)
Metallization Options on page 64). VQBAR is allowed only in
the Chip Guard Ring (See Table 114, Chip Guard Ring
Rules on page 319).
MG MG MG dg/vdd/ Shape = Second level of thick wiring. Use is OPTIONAL

gnd 1
65 0/0/0
VG VG VG dg 1 Shape = square vias for connecting MG to LM for the LM

Use is OPTIONAL
VGBAR VGBAR dg 1 Shape = rectangular vias for connecting MG to LM for the LM

VGBAR is allowed only in the Chip Guard Ring. (See
Table 114, Chip Guard Ring Rules on page 319).
LM LM LM dg/vdd/ Shape = Last level of thick wiring for the LM metallization

gnd 1 options (See section Table 11. , LM last metal Back End Of
Line (BEOL) Metallization Options on page 64).
24 0/0/0
QT or QT QT dg For mask level QK (Design Level QT), Shape = Bottom plate

QK of the Hi-K MIM for OL with LD metallization option.
30 4 For mask level QT (Design Level QT), Shape = Bottom plate
of the Single or Dual MIM for OL with LD metallization option
(See Table 13, OL with LD last metal Back End Of Line
(BEOL) Metallization Options, on page 66).
Use is OPTIONAL.


GDSII GDSII
number type
HT or HT HT dg For mask level HK (Design Level HT), Shape = Top plate of

HK the Hi-K MIM for OL with LD metallization option.
30 20 For mask level HT (Design Level HT), Shape = Top plate of
the Single Nitride MIM or middle plate of the Dual Nitride MIM
for OL with LD or AM metallization options.
(See Table 13, OL with LD last metal Back End Of Line
(BEOL) Metallization Options, on page 66.
Use is OPTIONAL.
KT KT KT dg Shape = Top plate of Dual Nitride MIM for OL with LD or AM

metallization options. (See Table 13, OL with LD last metal
30 9 Back End Of Line (BEOL) Metallization Options, on page 66.
Use is OPTIONAL.
JT JT JT dg 1 Shape = square via for connecting MQ to OL (when MIM or

MG is not present) or MG to OL (when MIM is not present
141 0 and MG is present) or QT or HT or KT MIM plates to OL for
the OL with LD metallization option (See Table 13, OL with
LD last metal Back End Of Line (BEOL) Metallization
Options, on page 66).
JTBAR JTBAR dg 1 Shape = rectangular via for connecting MQ to OL (when MG

is not present) or MG to OL (when MG is present) for the OL
141 1 with LD metallization option (See Table 13, OL with LD last
metal Back End Of Line (BEOL) Metallization Options, on
page 66). JTBAR allowed only in Inductors or Chip Guard
Ring.
OL OL OL dg/vdd/ Shape = second to the last metal level above JT or JTBAR

gnd 1 via below, for the OL with LD metallization option (See
Table 13, OL with LD last metal Back End Of Line (BEOL)
140 0/0/0 Metallization Options, on page 66). OL is the last copper
metal wiring level above MQ (if MG is not present) or above
MG (if MG is present) copper metal levels below before the
VV or VVBAR via and LD last metal above.
VV VV VV dg 1 Shape = square via for connecting OL to LD for the OL with

LD metallization option (See Table 13, OL with LD last metal
70 0 Back End Of Line (BEOL) Metallization Options, on
page 66). VV used with both Wirebond and C4 terminal
options.
VVBAR VVBAR dg 1 Shape = rectangular via for connecting OL to LD for the OL

with LD metallization option (See Table 13, OL with LD last
page 66). VVBAR allowed only in Inductors. VVBAR is not
allowed in the Chip Guard Ring.


GDSII GDSII
number type
LD LD LD dg/vdd/ Shape = Last aluminum metal level for inductors, terminal

gnd 1 pads and wiring for the OL with LD metallization options (See
Table 13, OL with LD last metal Back End Of Line (BEOL)
183 0/0/0 Metallization Options, on page 66).
FY FY FY dg 1 Shape =square Analog Via for connecting MG or MQ level to

LY for MA metallization options (See Table 12, MA last
page 65).
FYBAR FY BAR 1 Shape =bar Analog Via for connecting MG or MQ level to LY

for MA metallization options (See Table 12, MA last metal
86 1 Back End Of Line (BEOL) Metallization Options, on
page 65).
FYBAR is allowed only in the Chip Guard Ring (See
Table 114, Chip Guard Ring Rules on page 319).
LY LY LY dg/vdd/ Shape = Third to the last metal level before E1 and after MQ
gnd 1 or MG levels for MA metallization options (See Table 12, MA
last metal Back End Of Line (BEOL) Metallization Options,
42 1/1/1 on page 65).
QY QY QY dg Shape = Aluminum MIM Capacitor Top plate for the single

Aluminum MIM or Mid Plate for the dual Aluminum MIM for
30 5 MA metallization options (See Table 12, MA last metal Back
End Of Line (BEOL) Metallization Options, on page 65). Use
of QY is OPTIONAL.
HY HY HY dg Shape = Top plate for the Dual Aluminum MIM for MA metal-
lization options (See Table 12, MA last metal Back End Of
30 21 Line (BEOL) Metallization Options, on page 65). Use of HY
is OPTIONAL.
FT FT FT dg 1 Shape =square via for connecting LY level to E1 for MA met-

allization options (See Table 12, MA last metal Back End Of
84 0 Line (BEOL) Metallization Options, on page 65).
FTBAR FT BAR 1 Shape =rectangular via for connecting LY level to E1 for MA

metallization options (See Table 12, MA last metal Back End
84 1 Of Line (BEOL) Metallization Options, on page 65).
E1 E1 E1 dg/vdd/ Shape = Second to the last metal level before MA and after
gnd 1 LY for MA metallization options (See Table 12, MA last
83 0/0/0 page 65).


GDSII GDSII
number type
L1 L1 L1 dg Shape = BEOL metal level resistor for MA metallization

options (See Table 12, MA last metal Back End Of Line
6 35 (BEOL) Metallization Options, on page 65). Use of L1T is
OPTIONAL.
F1 F1 F1 dg 1 Shape =square via for connecting E1 level to MA for MA met-

allization options (See Table 12, MA last metal Back End Of
128 0 Line (BEOL) Metallization Options, on page 65).
F1BAR F1 BAR 1 Shape =rectangular via for connecting E1 level to MA for MA
metallization options (See Table 12, MA last metal Back End
128 1 Of Line (BEOL) Metallization Options, on page 65).
MA MA MA dg/vdd Shape = Last metal level for inductors and pad transfer for
gnd 1 MA metallization options (See Table 12, MA last metal Back
End Of Line (BEOL) Metallization Options, on page 65).
81 0/0/0
FQ FQ FQ dg Shape = square via (1.6um thick) for connecting AM level to

MQ level for AM metallization options.
59 0
FQBAR FQ BAR Shape = rectangular via (1.6um thick) for connecting AM

level to MQ level for AM metallization options. FQBAR is
59 1 allowed only in the Chip Guard Ring (See Table 114, Chip
Guard Ring Rules on page 319).
AM AM AM dg/vdd/gnd Shape = 4um thick Aluminum last metal layer.
53 0/0/0
TD TD TD dg/vdd/ Shape = AlCu transfer pad from last wiring level to final pas-
gnd 1 sivation terminal opening required for C4 terminal pad con-
nections, for the LM metallization options (See Table 11, LM
36 0/0/0 last metal Back End Of Line (BEOL) Metallization Options,
on page 64).
TD is drawn for wirebond and automatically generated in by
Data Preparation for C4 Designs. Table 9, Shape Manipula-
tion Prior to Mask Write (for LM last metal), on page 62
TV TV TV dg 1 Shape = Via opening in the oxide/nitride passivation above

the last level of metal. Required for C4 terminals, probe pads,
26 0 wirebond, etc., for the LM metallization options (See
Table 11, LM last metal Back End Of Line (BEOL) Metalliza-
tion Options, on page 64).


GDSII GDSII
number type
FV FV FV dg 1 Shape = opening in the final polyimide passivation. Required

over C4 terminals and probe pads for the LM metallization
27 0 options (See Table 11, LM last metal Back End Of Line
(BEOL) Metallization Options, on page 64).
DV DV DV dg 1 Shape = Wirebond opening in the final polyimide passivation

for the for the LM metallization options (See Table 11, LM
27 1 last metal Back End Of Line (BEOL) Metallization Options,
on page 64) or the oxide/nitride/polyimide passivation to MA
for MA metallization options (See Table 12, MA last metal
Back End Of Line (BEOL) Metallization Options, on page 65)
or the oxide/nitride/polyimide passivation to LD for the OL
with LD metallization options (See Table 13, OL with LD last
page 66).
LV LV LV dg 1 Shape = C4 opening in the final polyimide and

oxide/nitride/polyimide passivation to MA for MA metallization
28 0 options (See Table 12, MA last metal Back End Of Line
(BEOL) Metallization Options, on page 65) or the
oxide/nitride/polyimide passivation to LD for the OL with LD
metallization options (See Table 13, OL with LD last metal
Back End Of Line (BEOL) Metallization Options, on
page 66).
1. DRC will check to insure that the net purpose is not outside or straddling the dg (drawing) or BAR purpose on these design levels.
2. CF is generated from CA for special SRAM designs. Contact your IBM Technical Representative for more information.
3. D1 is generated from M1 for special SRAM designs. Contact your IBM Technical Representative for more information.
4. VE is generated from V1 for special SRAM designs. Contact your IBM Technical Representative for more information.

The mask levels, identified in Table 3, Design Service and Data Preparation Levels (Restricted), on
page 37, are for IBM use only. Designers shall not specify new mask levels, nor use design levels, similar to
those identified in Table 3.
Table 3. Design Service and Data Preparation Levels (Restricted)
Restricted Use CDS CDS Description Associated With

Level1 name pur-
pose
GDSII GDSII
number type
AMFILL AM fill Reserved Level Name. May be used by Design Services,

IBM to fill empty space on the AM mask Pattern Density
53 35 level to meet pattern density requirements
of the manufacturing process.
BU, PU, TU, UP, - - Reserved Level Names for masks not sup- Data Preparation
UT, DU ported in this technology
DNIRxx2 - - Reserved Level Names Mask Merge
DPWAIVxx 2 - - Reserved Level for IBM use only, used for Dataprep
Dataprep layout checking (xx=any combi-
nation of alphanumeric characters)
E1FILL3 E1 fill Reserved Level Name. May be used by Design Services,

IBM to fill empty space on the E1 mask Pattern Density
83 35 level to meet pattern density requirements
of the manufacturing process.
FUSE 3,4 OUT- fuse Reserved Level name for un-supported Design Services
LINE feature in this technology
12 56
LMFUSE - - Reserved Level name for un-supported Data Preparation

MTFUSE feature in this technology and Design Ser-
vices
FL, FLBAR, F0, - - Reserved Level Name for masks or fea- Data Preparation
F0BAR, LB, tures not supported in this technology and Design Ser-
LBEXCLUD, vices
LBFILL,
LBTRANS, TT,
VVDUMMY
JTHOLE 3 JT HOLE Reserved Level Name. JTHOLE is not Data Preparation

used in the technology. and Design Ser-
141 51 vices.


Level1 name pur-
pose
GDSII GDSII
number type
KERFEXCL 3,5 KER- dg Reserved Level name for IBM use only, Kerf Design
FEXCL associated with optical and alignment
structures in the manufacturing kerf. Used
101 250 to inhibit xxFILL generation inside certain
optical and alignment marks. KERFEXCL
is verified during DRC per Rule RL07a in
Table 18, Reserved Level Layout Rules,
on page 83 since it should not be present
in a production chip design except in the
IBM developed KERF (outside
CHIPEDGE)
LDFILL 3 LD fill Reserved Level Name. Used to fill empty Design Services,
space on the LD mask level to meet pat- Pattern Density
183 35 tern density requirements of the manufac-
turing process.
LMCHEXCL 3 LM CHEXC Placed over specific areas of the chip that LM Hole
L can not receive LM Hole shapes. Exclusion
24 47
LMEXCLUD 3 24 2 Reserved Level Name. Automatically gen- LMFILL exclu-

erated by Design Services sion.
LMFILL 3 LM fill Reserved Level Name. Used to fill empty Design Services,
space on the LM mask level to meet pat- Pattern Density
turing process.
LMHOLE 3 LM HOLE Reserved Level for IBM use only. Used to LM Density
check the interior of wide LM wires to meet
24 1 the pattern density layout requirements of
the Copper manufacturing process.
LMPLANE - - Reserved Level Name, May be used by Design Services

MxPLANE IBM Design Services to identify Mx or LM
(x=1,2,3,4,5,6,Q, wires that exceed groundrule maximum
G) width requirements.
LYFILL 3 LY fill Reserved Level Name. May be used to fill Design Services,
empty space on the LY mask level to meet Pattern Density
42 35 pattern density requirements of the manu-
facturing process.


Level1 name pur-
pose
GDSII GDSII
number type
MAFILL 3 MA fill Reserved Level Name. May be used to fill Design Services,
empty space on the MA mask level to Pattern Density
81 35 meet pattern density requirements of the
manufacturing process.
ME - - Reserved Level Name for un-used mask Dataprep

MECHEXCL or dummy design levels in this technology
MEHOLE
MEEXCLUD
MEPLANE
MT - - Reserved Level Name for un-used mask Dataprep

MTCHEXCL or dummy design levels in this technology
MTDUMHOL
MTEXCLUD
MTHOLE
MTPLANE
MxCHEXCL 3 Mx CHEXC Reserved Level for IBM use only. Placed Mx Hole Exclu-
L over specific areas of the chip that can not sion
receive Mx (x=1,2,3,4,5,6,Q,G) Hole
(x=1) 15 47 shapes.
(x=2) 17 47
(x=3) 19 47
(x=4) 21 47
(x=5) 31 47
(x=6) 44 47
(x=Q) 34 47
(x=G) 65 47
MxDUMHOL, - - Reserved Level for IBM use only. MxDUM- Mx Hole Exclu-
where x = HOL is not used in the technology. sion
1,2,3,4,5,6


Level1 name pur-
pose
GDSII GDSII
number type
MxEXCLUD 3 Mx exclude Reserved Level Name. Automatically gen- MxFILL exclu-

erated by Design Services sion.
(x=1) 15 2
(x=2) 17 2
(x=3) 19 2
(x=4) 21 2
(x=5) 31 2
(x=6) 44 2
(x=Q) 34 2
(x=G) 65 2
MxFILL 3 Mx fill Reserved Level Name. Used to fill empty Design Services,
space at the corresponding mask level Pattern Density
(x=1) 15 35 (first two letters or numbers in the Use
Level Name) to meet pattern density
(x=2) 17 35 requirements of the manufacturing pro-
cess.
(x=3) 19 35
(x=4) 21 35
(x=5) 31 35
(x=6) 44 35
(x=Q) 34 35
(x=G) 65 35


Level1 name pur-
pose
GDSII GDSII
number type
MxHOLE 3, Mx HOLE Reserved Level for IBM use only. Used to Mx Density
check the interior of wide Mx
(x=1) 15 1 (x=1,2,3,4,5,6,Q G) wires to meet the pat-
tern density layout requirements of the
(x=2) 17 1 Copper manufacturing process.
(x=3) 19 1
(x=4) 21 1
(x=5) 31 1
(x=6) 44 1
(x=Q) 34 1
(x=G) 65 1
NIXxx 2 - - Reserved Level Names Data Preparation
NOKERF - - Reserved Level Name Data Preparation
NONIAGxx - - Reserved Level Names Data Preparation
NR 3 NR dg Reserved Level Name for masks not sup- Data Prepara-

ported in this technology tion, DRC
12 8
OLCHEXCL 3 OL chexcl Reserved Level Name. OLCHEXCL is not Design Services.

used in the technology.
140 47
OLEXCLUD 3 OL TRANS Reserved Level for IBM use only. Shape DRC/Design Ser-
Identifies Transmission Lines Fill Exclu- vices
140 2 sion
OLFILL 3 OL fill Reserved Level Name. Used to fill empty Design Services,
space on the OL mask level to meet pat- Pattern Density
turing process.
OLHOLE 3 OL HOLE Reserved Level Name. OLHOLE is not Design Services.

used in the technology.
140 1
PCFILL 3 7 35 Reserved Level Name. Used to fill empty Design Services,

space on the PC mask level to meet pat- Pattern Density
tern density requirements of the manufac-
turing process.


Level1 name pur-
pose
GDSII GDSII
number type
PR 3 PR dg Reserved Level Name for masks not sup- Data Prepara-

ported in this technology tion, DRC
12 9
RXFILL 3 2 35 Reserved Level Name. Used to fill empty Design Services,

space on the RX mask level to meet pat- Pattern Density
tern density requirements of the manufac-
turing process.
SRAMCA 3 CA SRAM Reserved Level Name Design Kit
14 45
VxFILL - - Reserved Level Names for un-supported Design Services

(x=1,2,3,4,5) feature in this technology
VA - - Reserved Level Name for un-used mask Dataprep

VABAR or dummy design levels in this technology
VAHOLE
VM
VMBAR
VMHOLE
VxHOLE 3 Vx HOLE Reserved Level Names used to tailor Vx in Dataprep

the presence of metal HOLE shapes.
(x=1) 16 51
(x=2) 18 51
(x=3) 20 51
(x=4) 22 51
(x=5) 32 51
(x=L) 35 51
(x=Q) 33 51
(x=G) 64 51
xB (x - - Reserved Level Names Mask House Pro-

=1,2,3,4,5,6,7,8) cess Control
xxANCHOR 2 - - Reserved Level Names Data Preparation
xxCUS 2 - - Reserved Level Names Data Preparation


Level1 name pur-
pose
GDSII GDSII
number type
xxNOTCH 2 - - Reserved Level Names Data Preparation
xxOPC 2 - - Reserved Level Names Data Preparation
xxOPCHOLE 2 - - Reserved Level Names Data Preparation
1. Unless otherwise specified, all levels in this table are not in the IBM Design Kit Technology File.
2. xx = any combination of one or two alphabetic characters representing the Design or Mask Level names identified in Table 2, Mask
and Design Level Definitions, on page 27.
3. Level is included in the Design Kit Technology File.
4. For additional information on FUSE, see Rule RL07a in Table 18, Reserved Level Layout Rules, on page 83.
5. For additional information on KERFEXCL, see Table 4, KERF Dummy Design Levels (Restricted), on page 43 and Rule RL07a
in Table 18, Reserved Level Layout Rules, on page 83.
The levels, identified in Table 4, KERF Dummy Design Levels (Restricted), on page 43, are for IBM use
only. The levels in Table 4can not be used by designers. Designers shall not specify new mask levels similar
to those identified in Table 4.
Table 4. KERF Dummy Design Levels (Restricted)
Restricted Use Description Associated With

Level
KERFxxx1 Reserved Level for IBM use only, used in the Kerf Design
kerf design and merged during mask assembly.
KERFEXCL2 Reserved Level for IBM use only, associated Kerf Design
with optical and alignment structures in the man-
ufacturing kerf. Used to inhibit xxFILL genera-
tion inside certain optical and alignment marks.
KERFNUL Reserved Level for IBM use only, used in the Kerf Design
kerf design and merged during mask assembly
NEGMKS Reserved Level for IBM use only, used during Kerf Design and Mask
the auto kerf merge process during mask Merge
assembly of CN masks, associated with data
extremes.

Table 4. KERF Dummy Design Levels (Restricted)
Restricted Use Description Associated With

Level
POSMKS Reserved Level for IBM use only, used during Kerf Design and Mask
the auto kerf merge process during mask Merge
assembly of CP masks, associated with data
extremes.
FRAME Reserved Level for IBM use only, Reserved Kerf Design and Mask
Level, used during the auto kerf merge process Merge
during mask assembly of CP masks, associated
with shutter blade positioning.
1. xxx = any combination of one, two or three alpha-numerics.
2. For additional information on KERFEXCL, see Table 3, Design Service and Data Preparation Levels (Restricted),
on page 37 and Rule RL07a in Table 18, Reserved Level Layout Rules, on page 83.
The mask levels, identified in Table 5, Restricted Mask or Dummy Design and Utility Levels, on page 44,
are prohibited for use in a layout design. Designers shall not specify new mask levels, nor use design levels,
similar to those identified in Table 5.
Table 5. Restricted Mask or Dummy Design and Utility Levels
Restricted Use CDS CDS Description Associated

Level1 name pur- With
pose
GDSII GDSII
number type
ESDUMMY_DEV2 ESDU- dev Reserved Level LVS

MMY
63 35
QE QE dg Reserved Level Name for alignment mask KERF

formerly used for LM MIMCAP (not sup-
30 10 ported, device using QE is obsolete).
VPPCAPMx Mx CAP Shape identifies Mx levels used for a leg- LVS/DRC/M

acy VNCAP device (Use is obsolete) odeling
(x=1) 15 89
(x=2) 17 89
(x=3) 19 89
(x=4) 21 89
(x=5) 31 89
(x=6) 44 89

Physical Layout Information Dummy Design Levels and Utility Levels
Table 5. Restricted Mask or Dummy Design and Utility Levels
Restricted Use CDS CDS Description Associated

Level1 name pur- With
pose
GDSII GDSII
number type
%OUTLINE OUT- BOOK Test Site only
LINE
60 3
PAD1 OUT- pad Test Site only

LINE
60 12
$XYCOORD OUT- DOC Test Site only

LINE
60 13
QQ QQ dg Obsolete MIM Bottom Plate.
30 30
HQ HQ dg Obsolete MIM Top Plate.
30 31
WVR3 WVR dg Used with Waiver Shapes for DRC DRC
62 0
1. Unless otherwise specified, all levels in this table are included in the IBM Design Kit Technology File and verified in DRC as
prohibited. For additional information on all levels, except WVR, see Table 89, MIM Capacitor Rules (for MA BEOL
metallization only), on page 254.
2. ESDUMMY_DEV is not verified as prohibited in DRC.
3. WVR is not verified as prohibited in DRC.
2.3 Dummy Design Levels and Utility Levels

The following levels are drawn by the designer. CHIPEDGE is required for all chip designs.

Physical Layout Information Dummy Design Levels and Utility Levels IBM
Table 6. Dummy Design Levels and Utility Levels
Design Level CDS CDS Description Associ-

name purpose ated
With
GDSII GDSII
number type
AM_COIL AM IND Shape identifies AM shapes used in inductor coils DRC

(within IND_FILT).
53 19
AMESD1 AM esd Shape = Label that is used to identify pads used for DRC
ESD and Latchup Rule checking
53 60
AMEXCLUD AM exclude Reserved level for IBM use only. Shape Identifies DRC/Dat
Fill Exclusion areas aprep
53 2
AMPIN AM pin Shape identifies ports of a device or a cell LVS/

DRC
53 32
BFMOAT BFMOA dg Used to block P-well and N-well implants from BFMOA
T BFMOAT regions to create regions of high resistive T device
path.
5 5
BFMOATIND BFMOA ind Used to identify the M1 ground plane inductor. DRC
T
5 4
BONDPAD2 PAD DEV Shape identifies Wirebond and C-4 pads which are DRC/
treated as devices and modeled. Modeling
41 25
CAESD_ CA esdf Placed over CA to enable CA area summing. ESD

FINGER Rules/
14 62 DRC
C4LV C4 dg Shape identifies LV shapes which are C-4s and not DRC/
octagonal wirebond pads. Any LV not under C4LV Data
41 0 defaults to being checked to wirebond rules.
prep
CELLSNR CELL- dg Shape = marker level for SRAM layout rule check- DRC
SNR ing and denotes stepping periodicity of SRAM cells
in an array. Note to designers: When SRAM verifi-
63 103 cation checking is performed, there is checking that
RX not in the SRAM cell can not touch CELLSNR.


name purpose ated
With
GDSII GDSII
number type
CHIPEDGE CHIP- dg A polygon shape on the dummy design level, chip

EDGE CHIPEDGE, enclosing all active chip design guard
shapes including the chip guard ring (chamfers are ring,
62 1 required on all four corners). It is used for merging chamfer,
kerf data. See section 3.37 , Chip Guard Ring and
kerf
Chamfer on page 318.
These rules assume dicing being done by IBM. If
this is done elsewhere, these rules must be defined
by the appropriate dicing organization.
DI DI dg Placed over p-type junctions used under for- Forward

ward-bias in bandgap reference circuits. Used for biased-
29 0 verification -- both design rule checking and layout diodes
vs. schematic.
DIODE DIODE dg Shape to identify diodes that should be recognized DRC/Mo

as devices rather than parasitics. deling
62 4
DIVPNP DI PNP Shape to identify 3-terminal diode device that also DRC/Mo
includes the DI dummy design and utility level. deling
12 236
DS_MATCH DS dg Used to force identical IBM Design Services-gener- Design

ated FILL and HOLE shapes for a given model, Services
212 95 regardless of the location, orientation, or mirroring
of different instances of the model.
E1_COIL E1 IND Shape identifies E1 shapes used in inductor coils DRC

(within IND_FILT).
124 19
E1ESD3 E1 esd Shape = Label that is used to identify pads used for DRC
83 60
E1EXCLUD E1 TRANS Reserved level for IBM use only. Shape Identifies DRC/Dat
Transmission Lines Fill Exclusion aprep
83 18
E1PIN E1 pin Shape identifies ports of a device or a cell LVS/

DRC
83 32
EDGELAYER edge- dg Shape assists in the identification of device dimen- LVS

Layer sions.
2 19


name purpose ated
With
GDSII GDSII
number type
EFUSE OUT- efuse Electrical fuse marking layer used for BH genera- Datap-
LINE tion. rep
12 98
ESD_CDM ESD cdm Special level that is placed over ESD CDM struc- ESD
tures rules
12 88
ESD_CLAMP ESD clamp Placed over Big NFET of the RC-triggered power ESD
clamp structures connected to a power supply pad. rules
12 227
ESDIODE ESDIO dg Special level that is placed over ESD diodes. ESD
DE rules
62 71
ESDUMMY ESDU- dg Special level that is placed over the ESD pad struc- ESD
MMY ture. rules
63 36
ESD_STACK ESD stack Shape placed over the stacked devices (separate ESD
diffusions required for meeting ESD design rules). Rules
12 219
FINE_WB OUT- fine_wb Used to define fine-pitch terminal pad opening for DRC
LINE the LM BEOL only
12 191
GRLOGIC GR- dg Shape identifies structures that are exempt from DRC
LOGIC recommended or more stringent layout rule check-
ing. Intended for IBM use in Digital Library offerings.
6 34 See Rule 110 and 110a, 110R and 110aR, 269a,
385aR, 717a, 717a1, 737b, OP30R, OP31R,
DG110a
GUARDRNG OUT- guardrng Marking layer for the chip guard ring. DRC
LINE
12 71
IBLK IBLK dg Shape = BT mask generation block shape used for Datap-
T3 Isolation Well Isolation or T3 Well N-Band con- rep
212 37 tact.


name purpose ated
With
GDSII GDSII
number type
INJECTOR_C INJEC- cde IBM Reserved level (do not use). Obsolete level External
DE TOR name formerly used over signal pads which require Latchup
ESD and latchup Rule checking. rules to
12 84 meet
CDE/HM
M
require-
ments
INJECTOR_J INJEC- jedec Special level placed over I/O structures connected External
EDEC TOR to a pad and used for checking Latchup
rules to
12 85 meet
JEDEC
require-
ments
IODUMMY IODUM dg IBM Reserved level (do not use). Obsolete level ESD and
MY name formerly over signal pads which require ESD Latchup
and latchup Rule checking rules
63 37
IND IND dg Special level that is placed over Inductor structures Induc-
to generate the BT and BF levels under the inductor tors
12 38 (see Table 7 and Table 8)
IND_FILT OUT- IND Shape identifies INDUCTOR [LM, MG, MQ] or [MA, DRC/
LINE- E1] or [LD, OL, MG, MQ] shapes unique to the Modeling
CMRF8SF technology, and are modeled and DRC
60 4 checked to additional rules.
JTESD_ JT esdf Placed over JT or JTBAR vias to enable area sum- ESD
FINGER ming. Rules/
141 62 DRC
L1TEMP25 L1 res Placed over L1 resistor when Mx or LY wiring L1

sought below the device. See Reliability Section on Resistor
6 22 the L1 device for more information. Default is to Exclu-
NOT use L1TEMP25 in a chip design. It is strongly sion
recommended that a designer review the Reliability
Section prior to using the L1TEMP25 dummy
design level in a chip design.
LD_COIL LD IND Shape identifies shapes used in inductor coils DRC

(within IND_FILT).
183 19


name purpose ated
With
GDSII GDSII
number type
LDESD LD esd Shape = Label that is used to identify pads used for DRC
183 60
LDESD_ LD esdf Placed over fingered metal to enable width sum- ESD
FINGER ming. Rules/
183 62 DRC
LDEXCLUD LD TRANS Reserved Level for IBM use only. Shape Identifies DRC/De
Transmission Lines Fill Exclusion sign Ser-
183 2 vices
LDPIN LD pin Shape identifies ports of a device or a cell LVS/

DRC
183 32
LM_COIL LM IND Shape identifies LM shapes used in inductor coils DRC

(within IND_FILT).
24 19
LM_RFLINE LM rfline Shape identifies LM shapes used in rfline device. DRC./M

odel-
24 29 ing/Desi
gn Ser-
vices
LMDUMHOL LM dumhol Placed over C4 terminal pads to eliminate checking DRC

of oxide support structures
62 17
LMESD LM esd Shape = Label that is used to identify pads used for DRC
24 60
LMESD_ LM esdf Placed over fingered metal to enable width sum- ESD
FINGER ming. Rules/
24 62 DRC
LMTRANS LM TRANS Reserved Level for IBM use only. Shape Identifies DRC/Dat
24 18
LOGOBND LOGOB dg Placed over Product Labels to assist in DRC verifi- Labels
ND cation. See section 3.40 , Product Labels on
page 328
62 5


name purpose ated
With
GDSII GDSII
number type
LOWCRNT OUT- LOWCRN Shape identifies FQ vias which only use 20% or Labels
LINE T less of the rated current. See Section 5.4 , Back
End Of Line (BEOL) Reliability Design Rules on
60 28 page 489 for current ratings and Rule AM1a
LVDUMMY LVDU- dg Shape used to specify area for C4 ball placement C4

MMY but not open to LV etch. When C4 terminal connec-
tions are used (not wirebond), dummy terminals
28 1 provide additional mechanical support. See section
3.35.2 , C4 Terminals with MA Last Metal on
page 282.
LYESD 3 LY esd Shape = Label that is used to identify pads used for DRC
42 60
LYESD_ LY esdf Placed over fingered metal to enable width sum- ESD
FINGER ming. Rules/
123 62 DRC
LYEXCLUD LY TRANS Reserved Level for IBM use only. Shape Identifies DRC/Dat
42 18
LYPIN LY pin Shape identifies ports of a device or a cell LVS/

DRC
42 32
M4_COIL M4 IND Shape identifies M4 shapes used in inductor coils DRC

(within IND_FILT).
21 19
M5_COIL M5 IND Shape identifies M5 shapes used in inductor coils DRC

(within IND_FILT).
31 19
MA_COIL MA IND Shape identifies MA shapes used in inductor coils DRC

(within IND_FILT).
125 19
MA_RFLINE MA rfline Shape identifies MA shapes used in rfline device. DRC/

Model-
125 29 ing/Desi
gn Ser-
vices
MAESD 3 MA esd Shape = Label that is used to identify pads used for DRC
ESD and Latchup Rule checking.
81 60


name purpose ated
With
GDSII GDSII
number type
MAEXCLUD MA TRANS Reserved Level for IBM use only. Shape Identifies DRC/Dat
81 18
MAPIN MA pin Shape identifies ports of a device or a cell LVS/

DRC
81 32
MG_COIL MG IND Shape identifies MG shapes used in inductor coils DRC

(within IND_FILT).
65 19
MQ_COIL MQ IND Shape identifies MQ shapes used in inductor coils DRC

(within IND_FILT).
34 19
MGDUMHOL MG dumhol Placed over MG wires in OL or LD inductor struc- DRC/Dat

tures to prohibit MGHOLE placement. aprep
65 97
MQDUMHOL MQ dumhol Placed over MQ wires in OL or LD inductor struc- DRC/Dat

tures to prohibit MGHOLE placement. aprep
34 97
MIM_HK MIM hk Shape identifies designs containing High K MIM DRC/Dat

capacitors. Required to cover all MIM capacitors in aprep
61 51 each design.
MIM_NI MIM ni Shape identifies designs containing Single Nitride DRC

MIM capacitors. Required to cover all MIM capaci-
61 50 tors in each design.
MULTI_CAP MULTI CAP Shape identifies multiplicity for MIMs and devices LVS
under MIMs.
60 27
MULTI_RES MULTI RES Shape identifies multiplicity for L1 or Kx LVS

(x=2,3,4,5,6) resistors.
60 26
MULTI MULTI DEV Shape identifies multiple devices which represent a LVS
single schematic symbol with a value greater than
60 25 one


name purpose ated
With
GDSII GDSII
number type
MxESD Mx esd Shape = Label that is used to identify pads used for DRC
ESD and Latchup Rule checking.
(x=1) 15 60
(x=2) 17 60
(x=3) 19 60
(x=4) 21 60
(x=5) 31 60
(x=6) 44 60
(x=Q) 34 60
(x=G) 65 60
MxESD_ Mx esdf Placed over fingered metal to enable width sum- ESD
FINGER ming. Rules/
DRC
(x=1) 15 62
(x=2) 17 62
(x=3) 19 62
(x=4) 21 62
(x=5) 31 62
(x=6) 44 62
(x=Q) 34 62
(x=G) 65 62


name purpose ated
With
GDSII GDSII
number type
MxTRANS Mx TRANS Reserved Level. Shape included in Transmission DRC

Lines. Shapes used to determine if Kx BEOL resis-
(x=1) 15 18 tors are straddling transmission lines. For additional
information, see Rule KX14 in Table 72, Kx
(x=2) 17 18 (x=2,3,4,5,6,) Resistor Layout Rules, on page 224.
The MxTRANS levels are NOT used during the IBM
(x=3) 19 18
Release process and do not affect normal IBM
(x=4) 21 18 auto-generated MxFILL in the transmission line
device structures.
(x=5) 31 18
(x=6) 44 18
(x=Q) 34 18
(x=G) 65 18
NOPLYMD NOPLY dg Shape identifies designs which use the no final Technol-
MD polyimide chip passivation. section 3.41 , No Poly- ogy Fea-
imide Final Passivation option on page 332 tures
212 136
NWASP NWASP dg Placed over NW shapes to denote Nwells at the Nwells at

same potential. Used to denote relaxed NW to NW same
4 3 space rules for groundrule checking for this situa- potential
tion.
NW_RES NW res Used to define N-well resistor. Also helps to prohibit LVS
RXFILL placement within the N-well resistor device
4 22 per Rule NWR06 (see Table 69, N-well Resistor
Layout Rules, on page 217).
OL_COIL OL IND Shape identifies shapes used in inductor coils DRC

(within IND_FILT).
140 19
OLESD OL esd Shape = Label that is used to identify pads used for DRC
140 60
OLESD_ OL esdf Placed over fingered metal to enable width sum- ESD
FINGER ming. Rules/
140 62 DRC
OLPIN OL pin Shape identifies ports of a device or a cell LVS/

DRC
140 32


name purpose ated
With
GDSII GDSII
number type
OUTLINE4 OUT- dg Defines edge of IBM cells. -

LINE
62 21
OUTLINE_RF OUT- RF Shape identifies RF FET devices Modeling

LINE
62 65
PCEXCLUD 5 PC exclude Placed over specific areas of the chip that can not PCFILL
receive PCFILL shapes, such as ESD/IO circuits. exclu-
7 2 sion.
PROBE OUT- probe Used to define tested wire-bond pads in the LM DRC
LINE BEOL options only.
12 62
PROTECT PRO- dg Used during the CP mask assembly automatic KERF

TECT KERF merge process associated with preventing design
mask background overwrite. Triangular shape and
102 18 added to the four corners of the chip data on this mask
level. merge
RF_MODFILL RF_MO dg Marker Shape which identifies regions that receive Design
DFILL the reduced density fill during IBM design services. Services
212 183
RXEXCLUD5 RX exclude Placed over specific areas of the chip that can not RXFILL
receive RXFILL shapes, such as ESD/IO circuits exclu-
2 2 sion.
SBLK6 SBLK dg Shape identifies ballasted FETs. DRC
12 48
SCHKY OUT- SCHKY Shape identifies Schottky Barrier Diode devices. DRC,
LINE Datap-
rep
212 174
SILPCRES PC SILPCRE Marking layer for the silicided polysilicon resistor. DRC,
S Layer is used in data preparation to achieve p-type Datap-
doping for the polysilicon resistor. rep,
7 21 Design
Services


name purpose ated
With
GDSII GDSII
number type
SRAMM1 M1 sram Used to mark SRAM array data Datap-

rep,
15 45 OPC
SRAMPC PC sram Used to mark SRAM array data Datap-

rep,
7 45 OPC
SRAMRX RX sram Used to mark SRAM array data Datap-

rep,
2 45 OPC
TRANSMIS OUT- TRANS Shape is used to identify Transmission Lines LVS

LINE
60 18
TVDUMMY TVDU- dg Shape used to specify area for C4 ball placement C4

MMY but not open to TV etch. When C4 terminal connec-
tions are used (not wirebond), dummy terminals
26 1 provide additional mechanical support. See section
3.35.1 , C4 Terminals with LM Last Metal on
page 276.
VAR7 VAR dg Placed over PCDCAP ( Nfet-in-nwell) structures to Decou-

avoid extension or halo implants. pling
12 24 capaci-
tors /
varac-
tors
VNCAP8 VNCAP dg Marking layer for the vertical natural capacitor. Nor- DRC/LV
mal wiring is permitted above the last metal used for S
62 120 the capacitor for the back-end-of-line (BEOL) stack.
VNCAP_COU VNCAP count Marking layer for the vertical natural capacitor. It is LVS/DR
NT 8 used in design checking to indicate the number of C//Mod-
63 105 metal levels in the capacitor design. eling


name purpose ated
With
GDSII GDSII
number type
VNCAP_Mx 8 Mx vncap Marking layer for the vertical natural capacitor. It is LVS/DR
used in design checking to validate correct capaci- C/Model-
(x=1) 15 80 tor construction. ing
(x=2) 17 80
(x=3) 19 80
(x=4) 21 80
(x=5) 31 80
(x=6) 44 80
VNCAP_PAR VNCAP parm Marking layer for vertical natural capacitor. It is LVS/DR
M8 used in design checking to indicate the capacitor C/Model-
63 104 starting metal level. ing
VTSENS VTS- dg Placed over (PC intersect RX). (PC intersect RX) Vt sensi-
ENS must be completely within VTSENS tivity
check-
12 52 ing.
VxESD_ Vx esdf Placed over Vx or VxBAR to enable Vx, VxBAR ESD

FINGER area summing. Rules/
DRC
(x=1) 16 62
(x=2) 18 62
(x=3) 20 62
(x=4) 22 62
(x=5) 32 62
(x=L) 35 62
(x=Q) 33 62
(x=G) 64 62
ZEROVT9 ZEROV dg Placed over Zero Vt FET devices. Zero Vt

T Device
12 0
1. The levels are for labels only. For additional information, see Section 3.12.5 , Net Definitions for ESD and Latchup Verification on
page 201.
2. For additional information, see Table 111, Pad Model Rules for C4 and Wirebond with LM Metallization, on page 311 or Table 112,
Pad Model Rules for C4 and Wirebond with MA Metallization, on page 312.

Physical Layout Information Masks for Non-Design Levels IBM
3. The levels are for labels only. For additional information, see Section 3.12.5 , Net Definitions for ESD and Latchup Verification on
page 201.
4. OUTLINE [OUTLIN dg] is also used for IBM testsite macro outline definition.
5. For information on usage of RXEXCLUD and PCEXCLUD shapes, see section 2.9 , Important Design Guidelines on page 84. , and
see section 2.10 , Pattern Density Rules on page 87.
6. For additional information, see Rule 736a, 736a1, 736a2 and PBR19 in Table 63, ESDIODE Layout Rules, on page 203.
7. For additional information, see Table 83, Varactor Layout Rules, on page 237.
8. For additional information, see Table 93, Vertical Natural Capacitor Layout Rules, on page 263.
9. For additional information, see Table 25, ZVT NFET Layout Rules, on page 121.
2.4 Masks for Non-Design Levels

The following mask levels are generated during mask build and can not be drawn by the designer. Any
shapes drawn by a customer on one of the Mask Levels in Table 7 will be discarded and replaced with the
shapes derived during Data Preparation. See Section 2.5 , Level Generation and Design Preparation on
page 59 and Section P.0, Design Preparation on page 548 for more information about preparing design
data.
Table 7. Masks for Non-Design Levels1
Mask CDS CDS Description

Level name purpose
GDSII GDSII
number type
BN2 BN dg Shape = P+ source/drain implant area.
11 0
BT BT dg Shape = blocks deep implant in both Nwell and Pwell regions of a chip
design. Regions of the chip design blocked from the deep implant are
12 55 identified by Dummy Design Levels {SCHKY, BFMOAT, ZEROVT,
IND_FILT, IND, (ESDIODE sized by +0.1m per edge} or Mask Levels
{(PI sized by +1.1m per edge), JD}
DW DW dg Shape = thick oxide gate device well implant area. Use is OPTIONAL3.
48 0
BF BF dg Shape = complement of the P-well implant.
5 0
BH BH dg Shape = complement of the nFET halo implant. Determines the nFET

halo/extension implant area.
8 0
DF DF dg Shape = 5.2nm oxide pFET halo/LDD implant. Use is OPTIONAL 3.
12 12

Physical Layout Information Level Generation and Design Preparation
Table 7. Masks for Non-Design Levels1
Mask CDS CDS Description

Level name purpose
GDSII GDSII
number type
DE DE dg Shape = 5.2nm oxide nFET halo/LDD implant. Use is OPTIONAL 3.
12 7
PH PH dg Shape = pFET extension/halo implant area.
9 0
VI VI dg Shape = P+ implant area for HA Varactor. Use is OPTIONAL 3.
12 120
TD TD dg Shape = AlCu transfer pad from last wiring level to final passivation ter-
minal opening required for C4 terminal pad connections for the LM met-
36 0 allization options listed in Table 11 on page 64. TD is drawn for wirebond
and automatically generated in by Data Preparation for C4 Designs. See
also Table 9 on page 62.
TM TM dg Shape = area for plated terminal metal (C4 Plating) for both LM (see
Table 11 on page 64) and MA (see Table 12 on page 65) last metal
49 0 options. See also Table 9 on page 62 and Table 10 on page 63.
1. See Design Minimum values in Table 31, BP Layout Rules, on page 128 Some Design Levels also receive manipulation during
mask data preparation (DPREP). See section 2.5 , Level Generation and Design Preparation on page 59.
2. BN generations use BP shapes as designed and not the BP as generated in mask data preparation (DPREP).
3. For more information on optional Masks for Non-Design Levels, see Table 1, Optional Features with Feature Part numbers on
page 11 and Table 8, Shape Manipulation Prior to Mask Write on page 59.
2.5 Level Generation and Design Preparation
Table 8. Shape Manipulation Prior to Mask Write
Mask Description of Design Preparation From Design Levels

Level
BT BT = Union[ BB, BFMOAT, ZEROVT, (PI sized by +1.1um per edge), JD, IND_FILT, IND,
((ESDIODE) sized by +0.10), IBLK] Remove gaps 0.64, Remove slivers 0.64
BF BF = Union[DERIVEDBF, ZEROVT, BB, BFMOAT, IND, DBF1]

where
DERIVEDBF = NW sized by +0.00
DBF1 = Union [PI, IND_FILT, JD]
Remove gaps 0.62; Remove slivers 0.28

Physical Layout Information Level Generation and Design Preparation IBM

Level
NW1 NW = Union [ (NW not touching JD), (JD sized by -0.40um per edge), RN]
NV NV = Difference [ NV , NW ]
PV PV = Intersection [ PV, NW ]
DW DW = Difference [DG, Union (ZEROVT,NW) ]
DE2 DE = DERIVEDDE , where

DerivedDE = Union { ( ZEROVT sized by +0.52), Difference [ DG, Union (NW, XE) ] }
DF DF = difference { intersection (DG, NW) , Union (VAR, XF) }
BP BP = union [BP, Difference (BB, RN)]
BP gaps and notches are filled where the spacing is 0.34, the run length is 5.00, the
space to be filled is not touching RX or PC, and the space to be filled is 0.12 from
any RX or PC shape.
BP slivers 0.22 are removed.
BN BN = DERIVEDBN
where,
DBP1 = BP
DBN1 = PD
DERIVEDBN = union {[DBP1 not touching union (PD,RP,JD)] , DBN1}
BN gaps are filled where the spacing is 0.34, the run length is 5.00, the net union of the
DERIVEDBN space to be filled is not touching RX or PC, and the space to be filled is
0.12 from any RX or PC shape.
VI VI = Intersection [BP,JD]
BH BH = DBH50
where
DBH01 = [Intersection (OP, PC)]
DBH02 = RX sized by +0.20
DBH10 = { Difference (DBH01, DBH02) sized by +0.12}
DBH25 = { [ PC(touching OP, over RR) ] sized by +0.12}
DBH26 = { [ PC(touching OP, over RP) ] sized by +0.12}
DBH40 = Union {BB, DG, NW, VAR, [ZEROVT sized by +0.52], JD, DBH10, DBH25,
DBH26, EFUSE, SILPCRES}
DBH50 = Remove slivers 0.38 for DBH40

Physical Layout Information Level Generation and Design Preparation

Level
PH PH = DPH2
where
DPH1 = {difference [intersection (OP, PC), (RX sized by +0.20)] sized by +0.12}
Slivers 0.38 are removed after DPH1 derivation
DPH2 = difference {NW, union (DG, VAR, RP, JD, SILPCRES, DPH1)}
XW XW = Difference (XW, NW)
LW LW = Intersection (LW, NW)
PC Consult your IBM Technical Representative for more detail.

RX Consult your IBM Technical Representative for more detail.
LD3 For IBM KERF LDFILL Generation
LY 3 For IBM KERF LYFILL Generation
E1 3 For IBM KERF E1FILL Generation
MA 3 For IBM KERF MAFILL Generation
AM 3 For IBM KERF AMFILL Generation
M1 Data preparation for OPC, anchors, etc. Consult your IBM Technical Representative for
more detail.
more detail.
more detail.
more detail.
more detail.
more detail.
MG Data preparation for anchors, etc. Consult your IBM Technical Representative for more
detail.
MQ Data preparation for anchors, etc. Consult your IBM Technical Representative for more
detail.
OL 3 For IBM KERF OLFILL Generation.
D14 Copy of M1 for dense SRAM designs
CF 4 Copy of CA for dense SRAM designs

Physical Layout Information Level Generation and Design Preparation IBM

Level
VE 4 Copy of V1 for dense SRAM designs
V1 Data preparation for VxHOLE. Consult your IBM Technical Representative for more detail.
VL Data preparation for VxHOLE. Consult your IBM Technical Representative for more detail.
VQ Data preparation for VxHOLE. Consult your IBM Technical Representative for more detail.
VG Data preparation for VxHOLE. Consult your IBM Technical Representative for more detail.
1. Generated NW is not checked in DRC.
2. DE needs to be generated if ZVT or ZVT25 devices are used, even if no DG devices are present.
3. These keywords are listed to ensure inclusion of LYFILL, E1FILL or MAFILL (for the MA BEOL option only) or LDFILL, OLFILL (for
the OL with LD BEOL option only) in the KERF electrical macros.
4. For additional information, consult your IBM technical representative.
Table 9. Shape Manipulation Prior to Mask Write (for LM last metal)1

Level
TD2 TD = least enclosing orthogonal rectangle of TV sized by +15.00 m per

edge.
TV TV octagons converted to circles:

Size TV circle by +8.50 m
FV FV octagons converted to circles:

Size FV circle by -0.74 m
TM3 Generated from (TV, TVDUMMY)
1. See section 3.35.1 , C4 Terminals with LM Last Metal on page 276.
2. The TD level is drawn for Wirebond connections rules and generated for C4 connection rules.
3. Riston Cu plating mask process.

Physical Layout Information Mask Metallization Options
Table 10. Shape Manipulation Prior to Mask Write (for MA1 or OL with LD 2 last metals)

Level
QK 3 INTERSECTION [QT, MIM_HK]
HK 3 INTERSECTION [HT, MIM_HK]
LV (LV over C4LV) octagons converted to circles.

Size LV circle by +0.00 m.
TM4 Generated from ((LV over C4LV), LVDUMMY) (C4 Plating)
1. See section 3.35.1 , C4 Terminals with LM Last Metal on page 276.
2. See section 3.35.7 , LD Terminal Metal (with OL wiring) on page 304.
3. For OL with LD metallization options only.
4. Riston Cu plating mask process.
2.6 Mask Metallization Options

The CMRF8SF technology offers four BEOL metallization options. The metallization options are listed in
Table 11 on page 64 or Table 12 on page 65 or Table 13 on page 66 or Table 14 on page 67.

Physical Layout Information Mask Metallization Options IBM
2.6.1 LM Metallization Options
Table 11. LM last metal Back End Of Line (BEOL) Metallization Options
Type Of Optional Optional Final Passi-

Levels Metallization Kx BEOL Required Mask Levels MIM vation 2, 3
Of Resistor (except Kx; where x = 3,4,5,6 is Mask
Metal Mask optional) Level
Thin4 Thick5 RF6,7 Wire- C4
Level1
Metal bond
8 5 3 0 K5 M1, V1, M2, V2, M3, V3, M4, A MIM DV FV

V4, M5, (K5), VL, MQ, VQ, MG, option is
VG, LM, TV, TD not
offered
7 4 3 0 K4 M1, V1, M2, V2, M3, V3, M4, for the
(K4), VL, MQ, VQ, MG, VG, LM
LM, TV, TD BEOL
8 6 2 0 K6 M1, V1, M2, V2, M3, V3, M4, options8
V4, M5, V5, M6, (K6), VL, MQ, (only
VQ, LM, TV, TD VNCAP
device
7 5 2 0 K5 M1, V1, M2, V2, M3, V3, M4, using
V4, M5, (K5), VL, MQ, VQ, LM, required
TV, TD mask
levels is
6 4 2 0 K4 M1, V1, M2, V2, M3, V3, M4,
offered)
(K4), VL, MQ, VQ, LM, TV, TD
5 3 2 0 K3 M1, V1, M2, V2, M3, (K3), VL,

MQ, VQ, LM, TV, TD
1. The L1 BEOL resistor is not supported with the LM metallization options.
2. For Wirebond Final Passivation, See section 3.35.5 , Wirebond Terminals with LM (and TD) Last Metal Level on page 295.
3. For C4 Final Passivation, See section 3.35.1 , C4 Terminals with LM Last Metal on page 276.
4. Number 3 = (Mx, x = 1,2,3; Vx, x = 1,2,L); Number 4 = (Mx, x = 1,2,3,4; Vx, x = 1,2,3,L); Number 5 = (Mx, x= 1,2,3,4,5; Vx, x =
1,2,3,4,L); Number 6= (Mx, x = 1,2,3,4,5,6; Vx, x = 1,2,3,4,5,L);
5. Number 2 = (MQ, VQ, LM); Number 3 = (MQ, VQ, MG, VG, LM).
6. RF metal is not supported with the LM last Thick metal.
7. RF metal is also referred to as the Dual Metal [FY, LY, FT, E1, F1, MA] wiring option.
8. A VNCAP device is offered as a BEOL (MIM) capacitor. The VNCAP device does not require any additional mask levels, as it is
supported using the thin metal levels available for the Level of Metal option selected. The QY MIM or QY and HY MIM as well
as the QT and HT or KT MIMs are not supported for the LM metallization option.

Physical Layout Information Mask Metallization Options
2.6.2 MA Metallization Options
Table 12. MA last metal Back End Of Line (BEOL) Metallization Options

Levels Metallization Kx or L1 Required Mask Levels MIM (*) vation 5, 6
Of BEOL (except Kx; where x=2,3,4 or Mask
Metal Resistor L1, since one level is optional Level2,3,4
Thin7 Thick8 RF9 Mask and shown for completeness) Wire- C4
Metal bond
Level1
6 2 1 3 K2 or L1 M1, V1, M2, (K2), VL, MQ, FY, QY or DV LV
LY, (*), FT, E1, (L1), F1, MA QY, HY
7 3 1 3 K3 or L1 M1, V1, M2, V2, M3, (K3), VL,

MQ, FY, LY, (*), FT, E1, (L1) F1,
MA
7 2 2 3 K2 or L1 M1, V1, M2, (K2), VL, MQ, VQ,

MG, FY, LY, (*), FT, E1, (L1), F1,
MA
8 3 2 3 K3 or L1 M1, V1, M2, V2, M3, (K3), VL,

MQ, VQ, MG, FY, LY, (*), FT,
E1, (L1), F1, MA
8 4 1 3 K4 or L1 M1, V1, M2, V2, M3, V3, M4,

(K4), VL, MQ, FY, LY, (*), FT,
E1, (L1), F1, MA
1. Only one BEOL resistor can be used in a chip design. The L1 BEOL resistor is prohibited from being used if a Kx BEOL resistor
is selected, or if a L1 BEOL resistor is selected, then use of a Kx BEOL resistor is prohibited.
2. Single HP MIM (QY) or Dual HP MIM (QY, HY) are located above LY and are connected using FT vias and E1 metal wiring. L1
resistor is located above E1 and is connected using F1BAR vias, on the F1 mask level.
3. A VNCAP device is also offered as a BEOL (MIM) capacitor. The VNCAP device does not require any additional mask levels, as it is
supported using the thin metal levels available for the Level of Metal option selected.
4. Design levels QT and HT or KT are not supported with the MA metallization options.
5. For Wirebond Final Passivation, See section 3.35.6 , Wirebond with MA Last Metal on page 302.
6. For C4 Final Passivation, See section 3.35.1 , C4 Terminals with LM Last Metal on page 276.
7. Number 2 = (Mx, x= 1,2; Vx, x=1,L); Number 3 = (Mx, x = 1,2,3; Vx, x=1,2,L); Number 4 = (Mx, x = 1,2,3,4; Vx, x = 1,2,3,L)
8. Number 1 = (MQ); Number 2 = (MQ, VQ, MG).
9. RF metal is also referred to as the Dual Metal [FY, LY, FT, E1, F1, MA] wiring option.

Physical Layout Information Mask Metallization Options IBM
2.6.3 OL with LD Metallization Options
Table 13. OL with LD last metal Back End Of Line (BEOL) Metallization Options

Levels Metallization Kx BEOL Required Mask Levels MIM (*) vation 4, 5
Of Resistor (except Kx; where x=2,3,4 is Mask
Metal Mask optional and shown for com- Level2,3
Thin6 Thick7 RF8 pleteness) Wire- C4
Level1
Metal bond
5 2 1 2 K2 M1, V1, M2, (K2), VL, MQ, (*), QK, HK DV LV

JT, OL, VV, LD. (Hi-K MIM)
6 3 1 2 K3 M1, V1, M2, V2, M3, (K3), VL, or

MQ, (*), JT, OL, VV, LD.
7 4 1 2 K4 M1, V1, M2, V2, M3, V3, M4, QT, HT

(K4), VL, MQ, (*), JT, OL, VV, (single
LD. Nitride
MIM)
8 5 1 2 K5 M1, V1, M2, V2, M3, V3, M4,
V4, M5, (K5), VL, MQ, (*), JT, or
OL, VV, LD.
QT, HT, KT
8 4 2 2 K4 M1, V1, M2, V2, M3, V3, M4, (dual
(K4), VL, MQ, VQ, MG, (*), JT, Nitride
OL, VV, LD. MIM)
1. The L1 BEOL resistor is not supported in the OL with LD metallization options.
2. The MIMs are located above the last thick copper metal level MQ (unless MG is present) or MG (if present) and below the JT via. The
QT MIM bottom plate design level and the HT top MIM plate design level (for Hi-K or single Nitride MIM) or HT middle MIM plate design
level (for dual Nitride MIM) and KT top plate design level (for dual nitride MIM) are connected using JT vias and OL metal wiring. The
QK and HK mask levels are required when the Hi-K MIM feature is selected and are generated in data preparation from the QT and
HT design levels when they intersect the MIM_HK utility level. QT and HT mask levels are both required when the Single nitride MIM
feature is selected. QT, HT and KT mask levels are all required when the Dual nitride MIM feature is selected.
supported using the thin metal levels available for the Level of Metal option selected. The QY, HY MIM is not supported in the (OL with
LD) or LM metallization options.
4. For Wirebond Final Passivation, See section 3.35.8 , Wirebond for LD Last Metal (with OL wiring) on page 304.
5. For C4 Final Passivation, See section 3.35.3 , C4 Terminals for LD Last Metal on page 286.
6. Number 2 = (Mx, x= 1,2; Vx, x=1,L); Number 3 = (Mx, x = 1,2,3; Vx, x=1,2,L); Number 4 = (Mx, x = 1,2,3,4; Vx, x = 1,2,3,L), Number
5 = (Mx, x = 1,2,3,4,5; Vx, x = 1,2,3,4,L)
7. Number 1 = (MQ); Number 2 = (MQ, VQ, MG).
8. RF metal is a thick copper [OL] and thick aluminum [LD] wiring option. JT is the via between the last 2x copper and thick copper
OL wire, and VV is the via between OL second to the last metal and LD last metal.

Physical Layout Information Design Truth Tables
2.6.4 AM Metallization Options
Table 14. AM last metal Back End Of Line (BEOL) Metallization Options
Type Of Optional Required Mask Levels Optional Final Passi-

Levels Metallization Kx BEOL MIM (*) vation 3, 4
Of Resistor Mask
Metal Thin Thick RF7 Mask Wire- C4
Level 2
Cu5 Cu6 Metal bond
Level1
7 5 1 1 K5 M1, V1, M2, V2, M3, V3, M4, - DV LV

V4, M5, VL, MQ, FQ, AM
1. The L1 BEOL resistor is not supported in the AM metallization options.
supported using the thin metal levels available for the Level of Metal option selected.
3. For Wirebond Final Passivation, See section 3.35.9 , Wirebond with AM Last Metal on page 307.
4. For C4 Final Passivation, See section 3.35.4 , C4 Terminals with AM Last Metal on page 291.
5. Number 5 = (Mx, x = 1,2,3,4,5; Vx, x = 1,2,3,4,L)
6. Number 1 = (MQ)
7. RF metal is AM metal wiring option.
2.7 Design Truth Tables

The Design Truth Table is provided as an aid to the layout of various structures. In this table a 0 indicates
that design level must not touch the structure. A 1 indicates that design level must cover or match the struc-
ture.X means dont care; there is no electrical effect of this mask on this feature. P means the structure
must be partial covered by the shape. G indicates that the shape is generated. B is Boolean switch where
the feature can be turned on and off depending on desired electrical characteristics.
The structures in this table are the only structures permitted in this technology. Use of any other structure
requires prior approval in writing from the IBM Technical Representative.
In addition to the levels in the Truth Table the Identification level PD is required on the RR poly resistor. IND
is required on the Mx (x=1,2,3,4,5,6) Inductors (with the LM as the last metal level). IND or IND_FILT is
required on LM Inductors. IND_FILT is required on MA Inductors. IND_FILT is required for OL or LD induc-
tors.
Note: Design Levels XW, LW, NV, PV are manipulated by Section 2.5 , Level Generation and Design Prep-
aration on page 59. However, the Design Level entries in the truth table are accurate for the output after
Level Generation and Design Preparation is applied.
Note: Structures or Design or Derived Levels shaded in Gray are not supported or offered in the CMRF8SF
technology at this time.

Physical Layout Information Design Truth Tables IBM
Table 15. Design Truth Table
STRUC- Design Levels Derived Levels

TURE (Generated)
T R N R B N L P X P N D P J J J X X B P R R O B D B D D P B V B
3 X S N B W W I W V V G C D N P E F P D R P P T W H F E H F I N
T3 over 1 0 0 0 0 1 0 0 0 0 0 0 x 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 1 0 0
IBLK Well
Isolation
or T3 Well
N-band
contact
T3 Isola- 1 x 0 0 0 0 0 0 x 0 x x x 0 0 0 x 0 x x x x x 0 x 0 0 0 0 0 0 x
tion Pwell
T3 Isola- 1 x 0 0 0 1 x 0 0 x 0 x x 0 0 0 0 x x x x x x 0 x 1 x x 1 1 0 x
tion Nwell
not over
IBLK
T3 Isola- 1 1 0 0 0 0 x 0 x x x x 0 0 0 0 x x 1 0 0 0 0 0 x 0 x x 0 0 0 1
tion Pwell
Contact
T3 Isola- 1 1 0 0 0 1 x 0 0 x 0 x 0 0 0 0 0 x 0 0 0 0 0 0 x 1 x x 1 1 0 0
tion Well
Internal
NW Con-
tact
T3 Isola- 0 1 0 0 0 1 x 0 x x x 0 0 0 0 0 x x 0 0 0 0 0 0 x 1 x x 1 1 0 0
tion Well
External
NW Con-
tact (same
as bulk
NW con-
tact)
T3 Isola- 1 1 0 0 0 0 x 0 x x x x 0 0 0 0 x x 0 0 0 0 x 0 x 0 x x 0 0 0 0
tion Well
N+ junc-
tion
T3 Isola- 1 1 0 0 0 1 x 0 x x x x 0 0 0 0 x x 1 0 0 0 x 0 x 1 x x 1 1 0 1
tion Well
P+ junc-
tion
Regular x 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
NFET
Regular x 1 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 1 1 0 1
PFET
Low x 1 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Power
(LP)
NFET
Low x 1 0 0 0 1 0 0 0 1 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 1 1 0 1
Power
(LP) PFET


TURE (Generated)
LVT NFET x 1 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
LVT PFET x 1 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 1 1 0 1
ZVT Thin 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 0
NFET
ZVT Thick 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 0
NFET
Thick x 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 0
NFET25
Thick x 1 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 1 0 1
PFET25 1
Thick x 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0
NFET33
Thick x 1 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 1 0 1
PFET33 1
HIVT 3.3V x 1 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0
NFET
HIVT 3.3V x 1 0 0 0 1 0 0 0 0 0 1 1 0 0 1 0 1 1 0 0 0 0 0 0 1 0 0 0 1 0 1
PFET 1
Thin Triple 0 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0
Well
NFET
over PI
Thick Tri- 0 1 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 1 0 0
ple Well
NFET
over PI
PI Triple 0 x 0 0 0 1 0 1 0 0 0 x x 0 0 0 0 0 x 0 0 0 0 1 x P 0 x 0 1 0 x
Well Isola-
tion2
PI Triple 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 1
Well Con-
tact
HAVarac- 0 1 0 0 0 G 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 1 0 0 0 1 1 0
tor / Diff
HAVAR


TURE (Generated)
N+ Junc- x 1 0 0 0 0 x 0 x x x x 0 x x x x x 0 0 0 0 x 0 x x 0 x 0 0 0 0
tion
Substrate 0 1 0 0 0 0 x 0 x x x x 0 0 x x x x 1 0 0 0 0 0 x x 0 x 0 0 0 1
Contact
P+ Junc- x 1 0 0 0 1 x 0 x x x x 0 x x x x x 1 0 0 0 x 0 x 1 x 0 x 1 0 1
tion3
N-well x 1 0 0 0 1 x 0 x x x x 0 0 x x x x 0 0 0 0 0 0 x 1 x 0 x 1 0 0
Contact
DI Diode x 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 1 1 0 1
SBD 0 1 1 1 1 G 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 1 0 P
Electronic x 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 x 0 0 1 0 0 0 0 0 1
Fuse
OP N+ dif- x 1 0 0 0 0 0 0 0 x x 0 0 0 x x x x 0 0 0 0 1 0 x 0 0 0 0 0 0 0
fusion
resistor
OP N+ dif- 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 x 0 0 0 0 1 0 0
fusion
resistor,PI
OP P+ x 0 0 0 0 x x x x x x 0 1 0 x x x x 1 0 0 0 1 0 x 1 0 0 0 x 0 1
poly resis-
tor
OP P+ x 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 1
poly resis- 4
tor
(over_NW
)
PC P+ 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1
poly resis-
tor
(over_BF
MOAT)
OP RR x 0 0 0 0 x 0 x 0 0 0 0 1 0 0 0 0 0 1 1 1 0 1 0 0 1 0 0 0 x 0 1
PC poly
resistor
OP RR x 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 1 1 1 0 1 0 0 1 0 0 0 1 0 1
PC poly
resistor
(over_NW
)4
OP RR 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 1 1 0 1 1 0 1 0 0 0 1 0 1
PC poly
resistor
(over_BF
MOAT)


TURE (Generated)
OP RP PC x 0 0 0 0 x 0 x 0 0 0 0 1 0 0 0 0 0 1 0 0 1 1 0 0 1 0 0 0 x 0 0
poly resis-
tor
OP RP PC x 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 1 1 0 0 1 0 0 0 1 0 0
poly resis-
tor
(over_NW
)5
OP RP PC 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 1 1 1 0 1 0 0 0 1 0 0
poly resis-
tor
(over_BF
MOAT)
N-well 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0
Resistor
Silicided x 0 0 0 0 x 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 1 0 0 0
PC resis-
tor
L1 BEOL x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
resistor
Kx BEOL x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
resistor
(x= 2,3,4,5
or 6)
PCDCAP x 1 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0
Thin
Oxide /
Varactor
Thin
Oxide/ Diff
NCAP
PCDCAP x 1 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0
Thick
Oxide /
Varactor
Thick
Oxide
Hi-K MIM x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
(QT, HT)
Single x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
Nitride
MIM
(QT, HT)
Dual x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
Nitride
MIM (QT,
HT, KT)
Single HP x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
MIM (QY)


TURE (Generated)
Dual HP x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
MIM (QY,
HY)
VNCAP x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
Bondpad 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0
(WB,LD,
BFMOAT
or M1)
Bondpad x 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1
(WB,LD,
PC)
Bondpad x 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1
(WB,LD,
RX)
Bondpad 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0
(C4,LD,
BFMOAT
or M1)
Bondpad x 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1
(C4,LD,
RX)
Bondpad 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0
(WB,LM,
BFMOAT
or M1)
Bondpad x 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1
(WB,LM,
PC)
Bondpad x 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1
(WB,LM,
RX)
Bondpad 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0
(C4,LM,
BFMOAT
or M1)
Bondpad x 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1
(C4,LM,
PC)
Bondpad x 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1
(C4,LM,
RX)
Bondpad 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0
(WB,MA,
BFMOAT
or M1)


TURE (Generated)
Bondpad x 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1
(WB,MA,
PC)
Bondpad x 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1
(WB,MA,
RX)
Bondpad 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0
(C4,MA,
BFMOAT
or M1)
Bondpad x 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1
(C4,MA,
PC)
Bondpad x 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1
(C4,MA,
RX)
LD 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0
Inductor
LD Induc- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0
tor (M1)
LM 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0
Inductor
LM Induc- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0
tor (M1)
MA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0
Inductor
MA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0
Inductor
(M1)
AM 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0
Inductor
LM 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0
rfline
MA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0
rfline
LM (sin- x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
glewire)
LM (cou- x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
pledwires)
LM (sin- x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
glecpw)
LM (cou- x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
pledcpw)


TURE (Generated)
MA x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
(sin-
glewire)
MA x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
(coupled-
wires)
MA (sin- x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
glecpw)
MA (cou- x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
pledcpw)
Salicide x 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
Blocked
ESD Reg-
ular NFET
Salicide x 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 0 0 0
Blocked
Thick
(2.5V)
ESD
NFET
Salicide x 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 1 0 1 1 0 0 0 0 0 0
Blocked
Thick
(3.3V)
ESD
NFET
Vertical 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 1
PNP not in
T3 isola-
tion well6
Vertical 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 1 1 0 1
PNP in T3
isolation
well7
N+/SX 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 P 0 0 P P 0 1
8
diode
N+/PW 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 P 0 0 P P 0 1
8
diode in
T3 isola-
tion well9
1. DE may be formed by dataprep outside the active device, where DE shapes = ((DG overlap past NW) not over BP). PH may be formed by dataprep
outside the active device, where PH shapes = NW(not over DG).
2. BH is generated for the NW isolation ring, but not under the active device.
3. Forward-biased junctions employed in bandgap reference circuits require an additional design level (DI) for model extraction and design rule
checking. See section 3.14 , Forward-Biased Diode Layout Rules on page 206. .

4. For P+ Poly and OP RR Poly resistors, PH is generated over the ends of these two resistors, where PC intersects difference [NW. DPH1], where
DPH1 is defined in the PH row in Table 8, Shape Manipulation Prior to Mask Write, on page 59 and represents the high resistance portion of the
device.
5. For the RP resistor, PH is not generated over the ends of the resistor as defined in the PH row in Table 8, Shape Manipulation Prior to Mask Write,
on page 59.
6. Also referred to as a P+/NW diode. See See section 3.12 , ESD Rules on page 190. and See section 3.13 , ESDIODE Layout Rules on
page 203. .
7. Also referred to as a P+/NW diode. This is a separate device because it does not use the ESDIODE utility level.
8. NW in this device is referring to the N-well guardring which is required.
9. The N+/SX diode, when placed inside a T3 isolation well, effectively becomes a NPN physical device.
Table 16. Design Truth Table for Dummy Design Levels
STRUC- Dummy Design Levels

TURE
I D D V S Z D B B B I I x x T x P S E E V V V V E E S M M N
B I I A C E i F F O N N x x R x C I F S N N N N S S B I I W
L V R H R o M M N D D _ _ A T F L U D C C C C D L M M
K P K O d O O D _ N R U P S I A A A A U D K _ _ _
N Y V e A A P C R S A S C E O P P P P M _
P T T T A F O F M N E R D _ _ _ M C H N R
I D I I L I S E E M P C Y D K I E
N L L I S S x A O M S
D T N R U
E M N
T
T3 over IBLK 1 0 0 0 0 0 0 0 0 0 0 0 0 0 x x 0 0 0 0 x x x x 0 0 0 x x 0
Well Isola-
tion or T3
Well N-band
contact
T3 Isolation 0 0 0 0 0 0 x 0 0 x 0 0 0 0 x x x 0 x 0 x x x x x x x x x 0
Pwell
T3 Isolation 0 x x x 0 0 x 0 0 x 0 0 0 0 x x 0 0 0 1 x x x x x x x x x 0
Nwell not
over IBLK
T3 Isolation 0 0 0 0 0 0 x 0 0 x 0 0 c c x x 0 0 0 0 x x x x x x 0 x x 0
Pwell Con-
tact
T3 Isolation 0 x x 0 0 0 x 0 0 x 0 0 c c x x 0 0 0 x x x x x x x 0 x x 0
Well Internal
NW Contact
T3 Isolation 0 0 0 0 0 0 x 0 0 0 0 0 c c x x 0 0 0 x x x x x x x 0 x x 0
Well Exter-
nal NW Con-
tact (same as
bulk NW con-
tact)
T3 Isolation 0 0 0 0 0 0 x 0 0 0 0 0 c c x x 0 0 0 0 x x x x x x 0 x x 0
Well N+ junc-
tion
T3 Isolation 0 x x 0 0 0 x 0 0 x 0 0 c c x x 0 0 0 x x x x x x x 0 x x 0
Well P+ junc-
tion


TURE
D T N R U
E M N
T
Regular 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x 0 0 0 0 x x x x x x x x x 0
NFET
Regular 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x 0 0 0 0 x x x x 0 0 0 x x 0
PFET
LP NFET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x 0 0 0 0 x x x x 0 0 x x x 0
LP PFET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x 0 0 0 0 x x x x 0 0 0 x x 0
LVT NFET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x 0 0 0 0 x x x x 0 0 x x x 0
LVT PFET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x 0 0 0 0 x x x x 0 0 0 x x 0
ZVT Thin 0 0 0 0 0 1 0 0 0 0 0 0 0 0 x x 0 0 0 0 x x x x 0 0 x x x 0
NFET
ZVT Thick 0 0 0 0 0 1 0 0 0 0 0 0 0 0 x x 0 0 0 0 x x x x 0 0 0 x x 0
NFET
Thick 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x 0 0 0 0 x x x x x x x x x 0
NFET25
Thick 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x 0 0 0 0 x x x x 0 0 0 x x 0
PFET25
Thick 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x 0 0 0 0 x x x x 0 0 x x x 0
NFET33
Thick 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x 0 0 0 0 x x x x 0 0 0 x x 0
PFET33
HIVT 3.3V 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x 0 0 0 0 x x x x 0 0 x x x 0
NFET
HIVT 3.3V 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x 0 0 0 0 x x x x 0 0 0 x x 0
PFET
Thin Triple 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x 0 0 0 x x x x x 0 0 x x x 0
Well NFET
Thick Triple 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x 0 0 0 x x x x x 0 0 x x x 0
Well NFET
Triple Well 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x 0 0 0 x x x x x 0 0 x x x 0
Isolation
Triple Well 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x 0 0 0 x x x x x 0 0 0 x x 0
Contact
HAVaractor / 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x 0 0 0 0 x x x x 0 0 0 x x 0
Diff HAVAR


TURE
D T N R U
E M N
T
N+ Junction 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x 0 0 0 0 x x x x x x 0 x x 0
Substrate 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x 0 0 0 0 x x x x x x 0 x x 0
Contact
P+ Junction1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x 0 0 0 x x x x x x x 0 x x 0
N-well Con- x 0 0 0 0 0 0 0 0 0 0 0 0 0 x x 0 0 0 x x x x x x x 0 x x x
tact
SBD 0 0 0 0 1 0 0 0 0 0 0 0 0 0 x x 0 0 0 0 x x x x 0 0 0 x x 0
DI Diode (2 0 1 0 0 0 0 0 0 0 0 0 0 0 0 x x 0 0 0 0 x x x x 0 0 0 x x 0
terminal)
DI Diode (3 0 1 1 0 0 0 0 0 0 0 0 0 0 0 x x 0 0 0 0 x x x x 0 0 0 x x 0
terminal)
Electronic 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x 1 0 1 0 0 0 0 0 0 0 0 x x 0
Fuse
OP N+ diffu- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x 0 0 0 0 x x x x x x x x x 0
sion resistor
OP N+ diffu- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x 0 0 0 0 x x x x x x x x x 0
sion resistor,
PI
OP P+ poly 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x 0 0 0 0 x x x x x x 0 x x 0
resistor
OP P+ poly 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x 0 0 0 0 x x x x x x 0 x x 0
resistor
(over_NW)
PC P+ poly 0 0 0 0 0 0 0 1 0 0 0 0 0 0 x x 0 0 0 0 x x x x x x 0 x x 0
resistor
(over_BFMO
AT)
OP RR PC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x 0 0 0 0 x x x x x x 0 x x 0
poly resistor
poly resistor
(over_NW)
poly resistor
(over_BFMO
AT)
OP RP PC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x 0 0 0 0 x x x x x x 0 x x 0
poly resistor


TURE
D T N R U
E M N
T
poly resistor
(over_NW)
poly resistor
(over_BFMO
AT)
N-well 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x 0 0 0 0 x x x x x x 0 x x 1
Resistor
Silicided Pol- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x 0 1 0 0 x x x x x x 0 x x 0
ysilicon resis-
tor
L1 BEOL x x x x x x x x 0 0 0 0 0 0 0 0 x x x x x x x x x x x x x x
resistor
Kx BEOL x x x x x x x x 0 0 0 0 0 0 0 0 x x x x x x x x x x x x x x
resistor
(x=2,3,4,5 or
6)
PCDCAP 0 0 0 1 0 0 0 0 0 0 0 0 0 0 x x 0 0 0 0 x x x x 0 0 0 x x 0
Thin Oxide
Varactor Thin
Oxide / Diff
NCAP
PCDCAP 0 0 0 1 0 0 0 0 0 0 0 0 0 0 x x 0 0 0 0 x x x x 0 0 0 x x 0
Thick Oxide /
Varactor
Thick Oxide
Hi-K MIM x x x x x x x x 0 0 0 0 0 0 0 0 x 0 x x x x x x x x x 1 0 x
(QT, HT)
Single Nitride x x x x x x x x 0 0 0 0 0 0 0 0 x 0 x x x x x x x x x 0 1 x
MIM
(QT, HT)
Dual Nitride x x x x x x x x 0 0 0 0 0 0 0 0 x 0 x x x x x x x x x 0 1 x
MIM (QT,
HT, KT)
Single HP x x x x x x x x 0 0 0 0 0 0 0 0 x 0 x x x x x x x x x 0 1 x
MIM (QY)
Dual HP MIM x x x x x x x x 0 0 0 0 0 0 0 0 x 0 x x x x x x x x x 0 1 x
(QY, HY)
VNCAP x x x x x x x x 0 0 0 0 0 0 0 0 x 0 x x 1 1 1 1 x x x x x x


TURE
D T N R U
E M N
T
Bondpad 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x 0
(WB,LD,
BFMOAT or
M1)
Bondpad 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x 0
(WB,LD, PC)
Bondpad 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x 0
(WB,LD, RX)
Bondpad 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x 0
(C4,LD,
BFMOAT or
M1)
Bondpad 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x 0
(C4,LD, PC)
Bondpad 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x 0
(C4,LD, RX)
Bondpad 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x 0
(WB,LM,
BFMOAT or
M1)
Bondpad 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x 0
(WB,LM, PC)
Bondpad 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x 0
(WB,LM, RX)
Bondpad 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x 0
(C4,LM,
BFMOAT or
M1)
Bondpad 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x 0
(C4,LM, PC)
Bondpad 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x 0
(C4,LM, RX)
Bondpad 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x 0
(WB,MA,
BFMOAT or
M1)
Bondpad 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x 0
(WB,MA, PC)
Bondpad 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x 0
(WB,MA, RX)


TURE
D T N R U
E M N
T
Bondpad 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x 0
(C4,MA,
BFMOAT or
M1)
Bondpad 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x 0
(C4,MA, PC)
Bondpad 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x 0
(C4,MA, RX)
LD Inductor 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x 0
LD Inductor 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x 0
(M1)
LM Inductor 0 0 0 0 0 0 0 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x 0
LM Inductor 0 0 0 0 0 0 0 1 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x 0
(M1)
MA Inductor 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x 0
MA Inductor 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x 0
(M1)
AM Inductor 0 0 0 0 0 0 0 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x 0
LM rfline 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 x 0 0 0 0 0 0 0 x x 0
MA rfline 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 x 0 0 0 0 0 0 0 x x 0
LM x x x x x x 0 x 0 0 0 0 0 0 1 1 x 0 x x x x x x x x x x x x
(singlewire)
LM x x x x x x 0 x 0 0 0 0 0 0 1 1 x 0 x x x x x x x x x x x x
(coupled-
wires)
LM (sin- x x x x x x 0 x 0 0 0 0 0 0 1 1 x 0 x x x x x x x x x x x x
glecpw)
LM (coupled- x x x x x x 0 x 0 0 0 0 0 0 1 1 x 0 x x x x x x x x x x x x
cpw)
MA x x x x x x 0 x 0 0 0 0 0 0 1 1 x 0 x x x x x x x x x x x x
(singlewire)
MA x x x x x x 0 x 0 0 0 0 0 0 1 1 x 0 x x x x x x x x x x x x
(coupled-
wires)


TURE
D T N R U
E M N
T
MA (sin- x x x x x x 0 x 0 0 0 0 0 0 1 1 x 0 x x x x x x x x x x x x
glecpw
MA (coupled- x x x x x x 0 x 0 0 0 0 0 0 1 1 x 0 x x x x x x x x x x x x
cpw)
Salicide 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x 0 0 0 0 x x x x 1 1 1 x x 0
Blocked ESD
Regular
NFET2
Blocked
Thick (2.5V)
ESD NFET 2
Blocked
Thick (3.3V)
ESD NFET
Vertical 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x 0 0 0 1 x x x x 1 1 0 x x 0
PNP3 not in
T3 isolation
well
Vertical P 0 0 0 0 0 0 0 0 0 0 0 0 0 x x 0 0 0 1 x x x x 1 1 0 x x 0
PNP4 in T3
isolation well
N+/SX 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x 0 0 0 0 x x x x 1 1 0 x x 0
diode 2
N+/PW diode 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x 0 0 0 0 x x x x 1 1 0 x x 0
in T3 isola-
tion well 2
1. Forward-biased junctions employed in bandgap reference circuits require an additional design level (DI) for model extraction and design
rule checking. See section 3.14 , Forward-Biased Diode Layout Rules on page 206. .
2. ESDUMMY or ESD_CDM must be present. For more information see See section 3.12 , ESD Rules on page 190. .
3. ESDUMMY or ESD_CDM must be present, except when the Vertical PNP is used in for antiparallel circuit layout. For antiparallel circuit layout,
ESDUMMY or ESD_CDM design level is prohibited.
4. ESDUMMY or ESD_CDM must be present, except when the Vertical PNP is used in for antiparallel circuit layout. For antiparallel circuit layout,
ESDUMMY or ESD_CDM design level is prohibited.

Physical Layout Information Design Geometry Restrictions IBM
2.8 Design Geometry Restrictions

The following layout ground rules are present in the design rule checking deck.
Table 17. Geometry Restrictions
Rule C Notes Description

l
a
s
s
S1 a The design grid must be an integer multiple of 0.01 m
1
S2 a Shapes with acute angles are not allowed
S3 a Shapes that intersect and overlap themselves are not allowed (shapes that abut them-
selves are acceptable)
S4 a Shapes that cross over themselves are not allowed (also known as bow ties and
re-entrant shapes)
S5 a Shapes with zero area are not allowed
S6 a Only shapes that are orthogonal or on a 45 angle are allowed except in alphanumeric
labels
S7 a Shapes that are formed with two lines that never intersect are not allowed (also known
as inside-outside shapes)
S8 a Shapes that are formed with the line op code or path codes are not allowed to have 45
bends.
S9 a Line end segments formed with line op codes or path op codes must have a length to
width ratio > 0.50.
S10 a Text data (Alpha op code) is not allow on any mask build level
1. Acute notches verification is accomplished by the spacing rule for each design level (verification of the compliment of an obtuse
angle that is formed within a design level shape is accomplished by the spacing rule for each design level).

Physical Layout Information Design Geometry Restrictions
2.8.1 IBM Reserved Level Rules

The following rules correspond to the Reserved Levels described in Table 3, Design Service and Data Prep-
aration Levels (Restricted) on page 37, and Table 4, KERF Dummy Design Levels (Restricted) on page 43.
Table 18. Reserved Level Layout Rules1
Rule C Notes Description Design

l Min
a
s
s
RL01 a xxFILL touching CHIPEDGE is prohibited (xx = RX, PC, M1, M2, M3, M4, = -
M5, M6, MQ, MG, LM, LY, E1, MA, AM, OL, LD)
RL03 a xxEXCLUD touching CHIPEDGE is prohibited (xx = M1, M2, M3, M4, M5, = -
M6, MQ, MG, LM)
RL03a a 2 (xxEXCLUD not covered by TRANSMIS) touching CHIPEDGE is prohib- = -
ited (xx = LY, E1, MA, AM, OL, LD)
RL04 a xxCHEXCL touching CHIPEDGE is prohibited (xx = M1, M2, M3, M4, M5, = -
M6, MQ, MG, LM)
RL05 a xxHOLE touching CHIPEDGE is prohibited (xx = M1, M2, M3, M4, M5, = -
M6, MQ, MG, LM)
RL06 a xxHOLE touching CHIPEDGE is prohibited (xx = V1, V2, V3, V4, V5, VL, = -
VQ, VG)
RL07 a 3 {FRAME, NEGMKS, POSMKS} touching CHIPEDGE is prohibited = -
RL07a a {FUSE, KERFEXCL} touching CHIPEDGE is prohibited = -

RL08a a 4 xxHOLE touching CHIPEDGE is prohibited (xx = JT, OL) = -
OLCHEXCL touching CHIPEDGE is prohibited
RL09 a 5 {QQ,HQ} touching CHIPEDGE is prohibited = -
RL09a a 6 {JN,JP} touching CHIPEDGE is prohibited = -
1. Unless otherwise specified, the dummy design levels listed in this table are to be included in the IBM Design Kit technology file per
Table 3, Design Service and Data Preparation Levels (Restricted), on page 37, and are to be validated in DRC. For GL1, CDS or
GDSII information, see Table 3.
2. See related Rule TLR1 in Table 99, Transmission Line Rules, on page 276 which is also verified during DRC.
3. Rule not verified in DRC since these IBM reserved levels are not in the technology file.
4. IBM reserved levels. These levels are not used during IBM Data Preparation or Design Services. Rule is verified during DRC since
levels exist in the technology file.
5. These levels were used in support of the HiK MIM for the AM BEOL. This MIM is not qualified and support for these levels have
been dropped.
6. These levels are used in support of the 3.3V HiVt N/P-FETs. These fets are not qualified and support for these levels is restricted.
Contact your IBM Technical Representative for more information.

Physical Layout Information Important Design Guidelines IBM
2.9 Important Design Guidelines

The following design guidelines are not design rule checked which means a careful reading is particularly
important.
All wells must be contacted
Regular Array Layouts
Dummy cells or half cells are often used to terminate arrays. These are images that are not electrically active,
but serve to create a consistent physical environment across all of the active cells. Both RX and PC photo
effects have been observed that make the last cells on the edges of the array behave differently than the rest.
The addition of these dummy images will mitigate these effects.
Dynamic Circuits
Dynamic circuits are sensitive to leakage currents which could come from many sources. The designers must
ensure the circuits will function at all worst-case leakage conditions. Please refer to Section 4.0 , Electrical
Parameters and Models on page 335 for detailed information.
Keep dynamic nodes away from any junction that gets forward-biased (at least 3X minimum spacing
rules). If the junction is forward biased by an input-output (I/O) signal, an N-well guardring is recom-
mended.
Forward-Biased Diodes
The use of forward biased diodes is restricted to the bandgap reference circuit described Section 4.26 , For-
ward-Biased Diode Device Models on page 404.
Polysilicon and Diffusion Wiring
Narrow polysilicon (PC < 0.19 m wide) and diffusion lines (RX < 0.24 m wide) are highly susceptible to
defects which result in localized increases in the sheet resistance. The following design practices are strongly
recommended:
Narrow lines of polysilicon or diffusion must not be used in applications where DC voltage drops are
important.
Avoid chaining of gates.
Place contacts close to the end of the gate, preferably on both ends of the gate.
The length of narrow polysilicon or diffusion lines used for wiring should be kept to a minimum.
Leakage Sensitive Circuits
For circuits that are more sensitive to leakage than static logic designs, please see Section 4.0 , Electri-
cal Parameters and Models on page 335 for leakage-dictated design constraints.
No Polyimide Final Passivation Option - Modeling Implications

Physical Layout Information Important Design Guidelines
If a No Polyimide Final Passivation Feature is used (see Table 1, Optional Features with Feature Part
numbers, on page 11) the Polyimide elimination is not accounted for in the device models. See section
3.41 , No Polyimide Final Passivation option on page 332 for layout definition and Note: on page 432
for inductor modeling impact.
Mixed Voltage Interfaces
Special consideration must be given when the design will interface to a voltage above 1.6V. See Section
4.39 , Mixed Voltage Interfaces on page 450.
Relaxed Designs and Recommended Rules

Process and reliability yields will generally improve when designs are relaxed from the ground rule mini-
mums. Minimum design dimensions should only be used to decrease the chip size or to improve the
device performance.
Design rules requiring exact dimensions (denoted by in the rule tables) are not to be relaxed.
By using recommended rules R, higher product yields may be expected
Contacts and Vias
Using redundant contacts and vias is strongly recommended to prevent contact open circuits in the
design. See the recommendations in General Rules at 100C/100K POH on page 491 for using contacts
and vias in wide lines.
The electromigration reliability in terms of minimum intersection area of M1/CA, M2/V1, and so forth,
must be verified as described in Section 5.4 , Back End Of Line (BEOL) Reliability Design Rules on
page 489. Verification is particularly important for designs that will be miniaturized in future technologies.
Jogs and Non-orthogonal Lines

Minimize the use of jogs below 0.25 m in order to increase repairability of masks. Defects in the vicinity
of jogs < 0.25 m are generally not repairable.
Avoid the use of 45 lines. Their use increases data volumes and the possibility of checking errors. Note
that 45 lines are not allowed on several design levels as detailed in the Layout Rules tables.
The compact device models do not reflect bent-gate structures due to the inherent three dimensional
nature of these devices and the variable gate length at the bents.
Reducing White Space on the PC Level
In order to meet the stringent across-chip line-width variation (ACLV) and chip mean variation require-
ments of the device channel length and to minimize planarization problems at subsequent levels, IBM has
added a local PC fill requirement, see Local PC Pattern Density Requirements on page 90. High local
PC density is caused by large areas of dense polysilicon (e.g. decoupling capacitors) that can degrade
the ACLV. See Section 4.19.1 , MOS varactor Design on page 390 for more information on spacing
from these type of structures.
Reducing White Space on the RX Level

In order to adequately control the shallow trench isolation etch and polish processes, a global RX-density
constraint (see Section 2.10 , Pattern Density Rules on page 87) and a local RX-density constraint (see
Rule 40 in Table 21, Polysilicon and Isolation Layout Rules, on page 95). are required. IBM recommends

Physical Layout Information Important Design Guidelines IBM
using the RXFILL shapes that are automatically generated during data preparation by IBM during the
release process.
Chip Origin
The chip origin (x=0, y=0) must be placed at the lower left corner of the chip. CHIPEDGE must be
bounded at X=0 on the left side of the chip (not in the chamfer area), and bounded at Y=0 at the bottom
of the chip. See rule 999 in Table 114, Chip Guard Ring Rules, on page 319.
Layout Rule Table Notes

The following notes apply to the tables in the Layout Rules section (starting with Table 21 on page 95 through
Table 118 on page 334).
1. All layout rules are given in m or in m2.
2. Rules ending with the letter R, such as 104R, indicate that they are strong recommendations for a
designer to follow. Recommended rules are not present in all checking decks.
3. Rules ending with the letter M, such as 51M, indicate that they are required for the design to be
migrated (shrunk) into future technologies. These rules are not requirements for designs only to be
built in the technology described in this document.
4. While most wafer nominal dimensions refer to the bottoms of features, the following conventions are
followed:
4a) Widths of features are the width at the bottom.
4b) Spaces between like features are the minimum distance. For example, for poly lines the distance
is bottom-bottom, while stud contacts and stud vias the distance is top-top.
4c) Spaces between features on different levels are the horizontal component of the distance
between the bottom of the upper feature to the top of the lower feature.
4d) RX features are measured from the bottom of the silicide, which is the top of the isolation trench.
4e) Deviations from these conventions are noted in the tables.
5. Use of length indicates that the shape is required to be a rectangle.
6. RX Rules: RX denotes the active silicon region (source, drain, FET channel, capacitor, etc.) which is
also known as diffusion and as thin oxide. Where distinction is useful, junctions and contacts are dis-
tinguished.
OP resistors
The use of the n+-type poly and p+-type diffusion resistors are not offered due to higher overall process
tolerances.
The poly width should be greater than 1.5 m in order to obtain reasonably small absolute variation.

Physical Layout Information Pattern Density Rules
2.10 Pattern Density Rules
2.10.1 Global Pattern Density
Table 19. Global Pattern Density Rules1
Rule C Notes Description Design Design

l Min. Max.
a
s
s
PDRX b 2,3,4 (Summed RX area across full chip) / (CHIPEDGE area) 25% 75%
PDPC b 2,5,6
(Summed PC area across full chip) / (CHIPEDGE area) 15% 30%
PDQT a 7 (Summed QT area across full chip) / (CHIPEDGE area) 0% 40%
PDOL a 7 (Summed OL area across full chip) / (CHIPEDGE area) 27% 70%
PDVV a 7 (Summed {VV, VVBAR} area across full chip) / > 0% 10%
(CHIPEDGE area)
PDLD a 7 (Summed LD area across full chip) / (CHIPEDGE area) 27% 70%
PDQY a 8 (Summed QY area across full chip) / (CHIPEDGE 0% 40%

area)
PDLY a 8
(Summed LY area across full chip) / (CHIPEDGE area) 27% 70%
PDE1 a 8
(Summed E1area across full chip) / (CHIPEDGE area) 23% 70%
PDMA a 8
(Summed MA area across full chip) / (CHIPEDGE 27% 70%
area)
PDAM a 9 (Summed AM area across full chip) / (CHIPEDGE 27% 70%

area)
PDDV a 10,11 (Summed (DV intersect last metal) area across full 0% 20%
chip) / (CHIPEDGE area)
PDFV a 12 (Summed (FV intersect TD) area across full chip) / 0% 20%
(CHIPEDGE area)
PDLV a 13 (Summed (LV intersect last metal) area across full 0% 20%
chip) / (CHIPEDGE area)
1. These rules will be checked as part of the IBM release process.
2. Rules PDRX and PDPC apply to all metallization options.

Physical Layout Information Pattern Density Rules IBM
3. The RX Design Min (minimum) Global Pattern Density rule is not checked in the Design Kit. IBM prefers that the RX minimum Global
Pattern Density is not checked by the customer, or attempted to be met by the customer, prior to submission of the chip design to
IBM. The RX minimum Global Pattern Density for the chip design will be verified by the IBM release team to this rule requirement after
IBM-generated RXFILL is applied to the chip design, which is part of the IBM release process. After IBM auto-generated RXFILL is
applied, the RX minimum Global Pattern Density must be met as a requirement. Any chip design aspects that prohibit the RX Global
Pattern Density minimum from being met will require modification prior to final design submission. The RX maximum Global Density
Rule is checked in the Design Kit and should not be exceeded upon chip design submission to IBM.
4. The interpretation of the RX density value for the Design Maximum in the Global Pattern Density rule is for the drawn RX shapes in the
chip design. When feasible, it is recommended that designers avoid submitting designs to IBM close to the maximum RX global
pattern density limit.
5. The PC Design Min (minimum) Global Pattern Density rule is not checked in the Design Kit. IBM prefers that the PC minimum Global
Pattern Density is not checked by the customer, or attempted to be met by the customer, prior to submission of the chip design to
IBM. The PC minimum Global Pattern Density for the chip design will be verified by the IBM release team to this rule requirement after
IBM-generated PCFILL is applied to the chip design, which is part of the IBM release process. After IBM generated PCFILL is applied,
the PC minimum Global Pattern Density must be met as a requirement. Any chip design aspects that prohibit the PC Global Pattern
Density minimum from being met will require modification prior to final design submission. The PC maximum Global Density Rule is
checked in the Design Kit and should not be exceeded upon chip design submission to IBM.
6. The interpretation of the PC density value for the Design Maximum in this Global Pattern Density rule is for the drawn PC shapes in the
chip design, prior to the inclusion of IBM generated PCFILL. After the IBM release process is completed, (PC + IBM generated
PCFILL) may exceed this value. This effect is anticipated and is accounted for the Manufacturing Process assumptions.
7. Rules PDQT, PDOL, PDLD apply for the OL with LD metallization options.
8. Rules PDQY, PDLY, PDE1, PDMA apply for the MA metallization options.
9. Rule PDAM applies for the AM metallization option.
10. Wirebond Final Passivation applies to all metallization options.
11. For designs using the LM Metallization scheme PDDV should be interpreted as DV intersect TD since the TD layer is used for the
wirebond pad.
12. C4 Final Passivation for LM metallization option.
13. C4 Final Passivation for OL with LD, AM, or MA metallization options.
RX and PC General Pattern Density Requirements

Minimum-density requirements for RX and PC are normally satisfied by the use of IBM-generated FILL
shapes on those levels, and need not be satisfied before the design is released to IBM. If a particular design
does not use IBM-generated FILL shapes on any of these levels, the minimum-density requirement for that
level must be met as-designed.
Global RX Pattern Density Requirements

The CMRF8SF RX manufacturing process requires that the chip-average RX density be between 25% and
75% (see Table 19, Global Pattern Density Rules, on page 87).
The CMRF8SF Shallow Trench Isolation manufacturing process requires that local RX density be at least
20% over a distance of 126 m (Primary Layout Rule EPDL_RX). This STI-specific process requirement can
be satisfied by inactive dummy shapes placed by the designer on the level RX. Although non-functional from
a circuit perspective, these added shapes must satisfy all of the design rules applicable to RX. Alternatively,
dummy shapes generated on the reserved level RXFILL (available from IBM Product Engineering as a part of
the standard Tape-out and Release process) will also satisfy the STI manufacturing process requirements,
and with potentially much less design effort.
If RXFILL programs are to be used, shapes must be added to mark all of the following structures for exclu-

sion from RXFILL:
- product label area: IBM will place RXFILL shapes within product label areas defined by the design
level LOGOBND. If designers seek to exclude RXFILL shapes from the product label area, draw
RXEXCLUD over the entire product label. The local RX density within such RXEXCLUD shapes must
satisfy the minimum local-RX-density (see Rule EPDL_RX in Table 247 on page 565). For additional
information on LOGOBND, see section 3.40 , Product Labels on page 328.
- other regions: in certain rare circumstances it may be beneficial to exclude RXFILL shapes from
other circuit regions; draw RXEXCLUD to cover such regions. The local RX density within such
RXEXCLUD shapes must satisfy the minimum local-RX-density (see Rule EPDL_RX in Table 247 on
page 565). Contact IBM Product Engineering for detailed guidelines.
N-well resistors. Draw RXEXCLUD over the body of all n-well resistors. See Rule NWR06 in
Table 69, N-well Resistor Layout Rules, on page 217.
See additional information in section , Local RX Pattern Density Requirements on page 89
Global PC Pattern Density Requirements

The CMRF8SF PC manufacturing process requires that the chip-average PC density be between 15% and
30% (see Table 19, Global Pattern Density Rules, on page 87). This process requirement can be satisfied
by inactive dummy shapes placed by the designer on the level PC. Although non-functional from a circuit per-
spective, these added shapes must satisfy all of the design rules applicable to PC. Alternatively, dummy
shapes generated on the reserved level PCFILL (available from IBM Product Engineering as a part of the
standard Tape-out and Release process) will also satisfy the manufacturing process requirements. Rule
EPDG_PC checks for minimum PC global density issues by estimating the results of the IBM PCFILL place-
ment algorithm. For more details on rule EPDG_PC see Table 247, Estimated Pattern Density Rules on
page 565.
If PCFILL programs are to be used, shapes must be added to mark all of the following structures for exclu-
sion from PCFILL:
- product label area: draw LOGOBND over the entire product label. See section 3.40 , Product
Labels on page 328.
- other regions: in certain rare circumstances it may be beneficial to exclude PCFILL shapes from
other circuit regions; draw PCEXCLUD to cover such regions. IBM recommends that the local PC
density within such PCEXCLUD shapes should still satisfy the minimum local-PC-density (Primary
Layout Rule EPDL_PC). Contact IBM Product Engineering for detailed guidelines.
2.10.2 Local Pattern Density
Local RX Pattern Density Requirements

The CMRF8SF Shallow Trench Isolation manufacturing process requires that local RX density be at least
20% over a distance of 126 m (see Layout Rule EPDL_RX in Table 247, Estimated Pattern Density Rules,
on page 565).

All portions of the chip, except those specifically stated in Section Global RX Pattern Density Requirements
on page 88 will receive RXFILL shapes as part of the standard Tape-out and Release process. If RXFILL
generation is not performed by Product Engineering, the minimum local-RX-density (see Layout Rule
EPDL_RX) must be met for the entire design, as specified in Table 247, Estimated Pattern Density Rules, on
page 565. If RXFILL generation is performed by Product Engineering, Rule EPDL_RX must be met within
every region. Note that certain discouraged design practices, such as long dense runs of PC wiring, are not
compatible with RXFILL. Contact your IBM technical representative for more guidelines.
Local PC Pattern Density Requirements

The CMOS8RF (CMRF8SF) PC manufacturing step recommends a local PC density be between 5% and
80%. Because of this recommendation, PCFILL shapes are often required. All portions of the chip, except
those specifically stated in Section Global PC Pattern Density Requirements on page 89 will receive
PCFILL shapes as part of the standard Tape-out and Release process.
If PCFILL generation is not performed by Product Engineering, the minimum recommended local-PC-density
(see Layout Rule EPDL_PC) is specified in Table 21, Polysilicon and Isolation Layout Rules, on page 95. If
PCFILL generation is performed by Product Engineering, Rule EPDL_PC is still recommended to be met
within every region. Contact your IBM technical representative for more guidelines.
Local Metal Pattern Density Requirements

Copper Pattern Density Layout Requirements (for LM and MA and AM and OL with LD last metal
options)
The CMOS8RF (CMRF8SF) Copper manufacturing process requires several design constraints on the wiring
levels that are not necessary for Aluminum and Tungsten/Oxide based technologies. Specifically, local
regions of very-high or very-low metal pattern density are difficult to manufacture, as are very wide wires or
very wide regions of whitespace. Because of these constraints, IBM-generated Metal FILL and Metal HOLE
shapes are required for all CMOS8RF (CMRF8SF) designs. All portions of the chip except those specifically
enumerated below will receive Metal FILL and Metal HOLE shapes from IBM Product Engineering as a part
of the standard Tape-out and Release process.
Wide Copper Mx (x=1,2,3,4,5,6,Q,G) wires (structures) or LM wires (structures) that violate the spirit of the
wide line restrictions (see Rules 500b, 600b, 635b, or 690b) will receive special MxPLANE (x = 1,2,3,4,5,6,Q,
G) or LMPLANE level for 70% pattern density by IBM Design Services. For more guidelines, IBM Product
Engineering.

Figure 5. IBM-generated Metal Fill Shapes
IBM-generated MxFILL shapes are small, electrically-isolated metal shapes on a staggered grid. They are
squares, three times as large as the minimum linewidth for that metal level. The closest approach of an
MxFILL shape to Mx is twice the minimum space for that metal level. See Table 244, xxFILL Rules, on
page 549.

Figure 6. IBM-generated Metal HOLE shapes
IBM-generated MxHOLE shapes lie on the same staggered grid as MxFILL shapes, and are resolved at
Mask-write as small openings in the associated metal level. HOLE shapes are squares, two times as large as
the minimum linewidth for that metal level, and are only placed within wide metal. The closest approach of an
MxHOLE shape to the inside edge of an Mx line is twice the Mx minimum linewidth. HOLE shapes do not
obstruct single vias, single rows of vias or double rows of vias, and M1HOLE shapes do not obstruct CA or
CABAR shapes. MxHOLE shapes are allowed to touch or intersect a fraction of the vias directly above or
below Mx if those vias are redundant, as for example those in a dense array of vias contacting the same wide
metal above and below (See Figure 6). Typically 80% of the metal/via/metal intersect-area in such an array is
unobstructed by MxHOLE shapes. The via resistances specifications in Table 171, Corrected Linewidth for
Wires with HOLE Shapes, on page 419 are met for any collection of vias, even in the presence of IBM-gen-
erated HOLE shapes.
VxHOLE shapes are used to remove from the design those few redundant vias that are covered or
nearly-covered by a metal hole on the level immediately above.
The specified capacitance of the BEOL dielectric (4.31 Wiring Capacitance Models on page 421) and the
specified metal sheet resistance (Table 170, Conducting Film Thicknesses and Sheet Resistances at 25C,
on page 417 and Table 167, Capacitance Parameters for SBDI Diode, on page 410) anticipate the place-
ment of generated Fill and Hole shapes, and accurately reflect their effects on the measurable wiring resis-
tance and capacitance. Contact IBM Product Engineering for further details.
As MxFILL and MxHOLE shapes are generated for every design in CMOS8RF (CMRF8SF), shapes must be
added to mark all of the following specific structures for exclusion or modification:
Modelled Wirebond or C4 pads: draw BONDPAD to cover LM or MA or LD. See Section 3.35 , Ter-
minals, IO Pads, C4 and Wirebond on page 276. Drawing BONDPAD is not required for typical
non-modelled wirebond or C4 pads. No explicit MxEXCLUD shapes are required or recommended

for wirebond pads; all necessary exclude shapes are automatically generated in Design Services.
Chip guardring: draw GUARDRNG to cover the guardring structure. No explicit MxEXCLUD or
MxCHEXCL shapes are required or recommended for the Chip Guard Ring; all necessary exclude
shapes are automatically generated in Design Services. See Section 3.37 , Chip Guard Ring and
Chamfer on page 318.
Product Label area: draw LOGOBND over the entire product label. See Section 3.40 , Product
Labels on page 328.
Inductors: draw IND or IND_FILT (or both IND and IND_FILT) to cover the body of the inductor. See
Section 3.33 , Inductor Layout Rules on page 267.
RF Interconnect Line: See Section 3.34.1 , MA RF Interconnect Line Layout Rules on page 274 or
Section 3.34.2 , LM RF Interconnect Line Layout Rules on page 275. For MA rfline device: draw
MA_RFLINE. For LM rfline device: draw LM_RFLINE.
Transmission Lines: IBM uses TRANSMIS to cover the body of the transmission line. See TRANS-
MIS in Table 6, Dummy Design Levels and Utility Levels on page 46. The TRANSMIS shape
enables the use of xxEXCLUD (xx = LY, E1, MA) per Rules RL03a. Note that MxEXCLUD
(x=1,2,3,4,5,6,Q, G) or LMEXCLUD use is prohibited. Transmission line structures receive IBM
auto-generated MxFILL on the Mx (x=1,2,3,4,5,6,Q,G) or LM mask levels during the IBM release pro-
cess.
Kx BEOL Resistor (where x=2,3,4,5,6): IBM uses the Kx design level to prohibit MxFILL physically
under these devices. When Kx BEOL resistors are placed in a chip design, Rule EPDL_Mx, where
x=2,3,4,5,6(see Table 34, Mx (x=2,3,4,5, 6) Metal and Via Layout Rules on page 141) must be met
prior to design submission to IBM, and Rule PD4a (see Table 246, Pattern Density Rules (Post
Cheese and Fill) on page 562) must be met after IBM-generated Metal FILL is applied as a part of
the standard IBM Product Engineering Tape-out and Release process.
Note: MxEXCLUD or MxCHEXCL shapes are prohibited without prior approval of IBM Product Engineer-
ing, where Mx = 1,2,3,4,5,6,Q,G. LMEXCLUD or LMCHEXCL shapes are prohibited without prior
approval of IBM Product Engineering.
Additional Copper or Aluminum Pattern Density Layout Requirements (for non-LM last metal options)
The following rules describe additional layout rules to be met if the designer includes inactive metal shapes
prior to design submission to IBM. The inactive metal shapes drawn by the customer must be on the existing
metal drawing levels and can not be on the reserved levels xxFILL.
For further details on the IBM FILL-aware checking decks, or to have IBM fill the design in lieu of the designer
including inactive metal shapes, contact your IBM Product Engineering Representative.
Table 20. Additional LD or OL or LY or E1 or MA or AM Rules1

l Min
a
s
s
F27a b 2 Inactive LY area (m2) maximum per shape 100.0

Table 20. Additional LD or OL or LY or E1 or MA or AM Rules1

l Min
a
s
s
F27b b 3 Inactive {E1, OL} area (m2) maximum per shape 100.0
F27c b 4, 5 Inactive {MA, LD, AM} area (m2) maximum per shape 100.0
1. Inactive xx (where xx = metal level name) identified in this table refers to electrically inactive shapes drawn by the designer on the
respective LD, OL, LY, E1 or MA design levels. xx does not refer to the xxFILL shapes designed on these levels that are reserved for
IBM use only.
2. Inactive LY shapes are checked as: LY not touching (FY or (FT or FTBAR) or TRANSMIS or LOGOBND)
3. Inactive E1 shapes are checked as: E1 not touching ((FT or FTBAR) or (F1 or F1BAR) or TRANSMIS or LOGOBND). Inactive OL
shapes are checked as: OL not touching ((JT or JTBAR) or (VV or VVBAR) or TRANSMIS or LOGOBND)].
4. Inactive MA shapes are checked as: MA not touching ((F1 or F1BAR) or (LV or LVDUMMY or DV) or TRANSMIS or MA_RFLINE or
LOGOBND). Inactive LD shapes are checked as: LD not touching ((VV or VVBAR) or (LV or LVDUMMY or DV) or TRANSMIS or
LOGOBND). Inactive AM shapes are checked as: AM not touching ((FQ or FQBAR) or (LV or LVDUMMY or DV) or TRANSMIS or
LOGOBND)
5. Inactive MA, AM, or shapes are only required to meet Global Pattern Density Requirements. There is no local pattern density
requirement for MA or AM.

Layout Rules Polysilicon and Isolation Layout Rules
3.0 Layout Rules

Column Named: Class, adjacent to Rule column, specifies Manufacturability Rule Classification with
respect to DRC violations:
a. = Automatic Reject (severity 1)
Possible impact to either: production tools or processes
Possible impact to either: IBM Kerf and/or WAC
Possible impact to mask build
Possible impact to other rider (multi-client MPW)
b. = Significant Yield / Reliability Impact (severity 2)
c. = Moderate Yield / Reliability Impact (severity 3)
d. = Yield Enhancement (recommend compliance) (severity 4)
3.1 Polysilicon and Isolation Layout Rules

All layer names referred to in this design manual are design level names unless otherwise stated. For layer
names see section 2.0 , Physical Layout Information on page 27.
Table 21. Polysilicon and Isolation Layout Rules
Rule C Notes Description Des Waf. Tol.

l Min. Dim.
a
s
s
1 a 1 PC width over RX for NFET device Lp. 0.12 0.092 0.022
2 a 1 PC width over RX for PFET device Lp. 0.12 0.092 0.022
3 c 1 PC width over RX for 45 NFET device Lp. 0.127 0.0990 0.029
3R d 1 PC width over RX for 45 NFET device Lp. 0.140 0.1120 0.029
4 c 1 PC width over RX for 45 PFET device Lp. 0.127 0.0990 0.029
4R d 1 PC width over RX for 45 PFET device Lp. 0.140 0.1240 0.029
10 a RX width under PC for NFET device W. 0.16 0.1150 0.040
11 a RX width under PC for PFET device W. 0.16 0.1150 0.040
40 a This rule has been superseded by rule 20 - -

EPDL_RX on page 565.
EPDL_RX a 2,3,4 (rx_estimated) minimum density (%) over local 20 - -

126m x 126m areas stepped in 63m incre-
ments across the chip (where rx_estimated is
defined in rule EPDL_RX on page 565) ,
except those checking boxes that touch
LOGOBND or corner chamfers (PROTECT).

Layout Rules Polysilicon and Isolation Layout Rules IBM

l Min. Dim.
a
s
s
41 a 2,5 RX maximum density (%) over local 126m x 75 - -
126m areas stepped in 63m increments
across the chip.
EPDG_PC a (pc_estimated) minimum Global density (%), 15 - -

where pc_estimated is defined in rule
EPDG_PC on page 566.
EPDL_PC a (pc_estimated) minimum density (%) over local 5 - -

400m x 400m areas stepped in 200m incre-
ments across the chip (where pc_estimated is
defined in rule EPDG_PC on page 566),
except those checking boxes that touch
LOGOBND or corner chamfers (PROTECT).
42aR d 6,7 This rule has been superseded by rule 5 - -

EPDL_PC on page 566.
42bR d 6,8 PC maximum density (%) over local 126m x 80 - -

across the chip. This rule applies to all regions
of the chip except regions within VAR.
50 a RX width (silicide). 0.16 0.1150 0.040
50b b RX width (silicide), in at least one direction, 100.00 - -

minor dimension.
50R d RX width (silicide). 0.24 0.1950 0.040
51 a RX area (m2). 0.100 - -
51R d RX area (m2). 0.140 - -
52 b RX to RX space (trench). 0.18 0.2100 0.044
52R d RX to RX space (trench). 0.26 0.2900 0.044
100 a PC width not over RX (w/o spacer). 0.12 0.092 0.022
100R d PC width not over RX (w/o spacer). 0.19 0.1620 0.022
101a a PC area (m2). 0.105 - -
101b a PC enclosed area (m2). 0.151 - -
102 b (PC to PC space) not over RX. 0.20 0.1630 0.022


l Min. Dim.
a
s
s
102R d (PC to PC space) not over RX. 0.26 0.2230 0.022
104a b (PC to PC) over RX (NFET spacing). 0.20 0.0847 0.026
104b b (PC to PC) over RX (PFET spacing). 0.20 0.0847 0.026
104R d (PC to PC) over RX. 0.26 - -
110 b RX overlap past PC (silicide width).This Rule is 0.20 0.1199 0.065

checked as outside edge of PC to inside edge of
RX except for floating gate tie-downs. See two
usage examples in Figure 7, Isolation and Poly-
silicon Rules on page 103.
110R d RX overlap past PC (silicide width) 0.33 0.2499 0.065

This Rule is checked as outside edge of PC to
inside edge of RX except for floating gate
tie-downs.
110a b ((RX overlap past PC) not over GRLOGIC) (sili- 0.55 0.4699 0.065
cide width). This Rule is checked as outside
edge of PC to inside edge of RX except for float-
ing gate tie-downs. See one example in Figure
7, Isolation and Polysilicon Rules on page 103.
Note: Rule 110a only applies to RX (diffusion)
overlap past PC (gate edge) on the same FET.
110aR d ((RX overlap past PC) not over GRLOGIC) (sili- 0.680 0.5999 0.065
cide width)
This Rule is checked as outside edge of PC to
inside edge of RX except for floating gate
tie-down shapes.
Note: Rule 110aR only applies to RX (diffusion)
overlap past PC (gate edge) on the same FET.
111 b PC overlap past RX, when [(PC intersect RX) to 0.23 0.0845 0.068
RX corner 0.08 m] and [PC(END) area not
over RX <0.046m2].
111b b PC overlap past RX, when [PC(END) area not 0.200 - -

over RX 0.046m2].
111R d PC overlap past RX, when [(PC intersect RX) to 0.25 - -

RX corner 0.08m] and [PC(END) area not
over RX < 0.046m2].


l Min. Dim.
a
s
s
112 b PC overlap past RX, when (PC intersect RX) to 0.28 0.0345 0.077
RX corner < 0.08 m.
112R d PC overlap past RX, when (PC intersect RX) to 0.30 - -

RX corner < 0.08 m.
113b c PC to RX, for common run lengths >2.00m 0.08 - -

(See rule 130b).
113R d PC to RX for low PC wiring capacitance (except 0.08 0.1130 0.064

where PC is tied to RX).
114 c PC to RX corner, when RX corner and gate are 0.06 -0.007 0.074
on same FET.
114b c 9 PC to RX corner, when RX notch width < 0.28 0.10 -0.007 0.074
and RX corner and gate are on same FET.
114c c 9 PC to RX corner, when RX notch width < 0.24 0.15 -0.007 0.074
and RX corner and gate are on same FET.
114R d PC to RX corner, for constant Weff. 0.24 0.1730 0.074
115 c PC corner to RX, when gate corner and RX are 0.08 0.0255 0.067
on same FET; does NOT maintain constant Leff.
115R d PC corner to RX, when gate corner and RX are 0.24 0.1855 0.067
on same FET; for constant Leff.
119 c (PC vertex within RX) or (RX vertex within PC). 0.20 - -
120a c (PC gate vertices over RX) or (RX gate vertices - - -

over PC) are only allowed at 45.
120b c Distance between two inside corners of bent 0.08 - -

gate which bends twice in the same direction
(length of 45 gate segment).
120c c Minimum PC notch over RX. 0.33 - -
121 c PC may only straddle RX at 90 degrees. - - -
123a c 10 Only inside 45 degree RX vertices are allowed - - -

under (PC not over GRLOGIC).
123b c 10 Distance between 2 inside corners of ((RX 0.08 - -

under PC) not over GRLOGIC).


l Min. Dim.
a
s
s
125 c 11 PC over RX must divide the RX into two or more - - -

diffusions.
130a b For PC intersecting RX, maximum ratio of (the 100 - -

total PC area) / (the total PC area over RX).
130b b PC(not intersecting any RX) to RX. 0.08 - -
130c b For PC intersecting RX, maximum ratio of [ 210 - -

perimeter (PC not over RX) ] / [ area (PC over
RX) ] ; where ( [perimeter] / [area] rule units in
terms of 1/m).
131 b 12 Gates connected to Mx must meet the following ratio: { ( Mx area ) / [ ( PC over
RX ) area + ( 5 * ( diode diffusion area ) ) ] } 150. Where Mx = M1, M2, M3, M4,
M5, M6.
Gates connected to Mz must meet the following ratio: { ( Mz area ) / [ ( PC over
RX ) area + ( 2 * ( diode diffusion area ) ) ] } 150. Where Mz = MQ, MG, LM, LY,
E1, MA, OL, LD, AM.
See Rule 131f and see additional Rule 131g for (Gates touching DG) with metal-
lization options listed in Table 13 on page 66. See Rule 131f_Mx and Rule
131f_Mz for (Gates not touching DG).
131a b 13 Gates (Thick Oxide) connected to Vx must meet the following ratio: { ( Vx area )
/ [ ( ( PC over RX ) over DG ) area + ( 7.5 * ( diode diffusion area ) ) ] } 0.50 ,
where Vx = [union (V1, V1BAR) or union (V2, V2BAR) or union(V3, V3BAR) or
union (V4, V4BAR) or union (V5, V5BAR)].
Gates (Thick Oxide) connected to ViaZ must meet the following ratio: { ( ViaZ
area ) / [ ( ( PC over RX ) over DG ) area + ( 3.0 * ( diode diffusion area ) ) ] }
0.50, where ViaZ = [union (VL, VLBAR) or union (VQ, VQBAR) or union (VG,
VGBAR) or union (FY, FYBAR) or union (FT, FTBAR) or union (F1, F1BAR) or
union (JT, JTBAR) or union (VV, VVBAR) or union (FQ, FQBAR)].
131b b 13 Gates (Thin Oxide) connected to Vx must meet the following ratio: { ( Vx area ) /
[ ( ( PC over RX ) NOT over DG ) area + ( 7.5 * ( diode diffusion area ) ) ] }
10.00, where Vx = [union (V1, V1BAR) or union (V2, V2BAR) or union(V3,
V3BAR) or union (V4, V4BAR) or union (V5, V5BAR)].
Gates (Thin Oxide) connected to ViaZZ must meet the following ratio: { ( ViaZZ
area ) / [ ( ( PC over RX ) NOT over DG ) area + ( 3.0* ( diode diffusion area ) ) ]
} 10.00, where ViaZZ = [union (VL, VLBAR) or union (VQ, VQBAR) or union
(VG, VGBAR) or union (FY, FYBAR) or union (FT, FTBAR) or union (F1, F1BAR)
or union (JT, JTBAR) or union (VV, VVBAR) or union (FQ, FQBAR)].
131c b Ratio of contact area to gate oxide area, calcu- 2.00 - -

lated as (union(CA, CABAR)) / (PC over RX) .


l Min. Dim.
a
s
s
131f b (Gates over DG) connected to (VL or VLBAR) must have a RX diode diffusion tie
down (see section 3.1.3 , Antenna Rules on page 113 for valid tiedown defini-
tion) at Mx or lower. Where Mx = M1, M2, M3, M4, M5, M6. See also Rule 131.
See additional Rule 131g for gates touching DG using only the metallization
options listed in Table 13 on page 66).
131f_Mx b 14 For metallization options identified in Table 12, MA last metal Back End Of Line
(BEOL) Metallization Options, on page 65 or Table 14, AM last metal Back End
Of Line (BEOL) Metallization Options, on page 67, (Gates not over DG) con-
nected to (VL or VLBAR) must have a RX diode diffusion tie down (see section
3.1.3 , Antenna Rules on page 113 for valid tiedown definition) at the last 1x
metal wiring level Mx or lower. Where Mx = M1, M2, M3, M4, M5, M6 (See also
Rule 131).
131f_Mz b For metallization options that include LM as the last metal, identified in Table 11,
LM last metal Back End Of Line (BEOL) Metallization Options, on page 64,
(Gates not over DG), that are connected to the via level below the LM wiring level
[(VQ or VQBAR) when MG is not present] or [(VG or VGBAR) when MG is
present] in a chip design, must have a RX diode diffusion tie-down (see section
3.1.3 , Antenna Rules on page 113 for valid tiedown definition) at the last 2x
metal wiring level Mz, where z = (MQ or MG) or lower Mx metal wiring level,
where Mx= M1, M2, M3, M4, M5, M6 or (MQ if MG is present). See also Rule
131.
For metallization options that include JT or JTBAR vias (LD as last metal), identi-
fied in Table 13, OL with LD last metal Back End Of Line (BEOL) Metallization
Options, on page 66, (Gates not over DG), that are connected to the (JT or
JTBAR) via level below the OL wiring level in a chip design, must have a RX
diode diffusion tie-down (see section 3.1.3 , Antenna Rules on page 113 for
valid tiedown definition) at the last 2x metal wiring level Mz, where z = (MQ or
MG) or lower Mx metal wiring level, where Mx= M1, M2, M3, M4, M5, M6 or (MQ
if MG is present). See also Rule 131.
131g b For metallization options in Table 13, OL with 4.32 - -

LD last metal Back End Of Line (BEOL) Metalli-
zation Options, on page 66 or Table 14, AM
last metal Back End Of Line (BEOL) Metalliza-
tion Options, on page 67: (Gates touching DG)
connected to (VL or VLBAR) must have a RX
diode diffusion tie down with area (m2) (see
section 3.1.3 , Antenna Rules on page 113 for
valid tiedown definition) at Mx or lower. Where
Mx = M1, M2, M3, M4, M5, M6 (See also Rule
131).


l Min. Dim.
a
s
s
131m1aR d (PC over RX) touching (QT or QY) is recommended to have a valid RX diode dif-
fusion tied-down (see section 3.1.3 , Antenna Rules on page 113 for valid
tiedown definition) at M1. This gate and mim plate interaction is not a net based
verified check. This rule verifies gates physically placed under MIMs in a chip
design.
131m1bR d ((PC over RX) not over GRLOGIC) is recommended to have a valid RX diode dif-
fusion tied-down (see section 3.1.3 , Antenna Rules on page 113 for valid
tiedown definition) at M1.
132 c (PC intersect RX) must have an area (m2). 230.00 - -
132R d (PC intersect RX) must have an area (m2). 45.00 - -
134 b Every (Nwell not over T3) containing a gate15 must satisfy either
there is a p+ diffusion in the Nwell that is connected to a n+ diode diffu-
sion outside of (Nwell or IND or IND_FILT or BB or BFMOAT or PI or JD).
there is a n+ Nwell contact connected to an n+ diode diffusion outside of
(Nwell or IND or IND_FILT or BB or BFMOAT or PI or JD) (this may be
satisfied by an RX image straddling the Nwell).
there is a n+ Nwell contact (in the Nwell) or p+ diffusion (in the Nwell)
connected to an valid substrate contact [(RX over BP) not over (Nwell or
PC or IND or IND_FILT or BB or BFMOAT or PI or JD)].
by the time M1 level is complete.
1. This measurement is a physical on-wafer dimension for both the Waf. Dim. column and the Tol. column.
2. In checking this local area requirement the checking box must be stepped in half box sized increments. When tiling steps over the chip
or cell boundary, move the tile back in bounds to satisfy this requirement. For tiles containing corner chamfers, corner density is
calculated based on the least enclosing rectangular shape. If chip will be filled by IBM Product Engineering as part of the release
process, designers are expected to meet this rule, including areas that will be prevented from receiving IBM generated RXFILL (i.e.,
within RXEXCLUD or PCEXCLUD if RXFILL and PCFILL run together using Design Services) prior to design submission. For regions
of RXEXCLUD that are smaller than the checking box in at least one direction, the RX density must satisfy the minimum specification
for the checking box, taking into account that the region of RXEXCLUD will not get any additional RXFILL to increase the RX density.
IBM will place RXFILL within (LOGOBND intersect CHIPEDGE). For RXFILL aspects within LOGOBND that is part of the IBM KERF
(LOGOBND not touching CHIPEDGE), refer to the applicable RXFILL rule in Table 244, xxFILL Rules, on page 549. Lastly, as stated
in the rule description, this rule is not applicable for checking boxes that touch PROTECT, as the PROTECT shape is outside the
CHIPEDGE.
3. This rule is intended to be equivalent to the checking that is performed per Rule PD1a, after IBM design services is completed during
the typical IBM release process (see Table 246, Pattern Density Rules (Post Cheese and Fill), on page 562). Graphical
representation of the individual RXFILL shapes is not provided, rather a summary of the predicted local density results. This rule is
included to predictively estimate the resulting RX local pattern density, inclusive of IBM added RXFILL, that will occur in the final chip
design, after IBM design services is applied, to assist designers with layout so that the RX local density requirements that is necessary
for Front-End-Of-Line manufacturability can be achieved.

4. In the design kit, the actual Design Minimum value is coded at 21% in lieu of the specified 20% value in this table to account for any
potential tool-to-tool variation between the estimated density value and the actual density that results after the IBM design services
process is completed as part of the IBM release process. IBM strongly recommends designers adhere to the design kit checking of
this rule, even though it is slightly more restrictive than the actual rule, to avoid evidencing local density violations during the final
design release process, which could result in design submission delay. If errors are evidenced during layout, IBM recommends
spacing RXFILL inhibiting devices or design levels further apart, such as polysilicon resistors (P+, OP RR, OP, RP), or long dense PC
wires, PCFUSE devices or RXEXCLUD shapes. Additionally, IBM suggests limiting usage of design levels that intentionally reduce
auto-generated RXFILL density or also spacing these levels further apart, such as BONDPAD, IND, IND_FILT, or BFMOAT. Checking
boxes (tiles) that are completely within the (IND, IND_FILT, BONDPAD, BFMOAT) shapes will not be reported as fails given that these
checking boxes do not touch design levels which alter fill placement (RX, RXEXCLUD, PC, PCING, etc.). Checking boxes with actual
density between 20-21% will be identified as errors during DRC; IBM strongly recommends that designers modify these regions to
comply with the DRC criteria in order to avoid potential delays at the time of design submission.
5. The design kit uses the same design minimum value that is specified in this table for checking to this requirement. This check is not
required to include predictive RXFILL added during the IBM release process.
6. In checking this local area requirement the checking box must be stepped in half box sized increments. When tiling steps over the chip
or cell boundary, move the tile back in bounds to satisfy this requirement. For tiles containing corner chamfers, corner density is
calculated based on the least enclosing rectangular shape. If chip will be filled by IBM Product Engineering as part of the release
process, designers are expected to meet this rule in areas that will be prevented from receiving IBM generated PCFILL (i.e., within
PCEXCLUD or RXEXCLUD if RXFILL and PCFILL run together using Design Services) prior to design submission. For regions of
PCEXCLUD that are smaller than the checking box in at least one direction, the PC density must satisfy the minimum specification
for the checking box, taking into account that the region of PCEXCLUD will not get any additional PCFILL to increase the PC density.
Lastly, as stated in the rule description, this rule is not applicable for checking boxes that touch LOGOBND or PROTECT, as the
LOGOBND shape does not receive IBM auto-generated PCFILL and the PROTECT shape is outside the CHIPEDGE
7. This rule is intended to be equivalent to the checking that is performed per Rule PD2a, after IBM design services is completed during
the typical IBM release process (see Table 246, Pattern Density Rules (Post Cheese and Fill), on page 562). Graphical
representation of the individual PCFILL shapes is not provided, rather a summary of the predicted local density results. This rule is
included to predictively estimate the resulting PC local pattern density, inclusive of IBM added PCFILL, that will occur in the final chip
design, after IBM design services is applied, to assist designers with layout so that the PC local density requirements that is necessary
for Front-End-Of-Line manufacturability can be achieved.
8. The design kit uses the same design minimum value that is specified in this table for checking to this requirement. This check includes
predictive PCFILL added during the IBM release process.
9. Rule 114b and 114c are intended to protect against RX (space/notch) end shorting that travels perpendicular to the PC line direction. A
PC line traveling across a narrow RX notch (run perpendicular to the notch run - all or part way) should be subject to this rule. However,
(PC end that is coming into the RX notch) or (PC overlap past RX into the notch) are covered by other rules.
10. Rule 123a/b value is determined by Rule 120a/b. For additional information, contact your IBM technical representative.
11. Rule is waived for decoupling capacitors or varactors where (PC over RX) is covered by VAR. For additional information, see Rule
VAR29 in Table 83, Varactor Layout Rules on page 237.
12. For more information concerning these rules, including resistor pass through for gate tie-down, see section , Definitions on page 113.
Rules 130a and 131 and 131f, 131f_Mx, 131f_Mz, are intended to avoid gate oxide integrity degradation by polysilicon charging during
manufacturing. If PC is within 0.08 m (Rule 130b for PC of RX, PC may overlap RX and form a very large antenna. Therefore It is
highly recommended that ALL PC touching RX ({PC < Rule 130b from RX ) be connected to N+ or P+ junction prior to the MQ wiring
level. Circuits whose operation is critically dependent on threshold voltage control or matching should not have antennae without this
diode clamp. Note All gates are assumed to be analog gates and must be tied down to a diffusion before the MQ wiring level. Even if
gates are covered by GRLOGIC, or are logic gates, they are only assumed to be able to withstand the threshold voltage shift of the
metal antenna mentioned in Rule 131 if they are not in the same net as (Mx touching VL). However, gates tied to substrate contacts
do not need to meet the tiedown diffusion area requirements.
13. Rule does not apply to gates tied to substrate contacts.
14. For MPW designs, this rule applies to the individual chip containing this MA metallization option only. For additional information, contact
your IBM Technical Representative.
15. In GR 134, the term gate also includes the PCDCAP/MOS varactor. All NWs containing ((PC intersect RX) must satisfy the
requirements specified.

111b
0.20 w/ 111b
114b,c
RX
110 RX notch width

100
PC PC RX
113b 102 130b

1
110
120b
110a 111 PC
52
114 PC PC
112
120a 3
50 10
104a RX PC 119
104b RX
115
121
102
PC PC 120c
Figure 7. Isolation and Polysilicon Rules

3.1.1 Additional Isolation (RX) Rules
Table 22. Additional Isolation (RX) Layout Rules
Rule C Notes Description Des. Wafer Tol.
l Min.
a
s
s
CPRX4a c 1 RX within NS. 0.200 - -
RX5a a (RX touching RN) must be covered by NS.
RX19a a Distinct {RX,NS] within a common BB not allowed (See also rule NS15a).
RX22a b (RX touching BB) must touch {PD, RN}.
RX23a b (RX touching BB) must be covered by SCHKY.
RX24a1 a ((RX over BB) not touching RN) must touch PDHOLE (where PDHOLE is a PD
enclosed area).
RX25a1 a ((RX over BB) not touching PD) must be covered by RN.
1. This measurement is a physical on-wafer dimension.
3.1.2 T3 Isolation Well Layout Rules

Table 23. T3 Isolation Well Layout Rules
Rule C Notes Description Des. Waf. Tol.
l Min. Dim.
a
s
s
T3W01 a T3 minimum width. 3.20 3.20 0.300
T3W02 a T3 minimum space and notch. 5.00 5.00 0.300
T3W03 c T3 must be orthogonal. - - -
T3W04 a All T3 edges must be covered by NW. - - -
T3W04a b All outer IBLK edges must be coincident with T3 - - -
edges.
T3W05 b T3 overlap of NW. 2.00 - -
T3W06 b NW overlap past T3. 1.10 - -
T3W07a b RX to T3. 1.50 - -
T3W07b b (RX not over BP) to IBLK. 1.50 - -
T3W07c b (RX not over NW) touching IBLK prohibited. - - -
T3W07d b [(RX over BP) over NW] to IBLK. 1.50 - -
T3W07e c [(RX over BP) not over NW] to IBLK. 0.29 - -
T3W08 c (RX over BP) touching IBLK is prohibited. - - -


l Min. Dim.
a
s
s
T3W09 c (RX touching IBLK) must be within (T3 over NW). 0.38 - -
T3W09a c RX within {T3, IBLK}. 0.38 - -
T3W09b c RX within (NW touching T3 edges) [RX straddling 0.30 - -
(NW touching T3 edges)] is prohibited.
T3W10a b Each ((NW not over IBLK) within T3) must have at least one ({[(RX over T3) not
over IBLK] not over BP} not over PC) contact for each (within each) NW poly-
gon.
T3W10b c Each [(NW over T3) over IBLK] polygon must have at least one (RX over IBLK)
polygon.
T3W11 b NW to IBLK. 1.20 - -
T3W12 b (PC over RX) to T3. 1.50 - -
T3W13 b (NW touching T3) minimum space to {PI, 2.02
NWRES} with touching prohibited.
T3W14a c T3 to {BFMOAT, ZEROVT, JD, PI} with touching 3.12 - -
prohibited.
T3W14b2 c T3 to ESDIODE with touching prohibited. 2.02 - -
T3W14c c T3 to {LM_RFLINE, MA_RFLINE, IND, IND_FILT} 2.02 - -
with touching prohibited.
T3W15 b T3 to NW. 2.02 - -
T3W16 a T3 must touch at least one NW enclosed area. - - -
T3W17 a T3 must touch IBLK. - - -
T3W19 c IBLK must touch a minimum of 9 CAs - - -
(IBLK not touching CA is prohibited).
T3W20R d (NW over T3) maximum width (width being the 1000 - -
smaller of the two orthogonal dimension).
T3W21 a IBLK minimum width. 2.0 2.13 0.122
T3W22 a IBLK minimum space and notch. 2.0 1.87 0.122
T3W23 c IBLK must be orthogonal. - - -
T3W24a c IBLK must be within T3. 0.0 - -
T3W24b b IBLK must be within (NW over T3). 0.0 - -
T3W25 c CA within (RX touching IBLK). 0.14 - -
T3W27b b IBLK to (PC over RX) with touching prohibited. 1.50 - -
T3W28a c IBLK touching (PC touching OP) is prohibited. - - -

l Min. Dim.
a
s
s
T3W28b b IBLK touching {LW, XW, PV, NV, JN, JP, DG, XE, - - -
XF, BP, PD, RR, RP, OP} is prohibited.
T3W28c b IBLK touching {CELLSNR, DI, EFUSE, - - -
GRLOGIC, GUARDRNG, LOGOBND, NWASP,
SBLK, VAR} is prohibited.
T3W30 a BB space to T3 (with touching prohibited). 2.86 - -
T3W131f b ((Gates over DG) over T3) connected to (VL or VLBAR) must be tied to a [((RX
not over PC) over T3) not touching {IBLK, (NW which is not tied down per Rule
T3W134)} in its own T3 isolation well at Mx or lower. Where Mx = M1, M2, M3,
M4, M5, M6. See also Rule 131. For OL with LD metallization options, see addi-
tional Rule T3W131g for ((Gates over T3) touching DG).
Note: IND or IND_FILT or BB or BFMOAT or (PI which is not tied down (see rule
TW134)) or JD) are not valid tie-downs, as these levels are prohibited in the T3
isolation well.
Note: See additional Rule T3W131g for gates touching DG using only the OL
metallization option.
T3W131f_Mx b For metallization options that include MA or AM as the last metal, ((Gates not
over DG) over T3) connected to (VL or VLBAR) must have a [((RX not over PC)
over T3) not touching {IBLK, (NW which is not tied down per T3W134)} diode
diffusion tie-down in its own T3 isolation well at the last 1x metal wiring level Mx
or lower. Where Mx = M1, M2, M3, M4, M5, M6 (See also Rule 131).
Note: IND or IND_FILT or BB or BFMOAT or (PI which is not tied down (see rule
TW134)) or JD) are not valid tie-downs, as these levels are prohibited in the T3
isolation well.
T3W131f_Mz b For metallization options that include LM as the last metal, ((Gates not over DG)
over T3), that are connected to the via level below the LM wiring level [(VQ or
VQBAR) when MG is not present] or [(VG or VGBAR) when MG is present] in a
chip design, must have a [((RX not over PC) over T3) not touching {IBLK, (NW
which is not tied down per T3W134)} diode diffusion tie-down in its own T3 iso-
lation well at the last 2x metal wiring level Mz, where z = (MQ or MG) or lower
Mx metal wiring level, where Mx= M1, M2, M3, M4, M5, M6 or (MQ if MG is
present). See also Rule 131.
For metallization options that include JT or JTBAR vias (LD as last metal),
((Gates not over DG) over T3), that are connected to the (JT or JTBAR) via level
below the OL wiring level in a chip design, must have a [((RX not over PC) over
T3) not touching {IBLK, (NW which is not tied down per T3W134)} diode diffu-
sion tie-down in its own T3 isolation well at the last 2x metal wiring level Mz,
where z = (MQ or MG) or lower Mx metal wiring level, where Mx= M1, M2, M3,
M4, M5, M6 or (MQ if MG is present). See also Rule 131.


l Min. Dim.
a
s
s
T3W131g b For (OL with LD) or AM metallization options, 4.32 - -
((Gates over T3) touching DG) connected to (VL
or VLBAR) must have a [((RX not over PC) over
T3) not touching {IBLK, (NW which is not tied
down per (Rule 134 or T3W134))} in its own T3
isolation well at the last 1x Mx metal level where
Mx= M1, M2, M3, M4, M5, M6) with area (m2).
See also Rule 131.
T3W131m1cR d Every ((gate not over GRLOGIC) over a T3 isolated n-well, defined as [((PC
over RX) not over GRLOGIC) over (NW over T3)] is recommended to be tied
down to its own isolated nwell [((RX over T3) over NW) not over {IBLK, PC}] in
its own T3 isolation Nwell at M1.
T3W134 b 1 Every (NW over T3) containing a gate , by the time M1 is complete, must satisfy
either:
there is a T3 isolated p+ diffusion in the T3 isolated Nwell (((RX not over
PC) over BP) over T3) that is connected to a n+ diode diffusion inside
the T3 isolated pwell [((RX not over PC) not over BP) over (T3 not over
NW)] touching the T3 isolated NWell containing the gate.
there is a T3 isolated n+ Nwell contact [((((RX not over PC) not over BP)
over (NW not over IBLK) over T3] connected to a T3 isolated n+ diode
diffusion in the isolated pwell [((RX not over PC) not over BP) over (T3
not over NW)] touching the T3 isolated Nwell containing the gate.
For the T3 isolated n+ Nwell contact connected to a T3 isolated n+
diode diffusion condition listed above, this may be satisfied by an (RX
not over IBLK) polygon straddling both an abutting (coincident or com-
mon) T3 isolated pwell and T3 isolated Nwell edge, where the NWell
edge is touching the T3 isolated Nwell containing the gate.
there is a T3 isolated n+ Nwell contact ((((RX not over PC) not over BP)
over NW) not over IBLK) over T3] or a T3 isolated p+ diffusion (((RX not
over PC) over BP) over T3) connected to an valid T3 isolation Pwell
contact [(((RX not over PC) over BP) over T3) not over (NW or IBLK)].
Any ((RX over T3) over (IND or IND_FILT or BB or BFMOAT or PI or JD
or ZEROVT)) are not valid (NW over T3) tie-downs since T3 touching
these levels is prohibited by Rule T3W14a or T3W14c.
For all conditions above, an IBLK polygon edge breaks the net for a
path to a valid (NW over T3) tie-down at all levels used in the net gener-
ation (RX, PC, or any BEOL metals in the stack).
T3W135a b All T3 isolated well pwells (T3 not NW) must touch [[((RX over CA) over BP)
over T3).

l Min. Dim.
a
s
s
T3W268 b 2 ((RX P+ Junction over T3) to (RX N-well Contact 38.12 - -
over T3) over NW for no latchup.
T3W268b b 3,4 (distance of outer farthest RX edge of (N+ Junc- 38.12 - -
tion over T3) to T3 P-well Contact) outside of NW
for no latchup.
T3WDG268 b 5 ((RX P+ Junction touching DG) over T3) to (RX 15.00 - -
N-well Contact over T3) for no latchup.
T3WDG268b b 6 ((RX N+ Junction touching DG) over T3) to T3 14.00 - -
P-well Contact) for no latchup.
T3W594a a 7,8,9, For nets connected to NW contact touching T3 by 0.20
10 physical layout (i.e. not defined as a net check),
where the NW net is not connected to a T3 Isola-
tion PWell Contact defined by (((RX over BP) over
T3) not over (NW or RN or JD or PI)), the ratio of [
(20*Mx area) + (Isolated p+ junction area ((((RX
over BP) over NW) not over PC) over (T3 not over
IBLK)) ] / (union[NW,RN,PI,JD] area) where
x=1,2,3,4,5,6.
(This check is for isolated Nwells or the isolation
well perimeter Nwells not connected to a T3 isola-
tion well contact, and p+ junctions in the T3 isola-
tion well regions are used to meet the ratio)
T3W594b a 7,8,9, For nets connected to NW contact touching T3 0.20
10 electrical net (where NW touching IBLK enables
the NW to T3 electrical connection to be made),
where the NW net is not connected to a substrate
contact defined by ((RX over BP) not over (NW or
RN or BB or JD or PI or T3)), the ratio of [ (20*Mx
area) + (Non-isolated p+ junction area (((RX over
BP) over NW) not over PC)) ] / (union[NW, RN, PI,
JD, T3] area) where x=1,2,3,4,5,6.
(This check is for the isolation well perimeter
Nwells not connected to a substrate contact, and
p+ junctions in the non-isolated substrate regions
are used to meet the ratio.
This check assumes the T3 isolation well NW
contact (i.e. the contact to the T3 isolation) does
not contact the T3 isolated Pwell).


l Min. Dim.
a
s
s
T3W595 a 7,8,9, For nets connected to ((RX over BP) over T3) (T3 0.20 - -
11 Isolated Well Pwell contact), the ratio of [ (20*Mx
area) + (T3 Isolation Well N+ junction area ((RX
not over (BP or JD or NW or RN or PC)) over T3)
area ] / (union [(PI not over NW), (T3 not over
IBLK)] area) where x=1,2,3,4,5,6.
(This check is for the T3 isolation Pwell contact,
and the T3 isolation well N+ junction regions are
used to meet the ratio).
T3WQCAP24 b (QY touching (LY inside T3)) top or middle MIM capacitor plate must be tied
down to a (((RX not over {PC,OP}) over T3) not over (NW touching IBLK)) at E1.
All MIM plates {(LY touching QY), QY, HY} of a MIM inside T3 are tied down to
the same ((T3 not IBLK) not over NW) isolated triple well polygon. If a (LY
touching QY) bottom plate is straddling a T3 polygon edge then the verification
for the location of the tiedown for the QY plate within the same LY is required to
be only this criteria: (RX not over {PC, OP, T3}) diffusion.
T3WQCAP24a b (HY touching (LY inside T3)) top MIM capacitor plate must be tied down to a
(((RX not over {PC,OP}) over T3) not over (NW touching IBLK)) at E1. All MIM
plates {(LY touching QY), QY, HY} of a MIM inside T3 are tied down to the same
((T3 not IBLK) not over NW) isolated triple well polygon. If a (LY touching HY)
bottom plate is straddling a T3 polygon edge then the verification for the loca-
tion of the tiedown for the HY plate within the same LY is required to be only this
criteria: (RX not over {PC, OP, T3}) diffusion.
T3WQCAP24b b ((LY touching QY) inside T3)) top MIM capacitor plate must be tied down to a
(((RX not over {PC,OP}) over T3) not over (NW touching IBLK)) at E1. All MIM
plates {(LY touching QY), QY, HY} of a MIM inside T3 are tied down to the same
((T3 not IBLK) not over NW) isolated triple well polygon. If a (LY touching QY)
bottom plate is straddling a T3 polygon edge then the verification for the loca-
tion of the tiedown for the (LY touching QY) plate is required to be only this crite-
ria: (RX not over {PC, OP, T3}) diffusion.
T3WQT8e b 12,10 All plates ({KT, HT, QT} inside T3) of a MIM capacitor must be tied down to a
(((RX not over {PC,OP}) over T3) not over (NW touching IBLK)) at OL (per rule
QT8ae). All plates {KT, HT, QT} of a MIM inside T3 are tied down to the same
((T3 not IBLK) not over NW) isolated triple well polygon. If a QT bottom plate is
straddling a T3 polygon edge then the verification for the location of the tiedown
for all {QT, HT, KT} plates in the same QT are required to be only this criteria:
(RX not over {PC, OP, T3}) diffusion.
T3W999a a T3 must be within CHIPEDGE. 0.00 - -
T3WPT01h a T3 over PROTECT is prohibited.
T3WPN100 c T3 touching LOGOBND is prohibited.

l Min. Dim.
a
s
s
T3WLVS1 b [NW touching (IBLK over T3)] is at the same electrical potential as the T3.
(Note: IBLK cuts a hole in BT mask level, similar to ESDIODE polygon).
T3WLVS2 b [NW touching (ESDIODE over T3)] is at the same electrical potential as the T3.
(Note: ESDIODE cuts a hole in BT mask level, similar to IBLK polygon).
T3WLVS3 b All (T3 not NW) enclosed by a common ((NW over IBLK) over T3) area is at the
same electrical potential (All Pwells in a common isolated T3 well are at the
same electrical potential).
T3WLVS4 c (RX over PI) is not a valid well tie-down for (RX over T3).
1. In GR T3W134, the term gate also includes the PCDCAP/MOS varactor. All (NW over T3) containing ((PC intersect RX) must
satisfy the requirements specified.
2. P+ Junction over T3 = ((RX over BP) over NW) over (T3 not IBLK); NWell contact over T3= ((RX not over BP) over NW) over T3.
3. N+ Junction over T3 = (((RX not over BP) not touching SCHKY) not over NW) over (T3 not IBLK); T3 P-well contact= ((RX over BP) not
over NW) over T3
4. In case of large N+ diffusions, one requires to measure from the farthest N+ RX edge to the RX substrate contact.
5. P+ Junction touching DG over T3 = (((RX over DG) over BP) over NW) over (T3 not IBLK); NWell contact over T3= ((RX not over BP)
over NW) over T3.
6. N+ Junction touching DG over T3 = (((RX over DG) not over BP) not over NW) over (T3 not IBLK) ; T3 PWell contact= ((RX over BP)
not over NW) over T3
7. Only the current metal level is included in the metal area measurement.
8. Only (RX p+ junction not over PC) connected to (NW contact of the NW level in which the p+ junction resides) is included in the areas
measurement; any p+ junction note connected to the NW level in which it resides is ignored in the area measurement.
9. (NW not T3) and T3 are conductors, so two different NW contacts in the same NW level or two different T3 contacts in the same T3 level
are assumed to be shorted.
10. The connectivity net definition for this rule allows pass through for resistors which have an (OP intersect {RX or PC} aspect ratio of less
than 100 to 1. This limits the resistance of pass through resistors.
11. Only (RX n+ junctions not over PC, not over NW) connected to (T3 isolated well contact of the isolated pwell in which the n+ junction
resides) is included in the area measurement; any n+ junction not connected to the isolated pwell in which it resides is ignored in the
area measurement.
12. This rule requires all MIMs to be wired up to OL before being connected to other circuit nodes and then also requires the nodes
containing the MIM to be connected to a (RX not over {PC, OP, T3}) or to a ((RX over T3) not over NW). This ensures that all MIMs
electrically float until AFTER all RIE processing above QT as well as HT is completed and then are tied to RX.

T3W135a
T3W16
T3W17
T3W07b, c T3W06
[(RX not T3W07e
over BP) (RX RX
T3W07b over T3] over T3W07b
T3W07c BP) T3W07c
(RX N+
T3W04a Junction) T3W05
RX
IBLK [(RX not NW (touching T3)
over BP) T3W11
T3W10a over T3] (PC
T3W20 over RX P+ T3W10a
T3 Well T3 (RX NW
RX) Junction
Contact)
(not NW, NW
T3W07b T3W27b T3W07d
not IBLK
polygon) RX NW
CA
T3W07a T3W12
T3W27b T3
T3W04
T3W02 RX (or RX NW (PC over
Contact) or (RX RX)
T3 P+ Junction) [Gate]
T3 over
IBLK Well
Isolation
Contact
(PC over (RX over BP)
RX) T3W08 T3W19
T3W27b CA T3W10b
T3W25
T3W04 (RX not over (RX over
NW) T3W07c NW, over
T3 over)
IBLK) T3W09
T3W22 T3W09a
T3
T3W04a T3W09
T3W01 RX T3W09a RX over
T3W07b, T3W07c T3W09b BP
IBLK (Substrate
T3W21 Contact)
T3W24a
T3W24b T3W08
T3W07a T3W07a T3W07d
T3W07a T3W07d T3W07b
T3W07b T3W08
RX
(RX not (RX over BP)
over BP) P+ Junction T3W09b
T3W09b
Figure 8. T3 Isolated Well (Multiple T3 shapes)

T3W135a T3W07a
T3W07e
T3W16 T3W08 RX
T3W17 (RX over BP) or T3W09b
RX Substrate
Contact T3W07b
RX or N+
Junction
IBLK (over T3) RX N+
T3W07b NW
T3W24a Contact
T3W24b T3W07c RX
T3W07b
T3W07c T3W12
T3W27b
T3 Well T3W07b, c (PC over
(not NW, RX)
not IBLK (PC over
T3W09 T3 over
polygon) Substrate RX) T3W09a IBLK Well
Contact T3W27b T3W09b Isolation
T3W08 Contact
RX over IBLK CA
T3W19
T3W09 T3W10b
P+
Junction T3W09a T3W25
T3W04 (RX over BP)
T3W08 T3W08
(RX over
T3 BP)
(RX not over T3W07d

NW) T3W07c T3W08
NW
(under T3W10a
RX
T3) NW(touching T3)
T3W07b,c
T3W20 RX N+ P+
T3W22 NW RX P+ Junction
T3W04a Contact Junction
(over T3) T3W07d
w/Gate
T3W08
T3W11
T3W05
T3W06 T3W21
T3W01
NW
Figure 9. T3 Isolated Well (Single T3 shape)

3.1.3 Antenna Rules
Definitions
A floating gate device is any device where the PC (poly) shape
- touches RX (diffusion) and
- is NOT electrically connected to RX
The PC over RX area is defined as the gate oxide area.
For each PC shape intersecting RX, the poly antenna ratio is defined as the ratio of the total PC area to
the gate oxide area.
The metal antenna ratio is defined as the ratio of the metal area to the gate oxide area to which it is con-
nected at any level at which the gate has not yet been electrically connected to RX. Example: For gate
not electrically connected to RX at M2 (nor at M1), the M1 and M2 antenna ratios would be the M1 and
M2 area, respectively, divided by the gate oxide area of the gate to which the M1 and M2 are connected.
The antenna ratio defined is for individual level, not cumulative.
A valid tiedown RX diffusion is defined as ((RX not over PC) not touching (((NW not touching PI) which is
not tied down (see rule 134)) or IND or IND_FILT or BB or BFMOAT or (PI which is not tied down (see
rule TW134)) or JD). The following is a list of the valid tiedown devices: NFET source/drain (including
thick oxide and Zero Vt versions), N+ Diffused resistor, N+ junction in the substrate, Thin or Thick Triple
Well NFET source/drain in a tied down well (see rule TW134), PFET source/drain (including thick oxide
versions), P+ junction in a tied down NWell and substrate contact. Note: PFET pass-through not allowed
for tie-down net connectivity ((PC intersect RX) forming a gate breaks the net connectivity).
(RX over T3) is not a valid tie-down for any gate not touching T3.
(RX over IBLK) is not a valid tie-down for any gates
(RX over PI) is not a valid tie-down for any gates over T3.
For diffused resistors with an aspect ratio (OP intersect RX) greater than or equal to 100:1, only the con-
tact area (RX not over OP) which is part of the net is a valid tiedown.
The connectivity net definition allows pass through for resistors which have an (OP intersect (RX or PC))
aspect ratio of less than 100:1. This limits the resistance of pass through resistors.
Rules
These rules are intended to avoid gate oxide integrity degradation by polysilicon charging. See Rules
130a, 130c, 131, 131a, 131b, 131c, 131f, 131f_Mx, 131f_Mz, and 131g.
Rule 130a - Poly antenna. Since prior to first metal level, each PC shape that intersects RX results in a
floating gate device, poly antennae larger than 100:1 are NOT ALLOWED.
Rule 130c - Poly perimeter intensive antenna. This rules restricts the total perimeter of poly antennas as
a function of gate oxide area.
Rule 131 - Metal antenna. Floating gate devices with metal antennae larger than 150:1 at any level are
NOT ALLOWED (each metal layer may have an antenna ratio of 150:1). Additional RX tie-down diode cri-
teria may also be required.

- For the MA last metallization options (Table 12 on page 65):
Thick Oxide gates in the same net as a VL or VLBAR via must meet Rules 131 and 131f.
Thin Oxide gates in the same net as a VL or VLBAR via must meet Rule 131 and 131f_Mx.
- For the OL with LD BEOL metallization options (Table 13 on page 66):
Thick Oxide Gates in the same net as a VL or VLBAR via must meet Rules 131, 131f and addi-
tional Rule 131g.
Thin oxide gates in the same net as JT, JTBAR vias must meet Rules 131 and 131f_Mz.
- For the LM BEOL metallization options (Table 11 on page 64):
Thick Oxide Gates in the same net as a VL or VLBAR via must meet Rules 131 and 131f.
Thin oxide gates in the same net as the via below LM must meet Rules 131f and 131f_Mz.
Rules 131a, 131b and 131c - Contact and vias antennae. For active gates that are tied down by a diode,
these rules need to be followed to insure that the diode area is big enough to be able to clamp the voltage
low enough to avoid gate oxide damage.
Rule 134 - Nwell antenna rule. It is required that every NW is tied down by a n+/PW diode. No area spec-
ification exists. It is intended to prevent the Nwell potential from rising too high relative to the P-substrate
by providing the reverse biased leakage path from the n+/PW diode. This rules applies to both thin and
thick oxide devices. This rule also applies to n+ in Nwell devices (varactors and decoupling capacitors),
see section 4.19 , NCAP and DGNCAP Models on page 389.
Recommendations
It is recommended that all PC touching RX be connected to RX (N+ or P+ diffusion) by M1.
Circuits whose operation is critically dependent on threshold voltage control or matching should not have
antennae without a diode clamp. The diode area need to follow Rule 131 through Rule 134.

Layout Rules N-well, Contact, Junction Layout Rules
3.2 N-well, Contact, Junction Layout Rules

Table 24. N-well, Contact, Junction Layout Rules

l Min. Dim.
a
s
s
200 a CA width; CA length. 0.16 0.1750 0.025
201 b CA must be rectangular and not at 45. - - -
203 a 1 CA to CA space. 0.24 0.2250 0.045
203b a 1 CA to CA space, for common run lengths 0m, 0.20 0.2050 0.045
corner to corner spacing.
204 b CA within RX. 0.06 0.0375 0.089
204R d 2 CA within RX. 0.14 0.1175 0.089
207 b 3 CA (over RX) to adjacent PC; for PC width 0.10 0.0945 0.067
<0.13m.
207b b CA (over RX) to adjacent PC, when (0.13 PC 0.12 - -

width < 0.18m).
207c b CA (over RX) to adjacent PC, when PC width is 0.14 - -

0.18m.
207R d CA (over RX) to adjacent PC - Recommended. 0.14 - -
208 c (CA over PC) to adjacent RX. 0.11 0.1325 0.089

209 b 3 CA within PC. 0.02 0.0095 0.064
209R d CA within PC - Recommended for no CA etch into 0.09 0.0795 0.064

PC spacer. (CA landed on PC).
211 c CA over (PC intersect RX) not allowed. - - -
212 c CA must be within RX or PC (must satisfy rule - - -

204 or 209).
214 a Maximum percent (%) union (CA, CABAR) per- 16 - -

mitted over a 25m x 25m localized area
stepped in 12.5m increments.
214R d Maximum percent (%) union (CA, CABAR) per- 10 - -

mitted over a 25m x 25m localized area
stepped in 12.5m increments.

Layout Rules N-well, Contact, Junction Layout Rules IBM

l Min. Dim.
a
s
s
228 c CABAR not over GUARDRNG is prohibited. Note: - - -
GUARDRNG is the dummy design and utility level
that identifies the Chip Guard Ring.
250 a 4,5 NW width. 0.68 0.68 0.208
250a a NW shapes must be orthogonal. - - -
252a b 4,6 NW to NW space. 0.92 0.92 0.208
252aR d 4,6 NW to NW space, Recommended. 1.20 1.20 0.208
252b a 4,7 NW to NW space - for same potential wells; this 0.70 0.000 0.208
usage is restricted to unbended common run
lengths 0.68m (Rule 250).
252c b RX shapes are not allowed between NW shapes - - -

that are spaced less than 0.92 m apart.
252dR d NW-NW space for area >300 m2 and NW width 1.48 - -

>6.0m.
260 b 8,9 RX P+ Junction within NW. 0.30 0.3825 0.099
260aR d 9 RX P+ Junction within NW for [NW width 0.52 - -

18.0m and ((not NW) width 18.0m)].
261 b RX N-well Contact overlap of NW, when overlap 0.33 0.5275 0.130
area is <0.13m2.
261f b RX N-well Contact overlap of NW, when overlap 0.20 0.3975 0.130
area is 0.13m2.
262 b RX N-well Contact overlap area with NW (m2). 0.076 - -
262b b RX (within RN) intersect BB (area in m2). 0.150
265 b 9 RX N+ Junction to adjacent NW (where the RX 0.30 0.2625 0.099

does not intersect the NW).
265b b RX N+ Junction to adjacent NS. 2.52
CP265b1 b RX N+ Junction to BB. 0.42 - -
265aR d 9 RX N+ Junction to adjacent NW for (NW width 0.52 - -

18.0m).


l Min. Dim.
a
s
s
266 b RX Substrate Contact to NW - High resistance 0.06 0.0225 0.099

contact.
266R d RX Substrate Contact to NW - Recommended for 0.20 0.1625 0.099

low resistance contact.
266b b (RX touching BP) Sub Contact to NS (touching 2.50 - -

not allowed).
268a b 10 ((RX P+ Junction not over T3) to (RX N-well Con- 38.12 - -
tact not over T3) over NW for no latchup.
268b1 b 11,12 (distance of outer farthest RX edge of (N+ Junc- 38.12 - -

tion not over T3) to RX Substrate Contact) outside
of NW for no latchup.
269 c (PC over RX where RX straddles NW) to NW. 0.50 - -
269a c RX N+ junction overlap past (NW not over 0.50 - -

GRLOGIC) (for valid NW tiedown N+ junction).
NWASP1 b 13 NW shapes within NWASP (Adjacent NW(at the 0.00 - -

same potential) must be within the same NWASP
net to use Rule 252b).
1. The wafer value for this rule is measured at the top of CA.
2. IBM recommends following Rule 204R to prevent border leakage.
3. CA resistance tolerance depends on PC to CA distance and CA within PC , see Table 168, Contact Resistance, on page 416 and
Table 169, Via Resistance, on page 416.
4. These rules also check shapes internally generated in the DRC deck as defined in Table 8, Shape Manipulation Prior to Mask Write,
on page 59.
5. It is strongly recommended that shapes on levels involving pre-mask data preparation (DPREP) difference functions be placed at the
same cell nesting hierarchy in the design data. Examples of these levels are NW and DG; see Shape Manipulation Prior to Mask
Write on page 59.
6. The 2 NWells will be merged for NW space 0.9um.
7. The dummy level NWASP must be placed over (and fully covering) adjacent NW shapes at the same potential; place these shapes at
the lowest level of nesting possible for design rule checking. N-well regions using this rule may be electrically shorted together; hence,
RX shapes are not allowed between NW shapes spaced less than the value of Rule 252a apart.
8. P+ Junction refers to the RX diffusion over BP and over NW.
9. The N+ and P+ junctions in these rules must include the gate area (RX) under the PC for these rules.
10. P+ Junction not over T3 = ((RX over BP) over NW) not over T3; NWell contact not over T3= ((RX not over BP) over NW) not over T3.
For blocking shape information see also Figure 11, on page 118
11. N+ Junction not over T3 = (((RX not over BP) not touching SCHKY) not over NW) not over T3;Substrate contact= ((RX over BP) not
over NW) not over T3

12. In case of large N+ diffusions, one requires to measure from the farthest N+ RX edge to the RX substrate contact.
13. See also Rule 252b and the note requirement specified.
204
CA
209 207
PC
CA CA 208
203
203b
CA
CA
200 RX
Figure 10. CA Rules
Valid Blocking Layers: NW

BFMOAT NON-valid Checking Path
JD
IBLK
BB
RX RX
BP
Valid Checking Path (avoids blocking shapes)
Figure 11. Blocking shapes (NW,JD,BB,BFMOAT,IBLK) for 268 series of rules (268a, 268b1 {shown above},
DG268a1DG268a1, DG268b1, T3W268, T3W268b, T3WDG268, T3WDG268b.

GR 268b1
STI n+ p+
STI STI
P-well
Figure 12. Rule to Avoid Latch-up

NW NW
BP 252
261
RX (N+ P+
N-Well Junction
Junction) Contact
250
RX RX
269 353
262 260
PC
266 265
350
355 N+
Substrate Junction
Contact
352 RX
RX
BP BP
BP 354a
RX
NW sized by +0.30
354b 354b
NW
356b
Rules 354b and
356b apply in this RX
NW sized by -0.30
shaded area
356b
RX
356a BP
BP 354a
RX
Figure 13. N-well, Contact, Junction Rules

Layout Rules ZVT NFET Layout Rules
3.3 ZVT NFET Layout Rules

Table 25. ZVT NFET Layout Rules
Rule C Notes Description Des

l Min.
a
s
s
1a b PC width over (RX over ZEROVT) for 0-Vt NFET device Leff. 0.42
1b b PC width over (RX over ZEROVT over DG) for 0-Vt NFET device Leff - 0.56
Thick Gate.
10a b (RX under PC) touching ZEROVT min gate width (for Zero-VT NFET 2.34
device Weff).
122a c No bent gates (PC over RX) allowed over ZEROVT. -
280 b ZEROVT width. 1.74
280a c ZEROVT shapes must be orthogonal. -
282 b ZEROVT to ZEROVT space (BF gen also). 1.88
284 b ZEROVT must be within RX. 0.30
286 b BP touching ZEROVT not allowed. -
288 b ZEROVT to adjacent RX. 1.30
289 b ZEROVT to adjacent NW (for P-well placement and DE generation). 0.92
ZT1 b ZEROVT must overlap past gate on two opposite sides. 0.66
ZT2 b ZEROVT to adjacent DG space (for BH and DE generations). 0.92
ZT3 c ZEROVT to adjacent (OP intersect PC) - (for BH generation). 1.04

Layout Rules Low Power Vt FET and LVT FET Layout Rules IBM
NFET ZVT NFET PFET
RX
288 284
ZT1 10a
RX 1a
289
PC
ZEROVT NW
Figure 14. ZVT NFET Rules
3.4 Low Power Vt FET and LVT FET Layout Rules

Low Power Vt and Low-Vt devices can be used in the same build. Note that 4 well masks are required for this
option (so include the regular well masks NW and BF)
3.4.1 Low Power Vt (NV) and LVT (XW) NFET Rules

These devices are the standard NFET-like device with a different P-well implantation and hence a different
Vt. These devices receive the standard N+ source/drain implant and NFET halo implants.
Table 26. XW Layout Rules

l Min.
a
s
s
290 b 1 XW width. 0.46
291 c XW shapes must be orthogonal. -

Layout Rules Low Power Vt FET and LVT FET Layout Rules
Table 26. XW Layout Rules

l Min.
a
s
s
292 a XW to XW space. 0.40
294a b [(PC intersect RX) not within NW] to XW. 0.22
294aR d [(PC intersect RX) not within NW] to XW. 0.34
294b b [(PC intersect RX) not within NW] within XW. 0.22
294bR d [(PC intersect RX) not within NW] within XW. 0.34
XW10 a XW overlap past NW (for XW generation). 0.40
XW11 a XW to ZEROVT space (for XW generation). 0.56
XW12 a XW to BFMOAT space (for XW generation). 0.56
XW20 a (RX over NV) not allowed over XW - for nFET. -

1. It is strongly recommended that shapes on levels involving pre-mask data preparation (DPREP) difference functions be placed at
the same cell nesting hierarchy in the design data. Examples of these levels are NW and DG; Table 8, Shape Manipulation Prior
to Mask Write on page 59
Table 27. NV Layout Rules

l Min.
a
s
s
NV00 b 1 NV width. 0.46
NV00a a 2 NR is not a valid design level. Use NV. -
NV01 c NV shapes must be orthogonal. -
NV02 a NV to NV space. 0.40
NV04a b [(PC intersect RX) not within NW] to NV. 0.22
NV04aR d [(PC intersect RX) not within NW] to NV. 0.34
NV04b b (PC intersect RX) not within NW] within NV. 0.22
NV04bR d [(PC intersect RX) not within NW] within NV. 0.34
NV09b a NV overlap past NW (for NV generation). 0.40

the same cell nesting hierarchy in the design data. Examples of these levels are NW and DG; Table 8, Shape Manipulation Prior
to Mask Write on page 59
2. NR is an obsolete Design and Mask Level in the CMRF8SF technology. The LP NFET requires use of design and mask level NV. Design
and Mask Level NR is not used for the CMRF8SF Technology. See Table 2 on page 27 for NV and Table 3, Design Service and Data
Preparation Levels (Restricted), on page 37 for NR. For additional information on NV, see Table 8, Shape Manipulation Prior to Mask
Write on page 59.
3.4.2 Low Power Vt (PV) and LVT (LW) PFET Rules

These devices are the standard PFET-like device with a different N-well implantation and hence a different
Vt. These devices receive the standard P+ source/drain implant and PFET halo implants
Table 28. LW Layout Rules

l Min.
a
s
s
LW00 a LW width 0.46
LW01 c LW shapes must be orthogonal. -
LW02 a LW to LW space 0.40
LW04a b [(PC intersect RX) within NW] to LW 0.22
LW04aR d [(PC intersect RX) within NW] to LW. 0.34
LW04b b [(PC intersect RX) within NW] within LW. 0.22
LW04bR d [(PC intersect RX) within NW] within LW. 0.34
LW10 a LW overlap of NW (for LW derivation). 0.40

LW20 a (RX over PV) not allowed over LW - for pFET. -
Table 29. PV Layout Rules

l Min.
a
s
s
PV00 a PV width. 0.46
PV00a a 1 PR is not a valid design level. Use PV. -
PV01 c PV shapes must be orthogonal. -
PV02 a PV to PV space. 0.40

Layout Rules Low Power Vt FET and LVT FET Layout Rules
Table 29. PV Layout Rules

l Min.
a
s
s
PV04a b [(PC intersect RX) within NW] to PV. 0.22
PV04aR d [(PC intersect RX) within NW] to PV. 0.34
PV04b b [(PC intersect RX) within NW] within PV. 0.22
PV04bR d [(PC intersect RX) within NW] within PV. 0.34
PV09 a PV overlap of NW (for PV derivation) . 0.40

1. PR is an obsolete Design and Mask Level in the CMRF8SF technology. The LP PFET requires use of design and mask level PV.
Design and Mask Level PR is used for the CMS8SFG High Vt NFET, which is not a supported device in the CMRF8SF
technology. See Table 2 on page 27 for PV and Table 3, Design Service and Data Preparation Levels (Restricted), on page 37
for PR. For additional information on PV, see Table 8, Shape Manipulation Prior to Mask Write on page 59
LP or LVT NFET Std PFET

NV/XW NW
RX RX
PC PC
265 260
NW PV/LW
RX LW09/PV09
PC 260 265 PC
RX
LP or LVT PFET Std NFET

Figure 15. LP and LVT Devices at Minimum n+ to p+ Space
NFET LP or LVT PFET PFET

LW00/PV00
PC 290
LW09/PV09
PV04b PV04a
LW04b LW04a
RX
RX
PC NW
PV/LW
RX 294a 294b
NV04a NV04b
RX 299b/NV09b
PC
LP or LVT NFET
NV/XW
NW

Layout Rules Threshold Voltage Rules
Figure 16. LP and LVT FET Rules
3.5 Threshold Voltage Rules
Table 30. VTSENS (Threshold Voltage) Layout Rules

l Min.
a
s
s
VTSENS00 c (RX intersect PC) within VTSENS. 0.00
VTSENS01 c ((PC intersect RX) over VTSENS) to {NW, BB, IND_FILT, JD, 3.00
ZEROVT, BFMOAT, IND}.
VTSENS01a c ((PC intersect RX) over VTSENS) to ESDIODE. 3.10
VTSENS02 c (((PC intersect RX) over BP ) over VTSENS) within NW. 2.30
VTSENS03 c ((PC intersect RX) over VTSENS) to PI. 4.10

Layout Rules BP Layout Rules IBM
3.6 BP Layout Rules

Table 31. BP Layout Rules

l Min. Dim.
a
s
s
350 a 1 BP Width. 0.24 0.2400 0.075
351a a 1 BP area (m2). 0.197 - -
351b a 1 BP enclosed area (m2). 0.197 - -
352 a 1 BP to BP space. 0.24 0.240 0.075
353R d 2 RX P+ Junction within BP or BB. 0.14 0.1625 0.095
353 b 2 RX P+ Junction within BP or BB. 0.12 - -
354a b 3 [RX Substrate Contact not over (NW sized by 0.00 0.0225 0.095
+0.30)] within BP.
354bR d [RX Substrate Contact over (NW sized by 0.14 0.1625 0.095
+0.30)] within BP.
354b b [RX Substrate Contact over (NW sized by 0.12 - -

+0.30)] within BP.
355R d RX N+ Junction to adjacent BP. 0.14 0.1625 0.095
355 b RX N+ Junction to adjacent BP. 0.12 - -
356a b 4 [RX N-well Contact over (NW sized by -0.30)] to 0.00 0.0225 0.095
BP.
356bR d [RX N-well Contact not over (NW sized by 0.14 0.1625 0.095
-0.30)] to BP.
356b b [RX N-well Contact not over (NW sized by 0.12 - -

-0.30)] to BP.
357 b 5 BH to adjacent {NW, BB}. 0.40 0.40 0.075
357a a 5 BH width(for the BH mask). 0.40 0.40 0.075
357b a 5 BH to BH space(for BH mask). 0.40 0.40 0.075
357b1 a 5 BH to adjacent ZEROVT. 0.92 0.92 0.075
357b2 a 5 BH to adjacent {VAR, DG, JD, EFUSE}. 0.40 0.40 0.075

Layout Rules BP Layout Rules

l Min. Dim.
a
s
s
357b3 a 5 BH to adjacent PC(touching OP, over {RR, RP}). 0.52 0.52 0.075
358b a 5 PH width(for the PH mask). 0.40 0.40 0.075
358c a 5 PH space(for the PH mask). 0.40 0.40 0.075
358d a 5 BN width(for the BN mask). 0.24 0.24 0.075
358e a 5 BN to adj BN space(for the BN mask). 0.24 0.24 0.075
358f a 5 {BN,PD} to adj {BN,PD} (for generation of BN 0.24 0.24 0.075

mask).
358h a 5 BF width(for the BF mask). 0.68 0.68 0.122
358h1 a 5 BF to BF space. 0.92 0.92 0.122
358h2 a 5 (BF to BF space) over NWASP, not including 0.70 - -

notch.
358h3 a 5 BF notch. 0.70 - -
358j a 5 DE width. 0.40 0.40 0.075
358k a 5 DE space. 0.40 0.40 0.075
358k1 a 5 DE space to JP with touching prohibited. 0.40 - -
358m a 5 DF width. 0.40 0.40 0.075
358n a 5 DF space. 0.40 0.40 0.075
358n1 a 5 DF space to JN with touching prohibited. 0.40 - -
358p a 5,6 BT width. 0.88 1.01 0.122
358q a 5,6 BT space. 0.72 0.59 0.122
358r a 5 DW width. 0.40 0.40 0.075
358s a 5 DW space. 0.40 0.40 0.075
358t a 5 VI width. 0.80 0.8000 0.080
358u a 5 VI space. 0.80 0.8000 0.080
370 b 7 (PC over RX) to BP for no P+ in NFET gate. 0.25 0.2550 0.095
370a b (PC over RX) to BB ((PC over RX) touching BB 0.50 - -

not
allowed).

Layout Rules BP Layout Rules IBM

l Min. Dim.
a
s
s
371 b 8 (PC over RX) within BP for no N+ in PFET gate. 0.25 0.2550 0.095
1. This rule should check both drawn and generated BP shapes.
2. If a violation occurs where the RX is not fully within BP, then the Butted Junction rules apply. See Table 32, Butted Junction Layout
Rules, on page 131.
3. This rule does not need to be checked. When RX within BP < 0, butted junction rules apply. This rule clarifies that the coincidence of
BP and RX are allowed when Rule 354b does not apply.
4. This rule does not need to be checked. When RX to BP < 0, butted junction rules apply. This rule clarifies that the coincidence of BP
and RX are allowed when Rule 356b does not apply.
5. These rules are to check shapes internally generated in the DRC deck as defined in Table 8, Shape Manipulation Prior to Mask Write,
on page 59.
6. Wafer dimension bias 0.13m [ 0.88m to 1.01m, or 0.72m to 0.59m] specified is measured during lithography. Implant diffusion
bias is expected to be 0.1m (or approximately 0.03m [0.015m/edge] less than the lithography bias [ 0.88m to 0.98m, or 0.72m
to 0.62m]).
7. Exempt for BP edge of Butted Substrate Contact; see rule 378.
8. Exempt for BP edge of Butted N-well Contact; see rule 379. Space from butting BP inner edge of N-well contact to gate is given by rule
379.
BP
353
355
RX RX
371
PC 370 PC
371
(P+ Junction) (N+ Junction)
Figure 17. BP Rules

Layout Rules Butted Junction Layout Rules
3.7 Butted Junction Layout Rules

Butted junctions are formed when BP (not over BB) intersects RX. This region will be either a N+ junction and
a P+ substrate contact (if not over NW), or a P+ junction and a N-well contact (if over RX) within the same RX
shape. In Figure 18. Butted Junction Rules on page 132, Rules 260, 265, 353, 355 still apply outside the
butted junction region. A butted junction in close proximity to a FET can degrade the device. Therefore,
the use of butted junction is not recommended in analog, matching, or performance-critical circuits.
Table 32. Butted Junction Layout Rules

l Min. Dim.
a
s
s
372 b BP overlap of RX (butted substrate contact). 0.18 0.1575 0.095
372a b BP overlap RX - area (m2); (butted substrate con- 0.076 - -

tact).
373 b RX overlap past BP (butted n-well contact). 0.18 0.1575 0.095
373a b RX overlap past BP - area (m2); (butted n-well con- 0.076 - -

tact).
374 b (RX not over BP) over (NW sized by -0.08m) area 0.076 - -
(m2) (butted Nwell contact).
378 b (BP intersect RX) to adjacent [(PC intersect RX) not 0.24 0.1824 0.111
within BP] NFET gate to substrate contact space.
379 b (BP intersect RX) overlap past [(PC intersect RX) 0.24 0.1824 0.111
within BP] PFET gate to n-well contact space.

Layout Rules Butted Junction Layout Rules IBM
NW BP
Nwell 354a Substrate

373, 373a Contact 372, 372a Contact
379 378
260 265
CA CA CA CA
PC
CA CA CA CA
355
RX p+ junction n+ junction
RX
353
BP
Figure 18. Butted Junction Rules

Layout Rules CA, Metals and Via Layout Rules
3.8 CA, Metals and Via Layout Rules
3.8.1 CA, M1 (Thin) Metal and Vx Via Rules
Table 33. CA, M1 Metal and Via Layout Rules

l Min. Dim.
a
s
s
500 a M1 width (minimum). 0.16 0.160 0.045
500b a M1 width (maximum). 50.00 - -
501a b M1 area (m2). 0.089 - -
501b a M1 enclosed area (m2). 0.366 - -
502 a M1 to M1 space. 0.16 0.1448 0.045
504 b M1 to M1 space ; (if at least one metal line is 0.26 - -

>1.76 m wide) for run length > 0.
504R d M1 to M1 space ; (if at least one metal line is 0.36 - -

>1.04 m wide) for run length > 0.
504b b M1 to M1 space ; (if at least one metal line is 1.12 - -

>8.0m wide) for run length > 0.
504c b M1 to M1 space ; (if at least one metal line is 1.92 - -

504d b M1 to M1 space ; (if both metal lines are >4.0m 0.36 - -

wide) for run length > 0.
505a b 1 CA must be within M1. 0.00 -0.0205 0.069
506a b 1 M1 overlap past CA for at least 2 sides. 0.06 -0.0205 0.069
506aR d M1 overlap past CA for two opposite sides. 0.06 -0.0205 0.069
506ab b 1 CA must be within M1. 0.04 -0.0405 0.069
550 a V1, V2, V3, V4, V5 width and length. 0.20 0.230 0.050
551 b A Via array is defined as any group of two or - - -

more Vx (x = 1,2,3,4,5) vias spaced 0.38m
apart.

Layout Rules CA, Metals and Via Layout Rules IBM

l Min. Dim.
a
s
s
551a b 2 (Vx expanded by +0.19m then shrunk -0.69m) 1.60 - -

0.40m space and notch to (Vx expanded by
+0.19m then shrunk -0.69m), where
x=1,2,3,4,5. Four by n min pitch via arrays must
be 0.60m from any other via array.
551b b 2 (Vx expanded by +0.19m then shrunk -0.69m) 2.00 - -

0.80m space and notch to (Vx expanded by
+0.19m then shrunk -0.69m) where
x=1,2,3,4,5. Five by n min pitch via arrays must
551c b 2 (Vx expanded by +0.19m then shrunk -0.69m) 2.40 - -

= 1.20m space and notch to (Vx expanded by
+0.19m then shrunk -0.69m) where
x=1,2,3,4,5. Six by n min pitch via arrays must
551d b 2 (Vx expanded by +0.19m then shrunk -0.69m) 1.20 - -

maximum width, where x=1,2,3,4,5. Via arrays
larger than six by n are not allowed.
553 a Vx to Vx space where x=1,2,3,4,5. 0.20 0.17 0.050
553b a Vx minimum space for runlength > 0m, were 0.28 0.25 0.050
x=1,2,3,4,5 on different nets.
553d a Vx to VxBAR space (Vx touching VxBAR is pro- 0.60 - -

hibited) (x=1,2,3,4,5).
553e a Vx to VxBAR space (Vx touching VxBAR is pro- 1.20 - -

hibited) (x=L, Q, G).
557 c Vx must be square or rectangular and not at 45, - - -

where x=1,2,3,4,5, L,Q,G.
557b a VxBAR not over {GUARDRNG, IND, IND_FILT} - - -

must be square or rectangular and not at 45,
where x = L,Q, G (Note: GUARDRNG defines
the Chip Guard Ring).


l Min. Dim.
a
s
s
558 c 3 VxBAR not over {GUARDRNG, IND} is prohib- - - -
ited, where x = 1,2,3,4,5. (Note: GUARDRNG
defines the Chip Guard Ring, see Table 96,
Inductor Layout Rules, on page 269 or
Table 114, Chip Guard Ring Rules, on
page 319 for VxBAR dimensions).
558a a 4 VQBAR not over {GUARDRNG, IND, IND_FILT, - - -

(LM_RFLINE over LM)} is prohibited. (Note:
GUARDRNG defines the Chip Guard Ring, see
page 319. See Table 96, Inductor Layout Rules,
on page 269 or Table 98, LM RF Interconnect
Line Layout Rules, on page 275 or Table 114,
Chip Guard Ring Rules, on page 319 for
VQBAR dimensions).
558b a 5 VGBAR not over {GUARDRNG, IND, - - -

(LM_RFLINE over LM)} is prohibited. (Note:
GUARDRNG defines the Chip Guard Ring, see
page 319. See Table 96, Inductor Layout Rules,
on page 269 or Table 98, LM RF Interconnect
Line Layout Rules, on page 275 or Table 114,
Chip Guard Ring Rules, on page 319 for
VGBAR dimensions).
558c a 6 VLBAR not over {GUARDRNG, IND, IND_FILT} - - -

is prohibited. (Note: GUARDRNG defines the
Chip Guard Ring, see Table 96, Inductor Layout
Rules, on page 269 or Table 114, Chip Guard
Ring Rules, on page 319 for VLBAR dimen-
sions).
570 b 7 V1 must be within M1. -0.02 -0.0274 0.067
571 b 7 M1 overlap past V1 for at least 2 sides. 0.06 -0.0074 0.067
571aR d 7 M1 overlap past V1 for two opposite sides. 0.06 -0.0074 0.067
571b b 7 V1 must be within M1. 0.02 -0.0474 0.067
575 b V1 must be within M2. 0.00 -0.0639 0.099


l Min. Dim.
a
s
s
594 a 8,9,10, For nets connected to NW contact, where the 0.20 - -

11 NW net is not connected to a substrate contact
defined by ((RX over BP) not over (NW or RN or
BB or JD or PI or T3)), the ratio of [ (20*Mx area)
+ (Non-isolated p+ junction area ((((RX over BP)
over NW) not over PC) not over T3)) ] /
(union[NW,PI] area) where x=1,2,3,4,5,6.
(This check is for non-isolated Nwells not con-
nected to a substrate contact, and p+ junctions
in the non-isolated substrate regions are used to
meet the ratio).
594R d 8,9, 10, For nets connected to HA Varactor Cathode ((RX 0.20 - -
11 not over BP) over JD), where the cathode is not
connected to a substrate contact defined by ((RX
over BP) not over (NW or RN or BB or JD or PI
or T3)), the ratio of [ (20*Mx area) + (Non-iso-
lated p+ junction area ((((RX over BP) over NW)
not over PC) not over T3)) ] /
(union[NW,RN,PI,JD] area) where x=1,2,3,4,5,6.
(This check is for HA varactor well that is not
connected to a substrate contact, and p+ junc-
tions in the non-isolated substrate regions are
595 a 8, 10, For nets connected to ((RX over BP) over PI) 0.20 - -
11, 12 (Triple Well Pwell contact), the ratio of [ (20*Mx
area) + (Triple Well n+ junction area ((RX not
over (BP or JD or NW or RN or BB or PC)) over
PI) area ] / (union [(PI not over NW), (T3 not over
NW)] area) where x=1,2,3,4,5,6.
(This check is for the PI/T3 triple well (Pwell)
contact, and the PI/T3 N+ junction regions are
EPDL_M1 a (m1_estimated) minimum density (%) for boxes 10 - -

which do not touch {IND, IND_FILT, BONDPAD,
LOGOBND, PROTECT} over local 126m x
across the chip (where m1_estimated is defined
in rule EPDL_M1 on page 567).


l Min. Dim.
a
s
s
EPDLi_M1 a (m1_estimated) minimum density (%) for boxes 8 - -

which touch {IND, IND_FILT, BONDPAD} over
local 126m x 126m areas stepped in 63m
increments across the chip. Boxes which touch
LOGOBOUND or PROTECT are exempt.
1. Either rule 506ab OR (rule 505a + 506a) must be used.
2. All expand rules, which determine the boundaries of the via arrays, are in um/edge and are derived from: (Vx expanded by (Vx -
0.01um)), the generated shapes are unioned, then shrunk ((-3.5 x Vx) + 0.01um). The space and notch to any other Vx union (same
expand and shrink as above) must be groundrule defined width.
3. See also Rule IND11 in Table 96, Inductor Layout Rules, on page 269 for the inductor layout rule guidelines for the OL with LD or MA
metallization options. VxBARs are allowed only in the LM metallization option inductors or the Chip Guard Ring. However, per Rule
IND11, VxBARs are not allowed for the OL with LD or MA inductors.
4. See also Rule IND11 in Table 96, Inductor Layout Rules, on page 269for the inductor layout rule guidelines and Rule TL6a in Table 97,
MA RF Interconnect Line Rules, on page 274 for the MA metallization option. VQBARs are allowed in the LM or OL with LD
metallization option inductors, the LM metallization option RF lines structures and the Chip Guard Ring. However, per the rules
mentioned, VQBARs are not allowed for the MA inductors or MA RF lines.
5. See also Rule IND11d in Table 96, Inductor Layout Rules, on page 269 for the inductor layout rule guidelines and Rule TL6a in Table 97,
MA RF Interconnect Line Rules, on page 274 for the MA metallization option. VGBARs are allowed in the LM metallization option
inductors, the LM metallization option RF lines structures and the Chip Guard Ring. However, per the rules mentioned, VGBARs are
not allowed for the LD or MA inductors or MA RF lines since MG is not a valid level in those metallization stack options.
6. See also Rule IND11 in Table 96, Inductor Layout Rules, on page 269 for the inductor layout rule guidelines for the MA metallization
options. VxBARs are allowed in the LM or LD metallization option inductors or the Chip Guard Ring. However, per Rule IND11,
VxBARs are not allowed for the MA inductors.
7. Either rule 571b OR (rule 570 + 571) must be used.
8. Only the current metal level is included in the metal area measurement.
9. Only (RX p+ junction not over PC) connected to (NW contact of the NW level in which the p+ junction resides) is included in the area
measurement; any p+ junction not connected to the NW level in which it resides is ignored in the area measurement.
10. (NW not PI) and PI are conductors, so two different NW contacts in the same NW level or two different PI contacts in the same PI level
are assumed to be shorted.
11. The connectivity net definition for these rules allows pass through for resistors which have an (OP intersect {RX or PC} aspect ratio of
less than 100 to 1. This limits the resistance of pass through resistors.
12. Only (RX n+ junctions not over PC, not over NW) connected to (triple well contact of the isolated pwell in which the n+ junction resides)
is included in the area measurement; any n+ junction not connected to the isolated pwell in which it resides is ignored in the area
measurement.

553
V1 V1
553
V1 V1
V1
M1
505a, 506ab 600
V1 M1 V1 CA
M2
506a, 506ab
550
602
570,571b
571
M1 V1 571b M2
500 V2 V1
570,571 502
V1
V1 M1 CA
M1 M1
575
Figure 19. CA, Metal, Via Interconnect Rules
Clusters of min pitch Via arrays 0.38 apart will be unioned after expansion and treated as a larger array
(generated light gray shaded shape) which is measured against the size in the first line of Rule 551a, Rule
551b, Rule 551c description ( 0.40, 0.80, = 1.20) OR the Design Min column in GR 551d.
Example: Three 2X8 arrays spaced exactly equal to 0.38 apart are treated as a 6X8 array wider than
allowed by GR551d.

Via Array A Via Array B Via Array C

0.19
0.38 0.38 0.19
0.20 via space 0.38 (typical 3 places)
Expand all vias +0.19 per edge and union
Shrink -0.69 per edge
Figure 20. Example of 551d for 6 x 8 array Via Expansion, Union and Shrink

551a
Expand all vias +0.19 per edge and union
Shrink -0.69 per edge
Figure 21. Example of 4 x n Via Spacing array Rule

3.8.2 Mx (Thin) Metal, Interconnect and VL Via Rules
Table 34. Mx (x=2,3,4,5, 6) Metal and Via Layout Rules

l Min. Dim.
a
s
s
600 a M2, M3, M4, M5, M6 width (minimum). 0.20 0.2000 0.060
600b c M2, M3, M4, M5, M6 width (maximum). 50.00 - -
601a a M2, M3, M4, M5, M6 area (m2). 0.120 - -
601b a M2, M3, M4, M5, M6 enclosed area (m2). 0.366 - -
602 a M2 to M2, M3 to M3, M4 to M4, M5 to M5, M6 0.20 0.1632 0.060

to M6 space (top to top).
604 c M2 to M2, M3 to M3, M4 to M4, M5 to M5, M6 0.28 - -

to M6 space (if at least one metal line is
604R d M2 to M2, M3 to M3, M4 to M4, M5 to M5, M6 0.36 - -

to M6 space (if at least one metal line is
604b c M2 to M2, M3 to M3, M4 to M4, M5 to M5, M6 1.12 - -

to M6 space (if at least one metal line is >
8.0m wide) for run length > 0.
604c c M2 to M2, M3 to M3, M4 to M4, M5 to M5, M6 1.92 - -

to M6 space (if at least one metal line is >
25.0m wide) for run length > 0.
604d c M2 to M2, M3 to M3, M4 to M4, M5 to M5, M6 0.36 - -

to M6 space (if both metal lines are > 4.0m
wide) for run length > 0.
609 b 1,2 [(Mx width > 2.8m) intersect M(x+1)] density - - -

must be 56% over local 200m x 200m
areas, stepped in 100 m increments, where
Mx = M1, M2, M3, M4, M5, M6 and where
M(x+1) = M2, M3, M4, M5, M6 or MQ.
609R d 1,2 [(Mx width > 2.8m) intersect M(x+1)] density - - -

must be 50% over local 200m x 200m
areas, stepped in 100m increments, where
Mx = M1,M2, M3, M4, M5, M6 and where
M(x+1) = M2, M3, M4, M5, M6 or MQ.
610 b Vx must be within Mx, where x = 2-5. 0.00 0.0034 0.078


l Min. Dim.
a
s
s
610R d Vx must be within Mx, for at least 2 sides, 0.09 0.0934 0.078
preferably opposite sides, where x = 2-5.
610aR d Vx must be within Mx for two opposite sides, 0.00 0.0034 0.078
where x = 2-5.
611 b V2 must be within M3. 0.00 -0.0839 0.105

V3 must be within M4.
612 c 3,4,5 At least 2 vias must connect metal below to - - -

metal above when metal width is 1.04m.
For example, Mx to M(x+1) when either Mx or
M(x+1) 1.04 um wide.
See Figure 22, Redundant Via on Wide Line
Rules (Mx=M1,M2,M3,M4,M5 and M(x+1) =
M2, M3, M4, M5, M6) on page 145 for draw-
ings of this rules use.
612b c 3 At least 3 vias must connect metal below to - - -

612c c 3 At least 4 vias must connect metal below to - - -

612R d Use redundant vias when possible for Vx, - - -

where x = 1,2,3,4,5.
620a a VL width. 0.40 0.40 0.050
620b a VL length. 0.40 0.40 0.050
622 a VL to VL space. 0.40 0.40 0.050
622b a VL to VL space for common run length 0.56 0.3100 0.050

greater than 0m; vias on the same net are
exempt.
623a b 6 (VL not over Kx) must be within the Mx metal 0.00 0.0284 0.083
below (x=2,3,4,5,6).
624a b VL must be within MQ. 0.00 -0.0450 0.123


l Min. Dim.
a
s
s
EPDL_M2 a (m2_estimated) minimum density (%) for 10 - -

boxes which do not touch {IND, IND_FILT,
BONDPAD, LOGOBND, PROTECT} over
increments across the chip, where
m2_estimated is defined in rule EPDL_M2
on page 568
EPDLi_M2 a (m2_estimated) minimum density (%) for 8 - -

boxes which touch {IND, IND_FILT, BOND-
PAD} over local 126m x 126m areas
stepped in 63m increments across the chip.
Boxes which touch LOGOBOUND or PRO-
TECT are exempt.

on page 569.

TECT are exempt.

on page 570.

TECT are exempt.


l Min. Dim.
a
s
s

on page 571.

TECT are exempt.

on page 572.

TECT are exempt.
1. This local density requirement is calculated using the intersection of consecutive metal shapes over which the checking box is
stepped. When the box steps over the chip boundary, the box is moved back in bounds. The metal density is calculated using
design layout data prior to IBM design services MxHOLE or MxFILL. For consecutive level of metal information see Table 11,
LM last metal Back End Of Line (BEOL) Metallization Options, on page 64, Table 12, MA last metal Back End Of Line (BEOL)
Metallization Options, on page 65, and Table 13, OL with LD last metal Back End Of Line (BEOL) Metallization Options, on
page 66, and Table 14, AM last metal Back End Of Line (BEOL) Metallization Options, on page 67.
2. This local density requirement limits the stacked metal pattern (directly above and below) using an intersection methodology for
compatibility with available checking tools.
3. As further clarification for Rule 612: Redundant Vx vias can exist in any (Mx over M(x+1)) intersection under evaluation as long as the
redundant vias under consideration touch the wide metal intersection under consideration. To satisfy Rule 612, 612b, 612c, only one
via has to touch the wide metal intersection under consideration, while the remaining redundant vias, spaced according to the note
above and Figure 22, can be in any (Mx over M(x+1)) intersection, whether it is comprised of wide wires or thin wires, or any
combination thereof, that touch (or abut) the initial wide metal intersection, to satisfy this rule. It is preferred that all vias are placed in
the intersection where the wide metal is located, but it is not mandatory. See Figure 23 for one example layout.
4. Mx is metal below via and Mx+1 is metal above the via.

5. As further clarification for Rule 612: A minimum of 2 vias (touching each other when sized by 0.30um per edge) must connect to the
same metal shapes above and below. See Figure 22.
6. See various BEOL metallization options under Table 11, LM last metal Back End Of Line (BEOL) Metallization Options, on page 64,
Table 12, MA last metal Back End Of Line (BEOL) Metallization Options, on page 65, and Table 13, OL with LD last metal Back
End Of Line (BEOL) Metallization Options, on page 66, and Table 14, AM last metal Back End Of Line (BEOL) Metallization Options,
on page 67.
Note on Redundant Via Rule 612

In order to avoid a reliability failure mechanism for opens, redundant vias are required on any V1, V2, V3, V4,
V5 level that is used to electrically connect two metal levels (M1, M2, M3, M4, M5, M6) where either metal
shape is greater than the wide metal criteria of Rule 612, 612b, 612c.
Mx >= 1.04 um wide

minimum 2 or more vias
for V1, V2, V3, V4, V5.
M(x+1)
Figure 22. Redundant Via on Wide Line Rules (Mx=M1,M2,M3,M4,M5 and M(x+1) = M2, M3, M4, M5, M6)
One Example of Redundant Via Rule 612c

The example layout shown in Figure 23 satisfies Rule 612c. This is just one example for reference.
Narrow M1 abuts the wider M1 (same net)
M1 >= 0.20 um wide

(as an example)
M2 >= 0.20 um wide

(gray shaded M2 wire,
straddles both the M1 > = 3.0um wide
narrow and wide M1
wires)
Figure 23. Redundant Via on Wide Line Rule Example
Figure 24. Thin Metal Interconnect Rules (Mx=M1,M2,M3,M4,M5 and M(x+1) = M2, M3, M4, M5, M6)

M(x+1) M(x+1)
602
600
550
553 Vx
Vx
610 Vx
611
Mx Mx

MQ MQ
692
690
620a
Mx 620b
623a
VL VL
622
Mx
VL
Figure 25. VL Interconnect Rules (x=2,3,4,5,6)
3.8.3 LM (Thick) Metal Rules
Table 35. LM (Thick) Metal Layout Rules
C Notes Description Des Waf. Tol.

Rule l Min. Dim.
a
s
s
635 a LM width (minimum). 0.40 0.400 0.090
635b c 1 LM width (maximum). 53.00 - -
636a a LM area (m2). 0.48 - -
636b a LM enclosed area (m2). 0.87 - -
637 a LM to LM space. 0.40 0.3424 0.090

Table 35. LM (Thick) Metal Layout Rules

Rule l Min. Dim.
a
s
s
639 b LM to LM space (when at least one metal line is > 0.60 - -

2.0m) for run length > 0.
639b b LM to LM space (when at least one metal line is > 8.0 1.12 - -
m) for run length > 0.
639c b 2 LM to LM space (when at least one metal line is > 25.0 1.92 - -
m) for run length > 0.
639d c LMDUMHOL must be covered by (FV expanded by = - - -

21m).
1. This rule is waived for Wirebond pad structures (where the width (24um) of the last metal is governed by the Wirebond rules) and
for C4 pads that are supplied by the contact given in the Appendix.
2. The LM C4 pad oxide supports (holes), identified using LMDUMHOL, as shown in Figure 65, C4 Pad Design with LM pad (not drawn
to scale). on page 281 are excluded from this rule. For additional information on LMDUMHOL, see Table 6 on page 46.
LM LM
637
635
VQ
675
VG
676
VQ
VG
MQ, MG
Figure 26. LM Interconnect Rules

3.8.4 TV, FV Layout Rules (for LM BEOL Metallization Option Only)

See Table 11, LM last metal Back End Of Line (BEOL) Metallization Options, on page 64
or the allowable LM BEOL configurations related to the Rules in Table 35. See also
Table 111, Pad Model Rules for C4 and Wirebond with LM Metallization, on page 311 for
additional TV and FV layout rules.
Table 36. TV and FV Rules for LM Metal Options

Rule l Min. Dim.
a
s
s
650a a 1 TV Width (wafer bias shown is for small TV). 9.900 10.000 0.50
651a c TV area (min. m2). 370.75 - -
653a a TV to TV space (wafer bias shown is for small TV). 12.00 11.273 0.05
655 b FV width. 28.00 32.000 2.50
657 a FV to FV space. 19.36 11.8161 2.52
658a a FV within CHIPEDGE. 21.00 19.0000 1.73

1. Dimension perpendicular to the CHIPEDGE for Wirebond pad designs. The width in the Kerf (Dice lane) Crack-Stop is smaller
(1.60um).
3.8.5 DV Layout Rules

For LM metallization options, see alsoTable 11 on page 64 as well as Table 104 on
page 296 and Table 105 on page 300.
For MA metallization options, see also Table 12 on page 65 and Table 106 on page 302.
For the OL with LD metallization options, see also Table 13 on page 66 and Table 107 on
page 305.
For AM metallization options, see also Table 14 on page 67 and Table 108 on page 307.

.
Table 37. DV Rules

l Min. Dim.
a
s
s
655b a DV width. 28.00 28.00 2.50
657b a DV to DV space. 8.00 8.00 2.55
LD657b a (DV touching LD) to DV space. 11.00 11.00 5.50
MA657b a (DV touching MA) to DV space. 11.00 11.00 5.50
658ab a DV within CHIPEDGE. 8.00 8.00 1.73
659a a DV not over {TD, LD, MA, AM} is prohibited. = - - -
659b a LV not over {LD, MA, AM} is prohibited. = - - -
3.8.6 LV Layout Rules

See Table 12, MA last metal Back End Of Line (BEOL) Metallization Options, on page 65 for the allowable
MA BEOL metallization options that are related to the rules in Table 55. See also Table 101, C4 Layout
Rules (Active and Dummy with MA last metal level), on page 284 for additional LV layout rules.
See Table 13, OL with LD last metal Back End Of Line (BEOL) Metallization Options, on page 66 for the
allowable OL with LD BEOL metallization options that are related to the rules in Table 47. See also
Table 102, C4 Layout Rules (Active and Dummy for LD last metal level), on page 288 for additional LV lay-
out rules.
Table 38. LV Rules for OL with LD or MA Metal Options

Rule l Min. Dim.
a
s
s
650b b LV width. 14.00 14.000 5.500
651b c LV area (min. m2). 480.00 480.00 5.50
653b a LV to LV space. 20.00 20.000 5.500
658b a LV within CHIPEDGE. 16.00 16.000 3.028

3.8.7 MQ, VQ and MG, VG (Thick Metal) Layout Rules
Table 39. MQ, VQ and MG, VG (Thick Metal) Layout Rules

l Min. Dim.
a
s
s
675 a VQ width and length. 0.40 0.40 0.06

VG width and length.
676 a VQ to VQ space. 0.40 0.40 0.06

VG to VG space.
676b a VQ to VQ space. 0.56 0.56 0.06

VG to VG space.
for common run length greater than 0m; vias on
the same net are exempt.
690 a MQ width (minimum). 0.40 0.400 0.09

MG width (minimum).
690b c MQ width (maximum). 50.0 50.0 0.09

MG width (maximum).
691a a MQ area (m2). 0.48 - -

MG area (m2).
691b a MQ enclosed area (m2). 0.87 - -

MG enclosed area (m2).
692 a MQ to MQ space. 0.40 0.3424 0.09

MG to MG space.
693 b VQ must be within MQ. 0.00 0.0388 0.10

VG must be within MG.
EPDL_MQ a (mq_estimated) minimum density (%) for boxes 10 - -

LOGOBND, PROTECT, (QT if MG is not present)}
over local 126m x 126m areas stepped in 63m
increments across the chip, where mq_estimated
is defined in rule EPDL_MQ on page 573.
EPDLi_MQ a (mq_estimated) minimum density (%) for boxes 8 - -

which touch {IND, IND_FILT, BONDPAD, (QT if MG
is not present)} over local 126m x 126m areas
Boxes which touch LOGOBOUND or PROTECT
are exempt.

Table 39. MQ, VQ and MG, VG (Thick Metal) Layout Rules

l Min. Dim.
a
s
s
EPDL_MG a (mg_estimated) minimum density (%) for boxes 10 - -

LOGOBND, PROTECT, QT} over local 126m x
126m areas stepped in 63m increments across
the chip, where mg_estimated is defined in rule
EPDL_MG on page 574.
EPDLi_MG a (mg_estimated) minimum density (%) for boxes 8 - -

which touch {IND, IND_FILT, BONDPAD, QT} over
increments across the chip. Boxes which touch
LOGOBOUND or PROTECT are exempt.
694 b MQ to MQ space. 0.60 - -

MG to MG space.
when at least one metal line is > 2.0m wide, for
common run length greater than 0m.
694b b MQ to MQ space. 1.12 0.3424 0.09

MG to MG space.
when at least one metal line is > 8.0um wide, for
common run length greater than 0m
694c b MQ to MQ space. 1.92 0.3424 0.09

MG to MG space.
when at least one metal line is > 25.0um wide, for
common run length greater than 0m
695 b VQ must be within LM (if no MG present); 0.00 -0.0900 0.16

VQ must be within MG (if MG present).
695b b VG must be within LM. 0.00 -0.0900 0.16

MG
690
MQ
692
675
676 VQ
VQ
695
693
MQ
Figure 27. MQ and MG Rules
3.8.8 MQ or MG Layout Rules for Inductors (for OL with LD Metallization

options)
For the OL with LD metallization options only, defined in Table 13 on page 66, MQ or MG wires in the induc-
tors regions intersecting the dummy design level MxDUMHOL, where x = G or Q, do not receive MQHOLE or
MGHOLE shapes during the IBM release process, requiring additional layout rules for manufacturability as
listed in Table 40 on page 153 and Table 41 on page 154. MQ or MG wires that do not intersect the MxDUM-
HOL shapes, receive typically MxHOLE shapes on the same level.
Note: MxDUMHOL shapes that do not intersect the dummy design and utility level IND_FILT, when used for
OL or LD inductor layout, are prohibited.
For additional information on MxDUMHOL, where x = Q or G, that can only be used for the OL with LD metal-
lization options, see Table 6, Dummy Design Levels and Utility Levels on page 46, or Rule DS609h in
Table 245, xxHOLE Rules on page 558.
Table 40. MG Inductor Layout Rules

l Min.
a
s
s
INDMG1 a MGDUMHOL touching IND is prohibited. -

Table 40. MG Inductor Layout Rules

l Min.
a
s
s
INDMG2 a MGDUMHOL touching (IND_FILT touching {LM, LY, E1, MA, AM} is -
prohibited.
INDMG2a b 1,2 ((IND_FILT touching MG) touching {OL, LD}) must be within MGDUM- 0.0
HOL.
INDMGS3 b (MG over MGDUMHOL) space and notch if one MG wire is > 4.8m 1.5
wide.
wide.
wide.
wide.
wide.
wide.
wide.
1. The measured distance of MGDUMHOL not over IND_FILT, or IND_FILT within MGDUMHOL might not exactly match the specified
dimensions due to grid snapping ( grid times the square root of 2 tolerance).
2. Rule applies only to OL with LD metallization options that include MG. For additional information, see Table 13 on page 66.
Table 41. MQ Inductor Layout Rules

l Min.
a
s
s
INDMQ1 a MQDUMHOL touching IND is prohibited. -
INDMQ2 a 1 MQDUMHOL not over IND_FILT is prohibited. -
INDMQ2a b 1 ((IND_FILT touching MQ) touching {OL, LD}) must be within MQDUM- 0.0
HOL.

Table 41. MQ Inductor Layout Rules

l Min.
a
s
s
INDMQ2b a MQDUMHOL touching {MA,E1,AM,LM} is prohibited -
INDMQS3 b (MQ over MQDUMHOL) space and notch if one MQ wire is > 4.8m 1.5
wide.
wide.
wide.
wide.
wide.
wide.
wide.
1. The measured distance of MQDUMHOL not over IND_FILT, or IND_FILT within MQDUMHOL might not exactly match the specified
dimensions due to grid snapping ( grid times the square root of 2 tolerance).

3.8.9 JT and OL Layout Rules
JT and OL Standard Rules
Table 42. JT and OL Layout Rules

l Min. Dim.
a
s
s
JA1 a 1 JT exact width and length. = 1.2 1.55 0.55
JA1a a 1,2 JTBAR exact width. = 1.2 1.55 0.55
JA1b b JTBAR minimum length. 1.21 - -
JA1c1 b 3 (JTBAR not over GUARDRNG) maximum length. 20.0 - -
JA1d1 a JTBAR must be within {GUARDRNG, IND_FILT}. 0.0 - -
JA2 a JT minimum space to JTBAR with touching prohibited. 3.0 - -
JA3 a JTBAR minimum space and notch. 3.0 - -
JA4 b (JT not touching QT) must be within the metal below
(that is MQ, when MG is not present; or MG, when MG
is present). (Note: JT must be within metal below, unless
used for contact to QT or HT or KT MIM capacitor 0.6 0.11 0.18
plates. See Rule QT8ae in Table 90, QT and HT and
KT Common Layout Rules, on page 257 for (JT touch-
ing UNION(QT,HT, KT)).
JA5 b JTBAR must be within the metal below (that is MQ,

0.6 0.11 0.18
when MG is not present; or MG, when MG is present).
JA6 b JTBAR must be within metal above (that is, OL) - -

0.6
(Note: See Rule OL2 for JT within metal above).
JA7 a JT minimum space. 1.5 0.74 0.20
JA8 a JT must be an orthogonal rectangle. - - -
JA8a c 4 (JTBAR not over {GUARDRNG, IND_FILT}) must be an - - -

orthogonal rectangle.
JA551a b Via Density Rules: Use this Via Density Algorithm: Expand all JT vias by 1.19
m/edge, union all touching shapes, and shrink all unioned shapes by 4.19
m/edge to get Result Shapes. WR means width of Result Shape and SR means 1)
space between any two Result Shapes and 2) notch width of a Result Shape. The
algorithm groups JT vias with space 2.38 m (SD, array defining spacing). Rules
JA551b through JA551e gives limits on WR and SR. See also Section 3.8.10 Via
Density and Via Array Design Guide for JT Vias on page 159.


l Min. Dim.
a
s
s
JA551b b If width WR of Result Shape is 3.30 m, then this - -

design minimum is for SR. (For terms see Rule JA551a.
For application of this rule, see Array Design Guide. In 9.60
brief, this rule requires packed 4-wide JT arrays to be
3.6 m from other vias).
JA551c b If width WR of Result Shape is 6.00 m, then this - -

brief, this rule requires loose 4-wide JT arrays and
packed 5-wide arrays to be 6.0 m from other vias).
JA551d b If width WR of Result Shape is = 8.70 m, then this - -

brief, this rule requires packed 6-wide JT arrays to be
8.4 m from other vias).
JA551e b Maximum for width WR of Result Shape. (For terms see - -

Rule JA551a. For application of this rule, see Array
Design Guide. In brief, this rule allows packed 6-wide JT
arrays but prohibits loose 6-wide and all bigger JT arrays 8.70
( 7 vias wide) unless all internal via spaces > SD = 2.38
m).
OL1 b (OL touching IND_FILT) maximum width. 30.0 30.0 0.26
OL1b b (OL not touching IND_FILT) maximum width. 25.0 25.0 0.26
OL2 b JT must be within metal above (that is, OL). 0.6 0.33 0.25
OL3 a OL minimum width . 1.2 1.2 0.26
OL4 a OL minimum area (m2). 4.32 - -
OL4a a OL minimum enclosed area (m2). 1.83 - -
OL5 a OL minimum space and notch. 1.2 0.89 0.26
OL12 a 5 OL minimum local pattern density (%) with 400m tiling - -

10
stepped in 400m increments.
OL14 a OL maximum pattern density (%) with 100m tiling - -

stepped in 100m increments. (Failing checking boxes 85
are prohibited).


l Min. Dim.
a
s
s
OL16 a OL maximum local pattern density % (maximum) with - -

200m tiling stepped in 200m increments. (Failing 70
checking boxes are prohibited).
1. Rules JA1 and JA1a wafer dimension is at the bottom of the JT or JTBAR vias where they touch MG (build with MG) or touch MQ
(build without MG).
2. Non orthogonal widths can be checked to + or - 0.014 um from the groundrule value.
3. GUARDRNG = Chip Guard Ring.
4. Rule is not required to be verified in DRC since its intent is presently verified in Rule JA1d1. Rule defined as a reminder for future feature
development only.
5. Checking boxes with < 10% OL pattern density must not adjoin or hit any other box (in 8 directions) with < 10% OL density.
OL Step-Space Layout Rules (Wire Spacing Rules)

Step-space layout rules are also known as wide line, wide space layout rules. OL design level does not
receive auto-generated OLHOLE shapes.
Table 43. OL Thick Metal Wire Step-Space (Wire Spacing) Layout Rules

l Min.
a
s
s
OLS1 b OL minimum space and notch if at least one OL wire is > 2.4 m. 1.5
OLS1R d OL minimum space and notch if at least one OL wire is > 1.2 m. 1.5

OL Enclosed Area Layout Rules
Table 44. OL Enclosed Area Layout Rules

l Min.
a
s
s
OLA1 b OL minimum enclosed area (m2) touching (OL with width > 8.0 m and
19.0
11.5 m).
37.0
14.0 m).
61.0
17.5 m).
91.0
21.0 m).
127.0
24.5 m).
169.0
30.0 m).
3.8.10 Via Density and Via Array Design Guide for JT Vias
Summary of Via Density

JT via density rules for square JT vias require large spaces (at least 3 times min via space) between arrays 4
or more vias wide.
Via density is controlled because JT is etched before OL. Via density is not calculated by the usual pattern
factor formula (area of vias in a sample region divided by total sample area). Rather it is calculated by a linear
algorithm based on the clustering and spacing of vias. The result is a range of via densities between 11% and
21% depending on the actual layout of vias. The algorithm is correlated with test results.
The algorithms are complicated, so via pattern density is difficult to verify during design without stopping to
run a computer checking program. This design guide tells how to design arrays of vias without having to run
the algorithm. Final checking should use the algorithm.
The via density algorithms and this array density design guide do not apply to bar vias JTBAR. They gener-
ally do not form arrays because bar vias have more restrictions on their use (restricted to inductors and chip
guard ring and have bigger spaces).

Simplest Method
This is conservative method for designing arrays of JT vias. (That is, it has bigger spaces than necessary in
some cases.) But it is simple. It is best applied to arrays of vias (i.e., orderly groups with approximate uniform
internal spacing).
Table 45 on page 160 applies only to square JT vias. JT via array means any group of two or more JT vias
whose space is =< SD = 2.38. The rules for the two arrays do not interact. If an external via comes within SD
= 2.38 m of a via array or group being designed, then it must be considered part of the array or group. If any
internal spaces become greater than SD then the array splits up and must regroup.
Table 45. Via Array Design Guide for JT Vias - Simplest Method
Array Space to other (external) Comments.

Width (in VIas Sext min (m)
vias) N
2 2.38 No Comment
3 2.38 No Comment
4 6.00 No Comment
5 8.40 No Comment
6 8.40 only if tightly packed Tightly packed is defined as all internal via spaces are
minimum via space, per Rule JA7.
7 Not allowed 7 or more vias create a dense region that is too wide for
processing, if internal spacing is < SD = 2.38m.
Spread-out arrays (all internal space > SD) may be any
size.
Array Space to other Arrays or Vias

For a given size of Array (number of vias across and internal space Sint) a via density algorithm specifies the
minimum space Sext to the next array or to any via not part of the first array. Via density algorithms apply to
square JT vias. There is no density restriction on JTBAR vias. Via density rules do not apply to Bar vias,
because Bar vias have more restrictions on their use (restricted to inductors and chip guard ring and have
bigger spaces).

JT JT JT JT JT
S external
S internal
JT JT JT JT JT
Array Being Checked Neighboring Array

S external
JT
Neighboring Via
Figure 28. Array Space to other Arrays or Vias
Space Saver Method

Decide which vias to use, (JT is only choice). These are square vias, not bars.
Decide how big an array to design (how many vias across and down, the array span size).
Select the smaller array span, N (in number of vias in a row or column).
Decide on internal via space, Sinternal (between vias inside the array). (It may be uniform or an average
space along the row or column in step 2.) Select a internal via space value, Sint, that is within one of the
ranges in the table, between Sint lo and Sint hi.
In the table below, find the row corresponding to the desired N and Sinternal (Sint). The last column
gives, Sexternal (Sext), the minimum external space between the desired array and any other via, either
inside an array or isolated. (If the neighbor is a larger array, it will have its own external space require-
ment, which might be larger than for this array.)
Table 46 on page 162 applies for approximately regular dense arrays of JT square vias. Arrays designed
using this table are expected to pass the Via Density Algorithm. There might be exceptions. Final check
should be with the exact via density rule JA551. All dimensions are in microns.

Table 46. Via Array Design Guide for JT Vias - Space-Saver Method
JT N-Array (N All internal spaces in this range External Space Sect

columns) minimum (m)1
Sint lo Sint hi
2 1.50 no limit > 2.38
3 1.50 no limit > 2.38
4 1.50 > 2.00 3.60
4 1.50 2.38 > 6.00
4 > 2.382 no limit > 2.38
5 1.50 > 1.80 6.00
5 1.50 2.38 8.40
5 > 2.382 no limit > 2.38
6 = 1.50 = 1.50 > 8.40
6 1.50 2.38 not allowed
6 > 2.382 no limit > 2.38
7 1.50 2.38 not allowed
7 > 2.382 no limit > 2.38
1. Internal space Sint is the space between vias inside the array. SD is the dense via space, which determines when vias are
grouped by the via density algorithm. If Sint > SD = 2.38, then the array might change, becoming two arrays, requiring different
array rules. If all Sint > 2.38, then the dense array becomes a sparse array.
2. External space is the space between the outer vias of the array and a via outside the array. It is measured in x or y or both; not diagonal.
If Sect SD = 2.38, then the adjacent via becomes part of the array, changing the array size, and possibly requiring different array
rules.
Via Array Details

This guide tells how much to space an array of JT vias from other arrays of JT vias, or from isolated JT vias.
It works with regular arrays and somewhat irregular arrays. It is sometimes more conservative than the algo-
rithm rules (Rule JA551a for JT), but is easier to design with, and arrays designed using this guide are
expected to pass the algorithm rules unless the array is highly irregular.
This guide works with regular arrays and somewhat irregular arrays. A regular array has uniform internal via
spacing, Sint, and N vias across its width (i.e., N columns wide). Array width is the smaller of the two overall
dimensions of the array, as measured in microns along x and y design axes, independent of which direction
has more vias. (Usually, the long direction, or array length, has more vias, i.e. more rows.) This assumes the
array is oriented in the usual manner, with rows and columns of vias parallel to x and y.

An irregular array has variable internal spacing Sint, missing vias, staggered columns or rows, and other
deviations from a regular pattern. This guide might work with arrays that are not too irregular, and have the
general appearance of an array.
Under certain conditions the space from the array (outer vias) to a via outside the array, including to adjacent
arrays, must be greater than the minimum ground rule, S0, for space between vias. This is called the external
space, Sext. This guide shows how to determine Sext for a given array.
Sparse Arrays of JT Vias

Sparse arrays are defined as having every Sint greater than SD, the dense via space, Sint > SD. SD = 2.38
m for JT vias, by JA551a. External space Sext also must be greater than SD (Sext > SD). Otherwise the
external via(s) would become part of the array, for the purpose of this guide and for the array space rules,
which would modify how the rules and guide would apply to the desired array.
Via space requirement for Sparse Array: The only requirements are Sint > SD = 2.38 m and Sext > SD
= 0.38 m, when measured along either x or y design direction, or both. Diagonal space (corner to corner)
being greater than SD is not sufficient. This means the space from any via in a sparse array to any other via
whatsoever, inside the same array or outside it, must be greater than SD when measured along x or y as
described. The array rules JA551a do not apply to sparse arrays, or to any pattern, no matter how irregular,
so long as all spaces are > SD.
Dense Arrays of JT Vias

Dense arrays are defined as having every internal via space Sint not greater than SD, the dense via space
(Sint [SD). In this case, as the width an the array increases, its external space Sext to an adjacent array must
increase, by a step-function. For each array size (value of N) and minimum external space Sext, the via den-
sity algorithm limits the range of values allowed for internal space Sint. If Sint goes above that limit, then Sext
must increase. The maximum value of N (the number of columns of vias) is also limited. Values for Sext are
given in Table 45, Via Array Design Guide for JT Vias - Simplest Method, on page 160.
Regular Dense JT Arrays

A regular dense array has essentially straight columns and rows of vias, with N 2 vias in each row (N col-
umns of vias) and L 2 vias in each column (L rows of vias), where L N, for exactly L*N vias in the Array.
This is called an N-Array, N vias wide. The internal spacing is uniform enough that all Sint fall in one of the
ranges shown in Table 46, Via Array Design Guide for JT Vias - Space-Saver Method, on page 162. This
table also works for slightly irregular arrays, which has slightly staggered columns or rows, or missing vias, so
long as all Sint fall in one of the ranges. (Ignore Sint distorted by missing vias).

3.8.11 VV and LD Layout Rules
Table 47. VV, LD Layout Rules

l Min. Dim.
a
s
s
LD00 a 1 LD minimum width. 2.0 2.16 0.60
LD01a a LD minimum area (m2). 10.0 - -
LD02 a 1 LD minimum space and notch. 2.8 2.64 0.60
LD02a a 2 (LD over IND_FILT) minimum space and notch. 3.0 - -
LD04a b LD minimum space and notch to (LD with width > 35 4.0 - -
m).
LD04a1 b LD minimum space and notch to (LD with width > 50 5.0 - -
m).
LD04b b LD minimum space and notch to (LD with width > 17.50 - -
140 m).
LD40 a LD minimum density (%) with 400 m tiling, except 10.0 - -

use step increment equal to 400 m.
Exemption: Tiles touching {DV wirebond pads, DV
probe pads}3
LD49 a VV must be an orthogonal rectangle. - - -
LD50 a VV exact width and length. 4.0 3.90 0.50
LD53 a 4 VV minimum space. 2.0 1.90 0.50
LD57 c (VVBAR not over IND_FILT) must be orthogonal - - -

rectangle.
LD70 b 5 VV must be within OL. 0.7 0.91 0.57
LD75 b 6 VV must be within LD. 1.0 0.95 0.64
LD90 a 7 VVBAR exact width. 4.0 3.90 0.50
LD90a b VVBAR minimum length. 5.0 4.09 0.50
LD91 a VVBAR minimum space and notch. 2.0 1.90 0.50
LD91a a VVBAR minimum space to VV with touching prohib- 2.0 1.90 0.50
ited.
LD93 c VVBAR must be within IND_FILT. 0.0 - -

1. The wafer value is at the half-height measurements of an isolated feature. For the complete listing of wafer values see Table 180,
Extraction Parameters for Metal Wiring, on page 428.
2. The measured space of LD shapes used in inductors might not exactly match the specified dimensions due to grid snapping ( grid
times the square root of 2 tolerance).
3. For this rule only, {DV wirebond pads, DV probe pads} is defined as (DV over LD).
4. The wafer value for this rule is measured from the top of VV to top of VV.
5. For VVBAR within the metal above or below, see Table 96 on page 269.
6. The wafer value for this rule is measured from the top of VV to the bottom of LD.
7. The measured width of LD shapes used in inductors might not exactly match the specified dimensions due to grid snapping ( grid times
the square root of 2 tolerance).

3.8.12 FY Via Layout Rules
Table 48. FY Layout Rules

Rule l Min. Dim.
a
s
s
FY1 a 1 FY (tungsten via) width/length (exact). 1.000 0.900 0.250
FY2 a 2 FY space. 1.000 0.800 0.250
FY3 c FY must be square or rectangular and not at 45 degrees. (no polygon shapes
allowed).
FY4 b FY must be within MQ (if no MG present); 1.260 0.757 0.553

FY must be within MG (if MG present).
FY4a a FY can not touch LM.
FY5 b FY must be within LY. 1.260 0.721 0.489
FY7 c A minimum of 2 FY vias, spaced 1.00 m and 2.00 m, must connect (MQ or MG)
to LY.
FY14 a FYBAR not over GUARDRNG is prohibited. = - - -

1. Wafer dimension is at the bottom of via
2. Wafer dimension is at the top of via
3.8.13 LY Metal Layout Rules
Table 49. LY Layout Rules

Rule l Min. Dim.
a
s
s
LY1 a LY width (wafer dimension is at the bottom of metal). 0.600 0.600 0.260
LY2 a LY to LY space (bottom-to-bottom). 0.600 0.600 0.260
LY2a c LY to LY space (if at least one metal line is > 10.0m 0.800 0.800 0.260
wide and the common run length is > 10.0m long).
LY2b c LY to LY space (if at least one metal line is > 35.0m 2.000 - -
wide).
LY4 a LY Area (m2). 1.100 - -

Table 49. LY Layout Rules

Rule l Min. Dim.
a
s
s
LY5 a LY Enclosed Area (m2). 1.100 - -
LY6 a 1 LY pattern density % (minimum) over local 400m x 10 - -

400m areas stepped in 400m increments across the
chip.
(see also Rule F27b in Table 20 on page 93 for a
description of drawn LY used to meet pattern density
purposes)
1. Checking boxes with < 10% LY pattern density must not adjoin or hit any other box (in 8 directions) with < 10% OL density.

3.8.14 FT and FTBAR Via Layout Rules
Table 50. FT and FTBAR Layout Rules

Rule l Min. Dim.
a
s
s
FT1 a 1 FT width/length (only value allowed). 1.240 1.240 0.250
FT2 a 2 FT space. 2.000 1.240 0.250
FT3 a 1,3 FTBAR width. 1.240 1.240 0.250
FT4 c FTBAR minimum length. 1.280 - -
FT5 c FTBAR maximum length (except in chip guard ring). 20.00 - -
FT6 a 2 FT to FTBAR (FT cannot touch FTBAR). 2.000 1.240 0.250
FT7 a 2 FTBAR space (for common run less than or equal to 2.000 1.240 0.250
5.0m).
FT8 a 2 FTBAR space (for common run greater than 5.0m). 4.000 3.240 0.250
FT9 b FT must be within LY. 1.000 0.467 0.532
FT10 b FTBAR must be within LY. 1.000 0.467 0.532
FT11 b {FT, FTBAR(except in chip guard ring)} must be square or rectangular.
FT12 b 45o FT is prohibited.

45o FTBAR is prohibited (except in chip guard ring).
FT13 c A minimum of 2 ((FT not touching QY) or FTBAR(not in chip guard ring)) vias,
spaced 2.0 m and 4.0 m, must connect LY to E1.
3. For verification of 45 degree (FTBAR (in the chip guard ring)) width aspects, a 0.014 tolerance range on the exactly equal to design
minimum value specified applies to avoid false verification errors. This tolerance is intended to only apply in the non-orthogonal 45
degree bends in the chip guard ring (over GUARDRNG).
3.8.15 E1 Metal Layout Rules

E1 General Rules
Table 51. E1 Metal Layout Rules

l Min. Dim.
a
s
s
E1a a E1 width (wafer dimension is at the bottom of the metal). 1.500 1.250 0.250
E1aa a E1(not over IND_FILT) width (maximum). 25.00 - -
E1ab a (E1 over (IND_FILT sized by 25m)) width (maximum). 30.00 - -

E1b a E1 space (top-to-top). 2.000 1.750 0.250
E1c b F1 must be within E1. 1.260 0.855 0.530
E1d b F1BAR(not touching L1) must be within E1. 1.260 0.855 0.530
E1e b FT must be within E1. 1.000 0.210 0.530
E1eR d FT must be within E1. 1.200 0.410 0.530
E1f b FTBAR must be within E1. 1.000 0.210 0.530
E1fR d FTBAR must be within E1. 1.300 0.410 0.530
E1g a E1 area (minimum) (m2). 9.00 - -
E1 Enclosed Area Layout Rules
Table 52. E1 Enclosed Area Rules

l Min. Dim.
a
s
s
E1A1 c E1 minimum enclosed area (m2) touching (E1 with width > 19.0 - -
8.0m and 11.5m).
11.5m and 14.0m).
14.0m and 17.5m).
17.5m and 21.0m).
21.0m and 24.5m).

Table 52. E1 Enclosed Area Rules

l Min. Dim.
a
s
s
24.5m and 28.0m).
28.0m and 30.0m).

E1 Spacing and Pattern Density Layout Rules
Table 53. E1 Spacing and Pattern Density Rules

l Min. Dim.
a
s
s
E1S1 b 1 E1 to E1 space (if one metal line is > 8.0m and 11.5m). 2.50 - -
E1S2 b 1 E1 to E1 space (if one metal line is > 11.5m). 3.50 - -
E2 a 2 E1 local pattern density % (minimum) over local 400m x 10 - -

400m areas stepped in 400m increments across the chip.
(see also Rule F27b in Table 20 on page 93 for a description
of drawn E1 used to meet pattern density purposes).
E4 a E1 local pattern density % (maximum) over local 100m x 85 - -

Failing checking boxes are prohibited.
E6 a E1 local pattern density % (maximum) over local 200m x 70 - -

Failing checking boxes are prohibited.
1. Notch checking is not required in DRC since local pattern density rules E4 and E6 are verified.
2. Checking boxes with < 10% E1 pattern density must not adjoin or hit any other box (in 8 directions) with < 10% E1 density.
3.8.16 F1 and F1BAR Via Layout Rules
Table 54. F1 and F1BAR Layout Rules

l Min. Dim.
a
s
s
MAF1a a 1 F1 width/length (only value allowed). 1.240 1.240 0.250
MAF1b a 2 F1 space. 2.000 1.240 0.250
MAF1c1 a 1 F1BAR (not over {IND_FILT, GUARDRING}) 1.240 1.240 0.250

width.
MAF1c2 a 1,3 F1BAR (over {IND_FILT, GUARDRING}) width. 1.240 1.240 0.250
MAF1d b F1BAR minimum length. 3.000 - -
MAF1e c (F1BAR not covered by IND_FILT) maximum 20.00 - -

length.

Table 54. F1 and F1BAR Layout Rules

l Min. Dim.
a
s
s
MAF1g a 2 F1BAR space (for common run 5.0m). 2.000 1.240 0.250
MAF1h a 2 F1BAR space (for common run > 5.0m). 4.000 3.240 0.250
3,4
MAF1i b (F1BAR (not covered by IND_FILT) or (not in the chip guard ring)) must be rect-
angular and not at 45 degrees. (no polygon shapes allowed).
MAF1j b F1 must be square or rectangular and not at 45 degrees (no polygon shapes
allowed).
MAF1k a 2 F1 to F1BAR (F1 cannot touch F1BAR). 2.000 1.240 0.250
MAF1p c 5 A minimum of 2 F1 vias, spaced 2.0 m and 4.0 m, must connect E1 to MA.
MAF1qR d 6 A minimum of 2 F1BAR(not in the chip guard ring4) via bars, spaced 2.0 m and
4.0 m, must connect E1 to MA.
3. For verification of 45 degree width aspects, a 0.014 tolerance range on the exactly equal to design minimum value specified applies
to avoid false verification errors. This tolerance is intended to only apply in the non-orthogonal 45 degree bends in the inductors (over
IND_FILT) or chip guard ring (over GUARDRNG).
4. For verification, the description syntax (not in the chip guard ring) is the equivalent of (not over GUARDRNG).
5. The intent of Rule MAF1p is to verify where at least one or more F1 vias touches an E1 over MA metal intersection. Consecutive E1
and MA metal level intersections, not touching F1 vias, is not validated to this rule.
6. This is a recommended rule. The intent of Rule MAF1qR is where at least one or more F1BAR vias touches an E1 over MA metal
intersection. Consecutive E1 and MA metal level intersections, not touching F1BAR vias, is not validated to this recommended rule.
It is a known limitation that F1BAR vias in inductors coil areas may not comply with this recommended rule, when verified in DRC using
recommended rule verification.

3.8.17 MA Metal Layout Rules
Table 55. MA Layout Rules

l Min. Dim.
a
s
s
MA1 a MA width (wafer dimension is at bottom of metal). 4.000 4.320 0.860

MA2 a MA space (wafer bottom-to-bottom). 5.000 4.680 0.860
MA4 b F1 must be within MA. 1.500 0.367 0.874
MA4a b F1BAR must be within MA. 1.500 0.367 0.874
MA6 a MA Area (m2). 16.00 - -
MA7 a MA Enclosed Area (m2). 25.00 - -
3.8.18 AM Metal Layout Rules
Table 56. AM Layout Rules

l Min. Dim.
a
s
s
AM1 a 1 AM width (wafer dimension is at bottom of metal). 2.00 2.18 0.60
AM1a a AM minimum area (m2). 16.00

AM2 a 1 AM space (wafer bottom-to-bottom). 2.80 2.64 0.60
AM2a c AM space for AM edges over ((FQ not over 5.00

{LOWCRNT,IND_FILT}) sized by 8m).
AM2a1 c AM space for AM edges over (((FQ over IND_FILT) 5.00

not over LOWCRNT) sized by 6m).
AM2b c (AM not over IND_FILT) space (if at least one metal 4.00
line is greater than 10 m wide).
AM2b1 c (AM over(IND_FILT sized by 25m per edge)) space 3.00

(if at least one metal line is > 10m and 25m
wide).
AM2b2 c (AM over(IND_FILT sized by 50m per edge)) space 4.00

(if at least one metal line is > 25m and 50m
wide).

Layout Rules Mask Process Control Images IBM
Table 56. AM Layout Rules

l Min. Dim.
a
s
s
AM2c c AM space (if at least one metal line is greater than 50 5.00
m wide).
AM3 b FQ must be within AM. 0.68 0.625 -0.047

1. The physical wafer values are at half-height measurements of an isolated feature
3.8.19 FQ & FQBAR Via Layout Rules
Table 57. FQ Layout Rules

l Min. Dim.
a
s
s
FQ1 a FQ width and length(only allowed value) = 0.60 0.60 0.090
FQ3 a FQ must be square (no polygon shapes allowed except in chip guard ring)
FQ4 a FQ space 0.60 0.60 0.090
FQ6a b FQ must be within MQ 0.24 0.309 0.071
FQ7 c A minimum of 2 FQ vias, spaced 0.6m and 1.8m, must connect MQ to AM. This
rule only applies to the intersection of MQ/AM does not apply to MIM structures.
FQ14 a FQBAR is only allowed in the Chip Guard Ring.
3.9 Mask Process Control Images

To achieve tight image size and registration control for PC mask, special reticle measurement features, called
Process Control Images (PCIs) are required to be placed in the data.
The PCI requirement is waived on any chip with a width or length shorter than 6mm on any side. Suf-
ficient PCIs are placed in the kerf for chips with a length or width dimension smaller than 6mm.
Requirements:
1. The design level PCING must be used to draw each PCI
2. The PCI shape must exist in its own, separate data cell (model). The cell must have a 6-8 character
uppercase alphanumeric name containing the string IPCI. The character string IPCI must be in the

Layout Rules Mask Process Control Images
upper case. There is no limit to the number of cell names.

3. The character string IPCI must not be used in any other cell names.
4. Ideally, if the chip was divided into a 12 x 12 matrix, each of the 144 tiles would contain one PCI. How-
ever, it is sufficient to have some PCIs near each of the corners of the chip and some PCIs in the interior
of the chip near the center.
5. The centerpoint of the PCI shape must be identical to the origin of the cell (model). The centerpoint is at
the center of the intersect of horizontal and vertical arms.
Table 58. PCING Layout Rules
C Notes Description Des

Rule l Min.
a
s
s
780 a PCING width. 0.12
781b a The character sequence IPCI (all uppercase) is prohibited in all data cells -
in the design except those defined by Rules 780, 782 and 783.
782 a PCING to {PC, PCING, RX, CA, CABAR, IND_FILT, BONDPAD, IND, 0.42
BFMOAT}
(PCING touching {PC, PCING, RX, CA, CABAR, IND_FILT, BONDPAD,
IND, BFMOAT} is prohibited).
783 a Length of PCING arm from corner to end. 2.00
784 a 1 At least 40 PCI cells should be uniformly distributed over the active chip -
area.
1. This requirement is waived on any chip with a width or length shorter than 6mm on any side. . For width/length checking purposes,
the chip active area = least enclosing rectangle of CHIPEDGE (because of the chamfered corners)
780
780
783
centerpoint
783
783
Figure 29. PCING Structure

Layout Rules Latchup Rules IBM
3.10 Latchup Rules

Table 59. Latchup Rules

l Min.
a
s
s
LUP01 b Nwell contact distance to thin-oxide PFET and p+ junctions, refer to

Rule 268a (see Table 24 on page 115) and Rule T3W268 (see
--> Limit resistance from PFET source/drain and p+ junctions to NW

contact inside Nwell (thin-oxide PFET and p+ junctions).
LUP02 b Substrate contact distance to thin-oxide NFET and n+ junctions, refer

to Rule 268b1 (see Table 24 on page 115) and Rule T3W268b (see
--> Limit resistance from NFET source/drain and n+ junctions to SX

contact or triple well Pwell contact (thin-oxide NFET and n+ junc-
tions).
LUP03 b Nwell contact distance to thick-oxide PFET and p+ junctions, refer to

Rule DG268a1 (see Table 78 on page 231) and Rule T3WDG268
(see Table 23 on page 104).
--> Limit resistance from PFET source/drain and p+ junctions to NW

contact inside Nwell (thick-oxide PFET and p+ junctions).
LUP04 b Substrate contact distance to thick-oxide NFET and n+ junctions,

refer to Rule DG268b1 (see Table 78 on page 231) and Rule
T3WDG268b (see Table 23 on page 104).
--> Limit resistance from NFET source/drain and n+ junctions to SX

contact or triple well Pwell contact (thick-oxide NFET and n+ junc-
tions).
LUP05 b RX P+ junction within NW, refer to Rule 260 (see Table 24 on

page 115).
--> P+ inside NW, defines minimum lateral PNP (P+/NW/SX) base

width (thin-oxide diffusions).
LUP06 b RX N+ junction to adjacent NW, refer to Rule 265 (see Table 24 on

page 115).
--> N+ to adjacent NW, defines minimum lateral NPN (N+/SX/NW)

base width (thin-oxide diffusions).

Layout Rules Latchup Rules

l Min.
a
s
s
LUP07 b (RX P+ junction touching DG) within NW , refer to Rule DG260 (see
--> P+ inside NW, defines minimum lateral PNP (P+/NW/SX) base

width (thick-oxide diffusions).
LUP08 b (RX N+ junction touching DG) to adjacent NW, refer to Rule DG265a
(see Table 78 on page 231).
--> N+ to adjacent NW, defines minimum lateral NPN (N+/SX/NW)

base width (thick-oxide diffusions).
LUP09A b (Total area of [(RX intersect BP) touching CA] outside {NW, BB}) / 0.01
(Total {PC intersect RX} outside {NW, BB}) over local (2.1XLUP02)2
area stepped in ((2.1XLUP02)/2) increments (Applicable if burn-in
or in general elevated voltage stressing will NOT occur).
--> Limit amount of vertical SX resistance seen by thin-oxide NFETs

in a given tile.
LUP09B b (Total area of [(RX intersect BP) touching CA] outside {NW, BB}) / 0.2
(Total {PC intersect RX} outside {NW, BB}) over local (2.1XLUP02)2
area stepped in ((2.1XLUP02)/2) increments (Applicable if burn-in
[1.5X Vdd] WILL occur).
--> Limit amount of vertical SX resistance seen by thin-oxide NFETs

in a given tile.
LUP10A b (Total area of [(RX intersect NW) touching CA] outside BP) / (Total 0.01
{PC intersect RX and BP} inside NW) over local (2.1XLUP01)2 area
stepped in ((2.1XLUP01)/2) increments (Applicable if burn-in or in
general elevated voltage stressing will NOT occur) (For each
Nwell within the tile, the ratio should be checked separately).
--> Limit amount of vertical NWell resistance seen by thin-oxide

PFETs in a given tile.


l Min.
a
s
s
LUP10B b (Total area of [(RX intersect NW) touching CA] outside BP)/(Total 0.2
{PC intersect RX and BP} inside NW) over local (2.1XLUP01)2 area
stepped in ((2.1XLUP01)/2) increments (Applicable if burn-in,
[1.5X Vdd] WILL occur) (For each Nwell within the tile, the ratio
should be checked separately).
--> Limit amount of vertical NWell resistance seen by thin-oxide

LUP11A b (Total area of [(RX intersect BP) touching CA] outside {NW, BB}) / 0.06
(Total {(PC intersect RX) over DG} outside {NW, BB}) over local
(2.1XLUP02)2 area stepped in ((2.1XLUP02)/2) increments (Appli-
cable if burn-in or in general elevated voltage stressing will NOT
occur).
--> Limit amount of vertical SX resistance seen by thick-oxide NFETs

in a given tile.
LUP11B b (Total area of [(RX intersect BP) touching CA] outside {NW, BB}) / 1.0
(Total {(PC intersect RX) over DG} outside {NW, BB}) over local
(2.1XLUP02)2 area stepped in ((2.1XLUP02)/2) increments (Appli-
cable if burn-in [1.5X Vdd] WILL occur).
--> Limit amount of vertical SX resistance seen by thick-oxide NFETs

in a given tile.
LUP12A b (Total area of [(RX intersect NW) touching CA] outside BP) / (Total 0.06
{(PC intersect RX and BP} over DG inside NW) over local
(2.1XLUP01)2 area stepped in ((2.1XLUP01)/2) (Applicable if
burn-in or in general elevated voltage stressing will NOT occur)
(For each Nwell within the tile, the ratio should be checked sep-
arately).
--> Limit amount of vertical NWell resistance seen by thick-oxide



l Min.
a
s
s
LUP12B b (Total area of [(RX intersect NW) touching CA] outside BP) / (Total 1.0
{(PC intersect RX and BP} over DG inside NW) over local
(2.1XLUP01)2 area stepped in ((2.1XLUP01)/2) (Applicable if
burn-in, [1.5X Vdd] WILL occur) (For each Nwell within the tile,
the ratio should be checked separately).
--> Limit amount of vertical NWell resistance seen by thick-oxide

LUP13 b 1 RX N+ (RX not over BP) shapes connected to an IO pad must be

contained within a Substrate guard ring (RX over BP) and a Nwell
guard ring (N+ inside NW). The guard rings must be within 15 um
from at least one edge of the RX shape. No P+ shapes within NW
are allowed within this guardring.
--> NW guardring is used to collect minority electrons injected into

the substrate.
LUP13aR d {[NW touching (RX n-well contact guard ring, satisfying Rule LUP13)] 2.0
over ESDUMMY} minimum width.
LUP13bR d [CA over (RX n-well contact guard ring, satisfying Rule LUP13a)] 10.0
maximum space.
LUP14A b NW of ESD PNP devices meeting Rule ESD01b must be enclosed within a P+
diffusion ring (substrate ring for dual well or T3 P-Well Contact T3 triple well.)
LUP14B b Inside edge of P+ diffusion ring of LUP14A must be placed near the 5.0
outer edge of the NW of Rule ESD01b.
LUP14TW b (NW over IBLK) intersecting T3 of ESD triple well PNP device meeting Rule
ESD01b (sized by 5m) must be enclosed within an additional P+ diffusion ring
(substrate ring over dual-well or P-well contact in triple-well).
LUP15A b LUP14A P+ diffusion rings must have a width [m]. 3.0
LUP15B b LUP14A and LUP14TW P+ diffusion rings must have CA to CA spac- 10.0
ing [m].
LUP15TW b LUP14TW P+ diffusion rings must have a width [m]. 0.5

1. This rule does not apply for (RX diffusions not touching PC) with an area < 1.0m2.

Notes:
GR = groundrule in above table
SX = substrate in above table
NW = NWell in above table
Substrate contacts are defined as [(BP intersect RX) touching CA] outside of (NW or BB)
NWell contacts are defined as [(RX intersect NW) touching CA] outside BP
Substrate is defined as the compliment of (NW or BB)
Window shapes are squares of size (2.1*GR 268a) and the windows are stepped across the data in
increments of ((2.1*GR 268a)/2)
N-Type gate is defined as (RX intersect PC) outside (BP or BB) and outside NW
P-Type gate is defined as (RX intersect PC) inside BP and inside NW
N-Type DG gates are defined as N-Type gates inside DG
P-Type DG gates are defined as P-Type gates inside DG
All thin oxide NFET with channel lengths >1.5 X (Rule 1) should NOT be included for checking
All thin oxide PFET with channel lengths >1.5 X (Rule 2) should NOT be included for checking
All thick oxide NFET with channel lengths >1.5 X (Rule DG8a) should NOT be included for checking
All thick oxide PFET with channel lengths >1.5 X (Rule DG8b) should NOT be included for checking
For latchup ratio rules, a gate only fails if it is hit by a failing window
For Rules LUP09a through LUP10b, the ratio is checked as follows:
SX (p-well) area
Ratio = ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Thin-oxide PC Area + [ ( ( LUP 11a ) ( LUP 09a ) ) Thick-oxide PC area ]
In a given tile, the thick oxide gate areas should be weighed by the ratio of LUP11A/LUP09A (i.e. DG gate
area X LUP11A/LUP09A) and the tile used should be the same as that used in LUP9A
In a given tile, the thick oxide gate areas should be weighed by the ratio of LUP11B/LUP09B (i.e. DG gate
area X LUP11B/LUP09B) and the tile used should be the same as that used in LUP9B
In a given tile, the thick oxide gate areas should be weighed by the ratio of LUP12A/LUP10A (i.e. DG gate
area X LUP12A/LUP10A) and the tile used should be the same as that used in LUP10A
In a given tile, the thick oxide gate areas should be weighed by the ratio of LUP12B/LUP10B (i.e. DG gate
area X LUP12B/LUP10B) and the tile used should be the same as that used in LUP10B
For checking time improvement, Nwells with a ratio 10 X (LUP10A or LUP10B or LUP112A or LUP12B)
maybe screened out as passed.
See section , Pad Identification for Latchup Verification Purposes: on page 181.

Pad Identification for Latchup Verification Purposes:

IBM strongly supports using Pad Labeling as defined in Section 3.12.5 , Net Definitions for ESD and
Latchup Verification on page 201. The IODUMMY methodology is not supported.
All pads identified using the net definitions defined in Section 3.12.5 , Net Definitions for ESD and
Latchup Verification on page 201 will be checked for ESD and Latchup rule compliance.

PC
Tile
LUP02 LUP04
2.1 x
GRLUP02
RX
LUP08
LUP06 SX
LUP05 LUP07 BP contact
DG
LUP03
BP
LUP01 2.1 x (GR LUP02)
NW
LUP09A=Total area of SX/Total area of PC

RX CA LUP09B=Total area of SX/Total area of PC
BP
DG
2.1 x
GRLUP02 BP
RX RX
NWell SX
contact contact
2.1 x (GR LUP02)

LUP10A=Total area of NW contact/Total area of PC LUP11A=Total area of SX/Total area of PC
LUP10B=Total area of NW contact/Total area of PC LUP11B=Total area of SX/Total area of PC
Figure 30. Latchup Rule Figure

BP
NW GR
SX GR
DG
RX
RX
NWell
contact
LUP12A=Total area of NWcontact/Total area of PC

LUP13
LUP12B=Total area of NWcontact/Total area of PC
SX GR SX GR
NW NW
RX RX
BP BP
ESDUMMY
LUP15B
LUP14B
LUP15A LUP14A
I/O Pad I/O Pad
Figure 31. Latchup Rule Figure

Layout Rules External Latchup Rules IBM
3.11 External Latchup Rules
JEDEC JESD78 Latchup requirements

Perimeter Images (Perimeter I/Os, wirebond or C4):
Rules ELUP01 to ELUP10B, ELUP01TW, and ELUP01BTW are applicable only inside I/O cell
Note: See Table 60 for ELUP Latchup rules
Area array Images (C4):
Rules ELUP01 to ELUP10B, ELUP01TW, and ELUP01BTW are applicable inside I/O cell and outside I/O
cell
Note: See Table 60 for ELUP Latchup rules
HMM/Cable Plug Latchup requirements

Perimeter or Area array Images
Rules ELUP11 to ELUP23B are applicable inside I/O cell and outside I/O cell.
All JEDEC JESD78 Latchup requirements, included in rules ELUP01 to ELUP10B, will be satisfied by
adhering to the applicable rules ELUP11 to ELUP17B.
Note: See Table 60 for ELUP Latchup Rules.
Table 60. External Latchup Rules

l Min.
a
s
s
ELUP00 b INJECTOR_JEDEC marking layer is required over (RX N+ (RX -

not over BP), RX P+ (RX over BP) over T3) shapes connected to
an I/O pad.
ELUP01 b RX P+ junction (within 0.0 < D 9.6um from an 1.20

INJECTOR_JEDEC shape touching RX N+ (RX not over BP)
shapes connected to an I/O pad) maximum distance to RX
N-well contact.

Layout Rules External Latchup Rules

l Min.
a
s
s
ELUP01B b RX N+ junction (within 0.0 < D 9.6um from an 1.20

shapes connected to an I/O pad) maximum distance to RX sub-
strate contact for dual-well or P-well contact for triple-well.

N-well contact.


N-well contact.


N-well contact.

ELUP05 b RX P+ junction (within 38.4 < D 48um from an 17.60

N-well contact.
ELUP05B b RX N+ junction (within 38.4 < D 48um from an 17.60



l Min.
a
s
s
ELUP06 b RX P+ junction (within 48 < D 57.6um from an 21.20

N-well contact.
ELUP06B b RX N+ junction (within 48 < D 57.6um from an 21.20


N-well contact.


N-well contact.


N-well contact.



l Min.
a
s
s
ELUP10 b RX P+ junction (D > 86.4um from an INJECTOR_JEDEC shape = -

touching RX N+ (RX not over BP) shapes connected to an I/O
pad) maximum distance to RX N-well contact, refer to Rule 268a
for dual-well or T3W268 for triple-well (see Table 24 on
page 115).
ELUP10B b RX N+ junction (D > 86.4um from an INJECTOR_JEDEC shape = -

touching RX N+ (RX not over BP) shapes connected to an I/O
pad) maximum distance to RX substrate contact for dual-well or
P-well contact for triple-well, refer to Rule 268b1for dual-well or
Rule T3W268b for triple-well (see Table 24 on page 115).

INJECTOR_CDE shape) maximum distance to RX N-well Con-
tact.

INJECTOR_CDE shape) maximum distance to RX Substrate
Contact.

tact.

Contact.

tact.

Contact.

tact.

Contact.


l Min.
a
s
s

tact.

Contact.
ELUP16 b RX P+ junction (within 86.4 < D 96um from an 30.00

tact.
ELUP16B b RX N+ junction (within 86.4 < D 96um from an 30.00

Contact.
ELUP17 b RX P+ junction (within D > 96um from an INJECTOR_CDE = -

shape) maximum distance to RX N-well Contact; refer to Rule
268a (see Table 24 on page 115).
ELUP17B b RX N+ junction (within D > 96um from an INJECTOR_CDE = -

shape) maximum distance to RX Substrate Contact; refer to
Rule 268b1 (see Table 24 on page 115).
ELUP20RNR d (NS touching [(RX over RN) connected to a pad]) must be cov- = -
ered by {INJECTOR_JEDEC, INJECTOR_CDE}.
ELUP01TW b RX P+ junction within ((NW over IBLK) intersecting T3) (within 5.00
0.0<D20m from an INJECTOR_JEDEC shape touching RX
P+ (RX over BP) shapes connected to an I/O pad over same T3
shape but not within same (NW over IBLK)) maximum distance
to RX N-well contact.
ELUP01BTW b RX N+ junction within ((NW over IBLK) intersecting T3) (within 5.00
0.0<D20m from an INJECTOR_JEDEC shape touching RX
P+ (RX over BP) shapes connected to an I/O pad over same T3
shape but not within same (NW over IBLK)) maximum distance
to triple-well RX P-well contact.

N+ junction ELUPxxB
I/O Cell
RX BP
INJECTOR_JEDEC or
INJECTOR_CDE SX Contact
D < S
N+ diffusion P+ junction NW Contact

in P-Well
NW
ELUPxx
NWell Guard ring

I/O Pad
Figure 32. External Latchup Rules
Notes:
These DRC rules apply only to n-diffusion (RX not inside a NW or BP) whose RX has a maximum spac-
ing < S to adjacent NW shapes containing p-diffusions (RX inside BP inside NW). These DRC rules also
apply to p-diffusions <S inside (NW shapes that are < S from n-diffusion).
For regular I/O FETs neighboring ((INJECTOR_JEDEC or INJECTOR_CDE) not over T3), S=6.0um.
For 3.3V I/O FETs neighboring ((INJECTOR_JEDEC or INJECTOR_CDE) not over T3), S =8.0um.
For all other diffusions neighboring ((INJECTOR_JEDEC or INJECTOR_CDE) not over T3),
S=2.5um.
For all diffusions neighboring ((INJECTOR_JEDEC or INJECTOR_CDE) over T3), S=20.0um.

If the resistance between the I/O pad and the NFET drivers is < 20 ohms, any N+ junction of ESD diodes
and output driver NFETs connected directly to an I/O pad, should each be enclosed in their own
INJECTOR_JEDEC or INJECTOR_CDE shapes.
If the resistance between the I/O pad and the PFET drivers is < 20 ohms, any P+ junction of triple-well
ESD diodes and output driver PFETs connected directly to an I/O pad, should each be enclosed in their
own INJECTOR_JEDEC or INJECTOR_CDE shapes.
If the resistance between the I/O pad and the NFET drivers is 20 ohms, any N+ junction of ESD diodes
connected directly to an I/O pad, should be enclosed in its own INJECTOR_JEDEC or INJECTOR_CDE
shapes.

Layout Rules ESD Rules IBM
If the resistance between the I/O pad and the PFET drivers is 20 ohms, any P+ junction of triple-well
ESD diodes connected directly to an I/O pad, should be enclosed in its own INJECTOR_JEDEC or
INJECTOR_CDE shapes.
OP resistors < 20 ohms should be treated as a short and any N+ junction or triple-well P+ junction con-
nected to the pad via OP resistors should be enclosed in its INJECTOR_JEDEC or INJECTOR_CDE
shape.
If the OP resistor is 20 ohms, the N+ junction or triple-well P+ junction connected to the pad via the OP
resistors can be ignored.
3.12 ESD Rules
3.12.1 Rule Definitions

I/O pad: DV wire-bond or TD/TV/FV C4 pad (for LM BEOL) or LV C4 pad (for MA or OL with LD
BEOL) including signal and power pads.
I/O signal pad: All I/O pads either labeled FULL_ESD on the xxESD level or not otherwise identified
as LC power or HC power supply pads, where xx = the appropriate alphabetic or
numeric or alphanumeric identifiers supported for pad definition (see Table 6,
Dummy Design Levels and Utility Levels, on page 46).
Low Capacitance (LC) power supply pad:
An I/O pad either labeled LC_POWER_ESD on the xxESD level or electrically con-
nected to a metal and labeled LC_POWER_ESD on the xxESD level, where xx = the
appropriate alphabetic or numeric or alphanumeric identifiers supported for pad defini-
tion (see Table 6, Dummy Design Levels and Utility Levels, on page 46).
High Capacitance (HC) power supply pad:
An I/O pad either labeled HC_POWER_ESD on the xxESD level or electrically con-
nected to a metal and labeled HC_POWER_ESD on the xxESD level, where xx = the
appropriate alphabetic or numeric or alphanumeric identifiers supported for pad defini-
tion (see Table 6, Dummy Design Levels and Utility Levels, on page 46).
Design rule ESD30, presented in Table 61, ESD Rules, on page 191 uses the following syntax:
HBM diode string: A diode-based ESD HBM protection device comprised of two or three p+ n-well
diodes connected in series between an I/O pad and a power supply and an N+ sub-
strate diode connected between an I/O pad and a ground.
HBM NFET: An NFET-based ESD HBM protection device comprised of a grounded gate NFET
with a drain connected to an I/O pad.
HBM double diode: A diode-based ESD HBM protection device comprised of one P+ n-well diode con-
nected between an I/O pad and a power supply and one N+ substrate diode con-
nected between an I/O pad and a ground.
CDM resistor: A P+ polysilicon OP resistor placed in the path between an I/O signal pad and receiver
FET gates.

Layout Rules ESD Rules
3.12.2 Layout Rules
Table 61. ESD Rules

l Min.
a
s
s
ESD0e c LC power supply pads must be connected to: -

One or more (RX n+ diffusions satisfying Rule ESD01a) and
one or more (RX p+ diffusions satisfying Rule ESD01b)
One or more (RX n+ diffusions touching NFET gates, satisfy-
ing Rule ESD01c), or
One or more (RX n+ diffusions touching NFET gates, satisfy-
ing Rule ESD01d), or
One or more (RX n+ diffusions satisfying Rule ESD01a) and
one or more (RX p+ diffusions satisfying Rule ESD01e).
--> Diode based, NFET based or RC-triggered power clamp based
ESD device required.
ESD01 c 1 All I/O (not including power supply pads) pads must be connected to one or more
RX (not covered by BP) or RX (covered by BP inside NW) shapes within
ESDUMMY satisfying (ESD01a and ESD01b) or ESD01c or (ESD01a and
ESD01e).
--> Diode based or NFET based ESD device required.
ESD01a c If none of the diffusion shapes within ESDUMMY identified in ESD01 110
contain an NFET, the pad must be connected to one or more RX (not
covered by BP or NW) shapes within ESDUMMY having a total
perimeter [um].
--> N+/SX or N+/PW diode perimeter.
ESD01aR d If none of the diffusion shapes within ESDUMMY identified in ESD01 125
contain an NFET, the pad must be connected to one or more RX (not
covered by BP or NW) shapes within ESDUMMY having a total
perimeter [um] (On pads where minimum capacitance is not
required, it is strongly recommended to use this groundrule to
meet ESD robustness requirement).
--> N+/SX or N+/PW diode perimeter.
ESD01b c If none of the diffusion shapes within ESDUMMY identified in ESD01 220
contain an NFET, the pad must be connected to one or more RX (cov-
ered by BP inside NW) shapes within ESDUMMY and ESDIODE hav-
ing a total perimeter.
--> P+/NW diode perimeter.

Table 61. ESD Rules

l Min.
a
s
s
ESD01bR d If none of the diffusion shapes within ESDUMMY identified in ESD01 350
ered by BP inside NW) shapes within ESDUMMY and ESDIODE hav-
ing a total perimeter [um] (On pads where minimum capacitance is
not required, it is strongly recommended to use this groundrule
to meet ESD robustness requirement).
--> P+/NW diode perimeter.
ESD01c c 2 If one or more of the diffusion shapes within ESDUMMY identified in 400
ESD01 contain an NFET, the pad must be connected to one or more
RX (not covered by BP or NW) shapes within ESDUMMY where the
gate (PC intersect RX) perimeter [um].
--> NFET width/perimeter.
ESD01cR d 2 If one or more of the diffusion shapes within ESDUMMY identified in 800
ESD01 contain an NFET, the pad must be connected to one or more
RX (not covered by BP or NW) shapes within ESDUMMY where the
gate (PC intersect RX) perimeter [um].
--> NFET width/perimeter.
ESD01d c 3 LC power supply pads must be connected to one or more [(RX n+ dif- 4000
fusions touching NFET gates) within ESD_CLAMP] with a total gate
width.
--> Big NFET gate width of the RX-triggered power clamp.
ESD01e c If none of the diffusion shapes within ESDUMMY identified in ESD01 220
ered by BP inside NW) shapes within (ESDUMMY not over
ESDIODE) and T3 having a total perimeter.
--> P+/NW diode perimeter in T3 isolation well.
ESD01eR d If none of the diffusion shapes within ESDUMMY identified in ESD01 350
ered by BP inside NW) shapes within (ESDUMMY not over
ESDIODE) and T3 having a total perimeter. (On pads where mini-
mum capacitance is not required, it is strongly recommended to
use this groundrule to meet ESD robustness requirement).
--> P+/NW diode perimeter in T3 isolation well.
ESD02a c Rule Deleted.
ESD04 c Rule Deleted.

Table 61. ESD Rules

l Min.
a
s
s
ESD06b c Rule Deleted.
ESD06c c Rule Deleted.
ESD06d c Rule Deleted.
ESD06e c Rule Deleted.
ESD06f c Rule Deleted.
ESD08 c 4,5 {[NW connected to I/O signal pads], [(NW within ESDUMMY) con- 4.40
nected to LC power supply pads]} minimum space to NW, different
net [um].
--> Minimizes current through a parasitic NPN (NW/SX/NW)
during a negative-mode HBM event.
ESD09 c 4,5 {[RX n+ diffusions connected to I/O signal pads], [(RX n+ diffusions 3.50
within ESDUMMY) connected to LC power supply pads]} minimum
space to RX n+ diffusions, different net [um].
--> Minimizes current through parasitic NPN (n+/SX/n+)
during a negative-mode HBM event.
ESD10 c 4,5 {[RX n+ diffusions connected to I/O signal pads], [(RX n+ diffusions 3.50
within ESDUMMY) connected to LC power supply pads]} or {[NW
connected to I/O signal pads], [(NW within ESDUMMY) connected to
LC power supply pads]} minimum space to {NW, different net} or {RX
n+ diffusions, different net} respectively [um].
--> Minimizes current through parasitic NPN (n+/SX/NW) or
(NW/SX/n+) during a negative mode HBM event.
ESD11bR d Rule Deleted.
ESD11dR d Rule Deleted.
ESD11eR d Rule Deleted.
ESD12f c Rule Deleted.

Table 61. ESD Rules

l Min.
a
s
s
ESD12g c Rule Deleted.
ESD13A c 5 NWell Guardring Rule, Refer to GR# LUP13.
ESD13B c 5 Substrate Guardring Rule, Refer to GR# LUP13.
ESD14f c CA within RX within ESDUMMY [um], Refer to GR# 204R. 0.14

--> CA within RX covered by ESDUMMY must follow recommended
rule 204R.
ESD16 c If any resistor connected to an IO pad is < 19 ohms, it is considered a

conductor/short from a checking standpoint for rules ESD01 to
ESD15b. If it is 19 ohms and it is outside ESDUMMY, it is consid-
ered an open for ESD01 to ESD15b. OP resistance values are deter-
mined by OP intersect RX or PC (R=(Rs*L/W) + (2*Rend/W) ignoring
temperature and voltage dependencies; end resistance is included,
see Section 4.18.2 , Resistor Models on page 379 for further
details).
ESD17 c Rules 710, 710R, 711, 711R, 712, 712R, 713, 713R, 735a, 736a,
737, 738, 739aR do not apply if covered by (ESDUMMY or
ESD_CDM).
ESD19aa c Rule Deleted.
ESD19ab c Rule Deleted.
ESD19ac c Rule Deleted.
ESD20 c 2 (OP under (ESDUMMY or ESD_CDM)) to PC. 0.24
ESD21 c (OP under (ESDUMMY or ESD_CDM)) cannot touch BP or NW. -
ESD22 c (OP under (ESDUMMY or ESD_CDM)) must cut RX into two diffu- -
sions.
ESD23 c (OP under (ESDUMMY or ESD_CDM)) width on the source. 0.44
ESD24 c (OP under (ESDUMMY or ESD_CDM)) width on the drain not within 2.00
DG.
ESD24a c (OP under (ESDUMMY or ESD_CDM)) width on the drain within DG. 3.00

Table 61. ESD Rules

l Min.
a
s
s
ESD25 c ((PC over (RX touching OP) under (ESDUMMY or ESD_CDM)) -

expanded by 0.24 um) must touch exactly one (OP=0.44 um under
(ESDUMMY or ESD_CDM)) source and exactly one (OP 2.0 um
under (ESDUMMY or ESD_CDM)) drain.
ESD26 c ((OP under (ESDUMMY or ESD_CDM)) expanded by 0.24 um) -

touches exactly one (PC intersect RX).
ESD30 c 6, 7 All gates connected to an I/O signal pad and an HBM device must be -
connected through a CDM resistor to one or more (RX diffusions
within ESD_CDM).
ESD32bR d Rule Deleted.

1. ESDUMMY is a dummy shape that is placed over the ESD structure.
2. Designs MUST pass rules ESD20 to ESD26 only on NFETs if they are used as HBM or CDM protection devices.
3. ESD_CLAMP is a dummy layer placed over the Big NFET of the ESD RC-triggered power clamp.

4. RX diffusion and NW shapes covered by the same ESDUMMY marker shape are exempt from this rule. NW shapes that are terminals
of the same string diode or anti-parallel diodes are also exempt.
5. This rule does not apply for (RX diffusions not touching PC) with an area < 1.0m2.
6. HBM Device is a term inclusive of the following devices: HBM diode string, HBM double diode, and HBM NFET. These devices are
defined in detail in Section 3.12.1 , Rule Definitions on page 190.
7. RX diffusions within ESD_CDM are the RX portion of the CDM Diodes.
Notes:
The ESDUMMY shapes should be drawn to cover all RX shapes (expanded by 0.5 um) associated with
the ESD design that are connected to the IO pad.
It is recommended to tie both the Source and the Substrate of a transistor to the same ground and not dif-
ferent grounds to stop the formation of a parasitic diode between any two grounds
Rule ESD14f conflicts with Rule 739aR for certain programs when diffused OP resistors are used. In this
case Rule ESD14f takes precedence.
Note that all required guardrings are not included it the figures that follow.
A CDM resistor length of 2.5um will allow a maximum of 40V across the resistor.
For Allowed CDM protection strategies, see Table 62.
See section , Pad Identification for ESD Verification Purposes: on page 196.
ESD HBM diodes with diode finger length < 35m result in a higher on-resistance of the diode and could
lead to lower ESD results.
Pad Identification for ESD Verification Purposes:

IBM strongly supports using Pad Labeling as defined in Section 3.12.5 , Net Definitions for ESD and
Latchup Verification on page 201. The IODUMMY methodology is not supported.
All pads identified using the net definitions defined in Section 3.12.5 , Net Definitions for ESD and
Latchup Verification on page 201 will be checked for ESD and Latchup rule compliance.
Table 62. CDM Protection Strategies
Application CDM Structure Perimeters
Double Diode Diode Strings Thin-oxide Thick-oxide

NFET NFET
Thin-ox gates with 50um Not allowed 100um Not Allowed

50 ohm resistor
Thin-ox gates with 25um 50um 50um Not Allowed

250 ohm resistor

Table 62. CDM Protection Strategies
Application CDM Structure Perimeters
Double Diode Diode Strings Thin-oxide Thick-oxide

NFET NFET
Thick-ox gates with 50um 50um Not Allowed 100um

50 ohm resistor
Thick-ox gates with 25um 25um Not Allowed 50um

250 ohm resistor

3.12.3 ESD Groundrule Figures (Diode Based Protection)
NW NW
ESD08
RX
ESD10
LM/MA/LD PC
LY/E1/OL M2
M1
I/O PAD M1
ESD09
ESD01a
RX
I/O NFET
ESD RX
ESDUMMY
NWell/SX ESD01
or N+/SX diode
ESD
P+/NW
Diode
NW
ESD01b
RX BP
Nwell Contact
Figure 33. ESD Diode Based Protection

3.12.4 ESD Groundrule Figures (MOSFET Based Protection)
NW Guard Ring
LM/MA/LD
M1
LY/E1 M2
/OL
I/O PAD
M1
Resistor
PC
ESDUMMY RX ESD1c
ESD NFET
Figure 34. ESD MOSFET Based Protection

NW Guard RIng
LM/MA/LD OP
LY/E1/OL M2 M1 N+ OP
ESD10
Diffusion
RX Resistor
ESD14f
in I/O
I/O PAD M1 Circuits
M1
ESDUMMY
RX
RX
BP DG
Sx Contact PC
ESD NFET NFET in I/O Circuits

Figure 35. ESD MOSFET Based Protection
ESD23 ESD24
Source Drain
RX
ESDUMMY or
ESD_CDM
OP
ESD20 ESD NFET
PC
Figure 36. ESD NFET

ESD 32b
> 250 ohm

resistance Thin-oxide gate
I /OPad
ESD 32a
HBM Protection CDM Protection
Figure 37. ESD30 when > 250 ohm is used and diode / bipolar based CDM is used
3.12.5 Net Definitions for ESD and Latchup Verification

For cell-level testing, all nets that ultimately will be connected to chip pads should be labelled with one of the
labels defined below. These text labels must be placed on an xxESD level, where xx = M1, M2, and so forth.
For chip level testing, only the FULL_ESD, LC_POWER_ESD or HC_POWER_ESD labels are valid on chip
pads. All pads not identified with any label will be assumed to have the FULL_ESD label and checked as a
signal I/O pad. These chip pad text labels should use LMESD or MAESD or LDESD level and the text should
be placed within the chip pad region (e.g. DV, LV, etc. passivation opening layer). Use of LMESD or MAESD
or LDESD is determined by which Back-End-Of-Line metallization option is being used for the chip design, as
described in Table 11 on page 64 or Table 12 on page 65 or Table 13 on page 66, or Table 14 on page 67 .
LC_POWER_ESD and HC_POWER_ESD labels on xxESD used in cell level checking can also be used to
identify pads as if those pads were labelled with LMESD or MAESD text as described above (i.e. chip pads
connected to metal levels containing these xxESD labels are to be treated as power supply pads).
FULL_ESD - Full checking of all ESD and Latchup layout rules, signal pads with ESD protection.
WIRE_ESD - Used to check metal width, contact and via areas for fat wire like books w/o ESD protection,
pad transfer books. ESD02a-ESD06e values (wires, vias, contacts only checked) are applicable here even if
the metal does not extend to RX.
WIRE_ESD_ENDPT - Used to define a termination point for wide metal checking of cell I/O pads labeled
WIRE_ESD and LC_POWER_WIRE_ESD within a cell.
NO_PROTECT_HBM - Used for internal books without HBM protection but will eventually
go to a pad. All rules except ESD01 - ESD06e apply.

LC_POWER_ESD- Used for power supply pins that DONT achieve 100nF of chip capacitance between the
supply and GND. Below table indicates the groundrules that are applicable.
HBM To be applied under ESDUMMY only

rules
ESD0e ESD01a ESD08 to ESD10
ESD13A to ESD13B/LUP13
ESD14f to ESD15a
ESD01b LUP14a
ESD14f
ESD15b
LUP14b to LUP15b
ESD01c ESD09 to ESD10

ESD13A to ESD13B/LUP13
ESD14f
ESD20 to ESD26
ESD01d
ESD02a
to
ESD06e
HC_POWER_ESD - Used for power supply pins that DO achieve 100nF of chip capacitance between the
supply and GND. Metal rules ESD02a-ESD06e should be followed, similar to WIRE_ESD. Rules
ESD02a-ESD06e are not checked by DRC on pads using this label.
LC_POWER_WIRE_ESD - Used for a power supply net that DOESNT achieve 100nF of chip capacitance
between the supply and GND, and whose HBM protection is provided in another cell that connects to the chip
pad. Metal rules ESD02a-ESD06e and CDM rules ESD30 to ESD40 are applicable.

Layout Rules ESDIODE Layout Rules
WIRE_ESD_ENDPT
LC_POWER_WIRE_ESD
WIRE_ESD
Wide Metal
or
Figure 38. WIRE_ESD_ENDPT Text Label (Example)
3.13 ESDIODE Layout Rules
3.13.1 General
To keep the NW sheet resistance low enough, as well as the parasitic vertical pnp current gain, the blanket
PW implant needs to be blocked from beneath the P+/NW diodes and the NW/PW diodes but not from the
N+/PW diodes. For this purpose, the layer ESDIODE is introduced.
Table 63. ESDIODE Layout Rules

l Min.
a
s
s
BT00 a ESDIODE width. 0.68
BT02 a ESDIODE space. 0.92
BT02R d ESDIODE space. 1.12
BT03a a ESDIODE to (PI expanded by 1.1m) (for BT generation). 0.92
BT03R d ESDIODE to (PI expanded by 1.1m) (for BT generation). 1.12
BT04 b ESDIODE to {BFMOAT, BB}. 0.92
BT04R d ESDIODE to {BFMOAT, BB}. 1.12
BT20 b RX n+ junction to ESDIODE (RX n+ junction touching ESDIODE not 1.0

allowed).
BT21 b RX p+ junction within ESDIODE. 0.5

Layout Rules ESDIODE Layout Rules IBM
Table 63. ESDIODE Layout Rules

l Min.
a
s
s
BT22 a NW within ESDIODE. 0.0
BT23 a ESDIODE to JD (ESDIODE touching JD not allowed) (for BT generation). 3.10
BT24 b ESDIODE to NS. 6.0
BT40 b ESDIODE to adjacent ZEROVT space. 2.0
BT41 b ESDIODE to (PC over RX). 2.0
BT42 c ESDIODE touching {PC, PCFUSE, VAR, DG, DI, (RX touching OP) } not -
allowed.
BT42a c ESDIODE touching {NV, PV, JN, JP, XW, LW, XE, XF } not allowed. -
BT42b c ESDIODE touching {RR, RP} not allowed. -

Layout Rules ESDIODE Layout Rules
PI (expanded by 1.1um ).
Note: Triple Well NW Isolation Ring
may straddle or be exactly
equal to PI (expanded by 1.1um )
BT00
BT04
BFMOAT BT03a
PI
BT40
ZEROVT
BT23 RX
JD
BT41
BT20
PC BT02
BT21
BP
NW ESDIODE
**Note: Draw ESDIODE coincident with NW **
Figure 39. Layout Rules for p+/NW diode (ESDIODE drawn coincident with NW)

Layout Rules Forward-Biased Diode Layout Rules IBM
3.14 Forward-Biased Diode Layout Rules

The general use of forward-biased diodes as circuit elements is not supported. However, bandgap reference
circuits employing forward-biased p-diffusions in a grounded n-well (see section 4.26 , Forward-Biased
Diode Device Models on page 404) are allowed provided they adhere to the design rules below. Each design
that does not follow the design methods and the rules below must be reviewed with the IBM Technical Repre-
sentative.
The level DI is required as a dummy level for forward-biased diodes. ESD diodes must be marked with the
ESDUMMY level. These dummy levels are used for both DRC and LVS verification. Rules for implementing DI
are tabulated below. See Section 3.12 , ESD Rules on page 190 for other ESD diode design rules.
Table 64. DI Layout Rules

l Min.
a
s
s
380 b DI must be within BP. 0.04
380a b (NW touching DI) to JD. 5.00

(((NW touching DI) touching JD) not allowed).
380b1 b (NW touching DI) to BB. 5.00
380c b (NW touching DI) touching PI not allowed. -
380d b (NW touching DI) to {RR, RP}. 2.50

(((NW touching DI) touching {RR, RP}) not allowed).
380g b ((BP touching DI) touching PD) not allowed. -
381 b RX within DI (minimum). 0.10
381b b RX within DI (maximum) . 0.34
382b b RX nWell contact to DI. 0.30
383 b DI must enclose RX. -
384 b DI touching {DG, PC, OP} not allowed. -
384a b (NW touching DI) touching {DG, PC, OP} not allowed. -
385 b RX width - (when RX is within DI). 1.00
385a b 1 (RX not over GRLOGIC) width (maximum) - (when RX is within DI). 2.00
386 b 2 RX minimum length - (when RX is within DI). 2.00
387 b (RX within DI) must be within NW. -
387b b 3 (NW touching DI) to RX substrate contact space - Maximum. 1.00

Layout Rules Forward-Biased Diode Layout Rules
Table 64. DI Layout Rules

l Min.
a
s
s
388 b [ RX nWell contact over (NW touching DI)] to BP. 0.12
389 b [ RX substrate contact over ((NW touching DI) sized by +1.00)] within BP. 0.12
1. The maximum width is limited to minimize current crowding in the structure that affects series resistance. Larger diode width can
be used if the RX p+ anode is covered by a GRLOGIC shape, but these geometries are not represented by the IBM device model.
2. The RX minimum length requirement applies to (RX within DI), for the allowable range of (RX within DI) widths that are specified in Rule
385 as well as Rule 385a. When the (RX within DI) over GRLOGIC width exceeds 2.00m, it is expected that the (RX within DI) length
complies with Rule 386.
3. Rule requires a substrate contact ring to enclose the perimeter of this diode device defined by (NW touching DI) at a spacing that does
not exceed the value specified.

Layout Rules OP Resistor Layout Rules IBM
RX, substrate contact
387b NW
DI, BP
RX
Unit Cell
380
385 RX
381
DI
BP
RX
RX, n-well contact
NW
Figure 40. Forward-Biased Diode Layout Rules (The figure illustrates the layout for p-diffusion in grounded n-well
diodes)
3.15 OP Resistor Layout Rules

The OP mask is used to block the formation of silicide, creating N+ diffusion and P+ poly resistors. Below are
the rules used to form the OP diffusion and poly resistor.

Layout Rules OP Resistor Layout Rules
Table 65. OP Resistor Layout Rules

l Min.
a
s
s
710 b 1 Diffusion resistor length (OP intersect RX). 0.44 0.4400 0.100
710R d 1,2 Diffusion resistor length (OP intersect RX). 1.60 1.6000 0.100
711 b 1 Diffusion resistor width (OP intersect RX). 0.20 0.1900 0.040
711R d 1,2 Diffusion resistor width (OP intersect RX). 1.50 1.4900 0.040
712 b 1 Poly resistor length (OP intersect PC). 0.80 0.8000 0.100
712R d 1,2 Poly resistor length (OP intersect PC). 1.60 1.6000 0.100
713 b 1 Poly resistor width (OP intersect PC). 0.20 0.1790 0.02
713R d 1,2 Poly resistor width (OP intersect PC). 1.50 1.4790 0.02
716a b (RX touching OP) must not touch NW. - - -
716b b (RX touching OP) must not touch BB (straddling not - - -

allowed).
716d b (OP intersect RX) must not touch BP. - - -
716e b (OP intersect PC) must touch BP. - - -
717a c ((PC intersect OP) covered by GRLOGIC) to (NW cov- 0.52 0.5200 0.15
ered by GRLOGIC) space (for BH generation).
717a1 c ((PC intersect OP) not over GRLOGIC) to (NW not over 0.63 0.6300 0.148
GRLOGIC) space (for BH generation).
717b c (PC intersect OP) within NW (for PH generation). 0.52 0.5200 0.15
717bf c (PC touching (OP over BP)) within BFMOAT. 3.200 - -
717c c (PC intersect OP) to (PC intersect OP) space (for 0.64 0.6400 0.10
PH,BH generation).
725 a OP width. 0.40 0.4000 0.100
726 a OP to OP space. 0.40 0.4000 0.100
727 b OP overlap past RX. 0.18 0.2025 0.114
728 b OP to RX. 0.16 0.1825 0.114
729a a OP area. 0.37 - -


l Min.
a
s
s
729b a OP enclosed area. 0.37 - -
730 b OP overlap past PC. 0.20 0.2105 0.127
731 b OP to PC (shapes can not abut). 0.24 0.2505 0.127
732 b CA over OP is not allowed. - - -
733 b (CA over (RX or PC)) to adjacent (OP intersect (RX or 0.20 0.200 0.140
PC)).
733R d (CA over (RX or PC)) to adjacent (OP intersect (RX or 0.20 0.200 0.140
PC)).
734a b (RX over OP) to {NV, PV, JN, JP, XW, LW, XF}. ((RX 0.26 - -
over OP) touching {NV, PV, JN, JP, XW, LW, XF} is
prohibited).
734b b 1 (RX touching OP) to BP. 0.20 0.2050 0.095
734c b (RX touching OP) to BB (see also rule CP265b). 0.42 - -
735a b 1,3 (( PC touching OP) must be within BP. 0.25 0.2605 0.11
736 c OP over (PC intersect RX) not allowed. - - -

4
736a c RX(touching OP) must not touch PC.
736a1 c RX(touching OP, not touching PC) touching SBLK not allowed.
736a2 c PC(touching OP) touching SBLK not allowed.
736a3 b SBLK must touch OP. - - -
737 c 1 OP touching DG not allowed. - - -
737b c 5
((PC touching OP) not touching GRLOGIC) touching - - -
DG - not allowed.
738 c 1 (OP intersect (RX or PC)) must be rectangular - - -
738b c OP over RX must divide the RX into two separate diffu- - - -

sions;
OP over PC must divide the PC into two separate poly
regions.
739a c RX overlap past OP. 0.45 0.4450 0.11
739aR d 1 RX overlap past OP. 0.50 0.4550 0.11

Layout Rules OP Resistor Layout Rules

l Min.
a
s
s
739b c PC overlap past OP. 0.42 0.4095 0.13
739bR d PC overlap past OP. 0.45 0.4495 0.13
OP9aR d 6 (OP over RR) overlap of PD. 0.360 0.5160 0.147
OP20a c OP to RN. 0.60 - -
OP24 c OP touching RX(over RN) not allowed.
OP24a c OP touching (RX touching PD) not allowed.
OP30R d (((PC over OP) over NW) not over GRLOGIC) to RX. 0.320 - -
OP31R d (((PC over RX) over NW) not over GRLOGIC) to {differ- 0.320 - -
ence [intersection (OP, PC), (RX sized by +0.20)] sized
by +0.12}.
4
PBR19 c No more than 1 set of contacts allowed on any resistor (no center-tapping
allowed!)(only1 OP allowed per resistor > no center tapping of resistor body).
1. Approved IBM ESD structures covered by (ESDUMMY or ESD_CDM) are exempt from this rule. See also ESD specific rules
Section 3.12 , ESD Rules on page 190.
2. For details on the OP recommended rules, see Section 4.18 , Resistor Models on page 378
3. For OP RR Resistor, See Rule RR10 in Table 66, RR Rules, on page 213.
4. Approved IBM ESD structures covered by (ESDUMMY or ESD_CDM) or ((OP intersect RX) touching SBLK) are exempt from this rule.
See SBLK in Table 6 on page 46. See Section 7.0 , Electrostatic Discharge (ESD) on page 523.
5. The intent of this rule is to when Rule 737 ((OP touching DG) not allowed) is nullified in DRC for IBM ESD structures covered by
(ESDUMMY or ESD_CDM) that P+ poly resistors (PC touching OP) still can not touch DG for model-to-hardware correlation integrity.
6. See Rule RR9a in Table 66, RR Rules, on page 213 for the actual Rule to be checked in DRC.

725
OP 727
RX
CA 733 711 733 CA
710
739a
CA CA
738
728 731
RX PC
Figure 41. Layout for OP N+ Diffusion Resistor
725
OP 730
PC
CA 733 713 733 CA
735a
712
739b
CA CA
738
BP
728 731
RX PC
Figure 42. Layout for OP P+ Polysilicon Resistor

Layout Rules OP RR Resistor (RR and PD) Layout Rules
3.16 OP RR Resistor (RR and PD) Layout Rules

Table 66. RR Rules

l Min. Dim.
a
s
s
RR1 a RR width. 0.800 0.800 0.105
RR2 a RR space. 0.800 0.800 0.105
RR3 c RR must be orthogonal.
RR4a b (PC touching OP) within RR. 0.260 0.2705 0.157
RR5 b RR to adj PC. 0.280 0.2905 0.157
RR7 b RR to adj RX (RX touching RR not allowed). 0.280 0.2850 0.146
RR8 b BP within RR. 0.000 0.0000 0.172
RR9 b ((BP touching RR) can not touch (PC not touching RR)).
RR9a b (OP touching RR) overlap of PD. 0.360 0.5160 0.147
RR10 c 1 ((PC touching OP) over RR) must be within BP. 0.400 0.4105 0.111
RR10a c (PC not touching OP) can not touch RR.
RR11 b (CA over RR) must be covered by PD.
RR14 c RR touching {DG, NV, PV, JN, JP, XE, XF, XW, LW} not allowed.
RR15 b ((PC touching OP) touching RR) width (minimum). 0.740 0.719 0.02
1. GR RR10 supersedes Design Min in Rule 735a (see Table 65, OP Resistor Layout Rules, on page 209) for the OP RR Resistor.
Table 67. PD Rules

l Min. Dim.
a
s
s
PD1 a 1 PD width. 0.340 0.3400 0.075
PD2s a 1 PD space. 0.340 0.0680 0.085
PD3 b PDHOLE width (where PDHOLE is a PD enclosed 1.00 - -

area for SBD anode).

Layout Rules OP RR Resistor (RR and PD) Layout Rules IBM
Table 67. PD Rules

l Min. Dim.
a
s
s
PD4 b PD to RX (shapes cannot abut) 0.360 0.365 0.095

(PD cannot touch (RX not over SCHKY)).
PD5 b (RX intersect PD) width (for SBD guardring, width 0.560 - -
checked in orthogonal directions only).
PD6a b PD overlap past RX (SBD guardring). 0.360 - -
PD7 b PD overlap past PC. 0.280 0.2905 0.111
PD9 c PD must be orthogonal.
PD10a b PD to adj PC (abutting not allowed). 0.280 0.2905 0.111
PD11 a PD enclosed area (m2) (min resist island). 0.320 - -
PD14 b ((CA touching SCHKY) not over RN) must be within 0.280 - -
PD.
PD14a b (CA touching RN) within RX. 0.140 - -
PD14b b (CA touching PD) within RX. 0.120 - -
PD15 b PD must be within {(BP intersect RR),(BB intersect 0.000 - -

SCHKY)}.
PD15a b {PD, BP} within BFMOAT. 2.950 - -
PD16a1 c PD to {BP, BB}. 0.240 - -
PD21a b (PD touching SCHKY) cannot touch (PC or (RX not touching PD)).
PD21b a (PD touching RX) must be covered by SCHKY.
PD22a a ((RX touching PD) cannot touch BP (drawn BP not generated).

1. PD is not a mask level, it is a design level used for Data Preparation. PD is merged onto the BN mask. See Mask Level BN, Design
Level PD in Table 2, Mask and Design Level Definitions on page 27 and Mask Level BN in Table 8, Shape Manipulation Prior
to Mask Write on page 59. PD min width and space specified in this table is larger than BN minimum width and space for the
technology by design. However, the technology minimum BN limits are specified in GR 358d and 358e in Table 31, BP Layout
Rules on page 128.

Layout Rules OP RP Resistor (Precision Resistor) Layout Rules
RR/BP/BFMOAT
RR10 PD15, PD15a, RR8
High Resistance Region
PD PD7 PD
RR1 OP
PC
CA RR9a CA PD1
CA CA
RR15
PD2s
PD4 PD10a
RR7 RR5
RX PC
Figure 43. OP RR Resistor (RR and PD) Layout Rules
3.17 OP RP Resistor (Precision Resistor) Layout Rules
Table 68. RP Rules

l Min. Dim.
a
s
s
RP1 a RP width. 0.800 0.800 0.105
RP2 a RP space. 0.800 0.800 0.105
RP2b b RP to RR (RP touching RR not allowed). 0.800 0.800 0.105
RP3 b RP must be orthogonal.
RP4a b (PC touching OP) within RP. 0.400 0.4105 0.157

Layout Rules OP RP Resistor (Precision Resistor) Layout Rules IBM
Table 68. RP Rules

l Min. Dim.
a
s
s
RP5 b RP to PC. 0.280 0.2905 0.157
RP7 b RP to RX (RX touching RP not allowed). 0.280 0.2850 0.146
RP8 b BP within RP. 0.000 0.0000 0.172
RP9 b ((BP touching RP) must not touch (PC not touching RP)).
RP10 b 1 ((PC touching OP) over RP) must be within BP. 0.400 0.4105 0.111
RP10a c (PC not touching OP) must not touch RP.
RP12 c RP touching PD not allowed.
RP14 c RP touching {NV, PV, JN, JP, XE, XF, XW, LW} not allowed.
RP14a a RP to {DG, VAR} (RP touching {DG, VAR} not 0.400 - -

allowed) (for PH generation).
RP14b a RP to {difference [intersection (OP, PC), (RX sized by 0.400 - -

+0.20)] sized by +0.12} (for PH generation).
RP15 b ((PC touching OP) touching RP) width (minimum). 0.740 0.719 0.02
RP16 a RP within NW (for PH generation). 0.400 0.400 0.174

1. GR RP10 supersedes Design Min in Rule 735a (see Table 65, OP Resistor Layout Rules, on page 209) for the OP RP Resistor.

Layout Rules N-well Resistor Layout Rules
RP16 NW (optional)
RP
RP8
RP4a
BP RP10
RP1 OP
PC
CA CA
CA CA
RP15
RP5 RP10
RP2 RP2b RP7
RP RR PC RX PD
Figure 44. OP RP Resistor Layout Rules
3.18 N-well Resistor Layout Rules
Table 69. N-well Resistor Layout Rules

l Min.
a
s
s
NWR01 a RX over NW_RES exact width. 0.80
NWR02 b 1 RX over NW_RES minimum length. 1.20
NWR03 a 1 [(Least enclosed rectangle of RX) over NW_RES] within NW (exact 0.90
value).
NWR04 a (RX over NW_RES) minimum space. 3.00
NWR04R d (RX over NW_RES) minimum space. 10.00

Layout Rules N-well Resistor Layout Rules IBM
Table 69. N-well Resistor Layout Rules

l Min.
a
s
s
NWR05 a 2 [(Least enclosed rectangle of CA) over NW_RES] within RX (exact 0.12
value).
NWR06 a NW_RES must be within RXEXCLUD. 0.00
NWR06a b 3 RXEXCLUD overlap past NW_RES. 0.10
NWR07 c NW_RES must be an orthogonal rectangle.
NWR08 b NW within NW_RES (exact value). 0.00
NWR09 a Only two RX shapes over NW_RES are permitted.
NWR10 c {LW, XW, PV, NV, JN, JP, DG, PC, XE, XF, BP, PD, RR, RP, OP, ZEROVT,
VAR, DI, SBLK} touching NW_RES is prohibited.
NWR10a c PI to NW_RES (PI touching NW_RES is prohibited). 3.10
NWR10b c {BFMOAT, ESDIODE} to NW_RES ({BFMOAT, ESDIODE} touching 2.00

NW_RES is prohibited).
4
NWR10c c ({VNCAP, QY} covered by NW) touching NW_RES is prohibited.
1. Rule NWR02 + 2 x Rule NWR03 defines the NW resistor minimum width ( 3.00m).
2. Assumes two rows of CAs are present for each N-well resistor device RX contact.
3. Intent of this rule is limit how far the edges of a RXEXCLUD shape should be placed beyond the perimeter of a N-well resistor. For
additional information, see Rule 40 in Table 21 on page 95.
4. Intent of this rule is to prevent N-well resistor being part of the NW ground plane of either the VNCAP or MIM devices, and to prevent
RXEXCLUD placement over the VNCAP or MIM N-well groundplanes. VNCAP or MIM layout, without its N-well groundplane, being
placed over typical Front-End-Of-Line devices, including the N-well resistor, is not restricted.

Layout Rules Silicided Polysilicon Resistor
NWR09
NWR01 NW NWR03
RX RX
NWR08
CA CA CA CA
NWR05
NWR04 NWR02
CA CA CA CA
CA CA CA CA NWR06a
NWR03 NWR03
NWR10a NWR10b NWR10b

NW_RES (NWR07)
PI BFMOAT ESDIODE RXEXCLUD (NWR06)
Figure 45. N-well Resistor Design Rules
3.19 Silicided Polysilicon Resistor

CMOS8RF offers a low value and scalable resistor in the form of a silicided P+ poly line resistor . The dummy
design level SILPCRES is used to identify the silicide-blocked resistors. The SILPCRES design level is also
used in data preparation to generate the BH block level and suppress PH openings when placed over an
N-well, P-well, or T3 isolated P-well.
Table 70. Silicided Polysilicon Resistor Design Rules

l Min. Dim.
a
s
s
PCR11 a (PC over SILPCRES) minimum width. 0.34
PCR11a c (PC over SILPCRES) maximum width. 20.0
PCR11b a SILPCRES minimum width. 0.40

Layout Rules Silicided Polysilicon Resistor IBM
Table 70. Silicided Polysilicon Resistor Design Rules

l Min. Dim.
a
s
s
PCR12 a SILPCRES minimum space. 0.40
(PC over SILPCRES) minimum resistor length between

PCR13b b 1.00
two inner rows of CA contacts.
PCR14 c (PC over SILPCRES) must be an orthogonal rectangle.
PCR15 c SILPCRES must be an orthogonal rectangle.
SILPCRES minimum space to (DG, EFUSE, VAR,

PCR16 a ZEROVT) with touching prohibited. (Note: This is for BH, 0.40
PH derivation).
SILPCRES minimum space to [(PC touching OP), RP,

PCR16a a gate] with touching prohibited. (Note: This is for BH, PH 0.56
derivation).
SILPCRES minimum space to RX with touching prohib-

PCR16c b 0.36
ited.
SILPCRES minimum space to OP with touching prohib-

PCR16d b 0.50
ited.
SILPCRES minimum space to (NW not T3) (Note: This

PCR16f a 0.45
is for BH, PH derivation).
PCR16g b SILPCRES touching (RR, LW, JN, JP, XE, XF, SBLK, IND) is prohibited.
PCR20a a SILPCRES must touch PC.
SILPCRES within (NW not T3) (Note: This is for PH der-

PCR23 a 0.40
ivation).
PCR505aR d (CA touching SILPCRES) must be within M1. 0.08
PCR735a b (PC touching SILPCRES) must be within BP. 0.24

Layout Rules Silicided Polysilicon Resistor
Figure 46. Silicided Polysilicon Resistor Design Rules
PCR11bR
PCR11
PCR11a PCR209 PCR209
CA CA PCR13b CA CA
M1 M1
CA CA CA CA
PCR505a
CA CA CA CA
PCR505aR PCR209
PCR209
PCR505aR PCR505aR
PC
PCR735a
SILPCRES, BP PCR735a
PCR22
PCR16f PCR12
PCR23
NW not N3
SILPCRES
BP
PC

Layout Rules Back-End-Of Line Resistor Layout Rules IBM
3.20 Back-End-Of Line Resistor Layout Rules
3.20.1 L1 Resistor Layout Rules

Below are the rules used to form the L1 resistor between the E1 and MA design levels. For the model see
Section 4.18 , Resistor Models on page 378.
MA MA MA Note: L1, between the

E1 and MA design levels,
is only permitted.
F1BAR
F1BAR F1BAR
L1 Resistor
E1 E1
Figure 47. Cross Section of the BEOL Resistor (L1) structure.
E1
L16 (typ 2 sides)

(both ends of L1) L14
L13
L12
L11 L1 L12a L1
L11a
F1BAR F1BAR
MA MA F1BAR MA
Figure 48. Layout for BEOL (L1) Layout
Table 71. L1 RESISTOR Layout Rules
Rule C Notes Description Des Wafe Tol.

l Min r
a
s
s
L11 a L1 width minimum. 5.000 5.000 0.200
L11a c L1 width maximum. 30.00 - -

Layout Rules Back-End-Of Line Resistor Layout Rules
Table 71. L1 RESISTOR Layout Rules
Rule C Notes Description Des Wafe Tol.

l Min r
a
s
s
L12 b F1BAR within L1. 1.000 - -
L12b a F1 must not touch L1 (Note: F1BAR is used to connect L1 to MA).
L13 a L1 space. 5.500 - -
L13a b 1 (L1 not over L1TEMP25) to (L1 not over L1TEMP25) 45.0 - -
space.
L13b b 1 (L1 over L1TEMP25) to (L1 not over L1TEMP25) space. 45.0 - -
L14 b L1 to E1 space. L1 touching E1 not allowed. 2.000 1.875 0.334
L15 c No more than 1 set of contacts allowed on L1 resistor (no center-tapping allowed).
L16 b 1 MA overlap past L1 resistor end must be 0.00. = - - -

L17 b L1 minimum length (F1BAR to F1BAR space). 8.000 - -
L18 c L1 shapes must be rectangular. 45o L1 shapes not allowed.
L19 c 1 ((L1 expanded by +45m per edge) not over L1TEMP25) = - - -

intersect {E1,LY, MG, MQ, Mx (x=1,2,3,4)} not allowed.
L19a c 1 ((L1 expanded by +45m per edge) not over L1TEMP25) = - - -

intersect (MA not touching (L1 intersect F1BAR)) not
allowed.
L19b c 1 L1TEMP25 not touching L1 not allowed. = - - -
L19c c 1 L1TEMP25 must be covered by (L1 expanded = - - -

+45m/edge).
1. For additional information on these layout rules, see Reliability section , Back-End-Of-Line L1 Resistor: on page 486 or
L1TEMP25 in Table 6, Dummy Design Levels and Utility Levels, on page 46.
3.20.2 Kx (x=2,3,4,5,6) Resistor Layout Rules

Below are the rules used to form the Kx resistor between the last Mx thin copper metal level and the MQ
design level, which is the first thick copper design level. For the model see Section 4.18 , Resistor Models
on page 378.

MQ MQ MQ Note: Only one level of Kx

resistor allowed in any one
design.
VL
VL VL
Kx Resistor
Mx Mx
Figure 49. Cross Section of the BEOL Kx Resistor (x = 2,3,4,5 or 6) structure.
M2
KX4
KX2
KX1 K2 Kx
KX1a
KX7 KX3
VL VL
MQ MQ VL MQ
Figure 50. Sample layout for BEOL K2 Resistor. In the figure, K2 may be replaced by Kx, and M2 may be replaced by Mx,
where x = 2,3,4,5, or 6 for the other layout options.
Table 72. Kx (x=2,3,4,5,6,) Resistor Layout Rules
Rule C Notes Description Des Wafer Tol.

l Min
a
s
s
KX1 a Kx width minimum, where x=2,3,4,5 or 6. 5.00 5.00 0.14
KX1a c Kx width maximum, where x=2,3,4,5 or 6. 75.00 - -
KX1aR d Kx width maximum, where x=2,3,4,5 or 6. 30.00 - -
KX2 a Kx space, where x=2,3,4,5 or 6. 5.50 5.50 0.14
KX3 b VL within Kx, where x=2,3,4,5 or 6. 0.50 0.4916 0.326

1
KX3a b VLBAR over Kx not allowed, where x=2,3,4,5 or 6.

Layout Rules Back-End-Of Line Resistor Layout Rules

l Min
a
s
s
KX4 b Kx to Mx space. (Kx touching Mx not allowed), where 1.00 0.990 0.309
x=2,3,4,5 or 6.
KX5 c No more than 1 set of VL vias allowed on Kx resistor (no center-tapping allowed).
KX7 c Kx minimum length (measured as VL space), where 5.00 - -

x=2,3,4,5 or 6.
KX8 c Kx shapes must be rectangular. 45 degree Kx shapes not allowed, where x=2,3,4,5
or 6.
KX9 b Kx to {BONDPAD, QY, QT} space. (Kx touching {QY, 5.00 - -

BONDPAD, QT} not allowed), where x=2,3,4,5 or 6.
KX13 a Only 1 Kx level may be used in a chip design, where x=2,3,4,5 or 6.
The following series of statements are provided as reference information to assist

with interpretation of this rule. Rule checking methodology may vary depending on
checking tool capabilities.
Kx (where x= 3,4,5,6) can not touch (CHIPEDGE touching K2)

Or
(If K2 is used, VL not touching M2 (where M2 will always be present) vias must touch
K2 (see Rule 623a), and Kx can not be present within CHIPEDGE, where x= 3,4,5 or
6)
(If K3 is used, VL vias not touching M3 (if M3 is present) must touch K3 (see Rule
623a), and Kx can not be present within CHIPEDGE, where x= 2,4,5 or 6).
623a), and Kx can not be present within CHIPEDGE, where x= 2, 3, 5 or 6).
623a), and Kx can not be present within CHIPEDGE, where x= 2, 3,4, or 6).
(If K6 is used, VL vias not touching M6 (if M6 is used) must touch K6 (see Rule
623a), and Kx can not be present within CHIPEDGE, where x= 2,3,4,or 5).
2
KX13a a L1 can not touch (CHIPEDGE touching Kx); where x = 2,3,4,5,6.


l Min
a
s
s
3
KX14 b (TRANSMIS touching M3TRANS) touching K3 not allowed; for 5LM LM BEOL
option. (TRANSMIS touching M4TRANS) touching K4 not allowed; for 6LM LM
BEOL option. (TRANSMIS touching M5TRANS) touching K5 not allowed; for 7LM
LM BEOL option. (TRANSMIS touching M6TRANS) touching K6 not allowed; for
8LM LM BEOL option. (TRANSMIS touching M4TRANS) touching K4 not allowed;
for 7LM LM BEOL option. (TRANSMIS touching M5TRANS) touching K5 not
allowed; for 8LM LM BEOL option.
(TRANSMIS touching M2TRANS) touching K2 not allowed; for 6LM MA BEOL

option. (TRANSMIS touching M3TRANS) touching K3 not allowed; for 7LM MA
BEOL option. (TRANSMIS touching M2TRANS) touching K2 not allowed; for 7LM
MA BEOL option. (TRANSMIS touching M3TRANS) touching K3 not allowed; for
8LM MA BEOL option. (TRANSMIS touching M4TRANS) touching K4 not allowed;
for 8LM MA BEOL option.
(TRANSMIS touching M2TRANS) touching K2 not allowed; for 5LM OL/LD BEOL
option. (TRANSMIS touching M3TRANS) touching K3 not allowed; for 6LM OL/LD
BEOL option. (TRANSMIS touching M4TRANS) touching K4 not allowed; for 7 or
8LM OL/LD BEOL option.
(TRANSMIS touching M5TRANS) touching K5 not allowed; for 8LM OL/LD BEOL
option.
1. Rule may be omitted from DRC if it is verified by existing Rule 558c as well as Rules IND11a, IND11b.
2. See Table 1, Optional Features with Feature Part numbers, on page 11. L1 and Kx can not be used in the same chip design. Features
is setup as select one.
3. See Table 11, LM last metal Back End Of Line (BEOL) Metallization Options, on page 64 or Table 12, MA last metal Back End Of
Line (BEOL) Metallization Options, on page 65 or Table 13, OL with LD last metal Back End Of Line (BEOL) Metallization Options,
on page 66. Rule is to prevent Kx resistor body from straddling a transmission line device, only when a transmission line device, from
a BEOL cross-sectional perspective, passes through the mask level where a Kx resistor could also be placed. For example, in a five
level-of-metal (5LM) LM BEOL stack (M1, M2, M3, MQ, LM) a ( LM over MQ ) singlewire transmission line may have a K3 resistor
body below or straddling the MQ groundplane of the singlewire device, since the singlewire device TRANSMIS level would not touch
a M3TRANS dummy design level. However, for a (LM over M1) singlewire device, can not have a K3 resistor body touching or
straddling the TRANSMIS dummy design level, since TRANSMIS will touch a M3TRANS dummy design level.

Layout Rules Barrier Diode Rules (RN, NS, & BB)
3.21 Barrier Diode Rules (RN, NS, & BB)
3.21.1 RN Rules
Table 73. RN Layout Rules (Reachthrough N+)
l Min. Dim.
a
s
s
RN1 a RN width. 0.680
RN2 a RN space (diffusion to diffusion). 0.920
RN2a a RN notch (same potential). 0.700
RN3 b RN to adjacent RX. 0.360
RN3a b RN touching more than one RX shape not allowed.
RN4 b RX within RN. 0.200
RN4a b RN must touch RX.
RN9 a RN enclosed area, m2 (for minimum resist island). 0.537 - -
RN10 b (RN over RX) must not touch {PD, BN(generated)}.
RN11 b RN must be within NS. 0.000 - -
RN12 a RN to NW (for RN copy to NW in dataprep). 0.920 - -
RN12a a RN not touching {RX, BB, NS} not allowed (This rule means that each RN must touch
one or more of the listed shapes.
RN13 a RN union NW width (for RN copy to NW in dataprep). 0.680 - -
RN14 a RN union NW notch (for RN copy to NW in dataprep). 0.920 - -
3.21.2 NS Rules
NS is the subcollector for the Schottky Barrier Diode.
Table 74. NS (N+ Subcollector) Layout Rules

l Min. Dim.
a
s
s
NS1 a NS width (with lateral diffusion the wafer dimension = 4.1). 3.200
NS2 a NS to NS space (Rule BB2 only allow NS space to be 6.2 m 3.680
or greater).
NS4b1 c NS touching NW not allowed.
NS5 b NS to adjacent NW. 3.680 - -

Layout Rules Barrier Diode Rules (RN, NS, & BB) IBM
Table 74. NS (N+ Subcollector) Layout Rules
l Min. Dim.
a
s
s
NS5R d NS to adjacent NW. 4.600 - -
NS9 b NS must be covered by BB.
NS9a b NS must be within BB. 2.100 - -
NS10a c NS to adjacent BB. 5.200 - -
NS15a b More than one (RX union NS) within a common BB shape not allowed.
NS16 c Every NS AC ground plane bed must be electrically contacted (no floating NS
allowed) (use RX (touching RN, touching BB) contacts to NS beds). Each NS must
have one RX (over RN) contact to it.
NS21b1 b 1 NS to (RX touching {PD, BP}) (NS cannot touch (RX touching 2.760
{(PD not over SCHKY), BP}).
2
NS26 c NS must touch PDHOLE (where PDHOLE is a PD enclosed area for SBD anode).
NS30 a NS must be covered by SCHKY.
1. BP is drawn BP, not generated BP.
2. Schottky Barrier Diode (SBD) is defined as union(NS,BB, RN))covered by SCHKY.

Layout Rules Barrier Diode Rules (RN, NS, & BB)
3.21.3 BB Rules
Table 75. BB Layout Rules
l Min. Dim.
a
s
s
BB1 a BB width. 2.760 - -
BB2 a BB to BB space. 2.00 - -
BB6 a BB area (m2 ) (for minimum resist island). 9.600 - -
BB6a1 b SCHKY must be within BB. 0.000 - -
BB7 a BB enclosed area (m2). 4.000 - -
BB32 c BB to NW. 1.760 - -
BB34a1 b BB touching NW not allowed.
BB34a2 b BB touching more than 1 union(NS, RN) not allowed.
BB35 b BB to BP (BB touching BP not allowed). 0.400 - -
BB38a c (RX touching BB) must touch NS.
BB42 c Rule deleted, check consolidated into BB51.
BB50 c {ESDUMMY, ESD_CDM, ESD_CLAMP, ESDIODE,ESD_STACK} touching BB not
allowed.
BB51 c {LW,DG,XW,PC,RR,RP, NV, PV, JN, JP} touching BB not allowed.
BB53 a {IND, IND_FILT, ZEROVT} to BB ({IND, IND_FILT, ZEROVT} 2.000
touching BB not allowed) (for BF,BT generation).
BB55 a VAR to BB (VAR touching BB not allowed) (for BH genera- 0.400
tion).
PBN12 c PC to BB (abutting or straddling not allowed). 0.520
3.21.4 SCHKY Rules

Table 76. SCHKY Layout Rules
l Min. Dim.
a
s
s
SCH01 a OP touching SCHKY not allowed.

Layout Rules BFMOAT Design Rules IBM
3.22 BFMOAT Design Rules

The BFMOAT level may be used to layout a ring of resistive substrate area that is useful in reducing the cou-
pling of substrate noise between regions on the same chip. Section 4.33 , Noise on page 431 provides the
amount of resistance given for various moat lengths (BFMOAT width). Section Q.1, xxFILL and xxHOLE
Generation on page 549 provides BFMOAT pattern file rules.
Table 77. BFMOAT Design Rules

Rule l Min. Dim.
a
s
s
790 c BFMOAT not touching (PC touching (OP over BP)) width. 10.00 - -
790a c BFMOAT touching (PC touching (OP over BP)) width. 1.00 - -
792 c BFMOAT not touching (PC touching (OP over BP)) space. 10.00 - -
792b c BFMOAT touching (PC touching (OP over BP)) space. 2.00 - -
793 c BFMOAT to adjacent NW space. 2.00 - -
795 c BFMOAT to adjacent RX space. 1.00 - -
796 c BFMOAT to adjacent ZEROVT space. 2.00 - -
797 c BFMOAT to (PC over RX). 3.00 - -
797b c BFMOAT to (PC touching (OP over BP)) (outside of 3.50 - -

BFMOAT).
797c c BFMOAT to BB (BFMOAT touching BB not allowed). 2.00 - -
798 c {PC, RX, OP, RR, PD, RP} straddling BFMOAT not allowed.
799 b BFMOAT touching {RX, NW, PI, XW, LW, NV, PV, JN, JP, NS, RN, XE, XF, DG, JD,
DI, VAR, ESDIODE, PCFUSE, EFUSE, ({PC,RR, PD, RP} not touching OP)} not
allowed.
799a b (CA touching BFMOAT) must be covered by ((PC touching = - - -

OP) over BP).
3.23 DG Layout Rules

For IO circuits and peripheral circuits, see Section 3.10 , Latchup Rules on page 176.

Layout Rules DG Layout Rules
Table 78. DG Layout Rules

l Min. Dim.
a
s
s
DG1 c DG must be orthogonal. - - -
DG1b c NW touching DG must be orthogonal. - - -
DG1c c Intersection(DG,NW) touching VAR must be - - -

orthogonal.
DG2R d (PC over RX) touching DG must be orthogonal. - - -
DG3 b (PC vertices touching DG) to RX space. 0.08 0.0955 0.064
DG4 b (PC over RX) within DG. 0.50 0.4424 0.132
DG5 b (PC over RX) to DG. 0.50 0.4424 0.132
DG6 a 1 DG width. 0.40 0.4000 0.122
DG7 a DG space and notch. 0.40 0.4000 0.122
DG8a b 2 [(PC over RX) over DG] width for NFET device 0.24 0.2200 0.034
Leff.
DG8a45 b [(PC over RX) over DG] width for 45 NFET 0.26 0.2400 0.034
device Leff.
DG8b b 2 [(PC over RX) over DG] width for PFET device 0.24 0.2140 0.034
Leff.
DG8b45 b [(PC over RX) over DG] width for 45 PFET 0.26 0.2340 0.034
device Leff.
DG8c b (((PC to PC) over RX) over DG) - spacer to 0.30 0.1847 0.026
spacer.
DG8cR d (PC touching DG) minimum space to adjacent 0.30 - -

PC.
DG9 a DG overlap past NW (for DE level derivation) . 0.40 - -
DG10 c 3 DG to (NV over RX) space; 0.50 - -

DG to (PV over RX) space;
DG to (XW over RX) space;
DG to (LW over RX) space.

Layout Rules DG Layout Rules IBM
Table 78. DG Layout Rules

l Min. Dim.
a
s
s
DG10b c 3 DG touching (NV over RX) is Not Allowed; - - -
DG touching (PV over RX) is Not Allowed;
DG touching (XW over RX) is Not Allowed;
DG touching (LW over RX) is Not Allowed.
DG13 a DG to NW space (for BH derivation). 0.40 - -
DG13a1 a DG to BB space (for BH generation). 0.40 - -
DG14 a DG overlap NW (for DF derivation). 0.40 - -
DG15 a DG to (OP intersect PC) (for BH derivation). 0.52 - -
DG16 a NW overlap past DG (for PH derivation). 0.40 - -
DG50 c [(RX over PC) over DG] width for device Weff. 0.36 - -
DG52 b (RX touching DG) to RX. 0.22 0.2170 0.040
DG110 c ((RX over DG) overlap past PC) 0.25 0.2170 0.040
(Checked as outside edge of PC to inside edge
of RX).
DG110a c (((RX straddling DG) overlap past PC) not over 0.60 0.5670 0.040
GRLOGIC).
Note: Rule DG110a only applies to RX (diffusion)
overlap past PC (gate edge) on the same Thick
Oxide FET whether DG covers the entire RX dif-
fusion, or RX diffusion straddles DG.
DG252R d 4 NW to NW space - if either NW shape touches 1.30 - -

DG.
DG260 b 5 ((RX P+ junction) touching DG) within NW. 0.50 0.5825 0.099
DG265a b 5 ((RX N+ junction) touching DG) to adjacent NW. 0.50 0.805 0.200
DG265a1 b 5 ((RX N+ junction) touching DG) to adjacent BB. 0.50 - -
DG265b b 5 (RX N+ junction) to adjacent (NW touching DG). 0.50 0.805 0.200
DG268a1 b 6 ((RX P+ Junction touching DG) not over T3) to 15.00 - -

(RX N-well Contact not over T3) for no latchup.
DG268b1 b 7 ((RX N+ Junction touching DG) not over T3)to RX 14.00 - -

Substrate Contact) for no latchup.

Layout Rules DG Layout Rules
the same cell nesting hierarchy in the design data. Examples of these levels are NW and DG; see Data Preparation Section
2. This is an effective electrical value, not a physical on-wafer dimension.
3. XW and LW Rules not required
4. This is strongly recommended for a Nwell to Nwell potential difference >=2.5V
5. The N+ and P+ junctions in these rules must include the gate area (RX) under the PC for these rules.
6. P+ Junction touching DG not over T3 = (((RX over DG) over BP) over NW) not over T3; NWell contact not over T3= ((RX not over BP)
over NW) not over T3.
7. N+ Junction touching DG not over T3 = (((RX over DG) not over BP) not over NW) not over T3;Substrate contact= ((RX over BP) not
over NW) not over T3
DG
DG
BP DG6 RX
NV PV N+
DG7 DG265a
NW
DG10 DG11
BP
DG5
DG9
RX DG RX
DG14 P+
DG4
DG260
DG110
RX RX RX
DG8a,b DG52 DG16
DG4
DG52 DG5
DG265b
DG8c
207c CA RX
DG110
N+
DG110a PC PC
PC
Figure 51. Dual Gate (DG) Oxide Rules

Layout Rules Dual Gate 3.3V I/O Device (5.2nm) Rules IBM
3.24 Dual Gate 3.3V I/O Device (5.2nm) Rules
3.24.1 3.3V NFET

This device requires both DG and XE layers to be present for the NFET.
Table 79. Dual Gate 3.3V I/O NFET Device Rules

l Min.
a
s
s
XE00 a XE width. 0.42
XE01 c XE shapes must be orthogonal.
XE02 a XE to XE space. 0.42
XE04a b (PC intersect RX) to XE min space. 0.50
XE04b b (PC intersect RX) within XE. 0.50
XE10 a 1 XE to NW space. Can be zero(0.00) or 0.400 um. 0.40
XE10b b XE over NW - Not Allowed.
XE10c b XE over PI - Not Allowed.
XE11 a 1 XE must be within DG. Can be zero(0.00) or 0.400um. 0.40
XE50 b ((RX over PC) over XE) width; RX width for Weff. 0.50
XE100 b ((PC over RX) over XE) width; PC width for Leff. 0.40
1. DRC should first check to see if the shapes are coincident ( within == 0.000) meaning after the shapes are subtracted, the
remainder is 0.000 which is acceptable. However, if the remainder after subtraction is not 0.000, then DRC should check that the
remaining distance after subtractions is greater than or equal to 0.400.

Layout Rules Low Leakage 3.3V I/O FET Device Layout Rules
3.24.2 3.3V PFET

This device requires both DG and XF layers to be present for the PFET
Table 80. Dual Gate 3.3V I/O PFET Device Rules

l Min.
a
s
s
XF00 a XF width. 0.42
XF01 c XF shapes must be orthogonal.

XF02 a XF to XF space. 0.42
XF04a b (PC intersect RX) to XF min space. 0.50
XF04b b (PC intersect RX) within XF. 0.50
XF10 a 1 XF must be within NW. Can be zero(0.00) or 0.400 um. 0.40
XF10c b XF over PI - Not Allowed.
XF11 a 1 XF must be within DG. Can be zero(0.00) or 0.40 um. 0.40
XF50 b ((RX over PC) over XF) width. RX width for Weff. 0.50
XF100 b ((PC over RX) over XF) width. PC width for Leff. 0.40
3.25 Low Leakage 3.3V I/O FET Device Layout Rules
3.25.1 3.3V HiVt NFET (JN) Rules

This device is the 3.3V NFET with a different P-well implantation and hence a different Vt. This device
receives the 3.3V N+ source/drain implant and NFET halo implants and requires DG, DW, JN, and XE layers
to be present.

Layout Rules Low Leakage 3.3V I/O FET Device Layout Rules IBM
Table 81. JN Layout Rules

l Min.
a
s
s
JN00 b JN width. 0.46
JN01 c JN shapes must be orthogonal. -
JN02 a JN to JN space. 0.40

JN03 a JN must be covered by XE.
JN04a b (PC intersect RX) to JN min space. 0.50
JN04aR d Rule Deleted.
JN04b b (PC intersect RX) within JN. 0.50
JN04bR d Rule Deleted.
JN09 d Rule Deleted.
JN11 a 1 JN must be within DG. Can be zero(0.00) or 0.400um. 0.40
3.25.2 3.3V HiVt PFET (JP) Rules

This device is the 3.3V PFET with a different N-well implantation and hence a different Vt. This device
receives the 3.3V P+ source/drain implant and PFET halo implants and requires DG, JP, and XF layers to be
present.
Table 82. JP Layout Rules

l Min.
a
s
s
JP00 b JP width. 0.46
JP01 c JP shapes must be orthogonal. -
JP02 a JP to JP space. 0.40
JP03 a JP must be covered by XF

Layout Rules nFET-in-Nwell (VAR) Device Layout Rules
Table 82. JP Layout Rules

l Min.
a
s
s
JP04a b (PC intersect RX) to JP min space. 0.50
JP04aR d Rule Deleted.
JP04b b (PC intersect RX) within JP. 0.50
JP04bR d Rule Deleted.
JP09 d Rule Deleted.
JP11 a 1 JP must be within DG. Can be zero(0.00) or 0.400um. 0.40
3.26 nFET-in-Nwell (VAR) Device Layout Rules

The decoupling capacitor and varactor are a capacitor that consists of an N+ poly gate electrode and an
N-well contacted through N+ diffusions.
In rules VAR1a, gatelength refers to PC length while in rules VAR10a it refers to RX width.
Table 83. Varactor Layout Rules

l Min.
a
s
s
VAR0 a VAR width. 0.68
VAR1a a ((PC over RX) over VAR) min width gatelength. 0.24
VAR1aR d ((PC over RX) over VAR) exact width gatelength. 1.0
VAR1b c ((PC over RX) over VAR) max width gatelength. 10.0
VAR10a a ((RX width under PC) over VAR) min width gatewidth. 1.0
VAR10aR d ((RX width under PC) over VAR) exact width gatewidth. 10.0
VAR10b c ((RX width under PC) over VAR) max width gatewidth. 32.0
VAR2 a VAR to VAR space. 0.92
VAR2b c VAR shapes must be orthogonal. -

Layout Rules nFET-in-Nwell (VAR) Device Layout Rules IBM
Table 83. Varactor Layout Rules

l Min.
a
s
s
VAR5 c VAR overlap past RX. 0.30
VAR6 c VAR must enclose NW. 0.00
VAR6b b NW cannot straddle VAR. -
VAR7 b BP touching VAR not allowed. -
VAR8 b (RX over VAR) must be within NW. -
VAR10 a ZEROVT to VAR space (for BH and DE generations). 1.13
VAR11 a DG to VAR space (for BH and DE generations). 0.40
VAR11c a DG overlap past VAR (for dataprep). 0.40
VAR12 a NW to VAR space (for BH generations). 0.40
VAR14 a (PC over OP) to VAR space (for BH generations). 0.56
VAR20 c {XW, LW} touching VAR not allowed. -
VAR20b c {NV, PV, JN, JP} touching VAR not allowed. -
VAR21 c 1 {XE, XF} touching VAR not allowed. -
VAR29 c (PC over RX) within VAR. 0.4
VAR30 c (PC over RX) to VAR. 0.5

1. (XE touching VAR) not allowed is also checked by combination of Rules VAR6 and XE10b in Table 79 on page 234 .

Layout Rules Triple Well (Isolated) NFET Layout Rules
3.27 Triple Well (Isolated) NFET Layout Rules

The PI level along with an NW ring forms the N type isolation for the isolated pwell of a triple well NFET
device, see Figure 52, Triple Well NFET (Single PI shapes) on page 241 and Figure 53, Triple Well NFET
(Multiple PI shapes) on page 242. All FET rules also apply to the Triple Well. PFETs are not supported in the
isolated Pwell or allowed within the NWell over the PI isolation design level per Rule TW260.
Table 84. Triple Well nFET Rules

l Min
a
s
s
TW00 a PI touching greater than one (PI not NW) is prohibited. = - - -
TW01 a PI width. 2.100 2.1000 0.208
TW02 a PI space (including notch). 1.000 1.0000 0.208
TW03 c PI shapes must be orthogonal.
TW04 b PI edges must be covered by NW (all edges).
TW05 b PI overlap of NW. 0.400 0.400 0.189
TW06 b NW overlap past PI. 1.100 1.100 0.189
TW07 c RX can not straddle PI.
TW07a c {(PC intersect RX), (PC touching OP) } touching (NW intersect (PI expanded by
+1.1)) not allowed (straddling not allowed).
TW08 c PI touching {DI,VAR} not allowed.
TW10 c NW ring must have at least one RX(not over PI) NW contact (NW ring around the PI
triple well tub must have at least one RX NW contact that is not over the PI which
contains Pwell. RX NW contact abutting PI not allowed).
TW12 a (NW over PI) minimum spacing and notch. 1.300 1.300 0.208
TW13 a PI to BFMOAT (PI touching BFMOAT not allowed) (for 3.100 3.1000 0.205
BF and BT gen).
TW13a c PI to BB (PI touching BB not allowed). 3.100 - -
TW13b a PI to ZEROVT (PI cannot touch ZEROVT) (for BF and 2.020 2.0200 0.207
BT gen).
1
TW13c c {NV, PV, JN, JP, XW, LW} touching PI not allowed.
TW13d c PCFUSE touching PI not allowed.
TW13f c {ESDIODE, ESDUMMY, ESD_CDM} touching PI not allowed.
TW14 c PI to JD space (PI touching JD not allowed). 4.600 4.5500 0.306

Layout Rules Triple Well (Isolated) NFET Layout Rules IBM
Table 84. Triple Well nFET Rules

l Min
a
s
s
TW15 c PI to adj NW (for NW that is not straddling PI edges). 2.020 0.281
TW16 c PI to adj (PC intersect OP). 1.750 1.7605 0.192
TW19 c (PI not over NW) must touch (RX over BP) to insure triple well contact.
TW134 b All triple wells (PI not NW) must touch RX, which is electrically connected to M1 to a
(RX not over (IND or IND_FILT or BB or BFMOAT or PI or NW or JD or T3)).
TW252b b PI to adj {XW, PV, LW, NV, JN, JP, XE, XF}. 1.100 - -
TW260 b RX P+ Junction2 to adjacent PI ((RX over BP) over 2.320 2.3425 0.184
NW) touching PI not allowed (for BT spacing to P+
junction).
TW260a b ((RX P+ Junction2) over DG) to adjacent PI ((RX over 2.580 2.6025 0.184
BP) over NW) touching PI not allowed (for BT spacing
to P+ junction).
TW261 b RX NW contact to PI (RX NW contact can not touch 0.290 -.0542 0.541
PI, RX NW contact abutting PI not allowed).
TW265 b (RX N+ junction2 over PI) min space to NW. 0.460 0.4225 0.099
TW265a b ((RX N+ junction2) touching DG) over PI) min space to 0.600 0.5625 0.099
NW.
TW265b b (RX N+ Junction2 not over PI) to adjacent (NW touch- 0.560 0.5225 0.099
ing PI) (where the RX does not intersect the (NW
touching PI)).
TW265c b (((RX N+ Junction2) touching DG) not over PI) to adja- 0.940 0.9025 0.099
cent (NW touching PI) (where the (RX touching DG)
does not intersect the (NW touching PI)).
TW266 b (RX triple-well contact over PI) min space to NW. 0.290 0.0925 0.099
TW266a b ((RX Substrate Contact) not over PI) to (NW touching 0.120 0.0825 0.099
PI).
TW268b b (RX N+ junction over PI) maximum distance to RX tri- 15.00 - -

ple-well contact [for no latchup]).
TW268c b ((RX N+ junction over PI) over DG) maximum distance 10.00 - -
to RX triple-well contact [for no latchup]).
1. See Rules XE10c and XF10c for 3.3V NFET and PFET check for not allowed in the triple well.

Layout Rules Triple Well (Isolated) NFET Layout Rules
2. N+ and P+ Junctions in these rules also include the gate area under the NFET and PFET.
TW5
N+
Junction
TW265 P+
TW268b Contact TW261
TW265a
TW268c
TW266 NW
Contact
TW06 TW10
PI
TW261
TW260
NW TW00
P+ Contact
Junction
TW04 [The two
(PI not over
NW) are not
electrically
isolated]
TW260
P+
P+ Junction
TW12 Junction
TW260
TW01 NW
Figure 52. Triple Well NFET (Single PI shapes)

Layout Rules Triple Well (Isolated) NFET Layout Rules IBM
N+
Junction
TW265
TW5
P+
TW268b
TW265a Contact
TW268c
TW266
TW06
NW
TW00
TW261
TW02 PI
NW
Contact TW10
TW00
TW260
TW01
TW12 P+
Junction
TW04
TW260
P+
Junction
Figure 53. Triple Well NFET (Multiple PI shapes)

Layout Rules Electrically Programmable Fuse
3.28 Electrically Programmable Fuse

This section describes the rules for the electrically programmed fuse (efuse).
3.28.1 Specifications
The electrically programmable fuse (e-fuse) is constructed on the poly-silicide level, which also is the level at
which the transistor gates are formed. The shape of the e-fuse is as shown in Figure 54, Electrically Pro-
grammable Fuse (e-fuse) Layout on page 243. For layout purposes, the e-fuse-link will be drawn in the
PCFUSE level which will be later integrated into PC level during data preparation. The EFUSE level is used in
dataprep to block the N+ S/D implant from being in the fuse device area.
BP
one direction EF14a EF25
EF16b
EF11b
EF24 one direction
PC EF16a
CA
EF11a
EF10a PC
CA CA CA
EF10b PCFUSE
CA CA CA
ANODE
CA EF11c
CATHODE
EF11d
M1
EFUSE M1
Figure 54. Electrically Programmable Fuse (e-fuse) Layout
Fuse Design Guidelines

The e-fuse anode and cathode have a positive and negative electrical bias with respect to each other dur-
ing fuse programming.
The e-fuse structure is positioned above the shallow trench isolation (STI) region. The poly-silicon on the
e-fuse link is p-doped. Hence, the e-fuse layout is enclosed by a BP mask.

Layout Rules Electrically Programmable Fuse IBM
Programming voltage must be applied with a positive bias on the anode.
The FET channel length must be the minimum allowed by the Layout Rules.
Each e-fuse is to be programmed by a programming transistor attached to it (shown schematically for one
e-fuse in Figure 55). The electrical parameter requirements for the e-fuse are given in Table 85, e-fuse
programming specifications on page 244.
Programming Bias VDD

VGS Fuse
VGS
Program Transistor (NFET or PFET)
t
Figure 55. The e-fuse appears as the load of a programming transistor.
The transistor and e-fuse programming specifications are shown in the following Table 85:
Table 85. e-fuse programming specifications
e-fuse Property Specification Tolerance
Programming voltage VDD 3.3V VDD < 3.7V, 100mV

VDD = 3.3V recommended.
Programming transistor current Ion 10 mA < Ion < 13.5mA -
Programming time, t 0.18 ms t < 1.0 ms -

Programming Pulse Rise time < 200ns -
Intact e-fuse resistance 50 < R < 130 -
Programmed e-fuse resistance > 5 k -
Fuse sense voltage - 100mV
Blown fuse sense voltage1 1.6V Maximum -
Fuse sense current < 0.5mA -
Fuse sense time < 100ns -
Fuse sense operations < 1 x 109 -

Table 85. e-fuse programming specifications
e-fuse Property Specification Tolerance
Sensed Programmed e-fuse Positive Bias on Anode -

1. Maximum sensing voltage across the blown (post programmed) fuse.
For further details, please contact your IBM Representative.
3.28.2 ECID Fuse

Electronic chip identification (ECID) designs must use at least 72 fuses to accommodate the 12-character (six
fuses per character) wafer ID. The wafer ID is comprised of the following characters:
Two-character IBM part number
Six-character wafer number unique to the manufacturer
Two-character manufacturer code
Two-character checksum on the previous ten characters

Layout Rules Electrically Programmable Fuse IBM
3.28.3 Layout Rules
Table 86. Electrically Programmable Fuse Layout Rules

l Min.
a
s
s
EF10a a PCFUSE width. 0.12
EF10b c PCFUSE length. 1.20
EF10c c PCFUSE to PCFUSE space. 2.00
EF10d c PCFUSE shapes must be orthogonal rectangles. -
EF10e c PC touching (PCFUSE sized by +2.00m) must be orthogonal rectan- -

gles.
EF10f c PC touching (PCFUSE sized by +2.00m) must abut PCFUSE. -
EF11a c (PC touching PCFUSE) butting edge length on one side of PCFUSE 0.68
(anode).
EF11b c (PC touching PCFUSE) butting edge length on other side of PCFUSE 1.70
(cathode).
EF11c c (PC touching PCFUSE) butting edge width on one side of PCFUSE 1.73
(anode).
EF11d c (PC touching PCFUSE) butting edge width on other side of PCFUSE 1.38
(cathode).
EF12b c PCFUSE to M1. 1.00
EF12c c PCFUSE to {RX, NW, OP, DG, XW, LW, NV, PV, JN, JP, V1, M2, V2}. 2.00
EF12d c PCFUSE not allowed over {RX, NW, OP, DG, XW, LW, NV, PV, JN, JP, -
CA, M1, V1, M2, V2}.
EF12e c (PCFUSE edges not abutting PC)1 to PC. 2.01
EF12f c PCFUSE to BFMOAT (PCFUSE not allowed over BFMOAT) . 3.00
EF12g c (BP touching PCFUSE) to JD (((BP touching PCFUSE) touching JD) 3.00
not allowed).
EF12h c PCFUSE not allowed over PI. -
EF12j c PCFUSE to {PD, RR, RP}. 2.00
EF12k c PCFUSE not allowed over {PD, RR, RP}. -
EF12m c PCFUSE to Kx (PCFUSE touching Kx not allowed); where x = 2,3. 3.00


l Min.
a
s
s
EF13b c 2 PCFUSE must abut PC on both ends. -
EF13c c PCFUSE may only abut one anode and one cathode. -
EF13e c PCFUSE must be centered at PC anode and cathode ends. -
EF14a c (PC touching PCFUSE) must be within BP. 0.25
EF14b c PCFUSE must be within BP. 0.25
EF15 c (PC touching PCFUSE) must touch exactly 4 CA shapes (4 CAs on the -
anode and 4 CAs on the cathode).
EF16a c { (M1 touching (PC touching PCFUSE)) /Anode width } in one direction. 0.8
EF16b c { (M1 touching (PC touching PCFUSE)) /Cathode width } in one direc- 1.8
tion.
EF20 c EFUSE shapes must be orthogonal. -
EF21 c EFUSE width (minimum). 0.40
EF22 c EFUSE spacing and notch (minimum). 0.40
EF23 c EFUSE must touch PCFUSE. -
EF24 c PCFUSE must be within EFUSE. 0.40
EF25 c (PC touching PCFUSE) must be within EFUSE. 0.40
EF27 c 3 EFUSE over {RX, OP} not allowed. -
EF27a c EFUSE over {PI, BFMOAT} not allowed. -
EF27a1 c EFUSE to BB (EFUSE touching BB not allowed) (for BH generation). 0.40
EF27b c EFUSE over {XW, LW, NV, PV, JN, JP} not allowed. -
EF28 c 4 EFUSE to adj {NW, DG,VAR} (EFUSE touching {NW, DG,VAR} not 0.40
allowed) (for BH generation).
EF28a c EFUSE to {difference [ intersection (OP, PC), (RX sized by +0.20m)]} 0.52
(for BH generation).
EF28b c EFUSE to ZEROVT (for BH generation). 0.92
EF28c c EFUSE to JD (EFUSE touching JD not allowed) (for BH generation). 3.00
EF28dR d EFUSE to [PC(touching OP, over RR)] (for BH generation, see Rule 2.00
EF29).

Layout Rules Design Services Matched-Circuit Design Rules IBM

l Min.
a
s
s
EF29 c EFUSE to {PD, RR, RP} (EFUSE touching {PD, RR, RP} not allowed). 1.60
EF30R d EFUSE to (PC over RX) (EFUSE touching (PC over RX) not allowed). 0.50
EF31R d EFUSE to RX. 0.30

1. Both larger edges of PCFUSE must be spaced away from (and not abut) separate {PC, PCEND} shapes.
2. The PCFUSE must abut two separate PC shapes on each small edge end of PCFUSE.
3. Former design levels {NW, DG} in this rule are checked by the not touching condition in Rule EF28, and have been deleted from the
Rule EF27 description.
4. XE is not listed since it will be checked by related Rule XE11. XF is not listed since it will be checked by related Rule XF11.
3.29 Design Services Matched-Circuit Design Rules

Analog, RF, high-frequency , and other circuits that are sensitive to matching can receive a special marker
level in IBM design services to ensure that all generated FILL and HOLE shapes in and around specific cir-
cuits are identical, regardless of location, orientation, or mirroring.
All models to receive matched FILL and HOLE shapes should contain one or more DS_MATCH marker lev-
els. All IBM design services-generated FILL and HOLE shapes are then identical in the model, provided there
are no shapes incurring on DS_MATCH from elsewhere in the hierarchy. If shapes from elsewhere in the
hierarchy do incur upon DS_MATCH, IBM-generated FILL and HOLE shapes are adjusted to accommodate
the incursion: FILL shapes are removed and/or HOLE shapes are added to individual instances as required.
In all cases, IBM-generated FILL and HOLE shapes within DS_MATCH are as identical as the layout allows,
regardless of the location, orientation, or mirroring of individual instances of the circuit that contain the
DS_MATCH marker level.
Table 87. DS_MATCH Design Rules
Rule C Notes Description Des.

l Min.
a
s
s
DS001 c DS_MATCH minimum space to DS_MATCH. 0.100
DS001bR d 1 DS_MATCH touching DS_MATCH prohibited. = -

Layout Rules Design Services Matched-Circuit Design Rules
Table 87. DS_MATCH Design Rules

l Min.
a
s
s
DS002 c DS_MATCH touching { IND, BFMOAT, IND_FILT, BONDPAD, = -

((LM intersect LM_RFLINE) sized by 3.1um), ((MA intersect
MA_RFLINE) sized by 3.1um) } is prohibited.
DS003 c DS_MATCH maximum area per shape. 400,000

1. DS001bR is not checked or coded in DRC. Per text in section 3.29 , Design Services Matched-Circuit Design Rules on page 248,
DS_MATCH should not incur on DS_MATCH from elsewhere in the hierarchy.

Layout Rules JD Junction Varactor Rules IBM
3.30 JD Junction Varactor Rules

Table 88. JD Rules

l Min. Dim.
a
s
s
JD1 a JD width. 2.000 2.450 0.210
JD2 a JD space. 2.860 2.410 0.210
JD3 b (RX over JD) over BP) min width (anode). 0.800
JD3aR d (BP over JD) min width (for VI generation). 1.080
JD3b b 1 (RX over JD) width (maximum). 65.00 - -
JD4R d 2 (((RX intersect BP) to (RX not over BP)) over JD) 0.240
space.
JD5R d 2 (RX cathode contact ring) must be within JD. 0.800
JD6 b JD to adj RX. 3.000
JD7 b JD to adj BP. 3.000
JD7b a BP straddling JD not allowed ((BP over JD) can not be - - -

shared with any other (BP not over JD)) (for VI genera-
tion).
JD8 b JD to adj NW (JD touching NW not allowed). 3.000
JD9 b 3 JD to adj {DG, BFMOAT, VAR, ESDIODE}. 3.000

(JD can not touch {DG, BFMOAT, VAR, ESDIODE}).
JD9a c JD to adj PC (JD can not touch PC). 3.000
JD9b b 3 JD to adj (ZEROVT expanded by 0.52um)) (JD can not 3.000

touch (ZEROVT(expanded by 0.52um)).
JD9c b JD to adj {RR, OP,PD, RP}. 3.000

(JD can not touch {RR, OP, PD, ESDIODE, RP}).
JD9d b JD to adj IND_FILT (JD can not touch IND_FILT). 3.000
JD9e b JD to adj IND (JD can not touch IND). 3.000
JD9f a JD to adj {XW, LW, NV, PV, JN, JP, XE, XF}. 3.000
(JD can not touch {XW, LW, NV, PV, JN, JP, XE, XF}).
JD9g b JD can not touch {ESDUMMY, ESD_CDM}. = - - -
JD9h1 a JD to BB (JD touching BB not allowed). 3.000 - -

Layout Rules Metal-to-Metal (MIM) Capacitor Layout Rules
Table 88. JD Rules

l Min. Dim.
a
s
s
JD11 a JD to adjacent NS (JD cannot touch NS). 5.520 - -
JD20 c JD must be orthogonal.

1. For more information, see Rule 41 in Table 21, Polysilicon and Isolation Layout Rules on page 95.
2. Applicable for non-differential HA Varactors only.
3. JD to {VAR, (ZEROVT sized by 0.52) for BH generation
3.30.1
3.31 Metal-to-Metal (MIM) Capacitor Layout Rules
3.31.1 MA metallization - Single and Dual Nitride MIM options

A single and dual aluminum nitride metal-to-metal (MIM) capacitor is offered with the metallization options
that include LY, E1 and MA. See Table 12, MA last metal Back End Of Line (BEOL) Metallization Options,
on page 65.
A single nitride LY to E1 metal-to-metal capacitor is formed by adding a thin layer of metal, QY, between E1
metal and the underlying layer of metal, LY.The top plate of the single capacitor, QY, is connected to E1 with
the via level FT.
A dual nitride MIM is like the single nitride MIM, except it is formed by adding a thin insulator and a thin metal
layer HY above the QY connecting to E1 through FT via.
The single and dual nitride MIM capacitors can be formed over a NW Ground Plane or other devices and wir-
ing.

Layout Rules Metal-to-Metal (MIM) Capacitor Layout Rules IBM
Single Nitride MIM Dual Nitride MIM

E1 E1 E1 E1 E1
FT Thin HY FT
FT Dielectric 2
Thin
Dielectric 1 QY
LY
Note: MA BEOL metallization shown

Figure 56. Cross Section of Single and Dual Nitride MIM capacitor structures (for MA metallization option).

QCAP3
Single MIM
QY
QCAP4
LY
QCAP1
QCAP5
QCAP2
FTBAR FT
E1
QCAP3
E1
Dual MIM
QY
FT
HY
QCAP4c
FT
QCAP4b
FT
QCAP1
LY
QCAP3a
Note: MA BEOL
metallization shown E1
Figure 57. Layout for Single and Dual Nitride MIM Capacitor (for MA Metallization Option)

Table 89. MIM Capacitor Rules (for MA BEOL metallization only)

l Min.
a
s
s
QCAP1 a 1 HY minimum width. 8.50
QCAP1a a QY minimum width. 5.24
QCAP1b c {QY, HY} area (m2) (maximum per shape). 100,000
QCAP1c c 2,3 (QY+HY) area (maximum per chip) (m2). 2,000,000
QCAP1dR d {QY, HY} maximum width (covered by Rule QCAP2b and 1,000
QCAP1b).
QCAP2 a QY to QY (HY to HY) space. 5.0
QCAP2a c {QY, HY} must be rectangular (45 QY or 45 HY not allowed).
QCAP2b c {QY, HY} aspect ratio (length/width ratio) (Needed for Rule 3
QCAP1dR).
QCAP3 a QY must be within LY. 2.0
QCAP3a a HY must be within QY. 2.0
QCAP4 a (FT touching QY) must be within QY (QY must touch FT(not 2.0
over HY)).
4
QCAP4a b (LY touching QY) touching FY not allowed.
QCAP4b b (FT touching HY) within HY. 2.0
QCAP4c b FT/FTBAR to adjacent HY (applies to HY and FT/FTBAR on the 2.0

same level).
QCAP5 b FT/FTBAR to adjacent QY (applies to QY and FT/FTBAR on the 2.0

same level).
QCAP12a b (QY covered by (NW not touching (PC or RX))) within NW (to 3.960
keep the NW fully viewable as an AC ground plane under the
QY MIM body).
QCAP17R d (QY(expanded by GR QCAP3) not touching {RX, PC} to RX). 3.500
QCAP18 a QY must touch FT.
QCAP18a a QY touching FTBAR not allowed.
QCAP19 a HY must touch FT.
QCAP19a a HY touching FTBAR not allowed.

Table 89. MIM Capacitor Rules (for MA BEOL metallization only)

l Min.
a
s
s
QCAP20R d QY to IND_FILT space. 10.00
QCAP22 a (FT touching HY) must have a minimum of 2 vias connecting to E1.
QCAP22a a (FT touching (QY width 8.5m)) must have a minimum of 2 vias connecting to
E1.
QCAP23a c Ratio of (FT over (QY not over HY)) area to QY area. (FT and 8.3
QY areas are measured in m2) (The ratio is the value in Design
Min column and is stated in units of percent or %).
QCAP23b c Ratio of (FT over HY) area to HY area. (FT and HY areas are 8.3
measured in m2) (The ratio is the value in Design Min column
and is stated in units of percent or %).
4, 5
QCAP24 b (QY touching (LY not within T3)) top or middle MIM capacitor plate must be tied
down to RX not over {PC, OP, T3} diffusion at E1.
4,5
QCAP24a b (HY touching (LY not within T3)) top MIM capacitor plate must be tied down to
RX not over {PC, OP, T3} diffusion at E1.
4,5
QCAP24b b ((LY touching QY) not within T3) bottom MIM capacitor plate must be tied down
to RX not over {PC, OP, T3} diffusion at E1.
QCAP25 b (LY touching QY) to LY. 1.20

1. HY dual MIMCAPs < 8.5um are not permitted.
2. The maximum MIM Capacitor area rule is the sum of the QY and HY areas and is based on 3.3V, 85C, 100K POH and 10 FIT use
conditions. See Section 4.39.9 , VMAX for Single and Dual Nitride MIM Capacitor (for MA or OL with LD Metallization Options) on
page 454 for complete Reliability Model.
3. The maximum area limit only applies to all QY shapes including QY shapes added to meet pattern density (see section 2.10 , Pattern
Density Rules on page 87).
4. This rule requires all MIM capacitors to be wired up to the E1 metal, before being connected to other circuit nodes using the E1 metal,
and then also requires all MIM capacitor plates to be connected to any RX(not over (PC or OP)) starting at the top plate of the
MIMCAPs. This insures that all MIMs electrically float until AFTER all RIE processing above QY is completed and then are tied to a
RX shape. FYBAR, which is allowed only used in the chip guard ring, can not contact the MIM LY bottom plate.
3.31.2 OL with LD Metallization - Single Hi-K MIM

A single Hi-K MIM capacitor is offered for the OL with LD metallization (options listed in Table 13 on page 66).
Hi-K MIM capacitors and nitride MIM capacitors can not both be used in a common chip design. For MPW
layout, consult your IBM technical representative.

The single Hi-K MIM capacitor uses design levels QT (bottom plate) and HT (top plate) with identification
level MIM_HK. The single Hi-K MIM uses mask levels QK and HK during fabrication. Fore more details,
see Table 9 on page 62.
Single Hi-K MIM Figure (for OL with LD Metallization option only)
OL OL
JT MIM (Single Hi-K)

JT
Thin
Dielectric HT
QT
MQ or MG
Figure 58. Single Hi-K MIM structure
3.31.3 OL with LD Metallization - Single or Dual Nitride MIM

A single nitride MIM capacitor or dual nitride MIM capacitor is offered for the OL with LD metallization (options
listed in Table 13 on page 66). Hi-K MIM capacitors and nitride MIM capacitors can not both be used in a
common chip design. For MPW layout, consult your IBM technical representative.
The single nitride MIM capacitor uses design and mask levels QT (bottom plate) and HT (top plate) with
identification level MIM_NI.
The dual nitride MIM capacitor uses design and mask levels QT (bottom plate) and HT (middle plate) and
KT (top plate) with identification level MIM_NI.
Single or Dual Nitride MIM Figure (for OL with LD Metallization option only)
Single Nitride MIM Dual Nitride MIM
OL OL OL OL OL OL
JT JT
JT JT JT
KT
HT HT
QT QT
Thin Thin
Dielectric MQ or MG Dielectric

Figure 59. Single or Dual Nitride MIM structure
Note: (see also Table 13 on page 66)

1. For MQ metallization options: MQ is not allowed under QT MIM if MG is not present on chip.
2. For MG metallization option: MG is not allowed under QT MIM bottom plate. MQ (required level) is
allowed under MIM in this option.
3. MIM must be directly under OL design level whether or not MG option is used.
4. Thin metals M1 through M6 are allowed under MIM.
OL
MQ (not allowed under QT)

when MG is not present.
MG (not allowed under QT)
when MG is present.
OL
JT
QT
HT
MQ or MG
OL OL
Figure 60. Layout for the Hi-K Single MIM capacitor.
QT, HT and KT Common Layout Rules for MIM Capacitors
Table 90. QT and HT and KT Common Layout Rules

l Min
a
s
s
QT0 a QT must touch HT. = -
QT1m c QT maximum width. 90
QT2 a QT minimum space. 1.00

Table 90. QT and HT and KT Common Layout Rules

l Min
a
s
s
QT2a c QT must be an orthogonal rectangle. = -
QT5c a QT space to MQ with touching prohibited when MG is not present. 1.00
QT6R d QT maximum length. 1000
QT7a c QT maximum area per shape (m2). 100,000
QT12a b ((QT covered by (NW not touching (PC or RX))) within NW (to keep 4.00
the NW fully viewable as an AC ground plane under the QT MIM
body).
QT20R d QT minimum space to IND_FILT with touching prohibited. 10.00
QT20aR d QT minimum space to Kx (x = 2,3,4,5,6) with touching prohibited. 5.00
QT30 a QT must touch {MIM_HK, MIM_NI}. -
QT31 a QT minimum within {MIM_HK, MIM_NI} with straddling prohibited. 0.20
QT32 a MIM_NI touching (CHIPEDGE touching MIM_HK) is prohibited. -
HT0 a HT must be within QT. 1.00
HT1bR c HT maximum width. 84.8
HT1cR c HT maximum area per chip (m2). 1,000,000
HT2 a HT minimum space. 2.00

HT2a c HT must be an orthogonal rectangle. = -
HT2b c Maximum ratio of [(HT length) (m)] / [HT width (m)]. 12
HT7 c 1 (HT touching MIM_HK) maximum total area per chip (m2). 1,000,000
KT0 a KT must be within HT. 1.00
KT2 a KT minimum space. 2.00
KT2a c KT must be an orthogonal rectangle. = -
KT2b c Maximum ratio of [(KT length) (m)] / [KT width (m)]. 12
KT7 c 2 [(HT touching MIM_NI) + KT] maximum total area per chip (m2). 2,000,000
KT25 a KT touching MIM_HK is prohibited. = -

1. The maximum Hi-K MIM Capacitor area rule is the sum of the HT area and is based on 3.3V, 85C, 100K POH and 10 FIT use
conditions. See Section 4.39.10 , VMAX for Hi-K MIM (for OL with LD Metallization Option) on page 456 for complete Reliability
Model.
2. The maximum single nitride or dual nitride MIM Capacitor area rule is the sum of the HT area (HT design level that is not touching the
separate identification level for the Hi-K mim) added to the KT area, if present. The maximum area is based on 3.3V, 85C, 100K POH
and 10 FIT use conditions. See Section 4.39.9 , VMAX for Single and Dual Nitride MIM Capacitor (for MA or OL with LD Metallization
Options) on page 454 for complete Reliability Model.
Table 91. MIM (QE) Alignment Rules1

l Min
a
s
s
QE1 d QE minimum width (Rule is not verified in DRC). 2.00
QE2 d QE minimum space (Rule is not verified in DRC). 2.00

1. For IBM KERF Reserved Level mask level QE listed in Table 5 on page 44.

QT, HT and KT OL with LD-specific Layout Rules for MIM Capacitors
Table 92. QT and HT and KT Layout Rules for the OL with LD metallization
Rule Class Notes Description Des

Min
QT1ae a QT minimum width. 6.0
QT3ae a JT minimum space to QT. 1.60
QT4ae a JT minimum within QT. 1.40
QT4be a JT minimum space to HT. 1.60
QT4ce a JT minimum space to KT. 1.60

QT4fe b (QT not over HT) must touch two or more JT shapes. = -
QT5be a QT minimum space to (OL not touching QT). 1.00
QT5d a QT space to MG (see also Rule QT9b). 1.00
QT8e b 1,2 All plates ({KT, HT, QT} not within T3) of a MIM capacitor must be = -
tied down to RX not over {PC, OP, T3} diffusion at OL (per rule
QT8ae).
QT8ae b 1,2 All plates (KT, HT, QT) of a MIM capacitor must be connected up to = -
OL. (Top or middle plate HT must be connected up using at least
one JT via or comply with Rule HT4fe; see Rule QT4fe for bottom
plate connection verification description; Top plate KT must be con-
nected up using at least one JT via or comply with Rule KT4fe).
QT9ae b 3 [(OL touching QT) not touching (JT over QT)] is prohibited. = -
QT9b a MG touching QT is prohibited. = -
QT22e a JTBAR touching QT is prohibited. = -
QT23e c Maximum ratio (%) of {[JT over (QT not over HT)] via area (m2)} / 5.0
(QT bottom plate area (m2)).
HT1ae a HT minimum width. 4.00
HT4ae b JT minimum within HT. 1.40
HT4fe c (HT width 7.6 m) must touch at least two (JT not over KT) vias. = -
HT5ce b HT to (OL not touching HT) space. 1.00
HT9ae a 3 ((OL not touching KT) touching HT) not touching JT is prohibited. = -
HT23e c Maximum ratio (%) of [(JT over ((HT width 7.6 m) not over KT)) 5.0
via area (m2)] / [HT middle or top plate area (m2)].
KT1ae a KT minimum width. 4.00

Layout Rules Vertical Natural Capacitor
Table 92. QT and HT and KT Layout Rules for the OL with LD metallization
Rule Class Notes Description Des

Min
KT4ae b JT minimum within KT. 1.40
KT4fe c (KT width 7.6 m) must touch at least two JT vias. = -
KT5ce b KT to (OL not touching KT) space. 1.00
KT9ae a 3 [(OL touching KT) not touching (JT over KT)] is prohibited. = -
KT23e c Maximum ratio (%) of [(JT over (KT width 7.6 m)) via area (m2)] 5.0
/ [KT top plate area (m2)].
1. This rule requires all MIMs to be wired up to OL before being connected to other circuit nodes and then also requires the nodes
containing the MIM to be connected to a (RX not over {PC, OP, T3}). This ensures that all MIMs electrically float until AFTER all
RIE processing above QT as well as HT or KT is completed and then are tied to RX.
3. The intent of this rule is any OL wire over a MIMCAP plate (QT or HT or KT) should be used to electrically wire to the plate and not pass
over the plate without making electrical contact to it.
3.32 Vertical Natural Capacitor

The Vertical Natural Capacitor (VNCAP) BEOL capacitor is constructed from fingers of metal wires and vias
laid out to create a capacitor. The VNCAP is built in a continuous metal stack (see Figure 61). Missing metal
levels are prohibited because they affect the capacitance density calculation (see Table 159 on page 401).
Normal wiring is permitted above the VNCAP stack.
Mx
V2
M2
V1
M1
Figure 61. VNCAP Capacitor Cross Section.
The Vertical Natural Capacitor (VNCAP) is built in any metal sequence of M1 through M6 (for example, M1
through M3 or M2 through M6). As shown in Figure 62 the capacitor width determines the number of metal
walls comprised of multiple metal levels and their connecting vias, while capacitor length determines the
length of the metal wires that form the metal walls. Both square and rectangular capacitor shapes are permit-
ted; irregular capacitor designs are not supported. The VNCAP marking layer must be used around the layout
to identify the device.

Layout Rules Vertical Natural Capacitor IBM
W VNCP1
VNCAP
VNCAP_Mx,
VNCAP_M(x+1), ...
L Mx, M(x+1), ...

Note:
VNCAP length
not drawn to
scale in Figure
Figure 62. VNCAP Capacitor Top View
Figure 63 shows the general layout of the VNCAP capacitor. The OUTLINE_VNCAP shape is not shown.
VNC199 (Vx vias intentionally not shown here) Mx straps

M(x+1) straps
Vx vias
VNC121 Mx fingers,
M(x+1) fingers
VNC140
Note: VNC110a
VNCAP length
(finger length)
is not drawn to
scale in Figure VNC120a VNC155
VNC196a
VNC196b
W
VNC196b
Figure 63. VNCAP Capacitor Metal Fingers and Tabs (Top View)

3.32.1 Vertical Natural Capacitor Layout Rules
Table 93. Vertical Natural Capacitor Layout Rules

l Min.
a
s
s
VNCA1 a VPPCAPMx touching CHIPEDGE is prohibited, where x = -

1,2,3,4,5,6.
VNCP0 c 1 When used as for a Vertical Natural Capacitor, Mx must be -

covered by VNCAP_Mx, where x = 1,2,3,4,5,6.
VNCP1 c VNCAP minimum width. 3.64
VNCP2 c VNCAP minimum space and notch. 2.00
VNCP5 c VNCAP touching {IND, IND_FILT, BONDPAD, LM_RFLINE, -

MA_RFLINE, LOGOBND, EFUSE, GUARDRNG, PROTECT}
is prohibited.
VNCP5a c VNCAP minimum space to {all levels listed in VNCP5}. 5.00
VNCP10 c VNCAP must be orthogonal. -
VNCP11 c 2 VNCAP must enclose at least one VNCAP_PARM. -
VNCP12 c 2 VNCAP must enclose at least one VNCAP_COUNT. -
VNCM0 c Only one VNCAP_Mx is permitted within VNCAP for each Mx, -
where x = 1,2,3,4,5,6.
VNCM1 c VNCAP_Mx must be covered by VNCAP, where x = -

1,2,3,4,5,6.
VNCM2 c 3 VNCAP_Mx must touch at least two Mx fingers; where -

x=1,2,3,4,5,6.
VNCM3 c 3 VNCAP_Mx must touch exactly two Mx straps; where -

x=1,2,3,4,5,6.
VNCM6 c VNCAP_Mx that touch (that is they are part of the same -
device) must be coincident on all sides, where x = 1,2,3,4,5,6.
VNCM10 c VNCAP_Mx must be orthogonal, where x = 1,2,3,4,5,6. -
VNCM11 c 3 VNCAP_Mx must be coincident with the outer edges of the Mx -

straps, where x = 1,2,3,4,5,6.
VNCM12a c 3 VNCAP_Mx must be coincident with the outer edges of at least -

two Mx finger where x = 1,2,3,4,5,6.
VNCM55b c (M1 intersect VNCAP_M1) touching CA not allowed. -


l Min.
a
s
s
VNCM55c c (Mx intersect VNCAP_Mx) touching VL not allowed, where -

x=2,3,4,5,6.
VNCM59 c VNCAP within (NW not touching (PC or RX)). 5.00
VNCM90 c 4 VNCAP_Mx area (maximum per chip for each Mx level) (m2), 1,000,000
where x = 1,2,3,4,5,6 (Maximum allowable VNCAP capacitor
area on each Mx mask level is the sum of the separate
VNCAP_Mx dummy design and utility level shape areas on
each mask design level).
VNCM100a c [(Mx over VNCAP_Mx) not over VNCAP_M(x-1)] touching -

V(x-1) is prohibited, where x=2,3,4,5,6. This rule prohibits vias
down to non capacitor metal.
VNCM100b c [(Mx over VNCAP_Mx) not over VNCAP_M(x+1)] touching Vx -

is prohibited, where x=1,2,3,4,5. This rule prohibits vias up to
non capacitor metal.
VNC110a c 3 Mx finger exact width, where x =1,2,3,4,5,6. 0.28
VNC120a c 3 Mx finger exact space to Mx finger, where x =1,2,3,4,5,6. 0.20
VNC121 c 3 Mx finger exact space to Mx strap, where x =1,2,3,4,5,6. 0.36
VNC125 c 3 (Mx over VNCAP_Mx) must be either a finger or strap, where x -

= 1,2,3,4,5,6.
VNC140 c Vx exact space to adjacent Vx (within same Mx finger, 0.40

edge-to-edge), where x = 1,2,3,4,5.
VNC155 c 5 (Vx over VNCAP_Mx) must be within [Mx and M(x+1)] where x 0.04
= 1,2,3,4,5.
VNC196a c Vx minimum space to adjacent [Mx, M(x+1)] strap, where x = 0.10

1,2,3,4,5.
VNC196b c Vx within the [Mx, M(x+1)] strap, where x = 1,2,3,4,5 (at least 0.40
one side of the Vx should be within metal strap by 0.40).
VNC199 c Mx strap exact width, where x=1,2,3,4,5,6. 2.80
VNC500 c 3,6 All Mx finger edges must be coincident with all other M(x-1) fin- -
ger edges below them, where x = 2,3,4,5,6.
VNC500b c 3,6 All Mx strap edges must be coincident with all other M(x-1) -
strap edges below them, where x = 2,3,4,5,6.


l Min.
a
s
s
VNC510 c 3,7 Each Mx finger must be fully populated with Vx vias, where x = -
1, 2,3,4,5.
VNC510b c 3,7,8 Each Mx strap must be fully populated with four rows of Vx vias -
along the capacitors width (the long direction of the metal
strap), where x = 1, 2,3,4,5.
VNC510c1 c 3,7,9 When a VNCAP contains more than one consecutive level of -
metal, each Mx finger must touch at least one Vx via. ( [(Mx fin-
ger) over (M(x+1) finger)] must touch at least one Vx via).
VNC510c2 c 3,7,9 When a VNCAP contains more than one consecutive level of -
metal, each Mx strap must touch at least one Vx via. ( [(Mx
strap) over (M(x+1) strap) ] must touch at least one Vx via).
VNC520 c 10 Vx on adjacent Mx fingers must be staggered (no common run -

length 0), where Vx = 1,2,3,4,5 and Mx = 1,2,3,4,5,or 6.
VNC530 c 6 ((Vx intersect VNCAP_Mx) intersect VNCAP_M(x-1)) must be -

coincident with V(x-1), where x = 2,3,4,5. (All capacitor Vx vias
in the same net must be placed directly over each other and
travel completely through the capacitor stack form the top
metal plate to the bottom metal plate) .
VNC575 c Adjacent (interdigitated) Mx fingers must be on different nets, -

where x = 1,2,3,4,5,6.
VNC575b c Mx fingers must touch only one Mx strap, where x = -

1,2,3,4,5,6.
VNC576 c The Mx straps must touch exactly two different nets, where x = -
1,2,3,4,5,6. (Two Mx straps on the same net is prohibited).
VNC588 c 11 VNCAP_Mx must be fully populated with an even number of -

Mx fingers, where x = 1,2,3,4,5,6.
VNCPM1 c 2 VNCAP_Mx over VNCAP is prohibited unless VNCAP_Mx is -

defined by VNCAP_PARM and VNCAP_COUNT within
VNCAP and the corresponding BEOL stack, where x =
1,2,3,4,5,6.
VNCPM2 c 2 VNCAP_Mx must be present for every Mx level defined by -

VNCAP_PARM and VNCAP_COUNT within VNCAP and the
corresponding BEOL stack, where x = 1,2,3,4,5,6. The metal
levels must be continuous through the device.
1. This rule is not validated during DRC.IBM recommends using the vncap pcell layout, otherwise the designer is responsible for
drawing VNCAP, VNCAP_COUNT, VNCAP_PARM, VNCAP_Mx shapes that correctly represent the designed capacitor.

2. See Section 3.32.2 , Using VNCAP_PARM and VNCAP_COUNT on page 266 for information on using VNCAP_PARM and
VNCAP_COUNT.
3. Mx finger = [Mx over VNCAP_Mx] with a width equal to Rule VNC110 (for x=1,2,3,4,5,6). Mx strap = [Mx over VNCAP_Mx] with a width
equal to Rule VNC199 (for x=1,2,3,4,5,6). There are only two straps allowed on each metal level per capacitor.
4. Capacitor device area can not exceed 1,000,000um2 on each individual Mx mask level (x=1,2,3,4,5, 6)
5. For this rule, the Mx and M(x+1) are assumed to be part of the VNCAP, have coincident edges, and be identified by their corresponding
VNCAP_Mx level shapes, where x = 1,2,3,4,5. The Vx vias that are part of a VNCAP must be within the metal above as well as the
metal below that are only part of a VNCAP layout. See related Rule VNCM100a and VNCM100b.
6. Rule applies to all BEOL Mx level stack options used for capacitor designs, where x = 1,2,3,4,5,6.
7. This rule is not validated during DRC. If Rule VNC510 or VNC510b are not validated during DRC, then related Rule VNC510c1 and
VNC510c2 must be checked. IBM recommends using the vncap pcell layout to closely match the model.
8. If Rule VNC510b is verified in DRC, a (Vx over Mx_strap) space equal to 0.40m, where x = 1,2,3,4,5, is suggested to be used to match
the layout criteria supported in the design kit. A separate rule that validates the Vx via spacing in the Mx_strap regions of the VNCAP
device has not been included in the layout rules, by intention. If a designer elects to use Vx via spacing less than 0.40m in this device,
up to five rows of vias may fit in the strap. However, use of 5 rows of Vx vias in the strap is not supported in the design kit or device
model, nor is use of greater than 4 rows of vias reported as a DRC violation to this rule during verification.
9. There may be alternate verification methods in DRC to satisfy the criteria described in the Rule description. A specific rule description
is provided to insure that the special case, where a VNCAP device is constructed using only a single Mx level for each net and does
not contain any Vx vias, is not falsely reported as an error. Only VNCAP devices containing consecutive levels of Mx and M(x+1) must
touch a Vx via.
10. For this rule, by default Vx intersects (VNCAP_Mx and VNCAP_M(x+1))
11. To determine if VNCAP_Mx is fully populated with fingers, use Rules VNC110a and VNC120a for x = 1,2,3,4,5,6 to calculate the
maximum number of allowable fingers within the VNCAP_Mx shape.
3.32.2 Using VNCAP_PARM and VNCAP_COUNT

The number of VNCAP_PARM shapes determines the metal level on which the capacitor starts as shown in
Table 94.
Table 94. VNCAP starting level according to VNCAP

Number of VNCAP_PARM Shapes Capacitor Starting Level
1 M1
2 M2
3 M3
4 M4
5 M5
6 M6
The number of VNCAP_COUNT shapes equals the number of metal levels in the capacitor. For example,
three VNCAP_COUNT shapes indicates that the capacitor is comprised of three metal levels.
When combined with the specified BEOL stack, VNCAP_PARM and VNCAP_COUNT can be used to fully
specify the capacitor.

Layout Rules Inductor Layout Rules
For example, if a VNCAP contains three VNCAP_PARM shapes and three VNCAP_COUNT shapes, and the
BEOL stack is comprised of five Thin (1x) metal levels and two Thick (2x) metal levels, which is shown as one
of the 7LM options in Table 11 on page 64, then the capacitor starts on M3 and is comprised of metal levels
M3, M4, and M5. For this capacitor, VNCAP, VNCAP_M3, VNCAP_M4 and VNCAP_M5 must be present;
and any other VNCAP_Mx shapes are invalid for this capacitor.
Note: The VNCAP_PARM and VNCAP_COUNT shapes can be placed anywhere within the VNCAP level.
3.33 Inductor Layout Rules
3.33.1 LM Inductor
Inductors for the LM BEOL options can be designed using a variety of BEOL and via levels.
For compatibility to the base CMS8SFG technology, the IND level is the corresponding marking layer (without
using the IND_FILT marking level).
For CMRF8SF technology offered LM BEOL inductors, both the IND and IND_FILT (IND intersect IND_FILT)
levels are to be used as the corresponding marking layers.
The IND or the IND_FILT marking layers, prevent the formation of a p-well underneath the inductor, resulting
in a low-doped silicon substrate, (similar to, or redundantly with, the BFMOAT marking layer), when an NW is
not drawn (see Table 8, Shape Manipulation Prior to Mask Write on page 59). The IND or IND_FILT mark-
ing layers also affect the generated FILL shapes, resulting in reduced-density RXFILL, PCFILL and MxFILL
shapes to minimize substrate coupling (see section 2.10 , Pattern Density Rules on page 87).
Inductors that include Mx (x=1,2,3,4,5,6,Q,G) or LM metal levels, that intersect the IND or IND_FILT marking
layers, receive standard IBM MxHOLE or LMHOLEs during the IBM release process.
The Inductor layout rule allowances differ between the CMS8SFG compatible (IND) and CMRF8SF (IND and
IND_FILT) offering.
The measured width of the 45 degree (xxBAR shapes touching IND) in Inductors may not exactly match the
specified dimensions to grid snapping ( +/- Grid * sqrt(2)) tolerance, where xx = V1, V2, V3, V4, V5, VL
The measured width of the 45 degree (xxBAR shapes touching (IND intersect IND_FILT)) in Inductors may
not exactly match the specified dimensions to grid snapping ( +/- Grid * sqrt(2)) tolerance, where xx = VQ,
VG.
3.33.2 MA Inductor
Inductors for the MA BEOL options can be designed using a primarily the last three BEOL levels, except for
the M1 groundplane version where all the BEOL metal levels are enabled for interconnect design.
Only the IND_FILT (IND_FILT not touching IND) level is to be used as the corresponding marking layer for
the MA inductor.

Layout Rules Inductor Layout Rules IBM
The IND_FILT marking layer prevents the formation of a p-well underneath the inductor, resulting in a
low-doped silicon substrate, (similar to, or redundantly with, the BFMOAT marking layer), when an NW is not
drawn (see Table 8, Shape Manipulation Prior to Mask Write on page 59). This marking layer also affects
the generated FILL shapes, resulting in reduced-density RXFILL, PCFILL and MxFILL shapes to minimize
substrate coupling (see section 2.10 , Pattern Density Rules on page 87).
M1 groundplane Inductor wiring that includes (Mx (x=1,2,3,4,Q,G) intersect IND_FILT) receive standard
MxHOLE during the IBM release process, if the wires are designed wide enough to receive these MxHOLE
shapes.
The measured width of the 45 degree (xxBAR shapes touching IND_FILT) in Inductors may not exactly
match the specified dimensions to grid snapping ( +/- Grid * sqrt(2)) tolerance, where xx = FT or F1.
3.33.3 AM Inductor
Inductors for the AM BEOL options can be designed using a primarily the last three BEOL levels, except for
the M1 groundplane version where all the BEOL metal levels are enabled for interconnect design.
Both the IND_FILT level and IND levels are to be used as the corresponding marking layers for the AM induc-
tor.
drawn (see Table 9, Shape Manipulation Prior to Mask Write (for LM last metal) on page 62). This marking
layer also affects the generated FILL shapes, resulting in reduced-density RXFILL, PCFILL and MxFILL
shapes to minimize substrate coupling (see section 2.10 , Pattern Density Rules on page 87).
M1 groundplane Inductor wiring that includes (Mx (x=1,2,3,4,5,Q) intersect (IND_FILT covered by IND))
receive standard MxHOLE during the IBM release process, if the wires are designed wide enough to receive
these MxHOLE shapes.
match the specified dimensions to grid snapping ( +/- Grid * sqrt(2)) tolerance, where xx = FT or F1.
3.33.4 LD Inductor
Inductors for the OL with LD metallization options can be designed using a primarily the last three or four
BEOL levels, except for the M1 groundplane version where all the BEOL metal levels are enabled for inter-
connect design.
Only the IND_FILT (IND_FILT not touching IND) level is to be used as the corresponding marking layer for
the OL with LD inductor, and the MxDUMHOL (where x = Q, G) shapes must also be used to identify these
inductors.
drawn (see Table 8, Shape Manipulation Prior to Mask Write on page 59). This marking layer also affects
the generated FILL shapes, resulting in reduced-density RXFILL, PCFILL and MxFILL shapes to minimize
substrate coupling (see section 2.10 , Pattern Density Rules on page 87).

Inductors that include Mx (x=1,2,3,4,5,6) metal levels, that intersect the IND_FILT marking layer, receive
standard IBM MxHOLEs during the IBM release process. However, for the OL with LD metallization options
only, the inductor Mx wiring levels (where x=Q,G) do not receive MxHOLE shapes during the IBM release
process. Use of the MxDUMHOL shapes (where x=Q,G) prohibited MxHOLE shape placement, and wide
metal spacing rules listed in section 3.8.8 , MQ or MG Layout Rules for Inductors (for OL with LD Metalliza-
tion options) on page 153 must be followed for manufacturability.
match the specified dimensions to grid snapping ( +/- Grid * sqrt(2)) tolerance, where xx = JT or VV.
3.33.5 M1 Inductor Groundplane (BFMOATIND) Layout Rules
Table 95. Inductor M1 Groundplane (BFMOATIND) Layout Rules

l Min.
a
s
s
INDGP1 b (BFMOATIND covered by (BFMOAT intersect IND_FILT)) must touch = -

M1.
3.33.6 Inductor Layout Rules
Table 96. Inductor Layout Rules

l Min.
a
s
s
IND05a c (IND not touching IND_FILT) max width or length. 320.00
IND05a1 c (IND touching IND_FILT) max width or length. 474.00
IND05a1R d (IND_FILT touching LM) max width or length (recommended rule 474.00
since checked by Rule IND10b).
IND05b c IND min width or length. 30.00
IND05c c IND_FILT min width or length. 30.00
IND06 c IND shapes must be orthogonal. = -
IND06a c IND_FILT shapes must be orthogonal rectangles.


l Min.
a
s
s
IND07R d 1 Place BFMOAT or M1 ground plane under ((E1 over MA) over IND_FILT) or
((OL, LD) over IND_FILT) inductor to minimize capacitance to substrate. See
rule IND08aR for the required layout details.
IND08aR d 1 {BFMOAT, BFMOATIND} overlap past ((MA over E1) over 5.040
IND_FILT)
{BFMOAT, BFMOATIND} overlap past ({LD, OL}) over IND_FILT).
IND08bR d 1 {BFMOAT, BFMOATIND} overlap past ((LM over {MQ, MG}) over 5.040
IND_FILT).
IND08R d 2 Use 45 degree metal bends and viabars. = -
IND09a c 3 (IND_FILT touching {LY, E1, MA, OL, LD}) over IND is prohibited. = -
IND10a c (IND_FILT not touching IND) must touch {LY, E1, MA, OL, LD}. = -
IND10b c (IND touching IND_FILT) must be coincident on all sides with = -

IND_FILT.
IND10c c (LM over IND_FILT ) must touch IND). = -
IND11 c VxBAR where (x=1,2,3,4,G) touching (IND_FILT not over IND) is prohibited.
VxBAR where (x=1,2,3,L,Q) touching (IND_FILT touching {LY, E1, MA}) is pro-
hibited.
VxBAR where (x=1,2,3,4,5,L,Q,G) straddling IND is prohibited (see also Rules
557, 558, 990e, 990g).
Note: The intent of Rule IND11 is to prohibit all VxBARs from use in inductors or
wiring under the LY, E1,MA, or AM inductor coils. VxBARs between the 1x cop-
per Mx (x=1,2,3,4) or VGBAR levels are prohibited in inductors or wiring under
the (OL or LD) as well as (LY, E1, MA or AM) inductor coils (IND_FILT not over
IND). VxBARs are allowed for LM inductors [IND or (IND over IND_FILT)] given
that the viabars are within the IND dummy design level. See also Rules IND11a,
IND11b, IND11d, IND11e for other inductor layout rule guidelines.
IND11a c {RX, JD, NW, LW, PV, PI, XW, NV, JN, JP, BB, DG, PC, XE, XF, BP, PD, RR,
RP, OP, CA, LV, DV, QT, QY, Kx (where x = 2,3,4,5,6)} touching IND_FILT is
prohibited.
IND11b c Kx touching IND is prohibited; where x = 2,3,4,5,6.

4
IND11d c VxBAR where (x=5) touching (IND_FILT touching {OL, LD}) is prohibited.
VxBAR where (x=4,5) touching (IND_FILT touching {LY, E1, MA}) is prohibited.


l Min.
a
s
s
4
IND11e c M6 touching (IND_FILT touching {OL, LD}) is prohibited.
{M5, M6} touching (IND_FILT touching {LY, E1, MA}) is prohibited.
IND12 c NW to IND_FILT. 4.60

5
IND16a c (BFMOAT touching IND_FILT) cannot touch (BP or PC or RX).
IND17 c {MA, E1, LY, LD, OL} over IND is prohibited.
IND20 c 6 IND_FILT to Mx not over IND_FILT on all metal levels 10.0

(x=1,2,3,4,5,Q,G) (for required MxFILL region).
IND23 c 7 Inductor coil shorting is prohibited. Rule applies to all metal levels used in the
construction of the inductor spiral. Inductor groundplanes are exempt from this
check. For the purpose of inductor spiral checking:
[MQ (used for the inductor coils) over IND_FILT] must be covered by MQ_COIL.
[MG (used for the inductor coils) over IND_FILT] must be covered by MG_COIL.
[ LM (used for the inductor coils) over IND_FILT] must be covered by LM_COIL.
[ E1 (used for the inductor coils) over IND_FILT] must be covered by E1_COIL.
[MA (used for the inductor coils) over IND_FILT] must be covered by MA_COIL.
[OL(used for the inductor coils) over IND_FILT] must be covered by OL_COIL.
[LD (used for the inductor coils) over IND_FILT] must be covered by LD_COIL.
[AM (used for the inductor coils) over IND_FILT] must be covered by AM_COIL.
[M4 (used for the inductor coils) over IND_FILT] must be covered by M4_COIL.
[M5 (used for the inductor coils) over IND_FILT] must be covered by M5_COIL.
IND23a c xx_COIL must be covered by IND_FILT; where xx = MQ, MG, LM, E1, MA, OL,
LD, AM, M3, M4.
IND25a c 8 M1 groundplane, when used in a completed chip design, can not = -

be electrically floating.
IND80 c IND_FILT to RX (RX straddling IND_FILT not allowed). 1.00
IND82 c IND_FILT to {IND_FILT, BB, BFMOAT, ZEROVT, ESDIODE, JD, (PI 2.00
expanded by +1.1m))} space (for BT generation).
IND200 c CA must not touch IND.
IND560 c 9 V1BAR,V2BAR,V3BAR,V4BAR,V5BAR width (over IND). = 0.20
IND564 c V1BAR to V1BAR, V2BAR to V2BAR, V3BAR to V3BAR, V4BAR 0.60

to V4BAR V5BAR to V5BAR space (over IND).
IND567 c VxBAR (over IND) must be within Mx (x=1,2,3,4,5). 0.20


l Min.
a
s
s
IND567a c (VQBAR over {IND, IND_FILT}) must be within MQ. 0.20

(VGBAR over IND) must be within MG.
IND568 c (VxBAR over IND) must be within Mx +1 (x=1,2,3,4,5). 0.20
IND568a c (VQBAR over IND) must be within (MG or LM). 0.20

(VQBAR over (IND_FILT not over IND)) must be within MG.
(VGBAR over IND) must be within LM.
IND571 c (VLBAR over {IND, IND_FILT}) must be within Mx (x=3,4,5,6,Q). 0.20
IND625 c 9 (VLBAR over {IND, IND_FILT}) width. = 0.40

(VQBAR over {IND, IND_FILT}) width.
(VGBAR over IND) width.
IND628 c (VLBAR over {IND, IND_FILT}) space. 1.20

(VQBAR over {IND, IND_FILT}) space.
(VGBAR over IND) space.
IND629 c (VQBAR over {IND, IND_FILT}) to (VQBAR over LM_RFLINE) 1.20

space.
(VGBAR over IND) to (VGBAR over LM_RFLINE) space.
IND702 c Maximum (VxBAR over IND) density (%) over local 50m x 50m 12.5
areas stepped in 25m increments across the chip, where x =
1,2,3,4,5,L.
IND800 c RX to IND space. 1.00
IND810 c IND to NW space (for BF generation). 1.00
IND820 c IND to {IND, BFMOAT, ZEROVT, ESDIODE} space (for BT genera- 2.00
tion).
IND820a c IND to {JD, (PI expanded by +1.1m), IND_FILT } space (for BF or 2.00
BT generation).
IND894 c 10 (VVBAR over IND_FILT) must be within OL. 1.00
IND895 c 10 (VVBAR over IND_FILT) must be within LD. 1.00
1. Rule not verified during DRC. Rule is for inductor layout guidance only.
2. Rule not verified during DRC. It is recommended that viabars are connected in a vertex.
3. A description for the OL or LD inductors is not included in this Rule. See rules INDMG2a and INDMG1 in Table 40, MG Inductor Layout
Rules, on page 153 and rules INDMQ2a and INDMQ1 in Table 41, MQ Inductor Layout Rules, on page 154, which verifies this rule
description for (IND_FILT touching {OL, LD}).

4. Rule IND11d and IND11e defines the xxbar via or Mx metal levels that are not supported in MA or OL with LD metallization inductor
layouts (not valid levels in those metallization stack options), in contrast to the LM metallization option which supports the use of these
design levels. Rule IND11 only includes the valid levels for each inductor layout option. For more information on the LM, MA or OL
with LD metallization options, see Table 11 on page 64, or Table 12 on page 65 or Table 13 on page 66, respectively.
5. GR IND16a and IND16 are applicable to both the LM and MA Inductors.
6. Rule IND20, IND20a and IND20b, IND20c and IND20dR are intended to allow Mx wiring to straddle the IND_FILT shape only
perpendicular to the outer edges of the IND_FILT shape. Any Mx wires that straddle the IND_FILT shape, and have a vertex outside
of the IND_FILT shape, that vertex must be at least 10um from the outer edges of the IND_FILT shape. Any Mx wires that do not touch
the IND_FILT shape must be at least 10um away from the IND_FILT shape.
7. DRC shall report shorted coils. The xx_COIL shapes are provided to assist in this verification. The xx_COIL shapes should be enlarged
by less than half of the spacing of the spiral metals to avoid false errors due to the 45 degree line edges or slivers.
8. This rule can be waived for symmetric inductor layouts.
9. Non orthogonal widths can be checked to + or - 0.02 um from the groundrule value.
10. The measured distance of VVBAR within OL or LD shapes used in inductors might not exactly match the specified dimensions due to
grid snapping ( grid times the square root of 2 tolerance).

Layout Rules RF Interconnect Line and Transmission Line Rules IBM
3.34 RF Interconnect Line and Transmission Line Rules
3.34.1 MA RF Interconnect Line Layout Rules
Table 97. MA RF Interconnect Line Rules

l Min. Dim
a
s
s
TL1b c (MA over MA_RFLINE) shape maximum width. 25.000 - -
TL2a c MA_RFLINE overlap past MA. 20.000 - -
TL2b c MA overlap past MA_RFLINE. 1.000 - -
TL2c c MA_RFLINE must touch MA.
TL3a c (MA over MA_RFLINE) shape minimum area(m2). 400.0 - -
TL3b c (MA over MA_RFLINE) shape minimum length. 100.0 - -
TL4a c (MA over MA_RFLINE) shape maximum area(m2). 37500 - -
TL4b c (MA over MA_RFLINE) shape maximum length. 1500.0 - -
TL5 c (MA over MA_RFLINE) must be within BFMOAT. 4.000 - -

1
TL6a c MA_RFLINE cannot touch any shape except (MA, F1, F1BAR, E1,BFMOAT,BF, (M1
not touching (CA or V1)), (M2 not touching (V1 or V2 or VL)), (M3 not touching (V2 or
V3 or VL)), (M4 not touching (V3 or V4 or VL)), (M5 not touching (V4 or V5 or VL)),
(M6 not touching (V5 or VL)), (MQ not touching (VL or VQ)), (MG not touching (VQ or
VG)), (LY not touching (FY or FT or FTBAR)).
TL6b c (MA over MA_RFLINE) space. 40.000 - -
TL9 c (MA over MA_RFLINE) must be rectangular.

1. The following levels are checked by DRC: DV, BP, QY, JD, LW, PV, NV, JN, JP, BB, DG, XW, XE, XF, PC, RR, RP, CABAR, NW,
OP, RX, LV, LVDUMMY, L1, LM, LM_RFLINE, OL, LD, QT, Kx (x=2,3,4), VxBAR x = 1,2,3,4,5,6,G,Q (unless VxBAR is already
verified in DRC by Rules 558 or 558a or 558b as defined in Table 33 on page 133).

Layout Rules RF Interconnect Line and Transmission Line Rules
3.34.2 LM RF Interconnect Line Layout Rules
Table 98. LM RF Interconnect Line Layout Rules
Rule C Notes Description Des. Waf Tol.

l Min. Dim
a
s
s
TL11b c (LM over LM_RFLINE) shape maximum width. 25.00 - -
TL12a c LM_RFLINE overlap past LM. 20.00 - -
TL12b c LM overlap past LM_RFLINE. 1.000 - -
TL12c c LM_RFLINE must touch LM.
TL13a c (LM over LM_RFLINE) shape minimum area(m2). 400.0 - -
TL13b c (LM over LM_RFLINE) shape minimum length. 100.0 - -
TL14a c (LM over LM_RFLINE) shape maximum area(m2). 37500 - -
TL14b c (LM over LM_RFLINE) shape maximum length. 1500 - -
TL15 c (LM over LM_RFLINE) must be within BFMOAT. 4.000 - -

1
TL16a c LM_RFLINE cannot touch any shape except (LM, VG, VGBAR, MG, VQ, VQBAR,
MQ, BFMOAT).
TL16b c (LM over LM_RFLINE) space. 40.00

2
TL17 c ((LM over LM_RFLINE) over ((MG touching {VG, VGBAR}) over LM_RFLINE)) can
not touch MQ. (LM RF Interconnect Line device can not have more than one LM-1
Metal level below it).
3
TL18 c ((LM over LM_RFLINE) over ((MQ touching {VQ, VQBAR}) over LM_RFLINE)) can
not touch MG). (LM RF Interconnect Line can not have more than one LM-1 Metal
level below it).
TL19 c (LM over LM_RFLINE) must be rectangular.
TL567a c ((VQBAR over LM_RFLINE) must be within MQ. 0.20 - -

((VGBAR over LM_RFLINE) must be within MG.
TL568a c ((VQBAR over LM_RFLINE) must be within (MG or LM). 0.20 - -

((VGBAR over LM_RFLINE) must be within LM.
TL675 c (VQBAR over LM_RFLINE) width. = 0.40 - -

(VGBAR over LM_RFLINE) width.
TL676 c ((VQBAR to VQBAR) over LM_RFLINE) space. 1.20 - -

((VGBAR to VGBAR) over LM_RFLINE) space.
1. The following levels are checked by DRC: PC, RX, BP, NW, PI, JD, Mx (x=1,2,3,4,5,6), {Vy, VyBAR} (y = 1,2,3,4,5,L), LW, PV, NV,
JN, JP, BB, DG, XW, XE, XF, RR, RP, OP, CABAR, DV, TV, TVDUMMY, LY, E1, MA, OL, LD, QT, Kx (x= 3,4,5,6).

Layout Rules Terminals, IO Pads, C4 and Wirebond IBM
2. LM RF Interconnect Line with MG shield can not also have a MQ metal shield level. The LM-1 metal level must be MG.
3. LM RF Interconnect Line with MQ shield can not also have a MG metal shield. The LM-1 metal level must be MQ.
3.34.3 Transmission Line Layout Rules
Table 99. Transmission Line Rules

l Min. Dim.
a
s
s
TLR1 a 1 xxEXCLUD must touch UNION {LYPIN, E1PIN, MAPIN}, = - - -

where xx = LY, E1, MA.
TLR1a a 1 xxEXCLUD must touch UNION {OLPIN, LDPIN}, where xx = - - -

= OL, LD.
1. For additional information on the design levels listed, see Table 6 on page 46 and Table 19 on page 87.
3.35 Terminals, IO Pads, C4 and Wirebond

Either C4 terminals or wirebond terminals may be used. Different C4 and wirebond termination mask levels
are used with either the LM or MA or OL with LD metallization options as discussed below.
Note: See Section 5.3.6 , Soft Error Rate on page 481 and Table 222, Adjustment Factors for I(dc) only,
for Temperature and Time on page 496 for additional information.
3.35.1 C4 Terminals with LM Last Metal

For C4 Reliability Design Rules, call your IBM technical representative.
Active C4 Terminals with LM last metal

The C4 structure is a solder ball over a transition metallurgy pad. This section describes the required design
rules for connecting a C4 terminal to the chip circuitry (an active C4). Section , Dummy C4 Terminals with LM
last metal on page 281 describes how dummy C4 terminals can be used.
An active C4 terminal makes contact with the final metal level through the FV via, and TD transfer pad and TV
via in the final passivation layer (polyimide, AlCu, nitride, oxide). The structure is shown in Figure 64, Rules
for C4 Terminals (with LM last metal. Oxide Pegs not shown in LM Pad) on page 280.
The guidelines below must be followed when designing a C4 pattern.
The outer row of pads must be asymmetrical on all four sides of the chip.

Layout Rules Terminals, IO Pads, C4 and Wirebond
The asymmetrical pad design is required within 2.34 mm of the true chip center for all chips larger than
10 mm on a side in one or both dimensions. The preferred pattern of asymmetry consists of three adja-
cent depopulated C4 sites surrounded by an area of fully populated sites. The three depopulated sites
should not be in the same row or the same column.
For standard C4 flip chip packages, the TV terminal to CHIPEDGE must be 500 m or less on at least
three sides of the chip for some C4s. Dummy C4 pads can be used to achieve this requirement.
The outer row of pads must be approximately the same distance from the edge of the chip on all sides.
Circular patterns of C4 pads are prohibited.
C4s are prohibited outside of CHIPEDGE.

C4 terminals connected to last wiring metal pads must not float. The metal must be connected to RX and
must satisfy the ESD rules given in Section 6.0. See also rule 908. Floating C4 terminals that use the
TVDUMMY level are permitted.
All designs with > 5000 tested pins must have prior approval from Test Probe Engineering.
Areas on the surface of the chip larger than 3mm x 3mm that do not have C4s is prohibited. See Rule 927
in Table 100 on page 278.
In addition, the following guidelines are recommended:
For designers who plan to characterize their designs prior to C4 processing by probing last metal pads,
the following recommendation should be observed to prevent probe damage to adjacent wiring: LM pad
to LM wiring should be at least 60 m
Using a 5 on 10 C4 size/pitch or fewer than the maximum number of C4 terminals per chip, typically
improves manufacturing yields. The 5 on 10 syntax refers to a 5mil solder bump on a 10mil pitch (1 mil
= 0.001 inch = 25.4 m). C4 solder ball sizes (wafer dimensions) are typically about 1 mil larger.
Note: The C4 terminal design must be reviewed with packaging and test groups. C4 terminal designs with
on-chip pitches of less than 230 m must be reviewed with probe engineering. Deviations from the above
guidelines or from the design rules in Table 100, C4 Layout Rules (Active and Dummy with LM last metal
level), on page 278 must be approved by IBM Terminal Metals engineering.

Table 100. C4 Layout Rules (Active and Dummy with LM last metal level)
C4 BLM/UBM solder ball diameter1,2,3 and pitch (Mil)
= 4 on 8 4 on 9 5 on 9 5 on 10
Number of C4s per 9000 9000 7100 7100

chip - max
Number of C4s per 3 3 3 3

chip - min
Rule C Notes Dimensions = Des 1x Des 1x Des 1x Des 1x

l Min Mask Min Mask Min Mask Min Mask
4 4
a 4 4
s
s
900 c 5,6,7 TV octagon dimension D. 47.00 64.00 47.00 64.00 47.00 64.00 47.00 64.00
900c a 8 TV/FV used for C4 pads must = - - - - - - - -

be octagonal.
901 c TV center to center. 200.00 200.00 225.00 225.00 225.00 225.00 250.00 250.00
902 c 9 (TV) within (LM) 14.00 5.500 14.00 5.500 14.00 5.500 14.00 5.500
(within outside edge of pad).
902p c 10 (TV) within (LM) 8.81 0.3100 8.81 0.3100 8.81 0.3100 8.81 0.3100
(within edge of oxide pegs).
902p1 c 11 TV must be covered by LM. = - - - - - - - -
903 c 9,12,7 TV must be within FV. 4.00 -8.50 4.00 -8.50 4.00 -8.50 4.00 -8.50
904 c 9 FV octagon dimension D. 55.00 47.00 55.00 47.00 55.00 47.00 55.00 47.00
905a c 13 FV to [union(TV(center) 112.50 112.50 112.50 112.50 125.00 125.00 125.00 125.00
,TVDUMMY(center))].
905b c FV to [union(TV(edge) 89.00 80.50 89.00 80.50 101.50 93.00 101.50 93.00
,TVDUMMY(edge))].
906 c 14,15 TV(center) within 118.00 118.00 118.00 118.00 136.00 136.00 136.00 136.00
CHIPEDGE.
906a c 15 TV(edge) within CHIPEDGE. 94.50 86.00 94.50 86.00 112.50 104.00 112.50 104.00
907 c 16 TV(center) to Chip Logo and 100.00 100.00 100.00 100.00 110.00 110.00 110.00 110.00
part number.
907a c 17 (TV(edge) to Chip Logo and 76.50 68.00 76.50 68.00 86.50 78.00 86.50 78.00
part number.
908 c 9,18,19 LM containing a TV shape = - - - - - - - -

must be connected to an RX
shape. This rule is exempt
when LM contains
TVDUMMY shapes.

Table 100. C4 Layout Rules (Active and Dummy with LM last metal level)
C4 BLM/UBM solder ball diameter1,2,3 and pitch (Mil)
= 4 on 8 4 on 9 5 on 9 5 on 10
Number of C4s per 9000 9000 7100 7100

chip - max
Number of C4s per 3 3 3 3

chip - min
Rule C Notes Dimensions = Des 1x Des 1x Des 1x Des 1x

l Min Mask Min Mask Min Mask Min Mask
4 4
a 4 4
s
s
911a c TVDUMMY must not touch = - - - - - - - -
TV.
927 c 20 CHIPEDGE must be within = - - - - - - - -

{[UNION (TV, TVDUMMY)]
sized by +1500.0m}.
1. Pad sizes/pitches smaller than 4 on 8 are not offered at this time.
2. For Mask ordering purposes when using Plated Bumps, both High Temp and Low Temp, a Mask Size 1mil smaller than the required Plated
bump diameter should be ordered. For example, for a 5mil Plated bump a 4mil mask should be ordered. The typical size of plated C4s
is 1 mil larger once they are built. C4 Plated ball sizes (wafer dimensions) are typically about 1 mil larger than the stated BLM/ UBM design
size.
3. IBM can manufacture a 4.5 on 9 offering. However, this offering is not preferred and is not being supported for the CMRF8SF technology.
Contact you IBM technical representative for additional information.
4. The dimensions in the Mask columns include the C4 design prep comps and scaling, but do not include wafer level biases.
5. The last metal outer perimeter pad size is (Rule 900 + 2x Rule 902). In this case (47+2x 14.00).
6. All TV rules apply to TVDUMMY unless otherwise noted. All TV, FV shapes (including TVDUMMY) in this table should be understood to be
TV/FV terminal vias for active C4s unless noted otherwise.
7. Octagon dimensions are given below and are required for C4 TV, TVDUMMY and FV shapes. Dimensions have tolerance of 0.10m
associated with them. Because of special design data prep done to octagon shapes on levels TV and FV, Rules 651a (TV area) and 655
(FV width) in Section 3.8.4 , TV, FV Layout Rules (for LM BEOL Metallization Option Only) on page 149, do not apply.
Octagon TV FV
Dimension
S D
D 47.00 55.00
S 19.48 22.84 Y
X, Y 13.76 16.08
X
8. Non-octagonal C4s will be removed from the dataset during design services and design preparation.
9. These rules do not apply to TVDUMMY designs.

10. This rule value is derived from the amount the TV shape is away from the innermost cheesing hole in the standard POR pad provided. Also,
this rule does not apply to TVDUMMY designs.
11. This rule does not apply to TVDUMMY.
12. Rule is not applicable to wirebond designs.
13. Rule 905a not coded in DRC. See equivalent Rule 905b. Rule 905b is coded in lieu of Rule 905a since some DRC verification tools can not
check Rule 905a which identifies a measurement to the TV center.
14. Rule 906 not coded in DRC. See equivalent Rule 906a. Rule 906a is coded in lieu of Rule 906 since some DRC verification tools can not
check Rule 906 which identifies a measurement to the TV center.
15. The minimum distance between the C4 center (Rule 906) or C4 edge (Rule 906a) and the diced chip edge is a critical parameter for certain
package types, especially flip chip plastic ball grid array packages. For specific applications, this minimum distance must be reviewed for
compliance with reliability restrictions.
16. Rule 907 not coded in DRC. See equivalent Rule 907a. Rule 907a is coded in lieu of Rule 907 since some DRC verification tools can not
check Rule 907 which identifies a measurement to the TV center.
17. The purpose of rule 907 is to prevent the chip identification from being obscured by the terminals. However, since there are typically multiple
occurrences of the PN on the chip, this rule need not be satisfied for all PN occurrences.
18. The metal must be connected to RX and must satisfy the ESD rules given in Section 3.12 , ESD Rules on page 190.
19. The connectivity net definition for this rule allows pass through for resistors which have an (OP intersect {RX or PC} aspect ratio of less than
100 to 1. This limits the resistance of pass through resistors.
20. Dummy C4s should be used to meet this density rule, if the requirement can not be met with active C4s.
900
TV IBM Logo and
907a Part Number
LM
902
FV 901 FV
TV
904 905a
906R
903 906a CHIPEDGE
Figure 64. Rules for C4 Terminals (with LM last metal. Oxide Pegs not shown in LM Pad)

C4 Terminal Pad Design (with LM last metal level)

IBM has designed a C4 pad compatible with the planarization requirement of copper damascene metal. This
pad MUST be used on all C4 products that use LM as the last metal. Figure 65, C4 Pad Design with LM pad
(not drawn to scale). on page 281 illustrates this design. Note that the oxide supports do not extend into the
TV shape, but are spaced according to Rule 902p. Further, the C4 pad area will be excluded from LMHOLE
generation by IBM Product Engineering or Design Services as defined in Rule H35c within Table 245,
xxHOLE Rules, on page 558.
Design On Wafer
TV TV
FV
FV
Last Cu Metal with Oxide Supports
Figure 65. C4 Pad Design with LM pad (not drawn to scale).
Dummy C4 Terminals with LM last metal

Dummy C4 terminals are electrically inactive. They may be designed to provide additional mechanical sup-
port or to enable the same C4 masks to be used for multiple part numbers. C4 dummy terminals are designed
by using the dummy level TVDUMMY instead of TV so that there is no TV opening in the nitride passivation.
Locate TVDUMMY anywhere that is consistent with the TV rules for designs in Table 100, C4 Layout Rules
(Active and Dummy with LM last metal level), on page 278 with the exception that rules 902, 903 and 908 do
not apply. Neither TV nor FV shapes may be located under TVDUMMY.

C4 Pb/Sn Solder Ball

BLM Films
FV Polyimide
TV Insulator TD Metal
LM Metal
Active C4 (TV/FV)
Figure 66. Active C4 Terminal Structures (with LM last metal)
BLM Films FV Polyimide no FV or TV (use TVDUMMY)
TV Insulator
Dummy C4
Figure 67. Dummy C4 Terminal Structure (with LM last metal)
3.35.2 C4 Terminals with MA Last Metal

Active C4 Terminals with MA last metal

rules for connecting a C4 terminal to the chip circuitry (an active C4). Dummy C4 Terminals with MA last
metal on page 286 describes how dummy C4 terminals can be used.
The active C4 terminal makes contact with the final metal level through the LV via in the final passivation layer
(polyimide, nitride, oxide). The structure is shown in Figure 69, Active and Dummy C4 Terminal Structures
(with MA last metal) on page 286.

10 mm on a side in one or both dimensions. The preferred pattern of asymmetry is three adjacent depop-
ulated C4 sites surrounded by an area of fully populated sites. The three depopulated sites should not be
in the same row or the same column.
For standard C4 flip chip packages, some C4s must be within 225 m of the CHIPEDGE (outer edge of
MA in the chip guard ring). LV terminal to CHIPEDGE (outer edge of MA in the chip guard ring) must be
250 m or less on at least three sides of the chip for some C4s. Dummy C4 pads can be used to achieve
this requirement.
C4s are prohibited outside of CHIPEDGE (C4s are not allowed outside the of the outer edge of MA in the
chip guard ring).
C4 terminals connected to the last wiring metal (MA) pads must not float. The metal must be connected
to RX and must satisfy the ESD rules given in section 7.0 , Electrostatic Discharge (ESD) on page 523.
See also rule MA908. Floating C4 terminals that use the LVDUMMY level are permitted.
Areas on the surface of the chip larger than 3mm x 3mm that do not have C4s is prohibited. See Rule
MA927 in Table 101 on page 284.
the following recommendation should be observed to prevent probe damage to adjacent wiring: MA pad
to MA wiring should be at least 30 m.
guidelines or from the design rules in Table 101, C4 Layout Rules (Active and Dummy with MA last metal
level) on page 284 must be approved by IBM Terminal Metals engineering.
Layout Rules MA901 in Table 101, C4 Layout Rules (Active and Dummy with MA last metal level) on
page 284, define the periodicity for 4 and 5 mil pads that are necessary for a product to function at PAS (Pad
Analysis System). Please note this periodicity is not the minimum diagonal spacing when staggered pads
are used. This is a larger number which is also listed. The pad periodicity is required in the perpendicular, or
X/Y direction. If the minimum pad spacings (diagonal) cannot be met the part may not be PAS checkable.
The pad periodicity can vary in the X and Y dimensions as long as the diagonal minimum value is met
(NOTE: Diagonal values cannot be checked by the DRC decks).
For MA C4 pads, LV is the Design Level for C4 Terminals and LV will be the generated Mask Level used to
manufacture C4 terminals. See Mask Level LV and Design Level LV in Table 2 on page 27.

MA900
MA901 Logo
MA907 and Part No.
MA
MA902b
MA906
CHIPEDGE LV
Figure 68. Rules for C4 Terminals (with MA last metal level)
Table 101. C4 Layout Rules (Active and Dummy with MA last metal level)
C4 BLM/UBM solder ball diameter and = 4 on 8 4 on 9 5 on

pitch1,2,3 10
Number of C4s per chip - max 9000 9000 7100
Number of C4s per chip - min 3 3 3
Rule C Notes Dimensions4 = Design Design Design

l
a
s
s
MA900 c 5,6 LV octagon dimension D. 47.00 47.00 47.00
MA900ab c 9 LV octagon must be within C4LV. 0.000 0.000 0.000
MA900b c 9 C4LV must touch LV. = - - -
MA900c a 7 LV/C4LV used for C4 pads must be octagonal. = - - -
MA901 c 8 LV center to center. 200.00 225.00 250.00
MA902b c 9 LV within MA. 19.0 19.0 19.0
MA906 c 10,11 LV within CHIPEDGE. 86.00 86.00 104.00
MA906R d 11 LV within CHIPEDGE. 101.00 101.00 113.00
MA907 c 12 LV to Chip Logo and PN (LV can not touch 64.00 64.00 80.00
LOGOBND).
9,13,14
MA908 c MA containing a LV shape must be connected to an RX shape (DC path, Float-
ing C4s are not allowed). MA containing LVDUMMY shapes are allowed.
15
MA909 c (LV or LVDUMMY) shapes must not touch (LM or FV or TV). (((TV or
TVDUMMY)) and (LV or LVDUMMY)) can not be used in the same chip design).
MA911a c 9 LVDUMMY touching {LV, C4LV} not allowed. = - - -

Table 101. C4 Layout Rules (Active and Dummy with MA last metal level)

pitch1,2,3 10

l
a
s
s
MA927 c 16 CHIPEDGE must be within {[UNION (LV, 0.0 0.0 0.0
LVDUMMY)] sized by +1,500.0m}.
1. For Mask ordering purposes when using Plated Bumps, both High Temp and Low Temp, a Mask Size 1mil smaller than the required
Plated bump diameter should be ordered. For example, for a 5mil Plated bump a 4mil mask should be ordered. The typical
size of plated C4s is 1 mil larger once they are built. C4 Plated bump sizes (wafer dimensions) are typically about 1 mil larger
than the stated BLM/ UBM design size.
4. See also Dummy C4 Terminals with MA last metal on page 286.
5. All LV shapes in this table should be understood to be LV terminal vias for active C4s unless noted otherwise.
6. Octagon dimensions are given below for the MA last metal level. Dimensions have a tolerance of 0.10 m associated with them. As
a part of design preparation during mask build, octagons will be converted to circles.
Octagon LV
Dimension
S D
D 47.00
S 19.50 Y
X, Y 13.75
X
8. Exact pitch design must be determined by matching to the package application.
9. These rules do not apply to LVDUMMY.
10. These rules are to keep the C4s from shorting to the KERF crackstop. Also, the minimum distance between the C4 edge and the diced
chip edge is a critical parameter for certain package types, especially flip chip plastic ball grid array packages. For specific
applications, this minimum distance must be reviewed for compliance with reliability restrictions.
11. Equivalent to LV within CHIPEDGE when CHIPEDGE is coincident with the outer edge of the chip guard ring per GR 999d in Table 114,
Chip Guard Ring Rules on page 319.
12. The purpose of rule 907 is to prevent the chip identification from being obscured by the terminals.
13. The metal must be connected to RX and must satisfy the ESD rules given in section 7.0 , Electrostatic Discharge (ESD) on page 523.
The connection to RX must be a DC path (not through a capacitor).

15. LV only allowed with the MA last metallization option, see Table 12, MA last metal Back End Of Line (BEOL) Metallization Options,
on page 65. LV and LVDUMMY are not allowed with the LM metallization options defined in Table 11, LM last metal Back End Of
Line (BEOL) Metallization Options, on page 64. For LM last metal, use TV/TD/FV as defined in Table 100, C4 Layout Rules (Active
and Dummy with LM last metal level), on page 278.
Dummy C4 Terminals with MA last metal

by using the dummy level LVDUMMY instead of LV so that there is no LV opening in the nitride passivation.
Locate LVDUMMY anywhere that is consistent with the LV rules for designs in Table 101, C4 Layout Rules
(Active and Dummy with MA last metal level) on page 284 with the exception that rules MA900ab, MA900b,
MA902b, MA908 and MA911a do not apply. LV shapes may not be located under LVDUMMY.

BLM
Polyimide
Oxide/Nitride
MA
Active C4
BLM
No LV (use LVDUMMY)
Polyimide
Oxide/Nitride
Dummy C4
Figure 69. Active and Dummy C4 Terminal Structures (with MA last metal)
NOTE: For definition of BLM or UBM, see section N.0, Definitions of Process-Related Terms on page 546.
3.35.3 C4 Terminals for LD Last Metal


Active C4 Terminals for LD last metal

rules for connecting a C4 terminal to the chip circuitry (an active C4). Section , Dummy C4 Terminals with LD
last metal on page 290 describes how dummy C4 terminals can be used.
(with LD last metal) on page 291.
For standard C4 flip chip packages, some C4s must be within 225 m of the CHIPEDGE. LV terminal to
CHIPEDGE must be 250 m or less on at least three sides of the chip for some C4s. Dummy C4 pads
can be used to achieve this requirement.
C4s are prohibited outside of CHIPEDGE.
C4 terminals connected to the last wiring metal (LD) pads must not float. The metal must be connected to
RX and must satisfy the ESD rules given in section 7.0 , Electrostatic Discharge (ESD) on page 523.
See also rule LD908. Floating C4 terminals that use the LVDUMMY level are permitted.
LD927 in Table 102 on page 288
the following recommendation should be observed to prevent probe damage to adjacent wiring: LD pad to
LD wiring should be at least 30 m.
guidelines or from the design rules in Table 102, C4 Layout Rules (Active and Dummy for LD last metal

Layout Rules LD901 in Table 102, C4 Layout Rules (Active and Dummy for LD last metal level) on
For OL with LD C4 pads, LV is the Design Level for C4 Terminals and LV will be the generated Mask Level
used to manufacture C4 terminals. See Mask Level LV and Design Level LV in Table 2 on page 27.
LD900
LD901 Logo
LD907 and Part No.
LD
LD902b
LD906
CHIPEDGE LV
Figure 70. Rules for C4 Terminals (with LD last metal level)
Table 102. C4 Layout Rules (Active and Dummy for LD last metal level)

pitch1,2,3 10

l
a
s
s
LD900 c 5,6 LV octagon dimension D. 47.00 47.00 47.00
LD900ab c 9 LV octagon must be within C4LV. 0.000 0.000 0.000
LD900b c 9 C4LV must touch LV. = - - -
LD900c a 7 LV/C4LV used for C4 pads must be octagonal. = - - -
LD901 c 8 LV center to center. 200.00 225.00 250.00
LD902b c 9 LV within LD. 19.0 19.0 19.0
LD906 c 10,11 LV within CHIPEDGE. 86.00 86.00 104.00
LD906R d 11 LV within CHIPEDGE. 101.00 101.00 113.00

Table 102. C4 Layout Rules (Active and Dummy for LD last metal level)

pitch1,2,3 10

l
a
s
s
LD907 c LV to Chip Logo and PN12 (LV can not touch 64.00 64.00 80.00
LOGOBND).
9,13,14
LD908 c LD containing a LV shape must be connected to an RX shape (DC path, Floating
C4s are not allowed). LD containing LVDUMMY shapes are allowed.
15
LD909 c (LV or LVDUMMY) shapes must not touch (LM or FV or TV). (((TV or TVDUMMY))
and (LV or LVDUMMY)) used in the same chip design is prohibited).
LD911a c 9 LVDUMMY touching {LV, C4LV} is prohibited. = - - -
LD913 b VV/VVBAR minimum space to LV (touching pro- 4.5 4.5 4.5

hibited)
LD927 c 16 CHIPEDGE must be within {[UNION (LV, 0.0 0.0 0.0

4. See also section , Dummy C4 Terminals with LD last metal on page 290.
6. Octagon dimensions are given below for the LD last metal level. Dimensions have a tolerance of 0.10 m associated with them. As a
part of design preparation during mask build, octagons will be converted to circles.
Octagon LV
Dimension
S D
D 47.00
S 19.50 Y
X, Y 13.75
X

11. Equivalent to LV within CHIPEDGE when CHIPEDGE is coincident with the outer edge of the chip guard ring per GR 999d in Table 114,
Chip Guard Ring Rules on page 319.
12. The purpose of rule LD907 is to prevent the chip identification from being obscured by the terminals.
15. LV only allowed with the OL with LD or MA last metallization option, see Table 12, MA last metal Back End Of Line (BEOL)
Metallization Options, on page 65 or Table 13, OL with LD last metal Back End Of Line (BEOL) Metallization Options, on page 66.
LV and LVDUMMY are not allowed with the LM metallization options defined in Table 11, LM last metal Back End Of Line (BEOL)
Metallization Options, on page 64. For LM last metal, use TV/TD/FV as defined in Table 100, C4 Layout Rules (Active and Dummy
with LM last metal level), on page 278.
Dummy C4 Terminals with LD last metal

(Active and Dummy for LD last metal level) on page 288 with the exception that rules LD900ab, LD900b,
LD902b, LD908 and LD911a do not apply. LV shapes may not be located under LVDUMMY.


BLM
Polyimide
Oxide/Nitride
LD
Active C4
BLM
No LV (use LVDUMMY)
Polyimide
Oxide/Nitride
Dummy C4
Figure 71. Active and Dummy C4 Terminal Structures (with LD last metal)
3.35.4 C4 Terminals with AM Last Metal

Active C4 Terminals with AM last metal

rules for connecting a C4 terminal to the chip circuitry (an active C4). Section , Dummy C4 Terminals with
AM last metal on page 294 describes how dummy C4 terminals can be used.
(with AM last metal) on page 295.
For standard C4 flip chip packages, some C4s must be within 225 m of the CHIPEDGE (outer edge of
AM in the chip guard ring). LV terminal to CHIPEDGE (outer edge of AM in the chip guard ring) must be

250 m or less on at least three sides of the chip for some C4s. Dummy C4 pads can be used to achieve
this requirement.
C4s are prohibited outside of CHIPEDGE (C4s are not allowed outside the of the outer edge of MA in the
chip guard ring).
C4 terminals connected to the last wiring metal (AM) pads must not float. The metal must be connected
to RX and must satisfy the ESD rules given in section 7.0 , Electrostatic Discharge (ESD) on page 523.
See also rule AM908. Floating C4 terminals that use the LVDUMMY level are permitted.
AM927 in Table 103 on page 293.
the following recommendation should be observed to prevent probe damage to adjacent wiring: AM pad
to AM wiring should be at least 30 m.
guidelines or from the design rules in Table 103, C4 Layout Rules (Active and Dummy with AM last metal
Layout Rules AM901 in Table 103, C4 Layout Rules (Active and Dummy with AM last metal level) on
For AM C4 pads, LV is the Design Level for C4 Terminals and LV will be the generated Mask Level used to
manufacture C4 terminals. See Mask Level LV and Design Level LV in Table 2 on page 27.
AM900
AM901 Logo
AM907 and Part No.
AM
AM902b
AM906
CHIPEDGE LV

Figure 72. Rules for C4 Terminals (with AM last metal level)
Table 103. C4 Layout Rules (Active and Dummy with AM last metal level)

pitch1,2,3 10

l
a
s
s
AM900 c 5,6 LV octagon dimension D. 47.00 47.00 47.00
AM900ab c 9 LV octagon must be within C4LV. 0.000 0.000 0.000
AM900b c 9 C4LV must touch LV. = - - -
AM900c a 7 LV/C4LV used for C4 pads must be octagonal. = - - -
AM901 c 8 LV center to center. 200.00 225.00 250.00
AM902b c 9 LV within AM. 19.0 19.0 19.0
AM906 c 10,11 LV within CHIPEDGE. 86.00 86.00 104.00
AM906R d 11 LV within CHIPEDGE. 101.00 101.00 113.00
AM907 c 12 LV to Chip Logo and PN (LV can not touch 64.00 64.00 80.00
LOGOBND).
9,13,14
AM908 c AM containing a LV shape must be connected to an RX shape (DC path, Floating
C4s are not allowed). AM containing LVDUMMY shapes are allowed.
15
AM909 c (LV or LVDUMMY) shapes must not touch (LM or FV or TV). (((TV or TVDUMMY))
and (LV or LVDUMMY)) can not be used in the same chip design).
AM911a c 9 LVDUMMY touching {LV, C4LV} not allowed. = - - -
AM927 c 16 CHIPEDGE must be within {[UNION (LV, 0.0 0.0 0.0

4. See also section , Dummy C4 Terminals with AM last metal on page 294.

6. Octagon dimensions are given below for the MA last metal level. Dimensions have a tolerance of 0.10 m associated with them. As
a part of design preparation during mask build, octagons will be converted to circles.
Octagon LV
Dimension
S D
D 47.00
S 19.50 Y
X, Y 13.75
X
11. Equivalent to LV within CHIPEDGE when CHIPEDGE is coincident with the outer edge of the chip guard ring per GR 999a1 in
Table 114, Chip Guard Ring Rules on page 319.
12. The purpose of rule 907 is to prevent the chip identification from being obscured by the terminals.
15. LV only allowed with the AM last metallization option, see Table 14, AM last metal Back End Of Line (BEOL) Metallization Options,
on page 67. LV and LVDUMMY are not allowed with the LM metallization options defined in Table 11, LM last metal Back End Of
Line (BEOL) Metallization Options, on page 64. For LM last metal, use TV/TD/FV as defined in Table 100, C4 Layout Rules (Active
and Dummy with LM last metal level), on page 278.
Dummy C4 Terminals with AM last metal

(Active and Dummy with AM last metal level) on page 293 with the exception that rules AM900ab, AM900b,
AM902b, AM908 and AM911a do not apply. LV shapes may not be located under LVDUMMY.


BLM
Polyimide
Oxide/Nitride
AM
Active C4
BLM
No LV (use LVDUMMY)
Polyimide
Oxide/Nitride
Dummy C4
Figure 73. Active and Dummy C4 Terminal Structures (with AM last metal)
3.35.5 Wirebond Terminals with LM (and TD) Last Metal Level

Because packaging requirements vary widely across the industry, the Wirebond pad layout rules may differ at
each fabrication site. Consult your fab representative for more information.
The following rules are based on IBM performing the packaging and wafer level testing. If these functions are
performed elsewhere then the requirements may differ. Also see section 3.35.11 , Wire-bond Part Testing
and Packaging Restrictions on page 313.
The size of the wire bond pads that are standard for this technology are for gold ball bonds. If you or your
customer plan to use a wedge bond you will need to increase the size of the bond pad to accommodate the
bonding wedge.

In-Line and Staggered Wirebond Rules (with LM last metal)
Table 104. In-Line and Staggered Wirebond Rules (with LM and TD last metal levels)1,2

l Min.
a
s
s
WB02 c TD shapes must be rectangular.
WB03 c TD to TD terminal pad space. 2.00
WB04 c (TD not touching FINE_WB) terminal pad width (parallel to the clos- 58.00
est chipedge).
WB05 c (TD touching PROBE) terminal pad length (perpendicular to the clos- 117.00
est chipedge).
WB05cd c (TD not touching FINE_WB) terminal pad length (perpendicular to the 74.00
closest chipedge) for bonding only (probing is prohibited).
WB06 c TV terminal contact must be within TD. 3.00
WB08 c DV(touching TD) terminal pad must be within TD. 3.00
940 c DV(touching TD) within PROBE. 0.00
940a1 c PROBE must touch DV. = -
940a2 c PROBE must be within TD. 0.00
941c c DV(touching TD) terminal pad center to center (single row of pads). 60.00
S941c c DV(touching TD) terminal pad center to center (parallel dimension 60.00
closest to CHIPEDGE, staggered pads, both inner and outer rows).
942c c DV(touching TD) terminal pad to {EFUSE, DI, IND, IND_FILT, 3.00
LM_RFLINE, TRANSMIS, SRAMPC, SRAMRX, SRAMM1,
SRAMCA, Kx (x=3,4,5,6), VNCAP}.
943 c DV to TV (DV touching TV is prohibited). 6.00
945cR d DV(touching TD) terminal pad must be within CHIPEDGE (maximum) 190.00
(measured from the closest edge of the DV to the perimeter of the
chipedge).
945d c DV(touching TD) terminal pad must be within CHIPEDGE (maximum, 275.00
entire DV shape).
946a c 3 TV terminal contact length (dimension parallel to CHIPEDGE). 28.00
946ca c ((DV touching TD) not touching FINE_WB) terminal pad width (paral- 52.00
lel to the closest CHIPEDGE).

Table 104. In-Line and Staggered Wirebond Rules (with LM and TD last metal levels)1,2

l Min.
a
s
s
946cc c DV(touching TD, over PROBE) terminal pad length (perpendicular to 95.00
the closest CHIPEDGE).
946cd c DV(touching TD) terminal pad length (perpendicular to the closest 52.00
CHIPEDGE) for bonding only (probing is prohibited).
948a c 4 TV terminal contact must be within LM. 3.00
951 c ((DV touching TD) expanded by Rule WB08) terminal pad over {EFUSE, DI, IND,
IND_FILT, LM_RFLINE, TRANSMIS, SRAMPC, SRAMRX, SRAMM1, SRAMCA,
Kx (x=3,4,5,6), VNCAP} is prohibited.
This rule also is intended to prohibit SRAMs or Dense SRAMs below a (DV
expanded by Rule WB08) Terminal Pad, which includes the Dense SRAM derived
mask levels CF, D1, VE, which are not verified.
5
951a c ((DV touching TD) expanded by Rule WB08) terminal pad touching {L1, MA,
MA_RFLINE, E1, LY, LV, LD, OL, QT} is prohibited.
952 c For LM BEOL designs with exactly 5 levels of metal, {OP, PC over (RX expanded
by +0.14m per edge)} must not touch ((DV(touching TD)) expanded by Rule
WB08) terminal pad.
6,7
953 c LM containing a TV terminal contact wire-bond pad connection must be connected
to a RX shape. (Floating wirebond pads are prohibited).
S955c c DV(touching TD) terminal pad space (dimension perpendicular to 26.00

CHIPEDGE, between staggered row of wirebond pads).
957 c (Mx over (DV touching TD)) space for designs having (x+2) or more metal levels
must follow Rule 502, 504R, and 504d in Table 33 on page 133, and Rules 602,
604R and 604d in Table 34 on page 141, where x = 1,2,3,4,5,6.
1. See Figure 74, In Line Wirebond Rules (with LM last metal) on page 298 or Figure 76, Staggered Wirebond Rules (with LM last
metal) on page 299. Rules that start with the letter S apply to staggered designs only.
2. All references to DV or DV(touching TD) in this table refer to openings in the passivation above a wirebond pad for the LM last metal
options, unless otherwise noted.
3. Rule 650a in Table 36, TV and FV Rules for LM Metal Options on page 149 governs the TV width perpendicular to the CHIPEDGE.
4. The maximum (LM width rule, just below (TV sized by Rule 948a per edge) is exempt for wirebond pads. See Rule 635b in Table 35,
LM (Thick) Metal Layout Rules on page 147.
5. This rule may be omitted from DRC if there are other methods that non LM BEOL metallization levels are reported as DRC violations if
concurrently used with LM BEOL metallization levels. Vias are not listed since vias must be within their metal above or design level
or metal below, which are validated by this layout rule.
6. The metal must be connected to RX and must satisfy the ESD Rules, see Section 6.0.

Design
,Levels:
EFUSE,
DI, IND,
941c IND_FILT,
LM LM_RFLINE,
Terminal Contact TRANSMIS,
WB06 948a Kx, SRAMxx
or for 5LM
BEOL,: OP,
946a 650a TV PC over (RX
WB05/WB05cd sized +0.14)
943 942c
942c,
See DV 951,
Bonding 946ca 952
versus
Probing (951a not shown)
Figure
Terminal Pad
945d Opening
TD
WB04
WB08 658ab 945cR
WB03
CHIPEDGE
Figure 74. In Line Wirebond Rules (with LM last metal)

LM LM
TV TV
WB05 WB05cd
946cc 946cd
DV
DV
DV Terminal Pad for Wirebond and NO Probing
PROBE
940, 940a1, 940a2
DV Terminal Pad for Probing and Wirebond
Figure 75. Wirebond Pad Layout (for Probing versus Wirebond Only)
Figure 76. Staggered Wirebond Rules (with LM last metal)
Fine Pitch Wirebond Rules (with LM last metal)

Note: The fine-pitch wire-bond design rules in Table 105 supersede the inline and staggered wire-bond
design rules in Table 104 on page 296. All inline design rules not superseded by fine-pitch wire-bond design
rules still apply to fine-pitch wire-bond pads.
For the fine-pitch wire-bond option, note the following restrictions:
The fine-pitch wire-bond option requires a wire diameter less than 25m. Contact your IBM technical rep-
resentative for more information.
The fine-pitch wire-bond option is not offered with staggered wire-bond pads.
Multiple-device-under-test (DUT) probe testing with the fine-pitch wire-bond option requires prior
approval from your IBM technical representative. If testing is approved, designers must provide the x- and

y- coordinates for the center of the probe region for each new device probe request to IBM Test Engineer-
ing because this location is offset from the center of the pad opening.
Table 105. Fine Pitch In-Line and Staggered Wire-Bond Rules (with LM and TD last metal levels)1,2

l Min.
a
s
s
WB04a c (TD touching FINE_WB) terminal pad width (parallel to the closest 50.00
chipedge).
WB05a c (TD touching (PROBE touching FINE_WB)) terminal pad length (per- 139.00
pendicular to the closest chipedge).
WB05ca c (TD touching FINE_WB) terminal pad length (perpendicular to the 66.00
closest chipedge) for bonding only (probing is prohibited).
940a c 3 DV within FINE_WB. 0.00
940a3 c FINE_WB must touch DV. = -
940a4 c FINE_WB must be within TD. 0.00
941caR d 3,4,5
DV(touching TD, covered by FINE_WB) terminal pad center to center 52.00
(single row of pads).
945da c Only in-line wire-bond option is offered with fine-pitch wire-bond lay- = -
out. Staggered wire-bond option is prohibited.
946cb c DV(touching TD, touching by FINE_WB) terminal pad width and 44.00
length (must be square) ( probing is prohibited).
946ce c DV(touching TD, touching (PROBE touching FINE_WB) terminal pad 117.00
length (perpendicular to the closest CHIPEDGE).
946cf c DV(touching TD, touching (PROBE touching FINE_WB)) terminal 44.00

pad width (parallel to the closest CHIPEDGE).
1. See Figure 74, In Line Wirebond Rules (with LM last metal) on page 298 or Figure 76, Staggered Wirebond Rules (with LM last
metal) on page 299. Rules that start with the letter S apply to staggered designs only.
2. All references to DV or DV(touching TD) in this table refer to openings in the passivation above a wirebond pad for the LM last metal
options, unless otherwise noted.
3. All references to DV refer to openings in the passivation layer above a wire-bond pad unless otherwise noted.
4. This Rule assumes that dummy design level FINE_WB is present, and PROBE is or is not present
5. Rule 941caR = Rule 946cb + 657b.

LM LM
TV TV
WB05a
946cb WB05ca
946ce
FINE_WB DV
940a, 940a3, 940a4
DV
WB04a
Fine-Pitch Terminal Pad for
Wire-bonding Only (No Probing)
PROBE and FINE_WB
940, 940a, 940a1, 940a2
WB04a
Fine-Pitch Terminal Pad for

probing and Wire-bonding
Figure 77. Fine-pitch Wire-bond Pad Design Rules
Figure 78. Probe and Wire-bond Regions in a Fine-pitch Terminal Pad

LM
TV
Wire-bond Region
52 m
DV
Probe Region
65 m (Closest to CHIPEDGE)
CHIPEDGE
3.35.6 Wirebond with MA Last Metal

Note: The size of the wire bond pads that are standard for this technology are for gold ball bonds. If you or
your customer plan to use a wedge bond you will need to increase the size of the bond pad to accommodate
the bonding wedge.
RF device performance is not characterized or qualified below wirebond pads. For more information, contact
your IBM technical representative.
Table 106. MA Wirebond Rules

l Min.
a
s
s
MA940 c DV(touching MA) touching {PROBE, FINE_WB} is prohibited. -
MA941b c 1 DV(touching MA) terminal pad center to center (single row of pads). 73.00

Table 106. MA Wirebond Rules

l Min.
a
s
s
MA942b c DV(touching MA) terminal pad to {EFUSE, L1, QY, HY, F1, F1BAR, 3.00
E1, FT, FTBAR, LY, FY, FYBAR, DI, IND, IND_FILT, MA_RFLINE,
TRANSMIS, SRAMPC, SRAMRX, SRAMM1, SRAMCA,
LOGOBND, Kx (x=2,3,4), VNCAP}.
MA944b c DV(touching MA) must be within CHIPEDGE (minimum). 16.000
MA945b c DV(touching MA) must be within CHIPEDGE (maximum) (entire DV 150.00

shape).
MA946b c DV(touching MA) terminal pad width (parallel to the closest 62.00
CHIPEDGE) (must be rectangular).
MA946g c DV(touching MA) terminal pad length (perpendicular to the closest 95.00
CHIPEDGE) (increasing the dimension perpendicular to
CHIPEDGE does not impact the pitch).
MA948b1 c DV(touching MA) terminal pad must be within MA. 3.00
MA951 c (DV(touching MA) expanded by Rule MA948b1) terminal pad over -

{EFUSE, L1, QY, HY, F1, F1BAR, E1, FT, FTBAR, LY, FY, FYBAR,
DI, IND, IND_FILT, MA_RFLINE, TRANSMIS, SRAMPC, SRAMRX,
SRAMM1, SRAMCA, LOGOBND, Kx (x=2,3,4), VNCAP} is prohib-
ited.
This rule is also intended to prohibit SRAMs or Dense SRAMs below
a (DV(touching MA) expanded by Rule MA948b1) Terminal Pad,
which includes the Dense SRAM derived mask levels CF, D1, VE,
which are not verified.
MA951a c 2 ((DV touching MA) expanded by Rule MA948b1) terminal pad -

touching {LM, TD, TV, FV, LM_RFLINE, LD, OL, QT} is prohibited.
3,4
MA953 c MA containing a DV(touching MA) wirebond pad must be connected to an RX
shape (Floating DV wirebond pads are not allowed).
MA954 c Mx enclosed areas under (DV(touching MA) expanded by Rule MA948b1 per
edge) not allowed (x=1,2,3,4,Q,G).
MA956 c 1 Mx (x=1,2,3,4,Q,G) over (DV(touching MA) expanded by Rule 5.88

MA948b1 per edge) width (maximum).
1
MA957 c (Mx over (DV(touching MA) expanded by Rule MA948b1 per edge)) space for
designs having (x+2 or more levels of metals including MA) must follow Rules
502, 504R, 504d, 602, 604R, and 604d, where x=1,2,3,4.
1. All references to DV(touching MA) refer only to openings in the passivation above a wirebond pad unless otherwise noted.
2. This rule may be omitted from DRC if there are other methods that non MA BEOL metallization levels are reported as DRC violations if
concurrently used with MA BEOL metallization levels. Vias are not listed since vias must be within their metal above or design level
or metal below, which are validated by this layout rule

Note: If the pitch used is less than 90 m, the designer must take into account that there may be unique
packaging and test requirements. Designs that use a tight pitch should be reviewed with the IBM Technical
Representative
There may be special concerns when minimum pitch is used near chip corners. It is required that designs
with tight pitches in the corners be reviewed with the IBM Technical Representative prior to completion of the
design.
MA941b
MA
MA
946g MA946b
DV
MA948b1 MA942b
MA951
MA951a
MA945b
MA944b
CHIPEDGE
Figure 79. In Line Wirebond Rules ( for MA last metal)
3.35.7 LD Terminal Metal (with OL wiring)

LD is the terminal pad metal used with OL wiring and LD can also be used as a final wiring level and for
inductors. LD process has Wirebond and C4 options for terminal connections. Via VV connects LD to OL
below. Chip connection to LD is through via DV (Wirebond) or LV (C4) above LD.
3.35.8 Wirebond for LD Last Metal (with OL wiring)

the bonding wedge.
Note: Staggered wirebonds are not offered.

Table 107. In-Line Wirebond Rules (with LD last metal level)

l Min.
a
s
s
940LD c (DV touching LD) touching {PROBE, FINE_WB} is prohibited. -
WB08LD c (DV touching LD) must be within LD. 3.00
941cLD c 1,2
(DV touching LD) terminal pad center to center (single row of pads). 73.00
942cLD c (DV touching LD) terminal pad to {OL,QT, EFUSE, DI, IND, 3.00
IND_FILT, TRANSMIS, SRAMPC, SRAMRX, SRAMM1, SRAMCA,
Kx (x=2,3,4,5), LOGOBND, VNCAP}.
943LD c DV to VV (DV touching VV is prohibited). 4.68
945cLDR d (DV touching LD) terminal pad must be within CHIPEDGE (maxi- 190.00
mum) (measured from the closest edge of the DV to the perimeter
of the chipedge).
945dLD c (DV touching LD) terminal pad must be within CHIPEDGE (maxi- 230.00
mum, entire DV shape).
946caLD c (DV touching LD) terminal pad width (parallel to the closest 62.00
CHIPEDGE).
946cdLD c (DV touching LD) terminal pad length (perpendicular to the closest 95.00
CHIPEDGE) for bonding only (probing is prohibited).
951LD c ((DV touching LD) expanded by Rule WB08LD) terminal pad over {OL, QT,
EFUSE, DI, IND, IND_FILT, TRANSMIS, SRAMPC, SRAMRX, SRAMM1,
SRAMCA, Kx (x=2,3,4,5), LOGOBND, VNCAP} is prohibited.
This rule also is intended to prohibit SRAMs or Dense SRAMs below a (DV
expanded by Rule WB08) Terminal Pad, which includes the Dense SRAM
derived mask levels CF, D1, VE, which are not verified.
3
951aLD c ((DV touching LD) expanded by Rule WB08LD) terminal pad touching {LM, TD,
TV, FV, LM_RFLINE, L1, MA, MA_RFLINE, E1, LY, OL, QT} is prohibited.
952LD c For LD BEOL designs with exactly 5 levels of metal, {OP, PC over (RX expanded
by +0.14m per edge)} must not touch ((DV(touching LD)) expanded by Rule
WB08LD) terminal pad.
4,5
953LD c (LD touching DV) must be connected to a RX shape. (Floating wirebond pads are
prohibited).
957LD c (Mx over (DV touching LD)) must follow Rules 502, 504R, and 504d in Table 33
on page 133, and Rules 602, 604R and 604d in Table 34 on page 141, where x =
1,2,3,4,5.
1. Rule may alternatively be coded using Rule LD657b if center-to-center verification is a known verification limitation.

2. See Rule LD04a1 in Table 47 on page 164 for minimum LD metal spacing for wirebond pads, since (LD touching DV) in the wire bond
area must be greater than or equal to 70m in width per Rule 946caLD plus two times Rule WB08LD.
3. This rule may be omitted from DRC if there are other methods that non OL with LD BEOL metallization levels are reported as DRC
violations if concurrently used with OL with LD BEOL metallization levels. Vias are not listed since vias must be within their metal
above or design level or metal below, which are validated by this layout rule.
4. The metal must be connected to RX and must satisfy the ESD Rules, see Section 6.0.
Representative
design.
Note: Rule 940LD, 953LD and Rule 957LD are not shown.
941cLD 941cLD
OL VV 948a
via WB06LD
LD Terminal
Contact
OL
943LD 942cLD
DV 942cLD
951LD
946caLD 951aLD
DV 952LD
DV
946cdLD
Terminal Pad
945dLD Opening
LD
WB08LD 658ab 945cLDR
LD04a1
CHIPEDGE
Figure 80. In Line Wirebond Rules ( for LD last metal)

3.35.9 Wirebond with AM Last Metal

the bonding wedge.
Table 108. AM Wirebond Rules

l Min.
a
s
s
AM940 c DV(touching AM) touching {PROBE, FINE_WB} is prohibited. -
AM941b c 1 DV(touching AM) terminal pad center to center (single row of pads). 73.00
AM942b c DV(touching AM) terminal pad to {EFUSE, FQ, MQ, DI, IND, 3.00
IND_FILT, TRANSMIS, SRAMPC, SRAMRX, SRAMM1, SRAMCA,
LOGOBND, K5, VNCAP}.
AM944b c DV(touching AM) must be within CHIPEDGE (minimum). 16.000
AM945b c DV(touching AM) must be within CHIPEDGE (maximum) (entire DV 150.00

shape).
AM946b c DV(touching AM) terminal pad width (parallel to the closest 62.00
CHIPEDGE) (must be rectangular).
AM946g c DV(touching AM) terminal pad length (perpendicular to the closest 95.00
CHIPEDGE) (increasing the dimension perpendicular to
CHIPEDGE does not impact the pitch).
AM948b1 c DV(touching AM) terminal pad must be within AM. 3.00
AM951 c (DV(touching AM) expanded by Rule AM948b1) terminal pad over -

{EFUSE, FQ, MQ, DI, IND, IND_FILT, TRANSMIS, SRAMPC,
SRAMRX, SRAMM1, SRAMCA, LOGOBND, K5, VNCAP} is pro-
hibited.
This rule is also intended to prohibit SRAMs or Dense SRAMs
below a (DV(touching AM) expanded by Rule AM948b1) Terminal
Pad, which includes the Dense SRAM derived mask levels CF, D1,
VE, which are not verified.
AM951a c 2 ((DV touching AM) expanded by Rule AM948b1) terminal pad -

touching {LM, TD, TV, FV, LM_RFLINE, LD, OL, QT, MA} is prohib-
ited.
3,4
AM953 c AM containing a DV(touching AM) wirebond pad must be connected to an RX
shape (Floating DV wirebond pads are not allowed).
AM954 c Mx enclosed areas under (DV(touching AM) expanded by Rule AM948b1 per
edge) not allowed (x=1,2,3,4,5,Q).

Table 108. AM Wirebond Rules

l Min.
a
s
s
AM956 c 1 Mx (x=1,2,3,4,5,Q) over (DV(touching AM) expanded by Rule 5.88

AM948b1 per edge) width (maximum).
1
AM957 c (Mx over (DV(touching AM) expanded by Rule AM948b1 per edge)) space for
designs having (x+2 levels of metal including AM) must follow Rules 502, 504R,
504d, 602, 604R, and 604d, where x=5.
1. All references to DV(touching AM) refer only to openings in the passivation above a wirebond pad unless otherwise noted.
2. This rule may be omitted from DRC if there are other methods that non AM BEOL metallization levels are reported as DRC violations if
concurrently used with AM BEOL metallization levels. Vias are not listed since vias must be within their metal above or design level
or metal below, which are validated by this layout rule
Representative
design.
AM941b
AM
AM
946g AM946b
DV
AM948b1 AM942b
AM951
AM951a
AM945b
AM944b
CHIPEDGE
Figure 81. In Line Wirebond Rules ( for AM last metal)

3.35.10 Modelled Wirebond and C4 Bondpads
Introduction:
Modelled Bondpads are offered that simulate the loading effect of an C4 pad or wirebond pad over four pos-
sible groundplanes: BFMOAT, PC, RX or M1. For additional information, see section 4.35 , Bondpad Mod-
els on page 436. LM and MA or OL with LD metallization option bondpad model Layout Rules are included in
section , Modelled Wirebond and C4 Bondpad Layout Rules on page 310.
Local Pattern Density Considerations For Modelled Bondpads

All local pattern density layout rules must be satisfied when using modelled Bondpads, that include the
BONDPAD design level, prior to design submission to IBM.
Note: The PC and Mx (x=1,2,3,4,5,6,Q,G), LM, OL, LY, or E1 local density requirements may be more easily
satisfied compared to the RX local density requirements for the modelled bondpads, as described below.
Note: For information on IBM generated autofill for the BONDPAD design level, see Table 244, xxFILL
Rules, on page 549.
RX Local Pattern Density Considerations Using the BONDPAD Design Level
The RX local pattern density layout Rules EPDL_RX and 41 (see Table 21 on page 95) must be satisfied
when using modelled bondpads prior to design submission to IBM.
Note: The use of the design level BONDPAD, which is used to define modelled wirebond or C4 bondpads,
may not always satisfy the RX local pattern density Rule EPDL_RX for every design. Contact your IBM tech-
nical representative for more information.
The RX groundplane modelled bondpad should not affect a designers ability to meet RX local pattern
density requirements.
Use of the BFMOAT or PC or M1 Groundplane modelled bondpads may affect a designers ability to meet
the requirements of RX local pattern density Rule EPDL_RX.
- For the BFMOAT or M1 modelled bondpad, low density IBM auto-generated RXFILL is placed within
the BFMOAT design level. As a result, placement of the modelled BFMOAT bondpad may not always
satisfy the RX local pattern density Rule EPDL_RX, especially when modelled BFMOAT bondpads
are placed in closed proximity to other devices that do not contain the RX design level, or are placed
in close proximity to other design levels that prohibit the placement of IBM auto-generated RXFILL.
- The RX local pattern density requirement may not always be achieved for modelled bondpads that
include the PC groundplane.
IBM auto-generated RXFILL is suppressed from being placed under the modelled PC ground-
plane.
The RX local density requirement may not be met when multiple modelled PC groundplane bond-
pads are placed in close proximity, or are placed in close proximity to other devices that do not
contain the RX design level, or are placed in close proximity to other design levels that prohibit
the placement of IBM auto-generated RXFILL.
Note: The use of the modelled PC groundplane bondpad, or use of large or multiple modelled PC
groundplane bondpads in close proximity, is not recommended except if Rule EPDL_RX is satisfied.

Modelled Wirebond and C4 Bondpad Layout Rules
Common BONDPAD Layout Rules
The rules in the Table 109 are for terminals which include the BONDPAD shape for C4 or Wirebond LM, MA
or OL with LD metallization options, for the BFMOAT, PC or RX or M1 groundplane offerings.
Table 109. Common Layout Rules for C4 or Wirebond LM, MA or OL with LD Metallization Option M1 Modelled Pads

l .
a Min.
s
s
BONDPAD3c a (BONDPAD touching M1) must be within BFMOAT. 0.00
BONDPAD3c1 a 1
(BONDPAD touching {BFMOAT, M1}) touching {RX. PC} is pro- = -
hibited.
BONDPAD4c a BONDPAD minimum space to M2 with touching prohibited. 1.00
BONDPAD6c a (RX touching BONDPAD) must be within BP. 0.00
BONDPAD7c a ((RX touching PC) over BONDPAD) not allowed.

1. Auto-generated RXFILL or PCFILL are allowed below modelled M1 Groundplane pads, and are accounted for in the modelled
device.
OL with LD Metallization BONDPAD Layout Rules
The rules in the Table 110 are for terminals which include the BONDPAD shape for the OL with LD BEOL
metallization options, for both for wirebond (DV) and C4 (LV) terminations as defined in Table 13 on page 66
and are therefore extracted as a device instead of a parasitic. The BONDPAD device has the parasitic capac-
itance (to BFMOAT or PC or RX or M1) included in the model. If other design levels are under the pad, the
parasitics are altered, so the bondpad should be extracted with parasitics rather than as a device (i.e. remove
the BONDPAD shape).
Table 110. Pad Model Rules for C4 and Wirebond for OL with LD Metallization

l Min.
a
s
s
BONDPAD1b c BONDPAD overlap past LD. 0.10
BONDPAD3b c 1 (LD over BONDPAD) must be within (BP or BFMOAT or (the outer 4.90
edge of the (PC[Lattice] touching BONDPAD)) or (the outer edge
of the (RX[Lattice] touching BONDPAD))).
BONDPAD4b c 2 (LD over BONDPAD) to {BB, NW, Mx (x=3,4,5,Q,G), OL, (PC out- 4.90
side BONDPAD)}. ((LD over BONDPAD) touching {BB, NW, Mx
(x=3,4,5,Q,G), OL} not allowed).

Table 110. Pad Model Rules for C4 and Wirebond for OL with LD Metallization

l Min.
a
s
s
BONDPAD5b c (LD over BONDPAD) to (RX outside of BONDPAD). 3.50

1. (RXHOLE within the outer edge of the RX[Lattice]) or (PCHOLE within the outer edge of the PC[Lattice]) groundplane are exempt
from this rule.
2. PC is intentionally omitted from the touching description of Rule BONDPAD4. PC{Lattice] is permitted below (LD over BONDPAD) as
described in Rules BONDPAD3b.
LM Metallization BONDPAD Layout Rules
The rules in the Table 111 are for terminals which include the BONDPAD shape for the LM BEOL metalliza-
tion options, for both for wirebond (DV) and C4 (LV) terminations as defined in Table 11 on page 64 and are
therefore extracted as a device instead of a parasitic. The BONDPAD device has the parasitic capacitance
(to BFMOAT or PC or RX or M1) included in the model. If other design levels are under the pad, the parasitics
are altered, so the bondpad should be extracted with parasitics rather than as a device (i.e. remove the
BONDPAD shape).
Table 111. Pad Model Rules for C4 and Wirebond with LM Metallization

l Min.
a
s
s
BONDPAD1a c BONDPAD overlap past (LM or TD). 0.10
BONDPAD3a c 1 ((LM or TD) over BONDPAD) must be within (BP or BFMOAT or 4.90
(the outer edge of the (PC[Lattice] touching BONDPAD)) or (the
outer edge of the (RX[Lattice] touching BONDPAD))).
BONDPAD4a c 2 ((LM or TD) over BONDPAD) to {BB, NW, Mx (x=3,4,5,6,Q,G), 4.90

(PC outside BONDPAD)}. (((LM or TD) over BONDPAD) touching
{BB, NW, Mx (x=3,4,5,6,Q,G)} not allowed).
BONDPAD5a c ((LM or TD) over BONDPAD) to (RX outside of BONDPAD). 3.50

from this rule.
2. PC is intentionally omitted from the touching description of Rule BONDPAD4a. PC{Lattice] is permitted below ((LM or TD) over
BONDPAD) as described in Rules BONDPAD3a.
MA Metallization BONDPAD Layout Rules
The rules in the Table 112 are for terminals which include the BONDPAD shape for the MA BEOL metalliza-
tion options, for both for wirebond (DV) and C4 (LV) terminations, as defined in Table 12 on page 65 and are

BONDPAD shape).
Table 112. Pad Model Rules for C4 and Wirebond with MA Metallization

l .
a Min.
s
s
BONDPAD1 c BONDPAD overlap past MA. 0.10
BONDPAD3 c 1 (MA over BONDPAD) must be within (BP or BFMOAT or (the outer 4.90
edge of the (PC[Lattice] touching BONDPAD)) or (the outer edge of
the (RX[Lattice] touching BONDPAD))).
BONDPAD4 c 2 (MA over BONDPAD) to {BB, NW, Mx (x=3,4,Q,G), (PC outside 4.90
BONDPAD)}. ((MA over BONDPAD) touching {BB, NW, Mx
(x=3,4,Q,G)} not allowed).
BONDPAD5 c (MA over BONDPAD) to (RX outside of BONDPAD). 3.50

from this rule.
2. PC is intentionally omitted from the touching description of Rule BONDPAD4. PC{Lattice] is permitted below (MA over BONDPAD) as
described in Rules BONDPAD3.
AM Metallization BONDPAD Layout Rules
The rules in the Table 113 are for terminals which include the BONDPAD shape for the AM BEOL metalliza-
tion options, for both for wirebond (DV) and C4 (LV) terminations, as defined in Table 14 on page 67 and are
BONDPAD shape).
Table 113. Pad Model Rules for C4 and Wirebond with AM Metallization

l Min.
a
s
s
BONDPAD1d c BONDPAD overlap past AM. 0.10

Table 113. Pad Model Rules for C4 and Wirebond with AM Metallization

l Min.
a
s
s
BONDPAD3d c 1 (AM over BONDPAD) must be within (BP or BFMOAT or (the 4.90
outer edge of the (PC[Lattice] touching BONDPAD)) or (the outer
edge of the (RX[Lattice] touching BONDPAD))).
BONDPAD4d c 2 (AM over BONDPAD) to {BB, NW, Mx (x=3,4,5,Q), (PC outside 4.90
BONDPAD)}. ((AM over BONDPAD) touching {BB, NW, Mx
(x=3,4,5,Q)} not allowed).
BONDPAD5d c (AM over BONDPAD) to (RX outside of BONDPAD). 3.50
from this rule.
2. PC is intentionally omitted from the touching description of Rule BONDPAD4. PC[Lattice] is permitted below (AM over BONDPAD) as
described in Rules BONDPAD3d.
3.35.11 Wire-bond Part Testing and Packaging Restrictions

For IBM-tested wire-bond parts, note the following testing and packaging restrictions:
The largest possible pad size and opening should be used for manufacturing robustness.
Pad designs and the associated test approach must be approved by your IBM technical representative.
On chips with LM BEOL staggered wire-bonds pads, power and ground pads are prohibited on the inner
row.
On chips with LM BEOL staggered wire-bond pads, inner rows cannot be test probed. Inner pads are
designed to be bond only (52 x 52m). If testing is required on inner pads, the pad DV opening must be
altered to 52 x 95m.
Testing is done at 30 - 85 degrees C unless prior arrangements are made with the applicable test group.
Corner Rules:
- Inline pads:
(1) At the four corner areas, the first bond pad must be placed away from the mechanical and ther-
mal stress concentrated die edges. Unique patterns must be placed there for eye-point recogni-
tion. Starting from the corners, the first four pitches must be wider than the pitch in
regularly-repeating bond pad center area. See Figure 82, Corner Rules, In Line Wirebond Cor-
ner Pad for Single DUT (Device Under Test) on page 314 for design dimensions. All pads must
be located geometrically or symmetrically toward the direction of the internal leads. This may not
apply to chip sizes less than or equal to 4mm - Contact your IBM Packaging Representative.
(2) For Multi-DUT, an additional bondpad centerline spacing criteria must be satisfied at the four cor-
ners. Figure 84, In Line WIrebond Corner Pad Design Rules for Multi-DUT Probing (Device

Under Test) on page 316.
- Staggered pads (LM Last Metal only): See Figure 83, Staggered Wirebond Corner Pad Design
Rules (with LM last metal) on page 315 for design dimensions. All pads must be located geometri-
cally or symmetrically toward the direction of the internal leads.
For LM BEOL, each 52 x 95m DV pad opening is segregated as follows to optimize bondability and reli-
ability.
- The test probe region is the 52 x 85m pad region closest to the chip edge (probe design X/Y coordi-
nates are supplied as the center point of this region).
- The bond region is the 52 x 52m pad region toward the chip center. This region can overlap the
probe region.
Last Metal shown (values are minimums)

Dimensions apply in both vertical and
horizontal orientations
These dimension may not apply to chip sizes
less than or equal to 4mm.
Rule 941c (for LM BEOL)

Rule MA941b (for MA BEOL)
130 115 85 Rule 941cLD (for OL with
LD BEOL)
230
125
Rule 946ca (for LM BEOL)

125 95 Rule MA946b (for MA BEOL)
Rule 946caLD (for OL with LD BEOL)
(Note: Figure is not drawn to scale)
Figure 82. Corner Rules, In Line Wirebond Corner Pad for Single DUT (Device Under Test)


Dimensions apply in both vertical and
horizontal orientations
Rule S941c
CHIPEDGE
312 150 150 90 946ca
Typical
95
125 DV
946ca
125 Typical
230 140 140 125 90
Rule S941c
Figure 83. Staggered Wirebond Corner Pad Design Rules (with LM last metal)
3.35.12 Multiple DUT Pad Design Rules

The following device pad design restriction enables multiple device-under-test (DUT) probing productivity
enhancements:
For wire-bond pads probed in chip corners, the probe region vertical and horizontal center lines in the
corner pads must be spaced at least 200m apart.
Note: Multiple DUT probe testing with the fine-pitch wire-bond option requires prior approval from your IBM
technical representative. If testing is approved, the probe region coordinates must be provided.


All Dimensions In Single DUT figure apply except:
1. Centerline placement of the first wirebond
pad from chipedge must be increased in both
directions. (230um minimum dimension in
Single DUT figure must be increased
to 263.5um).
2. Wirebond pad centerline distance between
corner wirebond pads must be as shown herein.
3. Applies to LM, MA and LD (with OL) metallization
options.
200
(Note: Figure is not drawn to scale)

200
Figure 84. In Line WIrebond Corner Pad Design Rules for Multi-DUT Probing (Device Under Test)

All Dimensions In Single DUT figure apply except:
1. Centerline placement of the first wirebond
pad from chipedge must be increased in both
directions. (230um minimum dimension in
Single DUT figure must be increased
to 263.5um).
2. Wirebond pad centerline distance between
corner wirebond pads must be as shown herein.
200
Center-line of
Inner Pads 200 (Note: Figure is not drawn to scale)
Figure 85. Staggered WIrebond Corner Pad Design Rules for Multi-DUT Probing (Device Under Test, with LM last
metal)

Layout Rules Slots in Wide Metal
3.36 Slots in Wide Metal

The guidelines in this section are only applicable to Wirebond chips that are greater than 10mm x 10mm in
size and are packaged in a plastic package.
Chips packaged in plastic flat packs are subject to chip/plastic thermal mismatch stress which can result in
dielectric cracking and metal movement around the chip periphery. Susceptibility is a function of many factors
including the module build process, chip size, chip film thicknesses and composition, topology, and metal lay-
out. It is strongly recommended that chips to be packaged in plastic flat packs follow the slot and corner
chamfer guidelines below.
1. The portion of the chip where slots in the metal will provide stress relief can be approximated by placing a
dummy box that is 10mm x 10mm in the center of the chip. Wide metal lines outside of the box should
have slots placed in them.
2. The data suggests that the order of importance for placing slots in metal is from top to bottom.
That is, for the MA metallization options listed in Table 12 on page 65, it is most important to place
slots in MA, E1, LY and least important to place them in M1.
That is, for the OL with LD metallization options listed in Table 13 on page 66, it is most important to
place slots in LD, OL and least important to place them in M1.
3. A wide metal line is defined as being 40 m wide. Only wirebond pad areas are excepted.
4. Slots in MA or LD are recommended to be approximately 5 m wide and 30 m long.
5. Slots should be placed such that the maximum last metal width (outside of the 10x10 box) should be
< 40 m wide.
6. If the lines are very wide, space the slots 10 to 40 m apart along their sides. End to end spacing
between slots should be 5 m. It is desirable to stagger the starting position of the slots for long, wide
metal.
7. To avoid EM problems resulting from current funneling due to slots, the length of the slots should be par-
allel to the current flow. Care should be taken to avoid geometries that will funnel currents and lead to EM
problems.
8. Areas of the chip that should have slots in the metal should also have chamfered corners on right angled
bends of wide MA, E1, LY, or LD, OL lines. The length of the inside edge of the chamfered corner should be
15 m long.
9. The use of MA, E1, LY, LD or OL in the corners of the chip should be avoided other than for wirebond
pads and the chip guard ring. The corners of the chip are defined as the four triangular regions in the cor-
ners whose sides along the edge of the chip are 400 m long.

Layout Rules Chip Guard Ring and Chamfer IBM
400um
400um
CORNER AREA
>3um
CHIPEDGE
10mm x 10mm >40um

>15um
3um
30um
LAST METAL SLOT AREA
Figure 86. Guidelines for Slots in Last Metal
3.37 Chip Guard Ring and Chamfer

The chip guard ring provides both a low resistance path to ground for surge currents and a metal seal against
ionic contaminants.
The guidelines below must be followed when designing a chip guard ring:
The chip guard ring must be a complete, unbroken ring around the entire active chip area. This applies to
all shapes used to define the guard ring. The chip guard ring must be connected to the ground bus.
The chip guard ring must be comprised of the following levels: RX, BP, CABAR, M1, V1BAR, M2, VLBAR,
MQ. Continuous xxBAR vias and contacts must be used in the guard ring structure.
- For the LM metallization options see Table 11, LM last metal Back End Of Line (BEOL) Metallization
Options, on page 64. If the levels V2BAR, M3, V3BAR, M4, V4BAR, M5, V5BAR, M6, VQBAR, MG,
VGBAR, and LM are present in the data, then they must also be included in the guard ring. (Note:
The TV via and TD design level are not used in the chip guard ring structure).
- For the MA metallization options defined in Table 12, MA last metal Back End Of Line (BEOL) Metal-
lization Options, on page 65, the following also apply: FYBAR, LY, FTBAR, E1, F1BAR, MA. The fol-
lowing levels must be present if they are present in the design data: V2BAR, M3, V3BAR, M4,
VQBAR, MG.
- For the OL with LD metallization options defined in Table 13, OL with LD last metal Back End Of Line
(BEOL) Metallization Options, on page 66, the following also apply: JTBAR, OL. The following levels
must be present if they are present in the design data: V2BAR, M3, V3BAR, M4, V5BAR, M5,
VQBAR, MG. (Note: The VV or VVBAR via design levels and LD last metal design levels are not used
in the chip guard ring structure)
- For the AM metallization options defined in Table 14, AM last metal Back End Of Line (BEOL) Metal-
lization Options, on page 67, the following also apply: V2BAR, M3, V3BAR, M4, V4BAR, M5,

Layout Rules Chip Guard Ring and Chamfer
FQBAR, & AM.

The chip guard ring must not have any vertices except for the 45 angles that occur at the corner bevels.
The measured width of the 45 CABAR, V1BAR, V2BAR, V3BAR, V4BAR, V5BAR, VLBAR, VQBAR,
VGBAR, FYBAR, FTBAR, F1BAR, FQBAR, or JTBAR shapes on the corner bevels may not exactly
match the specified dimensions due to grid snapping ( 0.014 tolerance, or plus or minus the grid times
the square root of 2 tolerance). This tolerance also applies to the chip guard ring within rules.
The length restriction on CABAR, V1BAR, V2BAR, V3BAR, V4BAR, V5BAR, VLBAR, VQBAR, VGBAR,
FYBAR, FTBAR, F1BAR, FQBAR, or JTBAR, does not apply to the chip guard ring.
The chamfer region is required for all chips. An exact 125 m chamfer or corner bevel must be cut from
each corner of the chip. For process robustness, all designs must follow the chamfer rules. The chamfer
area is triangular, and has an area of exactly half of a 125 m2 square. The chip guard ring does not
enclose the chamfer area. The chip guard ring has 45 edges at the corners of the active chip area.
Data preparation and design services are not performed on the 125 m chamfer and fill shapes are not
placed in this region. The crackstop is to be automatically placed here during KERF merge. A shape
exactly matches triangular chamfer area must be added to all four corners on the PROTECT level (see
section 3.38 , Protect Layer on page 325. ).
In addition, the following guideline is recommended:
The chip guard ring should be comprised of four cells (top, bottom, left and right) placed on the primary
cell. This eases hierarchical data manipulation for design rule checking and design preparation.
The chip guard ring is available in the Design Kit.
Table 114. Chip Guard Ring Rules1

l Min.
a
s
s
990a c RX width. 1.50
990b c BP width. 1.82
990d a CABAR width. 0.16
990d1 a CABAR minimum space. 0.52
990d2 a CABAR to CA minimum space with touching prohibited. 0.28
990e a VxBAR exact width, where x = 1,2,3,4,5 (see also Rule IND560 in 0.20
Table 96 on page 269 or for VxBAR dimensions and Rule 558 in
Table 33 on page 133 for VxBAR use allowances).


l Min.
a
s
s
990e1 a A minimum of one continuous VxBAR in the chip guard ring layout is 0.80
required between each pair of consecutive metal levels, where x =
1,2,3,4,5. If multiple parallel via bars exist in the chip guard ring, then:
VxBAR to VxBAR space, where x=1,2,3,4,5.
(Note: There is a separate spacing Rule IND564 in Table 96 on
page 269 for Inductors and see also Rule 553d in Table 33 on page 133
for Vx to VxBAR space)
990e2 a GUARDRNG touching {IND, IND_FILT, LM_RFLINE, MA_RFLINE} is = -

prohibited.
990f a M1 width, M2 width, M3 width, M4 width, M5 width, M6 width. 1.50
990g a VxBAR exact width, where x = G, L, Q (see also Rule IND625 in 0.40
Table 96 on page 269 for VxBAR dimensions or Rules 558a, 558b,
558c in Table 33 on page 133 for VxBAR use allowances).
990g1 a A minimum of one continuous VyBAR in the chip guard ring layout 1.20
between each pair of consecutive metal levels is required, where y = L,
Q, G. If multiple parallel via bars exist in the chip guard ring, then:
VLBAR to VLBAR space
VQBAR to VQBAR space
VGBAR to VGBAR space
(Note: There are separate spacing Rules for Inductor or LM RF Inter-

connect Line. See Rule IND628 in Table 96 on page 269 for Inductors
or Rule TL676 in Table 98 on page 275 for LM RF Interconnect Line.
See also Rule 553e in Table 33 on page 133 for Vx to VxBAR space).
990h c (LM, MG, MQ) width. 1.50
990k a 2,3,4,5,6 Mx inside GUARDRNG, Mx=M1,M2,M3,M4,M5,M6,MQ,MG or LM or LY 0.00

or E1 or MA or OL or AM, that are part of the guardring.
990E1a a E1 width. 4.44
990FY1 a FYBAR exact width. 1.00
990FY2a a FY to FYBAR (FY touching FYBAR is prohibited). 2.00
990FY2b a A minimum of one continuous FYBAR in the chip guard ring layout 2.00
between (MQ or MG) and LY is required. If multiple parallel via bars
exist in the chip guard ring, then:
FYBAR to FYBAR space.
(see also Rule FY14 in Table 48 on page 166 for FYBAR use allow-
ance).


l Min.
a
s
s
990JTb a A minimum of one continuous JTBAR in the chip guard ring layout = -
between (MQ or MG) and OL is required.
(see also Rule JA1d1 in Table 42 on page 156 for JTBAR use allow-
ance).
990JTc a If multiple parallel JTBAR exist in the chip guard ring, then: JTBAR 10.0
space. 0
(Note: Design Min value supersedes Rule JA3 in Table 42 on page 156
for JTBAR over GUARDRNG. See also Rule JA2 for JA to JTBAR
space).
990LY1 a LY width. 3.52
990MA1 a MA width. 4.44
990OL3 a OL width. 4.44
990FQ1 a FQBAR exact width. 0.60
990FQ2a a FQ to FQBAR (FQ touching FQBAR is prohibited). 1.80
990FQ2b a A minimum of one continuous FQBAR in the chip guard ring layout 2.00
between MQ and AM is required. If multiple parallel via bars exist in the
chip guard ring, then: FQBAR to FQBAR space.
(see also Rule FQ14 in Table 57 on page 174 for FQBAR use allow-
ance).
990FQ3 a 7 FQBAR within AM. 0.68
991 c RX must be within BP. 0.16
992c c CABAR must be within RX. 0.67
993 c CABAR must be within M1. 0.67
994a c V1BAR must be within M1. 0.65
994b c V2BAR must be within M2. 0.65
994c c V3BAR must be within M3. 0.65
994d c V4BAR must be within M4. 0.65
994e c V5BAR must be within M5. 0.65
994FYa c FYBAR within MQ (for 6, 7 or 8LM). 1.20
994FYa1 c FYBAR within MG (for 7 or 8LM). 1.20


l Min.
a
s
s
994FYb c FYBAR must be within LY (for 6, 7 or 8LM with MA Metallization 1.20

options).
994FTa c FTBAR within LY (for 6, 7 or 8LM with MA Metallization options). 1.20
994FTb c FTBAR within E1 (for 6, 7 or 8LM with MA Metallization options). 1.30
994F1a c F1BAR within E1 (for 6, 7 or 8LM with MA Metallization options). 1.60
994F1b c F1BAR within MA (for 6, 7 or 8LM with MA Metallization options). 1.60
994FQa c FQBAR within MQ (for 7LM with AM Metallization options). 1.00
994h c VLBAR must be within {M3, M4, M5, M6}. 0.55
994h1 c 8 VLBAR must be within M2 (for 6 or 7 level of metal with MA = last metal, 0.55
see Table 12 on page 65) or for (5 level of metal for OL with LD = last
metal, see Table 13 on page 66).
994JT c JTBAR must be within MQ (when MG is not present). 1.60

JTBAR must be within MG (when MG is present).
994VG c VGBAR must be within MG. 0.55
994VQ c VQBAR must be within MQ. 0.55
996c c V3BAR must be within M4. 0.65
996e c V4BAR must be within M5. 0.65
996g c V5BAR must be within M6. 0.65
996JT c JTBAR must be within OL. 1.60
997a c VLBAR must be within MQ. 0.55
997VQ c VQBAR within (LM or MG). 0.55
997VG c VGBAR within LM . 0.55
999 a RX, M1, M2, M3, M4, M5, M6, MQ, MG, LM must be within CHIPEDGE. 0.00


l Min.
a
s
s
999a a {JD, NW, LW, PV, (PI sized by 1.1), XW, NV, JN, JP, BB, DG, PC, 0.00
PCING, PCFUSE, XE, XF, PD, RR, RP, OP, K2, K3, K4, K5, K6, QT, HT,
KT, OL, LD, LY, QY, HY, E1, L1, MA, FQ, AM, TD, TV, FV, DV, LV,
BFMOAT, BONDPAD, C4LV, DS_MATCH, EFUSE, (ESDIODE sized by
0.1), GUARDRNG, IND, IND_FILT, LM_RFLINE, LMTRANS,
LOGOBND, LVDUMMY, MA_RFLINE, MQDUMHOL, MGDUMHOL,
MIM_HK, MIM_NI, NW_RES, SRAMRX, SRAMPC, SRAMM1, VAR,
(ZEROVT sized by 0.52)} must be within CHIPEDGE.
(Note: BP is allowed to straddle CHIPEDGE, see Rule 999b).
The dummy design level CHIPEDGE must encompasses the levels

listed above (except BP) and must be beveled at each of the 4 corners
to follow the chip guard ring design, See section 3.37 , Chip Guard
Ring and Chamfer on page 318, requirement 7. CHIPEDGE is
bounded at X=0 on the left and Y=0 on the bottom.
For other rules related to CHIPEDGE, see Rule 658, the Terminal Con-
tact rules.
999a1 a Rule Deleted. = -
999b a BP within CHIPEDGE. -0.16
999d a 9 {LD, VV} touching GUARDRNG is prohibited. = -
999d1 a {CA, PC} touching (GUARDRNG touching OL) is prohibited. = -
1000LM c For designs that include LM, the guard ring must be connected, using -
LM metal, to a wirebond or C4 pad.
1000MA c For designs that include MA, the guard ring must be connected, using -
MA metal, to a wirebond or C4 pad.
1000OL c 10,11 For designs that include OL, the chip guard ring must be connected, -
using OL metal, to a LD metallization wirebond pad or C4 pad.
1000AM c For designs that include AM, the guard ring must be connected, using -
AM metal, to a wirebond or C4 pad.
1100 a (CHIPEDGE touching LM) touching (AM or LD or MA) is prohibited.

(CHIPEDGE touching AM) touching (LM or LD or MA) is prohibited.
(CHIPEDGE touching MA) touching (AM or LD or LM) is prohibited.
(CHIPEDGE touching LD) touching (AM or LM or MA) is prohibited.

1. All Rules in this table, with the exception of Rules 990b, 991, 999a, 999a1, 999b for the BP design level, since BP exists outside
the CHIPEDGE by the Rule 999b value, or Rules 999, 999LY, 999E1, 999MA, 999OL and 1000LM, 1000MA, 1000OL, 1000AM
since using this a dummy design level designator on these rules may lead to false errors, for checking purposes may be
interpreted as also being over the dummy design level GUARDRNG. For additional information on GUARDRNG, see Table 6,
Dummy Design Levels and Utility Levels on page 46 and Rule 990k in this Table. Rules 990b and 991 can be checked in DRC
using terminology over (GUARDRNG expanded by 0.16m).
2. GUARDRNG must be drawn so as to completely cover the metal of the chip guard ring, but not cover any metal shapes unrelated to the
chip guard ring. This rule does not apply to LM or MA or OL to satisfy other rules defined in this table.
3. LM is allowed to straddle GUARDRNG to satisfy Rule 1000LM.
4. MA is allowed to straddle GUARDRNG to satisfy Rule 1000MA.
5. OL is allowed to straddle GUARDRNG to satisfy Rule 1000OL.
6. AM is allowed to straddle GUARDRNG to satisfy Rule 1000AM.
7. Non-orthogonal widths can be checked to +/- 0.014um from the groundrule value.
8. Rule does not apply to the LM BEOL metallization options defined in Table 11 on page 64.
9. Rule does not include VVBAR since VVBAR touching GUARDRNG is satisfied per Rule LD93 in Table 47 on page 164 and Rule 990e2.
10. If net checking is not feasible for this rule, one suggested boolean methodology for identifying wirebond pads connected to the chip
guard ring is: (OL touching (OL over GUARDRNG)) touching (VV touching (LD touching (DV over LD)))]. Alternative verification
methods, that satisfy this rule, are allowed.
11. If net checking is not feasible for this rule, one suggested boolean methodology for identifying C4 pad connected to the chip guard ring
is [(OL touching (OL over GUARDRNG)) touching (VV touching (LD touching (LV over LD)))]. Alternative verification methods, that
satisfy this rule, are allowed.

Layout Rules Protect Layer
MA Metallization Option AM Metallization Option

OL with LD Metallization Option
(LD not part of the Chip Guard Ring)
CHIPEDGE CHIPEDGE
AM
MA
FQBAR
CHIPEDGE
F1BAR
MQ
E1 VLBAR
OL
M5
FTBAR
JTBAR V4BAR
MQ LY M4
VLBAR V3BAR
FYBAR
M3 MQ M3
V2BAR V2BAR
VLBAR
M2 M2 M2
V1BAR V1BAR V1BAR
M1 M1 M1
CABAR CABAR CABAR
RX RX RX
Figure 87. Chip Guard Ring Cross-Section (6 Level metal with MA or OL with LD last metal or 7 Level metal with AM last
metal). Not drawn to scale.
3.38 Protect Layer

To allow job decking the chip separately from the kerf when building glass, the following temporary require-
ment is in place (check with your IBM technical representative to confirm that this requirement is still valid).

Layout Rules Protect Layer IBM
Requirement: 4 right triangle shapes drawn on level PROTECT with the hypotenuse of the triangles coinci-
dent with the chamfered edges on CHIPEDGE. The function of the PROTECT level is to keep kerf data
located in the 4 triangle areas from getting overwritten if the kerf and chip data are job decked at the mask
house.
Table 115. Protect Layer Rules

l Min.
a
s
s
PT01a a PROTECT must be an orthogonal 45 triangle. -
PT01b a There should be four PROTECT shapes for every CHIPEDGE shape. -
PT01c a Union (CHIPEDGE, PROTECT) must be a single orthogonal rectangle. -
PT01d a Each PROTECT must have a 45 edge in common with CHIPEDGE. -
PT01e a Orthogonal PROTECT edge exact length (m). = 125
PT01f a PROTECT should not be checked against Rule S2 for acute angles. - -
PT01g a PROTECT should neither intersect nor be covered by CHIPEDGE. - -

Layout Rules Protect Layer
Table 115. Protect Layer Rules

l Min.
a
s
s
PT01h a 1,2,3,4,5 All Design levels, affecting mask build, except BP, are prohibited over - -
PROTECT. This rule shall be, at a minimum, checked as.
The following Design Levels are prohibited over PROTECT: RX, JD, NW,
BB, NS, RN, LW, PV, PI, XW, NV, JN, JP, DG, PC, XE,XF,PD,RR,OP, Mx,
M6, LM, LY, E1, L1, MA, AM, TD,FV, OL, LD, QT where x=1,2,3,4,5,Q,G.
The following Design Levels are prohibited over PROTECT: CA,

CABAR, Vx, VxBAR, VL, VLBAR, FY, FYBAR, QY, HY, FT, FTBAR, F1,
F1BAR, FQ, FQBAR, TV, DV, LV, JT, JTBAR, VV, VVBAR where x =
1,2,3,4,5,Q,G.
The following Design Levels are prohibited over PROTECT: PCING, RP,
Kx (where x=2,3,4,5,6).
The following Dummy Design & Utility Levels are prohibited over PRO-
TECT: BFMOAT, BONDPAD, xxEXCLUD where xx = {LY, E1, MA, AM,
OL, LD}, ESDIODE, EFUSE, GUARDRNG, IND, IND_FILT, LOGOBND,
LM_RFLINE, LMTRANS, MA_RFLINE, MGDUMHOL, MQDUMHOL,
MxTRANS (where x = 1,2,3,4,5,6,Q,G), NW_RES, OUTLINE, PCEX-
CLUD, RXEXCLUD, VAR, VNCAP, ZEROVT.
The following Restricted Design Levels are prohibited, over PROTECT:

NR, PR.
The following Restricted Design Levels are prohibited over PROTECT,

except if generated by IBM: ({MxCHEXCL, MxFILL} where
x=1,2,3,4,5,6,Q,G), LDFILL, LMCHEXCL, LMFILL, LYFILL, E1FILL,
MAFILL, AMFILL, OLFILL, PCFILL, RXFILL, KERFEXCL, QE.
The following Masks for Non-Design Levels are prohibited over PRO-
TECT, except if generated by IBM: BT, DW, BF, BH, DE, DF, PH, VI, BN,
QE.
The following Restricted6 Design Levels are prohibited over PROTECT,

except if generated by IBM: AMEXCLUD, LMEXCLUD or MxEXCLUD
where x=1,2,3,4,5,6,Q,G.
PT999a a CHIPEDGE must be chamfered. The orthogonal x and y dimensions of - -
the chamfer must be exactly 125m.
1. If all design levels, except BP are checked, the specific list of levels in the balance of the rule statement are for reference only to insure
completeness. The specific list of Design or Dummy design levels are the minimum list of levels that need to be checked to this rule
since these levels affect mask build.
2. For Rule PT01h, pin levels are to be checked, if required for DRC completeness.

Layout Rules Crackstop IBM
3. To simplify DRC checking, if necessary, the following levels mentioned in Rule PT01h can be omitted from checking, if the intent of Rule
PT01h is met by checking a subset of these levels, in combination with other Rules that will check that the intent of Rule PT01h was
achieved. For example, CA may be omitted from checking to this rule as long as ALL of the following levels within PROTECT are
validated to be checked to this rule: PC, RX, M1 since related Rules 212, 505a or 506ab should prevent CA from being present within
PROTECT too. CABAR may be omitted from checking to this rule as long as ALL of the following levels within PROTECT are validated
to be checked to this rule: RX, M1, IND, GUARDRNG since related Rules 228, 990d, 992, 993 should prevent CABAR from being
present within PROTECT too. Vx (x = 1,2,3,4,5,6,L,Q,G) may be omitted from checking to this rule as long as ALL of the following
levels within PROTECT are validated to be checked to this rule: M1, M2, M3, M4, M5, M6, MQ, MG, LM, since related Rules 570,
571b, 575, 611, 623a, 624a, 693, 695, 695b should prevent these vias from being present within PROTECT too. VxBAR (x =
1,2,3,4,5,6,L,Q,G) may be omitted from checking to this rule as long as ALL of the following levels within PROTECT are validated to
be checked to this rule: M1, M2, M3, M4, M5, M6, MQ, MG, LM since related Rules 994a, 994 b,994 c, 994d, 994e, 994h,
994h1,994VQ, 994VG, 995a, 996a, 996c, 996e, 996g, 997a, 997VQ, 997VG should prevent these bar vias from being present within
PROTECT too. QY or HY may be omitted from checking to this rule as long as ALL of the following levels within PROTECT are
validated to be checked to this rule: LY since related Rules HLM0, QCAP3, QCAP3a should prevent these MIM levels from being
present within PROTECT too. FY or FYBAR may be omitted from checking to this rule as long as ALL of the following levels within
PROTECT are validated to be checked to this rule: MQ, MG, LY since related Rules FY4, FY5, 994FYb should prevent these via levels
from being present within PROTECT too. FT or FTBAR or F1 or F1BAR may be omitted from checking to this rule as long as ALL of
the following levels within PROTECT are validated to be checked to this rule: LY, E1, MA, L1 since related Rules FT9, FT10, E1c,
E1d, E1e, E1f, FY5, MA4, MA4a should prevent these via or final passivation opening design levels from being present within
PROTECT too. DV or LV or TV may be omitted from checking to this rule as long as ALL of the following levels within PROTECT are
validated to be checked to this rule: MA, LM, TD since related Rules MA5, 902p1, WB08 should prevent these via or final passivation
opening design levels from being present within PROTECT too. JT or JTBAR may be omitted from checking to this rule as long as
ALL of the following levels within PROTECT are validated to be checked by this rule: MQ, MG, OL, QT since related Rules JA4, JA5
and JA6 should prevent these via or final passivation opening design levels from being present within PROTECT too. VV or VVBAR
may be omitted from checking to this rule as long as ALL of the following levels within PROTECT are validated to be checked by this
rule: OL, LD since related Rules LD70, LD75, LD93, IND894, IND895 should prevent these via or final passivation opening design
levels from being present within PROTECT too.
4. The Restricted design levels may be omitted from checking to this rule, if they are either 1) not included in the design kit or 2) checked
by other rules in DRC used to identify them as Restricted. This Rule check for the PROTECT shape differs from the Rules checking
these levels for the CHIPEDGE (see related Rules RL01, RL03, RL04, RL05, RL06, RL07 in Table 18, Reserved Level Layout Rules,
on page 83).
5. These Masks for Non-Design Levels may be omitted from checking to this rule, if they are checked by other rules in DRC used to identify
them as Restricted for design or use or not allowed to be drawn within PROTECT. See Table 7, Masks for Non-Design Levels, on
page 58.
6. The Restricted design levels may be omitted from checking to this rule if they are not included in the design kit.
3.39 Crackstop
Special crackstop design is placed around the entire chip. This is done by Design Services and is transparent
for designers. For details and purpose of the crackstop, contact your IBM technical responsible.
3.40 Product Labels

Product labels are placed in the chip, not in the kerf, and consist of:
Chip Legal Protection Notices
- copyright symbol and year
- company logo
- maskwork notice
Chip Identification

Layout Rules Product Labels
- part number
- release version or EC number

Mask Level Identification
- mask level names /versions
3.40.1 General Requirements

1. Product labels must be placed in one or more corners of the chip (placement in the lower left corner of
chip is preferred).
a. For products requiring packaging, at least one product label must be included. This label is used to
orient the chip during packaging.
b. When using two corners for the product labels, it is recommended to use corners on the same side of
the chip rather than diagonally across. This reduces the risk of the chip being oriented incorrectly dur-
ing packaging operations.
2. The entire group of product labels must be surrounded by a substrate contact ring (See Section 3.37 ,
Chip Guard Ring and Chamfer on page 318). No functional chip structures are to be placed within this
region.
3. The entire product label area must be covered by the LOGOBND dummy level. LOGOBND is used to
suppress spurious DRC errors. Only labels and non circuit shapes are permitted under LOGOBND.
4. The proper xxEXCLUD levels are also required to protect the area from pattern filling routines (xx level
identifier). The design must still pass all local and global pattern density rules. NOTE: IBM places
auto-generated RXFILL in LOGOBND regions.
5. Shapes within the LOGOBND area must abide by all line, space and area rules for the level on which they
are designed.
6. No extraneous symbols are allowed as they can cause mask processing difficulties.
7. Alphanumeric Polygon Definitions:
a. A character set is available in a design kit provided by your IBM technical representative.
b. If the IBM provided character set is not used, characters must be composed of polygons that follow
the design rules for line widths, spacing, orthogonal and 45 shapes, enclosed shapes, shape areas,
and so forth, and that meet the expanded spacing rules in Table 116, Special LOGOBND Rules on
page 330.
8. See Figure 89, Example Placement of Product Labels on page 332 for an example of the placement of
product labels and surrounding substrate contact ring.
9. Characters and symbols are prohibited on TV, FV or DV levels (see Rule PN907) and the LV level (see
Rule MA907, LD907).
10. Characters are required only on PC and M1 levels. If a designer chooses to place characters on other lev-
els, satisfying the design rules may be difficult.

Layout Rules Product Labels IBM
11. See Table 116 for additional LOGOBND Rules
Table 116. Special LOGOBND Rules

l Min.
a
s
s
PN100 b 1 {RX, JD, NW, LW, PV, JN, JP, (PI sized by 1.1), XW, NV, BB, DG, PC, PCING,
PCFUSE, XE, XF, PD, RR, RP, NS, RN, OP, CA, M1, M2, M3, M4, M5, M6, K2, K3,
K4, K5, K6, MQ, MG, LM, QT, HT, KT, OL, LD, LY, QY, HY, E1, L1, MA, AM, TD,
BFMOAT, BONDPAD, C4LV, DS_MATCH, EFUSE, (ESDIODE sized by 0.1),
GUARDRNG, IND, IND_FILT, LM_RFLINE, LMTRANS, MA_RFLINE, MQDUM-
HOL, MGDUMHOL, MIM_HK, MIM_NI, NW_RES, SRAMRX, SRAMPC,
SRAMM1, VAR, (ZEROVT sized by 0.52), E1FILL, JTHOLE, LDFILL, LMFILL,
LMHOLE, LYFILL, MAFILL, AMFILL, MxFILL, MxHOLE, , OLHOLE, PCFILL,
RXFILL, VyHOLE, where x = 1,2,3,4,5,6,Q,G, y = 1,2,3,4,5,L,Q,G), QE} straddling
LOGOBND is prohibited.
PN101 b The leading edge of LOGOBND must be within CHIPEDGE (maxi- < 50.0
mum).
PN101a b LOGOBND must not touch (CHIPEDGE sized by -150m) = -

(LOGOBND straddling (CHIPEDGE sized by -150m) is prohibited).
PN101b b LOGOBND width (orthogonal edges parallel to x or y axis, maxi- 150.0

mum).
PN101c b LOGOBND area (m2, each shape, maximum). 14050.0
PN101d b LOGOBND area (m2, maximum per chip). 28100.0
PN203 a 2 CA to CA space over LOGOBND. 0.28
PN502 a M1 to M1 space and notch over LOGOBND. 0.28
PN553 a 3 Vx to Vx space (x=1,2,3,4,5) over LOGOBND. 0.28
PN602 a Mx to Mx space (x=2,3,4,5,6) over LOGOBND. 0.28
PN620R d 4 VL to VL space. 0.40
PN637R d 4 LM to LM space. 0.40
PN675R d 4 VQ to VQ space, VG to VG space. 0.40
PN692R d 4 MQ to MQ space, MG to MG space. 0.40
PN907 c 5 TV, TVDUMMY, FV, DV not allowed over LOGOBND.
PN907a a {VV, VVBAR, FQ, FQBAR} over LOGOBND is prohibited.

Layout Rules Product Labels
1. For levels verified in DRC, see Section 2.2 , Mask Level Definitions on page 27; Table 2 and Table 3 (for only the levels supported
in the design kit techfile in Table 3), Section 2.3 , Dummy Design Levels and Utility Levels on page 45; Table 6, and Section
2.4 , Masks for Non-Design Levels on page 58 ; Table 7 and Section P.4, Far BEOL Manipulation on page 548 (already
verified per Table 2).
2. PN203 includes CA and CABAR.
3. PN553 includes Vx and VxBAR (x=1,2,3,4,5).
4. Rules may change to required in a future version of this document. Presently, these are checked using the equivalent rule without the
PN prefix.
5. See also Rule 907 in Table 100, C4 Layout Rules (Active and Dummy with LM last metal level), on page 278 for TV and TVDUMMY
and Rule MA907 in Table 101, C4 Layout Rules (Active and Dummy with MA last metal level), on page 284 for LV and LVDUMMY
or Rule LD907 in Table 102, C4 Layout Rules (Active and Dummy for LD last metal level), on page 288 for LV and LVDUMMY.
3.40.2 Chip Protection Notices

The copyright notice, the company logos, and the maskwork notice (*M*), are legal notices that provide legal
protection of proprietary design layouts and certain chip features. It is recommended that all product designs
contain both the company logos and the maskwork notice. Product designs that contain significant designs or
have a substantial risk of being copied may also be protected with the copyright notice.
These chip protection notices must be placed on first metal (M1) only.
An example of a combined maskwork and copyright notice is shown below. Note that the font shown has
enclosed shapes which might be subminimum. A design character generator will produce shapes without
enclosed areas.
1996 IBM *M*

Figure 88. Combined Maskwork and Copyright Notice
3.40.3 Chip Identification (Part Number and Release Version or EC

Number)
1. Part Numbers
a. The IBM-assigned chip part number is required on the PC and M1 levels of each chip. The IBM part
number is required whether the design is a test site, prototype, or production part. If a RIT A/B
approach is being used, where the front-end-of-line (silicon) and back-end-of-line (wiring levels)
designs have different part numbers, the RIT A part number appears on PC and the RIT B part num-
ber appears on M1. IBM part numbers may be obtained from your IBM product engineer prior to
design submission.
Exceptions
(1) Products for which the deliverable is untested wafers
(2) If the customer supplies a merged dataset that contains several chips or tiles, as in a multi-project
wafer (MPW) or an array of chip variants for design optimization, the IBM-assigned part number
must only appear once in the dataset. Place the part number in one of the corners of the dataset
as described in section 3.40.1 , General Requirements on page 329. In addition, the following
two statements apply:
If IBM is required to dice the sandbox into chip dies or test the chips, the Customer should
place a unique identifier for each instance of the chip. The customer should also provide a
drawing / GIF of the location and label of each chip with data submission.

Layout Rules No Polyimide Final Passivation option IBM
If IBM does not dice the sandbox, some level of identification is required, minimally a Cus-
tomer name.
b. If the product part number is later changed for any reason, a waiver is not required. The IBM product
engineer must submit an EC and maintain a change log for traceability purposes.
c. Customer part numbers and identifiers can be placed in addition to the IBM assigned part number.
2. Release Version or EC Number
- A single letter release version label (A, B, etc.) may appear on each level (subject to the constraints
listed in section 3.40.1 , General Requirements on page 329.) Alternatively the actual EC number
may be used.
3.40.4 Mask Level Identification

Mask level identification is not allowed on any Front-End-Of-Line design levels except PC or RX due to shape
propagation to derived levels.
CHIPEDGE
C 1996 IBM *M* Legal protection notices
01234567 RIT A part no. (place on PC)

89012345 RIT B part no. (place on M1)
Release version ID
(for RX level) M2A Mask level ID and release
A version ID (for M2 level)
PCA V2A
M3A
CAA Substrate guard ring
V3A
M1A surrounding all labels
M4A
Chip origin V1A V4A CHIPEDGE and guard ring
AMA
Figure 89. Example Placement of Product Labels
The surrounding line is the substrate contact ring at the lower left side of the chip.
3.41 No Polyimide Final Passivation option

IBMs technology level qualifications have included polyimide final passivation, but IBM sees no intrinsic
impact to the wafer reliability failure rate for foundry customers who require wafers without polyimide. The
customer is responsible however to evaluate product and packaging reliability failure rates for wafers without
polyimide. If the no polyimide option is selected in the Features Table (see Table 1, Optional Features with

Layout Rules Permissible Chip (CHIPEDGE) Sizes
Feature Part numbers, on page 11) the following ID shape must be added to the layout covering the
CHIPEDGE shape. Also see section 2.9 , Important Design Guidelines on page 84 for additional informa-
tion.
Table 117. No Polyimide Rules

l Min.
a
s
s
1
NOPLYMD01 b NOPLYMD level requires feature selection review with IBM Product Engineer-
ing. Contact your IBM technical representative for more details.
NOPLYMD02 b 2,3 If NOPLYMD exists, NOPLYMD must be drawn exactly coincident -
with CHIPEDGE.
NOPLYMD03 a NOPLYMD touching (CHIPEDGE touching LM) is prohibited. -

1. NOPLYMD (no polyimide) level found warning message is to be reported during a DRC run if the NOPLYMD level is found in the
design data. No polyimide feature selection is prohibited for IBM tested and packaged products.
2. For NOPLYMD or CHIPEDGE containing 45 degree angle bevels, the measured coincidence of these levels many not exactly match
due to grid snapping. A +/- square root of 2 x grid tolerance can apply during coincident checking.
3. For multi project wafer (MPW) designs submissions that may require both polyimide and no polyimide processing, contact your IBM
technical representative.
3.42 Permissible Chip (CHIPEDGE) Sizes

Chip (CHIPEDGE) size is subject to the following limitations:
1. Maximum chip size in the x-direction: 19.5 mm for thin production kerfs.
2. Maximum chip size in the y-direction is 21.0 mm.
3. The X and Y dimensions of CHIPEDGE must be an even multiple of 0.01 m and must be on grid.
See Table 118, CHIPEDGE Design Rules on page 334
4. Large chip sizes, exceeding 14.6 mm on a side, may result in nonlinear cost increases compared to
smaller chips.
5. Large chip sizes, exceeding 20.0mm, must be reviewed by the kerf design group.
The maximum die size might be restricted depending on the selected package technology. Contact your IBM
technical representative to obtain the correct die size for the specific package.

Layout Rules Permissible Chip (CHIPEDGE) Sizes IBM
Table 118. CHIPEDGE Design Rules

l Min.
a
s
s
CE001 a CHIPEDGE x and y dimensions must be an even number of grid points (2 -

x 0.01).

Electrical Parameters and Models Available Devices and Models
4.0 Electrical Parameters and Models

All the dimensions in this section are wafer dimensions, unless specified otherwise.
The electrical parameters are given for T=25 oC, unless specified otherwise.
4.1 Available Devices and Models

The following tables list the available FETs and passive devices in the CMOS8RF (CMRF8SF) technology.
Table 119. Available FETs
Device Name (FET) Model Name Max1 Min Min Tox Design and
Vdd [V] LDes WDes [nm] Dummy Design
[m] [m] Levels2
Regular NFET nfet 1.6 0.12 0.16 2.2 -
Regular PFET pfet 1.6 0.12 0.16 2.2 NW,BP
Low Vt NFET lvtnfet 1.6 0.12 0.16 2.2 XW
Low Vt PFET lvtpfet 1.6 0.12 0.16 2.2 NW, LW, BP
LP NFET (low power) lpnfet 1.6 0.12 0.16 2.2 NV
LP PFET (low power) lppfet 1.6 0.12 0.16 2.2 NW,BP, PV
Thin ZVT NFET

zvtnfet 1.6 0.42 2.34 2.2 ZEROVT
(thin oxide Zero Vt NFET)
Thick ZVT NFET

zvtdgnfet 2.7 0.56 2.34 5.2 ZEROVT, DG
(thick oxide Zero Vt NFET)
Thick NFET25
dgnfet 2.7 0.24 0.36 5.2 DG
(Regular IO NFET)
Thick PFET25
dgpfet 2.7 0.24 0.36 5.2 NW,BP, DG
(Regular IO PFET)
Thick NFET33 nfet33 3.6 0.40 0.50 5.2 DG, XE
Thick PFET33 pfet33 3.6 0.40 0.50 5.2 NW,BP, DG, XF
High Vt NFET33 hvtnfet33 3.6 0.40 0.50 5.2 DG, JN
High Vt PFET33 hvtpfet33 3.6 0.40 0.50 5.2 NW,BP,DG,JP
Thin Triple Well NFET nfettw 1.6 0.12 0.16 2.2 PI, NW3
Thick Triple Well NFET dgnfettw 2.7 0.24 0.36 5.2 PI, DG, NW4

Electrical Parameters and Models Available Devices and Models IBM
Table 119. Available FETs
Device Name (FET) Model Name Max1 Min Min Tox Design and
Vdd [V] LDes WDes [nm] Dummy Design
[m] [m] Levels2
Thick Triple Well NFET33 nfet33tw 3.6 0.40 0.50 5.2 T3, DG, XE, NW5
Thick Triple Well High-Vt

NFET33
hvtnfet33tw 3.6 0.40 0.50 5.2 T3, DG, JN, NW6
1. For maximum voltage use see 5.3 Front End Of Line (FEOL) Reliability Design Rules on page 461.
2. In addition to RX and PC.
3. NW ring can be shared amongst multiple nfettw devices within a single isolated pwell.
4. NW ring can be shared amongst multiple dgnfettw devices within a single isolated pwell.
5. NW ring can be shared amongst multiple nfet33tw devices within a single isolated pwell.
6. NW ring can be shared amongst multiple hvtnfet33tw devices within a single isolated pwell.
Table 120. non-FETs
Device Name Model Name Comment
Junction (forward biased) diode; 2-termi-

P+/Nwell diode dipdnw
nal model
Junction (forward biased) diode; 3-termi-

P+/Nwell diode divpnp
nal model
OP N+Diffusion Resistor opndres N type doped diffusion OP Resistor
OP P+Poly Resistor opppcres P type doped OP polysilicon resistor
P type lightly doped OP polysilicon resis-

OP RR PC Poly Resistor oprrpres
tor
OP RP PC Poly Resistor oprppres Precision Resistor
N-well Resistor nwres N-well Resistor
Low value rectangular silicided P+ Poly

Silicided Polysilicon Resistor silres
line.
Kx BEOL Resistor (x=2,3,4,5,6) kxres thin film resistor
L1 BEOL Resistor l1res thin film resistor (MA1 BEOL Metallization

option only)
Metal-to-Metal Capacitor (single Alumi-

single HP MIMCAP
(high performance)
mimcap num, MA 1 BEOL metallization option
only)

Electrical Parameters and Models Available Devices and Models
Table 120. non-FETs
Metal-to-Metal Capacitor (dual alumi-

dual HP MIMCAP
(high performance)
dualmimcap num, MA 1 BEOL metallization option
only)
Single Hi-K Metal-to-Metal Capacitor, (OL

Hi-K MIM mim with LD BEOL metallization option and
AM BEOL metallization option only)
Single Nitride Metal-to-Metal Capacitor,

Single Nitride MIM mimnit (OL with LD BEOL metallization option
only)
Dual Nitride Metal-to-Metal Capacitor,
Dual Nitride MIM dualmimnit (OL with LD BEOL metallization option
only)
(nFET-in-N-Well with tox=2.2nm)

PCDCAP thin oxide
ncap MOS Capacitor, decoupling capacitor,
Varactor
Differential thin-oxide nMOS varactor with

Differential nMOS Varactor diffncap
interdigitated fingers
(nFET-in-N-Well with tox=5.2nm)

PCDCAP thick oxide dgncap MOS Capacitor, decoupling capacitor,
varactor
Capacitor formed using 2 or more con-

Vertical Natural (BEOL)
vncap secutive thin Mx (x=1,2,3,4,5,6) metal lev-
Capacitor
els.
HA Varactor havar High Q tunable diode varactor
Differential HA junction varactor with

Differential HA Varactor diffhavar
interdigitated fingers
Inductor - LM 2X parallel stack indp LM BEOL Metallization option only
Inductor - MA ind MA 1 BEOL Metallization option only
Inductor - MA/E1 parallel indp MA 1 BEOL Metallization option only
Inductor - MA/E1 series inds MA 1 BEOL Metallization option and AM

BEOL Metallization only
OL with LD BEOL Metallization option

Inductor - LD ind
only

Inductor - LD/OL parallel indp
only

Electrical Parameters and Models Isolation Oxide (STI) Design Specifications IBM
Table 120. non-FETs

Inductor - LD/OL series inds
only

Inductor - Spiral symmetric symind
only
Inductor - Spiral symmetric par- OL with LD BEOL Metallization option

symindp
allel and AM BEOL Metallization only
Bondpad - TD/LM bondpad LM BEOL Metallization option only
Bondpad - MA bondpad MA 1 BEOL Metallization option only

Bondpad - OL with LD bondpad
only
Bondpad - AM bondpad AM BEOL Metallization option only
Inductor line - LM BEOL rfline LM BEOL Metallization option only
Inductor line - MA BEOL rfline MA 1 BEOL Metallization option only
E-fuse efuse electronic fuse
NW/SX diode diodenwx Parasitic Diode, reverse bias only
N+/PW diode diodenx Parasitic Diode, reverse bias only
Niso(PI)/SX diode diodepisx Parasitic Diode, reverse bias only
PW/Niso(PI) diode diodepwpi Parasitic Diode, reverse bias only
P+/Nwell diode diodepnw Parasitic Diode, reverse bias only
Vertical pnp esdvpnp For ESD use
N+/Sx diode esdndsx For ESD use
ESD nfet esdnfet For ESD use
ESD dgnfet esddgnfet For ESD use
ESD nfet33 esdnfet33 For ESD use

1. The MA BEOL Metallization Option may also be commonly referred to as Dual Metal or DM option.
4.2 Isolation Oxide (STI) Design Specifications

The following specifications restrict the isolation oxide or shallow trench isolation (STI) oxide width, and the
applied voltage under normal operating conditions, which may be used to ensure the acceptable leakage
level of 1.0 pA/m.

Electrical Parameters and Models Isolation Oxide (STI) Design Specifications
Voltages greater than 6.0 V may not be used on PC lines which gate n(+) diffusions separated by thick
oxide (isolation oxide) design widths of < 0.60 m.
Voltages up to 6.0 V may be used on metal lines with isolation widths down to 0.60 m on n-channel
structures.
P-channel PC gated structures may carry negative voltages (bootstrapped below ground) with Vws biases
> 0.7 V and Vgs > -3.0 V.

Electrical Parameters and Models General FET Electrical Design Considerations IBM
4.3 General FET Electrical Design Considerations

This section refers to the Regular Vt device, unless stated otherwise.
4.3.1 Maximum Operating Voltage Due to Hot Electrons

A degradation in FET device characteristics occurs as a result of exposure to high drain to source bias over
time. In section 5.3.1, Hot Carrier Effects, these phenomena are described in more detail. Hot electron
effects will limit the practical burn-in voltages that may be used with CMOS8RF (CMRF8SF), and are most
severe at shorter channel length. Circuit designers should simulate the worst case circuits to ensure stability
during worst case power supply and minimum channel length applications, see section 5.3 , "Front End Of
Line (FEOL) Reliability Design Rules" on page 461. In order to avoid device degradation during product use
conditions, the maximum potential difference allowed across source-drain during normal device operation is
1.6V.
4.3.2 Trigger and Sustaining Voltage

For the regular FETs, the trigger voltage is below 6.0 V and the sustaining voltage exceeds 3.5 V, so bipolar
action takes place far above the maximum allowed device operation voltage. See section 6.2 , "Latchup
Guidelines and Layout Constraints" on page 508.
4.3.3 Device Length and Width

The device length and width are the length and width values which are used in the electrical models and are
smaller than the design dimensions. The device length and width are a function of device design dimensions,
mask dimensions (including any compensations), and the process biases. These dimensions are referenced
with respect to the PC and RX design levels. The equations used to calculate the device length and width are
given below:
The minimal design length for the regular Vt, low Vt, and low power NFETs and PFETs is Ldesignmin =
0.120 m
The minimal design width for the regular Vt, low Vt, and low power NFETs and PFETs is Wdesignmin =
0.160 m
The worst-case minimal device length is given by Lmin = Ldesign Lptol , with Lptol = 0.022 m
Lp = Ldesign L
Weff = Wdesign W
L = 0.028 m 0.011 m for NFET and PFET (NOT including cross-chip variation)
W = 0.01 m 0.084 m for NFET and 0.04 m 0.084 m for PFET (including cross-chip variation)
4.3.4 Device Length Variation

The process variation in gate lithography, etch bias, STI height as well as mask compensation results in gate
length variation. The total gate length variation (Ltol ) includes the chip mean variation (Lchiptol) and the
across-chip variation (LACLV ).

Electrical Parameters and Models General FET Electrical Design Considerations
4.3.4.1 Chip Mean Variation (Lchiptol)

The 3 chip mean length variation (Lchiptol) refers to the length variation between two identical devices (width,
length, and orientation) on different chips. It includes chip to chip, wafer to wafer, and lot to lot variation.
For example, for regular FET, Lchiptol is 0.011 m.
4.3.4.2 Across-Chip Variation (LACLV)

The 3 cross-chip length variation (LACLV) refers to the length variation between devices with different proxim-
ity and different orientation within one chip. For regular FETs, LACLV is 0.011 m.
4.3.4.3 Total Channel Length Tolerance (Ltol)

The total channel length tolerance Ltol is the numeric sum of LACLV and Lchiptol.
For thin oxide FETs, except the ZVTNFET, the total Lp tolerance of 0.022 m is the numeric sum of the
cross-chip variation (0.011 m) and the chip mean variation (0.011 m).
For thick oxide FETs and the ZVTNFET, the total Leff tolerance of 0.032m is the numeric sum of the
cross-chip variation (0.016 m) and the chip mean variation (0.016 m).
To assure functionality:
For dynamic circuits, designers should assess leakage at the total Lp tolerance of 0.022 m (6) or
beyond a total 3 if the number of dynamic circuits is large. When the number of circuits requiring track-
ing is large, (e.g. SRAM cells) evaluation of tracking must use 4.5 sigma tracking numbers for product
robustness and good yield.
NFET and PFET hot electron analysis should be assessed at least at the minimum mean Lp variation of
-0.011m (0.016 m for the dual gate oxide device) plus the cross-chip 3 variation of 0.011 m (0.016
m for the dual gate oxide device). For large numbers of sensitive circuits 4.5 sigma analysis of the
cross-chip variation may be necessary.

4.3.4.4 Device Length Tracking
Device length tracking is the difference in device length between two devices, L = L 1 L 2 . If L1 and L2
each have standard deviation L, then the standard deviation of the tracking is:
L = L2 + L2 = 2 L
For example, the 3 variation of the channel length offset between two identical devices (width, length, and
orientation) is 2 ( 0.0085 )m .
Table 121. Gate Length Variation for thin oxide FETs (3)
Component Linewidth Variation Cross-Chip

within 200m Variation (m)1
(1) Site-to-Site variation2 0.0053 0.0085
(2) Horizontal-Vertical variation4 0.0045
(3) Nested-to-Isolated variation5 0.0053
(4) total across-chip variation (ACLV) 0.011
1. Use these numbers for linewidths placed randomly over the entire chip area.
2. This is the variation of an identical line placed randomly across the chip. Identical means
same line width and same line space along with the same local environment (both PC
and RX).
3. For identical lines/same orientation, within 200m, the process induced line width
variation is covered by section 4.3.6.3 , "Threshold Voltage Tracking for Devices" on
page 344. If one is interested in the actual linewidth variation, this number is to be
used.
4. This is the variation in line width between two otherwise identical lines except for the
orientation. Identical means same line width and same line space along with the same
local environment (both PC and RX).
5. This is the variation in line width between lines with the same orientation and same line
width, but different local environment (e.g. line space, pitch, or density).
Note that the gate length variation numbers specified above assume that the PC density requirements as
described in section 2.9 , "Important Design Guidelines" on page 84 and section 2.10 , "Pattern Density
Rules" on page 87 are satisfied.
4.3.4.5 Circuit-Path Mean Variation

The 3 across-chip variation of one circuit-path mean Lp to another circuit-path mean Lp is 0.0085 m (this
is useful for evaluating circuit-path matching within a chip, and is only true for circuits with similar
width/space/orientation topography.)

4.3.4.6 NFET Lp to PFET Lp Tracking

The 3 hot process induced NFET Lp to PFET Lp tracking is 0.014 m on the chip means. (This is useful for
examining circuits which depend upon N to P device ratios.) As an example, to calculate N to P tracking for
across-chip non-identical line and orientation, sum the N to P tracking for the chip and the Lp across-chip
tracking = (0.014 + 2 x 0.011) = 0.029 m.
4.3.4.7 Regular Vt Lp to High/Low Vt Lp Tracking

The process induced 3 variation between regular Vt NFET Lp and high/low Vt NFET Lp is 0.005 m on the
chip means. This is useful for examining circuits which depend on device ratio.
As an example, to calculate high/low Vt NFET to regular Vt NFET tracking for cross-chip non-identical line and
any orientation, sum the high/low Vt NFET to regular Vt NFET tracking for the chip and the Lp across-chip
tracking = (0.005 + 2 x 0.011) = 0.020 m.
4.3.5 Channel Width Variation

For device width variation, the following across-chip tracking variation (ACWV) values should be used:
Images 100 m apart: 0.044 m
Images > 100 m apart: 0.047 m
The chip mean variation is set at 0.040 m.
4.3.6 Threshold Voltage
4.3.6.1 Threshold Voltage Definition

The threshold voltage is defined as the gate to source bias, Vgs, at which
|Ids | = 300 nA Weff/Leff for NFET
|Ids | = 70 nA Weff/Leff for PFET
4.3.6.2 Threshold Voltage Tolerance

The threshold voltage tolerance may be calculated for any given device by combining the base value of toler-
ance with the tolerance expected from the short and narrow channel effects. The threshold tolerance, Dvt, is:
1/2
2 9 2
D vt = D vtb + --- ( Vt ) + [ V t ( L pnom ) V t ( L pmin ) ] 2 + [ V t ( W effnom ) V t ( W effmin ) ] 2
where: 2
Dvtb is the 3 base case tolerance: 0.045 V (additional end of life mismatch due to ionic Vt shift must be
taken into account when calculating the total tracking, see Reliability section).
(Vt) is the 1-sigma threshold voltage tracking as defined in section 4.3.6.6 , "Threshold Voltage Near
NW or BF or BT edges" on page 345.
The subscripts nom and min indicate the nominal and minimum device lengths and widths as defined
in section 4.3.3 , "Device Length and Width" on page 340.

4.3.6.3 Threshold Voltage Tracking for Devices
Tracking implies that the threshold of two NFETs or two PFETs on the same chip will be more similar than
those on different chips. The threshold tolerance for devices on the same chip may be calculated using the
equation in section 4.3.6.5 , "Device Current Matching for Separations Less than 200mm" on page 344.
4.3.6.4 Regular Vt to Low Vt tracking

The process (implant) induced 3 variation between regular Vt N/PFET Vt and low Vt N/PFET Vt is 0.016V.
4.3.6.5 Device Current Matching for Separations Less than 200m

Adjacent FET device current mismatch is modeled as a combination of threshold voltage mismatch and beta
(mobility) mismatch terms that vary in proportion to 1 ( WL ) :
( Ids ) 2 ( ) 2V T
----------------- ------------ + -------------------------------
2
Ids ( V GS V T )
where
K
mobility = = ----------------------------------------------------------
-
( W K W ) ( L K L )
and
KV
V T = ------------------------------------------------------------------
T
-
( W K VTW ) ( L K VTL )
and where W is the drawn device width, L is the drawn device length, and K, KW, KL, KVt, KVtW, and KVtL
are fitting coefficients which are different for each device type.
Table 122. Threshold Voltage and Mobility Mismatch equation coefficients

Device Type K KL KW KVT KVTL KVTW
NFET/
+3.00e-6 -7.00e-6 -6.00e-6 +1.35e-8 -5.00e-8 -7.00e-8
NFETTW
PFET +2.40e-6 -2.50e-7 -5.00e-6 +8.10e-9 +5.00e-8 -4.00e-8
LVTNFET +6.00e-6 +9.00e-8 -5.00e-7 +1.30e-8 0 -2.00e-7
LVTPFET +1.80e-6 -5.00e-8 -5.00e-6 +1.33e-8 -2.50e-8 -4.00e-7
LPNFET +1.15e-5 +6.00e-8 +2.00e-8 +9.00e-9 +4.00e-8 0
LPPFET +4.30e-6 -3.00e-6 -1.00e-7 +9.00e-9 +3.00e-8 -1.00e-7
Note 1: Units for L and W are meters in the mobility and Vt function calculations above.

4.3.6.6 Threshold Voltage Near NW or BF or BT edges

Devices located in close proximity to the NW or design level shapes generating BF or BT edges on mask,
such as BFMOAT or PI or JD or IND or IND_FILT or ESDIODE or ZEROVT (see Table 8, on page 59 or
Table 30, on page 127), will have an increased threshold voltage relative to devices remote from the edge.
Minimum width nFET devices have a threshold voltage increase as much as 20 20 mV (per edge) com-
pared to the nominal, and this effect is 3 to 5 times larger for thick oxide devices. This increase in threshold
voltage can impact digital circuit performance and functionality (for example: sense amplifiers, current mirrors,
etc.). This effect has been included in the compact model. Please note the special rules regarding match-
ing-critical analog considerations.
The local threshold voltage shift at a point in the active region of the device (the union of PC and RX shapes
defining the active area), depends on its drawn distance, D from each NW or BF or BT edge. The effect on the
active area due to each Nwell edge is additive. The local DeltaVth is averaged over the active area of the
device to obtain the total Vt shift. Contact the Design Manual owner for any analytical description.
This effect does not occur in thick or thin oxide ZeroVT devices.
The empirical algorithm in the compact model is intended for noise evaluation purposes only and must not be
used to tailor device threshold voltages.
Note: The Vt change will always increase the absolute value of Vt.
4.3.6.7 Mechanical stress effect on FETs

IBM has observed the impact of mechanical stress induced during wafer processing on FET devices. This
effect is accounted for when the model is extracted. The magnitude of this effect is highly variable, with typical
nfet current reductions on the order of 0 to 15% or pfet current increases on the order of 0 to 8%.
PC-RX
distance
Figure 4-1: FET distance between RX and PC impacts mechanical stress
4.3.6.8 Guidelines for Device Matching
Metal Antenna
Keep the metal antenna ratio to a minimum, preferably tying the gates to diodes at M1. If metal antennae do
occur at M1, make the ratio small or equal for the devices to be matched, and tie the gates to diffusions at M2,

Wiring Over Gates
Metal wiring over gates for each metal level should cover the same percentage of the device active area (PC
over RX) on matching devices.
Well Proximity
The NWELL mask edge should be at least 3 m from the active area (PC over RX) of devices to be matched
if the Vt matching is required to be within limits. At closer spacings, the Vt associated with that active device
is raised by an amount that increases with reduction in the space.
If a 3m spacing is impossible to achieve, identical layouts must be used. The layout must be identical with
respect to placement of the Nwell relative to the source and drain nodes of the device, and the absolute value
of the threshold will be modified by the presence of mask edge. Mirror image layouts are subject to Vt
mismatch induced by NWell misalignment which can be 20mV or larger depending on Nwell misalignment
and device type. Such asymmetric layouts must be reviewed by your IBM technical representative prior to
use.
RX Width Consideration
For precise current ratioing always use different numbers of identically designed fingers and do not expect
that the ratio of the current in a wide or long device to that of a short or narrow device is precisely represented
by the model. When using multiple fingers designed in a common active area rectangle, the carrier mobility in
the outermost fingers, adjacent to a parallel RX (active area) edge, will not match the inner fingers due to
stress propagated from the RX edge to the adjacent device region. It is advisable to use dummy fingers on
the outside of the RX edge to ensure that the inner fingers all match.
4.3.7 Effective Tox

The effective gate oxide thickness is greater than the physical Tox of the device due to gate depletion effects.
As a result the following Tox is used in the electrical models:
Tox(eff) = 3.03 0.2 nm for NFETs and Tox(eff) = 3.23 0.2 nm for PFETs
where
Tox(physical) = 2.2 0.15 nm
4.3.8 Substrate Current

Avalanche multiplication increases the channel current at high drain to source bias in the saturation region of
operation. Holes and electrons, generated by impact ionization, flow to the substrate or well and drain. This
current can be substantial and may predominate the well and substrate current at room temperatures.
For n-channel devices, the peak substrate current at Vds 1.6V will be less than 0.5 A/m at 25C.

4.3.9 Reverse Bent Gate Devices

Devices with RX bent at 45 degrees, so called Reverse Bent Gate Devices, have not been characterized
and will not necessarily be accurately represented by the FET models.

Electrical Parameters and Models Regular FET Device IBM
4.4 Regular FET Device
4.4.1 Electrical Parameters
Table 123. Electrical Parameters for Regular FETs1
Parameter Definition Unit NFET PFET
WDes/LDes Value Value
0.028 0.028
0.0112 0.011 2
L m
0.0113 0.011 3
0.0224 0.022 4
0.010 0.040
0.040 2 0.040 2
W m
0.044 3 0.044 3
0.084 4 0.084 4
Effective Tox nm 3.03 0.2 3.23 0.2
Physical Tox nm 2.2 0.15 2.2 0.15
Gate Oxide 20 1
pA/m2 5/5 (x 42)
leakage (80)5 (4)
Vtlin6 VD=0.05 V, VB=0 V V 5/5 0.170 0.045 -0.225 0.045
Vtsat 6 VD=1.2 V, VB=0 V V 5/0.12 0.355 0.050 -0.325 0.050
Vtsat 6 VD=1.5 V, VB=0 V V 5/0.12 0.340 0.055 -0.310 0.055
Vtsat 6 VD=1.2 V, VB=0 V V 0.16/0.12 0.295 0.080 -0.355 0.080
73
DIBL6 VB=0 V, Vtsat-Vtlin mV 5/0.12 76 40
+50 / -30
VD=1.2 V,
Body Effect 6 V 5/0.12 0.165 0.040 0.192 0.040
Vt-shift VB=0 ... -1 V
Sub Vt Slope VD=1.2 V, VB=0 V mV/dec 5/0.12 82 8 83 8
VD=0.05 V, VG=1.2 V,
Idlin A/m 5/5 4.00 0.60 0.68 0.10
VB=0 V
Ion VD=VG=1.2 V, VB=0 V A/m 5/0.12 530 85 190 45

Electrical Parameters and Models Regular FET Device
Table 123. Electrical Parameters for Regular FETs1
Ion VD=VG=1.5 V, VB=0 V A/m 5/0.12 770 120 315 70
23
Ion VD=VG=1.2 V, VB=0 V A 0.16/0.12 86 35
+15 / -12
Gm VD=VG=1.2 V, VB=0 V S/m 5/0.12 750 70 340 50
Ioff VD=1.2 V, VG=VB=0 V nA/m 5/Lmin 2 2.5
Ioff VD=1.2 V, VG=VB=0 V pA/m 5/0.12 300 (< 1140) 250 (< 900)
Ioff VD=1.5 V, VG=VB=0 V pA/m 5/0.12 450 (< 1820) 370 (< 1470)
Ioff VD=1.2 V, VG=VB=0 V pA 0.16/0.12 400 (< 1200) 30 (< 100)
VD=1.2 V, VG=VB=0 V,
Ioff nA/m 5/Lmin 24 14
T=85 C
Ioff nA/m 5/0.12 5.0 (< 21.0) 4.5 (< 20.5)
T=85 C
VG=VB=0 V,
Vleakage V 5/0.12 2.4 -2.5
ID=1 nA/m
VG=VB=0 V,
Vbreakdown V 5/0.12 4.3 -4.7
ID=1 A/m
30 0.4
Isx (Max) VG=0.7 V, VD=1.6 V nA/m 5/0.12
+30 / -20 +0.6 / -0.3
Cjarea Vj=0 V fF/m2 1.05 0.20 1.05 0.20
Coverl VG=0.0 V fF/m -/0.12 0.330 0.045 0.310 0.045
Cgon VG=1.2 V fF/m -/0.12 1.30 0.25 1.26 0.25
Ij Vj=1.2 V, T=25 C fA/m2 125 (< 600)) 0.5 (< 1)
Ij Vj=1.6 V, T=25 C fA/m2 750 (< 2000) 1 (< 5)
Ij Vj=1.2 V, T=85 C fA/m2 < 800 <5
Vjbreakdown
V > 10 > 10
(avalanche)
RO Delay
VDD=1.2 V psec 4/0.12 18.5 4.5
Time7

Electrical Parameters and Models Thin Triple Well NFET IBM
1. All tolerances are 3 values
2. Chip mean tolerance
3. ACLV or ACWV
4. Total tolerance
5. Worst case numbers are in parentheses
6. Threshold Voltage is defined as the gate to source bias at which |ID| = 300nA Weff/Leff for NFETs and |ID| = 70nA Weff/Leff for PFETs
7. This number depends on the exact details of the layout. This example is for Wn=4m, Wp=7m and minimum CA/M1 to PC
capacitances
4.5 Thin Triple Well NFET

See applicable NFET information in section 4.3 , "General FET Electrical Design Considerations" on page
340.

Electrical Parameters and Models Low-Vt FET Device
4.6 Low-Vt FET Device
Table 124. Electrical Parameters for Low-Vt FETs1
0.028 0.028
0.0112 0.011 2
L m
0.0113 0.011 3
0.0224 0.022 4
0.010 0.040
0.040 2 0.040 2
W m
0.044 3 0.044 3
0.084 4 0.084 4
Physical Tox nm 2.2 0.15 2.2 0.15
Vtlin5 VD=0.05 V, VB=0 V V 5/5 0.055 0.050 -0.085 0.050
Vtsat 5 VD=1.2 V, VB=0 V V 5/0.12 0.260 0.065 -0.235 0.065
Vtsat 5 VD=1.5 V, VB=0 V V 5/0.12 0.245 0.065 -0.220 0.065
Vtsat 5 VD=1.2 V, VB=0 V V 0.16/0.12 0.155 0.090 -0.275 0.090
VD=0.05 V, Vt - shift
Body effect 5 V 5/0.12 0.140 0.040 0.160 0.040
VB=0 ... 1 V
Sub-Vt slope VD=1.2 V, VB=0 V mV/dec 5/0.12 83 8 84 8
VD=0.05, VG=1.2 V,
Idlin A/m 5/5 4.25 0.20 0.85 0.035
VB=0 V
230
Ion VD=VG=1.2 V, VB=0 V A/m 5/0.12 605 90
+50 / -45
Ion VD=VG=1.5 V, VB=0 V A/m 5/0.12 850 120 355 70
Ion VD=VG=1.2 V, VB=0 V A 0.16/0.12 96 40 26 15
Ioff VD=1.2 V, VG=VB=0 V nA/m 5/Lmin 20 20

Electrical Parameters and Models Low-Vt FET Device IBM
Table 124. Electrical Parameters for Low-Vt FETs1
Ioff VD=1.2 V, VG=VB=0 V nA/m 5/0.12 3.5 (< 20.0)6 3.0 (< 12.5)
Ioff VD=1.5 V, VG=VB=0 V nA/m 5/0.12 5.0 4.5
Ioff VD=1.2 V, VG=VB=0 V nA 0.16/0.12 4.0 0.08
VD=1.2 V, VG=VB=0 V, 5/Lmin

Ioff nA/m < 150 < 100
T=85 C
Ioff nA/m 5/0.12 < 50 < 40
T=85 C
VG=VB=0 V,
Vbreakdown V 5/0.12 4.3 -4.7
ID=1 A/m
40 0.6
Isx (maximum) VG=0.7 V, VD=1.6 V nA/m 5/0.12
+100 / -20 +1.8 / -0.3
Cjarea Vj=0 V fF/m2 1.05 0.20 1.05 0.20
Coverl VG=0.0 V fF/m 0.340 0.045 0.340 0.045
Ij Vj=1.2 V, T=25 C fA/m2 < 400 <1
Ij Vj=1.2 V, T=85 C fA/m2 < 1000 <5
Vjbreakdown
V > 10 > 10
(avalanche)
3. ACLV or ACWV
4. Total tolerance

Electrical Parameters and Models LP NFET and PFET (for Low Power Applications)
4.7 LP NFET and PFET (for Low Power Applications)

Table 125. Electrical Parameter for LP FETs1
0.028 0.028
0.0112 0.011 2
L m
0.0113 0.011 3
0.0224 0.022 4
0.010 0.040
0.040 2 0.040 2
W m
0.044 3 0.044 3
0.084 4 0.084 4
Physical Tox nm 2.2 0.15 2.2 0.15
Gate Oxide 20 1
pA/m2 5/5 (x 42)
leakage (80)5 ( 4)
Vtlin6 VD=0.05 V, VB=0 V V 5/5 0.525 0.075 -0.455 0.110
Vtsat 6 VD=1.2 V, VB=0 V V 5/0.12 0.560 0.085 -0.500 0.120
Vtsat 6 VD=1.2 V, VB=0 V V 0.16/0.12 0.470 -0.465
DIBL 6 Vtsat-Vtlin, VB=0 V V 5/0.12 0.090 0.090
VD=1.2 V,
Body Effect 6 Vt-shift VB=0 ... 1 V
V 5/0.12 0.19 0.20
Sub Vt Slope VD=1.2 V, VB=0 V mV/dec 5/0.12 90 90
VD=0.05 V, VG=1.2 V,
Idlin A/m 5/5 1.9 0.4
VB=0 V
Ion VD=VG=1.2 V, VB=0 V A/m 5/0.12 325 130 125 65
Ion VD=VG=1.5 V, VB=0 V A/m 5/0.12 580 235
Ion VD=VG=1.2 V, VB=0 V A 0.16/0.12 59 17

Electrical Parameters and Models LP NFET and PFET (for Low Power Applications) IBM
Table 125. Electrical Parameter for LP FETs1
Ioff VD=1.2 V, VG=VB=0 V pA/m 5/Lmin 50 30
Ioff VD=1.2 V, VG=VB=0 V pA/m 5/0.12 1.5 2
Ioff VD=1.5 V, VG=VB=0 V pA/m 5/0.12 3 4
Ioff VD=1.2 V, VG=VB=0 V pA 0.16/0.12 3 0.8
VD=1.2 V,
Ioff nA/m 5/Lmin 500 220
VG=VB=0 V,T=85 C
Ioff pA/m 5/0.12 40 70
T=85 C
VD=1.5 V,
Ioff pA/m 5/0.12 55 88
VG=VB=0 V,T=85 C
Ioff pA 0.16/0.12 71 20
T=85 C
VG=VB=0 V,
Vbreakdown V 5/0.12 4.3 -4.4
ID=1 A/m
Cjarea Vj=0 V fF/m2 1.15 0.20 1.25 0.20
Coverl VG=0.0 V fF/m 0.330 0.320
Ij Vj=1.2 V, T=25 C fA/m2 400 (< 750) < 10
Ij Vj=1.6 V, T=25 C fA/m2 400 (< 3000) < 10
Ij Vj=1.2 V, T=85 C fA/m2 < 850 < 10
Igidl Vd=1.2 V, T=25 C pA/m 5/0.12 2 2
Igidl Vd=1.5 V, T=25 C pA/m 5/0.12 20 20
Vjbreakdown
V > 10 > 10
(Avalanche)
3. ACLV or ACWV
4. Total tolerance

Electrical Parameters and Models Regular-IO FET
4.8 Regular-IO FET

The maximum potential difference allowed across source-drain during normal device operation is 2.7V.
4.8.2 Trigger and Sustaining Voltage

For the regular I/O FETs, the trigger voltage < 8.0 V and the sustaining voltage exceeds 5.0 V, so bipolar
action takes place above the maximum allowed device operation voltage.
4.8.3 Effective Channel Length and Width

The minimal design length for the regular IO NFET and PFET is Ldesignmin = 0.240 m
The minimal design width for the regular IO NFET and PFET is Wdesignmin = 0.360 m
Lmin = Ldesign Lp tol
Lp = Ldesign L
Weff = Wdesign W
L = 0.028 m 0.016 m for NFET and L=0.028 m 0.016 m for PFET (NOT including across-chip
variation)
W = 0.000 m 0.065 m for NFET and -0.020 m 0.065 m for PFET (including across-chip varia-
tion)

Electrical Parameters and Models Regular-IO FET IBM
4.8.4 Channel Length Variation
4.8.4.1 Channel Length Tracking
Table 126. Gate Length Variation for DG FET (3)
Component Cross-Chip
Variation (m)
(1) Site-to-Site variation1 0.0120
(2) Horizontal-Vertical variation2 0.0065
(3) Nested-to-Isolated variation3 0.0077
(3) total across-chip variation (ACLV) 0.016
1. This is the variation of an identical line placed randomly across the

chip. Identical means same line width and same line space along
with the same local environment (both PC and RX).
2. This is the variation in line width between 2 otherwise identical lines
except for the orientation. Identical means same line width and same
line space along with the same local environment (both PC and RX).
3. This is the variation in line width between lines with the same
orientation and same line width but different local environment (e.g.
line space, pitch or density).
4.8.4.2 Total Leff Tolerance

The total Lp tolerance of 0.032m is the numeric sum of the Cross-Chip tracking variation (0.016 m) and
the Chip Mean variation (0.016 m).

For device width variation, the following cross-chip tracking variation (ACWV) values should be used:

Electrical Parameters and Models Regular-IO FET
4.8.6 Device Current Matching

(mobility) mismatch terms that vary in proportion to 1 ( WL ) . Please refer to section 4.3.6.5 , "Device Cur-
rent Matching for Separations Less than 200mm" on page 344 for detailed equations.

DGNFET/
+9.70e-6 0 -3.00e-6 +1.05e-8 +1.55e-7 0
DGNFETTW
DGPFET +1.00e-5 -2.00e-6 -1.00e-5 +1.00e-8 +8.00e-8 -2.00e-7

Electrical Parameters and Models Regular-IO FET IBM
Table 128. Electrical Parameters for Regular-IO FETs1
0.028 0.028
0.0162 0.016 2
L m
0.0163 0.016 3
0.0324 0.032 4
0.000 -0.020
0.030 2 0.030 2
W m
0.035 3 0.035 3
0.065 4 0.065 4
Physical Tox nm 5.2 0.4 5.2 0.4
Vtlin5 VD=0.05 V, VB=0 V V 5/5 0.465 0.060 -0.445 0.055
0.410 -0.440
Vtsat 5 VD=2.5 V, VB=0 V V 5/0.24
+0.075 / -0.095 -0.075 / +0.095
VD=0.05 V,
Body Effect 5 V 5/0.24 0.110 0.040 0.250 0.040
Vt-shift VB=0 ... 1 V
Sub Vt Slope VD=2.5 V, VB=0 V mV/dec 5/0.24 80 8 85 8
260
Ion VD=VG=2.5 V, VB=0 V A/m 5/0.24 660 100
+75 / -50
Ioff VD=2.5 V, VG=VB=0 V pA/m 5/Lmin 150 20
Ioff VD=2.5 V, VG=VB=0 V pA/m 5/0.24 10 (< 260)6 10 (< 60)
Ioff nA/m 5/Lmin < 3.0 < 0.2
T=85 C
Ioff nA/m 5/0.24 < 1.0 < 0.1
T=85 C
VD=1.25 V,
Early Voltage V 5/0.24 18 23
(VG-Vt)=0.3 V
Gmsat Vgs=Vds=2.5 V S/m 5/0.24 330 50 170 20

Electrical Parameters and Models Thick Triple Well NFET
Table 128. Electrical Parameters for Regular-IO FETs1
VG=VB=0 V,
Vleakage V 5/0.24 > 4.0 > 4.0
ID=0.1 nA/m
VG=VB=0 V,
Vbreakdown V 5/0.24 > 6.0 > - 6.0
ID=1 A/m
Rext m 225 30 450 30
1.10 0.02
Isx (Max) VG=1.35 V, VD=2.70 V A/m 5/0.24
+0.40 / -0.20 +0.02 / -0.015
Cjarea Vj=0 V fF/m2 1.0 0.2 1.0 0.2
Coverl VG=0.0 V fF/m 0.315 0.045 0.315 0.045
Ij Vj=2.5 V fA/m2 < 200 <1
Ij Vj=2.5 V, T=85 C fA/m2 < 400 <5
Vjbreakdown
V > 10 > 10
(Avalanche)
3. ACLV or ACWV
4. Total tolerance
4.9 Thick Triple Well NFET

See applicable NFET information in section 4.8 , "Regular-IO FET" on page 355.
4.10 3.3V I/O FET


Electrical Parameters and Models 3.3V I/O FET IBM
4.10.2 Sustaining Voltage
For the 3.3V I/O FETs the sustaining voltage exceeds 7V, so bipolar action takes place far above the
maximum allowed device operation voltage.

The minimal design length for the 3.3V IO NFET and PFET is Ldesignmin = 0.400 m
The minimal design width for the 3.3V IO NFET and PFET is Wdesignmin = 0.500 m
Lp = Ldesign L
Weff = Wdesign W
L = 0.065 m 0.016 m for NFET and L= 0.110 m 0.016 m for PFET (NOT including across-chip
variation)
tion)
4.10.3.1 Channel Length Variation

The total Leff tolerance of 0.032 m is the numeric sum of the across-chip tracking variation (0.016 m) and

For device width variation, the following cross-chip tracking variation values should be used:

Electrical Parameters and Models 3.3V I/O FET


NFET33 +7.00e-6 -3.00e-7 -8.00e-7 +1.20e-8 +2.00e-7 -3.00e-7
PFET33 +7.50e-6 -3.60e-6 -4.00e-6 +8.50e-9 +2.50e-7 -3.00e-7

Electrical Parameters and Models 3.3V I/O FET IBM
Table 130. Electrical Parameters for 3.3V I/O FETs1
0.065 0.110
0.0162 0.016 2
L m
0.0163 0.016 3
0.0324 0.032 4
0.000 -0.020
m 0.030 2 0.030 2
W
0.035 3 0.035 3
0.065 4 0.065 4
Vtlin5 VD=0.05 V, VB=0 V V 5/5 0.460 0.065 -0.420 0.052
Vtsat 5 VD=3.3 V, VB=0 V V 5/0.40 0.380 0.090 -0.320 0.055
VD=0.05 V,
Body Effect 5 V 5/0.40 0.121 0.030 0.180 0.015
Ion VD=VG=3.3 V, VB=0 V A/m 5/0.40 740 91 380 84
VD=1.35 V
Isx nA/m 5/0.40 200 1
VG=2.7 V, VB=0 V
Ioff VD=3.3 V, VG=VB=0 V pA/m 5/0.40 30 30
VG=VB=0 V,
Vbreakdown V 5/0.40 > 8.5 > - 7.0
ID=1 A/m
Rext m 5/0.40 300 900
Cjarea Vj=0 V fF/m2 0.8 0.2 0.8 0.2
Coverl VG=0.0 V fF/m 0.40 0.06 0.40 0.06
Ij Vj=3.3 V fA/m2 600 (< 3000)6 <1

3. ACLV or ACWV

Electrical Parameters and Models Thick Triple Well NFET33
4. Total tolerance
4.11 Thick Triple Well NFET33

See applicable NFET information in section 4.10 , "3.3V I/O FET" on page 359.
4.12 3.3V High-Vt I/O FET


For the 3.3V High-Vt I/O FETs the sustaining voltage exceeds 7V, so bipolar action takes place far above the
maximum allowed device operation voltage.

The minimal design length for the 3.3V High-Vt IO NFET and PFET is Ldesignmin = 0.400 m
The minimal design width for the 3.3V High-Vt IO NFET and PFET is Wdesignmin = 0.500 m
Lp = Ldesign L
Weff = Wdesign W
L = 0.065 m 0.016 m for NFET and L= 0.110 m 0.016 m for PFET (NOT including across-chip
variation)
tion)
4.12.3.1 Channel Length Variation

The total Leff tolerance of 0.032 m is the numeric sum of the across-chip tracking variation (0.016 m) and

Electrical Parameters and Models 3.3V High-Vt I/O FET IBM
For device width variation, the following cross-chip tracking variation values should be used:
The chip mean variation is set at 0.03 m

Electrical Parameters and Models 3.3V High-Vt I/O FET


HVTNFET33 +7.00e-10 -3.00e-7 -8.00e-7 +1.20e-8 +2.00e-7 -3.00e-7
HVTPFET33 +7.50e-10 -3.60e-6 -4.00e-6 +8.50e-9 +2.50e-7 -3.00e-7

Electrical Parameters and Models Thick Triple Well High-Vt NFET33 IBM
Table 132. Electrical Parameters for 3.3V High-Vt I/O FETs1
0.065 0.110
0.0162 0.016 2
L m
0.0163 0.016 3
0.0324 0.032 4
0.000 -0.020
m 0.030 2 0.030 2
W
0.035 3 0.035 3
0.065 4 0.065 4
Vtlin5 VD=0.05 V, VB=0 V V 5/5 0.580 0.080 -0.600 0.080
Vtsat 5 VD=3.3 V, VB=0 V V 5/0.40 0.525 0.075 -0.480 0.070
Ion VD=VG=3.3 V, VB=0 V A/m 5/0.40 720 100 310 45
Ioff VD=3.3 V, VG=VB=0 V pA/m 5/0.40 0.5 (< 5) 6 1 (< 10) 6

VG=VB=0 V,
Vbreakdown V 5/0.40 > 8.5 > - 7.0
ID=1 A/m
Rext m 5/0.40 300 900
Cjarea Vj=0 V fF/m2 0.8 0.2 0.8 0.2
Coverl VG=0.0 V fF/m 0.40 0.06 0.40 0.06

3. ACLV or ACWV
4. Total tolerance
4.13 Thick Triple Well High-Vt NFET33

Electrical Parameters and Models Thin oxide Zero-Vt NFET
See applicable NFET information in section 4.12 , "3.3V High-Vt I/O FET" on page 363.
4.14 Thin oxide Zero-Vt NFET

The maximum potential difference allowed across source-drain during normal device operation is 1.6 V.

Snapback and sustaining have not been measured on this device, but with the relatively long channel
length allowed for this device it is expected to exceed 3 volts for all cases.

The device effective length and width are the length and width values which are used in the electrical models
and are smaller than the design dimensions. The device effective length and width are a function of device
design dimensions, mask dimensions (including any compensations), and the process biases. These dimen-
sions are referenced with respect to the PC and RX design levels. The equations used to calculate the effec-
tive device length and width are given below:
The minimum design length for the thin oxide Zero-Vt NFET is Ldesignmin = 0.420 m
The minimum design width for the thin oxide Zero-Vt NFET is Wdesignmin = 2.340 m
Leff = Ldesign L
Weff = Wdesign W
L = 0.030 m 0.016 m for the thin oxide ZVTNFET (NOT including across-chip variation)
W = 0.250 m 0.250 m for the thin oxide ZVTNFET (including across-chip variation)

The channel length variation is expected to be the same as given for the I/O NFET. The minimum allowable
channel length for the zero-Vt device is so long, however, that this information should be less relevant.

Even though the device width variation is considerably larger than that for other MOSFETs, the minimum
allowable channel width for the zero-Vt device is so wide that this information should be of minimal impor-
tance.

Electrical Parameters and Models Thin oxide Zero-Vt NFET IBM

ZVTNFET +8.00e-6 0 -1.00e-6 +5.50e-9 +2.00e-7 1.00e-6

Electrical Parameters and Models Thin oxide Zero-Vt NFET
Table 134. Electrical Parameters for thin oxide Zero-Vt NFET1
WDes/LDes Value
Parameter Definition Unit
0.030
0.0162
L m
0.0163
0.0324
0.250
0.180 2
W m
0.070 3
0.250 4
Effective Tox nm 3.03 0.2
Physical Tox nm 2.2 0.15
Gate Oxide
Breakdown IG<10 A/m2 V > 4.5
Voltage
Vtlin5 VD=0.05 V, VB=0 V V 5/5 -0.010 0.045
Vtsat 5 VD=1.2 V, VB=0 V V 5/0.42 0.005 0.055
VD=1.2 V,
Body Effect 5 V 5/0.42 0.025 0.010
Sub Vt Slope VD=1.2 V, VB=0 V mV/dec 5/0.42 68
Ion VD=VG=1.2 V, VB=0 V A/m 5/0.42 410 60
Isx VG=0.7 V, VD=1.6 V nA/m 5/0.42 2
Cjarea Vj=0 V fF/m2 0.3 0.2
Coverl VG=-0.3 V fF/m 0.430 0.065
Ij Vj=1.2 V fA/m2 < 10
Ijsw Vj=1.2 V fA/m 80

3. ACLV or ACWV
4. Total tolerance

Electrical Parameters and Models Thick Oxide Zero-Vt NFET IBM
5. Threshold Voltage is defined as the gate to source bias at which |ID| = 300nA Weff/Leff for NFETs and |ID| =
70nA Weff/Leff for PFETs
4.15 Thick Oxide Zero-Vt NFET

The maximum potential difference allowed across source-drain during normal device operation is 2.7 V.

Snapback and sustaining have not been measured on this device, but with the relatively long channel length
allowed for this device it is expected to exceed 6 volts for all cases.

The minimal design length for the thick oxide Zero-Vt NFET is Ldesignmin = 0.560 m
The minimal design width for the thick oxide Zero-Vt NFET is Wdesignmin = 2.340 m
Leff = Ldesign L
Weff = Wdesign W
L = 0.028 m 0.016 m for thick oxide ZVTNFET (NOT including across-chip variation)
W = 0.300 m 0.250 m for the thick oxide ZVTNFET (including across-chip variation)

The channel length variation is expected to be the same as given for the I/O NFET. The minimum allowable
channel length for the zero-Vt device is so long, however, that this information should be less relevant.

Even though the device width variation is considerably larger than that for other MOSFETs, the minimum
allowable channel width for the zero-Vt device is so wide that this information should be of minimal impor-
tance.

Electrical Parameters and Models Thick Oxide Zero-Vt NFET


ZVTDGNFET +2.00e-5 +1.00e-7 -9.00e-5 +1.00e-8 +3.50e-7 -5.00e-7

Electrical Parameters and Models Thick Oxide Zero-Vt NFET IBM
Table 136. Electrical Parameters for Thick oxide ZVT NFET1
Parameter Definition Unit
WDes/LDes Value
0.028
0.0162
L m
0.0163
0.0324
0.300
0.180 2
W m
0.070 3
0.250 4
Effective Tox nm 5.9 0.5
Physical Tox nm 5.2 0.5
Gateoxide
Breakdown IG <10 A/m V > 8.5
Voltage
Vtlin5 VD=0.05 V, VB=0 V V 5/5 0.040 0.045
Vtsat 5 VD=2.5 V, VB=0 V V 5/0.56 0.070 0.060
VD=2.5 V,
Body Effect 5 V 5/0.56 0.04 0.01
Sub Vt Slope VD=2.5 V, VB=0 V mV/dec 5/0.56 70 10
Ion VD=VG=2.5 V, VB=0 V A/m 5/0.56 520 60
Cjarea Vj=0 V fF/m2 0.3 0.2
Coverl VG=-0.3 V fF/m 0.36 0.045
Ij Vj=2.5 V fA/m2 <10
Ij Vj=2.5 V, T=85 C fA/m2 <20
Ijsw Vj=2.5 V fA/m 80
Ij=1 A,
Vjavalanche V > 10
Area=200 m x 200 m

Electrical Parameters and Models Thick Oxide Zero-Vt NFET
3. ACLV or ACWV
4. Total tolerance
5. Threshold Voltage is defined as the gate to source bias at which |ID| = 300nA Weff/Leff for NFETs and |ID| =
70nA Weff/Leff for PFETs

Electrical Parameters and Models T3 Isolation Well IBM
4.16 T3 Isolation Well
4.16.1 Introduction
4.16.1.1 T3 Design and Mask Level

Device placement within the T3 isolation well has a few restrictions as listed in the sections below.
4.16.1.2 IBLK Utility Level

Except for the ability to form an electrical connection to the T3 isolation region, all devices are restricted from
being placed within the T3 isolation well perimeter region, where the IBLK shape is present.
4.16.2 Regular Vt
NFET and PFET are supported within the T3 isolation well.
4.16.3 Thin Triple Well (Regular Vt) in PI

NFETTW remain supported in the technology for the PI triple well. However, PI triple well and T3 isolation
well or devices must be independent of each other.
4.16.4 Low Vt
LVTNFET and LVTPFET are supported within the T3 isolation well.
4.16.5 Low Power

LPNFET and LPPFET are supported within the T3 isolation well.
4.16.6 Regular IO
DGNFET and DGPFET are supported within the T3 isolation well.
4.16.7 Thick Triple Well (Regular Vt) in PI

DGNFETTW remain supported in the technology for the PI triple well. However, the PI triple well and T3
isolation well or devices must be independent of each other.
4.16.8 3.3V I/O

NFET33 and PFET33 are supported within theT3 isolation well.

Electrical Parameters and Models T3 Isolation Well
4.16.9 3.3V High-Vt I/O

HVTNFET33 and HVTPFET33 are supported within theT3 isolation well.
4.16.10 Thin Oxide Zero-Vt NFET

ZVTNFET is not supported within the T3 isolation well.
4.16.11 Thick Oxide Zero-Vt NFET

ZVTDGNFET is not supported within T3 isolation well. See rule T3W14a (ZEROVT dummy design level
exists in the thick ox zero vt device).

Electrical Parameters and Models Junction Diodes IBM
4.17 Junction Diodes
4.17.1 STI-Bounded Breakdown
Table 137. Reverse-Bias Breakdown Voltage (V), IL = 1A, Area = 100 x 100m2
Device P+ / N-Well N+ / P-Well N-Well /

Substrate
Regular Vt > 5.5 >7 > 10
Thick Oxide >7 >7 > 10
Table 138. intra-well punch through voltage (V), IL = 1nA/m
Diffusion Space n+ / n+ p+ / p+
0.18 m >4 >7
0.36 m >4 >7
4.17.2 Junction Capacitance

Capacitances of N+, P+, and N-well diffusions are specified in the models. The junction area and perimeter
components of capacitance are given by:
Area component: Vbx is the source or drain diffusion to substrate/well bias (Vbx <0 for reverse bias).
MJ
C jA ( V ) = CjA ( T ) 1 -------------------------------------------------------------
Vbx
PB TPB ( T Tref )
STI bordered perimeter component: (Vbx<0)
MJSW
C jsw ( V ) = Cjsw ( T ) 1 -----------------------------------------------------------------------------------
Vbx
PBSW TPBSW ( T Tref )
Poly bordered perimeter component: (Vbx<0)
MJSWG
C jswg ( V ) = C jswg ( T ) 1 --------------------------------------------------------------------------------------------
Vbx
PBSWG TPBSWG ( T Tref )
where T= Temperature in C , Tref=25C and

CjA ( T ) = CjA ( 1 + Tc j ( T Tref ) )
Cjsw ( T ) = Cjsw ( 1 + Tcjsw ( T Tref ) )
Cjswg ( T ) = Cjswg ( 1 + Tcjswg ( T Tref ) )

Electrical Parameters and Models Junction Diodes
A tolerance of +/- 20% applies. Nominal values of the coefficients are given below.
Table 139. Junction Capacitances
Structure Regular Vt device Thick Oxide device N-Well

N+ diffusion P+ diffusion N+ diffusion P+ diffusion
CjA
Area component 1.050 1.050 1.000 1.000 0.93
(fF/m2)
Cjsw
Perimeter compo-
0.050 0.050 0.029 0.045 0.50
nent, STI bordered
(fF/m)
Cjswg
Perimeter compo-
0.380 0.415 0.195 0.315 -
nent, poly bordered
(fF/m)
When modeling junction capacitance, the substrate/N-well resistance from the bottom of the junction to the
substrate/N-well contact should be included. The junction capacitance is given by:
C j ( V ) = C jAt ( V ) + C jswt ( V ) + C jswgt ( V )
The following two examples illustrate how to calculate the area and perimeter terms:
1. Rectangular diffusion bounded on all four sides by STI (shallow trench isolation)
C jAt ( V ) = C jA ( V ) ( ( Length + 2b ) ( Width + 2b ) )
C jswt ( V ) = 2C jsw ( V ) ( ( Length + 2b ) + ( Width + 2b ) )
2. Rectangular diffusion bounded by an FET gate at the long end and STI on the other three sides
C jAt ( V ) = C jA ( V ) ( ( Length + b + a ) ( Width + 2b ) )
C jswt ( V ) = C jsw ( V ) ( Width + 2b ) + 2C jsw ( T ) ( Length + b + a )
C jswgt ( V ) = Cjsgw ( V ) ( Width + 2b )
where
Length = design length (STI to PC dimension if a FET), m
Width = design width (STI to STI dimension), m
a = the bias per edge (E8) (see Table 179, Extraction Parameters for Diffusion, on page 427)
b = the bias per edge (E8) (see Table 179, Extraction Parameters for Diffusion, on page 427)
Notes: T3 to SX breakdown voltage is not available

Resistor Models IBM
4.18 Resistor Models

The CMOS8RF (CMRF8SF) technology currently provides eight types of resistors: OP N+ diffusion (opn-
dres), OP P+ polysilicon (opppcres), OP RP polysilicon (oprppres), OP RR polysilicon (oprrpres), silicided
polysilicon (silres), N-well (nwres), Kx (x = 2,3,4,5,6) BEOL (kxres) and L1 BEOL (l1res) resistors. We note
that the silicided polysilicon resistor is not yet qualified. Supported resistor geometries include squares
and rectangles. Other irregular shapes, such as dog bones or L-shapes, are not supported. The models and
design tools have been constructed to allow the designer to select any length/width ratio that will yield the
optimum physical size resistor for a particular design situation and produce the specified resistance value.
The length of the OP mask determines the length of the OP resistor; the CA to CA spacing determines the
length of the silicided polysilicon resistor, the F1BAR to F1BAR spacing determines the length of the L1 resis-
tor, and the VL to VL spacing determines the length of the Kx resistor. Resistors with more than two contacts
to the body of the resistor such as resistors with taps in the middle are not supported by these models.
The N+ S/D and N-well resistors should be placed over substrate. The polysilicon resistors, including the
silicided polysilicon, can be placed entirely over substrate (P-well ), an N-well (NW), or inside an isolation tub;
but a single resistor cannot be placed so that it partially covers more than one type of these underlying bulk
regions. In addition, the polysilicon resistors except for the silicided polysilicon resistor can be placed over BB
(P- substrate). The resistor models are all three terminal devices. So, in schematic designs, the underlying
parasitic diode(s), e.g. NW/SX diode for the case of a polysilicon resistor over NW, is(are) not included.
Designers must ensure that the bulk connection is tied to the proper node in their designs. We note
that these parasitic diodes are included in extraction. The polysilicon resistors, as modeled, cannot be placed
over thin oxide (RX). The L1 or Kx resistor models assumes that there are no other devices under nor wiring
either above or under the L1 or Kx resistor. The L1 or Kx resistor parasitic capacitance will not be accurate if
these assumptions are not met. Further, any parasitic capacitance involving the L1 or Kx resistor is not
calculated by any of the extraction tools.
All resistors except the N-well resistor (see Rule T3W13, NW_RES covers this device) are supported within
T3 isolation well. BFMOAT variants of resistors are NOT supported in the T3 isolation well (per truth table and
Rule T3W14a).

Resistor Models
4.18.1 Resistor Design Specifications

The following specifications may be used as a guide in applications for the CMRF8SF resistors.
Table 140. Resistor Design Specifications
Specification N+ S/D N-Well Silicided P+ Poly RP Poly RR Poly Kx BEOL L1 BEOL
Resistor Resistor Poly Resistor Resistor Resistor Resistor Resistor
Resistor
Sheet Resis- 73 / 540 / 7 / 340 / 228 / 1700 / 58.5/ 60 /
tance
(0V, 25 C)
Body Temp tc1=1810 tc1=1175 tc1=3260 tc1=77 tc1=45 tc1=-117 tc1=-375 tc1=-405
Coefficient tc2= 0 tc2=0.20 3 tc2=0.45
tc2=2.60
(ppm / C)
End Temp 2100 3000 1860 -1220 750 -1220 2500 0
Coefficient
(ppm / C)
Voltage 0.0900 1.68 0 0 0 -0.0300 0 0
Coefficient
(% per Volt)
Voltage Limit 5.50 V 5.50 V 5.50 V 5.50 V 5.50 V 5.50 V 5.50 V 5.50 V
Current Limit 1 mA/m 1 mA/m 0.5 For P+ Poly, RP Poly, RR Poly, Kx BEOL and L1 Resistors, see
mA/m section 5.3.7 , Resistor Reliability on page 483.
(per resistor
width)
4.18.2 Resistor Models

There are four separate design equations for the different resistors. The resistor models assume minimum
groundrule spacings for the placement of the contacts consistent with the layout rules contained in the
resistor pcells. Example layout diagrams are shown, along with the nominal resistance calculations.
For the N+ S/D, P+ polysilicon, and RP polysilicon resistors, the nominal value resistance equation at 25 C
and 0 volts is:
R nom = Rs ------ + 2 ---------------

L Rend
k
W W
where:
Rs = Sheet Resistance in k/
Rend = End Resistance in k-m
L = LOP m LOP = Design Length (OP length) in m
W = WD + dw m WD = Design Width (RX or PC width) in m
Values for the parameters in the above equations are given in Table 141.

Resistor Models IBM
OP
PC or RX
CA CA
W
CA CA
Figure 90. Example layout for the N+ S/D, P+ Poly, and RP Poly resistor types: opndres, opppcres, and oprppres
For the RR polysilicon resistor, the nominal value resistance equation at 25 C and 0 volts is:
L ( 2 Lbn ) Rbn Lbn
R nom = Rs -------------------------------- + 2 --------------------------- + 2 ---------------
Rend
k
W W W
where:
Rs = Sheet Resistance in k/ Rbn = P+ Poly Sheet Resistance in k/

Rend = End Resistance in k-m Lbn = BN overlap OP Length in m
L = LOP m LOP = Design Length (OP length) in m
W = WD + dw m WD = Design Width (PC width) in m
Values for the parameters in the above equations are given in Table 141
Lbn
OP
CA CA
W
CA CA
PC
BN
L
Figure 91. Example layout for RR Polysilicon resistor type: oprrpres

Resistor Models
For the silicided polysilicon (silres), L1 (l1res), and Kx (kxres) resistors, the nominal value resistance equation
at 25 C and 0 volts is:
R nom = Rs ------ + 2 ---------------

L Rend
k
W W
where:
Rend = End Resistance in k-m
L = LRAV m LRAV= Design Length (via to via length) in m
W = WD + dw m WD = Design Width (L1 or Kx width) in m
CA/F1BAR / VL CA/F1BAR / VL
L1
W
L
Figure 92. Example layout for Silicided Polysilicon, L1 BEOL, and Kx BEOL resistor type: silres, l1res and kxres
For the N-well resistor (nwres), the nominal value resistance equation at 25 and 0 volts is:
R nom = Rs ------ + 2 ----------------------------------------------------------------------------------

L Rend
k
W ( 0.8 + delrx ) ( W 1.8 + delrx )
where:
Rend = End Resistance in k-m2
L = LRAV m LRAV= Design Length (Rx to Rx length) in m
W = WD + dw m WD = Design Width (N-well width) in m
delrx = -0.045 m

Resistor Models IBM
Rx Contact Rx Contact
Nwell
W
L
Figure 93. Example layout for N-well resistor type: nwres
Table 141. Resistor Design Parameters
Resistivity opndres silres nwres opppcres oprppres oprrpres kxres l1res

Parameters Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor
Rs (k/) .073 .007 .540 .340 .228 1.70 0.0585 .060
Rend .012 .00342 0.2702 .054 .045 .054 .020 .020
(k-m)
Rbn (k/) n/a 1 n/a 1 n/a 1 n/a 1 n/a 1 .340 n/a 1 n/a 1
Shape Bias
dw (m) -0.034 0.017 -0.02 -0.031 -0.031 -0.073 0.22 0.22
1 1 1 1 1 1
Lbn (m) n/a n/a n/a n/a n/a .439 n/a n/a 1
Note:
1. An unsilicided P+ (BN) region has an affect only in the RR polysilicon resistor.
2. End resistance of the N-well resistor is a vertical resistance in to the n-well and therefore has units of k-m2
4.18.3 Resistor Geometry

The minimum allowable drawn dimensions are shown in Table 142. It is highly recommended that resistors
be made larger than minimum lengths and widths to improve both tolerance and matching (see the layout
rules for the recommended minimum dimensions). Note that the minimum width values are not determined
from the layout rules for OP over RX (or PC), which would result in smaller values for the minimum resistor
widths. Rather, the minimum width values in Table 142 are obtained from the layout rules regarding the
dimensions of CA and the minimum CA to RX (or PC) edge distance. Since dog-bone shapes are not
supported, the larger values are used to specify the minimum widths allowed for the resistors.
Table 142. Minimum Groundrule Resistor Layout Dimensions
Layout Dimen- OP Silicided N-Well OP P+Poly OP RP OP RR Kx L1

sion N+Diffusion Poly
Width (m) 0.28 (0.44) 0.34 3 0.20 (0.34) 0.74 0.741 53 52
Length (m) 0.44 1.0 3 0.80 0.80 1.06 5 8

Resistor Models
1. Refer to ground rule RR15

2. The maximum width is 30 m, see GR L11a
3. The maximum width is 75 m, but it is recommended to not exceed 30 m. See GR KX1a (R).
Parenthetical values in Table 142 indicate minimum widths for best resistor performance. These values are
calculated using the recommended values for ground rules 204 and 209. This will ensure that there is no
border leakage for the diffusion resistors and that the contacts are fully landed on the PC for the polysilicon
resistors.
Design Layout Reminder
Strict adherence to the groundrules and layout details provided in the device set is recommended to ensure
full and consistent device model and design tool compatibility and accuracy. Should you require modeling
support for geometries other than those described here, please contact your IBM Product Engineers.
4.18.4 Voltage Coefficient of OP Resistance

As the voltage across the junction isolating the N+ diffusion or N-well resistor from the substrate changes, the
resistance of the resistor changes. The voltage dependence for the resistors is calculated as a function of the
resistor to substrate reverse bias. The voltage (Vavg) is an average of the voltage difference between the
resistor and the substrate. Note that the N+ diffusion resistor must always be positive-biased relative to the
substrate in order not to forward bias the junction between the resistor and the substrate. The equation below
calculates the change factor used by the model to adjust the 0V resistance value according to the applied
voltage bias. A similar phenomenon has been seen with the RR polysilicion resistor; the resistance various
slightly as a function of back bias. The VCR parameters are given in Table 140.
2
VCR X = ( 1.0 + VCR 10 V avg )
4.18.5 Temperature and Self-Heating Effects

The resistivity (Rs) and end resistance (Rend) of each of the various types of resistors varies with
temperature. This temperature variation is handled through the standard HSpice or spectre resistor model
equations with the Rs and Rend temperature coefficients given in Table 140.
In addition, the N-well (nwres), RR polysilicon (oprrpres), Kx BEOL (kxres), and L1 BEOL (l1res) resistors are
observed to have self-heating effects at high current levels, those approaching the limits specified in Table
140. Self-heating is expressed in terms of the resistivity possessing a voltage dependence that varies as the
square of the voltage across the resistor. Including the geometrical scaling, the resistance variation due to
self-heating is given by the equation
R = R o 1 + ---------------- A msh V 2
ksh
A Ro
where:
A = L OP W D , LOP (m) and WD(m) being the drawn OP length and PC width, respectively for
the RR (oprrpres) resistor.

Resistor Models IBM
A = L OP ( RAV ) W D , LOP(RAV) (m) is the drawn OP length (or drawn L1 resistor length) and WD is the
drawn width. Values for the parameters in this expression are given in Table 143.
Table 143. Self-Heating Coefficients
Resistor Type ksh msh
N-Well Resistor 120 -0.05
OP RR Poly Resistor -130 0.18
Kx BEOL Resistor -100 0.25
L1 BEOL Resistor -110 0.625
Thermal time constants for self-heating were derived for the OP RR Poly resistor as well as the Kx BEOL
resistor. For the RR resistor the thermal time constant varied inversely with area, from 35 ns (1m x 5m) to
138ns (30m x 120m). The Kx resistor showed a slightly slower time response varying from 80ns (5m x
5m) to 269ns (30m x 120m). The models do not support thermal time constants for self-heating, they are
provided here as a guideline for applications where the change in resistance with time for large DC biases
may be important.
4.18.6 Resistor Tolerance

The resistor tolerance is defined based on measured variation of both geometric process parameters and
sheet resistivities. In most cases, the dominant variation of resistance is due to only a few of the process
parameters defining a resistors value.
The models define statistical distributions for each resistance equation parameter as follows:
Table 144. Resistor Tolerance Parameters
Tolerance opndres silres nwres opppcres oprppres oprrpres kxres l1res
Parameter Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor
Trs (k/) 0.0095 0.003 0.110 .051 .0182 .340 .00468 .0048
Trend 0.012 -0.00152 0.0653 .016 0.030 .016 .0202 .0202
(k-m) +0.00418
Tw (m) 0.04 0.022 0.24 0.1 0.1 0.1 0.14 0.20
Tlbn (m) n/a 1 n/a 1 n/a 1 n/a 1 n/a 1 0.11 n/a 1 n/a 1
Note: Tolerance values represent 3-sigma process capability.
1. An unsilicided P+ (BN) region has an affect only in the RR polysilicon resistor.
2. The tolerance for these end resistances are described by a non-symmetric distribution. The range of values for the end resistance,
regardless of resistor type, is 5-45 -m.
3. End resistance of the N-well resistor is a vertical resistance in to the n-well and therefore has units of k-m2
The 3-sigma tolerance for the N+ S/D diffused, N-well, P+ polysilicon, RP polysilicon, silicided polysilicon, KX
BEOL, and L1 BEOL resistors can be estimated by:

Resistor Models
2 ( Tw R 2
nom )
2
( Trs L ) ( 2 Trend )
T = ------------------------
- + --------------------------------- + ------------------------------------
2 2 2
W W W
The values for the tolerances are given in Table 144.
.The 3-sigma tolerance for the RR polysilicon resistor can be estimated by:
2 2 2
( Trs ( L 2Lbn ) ) ( Tw ( Rs ( L 2Lbn ) + 2 Rbn Lbn + 2Rend ) ) ( 2Tlbn ( Rs Rbn ) )
T = - + -------------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------- - + ----------------------------------------------------------
-
2 4 2
W W W
The tolerance parameter values for these equations can be found in the preceding table. Nominal sheet
resistivities and definitions of all of the effective width and length dimensions can be found in Resistor Design
Specifications on page 379. Each of these terms can be significant in determining the overall tolerance,
depending on the actual width and length of the resistor layout. A corresponding term involving Trbn was
found to be insignificant over a typical range of lengths and widths. For large resistor dimensions, sheet
resistivity tolerances will be the most dominant effect.
4.18.7 Resistor Matching

The percentage matching for identical, adjacent resistors at the same orientation, at the same temperature, is
given by the equation below. It should be noted that any interconnect parasitic resistance and the voltage
coefficient of resistance may have an effect at these matching levels. When matching ratioed resistors, the
resistor must be built by combining identical unit resistors either in parallel or in series. Care should be taken
to adhere to symmetrical layout of matched resistors. Considerations should not only include length and
width, but metal coverage and symmetry of generated levels, i.e. special care should be given to assure that
any block mask levels being generated are present on both matched resistors.
2 2 2
MA MW ML
M = -------------- + ------------- + -----------
W L W2 L
2
.
Values for the matching parameters for each resistor are defined as follows:
Table 145. Resistor Matching Equation Parameters
Matching opndres silres nwres opppcres oprppres oprrpres kxres l1res
Parameters Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor
Ma 4.0 0.7 1.7 4.0 7.0 5.0 0.6 1.5
Mw 0 0.4 1.0 1.0 2.02 1.0 0.5 0
Ml 2.01 0.2 0 0 0 0 0.387 0
Note: Matching values represent 3-sigma limits.
1. For these devices the length term is Ml2 / (W * L2)
2. For these devices the length term is Mw2 / (L * W2)

Resistor Models IBM
4.18.7.1 Resistor Parasitic Capacitance

The resistor models assume minimum groundrule spacings for the placement of the contacts consistent with
the layout rules contained in the resistor pcells. The total area and perimeter used in the calculation of the
parasitic capacitance of the resistors is based on this assumption.
The parasitic capacitance of the resistors is composed of both an area and a perimeter component. The
overall length and width for parasitic capacitance is defined by the RX shape for the implanted resistors or the
PC shape for the polysilicon resistors.
The voltage dependence of the N+ S/D resistor junction capacitances is given by the equations:
C A0 2
C A = ----------------------------- fF/m
1 ------ V ma
-
pb
CP0
C P = --------------------------------- fF/m
V mp
1 ----------
php
where CA is the area component of capacitance, CP is the perimeter component of capacitance and V is the
bias voltage across the junction isolation. Temperature variation is handled by the standard SPICE diode
model equations. The voltage polarity defined in the model causes a decrease in parasitic capacitance for the
resistor with increasing reverse-bias (negative voltage) across the junction.
Table 146. Resistor Parasitic Capacitance Parameters

Capacitance opndres silres nwres opppcres oprppres oprrpres
Parameter Resistor Resistor Resistor Resistor Resistor Resistor
CA0 (fF/m2) 1.05 0.08381 0.93 0.08381 0.08381 0.08381
pb (Volts) 0.72 n/a 0.78 n/a n/a n/a
ma 0.35 n/a 0.34 n/a n/a n/a
CP0 (fF/m) 0.050 0.03811 0.50 0.04761 0.04761 0.04761
phb (Volts) 1.0 n/a 0.69 n/a n/a n/a
mp 0.01 n/a 0.34 n/a n/a n/a
1. Parasitic capacitance for the polysilicon resistors is a constant based on STI thickness (independent of bias and
temperature). Polysilicon resistors placed over a BFMOAT shape have a slightly lower (10%) parasitic capacitance.

Resistor Models
The parasitic capacitance for the L1 BEOL resistor is composed of both an area and a perimeter component.
These components are functions of the stack height that is determined by the number of thin-Cu layers and
the number of thick-Cu layers. Values for the capacitance parameters are defined in the following table.
Table 147. Kx BEOL Resistor Parasitic Capacitance Parameters
Capacitance Parameter 2 thin 3 thin 4 thin

-18 2
CA0(10 F/m ) 24.98 19.75 16.33
CP0(10-18F/m) 41.74 40.12 39.06
Table 148. L1 BEOL Resistor Parasitic Capacitance Parameters
Capacitance Parameter 2 thin / 1 thick 3 thin / 1 thick 2 thin / 2 thick 4 thin / 1 thick 3 thin / 2 thick
CA0 (10-18F/m2) 3.23 3.09 2.98 2.96 2.86

CP0(10-18F/m) 26.4 25.3 24.3 24.2 23.4
4.18.8 Resistor Selection
4.18.8.1 Resistor Models

The resistor models are designed as a subcircuit, or network of elements. The user must specify either the
resistance and width of the resistor, or the length and width of the resistor; the proper parasitic elements are
calculated based on these parameters. Please refer to the model files or internal web page documentation for
syntax specifics.
4.18.8.2 Resistor Selection

Resistor selection for a design is dependent on many factors. Following is a list of some design applications
which would benefit from the use of the proper resistor type:
Absolute Resistance Value
The RR polysilicon resistor has the highest sheet resistivity of all the resistor offerings, allowing for the most
compact layout for a given resistance value. The Kx BEOL resistor has the lowest sheet resistivity, which may
be most suitable for obtaining a small resistance value, though the silicided polysilicon resistor is useful as
ballast resistor because of its very low resistance, which is its intended application.
Absolute Resistance Sensitivity
For resistors of identical width and resistance value, the OP RP poly resistor has the best absolute resistance
tolerance. The L1 and Kx BEOL resistors have only a slightly higher tolerance and the L1 BEOL resistor has
the best mismatch.

Resistor Models IBM
Resistor Mis-match Sensitivity
For resistors of identical width and resistance value, the L1 BEOL resistor has the lowest mis-match. Of the
OP resistors, the N+ S/D resistor has the lowest mis-match, being only slightly higher than the L1 and Kx
BEOL resistors. For resistors of the same layout dimensions (width and length), the Kx BEOL resistor has the
lowest mis-match; and from the OP resistors, again the N+ S/D resistors has the lowest mis-match value.
Latchup Sensitivity and ESD
The P+ and RR polysilicon resistors are isolated from the bulk regions by a thick oxide dielectric. The L1
BEOL resistor, being located just above E1 in stack height or Kx BEOL resistor, being located just above the
last Mx in stack height, is even further isolated from substrate or N-well regions. Effectively, no leakages
leave or enter these resistors other than through the contacts. I/O regions that may see voltages above or
below the supply range can be particularly sensitive. These resistors can be used for current limiting during
out-of-supply I/O swings. However, the OP poly resistor must be wide enough to handle the current flowing
into or out of the I/O during normal operation. In the input receiver path, OP poly resistors are preferred over
diffusion resistors. Diffusion resistors in the input path have a parasitic diode associated with them that can
cause low CDM ESD failures. OP poly resistors are not recommended in the HBM ESD current path.
Parasitic Capacitance
The L1 BEOL resistor has the lowest total parasitic capacitance to the bulk region. The N+ S/D resistor has
the highest total parasitic capacitance. For OP polysilicon resistors of identical width and resistance value,
the RR resistor has a lower total parasitic capacitance. The L1 and polysilicon resistor parasitic capacitances
exhibit little voltage sensitivity.
Resistor Comparison Examples
The following comparison examples are designed to illustrate these basic differences (and advantages) of
the various resistor types. All of the quoted values in the examples are calculated from equations presented
throughout this section of the manual. The parasitic capacitance value for the polysilicon resistors assumes
the resistors are placed over substrate, and the L1 BEOL and Kx BEOL resistors assume the shortest stack
option, two thin and one thick metal levels (two thin metal levels).
Table 149. Resistor Comparison: Identical width, nominal resistance value and adjacent pitch.
Resistor Rnom (k) W (m) L (m) %Tol %Match C@ 0V

(fF)
opndres 1.5 8.0 163.4 13.0 0.11 1398
silres 1.5 8.0 1717 44.2 0.05 1282
nwres 1.5 8.0 21.7 19.1 0.31 178.36
opppcres 1.5 8.0 34.8 14.9 0.25 28.12
oprppres 1.5 8.0 52.0 8.0 0.56 41.29
oprrpres 1.5 8.0 7.63 19.5 0.71 7.29
kxres 1.5 8.0 210.1 8.2 0.06 60.70
l1res 1.5 8.0 204.8 8.3 0.04 16.88

NCAP and DGNCAP Models
Table 150. Resistor Comparison: Identical width, length and adjacent pitch.
Resistor Rnom (k) W (m) L (m) %Tol %Match C@ 0V

(fF)
opndres 0.141 8.0 15.0 12.9 0.37 136.80
silres 0.014 8.0 15.0 41.9 0.08 11.8
nwres 1.068 8.0 15.0 18.6 0.31 127.47
opppcres 0.654 8.0 15.0 14.8 0.39 12.93
oprppres 0.441 8.0 15.0 8.1 0.70 12.93
oprrpres 3.080 8.0 15.0 19.7 0.54 12.93
kxres 0.112 8.0 15.0 9.0 0.10 5.43
l1res 0.114 8.0 15.0 9.1 0.14 1.96
4.18.8.3 Resistor Layout Notes

Generally it is good design layout practice to limit the minimum ratio of the resistor design length to design
width to one square, particularly for narrow width resistors with widths less than a few microns.
Whenever there is a desire for a pair or group of resistors to match, they should be identical in layout. This
requirement extends to any wiring metal passing near/over/under the resistors (not necessarily connected)
and the voltage on these metal wires. Some applications may use a quadrature (also known as common-
centroid) layout to reduce the effects of process or thermal gradients near high power devices, and thereby
achieve good matching performance.
The resistor current levels are limited by heating, and should not exceed the maximum current.
4.19 NCAP and DGNCAP Models

The CMOS8RF (CMRF8SF) nMOS varactor (ncap) is a tunable capacitor using a thin oxide NFET in an
N-well with N+ source and drains shorted together. The variable capacitance is achieved by controlling the
gate to diffusion/N-well potential within the range of -0.5V to 1.0V, which takes the silicon surface under the
gate from depletion to accumulation. The capacitance per unit area can be varied from Cmax to a minimum of
approximately 20% of Cmax over this range. There are also fringe components that depend on channel width
and length and number of devices wired in parallel. At Vg-d below -0.5V, there is danger of instability
because of the need for hole generation as the device passes into inversion. The construction of the
equilibrium inversion layer takes some time (time scale on order of minutes) to accomplish. While this is
occurring, the depletion width is being reduced. Hence, the capacitance of the device is unstable during this
time. The maximum allowed voltage including power supply tolerances (Vg-d) for the ncap is +1.6 volts.
There is also a thick oxide NFET in an N-well device (dgncap). The capacitance per unit area can be varied
from Cmax to a minimum of approximately 37% of Cmax over the range -0.5V to 1.0V. The same instabilities
found for the ncap are also found for the dgncap. The maximum allowed voltage including power supply
tolerances (Vg-d) for the dgncap is +3.6 volts.

NCAP and DGNCAP Models IBM
Both the ncap and dgncap models support variable channel lengths and widths. Further, arrays of single
devices can be formed. Any other irregular capacitor designs are not supported. The model does not
calculate any inductance introduced by the metal wiring included in the ncap or dgncap. This must be
supplied by the user and is layout dependent.
NCAP and DGNCAP or PCDCAPs are supported within the T3 isolation well.
4.19.1 MOS varactor Design

The nominal value equation for the capacitance of a MOS varactor at 25C is:
C Nom ( V ) = ( C A ( V ) L W F ) + ( C L 2 L F ) + ( C W 2 W F ) + ( C F F )
where CA(V) is the capacitance per area. The expression for CA (V) is determined from first principles. The
CL, CW, and CF terms are fringe capacitance terms that are functions of the channel length (L), RX width (W),
and number of individual devices wired in parallel (F).
The parameters in this equation for the ncap are given by:
L = LDesign + dL m dL = -0.028 0.022m
W = WDesign + dW m dW = -0.045 0.04 m
F = # of individual devices
CA@ 1 V = 11.0 fF/m2 CA@ -0.5 V = 2.07 fF/m2
CL = 0.174 fF/m CW = 0.161 fF/m
CF = 0.090 fF/#
The parameters in this equation for the dgncap are given by:
L = LDesign + dL m dL = -0.02 0.034 m
W = WDesign + dW m dW = -0.045 0.04 m
F = # of individual devices
CA@ 3.3 V = 5.80 fF/m2 CA@ -0.5 V = 1.99 fF/m2
CL = 0.095 fF/m CW = 0.152 fF/m
CF = 0.129 fF/#
4.19.2 NCAP and DGNCAP Temperature Effects

Temperature variation has been included in the ncap and dgncap models. The models also include the
effects of the depletion of the polysilicon gate in accumulation mode. The change in the gate and N-well
depletion with temperature is the dominate mechanism for the change in shape of the CV curves with
temperature.
4.19.3 NCAP Gate Leakage Current

The gate leakage current has been measured for both the ncap and dgncap devices. The dgncap showed a
negligible effect, the current being less than 4 fA /m2 of gate area over the bias range -0.5 to +3.3 volts for
Vg-d. The ncap however did show an effect resulting in a DC leakage current of 7 pA /m2 at Vg-d = +1 V. The
expressions giving the gate leakage current in Amps are
where L, W, and F are as defined in Section 4.19.1. Temperature effects on the gate leakage are not included
in the model.

NCAP and DGNCAP Models
( exp ( 10.7 V g d ) 1 ) V g d > 0

16
I leak = L W F 1.5e
( exp ( 6.8 3 V g d ) 1 ) V g d < 0

16
I leak = L W F 1.5e
4.19.4 NCAP and DGNCAP Parasitic Capacitance

The parasitic backplate capacitance of either the ncap or the dgncap is composed of both an area and
perimeter component. The overall length and width of the NW shape is used to determine both the area and
perimeter of the NW-to-substrate diode.
The voltage dependence of the NW-to-substrate junction capacitances is given by the equations:
C A0 2
C A = ----------------------------- fF/m
1 ------ V ma
-
pb
CP0
C P = --------------------------------- fF/m
V mp
1 ----------
php
where CA is the area component of capacitance, CP is the perimeter component of capacitance and V is the
bias voltage across the junction isolation. Values for the parameters in these equations are found in Table
151. Temperature variation of the NW-to-substrate parasitic diode has been characterized and is included in
the model. The voltage polarity defined in the model causes a decrease in parasitic capacitance for the
mosvar with increasing reverse-bias (negative voltage) across the N-well to substrate junction.
Table 151. ncap and dgncap Parasitic Capacitance Parameters
Capacitance CA0 (fF/m2) pb (Volts) ma CP0 (fF/m) php (Volts) mp

Parameters
(dg) ncap NW-SX 0.93 0.78 0.34 0.50 0.69 0.34
4.19.5 NCAP and DGNCAP Layout Notes

The ncap or dgncap may be defined as either squares or rectangles.
The ncap and dgncap models reflect the default capacitor device layout. Strict adherence to the groundrules
and layout details provided in the device layout is recommended to achieve consistent device model and
design tool compatibility and accuracy. Of course, use of the ncap and dgncap pcells in laying out any of
these devices yield the most accurate model to hardware correlation. If designers choose to lay out these
devices themselves, it is very important to remember that the ncap and dgncap devices must have a VAR
layer surrounding them. This layer ensures proper device processing and recognition during LVS extraction.

Hyperabrupt (HA) Junction Varactor Diode IBM
The minimum length dimension for both the ncap and the dgncap is L = 0.24 m. The minimum width
dimension for both the ncap or dgncap is W = 1.0 m.
The following caution applies when using either a ncap or a dgncap with a large perimeter in a design. Large
perimeter designs have large fringe capacitances associated with them. These large fringe terms reduce the
tunability of the device. Further, due to overhead in making electrical connections to all the fingers, the
physical dimensions of large perimeter devices are larger, for a given total gate area, than for smaller
perimeter devices. On the other hand, large individual gate area devices have lower Q values than smaller
individual gate area devices, for the same total gate area.
4.20 Hyperabrupt (HA) Junction Varactor Diode

The CMOS8RF (CMRF8SF) technology offers a scalable varactor diode that is a P+/N junction diode, where
the P+ region is similar to the PFET S/D and the N region is composed of N+ subcollector and a specially
tailored N-type implant to enhance tunability. A reachthrough (NFET S/D + N-well) is used as the cathode
contact to provide a low-impedance path to the subcollector and, hence, a low diode series resistance.
Scalability is obtained by selecting both the size and number of anodes. Supported layouts consist of a single
or multiple anodes, all with wrap-around cathodes.
As input, the model requires the anode width, length and number of anodes, or the anode width, zero volt
device capacitance and number of anodes. Please review the HA varactor diode model file for syntax
specifics. The model reflects the default capacitor device layout. Strict adherence to the groundrules and
layout details provided in the device layout is recommended to achieve consistent device model and design
tool compatibility and accuracy. Of course, use of the HA varactor pcell in laying out any HA varactors yields
the most accurate model to hardware correlation. Use of other device layout/geometries is not supported.
Should you require modeling support for other diode geometries, please contact your IBM Product Engineer.
HA varactor is not supported within the T3 isolation well. See Rule T3W14a (JD covers this entire device)
4.20.1 HA Varactor Diode Device Parameters

The nominal value equation for the capacitance of a HA varactor at 25C is:
C Nom ( V ) = ( C A ( V ) L W N ) + ( C P ( V ) 2N ( W + L ) )
where CA(V) is the capacitance per area and CP(V) the capacitance per length.
The parameters in these nominal capacitance equations are given by:

L = LDesign + dL m dL = -0.1 0.04 m
W = WDesign + dW m dW = -0.1 0.04 m
N = # of anodes
CA @ 0 V = 2.40 fF/m2 CP @ 0 V = 0.19 fF/m
The model employs a physics-based calculation to determine the capacitance using VerilogA. The
temperature dependence of the capacitance is also included in the model and comes through the
temperature variation in the built-in potential across the p-n junction.

Differential Varactors
4.20.2 HA Varactor Parasitic Capacitance

The parasitic backplate capacitance of the HA varactor is composed of both an area and perimeter
component. The overall length and width of the subcollector shape is used to determine both the area and
perimeter of the cathode-to-substrate diode. The voltage dependences of the cathode-to-substrate junction
capacitances are given by the standard junction equations, c.f. section 4.19.4, NCAP and DGNCAP
Parasitic Capacitance on page 391. Values for the parameters in these equations are found in the Table
152.
Table 152. HA Varactor Parasitic Junction Capacitance Parameters
Capacitance / Temperature Cathode-SX Cathode-SX
Parameters Parasitic Temperature
Diode Coefficients
CAO (fF/m2) / CTA (1/oC) 0.27 0.15 1.8 x 10-3
pb (Volts) / tpb (mV/oC) 0.75 2.9
ma 0.45 n/a
CPO (fF/m) / CTP (1/oC) 1.45 0.20 9 x 10-4
php (Volts) / tphp (mV/oC) 0.70 1.8
mp 0.40 n/a
4.20.3 HA Varactor Leakage Current

The leakage current in the HA varactor model is derived from a voltage controlled current source, in which the
controlling voltage is that across the P+/N junction. The current is divided into area (IAlk) and perimeter (IPlk)
components so I leak = I Alk ( V ) W L N + I Plk ( V ) 2N ( W + L ) , where W, L, and N are as previously
defined for the junction capacitance. The IAlk(V) and IPlk(V) are functions of V given by
fA
I Alk = 0.06 sinh ( 1.5V ) -----------2
m
fA
I Plk = 1.8 sinh ( 0.95V ) --------
m
4.21 Differential Varactors

A thin oxide nMOS varactor device (diffncap) and a hyperabrupt junction varactor device (diffhavar) that are
specifically designed as differential devices for use in VCO circuits are available. The diffncap device consists
of two identical sets of polysilicon gates that are interdigitated and share the same N-well. The diffhavar
device consists of two sets of anodes that are interdigitated and share the same subcollector. Since the
signal travels into the device through one set of gates/anodes and exits the device through the other set,
there is no need for well contacts between the gates/anodes. This allows for an increased Q-factor compared
to the standard device. For single-ended operation however, the standard device should be used as the Q will
be better due to the close proximity of the well contacts to the gates/anodes in the standard device.
While the capacitance per area for the differential devices is exactly that of the corresponding standard
devices, being calculated by the same Verilog-A modules, there are a few notable differences between the
standard models and the differential models. First and foremost, the diffncap/diffhavar model has four nodes:
one for each set of gates/anodes, one for biasing the common subcollector, and one for the usual substrate

MIM Capacitor Models IBM
node. Second, the fringe capacitance changes slightly and a parasitic capacitance coupling between the two
sets of gates/anodes is introduced. Lastly, the manner in which the various resistances within the model are
distributed and combined are tailored to the specific layout of the diffncap/diffhavar; so use of the
diffncap/diffhavar pcell in laying out any differential nMOS/HA varactors yields the most accurate model to
hardware correlation.
As always, please see to the Model Reference Guide for model-to-hardware correlation plots.
4.22 MIM Capacitor Models
4.22.1 Introduction:
This technology has two types of MIM capacitors available with the MA back end of the line offering (where
the MA BEOL option is commonly referred to also as the Dual Metal or DM option), the single and dual MIM.
MIMCAP, DUALMIMCAP, are not restricted from being placed over a T3 isolation well.
4.22.2 MIM Capacitors

The single MIM capacitor (mimcap) is built between the E1 and LY levels. QY is the top plate of the capacitor.
The dual MIM (dualmimcap) built is between the E1 and LY levels. HY is the top plate, QY is the middle plate,
and LY is the bottom plate. The top and bottom plates are electrically connected.
The models support variable dimensions for both width and length. Allowable capacitor shapes include both
squares and rectangles. Note that any other irregular capacitor designs are not supported.
4.22.2.1 Capacitor Design Specifications

The specifications in Table 153 may be used as a guide in applications.
Table 153. Capacitor Specifications
Specification Mimcap Dualmimcap
Area Capacitance (0 V, 25 C) 2.05 fF/m2 4.10 fF/m2
Perimeter Capacitance 0.157 fF/m 0.309 fF/m
Temperature dependence 15.3 ppm / C 15.3 ppm / C
The nominal value equation for the capacitance of the mimcap at 25C and 0 volts is:
C N = (C A L W ) + (C P 2 (L + W )) fF
with CA and Cp as listed in Table 153, on page 394, and other terms in the equation given by:
L = Design Length (QY) in m

W = Design Width (QY) in m

MIM Capacitor Models
The nominal value equation for the capacitance of the dualmimcap at 25C and 0 volts is:
C N = C A ( 2 W L + 11.48 W + 4 L + 45.92 ) + C P 2 ( W + L + 15.48 )
with CA = 2.05 fF/m2, Cp = 0.309 fF/m and other terms in the equation given by:
L = Design Length (HY) in m

W = Design Width (HY) in m
4.22.2.2 Voltage Coefficient of Capacitance

The voltage coefficient ratio of the mimcap is governed by the equation:
5 5 2
VCR = 1.0 + ( 3.90 10 V ) + ( 2.72 10 V )
where V is the voltage across the capacitor, bottom plate positive w.r.t. top plate.
The voltage coefficient ratio of the dualmimcap is governed by the equation:

6 5 2
VCR = 1.0 + ( 7.57 10 V ) + ( 2.80 10 V )
where V is the voltage across the capacitor, bottom and top plates positive w.r.t. QY plate.
4.22.2.3 Capacitor Tolerance

The capacitor tolerances are defined based on measured variation of both geometric layout parameters and
process (sheet resistivities, unit capacitances) parameters. In most cases, the dominant variation of the
capacitance is due to only a few of the process parameters defining a capacitors value.
Table 154. MIM cap Tolerance Parameters
Capacitor Type TCA (fF/m2) TCP (fF/m)

mimcap 0.205 0.08
dualmimcap 0.410 0.15
Note: Tolerance values represent 3-sigma process capability.
4.22.2.4 Capacitor Matching

The 3-sigma percentage matching for identical MIM capacitors with the same orientation such that W is the
nearest edge dimension and at the same voltage is given by the following expression.

MIM Capacitor Models IBM
2 2 2
MA MW ML
M = -------------- + ------------- + -----------
W L W 2
L
2
Table 155. Mimcap Capacitor Mis-Match:
mimcap dualmimcap
Matching Parameter Capacitor Capacitor
MA 4.0 4.0
MW 1.0 0.5
ML 0.0 0.1
It should be noted that interconnect parasitic capacitance may have an effect at these matching levels. When
matching ratioed capacitors, the capacitors must be built by paralleling identical unit capacitors.
4.22.2.5 Capacitor Parasitics

Parasitic capacitances exist between MIM bottom plates and the substrate. The values in Table 156 assume
either an N-well or a plain substrate ground plane with auto-generated PC, RX, and metal level fill shapes
present. The unit area and perimeter capacitance values for the MIM capacitors are shown in Table 156.
Table 156. Capacitor Bottom Plate Parasitics for MA / OLBEOL option (mimcap and dualmimcap)
Capacitor Layout Area Parasitic Capacitance CA (fF/m2)

6LM 7LM 7LM 8LM 8LM
(MQ, no MG) (MQ, no MG) (MQ,MG) (MQ, MG) (MQ, no MG)
Bottom plate 0.0123 0.0109 0.0099 0.0090 0.0098
Capacitor Layout Perimeter Parasitic Capacitance CP (fF/m)
Bottom plate 0.0321 0.0317 0.0315 0.0312 0.0314
Note: This internal parasitic capacitance is set to a negligible value (0.01fF) whenever a netlist is generated
using the layout extraction tool or can be manually turned off by setting the model parameter est=0 in the
netlist. This allows for a more accurate calculation of the bottom plate parasitic capacitance to support the
option of placing other devices underneath the MIM. Simulations using a netlist generated from the schematic
with the default parameter settings (est=1) will underestimate this bottom plate parasitic capacitance for the
case where other devices will be placed underneath a MIM.
4.22.3 MIM Capacitor Application Notes

The capacitor models are quite robust as the parasitic resistances of back, mid and top-plates of the devices
are modeled, as is the parasitic capacitance to substrate. The model topology consists of a distributed
element network, which enhances the frequency response.

HiK and Nitride Capacitors for OL BEOL
The user must supply as parameters either length and capacitance, or length and width of the capacitor. The
associated device parasitic elements (resistances, capacitance to substrate) are then calculated based on
these parameters. Please consult the model file or internal web page documentation for other syntax
specifics.
4.22.3.1 Design Layout Reminder

All capacitor models reflect their default device set layout. Strict adherence to the groundrules and layout
details provided in the device set layout is recommended to ensure full and consistent device model and
design tool compatibility and accuracy.
4.22.3.2 Capacitor Layout Notes

The following cautions apply when using the MIM capacitor in a design:
1. See the text of the NOTE to Rule QCap4a concerning special wiring considerations for MIM devices. The
bottom plate must be wired up to E1 for the mimcap and dualmimcap before being wired into the circuit.
2. If a MIM plate is connected to a terminal pad then that plate must also be connected to silicon.
3. The MIM is very susceptible to ESD. If the MIM is connected to a terminal pad ESD protection should be
used. If this is not possible then handling procedures must be followed to prevent electro-static discharge
damage to the MIM. The floating metal check requires at least a minimum diode for minimal protection
during test and assembly.
4. Maximum area per HY and QY plate is 100,000 um2.
5. Maximum total area per chip for (QY+HY) plates is 2,000,000 um2.
4.23 HiK and Nitride Capacitors for OL BEOL

4.23.1 Introduction
This technology has a single HiK-dielectric or single nitride or dual nitride MIM capacitor available for the OL
back end. The HiK MIM capacitor (mim) or nitride MIM capacitor (mimnit) is built above the final double thick
metal level, either MQ or MG. The wiring to the MIM is found on the top metal, OL. The top plate of the single
Hi-K and nitride capacitor is called HT and the bottom plate is called QT. The top plate of the dual nitride
capacitor is called KT, the middle plate is called HT and the bottom plate is called QT. The models support
variable dimensions for both width and length. Allowable capacitor shapes include both squares and
rectangles. Note that any other irregular capacitor designs are not supported.
The single Hi-K MIM (mim) is not restricted from being placed over a T3 isolation well. The single Nitride MIM
(mimnit) is not restricted from being placed over a T3 isolation well. The dual nitride mim (dualmimnit) is not
restricted from being placed over a T3 isolation well.

HiK and Nitride Capacitors for OL BEOL IBM
4.23.2 Capacitor Design Specifications
The specifications in Table 157 may be used as a guide in applications. The capacitor tolerances are defined
based on measured variation of both geometric layout parameters and process (sheet resistivities, unit
capacitances) parameters. In most cases, the dominant variation of the capacitance is due to only a few of
the process parameters defining a capacitors value.
Table 157. Capacitor Specifications
Specification MIM MIMNIT DUALMIMNIT
Area Capacitance (0 V, 25 C) 4.1 0.41 fF/m2 2.05 0.205 fF/m
2
4.1 0.41 fF/m2
Perimeter Capacitance 0.4 0.2 fF/m 0.12 0.061 fF/m 0.44 0.22 fF/m
Temperature dependence 193 ppm / C 19 ppm / C 21 ppm / C
Temperature dependence 0.2 ppm / C2 N/A -0.03 ppm / C2
The nominal value equation for the capacitance of the MIM at 25C and 0 volts is:
C N = (C A L W ) + (C P 2 (L + W )) fF
with CA=2.05 fF/m2 and Cp as listed in Table 157, and other terms in the equation given by:
L = LDesign + dL m dL = -0.07 0.2 m

W = WDesign + dW m dW = -0.07 0.2 m
where LDesign and WDesign are the designed length and width, respectively, of the HT plate.
The nominal value equation for the capacitance of the MIMNIT at 25C and 0 volts is:
C N = (C A L W ) + (C P 2 (L + W )) fF
The nominal value equation for the capacitance of the dualMIMNIT at 25C and 0 volts is:
C N = C A ( 2 W L + 2.0 W + 5.2 L + 10.4 ) + C P 2 ( W + L + 7.2 )
with CA=2.05 fF/m2 and Cp as listed in Table 157, and other terms in the equation given by:
L = LDesign + dL m dL = 0.0 0.3 m

W = WDesign + dW m dW = 0.0 0.3 m
where LDesign and WDesign are the designed length and width, respectively, of the HT plate.
4.23.3 Voltage Coefficient of Capacitance

The voltage coefficient ratio for the HiK MIM is governed by the equation:
6 6 2
VCR = 1.0 ( 160 10 V ) + ( 230 10 V )

HiK and Nitride Capacitors for OL BEOL
where V is the voltage across the capacitor, top plate potential with respect to the bottom plate potential.
The voltage coefficient ratio for the single Nitride MIM is governed by the equation:
6 6 2
VCR = 1.0 + ( 66 10 V ) + ( 12 10 V )
where V is the voltage across the capacitor, top plate potential with respect to the bottom plate potential.
The voltage coefficient ratio for the dual Nitride MIM is governed by the equation:
6 6 2
VCR = 1.0 ( 6 10 V ) + ( 12 10 V )
where V is the voltage across the capacitor, middle plate potential with respect to the top / bottom plate
potential.
4.23.4 Capacitor Matching

The 3-sigma percentage matching for identical MIM capacitors with the same orientation and at the same
voltage is defined by two separate distributions. It should be noted that interconnect parasitic capacitance
may have an effect at these matching levels. When matching ratioed capacitors, the capacitors must be built
by paralleling identical unit capacitors.
HiK MIM:
55 0 0
M = -------------- + -----2- + --------2- %
W L L W
Single Nitride MIM:
16 0.25 2.25
M = -------------- + ----------
- + ----------
- %
2 2
W L L W
Dual Nitride MIM:
4 0 2.25
M = -------------- + -----2- + ----------
- %
2
W L L W
4.23.5 Capacitor Parasitics

Parasitic capacitances exist between MIM bottom plate (QT) and the substrate. This capacitance has an area
term and a perimeter term. The values in Table 158 assume either an N-well or a plain substrate ground
plane with auto-generated PC, RX, and metal level fill shapes present.

HiK and Nitride Capacitors for OL BEOL IBM
Table 158. Capacitor Bottom Plate Parasitics
Capacitance Thin and Thick Metal Option

Top Thin Metal M2 M3 M4 M5 M4
Top Thick Metal MQ MQ MQ MQ MG
CA (fF/m2) .0162 .0138 .0120 .0106 .0098
CP (fF/m) .0349 .0328 .0312 .0300 .0231
Note: This internal parasitic capacitance is set to a negligible value (0.01fF) whenever a netlist is generated
using the layout extraction tool or can be manually turned off by setting the model parameter est=0 in the
netlist. This allows for a more accurate calculation of the bottom plate parasitic capacitance to support the
option of placing other devices underneath the MIM. Simulations using a netlist generated from the schematic
with the default parameter settings (est=1) will underestimate this bottom plate parasitic capacitance for the
case where other devices will be placed underneath a MIM.
4.23.6 MIM Capacitor Application Notes

The capacitor models are quite robust as the parasitic resistances of the top and bottom plates are modeled
as is the parasitic capacitance to substrate. The model topology consists of a distributed element network,
which enhances the frequency response.
The user must supply as parameters either length and capacitance, or length and width of the capacitor. The
associated device parasitic elements (resistances, capacitance to substrate) are then calculated based on
these parameters. Please consult the model file or internal web page documentation for other syntax
specifics.
All capacitor models reflect their default device set layout. Strict adherence to the groundrules and layout
4.23.6.1 Capacitor Layout Notes

The following cautions apply when using the MIM capacitor in a design:
1. All wiring to MIM is done on top metal, OL. The only OL allowed over the MIM must be electrically con-
nected to the MIM. Maximum via density by area is 5%.
2. If a MIM plate is connected to a terminal pad then that plate must also be connected to silicon.
3. The MIM is very susceptible to ESD. If the MIM is connected to a terminal pad ESD protection should be
used. If this is not possible then handling procedures must be followed to prevent electro-static discharge
damage to the MIM. The floating metal check requires at least a minimum diode for minimal protection
during test and assembly.
4. Maximum width for QT plate is 90 m and the maximum length is 1000 m.
5. Maximum area per QT plate is 100,000 um2.

6. Maximum total area per chip for HT plate is 1,000,000 um2

Capacitors for AM BEOL
4.24 Capacitors for AM BEOL

4.24.1 Introduction
Support for MIM capacitors for the AM BEOL has been removed.
4.25 VNCAP - Vertical Natural BEOL Capacitor

This technology has a vertical natural capacitor (VNCAP) which is composed of thin metal M1 through M4
wires and V1 through V3 vias in the MA BEOL, and M1 through M6 and V1 through V5 in the LM BEOL. All
metal fingers are 0.28 m wide with a 0.20 m space.The wire and via spacing has been fixed to achieve
both good capacitance density and high yield.
The VNCAP capacitor can be constructed of any number of thin metal levels with the requirement that a
capacitor of more than one level must consist of consecutive levels (e.g., M2 through M4, or M1 through M3).
The model supports variable dimensions for both width and length. The width of the capacitor determines the
number of metal walls (fingers) composed of multiple metal levels and their connecting vias, while the length
of the capacitor determines the length of the metal wires that form the metal walls.Allowable capacitor shapes
include both squares and rectangles. Note that any other irregular capacitor designs are not supported.
VNCAP is not restricted from being placed over a T3 isolation well.
4.25.1 Capacitor Design Specifications

The specifications in Table 159 may be used as a guide in applications. The capacitance density numbers in
Table 159 are extracted from analysis of large structures composed of many long fingers, the size of which
smooths out the granularity inherent in a capacitor composed of a discrete number of interdigitated metal
wires. The values listed are applicable for the allowed thin metal levels of both the MA and LM BEOLs.
Table 159. VNCAP Capacitance Density Specifications

Bottom Metal Level Top Metal Level Capacitance Density to Capacitance Density (CA) Total Capacitor
Substrate (Csx) (over STI) Tolerance (3)
1 1 0.032 fF/m2 0.166 fF/m2 45%
1 2 0.032 fF/m2 0.393 fF/m2 31%
1 3 0.032 fF/m2 0.620 fF/m2 25%
1 4 0.032 fF/m2 0.848 fF/m2 22%
1 5 0.032 fF/m2 1.075 fF/m2 20%
1 6 0.032 fF/m2 1.302 fF/m2 18%
2 2 0.018 fF/m2 0.201 fF/m2 49%
2 3 0.018 fF/m2 0.428 fF/m2 33%
2 4 0.018 fF/m2 0.655 fF/m2 26%
2 5 0.018 fF/m2 0.883 fF/m2 22%
2 6 0.018 fF/m2 1.110 fF/m2 20%

VNCAP - Vertical Natural BEOL Capacitor IBM
3 3 0.013 fF/m2 0.201fF/m2 50%
2 2
3 4 0.013 fF/m 0.428fF/m 32%
2 2
3 5 0.013 fF/m 0.655 fF/m 26%
2 2
3 6 0.013 fF/m 0.883fF/m 22%
2 2
4 4 0.010 fF/m 0.201 fF/m 48%
2 2
4 5 0.010 fF/m 0.428 fF/m 32%
2 2
4 6 0.010 fF/m 0.655 fF/m 26%
2 2
5 5 0.008 fF/m 0.201 fF/m 48%
2 2
5 6 0.008 fF/m 0.428 fF/m 32%
6 6 0.007 fF/m2 0.201 fF/m2 50%
The equation describing the VNCAP capacitance is as follows:
C VNCAP = C A ( W ( L 6.32u ) )
Where:
L = Design Length in m
W = Design Width in m
4.25.2 Capacitor Tolerance

The capacitor tolerances are calculated based on expected variation of M1 through M6 wire thicknesses and
spacing. The 3- tolerance of the VNCAP capacitance, which varies with the number of metal levels utilized,
is specified in Table 159.
4.25.3 Temperature Coefficient of Capacitance

The temperature coefficient of capacitance of the vncap capacitor is governed by the equation:
5
TCC = 1.0 + ( 1.3 10 ( T T 25C ) )
where T is the simulation temperature and T25C is room temperature (25 C). The temperature effect is linear
for all metal levels.
4.25.4 VNCAP Capacitor Matching

The 3-sigma percentage matching for identical VNCAP capacitors with the same orientation and at the same
voltage is defined by a single distribution. Measurement system accuracy for matching has an apparent
measurement floor of approximately 0.200%. Therefore matching measurement values for large area,
multiple level vncaps appear to exhibit the same equivalent matching. For this reason, model calculations for

VNCAP - Vertical Natural BEOL Capacitor
multiple level vncaps are theoretically based on matching trends for smaller size devices where measured
matching values are greater than 0.200%. Alternate measurement structures/techniques will be evaluated on
future hardware and the results will be incorporated into the next available Design Kit release.For model
matching coefficients please see the Model Reference Guide.
Examples of VNCAP capacitor mis-match are included in Table 160:

Table 160. VNCAP Capacitor Mis-Match:
Model Mis-Match
M1-M2 or M2-M3 or
Device Size Center to Center
M1 only M3-M4 or ... M1-M4
(W x L) Spacing
10 x20 200 14.27 4.14 .56
40 x 40 200 1.48 .61 .29
100 x 100 200 .43 .32 .26
Matching structures for small geometry devices (L < 10 m) were not available for measurement and, as
such, model matching predictions for these small geometries can not be guaranteed.
4.25.5 VNCAP Capacitor Parasitics

Parasitic capacitances exist between VNCAP bottom metal level wires and the substrate, wiring and / or
surrounding devices. An estimate of the parasitic capacitance to substrate is provided in Table 159. These
values assume the presence of uniform RX and PC fill shapes below the VNCAP. For an accurate calculation
of the parasitic capacitance when devices and / or wiring is located below the VNCAP, a parasitic extraction
tool must be used.
4.25.6 VNCAP Capacitor Application Notes

All capacitor models reflect their default device set layout. Strict adherence to the ground rules and layout
The performance of VNCAP capacitor is expected to show a strong layout dependence. Table 159 indicates
that the more metal levels on which the capacitor is based, the less its variability is expected to be.
Simulations have shown VNCAP capacitors laid out with a length to width ratio close to 1 provide the highest
Q for a given value of capacitance.
Model-to-hardware correlation verification has not been conducted on vncap devices where W is less than 10
m and L is less than 10 m.
For additional information, please see Table 93, Vertical Natural Capacitor Layout Rules, on page 263.
4.25.7 VNCAP Reliability

The maximum applied voltage is 3.6V, including the 10% supply tolerance.

Forward-Biased Diode Device Models IBM
The maximum total capacitor area per metal level must not exceed 1 x 106 m2 - the sum of the top-down
areas of all the VNCAP capacitors on that level. For additional information, see Rule VNCM90 in Table 93,
Vertical Natural Capacitor Layout Rules, on page 263.
4.26 Forward-Biased Diode Device Models

The general use of forward-biased diodes as circuit elements is not supported. Forward bias of diffusions will
produce current at adjacent diffusions that can affect circuit performance, degrade device characteristics, and
cause latchup. It is to be avoided wherever possible by careful circuit design.
Customers are required to request a waiver from the IBM Technical Representative for each specific design
application where a forward-biased diode is used as a active circuit element. However, one application,
bandgap reference circuits using the P-diffusion in a grounded (tied to substrate) N-well as a diode, is being
allowed within specific restrictions. Supported geometries include squares and rectangles; other shapes,
such as L-shapes, are not supported. The designer is allowed to select lengths and (limited) widths and
number of fingers to optimize the physical size of the diode while remaining within the current density limits.
Ideally, the P+/N-well diode pcell (dipdnw or divpnp) should be used in order to ensure a fully consistent
device model. Both of these models simulate the same P+/NW junction. The dipdnw model is a simple
two-terminal model (diode model) in which the N-well and the substrate ring surrounding the device are
shorted together. The divpnp model is a three terminal model (bjt model) that has separate N-well and
substrate ring nodes. It is strongly recommended that these nodes be shorted together to prevent accidental
forward biasing of the NW/SX junction. Should you require modelling support for geometries other than those
described here, please contact your IBM Technical Representative.
Forward-Bias Diode (DI) is supported within T3 isolation well.
The allowable width and length dimensions are given in Table 161.
Table 161. Groundrule Layout Dimensions for P+ Nwell Diodes
Layout Dimensions Width (Min) Width (Max) Length (Min)

P+ Nwell Diode 1.0 2.0 2.0
The DC model described here becomes a poor predictor of the actual current-voltage relationship for current
densities above 50 /m2. The P-diffusion in a grounded N-well diode-current can be modeled as an ideal
diode with a series resistor, as shown below.
+ Vj Rs
The current flowing through the device is given by the expression
qV j
I = I o exp --------------- 1
N f kT

Forward-Biased Diode Device Models
where Vj is the voltage drop across the junction, Io the saturation current and Nf the ideality factor. For small
current values, the voltage drop across the resistor can be neglected resulting in a purely exponential I-V
dependence. In this case, Vj can be replaced with VA, the voltage applied to the anode. When the exponential
I-V relation is critical to the application, current densities should be maintained above 500 pA/m2 and below
1 A/m2.
The saturation current Io is expressed as a function of the area and perimeter of the anode
I o = J Area + K Perimeter
At higher current levels, the series resistance Rs cannot be ignored. The dominate terms for this resistance
are the resistance through the N-well from the anode to the cathode contact, and particularly the resistance
up through the cathode contact itself.
Extracted values at 25 oC for the various parameters used in these expressions for the forward-bias DC
operation of the P+ Nwell diode are given in Table 162.
Table 162. Forward-Bias Parameters for dipdnw diode
DC Parameter Values (@ 25 oC) Nf J (10-21 A/m2) K (10-21 A/m)

P+ Nwell Diode 1.0025 90. 50 % 27. 50 %
The preceding model parameters are valid at Tnom = 25 C. The most dominant temperature effect is an
increase in the saturation current Io. The theoretical temperature dependence of Io is given by the expression
E gap ( T nom ) E gap ( T )

ln [ I o ( T ) ] ln [ I o ( T nom ) ] = --------------------------------- ------------------------ + 3 ln ------------------------------
T + 273
V thrm ( T nom ) V thrm ( T ) T nom + 273
where Egap is the band gap energy and Vthrm is the usual kT
5
V thrm = 8.617 10 ( T + 273 ) eV.
The band gap energy has its own temperature dependence given by the expression
eg ( T + 273 ) 2
E gap ( T ) = E gap ( 0K ) ----------------------------------------- eV
eg + ( T + 273 )
where eg and eg are parameters taken from the literature. The Egap(0K) is the value of the band gap energy
at absolute zero, and has been adjusted in order to obtain a good fit to the measured data for the temperature
dependence of Io. Values for the parameters in the expression for the temperature dependence of the band
gap energy are given in Table 163.
Table 163. Parameters for the temperature of the band gap energy
Temperature Dependence Parameters Egap(0K) (eV) eg (10-4 eV/K) eg (K)

1.12 4.73 636

Schottky Barrier Diode IBM
The percentage matching for identical, adjacent diodes with the same orientation, at the same temperature, is
given by the equation below. Care should be taken to adhere to symmetrical layout of matched diodes.
Considerations should not only include length and width, but metal coverage and symmetry of generated
levels, i.e. special care should be given to assure that any block mask levels being generated are present on
both matched diodes.
The diode matching is handled through the saturation current and the matching coefficient is given by the
equation:
2
6.5
M = ----------------------- %
W LF
where L and W are the drawn length and width of the device in m, respectively, and F is the number of
fingers.
4.27 Schottky Barrier Diode

The CMOS8RF (CMRF8SF) technology offers a scalable Schottky Barrier Diode (sbd) over the NS implant
with a guard-ring. The device parameter specifications are given in Table 164. Scalability is obtained by
selecting both the size (l and W) and number of anodes (nf). Supported layouts consist of single and multiple
anodes with each anode surrounded by a wrap-around cathode to further reduce parasitic series resistance.
The SBD anode is made up of a silicide/silicon area with wrap-around p+ guardring. All sections of the anode
are silicided. Contact to the anode over the p+ guardring ensures that the interface that forms the SBD is not
disrupted. A reachthrough level is used at the cathode contact to provide a low-impedance path to the
subcollector and, hence, a low diode series resistance.
Please review the SBD diode model files for syntax specifics. By default, all other device dimensions and
spacings are as defined in the library pcell layout. Use of other device layout/geometries is not supported.
Should you require modeling support for other diode geometries, please contact your IBM Product Engineer.
Schottky Barrier Diode is not supported within T3 isolation well.
4.27.1 Schottky Barrier Diode Device Parameters

Table 164 contains standard device specs which represent 3-sigma process capability targets for a diode
with a single anode of area 5.0 m x 5.0 m, 25C:
Table 164. SBD Device Specifications
Parameters Units Min Nom Max

Forward Voltage @ 10uA V .279 0.328 .377
Leakage @ -1V nA 0.1 10
VBreakdown @ -10 A V 5 13.5 22
Note: Temperature = 25C

Schottky Barrier Diode
The minimum allowable width and length dimensions are given in Table 165. The various parameters that are
found within the model are given in Table 166.
Table 165. Groundrule Layout Dimensions for SBDI
Layout Dimensions Width (Min) Length (Min)

SBD minimum anode dimensions 2.0 2.0
Table 166. Electrical Parameters for Schottky Barrier Diode (SBD):
Parameter Description SBD
Min Nominal Max. Unit
Modelling Parameters
sbdia Pure Area part of saturation current (ISBDIS) 0.218 2.453 27.58 pA / m2
(Adjusted to fit Vfb spec)
sbdnf Pure Area part of saturation current (ISBDIS) 0.008 0.09 1.012 pA / m2
(Adjusted to fit Vfb spec)
XTI Schottky Saturation current temperature exponent 2.0

nvepi Vertical resistance through anode 1000 Ohm-m2
n_p Guard Ring Ideality 1.006 #
js_p Guard Ring Saturation Current (area) 450 10-21 A/m2
jsw_p Guard Ring Saturation Current (perimeter) 135 10-21 A/m
XTIP Guard Ring Saturation current temperature expo- 3.0
nent
Ilk Leakage Coeff. 0.36 63 11080 mA / m2
Leakage Voltage Coeff 0.4 V-1
nnsbdcj area junction capacitance 0.58 0.77 0.96 fF/m2
m area grading coefficient 0.27 #
vj area junction potential 0.26 V
nnsbdcjp sidewall (guard ring) junction capacitance 0.38 0.63 0.88 fF/m
mjsw sidewall (guard ring) grading coefficient 0.40 #
vjsw sidewall (guard ring) junction potential 0.89 V
cta area capacitance temperature coeff. 0.0008 #/K

Schottky Barrier Diode IBM
Table 166. Electrical Parameters for Schottky Barrier Diode (SBD):
Parameter Description SBD
Min Nominal Max. Unit
pta area junction potential temperature coeff -0.66 mV/K
ctp sidewall (guard ring) capacitance temperature 0.0007 #/K

coeff
ptp sidewall (gurard ring) junction potential tempera- 2.0 mV/K

ture coeff
delbn Anode bias -0.447 -0.497 -0.547 m

delrx RX line width bias -0.005 -0.045 -0.085 m
4.27.2 SBD Model Details
The SBD diode-current can be modeled as an ideal diode with a series resistor, as shown below.
+ Vj Rs
The current flowing through the device is given by the expression
qV j
I = I SBDIS exp ----------- 1
nkT
where Vj is the voltage drop across the junction, ISBDIS the schottky barrier saturation current and n the
ideality factor.
12
1.0665 10
n = ---------------------------------------
0.0077
Area
For small current values, the voltage drop across the resistor can be neglected resulting in a purely
exponential I-V dependence. In this case, Vj can be replaced with VA, the voltage applied to the anode.
The Schottky barrier saturation current ISBDIS (Amp) is expressed as a function of the area (m2) of the anode
I SBDIS = Area [ I sbdia NUMF I sbdnf ]

Schottky Barrier Diode
or
q B
I SBDIS = Area 1.416 10 T exp -----------
6 2
kT
with
I sbdia NUMF I sbdnf
B = K T ln --------------------------------------------------------------
1.416 10 T
6 2

where the factor 1.416x106 is from various constants, e.g.,Plancks constant, the effective electron mass, and
others. The saturation current (ISBDIS) has a pure area dependency as well as number of finger (NUMF)
correlation with NUMF capped at 10. The latter dependency is due to stress effects. At higher current levels,
the series resistance Rs cannot be ignored. The dominate terms for this resistance can be expressed in terms
of the resistance through the cathode and the resistance up through the cathode contact.
The model parameters given in the tables are valid at Tnom = 25 C. The most dominant temperature effect is
an increase in the saturation current ISBDIS. The theoretical temperature dependence of ISBDIS is given by the
expression
B ( T nom ) B ( T )
ln [ I SBDIS ( T ) ] ln [ I SBDIS ( T nom ) ] = --------------------------------- ------------------------ + 2 ln ------------------------------
T + 273
V thrm ( T nom ) V thrm ( T ) T nom + 273
where B is the Schottky barrier height. The temperature dependence of B follows that of the band gap
energy given in section 4.27 on page 406; similarly, the definition of Vthrm is given in this same section.
The p+ guardring diode portion of the SBD diode-current does not contribute any significant amount to the
forward bias current.
The leakage current in the Schottky diode device is controlled by a voltage controlled current source. The
controlling voltage is that which is across the metal-silicon interface. The current is defined using the area for
the SBD and follows the expression, including temperature effects,
I leak = I lk exp -------------- sinh ( 0.4V )
6863
T ( K )
where the value for the leakage coefficient parameter is also given in Table 166.
The junction capacitance results from the depletion region at the metal-silicon interface. This capacitance
varies in inverse proportion to the width of the depletion region, which is itself a function of the applied voltage
VA. The junction capacitance of the device scales with the anode area and the perimeter of the guard ring.
C = C A Area anode + C p Perimeter guardring
The voltage (reverse bias is negative voltage) dependence of CA and CP is given by (i = A or P)

C io
C i = ------------------------------
V A mi
1 --------
-
V bi

Substrate Contact IBM
The parameters used in these equations for the capacitance are given in Table 167.
Table 167. Capacitance Parameters for SBDI Diode
Capacitance Parameter Values Cio Vbi mi

Area Capacitance 0.774 0.19 (fF/m2) 0.258 0.271
Perimeter Capacitance 0.726 0.25 (fF/m) 0.886 0.404
The temperature dependence of the capacitance follows the usual standard diode expressions and the
associated parameters are also found in Table 166.
The breakdown voltage is another diode characteristic that is related to reverse bias operation of the diode.
The breakdown voltage, measured at 10 A, is nominally 13.5volts for the SBD (See Table 166.)
The parasitic capacitance associated with the cathode to SX junction is nearly identical to that found in the
HA junction varactor. The only difference is that the BB moat surrounding the SBD is wider than that
surrounding the HA varactor. As such, the perimeter component is reduced by a factor of one-half. For details
on the parameter values for this parasitic junction please refer to section 4.18.1 on page 379.
Lastly, we have also measured the mismatch between adjacent devices. The mismatch is measured in terms
of a mismatch in the forward voltage as given in Table 164. The matching is for identical, adjacent diodes with
the same orientation, at the same temperature. Care should be taken to adhere to symmetrical layout of
matched diodes. Considerations should not only include length and width, but metal coverage and symmetry
of generated levels, i.e., special care should be given to assure that any block mask levels being generated
are present on both matched devices.
The device matching is handled through modification to the device barrier height. The barrier height is
modified by the equation given below
-----------------
0.0047
-
A an
Bfinal = Binitial + ----------------------------
par
Where Aan is the total drawn anode area in m2, does not include delbn, and par is the number of parallel
devices.
4.28 Substrate Contact

The resistance associated with a simple substrate contact is modelled in the subc model. The resistance
varies as the inverse of the contact area. Temperature effects are also included in this model. The resistance
included in the model, and other models that include a substrate contact, e.g. the esdndsx model, is 750
Ohms-m2. This value was extracted from a series of monitors consisting of two closely placed substrate
contacts (< 1 m separation) of varying dimensions.
There is also an in-line test monitor for substrate contact resistance, and the nominal value reported here is
2kOhm-m2. However, the substrate contact in this in-line test monitor is surrounded by an Nwell ring.
Hence, the current through the contact has to come up from under the Nwell. In contrast, the current in
monitor used to extract the value employed in the models only needs to flow under the shallow trench

Substrate Contact
isolation (STI). So, the current is closer to the surface. This difference in the vertical distance through which
the current flows in the substrate contact accounts for the value difference between the model extracted
value and the in-line test results.

Conducting Film Thickness IBM
4.29 Conducting Film Thickness
4.29.1 Conducting Film Thickness for Metallization Options with LM
TV DV
FV 5.2m Polyimide
3.0um Polyimide
0.40m Nitride
TD (Al)
See Note 2 0.45m Oxide
TD (Al) 0.45m Oxide TV
0.07m Nitride
LM LM
1.27 0.18 (Al)
C4 Final Passivation WIREBOND

NOTES:
1. All BEOL Metal
LM 0.55 0.14 Levels Are
Copper Unless
Otherwise Noted
VG 0.65 0.12
VQ 0.65 0.12 2. Final Passivation
MG 0.55 0.14 Nitride Thickness:
0.22m not
0.65 0.12 under TD
VQ 0.40m under TD
MQ 0.55 0.14 MQ 0.55 0.14

(Resistor)
VL 0.65 0.12 (0.75 0.12 w/ Kx resistor) VL Kx
Mx (x= 3,4,5,6) 0.32 0.12 Mx (x= 3,4,5)
Vx (x= 2,3, 4, 5) 0.35 0.08 Vx (x=2,3, 4)
M2 0.32 0.12 M2
V1 0.35 0.08 V1
M1 0.29 0.11 M1
0.15 0.015 0.35 0.095, Nitride, BPSG CA

PC (Wire)
STI 0.35 0.03

PC (Gate)
Figure 94. BEOL Conducting and Interlevel Film Thicknesses for LM metallization option - Thicknesses not drawn to
scale

Conducting Film Thickness
4.29.2 Conducting Film Thickness for Metallization Options with MA

Final Passivation (LV for C4 or DV for Wirebond)
(The thicknesses given are physical dimensions)
2.5 m (Polyimide 1.0m min to 7.0m max measured over MA)
0.45 m (Nitride)
1.35 m (Oxide)
NOTES:
1. All BEOL Metal
MA (Alum) Levels Are
4.0 0.5 Copper unless
otherwise specified.
F1 4.0 0.5 (Resistor)

L1
E1 E1
3.0 0.5
FT 4.0 0.5
FT
HY (MIM)
4.0 0.5
QY (MIM) QY (MIM)
LY (Alum) 0.46 0.07 LY (Alum)
FY 1.4 0.3
FY 1.40.3 MG 0.55 0.14
VQ 0.65 0.12
MQ 0.55 0.14 MQ 0.55 0.14

(Resistor)
Mx (x= 2,3,4) 0.32 0.12 Mx (x=2,3) 0.32 0.12
Vx (x=1,2,3) 0.35 0.08 Vx (x=1,2) 0.35 0.08
M1 0.29 0.11 M1
0.35 0.095, Nitride, BPSG CA

0.15 0.015
PC (Wire)
STI 0.35 0.03

PC (Gate)
Figure 95. BEOL Conducting and Interlevel Film Thicknesses with MA metallization - Thicknesses not drawn to scale

Conducting Film Thickness IBM
4.29.3 Conducting Film Thickness for OL with LD Metallization Options
DV or LV 5.2um Polyimide (DV) for Wirebond.

3.0um Polyimide (LV) for C4 NOTE:
1. All BEOL metal
4.0 0.40 (Alum) levels are copper
except VV via and
0.45m Nitride LD last metal.
1.35m Oxide
LD (Alum)
0.90m Oxide
0.10m Nitride
VV
OL OL
3.0 0.5
(Single Hi-K MIM or

Single Nitride MIM KT
when MG is HT
not present) HT
JT 2.1 0.42
JT 2.1 0.42 QT
QT
KT (Hi-K MIM,
(Dual Nitride MIM MG 0.55 0.14 when MG
HT when MG is is present)
present, delete
QT KT for single VQ 0.65 0.12
Nitride MIM)
MQ 0.55 0.14 MQ 0.55 0.14
(Resistor)
Mx (x= 2,3,4,5) 0.32 0.12 Mx (x=2,3,4,5)
Vx (x=1,2,3,4) 0.35 0.08 Vx (x=1,2,3,4)
M1 0.29 0.11 M1

0.15 0.015
PC (Wire)
STI 0.35 0.03

PC (Gate)
Figure 96. BEOL Conducting and Interlevel Film Thicknesses for OL with LD metallization - Thicknesses not drawn to
scale

Conducting Film Thickness
4.29.4 Conducting Film Thickness for AM Metallization Option
Final Passivation (LV for C4 or DV for Wirebond)

2.5m (Polyimide 1.0m to 7.5m max measured over AM)
0.45m (Nitride)
1.35m (Oxide)
NOTE: All BEOL metal
levels are copper
AM (Alum) 4.0 0.4 except FQ via
and AM metal.
FQ 1.92 0.30
MQ 0.55 0.14 MQ
(Resistor)
VL 0.65 0.12 (0.75 0.12 w/ Kx resistor) VL K5
M5 0.32 0.12 M5
V4 0.35 0.08 V4
M4 0.32 0.12 M4
V3 0.35 0.08 V3
M3 0.32 0.12 M3
V2 0.35 0.08 V2
M2 0.32 0.12 M2
V1 0.35 0.08 V1
M1 0.29 0.11 M1

0.15 0.015
PC (Wire)
STI 0.35 0.03

PC (Gate)
Figure 97. BEOL Conducting and Interlevel Film Thicknesses for AM metallization - Thicknesses not drawn to scale

Wire Resistance Models IBM
4.30 Wire Resistance Models
4.30.1 Contact and Via Resistance

The following table lists contact resistance values. Contacts are made through M1/CA to RX or PC. If M1
through RX or M1 through PC contacts are stacked vertically, add the two relevant contact resistances to get
the total.
Do NOT root-sum-square (RSS) the contact resistance values for multiple contacts. For worst case analysis
use the parallel combination of several contacts all at their worst case resistance value. The resistances
include the metal pad immediately above and any resistance due to the 90 degree bend in the current flow.
The resistances of the allowed via sizes described in section 3.1, Polysilicon and Isolation Layout Rules on
page 95 are listed in Table 168, Contact Resistance on page 416. For worst case analysis use the parallel
combination of several vias all at their worst case resistance value.
Table 168. Contact Resistance
Contact Levels Nominal Minimum / Maximum TCR1

[/contact] [/contact] [% / C]
CA2 M1-CA-PC 9 5 / 20 <0.5

M1-CA-RX
CA3 M1-CA-PC 9 5 / 25 <0.5

M1-CA-RX
1. TCR is nominal room temperature (25 C)

2. The nominal CA resistances are extracted from a single contact, fully landed
3. for (PC-CA space < 0.12) OR (CA within PC < 0.04 um), see R207 and R209, Table 24, N-well,
Contact, Junction Layout Rules on page 115
.\
Table 169. Via Resistance
Via Levels Nominal Minimum / Maximum TCR

Resistance Resistance1 [% / C]
[/via] [/via]
Vx2 M2-V1-M1 0.9 0.2 / 6.0 0.33

(x=1,2,3,4,5,6,A,M)
VL MQ-VL-M6 0.25 0.1 / 3.0 0.33

MQ-VL-M5
MQ-VL-M4
MQ-VL-M3
MQ-VL-M2
VQ LM-VQ-MQ 0.25 0.1 / 3.0 0.33

MG-VQ-MQ

Wire Resistance Models
Table 169. Via Resistance
Via Levels Nominal Minimum / Maximum TCR

Resistance Resistance1 [% / C]
[/via] [/via]
VG LM-VQ-MG 0.25 0.1 / 3.0 0.33
FY MG-FY-LY 0.55 0.2 / 3.0 < 0.5

MQ-FY-LY
FT LY-FT-E1 0.40 0.2 / 3.0 < 0.5
F1 E1-F1-MA 0.27 0.1 / 3.0 < 0.5
JT OL-JT-MG 0.10 0.05 / 2.5 0.33

OL-JT-MQ
FQ AM-FQ-MQ 1.30 0.6 / 2.0 0.33
C4 VIA LM 0.02 0.004 / 0.1 0.33
C4 VIA MA or LD 0.02 0.004 / 0.1 < 0.33
1. Including TCR
2. All nominal via resistances are extracted for fully landed Via
4.30.2 Resistance of Conducting Film

The 25 C sheet resistances and film thicknesses are listed in the following tables.
Table 170. Conducting Film Thicknesses and Sheet Resistances at 25C
Film Rules Design Thickness Rs TCR

Width [m] [/square] [% / C]
[m]
P-well (under STI) - - - 1401 110 -

2602 110
Vertical P-well resistance - - 1.0 1.0 0.35 -

[k-um2]
N-well (under STI) 250 0.7 - 540 110 0.2
N-well (under STI over ESDIODE) 250 0.92 - 420 110 0.2
N-well3 (under STI outside (PI TW06 1.10 - 420 110 0.2
expanded by +1.1um))
Vertical N-well resistance - - 1.0 1.5 0.40 -

[k-um2]
P+ unsalicided poly - >2 0.15 0.015 340 40 -0.08 0.06
N+ unsalicided diffusion - > 0.20 - 73 8 0.143 0.1


[m]
N+ diffusion bounded by PC and 110 0.28 - 73 0.32

isolation
P+ diffusion bounded by PC and 110 0.28 - 73 0.34

isolation
N+ diffusion bounded by PC 104 < 0.22 - 12 0.31

7 / +60
N+ diffusion bounded by PC 104 0.22 - 10 0.31

< 0.26 5 / +15
N+ diffusion bounded by PC 104 0.26 - 73 0.31
P+ diffusion bounded by PC 104 < 0.22 - 12 0.34

7 / +100
P+ diffusion bounded by PC 104 0.22 - 10 0.34

< 0.26 5 / +15
P+ diffusion bounded by PC 104 0.26 - 73 0.31
N+ diffusion bounded by isolation4 50 0.22 0.17 0.017 73 0.32
P+ diffusion bounded by isolation 50 0.22 0.15 0.015 73 0.29
PC (N+ or P+) 100 0.12 0.15 0.015 73 0.32
M1 500 < 1.0 0.29 0.11 0.0709 0.0297 0.30
M1 500 1.0 0.32 0.11 0.0643 0.0242 0.30
M2, M3, M4, M5, M6 600 < 1.0 0.32 0.12 0.0639 0.0262 0.30
M2, M3, M4, M5, M6 600 1.0 0.35 0.12 0.0584 0.0217 0.30
MQ, LM, MG 635 < 1.0 0.55 0.14 0.0373 0.0082 0.30
MQ, LM, MG 635 1.0 0.60 0.14 0.0339 0.0068 0.30
TD WB04 58.0 1.27 0.18 - -
LY LY1 0.6 0.46 0.07 0.089 0.014 0.33
E1 E1a5, 1.50 E1 3.00 0.5 (0.006 + 0.33

E1aa Width (W) (0.0006 / W))
< 25.0 20%
E1aa, 25.0 E1 0.0063 0.00126

E1ab 6 30.0
(Wmax)
MA MA1 4.0 4.0 0.5 0.007 0.0014 0.38

Wire Resistance Models

[m]
OL OL37, 1.20 OL 3.00 0.5 (0.006 + 0.30

OL1b Width (W) (0.0006 / W))
< 25.0 20%
OL1b, 25.0 OL 0.0063 0.00126

OL18 30.0
(Wmax)
LD LD00 2.0 4.0 0.4 0.0070 0.0015 0.30

AM AM1 2.0 4.0 0.4 0.0070 0.0014 0.30
1. Measured over long distance (> 10 m). The lower resistance results from the fact that the current path is able to extend deep
into the bulk (with blanket implant).
2. Measured over short distances (< 10 m).
3. N-well Rs and TCR for NW outside PI is preliminary information, and is subject to change. See BT generation in .Table 8, Shape
Manipulation Prior to Mask Write on page 59.
4. Measured from bottom of CoSi2 to junction edge.
5. For E1 Rs value, W is the design width of the E1 wire in m.
6. For Inductor modeling only, see also Rule E1ab Table 51, on page 169 for Wmax.
7. For OL Rs value, W is the design width of the OL wire in m.
8. For Inductor modeling only, see also OL Rule for Wmax.
Note: Starting substrate resistivity is 1-2 ohm-cm.
4.30.3 Calculating Metal Line Resistance

The metal line resistance R per unit length is calculated as [/m]
Rs
R = ------------
-
W eff
with Rs taken from Table 170, Conducting Film Thicknesses and Sheet Resistances at 25C and Weff
defined as Weff = [Wc - (2 x PLB) - (2 x ELB)] with Wc from Table 171, Corrected Linewidth for Wires with
HOLE Shapes, and Physical Line Bias (PLB) and Electrical Line Bias (ELB) in Table 180, Extraction
Parameters for Metal Wiring.
Table 171. Corrected Linewidth for Wires with HOLE Shapes1
Contact Designed Linewidth, Wd Corrected Linewidth, Wc
M1 0.16 Wd 1.8 Wd
M1 1.8 < Wd 50 1.4 + 0.7 * (Wd 1.4)

Table 171. Corrected Linewidth for Wires with HOLE Shapes1
Contact Designed Linewidth, Wd Corrected Linewidth, Wc
M2, M3, M4, M5, M6 0.2 Wd 1.8 Wd
M2, M3, M4, M5, M6 1.8 < Wd 50 1.4 + 0.7 * (Wd 1.4)
MQ, MG, LM 0.4 Wd 2.4 Wd
MQ, MG, LM 2.4 < Wd 50 2.4 + 0.7 * (Wd 2.4)
OL2 Wd 1.2 Wd
LD 2 Wd 2.0 Wd
LY 2 Wd 0.6 Wd
E1 2 Wd 1.5 Wd
MA 2 Wd 4.0 Wd
AM 2 Wd 2.0 Wd
1. Because wide Copper wires will contain Metal HOLE shapes, the Effective Linewidth Weff must be
used for all Electron migration calculations (see Table 220, Current Limits at 100C, on page 492).
2. Note that LY, E1, MA, AM, OL, and LD do not require HOLE shapes.
The wiring resistance tolerance as a percent may be calculated as follows. The tolerances for T can be found
in Table 170, Conducting Film Thicknesses and Sheet Resistances at 25C, and Weff from Wd in Table
171, Corrected Linewidth for Wires with HOLE Shapes with Table 180, Extraction Parameters for Metal Wir-
ing. By applying this procedure to an array of minimum width and minimum space wires, the results in Table
172 are obtained. Note that all these cases give metal density pattern factors below 50%.
R A 8 A 2
-------- = -------- 1 + --- --------
R A 9 A
A T Weff
2 2
-------- = - + ------------------
-------
A T Weff
Table 172. Wire Resistance in an Array of Minimum Width and minimum Space Wires at 25C
Metal Layer Wire Resistance Wire Resistance Tolerance

per Unit Length
[/m] [/m] [%]

M1 (Wd=0.16 m) 0.518 0.287 55.5
M2, M3, M4, M5, M6 0.320 0.162 50.6

(Wd=0.20 m)

Wiring Capacitance Models
Table 172. Wire Resistance in an Array of Minimum Width and minimum Space Wires at 25C
Metal Layer Wire Resistance Wire Resistance Tolerance

per Unit Length
[/m] [/m] [%]

MQ, MG, LM (Wd = 0.40 m) 0.1051 0.039 36.8
MQ, MG, LM (W = 1 m) 0.035 0.010 27.9
LY 0.153 0.080 52
E1 0.0040 0.001 26
MA 0.0017 0.0004 22.5
OL 0.00502 0.0013 26.1
LD 0.0035 2 0.0012 34.9
1. This wire resistance per unit length value is from the Wafer Acceptance Criteria.
2. This wire resistance per unit length value is calculated from Wd, the design linewidth.
4.31 Wiring Capacitance Models
4.31.1 Interlevel Area Capacitance

The area component of wiring capacitance may be calculated using the dielectric thicknesses given in the fol-
lowing tables.
4.31.2 Parameters for Capacitance Calculation

The film parameters for the calculation of the wiring capacitances are found in Table 173, Wiring Capaci-
tance Model Parameters on page 422. These numbers assume that the calculation will be done with wiring
at pitch (a minimum line with neighboring lines at minimum space) and 100% metal coverage above and
below by metal. The interlevel thicknesses are the physical dielectric thicknesses.
The actual wiring capacitance is the sum of four capacitance components: Cup, Cdown, Cright, and Cleft. Each
component can be calculated as follows. Calculate an initial value for each component by assuming that the
surrounding dielectric medium is uniform and has a relative dielectric constant equal to one. This calculation
can be done using an analytical formula or a two-dimensional simulation tool. The final value for each compo-
nent is then obtained by multiplying the initial value by the corresponding effective dielectric constant, as
given in Table 174, Effective Dielectric Constant on page 423.
Accurate calculations of capacitance where closely spaced electrodes are involved will require 2-dimensional
or 3-dimensional simulation. This should be done for structures such as bit lines in which accurate prediction
of capacitance is critical.

Wiring Capacitance Models IBM
Table 173. Wiring Capacitance Model Parameters
Wiring Levels Design hB hA W1 Da Tfilm Sidewall

Size (lower (upper (wire (wire (wire Angle
(L/S) ILD) ILD) width) spacing) height) [degree]
[m] [m] [m] [m] [m] [m]
PC over isolation under M1 0.12/0.20 0.35 0.31 0.092 0.228 0.15 90
M1 over PC under M2 0.16/0.16 0.31 0.35 0.16 0.16 0.29 88.5 2
M1 over active area under M2 0.16/0.16 0.46 0.35 0.16 0.16 0.29 88.5 2
M1 over isolation under M2 0.16/0.16 0.81 0.35 0.16 0.16 0.29 88.5 2
M2 over M1 under M3 0.2/0.2 0.35 0.35 0.22 0.20 0.32 88.5 2

M3 over M2 under M4
M4 over M3 under M5
M5 over M4 under M6
M4 over M3 under MQ 0.2/0.2 0.35 0.65 0.22 0.20 0.32 88.5 2

M5 over M4 under MQ
M6 over M5 under MQ
MG over MQ under LM 0.4/0.4 0.65 0.65 0.42 0.4 0.55 88.5 2
MQ over M3 under LM 0.4/0.4 0.65 0.65 0.42 0.4 0.55 88.5 2

MQ over M4 under LM
MQ over M5 under LM
MQ over M6 under LM
MQ over M4 under MG
MQ over M5 under MG
MQ over M2 under LY 0.4/0.4 0.65 1.4 0.42 0.4 0.55 88.5 2

MQ over M3 under LY
MQ over M4 under LY
MG over MQ under LY
MQ over M2 under OL 0.4/0.4 0.65 2.1 0.42 0.4 0.55 88.5 2

MQ over M3 under OL
MQ over M4 under OL
MQ over M5 under OL
MG over MQ under OL
LM over MQ 0.4/0.4 0.65 - 0.42 0.4 0.55 88.5 2

LM over MG
LY over MQ under E1 0.60 / 0.60 1.4 4.0 0.58 0.62 0.46 92.3 3
LY over MG under E1
OL over MQ 1.2/1.2 2.1 - 1.36 1.04 3.0 87 3

OL over MG
E1 over LY under MA 1.5 / 2.0 4.0 4.0 1.5 2.0 3.0 85 3
MA over E1 4.0 / 5.0 4.0 - 4.16 4.84 4.0 92.3 3
1. Note: The W and D are wafer values at half height.

Table 174. Effective Dielectric Constant
Wiring Levels up down right left right left

nested isolated
PC over isolation under M1 4.39 4.10 5.21 4.10
M1 over PC under M2 4.18 4.39 4.36 3.60
M1 over active area under M2 4.18 4.29 4.34 3.60
M1 over isolation under M2 4.18 4.21 4.34 3.60
M2 over M1 under M3 4.18 4.18 4.00 3.60

M3 over M2 under M4
M4 over M3 under M5
M5 over M4 under M6
M4 over M3 under MQ 3.96 4.18 4.14 3.60

M5 over M4 under MQ
M6 over M5 under MQ
MG over MQ under LM 3.96 3.96 3.94 3.60
MQ over M3 under LM 3.96 3.96 3.94 3.60

MQ over M4 under LM
MQ over M5 under LM
MQ over M6 under LM
MQ over M4 under MG
MQ over M5 under MG
LM over MQ - 3.96 3.96 3.60

LM over MG
MQ over M2 under OL 4.00 3.96 3.96 3.60

MQ over M3 under OL
MQ over M4 under OL
MQ over M5 under OL
MG over MQ under OL
MQ over M2 under LY 4.19 3.96 3.96 3.60

MQ over M3 under LY
MQ over M4 under LY
MG over MQ under LY
OL over MQ - 4.00 3.93 3.90
OL over MG
LY over MQ under E1 4.13 4.19 4.50 4.1

LY over MG under E1
E1 over LY under MA 4.13 4.13 4.19 4.1
MA over E1 - 4.13 3.81 3.4

4.31.3 Wiring Capacitance Tracking
The tracking percentages listed below are for identical metal lines (M1, Mx and LM, MQ, MG) on the same
wiring level that are less than 1500 m long and less than 500 m apart. In addition, the lines must be sym-
metrical with respect to conductors crossing above and below and with respect to adjacent lines on the same
level. The lines are assumed to be design minimum width.
M1 5%
Mx 5%
LM, MQ, MG 5%
4.31.4 Quick Lookup Wiring Capacitances
Interlevel Capacitance
Table 175 presents the wiring capacitance for the various levels. (These numbers assume a metal plate
above and below, and minimum pitch wiring at the same level. ) See the pitches in Table 173, Wiring Capac-
itance Model Parameters on page 422. All parameters are assumed to be nominal. All values in the table are
for wafer dimensions.
Table 175. Wiring Capacitances1 Isolated Line
Wiring Levels Cup Cdown Cleft/Right Ctotal Cup C down Ctotal
PC over isolation under M1 0.0369 0.0308 0.0507 0.1691 0.0650 0.0569 0.1219
M1 over PC under M2 0.0334 0.0376 0.095500 0.2619 0.0730 0.0834 0.1565

M1 over active under M2 0.0334 0.0251 .0997 0.2579 0.0780 0.0638 0.1417
M1 over isolation under M2 0.0334 0.0141 0.1022 0.2519 0.0864 0.0428 0.1292
M2 over M1 under M3 0.0413 0.0395 0.0766 0.2341 0.0805 0.0787 0.1592

M3 over M2 under M4
M4 over M3 under M5
M5 over M4 under M6
M4 over M3 under MQ 0.0215 0.0395 0.0855 0.2320 0.0511 0.0870 0.1382

M5 over M4 under MQ
M6 over M5 under MQ
MG over MQ under LM 0.0418 0.0402 0.0659 0.2139 0.0771 0.0755 0.1526
MQ over M3 under LM 0.0418 0.0402 0.0659 0.2139 0.0771 0.0755 0.1526

MQ over M4 under LM
MQ over M5 under LM
MQ over M6 under LM
MQ over M4 under MG
MQ over M5 under MG
MQ over M2 under LY 0.0211 0.0402 0.0734 0.2082 0.0485 0.0858 0.1343

MQ over M3 under LY
MQ over M4 under LY
MG over MQ under LY

Table 175. Wiring Capacitances1 Isolated Line
Wiring Levels Cup Cdown Cleft/Right Ctotal Cup C down Ctotal
MQ over M2 under OL 0.0150 0.0441 0.0760 0.2110 0.0356 0.0913 0.1270

MQ over M3 under OL
MQ over M4 under OL
MQ over M5 under OL
MG over MQ under OL
LM over MQ - 0.0402 0.0784 0.1970 - 0.1150 0.1150

LM over MG
OL over MQ - 0.0460 0.1310 0.3080 - 0.1280 0.1280

OL over MG
LY over MQ under E1 0.0107 0.0311 0.0643 0.1704 0.0279 0.0799 0.1079
LY over MG under E1
E1 over LY under MA 0.0330 0.0282 0.0801 0.2212 0.0719 0.0671 0.1390
MA over E1 - 0.0751 0.0494 0.1740 - 0.1459 0.1459

1. Capacitance per unit length [ fF/m ]
4.31.5 PC to CA Capacitance
This capacitance becomes important at minimum CA to PC spaces and is sensitive to alignment. The value in
the following table is for an on pitch row of CAs next to a PC line at minimum space.
Table 176. PC to CA capacitance1
Parameter Value2 Tolerance
PC-CA capacitance for 0.10 um PC-CA space 0.016 fF/CA +0.016/-0.008
1. Note: the overlap capacitance in the FETs models does not include
PC-to-CA-M1 coupling capacitance.
2. value subject to change with hardware data.
4.31.6 Final Passivation
LM Last Metal Option

Final Passivation for the LM last metal option is shown in Figure 94, on page 412. See Table 177, on
page 426 for the final passivation dielectric constants.
MA Last Metal Option

Final Passivation over MA last metal option is 1.35 m oxide, 0.45 m nitride, plus 1.0 to 7.5 m (2.5 m
nominal) polyimide and is shown in Figure 95, on page 413. For the final passivation dielectric constants,
see Table 177, on page 426

OL with LD Last Metal Option
Final Passivation over LD last metal option is 1.35 m oxide, 0.45 m nitride, plus 5.2 m nominal Polyimide
(DV) for Wirebond or 3.0 m nominal Polyimide (LV) for C4 and is shown in Figure 96, on page 414. For the
final passivation dielectric constants, see Table 177, on page 426
AM Last Metal Option

Final Passivation over AM last metal option is 1.35 m oxide, 0.45 m nitride, plus 1.0 to 7.5 m (2.5 m
nominal) polyimide and is shown in Figure 97, on page 415. For the final passivation dielectric constants,
see Table 177, on page 426
4.31.7 Dielectric Constants
Table 177. Dielectric Constants

Material Value
Oxide 4.1 or 3.6
(dependent on metal/via interlevel
level dielectric)
Nitride 7.0
Polyimide 3.4

4.31.8 Resistance and Capacitance Extraction Parameters
Table 178. Extraction Parameters for Polysilicon1
Parameter Label Description Design Wafer Bias per edge 3

[m] Physical (design physical)/2 Tolerance
[m] [m] per edge
[m]
Polysilicon resistance E1 PC width 0.12 0.092 0.014 0.011

and parasitic capaci- at half-height
tance.
(Wiring)
Polysilicon resistance E1UT PC width 0.12 0.070 0.025 0.0095

and parasitic capaci- at half-height
tance.
(Wiring)
Polysilicon resistance E2 NGATE and 0.12 0.092 0.014 0.011

and parasitic capaci- PGATE width
tance to metal layers. at half-height
Polysilicon resistance E2UT NGATE and 0.12 0.070 0.025 0.0095

and parasitic capaci- PGATE width
tance to metal layers. at half-height
Polysilicon to polysili- E3 PC to PC space 0.20 0.228 0.014 0.011

con wiring capacitance at half-height
Polysilicon to polysili- E3UT PC to PC space 0.20 0.250 0.025 0.0095

con wiring capacitance at half-height
Polysilicon wiring to E4 PC to RX space 0.08 0.094 0.014 0.042

diffusion capacitance at half-height (per shape)
Polysilicon wiring to E4UT PC to RX space 0.08 0.105 0.025 0.042

diffusion capacitance at half-height (per shape)
Spacer width E5 - - 0.07 - 0.007
1. NGATE is defined as PC over RX not over BP; PGATE is defined as PC over both RX and BP; PC is
defined as PC not over RX. Note that width as used here is in the direction of Leff.
Table 179. Extraction Parameters for Diffusion1

[m] [m] per edge
[m]
Butted Junction E10 Butted Junction 0.16 0.115 0.023 0.040
Diffusion resistance, E7 RX bounded by 0.20 0.088 0.056 0.017

poly-bounded NGATE/PGATE poly
and spacers.

Table 179. Extraction Parameters for Diffusion1

[m] [m] per edge
[m]
Diffusion capacitance, E8 RX bounded by 0.20 0.228 0.014 0.011

poly-bounded, a NGATE/PGATE poly
(width at half-height)
Diffusion resistance, E7UT RX bounded by 0.20 0.110 0.045 0.017

poly-bounded NGATE/PGATE
spacers
Diffusion capacitance, E8UT RX bounded by 0.20 0.250 0.025 0.0095

poly-bounded, a NGATE/PGATE poly
(width at half-height)
Diffusion resistance E9 RX width at top 0.16 0.115 0.0225 0.020

and capacitance, N bounded by shallow
and P, isola- trench isolation
tion-bounded, b
N-well resistance & Effective electrical 0.7 0.556 0.072 0.05

capacitance width
1. See section 4.17, Junction Diodes on page 376, for use of a and b in capacitance calculations.
Table 180. Extraction Parameters for Metal Wiring
Parameter Design Pattern Physical Line Bias1 Electrical Line Bias2 3

width Factor = (design physical)/2 = (physical electrical)/2 Tolerance
= PLB = ELB per edge
[m] [m] [m]
M1 resistance all all 0.00 0.0115 0.0225

M2, M3, M4, M5, M6 all all -0.01 0.0000 0.030
resistance
MQ, MG, LM resis- all all -0.01 0.0220 0.045

tance
LY resistance all all +0.01 0.0 0.130

E1 resistance all all 0.0 0.0 0.125
MA resistance all all -0.08 0.0 0.430
OL resistance all all -0.08 0.0 0.130
S12.53 -0.080 0.0

LD resistance all 0.300
S<12.5 0.05584 0.0
3

Electrical Moat Parameters
1. Per edge, a positive number means that the on wafer is smaller than the design dimension. The physical (on wafer) dimension here
is measured at the half height.
2. Per edge, a positive number means that the electrical linewidth is smaller than the physical dimension.
3. The physical bias of LD lines as a function of the space to the next line (S) is given by the following:
If S < 12.5 Bias per edge = [-((0.028 x S) - 0.19)]/2. If S 12.5 Bias per edge = -0.08
4. Assumes minimum LD space of 2.8um
RX
E4
BP
PC PC
RX
E2
E10
E9
E1 Gate
E3
Spacer
E1,E2 E3
Source
Drain Isolation
E5 E6
E7
Diffusion boundaries Diffusion boundaries

for capacitance for resistance
E8
Figure 98: Extraction parameters
4.32 Electrical Moat Parameters

By designing a BFMOAT level, the designer may insert a resistive element between different regions of the
substrate. This may be useful to reduce the coupling of substrate noise between two regions on the same
chip. Table 181, Moat Parameters indicates how much resistive isolation may be obtained for a given moat
width.

Electrical Moat Parameters IBM
BFMOAT isolation is not supported within T3 isolation well.
For example, if a square region of 500 um on a side were to be surrounded by a moat 100 um long, the total
substrate resistance between the two regions would be:
Width of moat =100 um; Rmoat=50,000 ohm-um
Effective Length of moat = [ 500um + (100 um x 0.56)] x 4 = 2224 um (corner pieces contribute 0.56
squares to the total length
Resistance = 50,000/2224 = 22.5 ohms
Table 181. Moat Parameters
Moat length (um) Moat resistance (ohm-um)
10 23,000
20 30,000
30 33,000
50 40,000
100 50,000
The data in Table 181, Moat Parameters is based on a process model with a substrate similar to that of
CMOS8RF (CMRF8SF).
Figure 99. Moat Example
BFMOAT
500 m
100 m
600 m

Noise
4.33 Noise
4.33.1 1/f Noise

1/f noise are modeled using the BSIM4 set of noise equations. These equations incorporate the Qinv term
from the BSIM4 charge model into the thermal noise model and a Vds and Vgs bias dependence into the 1/f
noise model.
The BSIM4 noise model equations are documented in the standard BSIM4 Manual available from the
University of California at Berkeley.

Inductor IBM
4.34 Inductor
There are four back end of the line (BEOL) options available for CMOS8RF (CMRF8SF):
i) An all copper option associated with the base CMOS offering (LM) consisting of thin (1x) copper levels and
thicker (2x) copper levels;
(ii)An MA option (commonly referred to also as the Dual Metal or DM option) consisting of additional thick
dielectric and metal layers (LY, E1 and MA) above the base CMOS BEOL for low resistance and low parasitic
applications;
(iii) An OL option consisting of additional thick dielectric and metal layers (OL and LD) above the base CMOS
BEOL for low resistance and low parasitic applications.
(iv) AN AM option consisting of 5 thin (1x) copper levels, one thick (2x) copper level (MQ) and a final thick alu-
minum level (AM)
The base CMOS option consists of spirals constructed of LM in parallel with MQ (for designs with two thick
levels) or LM in parallel with MG and MQ (for designs with three thick levels). The MA option consists of three
different configurations: single layer inductors that can be realized at the uppermost level of metal (MA) as a
single layer spiral with an underpass to the center using the second to last metal level (E1), providing the
highest self resonant frequency achievable with this technology; MA and E1 spirals connected in parallel,
through one or more bar vias, to achieve a very low effective sheet resistance; MA and E1 spirals connected
in series to achieve a high inductance per unit area. The OL option consists of 2 different symmetric configu-
rations, single layer (symind) and parallel (symindp). A BF groundplane or M1 comb groundplane is optional
below all inductors. In addition, the OL option has been updated to include the standard inductors (ind, indp,
and inds) which were already available in the MA option.
Modelled inductors are not supported within T3 isolation well.
Note: The inductors have all been modelled assuming final passivation is covering the top of the spirals. If
the design is offered with no passivation, then the peak Q that is achieved (and in some cases peak Q fre-
quency and self-resonance frequency) will be slightly higher from the models predicted value. In general, this
increase will be less than 5%.
4.34.1 Parallel Stacked LM/MG/MQ Inductor (LM option, indp)

The vertical cross section of the parallel stacked spiral inductor consists of a metal spiral at the top levels of
metal (LM//MQ or LM//MG//MQ) with an underpass to the center of the spiral at the lowest thick copper level
(MQ). This composite structure is realized over a BF groundplane to maximize the self resonant frequency or
a M1 comb to maximize Q. This is standard inductor layout with inherent asymmetry, more suitable for sin-
gle-ended applications.
Table 182. Parallel Stacked Inductor Design Specifications
Specification BF/M1 Inductor

Inductance (nH) 0.21 to 33
Supported Turn Widths (m) 5 to 25
Supported Outer Diameters (m) 100 to 300
Turn-Turn Space (m) 3 to 5

Inductor

Number of Turns 1 to filled-in in 1/4 turn increments
4.34.2 Single Layer MA Inductor (MA option, ind)

The vertical cross section of the single layer spiral inductor consists of a metal spiral at the top level of metal
(MA) with an underpass to the center of the spiral at the second to last metal layer (E1). This composite struc-
ture is realized over a BF groundplane to maximize the self resonant frequency or a M1 comb to maximize Q.
This is a standard inductor layout with inherent asymmetry, more suitable for single-ended applications. .
Table 183. Single Layer Inductor Design Specifications

Inductance (nH) 0.21 to 21
Supported Turn Widths (m) 5 to 25
Turn-Turn Space (m) 5
Number of Turns 1 to filled-in in 1/4 turn increments
4.34.3 Dual Layer Parallel Stacked E1/MA Inductor (MA option, indp and
symindp)
The vertical cross section of the dual layer parallel stacked spiral inductor consists of a metal spiral at the top
level of metal (MA) connected in parallel, through one or more bar vias, with an identical spiral layer at the
second to last metal level (E1). For standard inductors, an underpass to the center of the spiral is provided at
the second to last metal layer (E1). For symmetric inductors, crossovers are provided by alternating between
the top level metal (MA) and the second to last metal layer (E1). These composite structures are realized
over a BF groundplane to maximize the self resonant frequency or a M1 comb to maximize Q. indp is a stan-
dard inductor layout with inherent asymmetry, whereas symindp is a symmetric layout suitable for differential
applications.
Table 184. Dual Layer Parallel Stacked Inductor Design Specifications
Specification BF/M1 Standard Spiral BF/M1 Symmetric Inductor

Inductance (nH) 0.21 to 21 0.2 to 24
Supported Turn Widths (m) 5 to 25 5 to 25
Supported Outer Diameters (m) 100 to 300 100 to 300
Turn-Turn Space (m) 5 5
Number of Turns 1 to filled-in in 1/4 turn increments 1 to filled-in in integer increments

Inductor IBM
4.34.4 Dual Layer Series Stacked E1/MA, AM/MQ, and OL/LD Inductors
(inds)
The vertical cross section of the series stacked spiral inductor consists of a metal spiral at the top level of
metal (MA, AM, or LD) connected in series with a similarly wound spiral at the second to last metal level (E1,
MQ, or OL) directly underneath it. This composite structure is realized over a BF groundplane to maximize
the self resonant frequency or a M1 comb to maximize Q. The OL inds can also be created without the top LD
layer and so be built on OL and the top 2x copper level MG or MQ.
Table 185. Dual Layer Series Stacked Inductor Design Specifications
Specification DM BF/M1 Inductor AM BF/M1 Inductor OL BF/M1 Inductor

Inductance (nH) 0.5 to 92 0.247 to 394 0.48 to 355
Supported Turn Widths (m) 5 to 25 2.01 to 30 2.02 to 30
Supported Outer Diameters (m) 100 to 300 75 to 300 100 to 300
Turn-Turn Space (m) 5 2.81-5 3-5
Number of Turns 2 to filled-in in 1/2 turn 2 to filled-in in 1/2 turn 2 to filled-in in 1/2 turn
increments increments increments
4.34.5 OL Single Layer Inductors (ind and symind)

The vertical cross section of the single layer spiral inductor either consists of a spiral at the top level of copper
metal (OL) and crossovers occurring at the metal level right below OL (MG if available, or MQ); or a symmet-
ric spiral at the top aluminum metal (LD) and crossovers occurring at OL. This composite structure is realized
over a BF groundplane to maximize the self resonant frequency or a M1 groundplane to maximize Q.
Table 186. Single Layer Inductor Design Specifications
Specification BF/M1 Standard Spiral BF/M1 Symmetric Inductor

Supported Turn Widths (m) 3 to 30 6 to 30
Turn-Turn Space (m) 3 to 5 3 to 5
Number of Turns 1 to filled-in 1/4 turn increments 1 to filled-in in integer increments
4.34.6 OL/LD Parallel Stacked Inductors (indp and symindp)

The vertical cross section of the parallel stacked spiral inductor consists of a spiral at the top levels of metal
and crossovers at alternating top level metals. This composite structure is realized over a BF groundplane to
maximize the self resonant frequency or a M1 groundplane to maximize Q.
Specification BF/M1 Parallel Spiral BF/M1 Parallel Symmetric

Supported Turn Widths (m) 6.04 to 30 6 to 30

Inductor
Specification BF/M1 Parallel Spiral BF/M1 Parallel Symmetric

Turn-Turn Space (m) 3 to 5 3 to 5
Number of Turns 1 to filled-in in 1/4 turn increments 1 to filled-in in integer increments
4.34.7 AM/MQ Parallel Stacked Inductor (symindp)

The vertical cross section of the parallel stacked symmetric spiral consists of a spiral at the top level of metal
(AM)connected in parallel, through many FQ vias, with an identical spiral layer at the second to last metal
level (MQ). This composite structure is realized over a BF groundplane to maximize the self resonant
frequency or a M1 groundplane to maximize Q. Supported widths are from 2 m to 30 m and diameters of
75 m to 300 m.
Specification BF/M1 Parallel Symmetric

Inductance (nH) 0.067 to 90.7
Supported Turn Widths (m) 2.02 to 30
Turn-Turn Space (m) 2.81 to 5
Number of Turns 1 to filled-in in integer increments
4.34.8 Inductor Design Considerations

Due to the fact that the inductor is fabricated over a conductive silicon substrate, the actual inductance and
quality factor seen in a circuit vary considerably with frequency. At low frequencies, the inductor behaves as a
pure inductance with a series resistance (metal resistance). At higher frequencies, however, the inductor is
shunted not only by the parasitic capacitance from turn to turn, but by the capacitance that exists between the
metal layers and the substrate itself. In this technology the silicon substrate is conductive (1.0-2.0 -cm).
This conductive substrate begins to cause power loss in the inductor structure at higher frequencies due to
the mentioned capacitance effect. This interplay between the inductance and the parasitic capacitance and
resistance causes the quality factor (Q) to rise at low frequencies, peak and then fall off at high frequencies.
The peak Q and the frequency at which it falls off will be lower than an equivalent inductor realized in a pro-
cess utilizing a semi-insulating substrate such as GaAs (all other factors being equal. i.e. metal sheet rho).
4.34.9 Inductor Ground Connection Notes (simulation and layout)

Simulation
Proper connection to the ground node of the spiral inductor during simulation is critically important to
achieving accurate simulation results.
The model for the BF groundplane spiral inductor has a ground node that must be connected to an ideal AC
ground in order to provide accurate simulations. This ideal ground connection does not represent an actual
physical connection to the P- substrate underneath the inductor and therefore should not contain series

Bondpad Models IBM
resistance representing the resistance present between the inductor and any adjacent substrate contacts.
The requirement for an ideal AC ground represents a limitation of representing a large, distributed spiral with
a lumped element circuit.
The M1 groundplane inductor model has an explicit ground connection representing the physical connection
to the M1 groundplane. This node should not be connected to an ideal ground as in the BF groundplane case
described above. It should be connected to the physical node representing the AC ground potential used to
ground the M1. This way, the actual impedance of the groundplane connection can be included in the
simulation.
Layout
In order for the ideal AC ground connection to the ground node of the inductor to be a valid representation of
the physical layout, all substrate contacts must be placed at least 80m from the spiral. This ensures that the
resistance between the spiral and the substrate contacts is large enough to decouple the spiral from those
substrate contacts.
4.34.10 Inductor to Wirebond/C4 Spacing Recommendations

In applications that require the highest possible Q for a given inductor layout, the proximity of the inductor to
adjacent metal areas is important. Adjacent metal areas that are tied to an AC ground (DC supplies) will add
capacitance in parallel with the inductance, lowering the self resonance. Large planes or closed loops of
metal placed close to an inductor will support eddy and loop currents that will lower the peak Q. In addition to
the obvious sources of nearby metal in the metal interconnect levels, the orientation of wirebond and C4 pads
should also be considered.
A C4 solder ball will actually extend beyond the edge of the TV and FV or LV shapes defining it due to its
inherently spherical shape. This may cause the C4 ball to end up closer to an inductor than is expected. Due
to these concerns, and C4 splattering concerns, it is recommended to maintain a spacing of 110m
between C4 solder balls and inductors, or 83m to wirebond pads, to avoid unwanted coupling and power
loss. These recommendations are not enforced for inductors since some designs are chip area limited and/or
do not require high Q inductors. On these types of designs, it is not necessary to follow the recommendations
above.
Please note that a C4 solder ball may also be present when there is no active connection required. This type
of C4 ball is defined by the TVDUMMY or LVDUMMY layer. Dummy C4 balls are provided for mechanical
rigidity in certain packaging applications.
4.35 Bondpad Models

A bondpad model is offered that simulates the loading effect of an LM C4 pad or TD wirebond pad over four
possible groundplanes: BFMOAT, PC, or RX or M1. The four groundplanes provide different combinations of
capacitance and groundplane resistance. Wire bond and C4 bondpads are offered for the OL/LD and MA
back end of the line options as well.
Modeled bondpads over T3 Isolation well are not offered.
Modelled bondpads are not prohibited from being placed within a T3 isolation well, except for the BFMOAT
versions or (PC or RX) modelled versions over the perimeter IBLK design level.

Bondpad Models
4.35.1 LM Bondpad Design Considerations

Table 189. LM Wirebond Bondpad Design Specifications
Specification Wirebond (TD) Wirebond (TD) Wirebond (TD)

over over over
BFMOAT (PC or RX) M1
Oxide Area Capacitance (fF/m2) 0.0062 0.0063 0.0074
for thick levels=2, thin levels=3
Oxide Fringe Capacitance (fF/m) 0.0293 0.0295 0.0351
4.35.2 MA Bondpad Design Considerations

Table 190. MA Bondpad Design Specifications
Specification Bondpad Bondpad Bondpad Bondpad

over over over over
PC RX BFMOAT M1
MA Oxide Area Capacitance (fF/m2) 0.0023 0.0025 0.0025 0.0027
for thick levels=1, thin levels=2 plus LY,
E1,and MA
MA Oxide Fringe Capacitance (fF/m) 0.0267 0.0266 0.0265 0.0283
for thick levels=1, thin levels=2 plus LY,
E1,and MA
4.35.3 OL with LD Bondpad Design Considerations

Table 191. OL with LD Bondpad Design Specifications
Specification Bondpad Bondpad Bondpad Bondpad

over over over over
PC RX BFMOAT M1
OL/LD Oxide Area Capacitance (fF/m2) 0.0043 0.0041 0.0041 0.0046
for thick levels=1, thin levels=2 plus OL,
LD
OL/LD Oxide Fringe Capacitance (fF/m) 0.0390 0.0372 0.0372 0.0417
for thick levels=1, thin levels=2 plus OL,
LD

Bondpad Models IBM
4.35.4 Floating Bondpad Concerns
Floating terminal pad design rules 908 and 953 require that a connection be made between bond/C4 pads
and silicon. The purpose of these rules is to provide a DC connection between the bondpad and silicon in
order to bleed off excess charge to the wafer substrate during wafer processing. If a bondpad is connected
directly to a MIM capacitor, and it does not have a DC connection to the substrate, the MIM dielectric is very
likely to be damaged during processing. So, always provide a DC connection to ground from any terminal pad
to avoid charging induced damage during wafer processing.

Rfline Device Models
4.36 Rfline Device Models

The CMOS8RF (CMRF8SF) technology currently supports rfline devices consisting of the topmost two thick
levels (LM and MG or MQ) in parallel over BFMOAT (P- substrate) for the LM metal option and rfline device
consisting of the topmost MA level over BFMOAT (P- substrate) for the MA metal stack (where the MA metal
stack is also commonly referred to as the Dual Metal or DM option).
The transmission line width can range from 4m to 25m. The length of the line is limited to be within the
range from 100m to 1500m. If a longer line is desired, two or more smaller transmission lines should be
connected in series. A true microstrip lines are also currently offered. The rfline, as it is offered, is intended to
be used as an inductor with a very low inductance value and a high Q factor.
The vertical cross section of the rfline consists of a metal line on the topmost two layers (LM and MG or MQ))
for the LM metal option or a metal line on the topmost MA layer for the MA metal stack. The structure sits in a
bed of BFMOAT so that the relatively low resistance PWELL is not under the transmission line. No other
design levels are currently allowed under the transmission line.
RF Lines are not supported over T3 isolation well.
4.36.1 Rfline Design Considerations

Table 192. Rfline Design Specifications: LM metal option
Specification Rfline w/BFMOAT

Oxide Area Capacitance (fF/m2) 0.0114
Oxide Fringe Capacitance (fF/m) 0.0484 to 0.0620
Supported Lengths (m) 100 to 1500
Supported Widths (m) 4 to 25
Table 193. Rfline Design Specifications: MA metal option
Specification Rfline w/BFMOAT

Oxide Area Capacitance (fF/m2) 0.0022
Oxide Fringe Capacitance (fF/m) 0.0379 to 0.0475
Supported Lengths (m) 100 to 1500
Supported Widths (m) 4 to 25

Capacitive Loading/Transmission Line Effects for Arbitrarily Shaped Interconnects IBM
4.36.2 Rfline Ground Connection Notes (simulation and layout)
Simulation
Proper connection to the ground node of the rfline during simulation is critically important to achieving
accurate simulation results.
The ground node must be connected to an ideal AC ground in order to provide accurate simulations. This
ideal ground connection does not represent an actual physical connection to the P- substrate underneath the
rfline and therefore should not contain series resistance representing the resistance present between the
rfline and any adjacent substrate contacts. The requirement for an ideal AC ground represents a limitation of
representing a a distributed structure with a lumped element circuit.
Layout
In order for the ideal AC ground connection to the ground node of the rfline to be a valid representation of the
physical layout, all substrate contacts must be placed at least 80m from the rfline. This ensures that the
resistance between the line and the substrate contacts is large enough to decouple the line from those
substrate contacts.
4.36.3 Rfline to Wirebond/C4 Spacing Recommendations

In applications that require the lowest possible coupling for a given rfline layout, the proximity of the rfline to
adjacent metal areas is important. Adjacent metal areas that are tied to an AC ground (DC supplies) will add
capacitance in parallel with the rfline, increasing the capacitive coupling to ground. Large planes or closed
loops of metal placed close to a rfline will support eddy and loop currents that will increase power loss. In
addition to the obvious sources of nearby metal in the metal interconnect levels, the orientation of wirebond
and C4 pads should also be considered.
A C4 solder ball will actually extend beyond the edge of the TV and FV shape defining it due to its inherently
spherical shape. This may cause the C4 ball to end up closer to an rfline than expected. Due to these
concerns, and C4 splattering concerns, it is recommended to maintain a spacing of 110m between C4
solder balls and rflines, or 83m to wirebond pads, to avoid unwanted coupling and power loss. These rules
are not enforced for rflines since some designs are chip area limited and/or do not require low loss
transmission lines. On these types of designs, it is not necessary to follow the recommendations above.
Please note that a C4 solder ball may also be present when there is no active connection required. This type
of C4 ball is defined by the TVDUMMY layer. Dummy C4 balls are provided for mechanical rigidity in certain
packaging applications.
4.37 Capacitive Loading/Transmission Line Effects for

Arbitrarily Shaped Interconnects
The above mentioned rfline models (section 4.36, Rfline Device Models on page 439) are meant to simulate
only straight, isolated metal lines over a P- substrate. Many designs will re quire a comprehensive knowledge
of the actual capacitive loading/transmission line effects for metal interconnects that do not fit the restrictive
definition required for use of the provided transmission line models (bends, Tees, embedded lines,
crossovers, etc.). In these cases, it would be prudent to characterize the critical interconnects using an e-m
solver (such as HPs Momentum or Sonnet Softwares Sonnet, or one of many other similar software
packages).

Capacitive Loading/Transmission Line Effects for Arbitrarily Shaped Interconnects
These types of solvers are optimized for planar multilayer/multiconductor simulations at high frequency. After
describing the material properties of the substrate, interlayer dielectrics, and metal levels, a graphical layout
is input and Maxwells equations are solved for the configuration of interest. S-parameter data over the
simulated frequency range is the typical output. From these s-parameters, capacitance, inductance, and
resistance may be extracted for use in a Spectre or Hspice netlist, or the s-parameters may be used directly if
a linear simulator is being utilized.
In order to make effective use of one of these planar e-m simulators, it is necessary to know the required
material properties, such as permittivity, permeability, conductivity and loss tangents of the dielectrics and
substrate and conductivity of the metal. Additionally, the vertical stack heights of the dielectrics, metal levels
and substrate must be known. The table below is intended as a summary of the types of inputs required for
this type of e-m simulation along with some values or suggestions on where to locate them.
Parameter Value Source

Dielectric Thickness varies depending on layers Figure 94, BEOL Conducting and Inter-
of interest level Film Thicknesses for LM metallization
option - Thicknesses not drawn to scale on
page 412 or Figure 95, BEOL Conducting
and Interlevel Film Thicknesses with MA
metallization - Thicknesses not drawn to
scale on page 413
Metal Thickness varies depending on layers Figure 94, BEOL Conducting and Inter-
of interest level Film Thicknesses for LM metallization
option - Thicknesses not drawn to scale on
page 412 or Figure 95, BEOL Conducting
and Interlevel Film Thicknesses with MA
metallization - Thicknesses not drawn to
scale on page 413.
Metal Sheet Resistivity (/sq.) varies depending on metal Table 170, Conducting Film Thicknesses
level of interest and Sheet Resistances at 25C, on
page 417
P- Silicon Substrate Conductiv- 50-100 Bulk resistivity of P- wafers of 1-2 cm
ity (S/m)
P- Silicon Substrate Relativity 11.9 Property of intrinsic silicon bulk material
Permittivity (rsi)
Si02 Conductivity (S/m) 0.00 nonconductive
Si02 Relative Permittivity (rsi02) 4.10 See Table 177, Dielectric Constants, on
page 426
Si02 Dielectric Loss Tangent 0.00-0.001 Based upon comparison between simula-
tion and measurement. (typically set to
0.00).
Polyimide Passivation Layer 0.00 nonconductive
Conductivity (S/m)
Polyimide Passivation Layer 3.4 See Table 177, Dielectric Constants, on
Permittivity (poly) page 426

Capacitive Loading/Transmission Line Effects for Arbitrarily Shaped Interconnects IBM
Parameter Value Source
Polyimide Passivation Layer 0.00-0.001 Based upon comparison between simula-
Loss Tangent tion and measurement. (typically set to
0.00).
All Dielectrics Relative Perme- 1.00 No magnetic materials in technology cross

ability (r) section
All Dielectrics Magnetic Loss 0.00 N/A
Tangent
With the above information, simulations can be performed to characterize the characteristics of arbitrarily
shaped pieces of interconnect metallization. If care is taken in setting up the simulation (including a thorough
understanding of the limitations of your particular simulator), accurate results can be expected from any of the
planar e-m simulators on the market.

Shielded Transmission Line (T-line) Interconnect Models
4.38 Shielded Transmission Line (T-line) Interconnect Models

Shielded Transmission Line (T-line) interconnect models are offered in the current CMRF8SF release for
both LM and MA metal options.
Transmission lines are allowed to be placed over T3 isolation well.
4.38.1 Purpose
The offered interconnect models refer to a definite set of parametrized shielded interconnect structures,
which enable high predictability of T-lines behavior and allow to predict parasitics effects due to interconnect
on early (schematic) design phase. T-lines models enable users to design well controlled impedance
environment.
4.38.2 Supported Topologies

The current release includes models for the following (straight-wire) topologies:
single wire (singlewire) shielded transmission line, thereafter referred to as TL1 (see Figure 100 and
Figure 101)
two wires (coupledwires) shielded transmission line, thereafter referred to as TL2 (see Figure 102
and Figure 103).
single wire coplanar waveguide (singlecpw), thereafter referred to as CPW1 (see Figure 104)
two wires coplanar waveguide (coupledcpw), thereafter referred to as CPW2 (see Figure 105)
All models are symmetrical, as shown on Figures 100, 101, 102, 103, 104 and 105.
4.38.3 Transmission Line Models

The schematic level models can be used at schematic or higher level design phases, i.e. behavioral and
mixed mode.
All offered models are suitable for time domain simulations, including both periodic steady state and true
transient simulations, as well as frequency domain simulations.
The offered modeling approach does not depend on whether impedance matching is used or not.
The models offered in the current release support usage of the Spectre and HSPICE simulators.
The TL2 and CPW2 models are intended mainly for differential designs, but they can also be used in
non-differential designs in order to model the electric and magnetic crosstalk between adjacent lines.
The suggested stages of T-line models usage are as follows.
Based on the floor plan, critical lines are identified.
For each critical line, the T-line topology and metal layers are specified; length and width values are
estimated, based on possible floor plan constraints and impedance considerations.

Shielded Transmission Line (T-line) Interconnect Models IBM
The defined T-line models are simulated as part of a design.
After completing the layout, T-line geometrical parameters are updated if needed, for the sake of LVS.
Post-layout simulation procedure and detailed discussion of the proposed design flow can be found in the
user guide.
TL1 Model
The TL1 model consists of a metal signal line above a metallic return path, with optional side shielding. All
legal metal level combinations as signal and shielding layers are permitted. This structure is shown in Figure
100 and Figure 101.
th
th_g
Legend Wg
signal wire
shielding
Figure 100. TL1 with side shielding only: cross-section.
The single transmission line model is a passive ladder model. The inductance and the resistance per unit
length both depend on frequency due to skin and proximity effects. The resistance per unit length includes
the signal wire resistance and the resistance of the shielding return path, with their frequency dependence.
Dielectric losses in the oxide layer are negligible and are therefore neglected. The losses due to possible
currents in the silicon substrate are effectively eliminated by the use of the bottom shield layer.

W Ws
S th
th_g
Legend Wg
signal wire
shielding
via
Figure 101. TL1 with both bottom and side shielding: cross-section
TL2 Model
The TL2 structure is two identical metal signal lines above a metallic return path, with optional side shielding.
all legal metal level combinations as signal and shielding layers are permitted. This structure is given in
Figure 102 and Figure 103, on page 446.
The TL2 is a passive ladder model which includes capacitance, resistance, inductance, cross capacitance,
and mutual inductance per unit length of the two coupled signal lines with the common shielding return path.
The model of is frequency dependent, as specified below. The resistance per unit length includes only the
signal wire resistance without the shielding return path resistance. This condition is exact for odd mode
(differential) signals, and still serves as good approximation for other modes of signal propagation. Dielectric
losses in the oxide layer are negligible and are therefore neglected. The losses due to possible currents in
the silicon substrate are effectively screened by the use of the bottom shield layer.
The model describes accurately the full electric and magnetic crosstalk between the two signal lines, in all
modes of signal propagation across the lines (odd mode, even mode and single mode).

d th
th_g
Legend
Wg
signal wire
shielding
Figure 102. TL2 with bottom shielding only: cross section
W Ws
s
d th
th_g
Wg
Legend
signal wire
shielding
via
Figure 103. TL2 with both bottom and side shielding: cross-section

CPW1 Model
The CPW1 model consists of a metal signal line above a silicon substrate, with side shielding.
This structure is shown in Figure 74. The CPW1 device can be at any legal metal level.
W Ws
S th
Legend
signal wire
shielding
silicon substrate
Figure 104. CPW1 with side shielding: cross-section
The single wire coplanar waveguide model is a passive ladder model. The inductance and the resistance per
unit length both depend on frequency due to skin and proximity effects. The resistance per unit length
includes the signal wire resistance and the resistance of the shielding return path, with their frequency
dependence. Dielectric losses in the oxide layer are negligible and are therefore neglected. The losses due to
possible currents in the silicon substrate are incorporated into model.
CPW2 Model
The CPW2 structure is two identical metal signal lines above a silicon substrate, with side shielding. This
structure is given in Figure 105. The CPW2 device can be at any legal metal level.
4.38.4 Transmission Line Design Considerations

There are some limitations on geometry of a transmission line structures supported by interconnect
transmission line models. They are due to technology layout rules as well as model limitations itself. We
mention here just a few of them. For further details, please refer to section 3.8, CA, Metal and Via Layout in
this manual.

Table 194. Transmission Line Design Specifications: LM metal option
Specification Singlewire and Coupledwires

Supported Mx (x=2,3,4,5,6) Signal Line Widths (m) 0.20 and higher
Supported Mx (x=Q,G) Signal Line Widths (m) 0.40 and higher
Supported LM Signal Line Widths (m) 0.40 and higher
Supported Lengths (m) up to 1000
Table 195. Transmission Line Design Specifications: MA metal option
Specification Singlewire and Coupledwires

Supported Mx (x=2,3,4) Signal Line Widths (m) 0.20 and higher
Supported Mx (x=Q,G) Signal Line Widths (m) 0.40 and higher
Supported LY Signal Line Widths (m) 0.60 and higher
Supported E1 Signal Line Widths (m) 1.50 and higher
Supported MA Signal Line Widths (m) 4.0 and higher
Supported Lengths (m) up to 1000
Note: If lines longer than 1000m are required, it is recommended that they be broken into smaller pieces and
connected in series.
The distance between signal and side shielding in singlewire and singlecpw device layouts must be less
than 20m
The distance between signal and side shielding in coupledwire and coupledcpw device layouts must be
less than 20m
The distance between two signal lines in coupledwire and coupledcpw device layouts must be less than
20m
When transmission lines are in close proximity to each other it is recommended to limit the minimum dis-
tance between their bottom ground shields to the minimum spacing allowed by layout rules for that metal
level. However, the local pattern density rules on the Mx (x=2,3,4,5,6,Q,G) and LM metal levels must also
be met, which may require adjacent transmission lines to be spaced further apart.
Mx (x=2,3,4,5,6,Q,G) ground shield widths must be less than or equal to 50m.

E1ground shield widths must be less than or equal to 25m.

W Ws
s
d th
Legend
signal wire
shielding
Figure 105. CPW2 with side shielding: cross-section
The CPW2 is a passive ladder model which includes capacitance, resistance, inductance, cross
capacitance, and mutual inductance per unit length of the two coupled signal lines with the side shielding
return path.
The model of is frequency dependent, as specified below. The resistance per unit length includes only the
signal wire resistance without the shielding return path resistance. This condition is exact for odd mode
(differential) signals, and still serves as good approximation for other modes of signal propagation. Dielectric
losses in the oxide layer are negligible and are therefore neglected. The losses due to possible currents in
the silicon substrate are incorporated into model.
The model describes accurately the full electric and magnetic crosstalk between the two signal lines, in all
modes of signal propagation across the lines (odd mode, even mode and single mode).
4.38.5 T-line Ground Connections Notes

Proper AC grounding of the transmission line during simulation is critically important to achieving accurate
simulation results.
Grounding with low ground impedance connection at near T-line end is a must. Grounding with low
impedance connection at far T-line end is highly recommended.

Mixed Voltage Interfaces IBM
4.39 Mixed Voltage Interfaces

This section involves rules for mixed voltage interface (MVI) environments. The issues of interest are burn-in,
dynamic voltage screen, enhanced voltage screen, hot electrons, dielectric breakdown, latch-up, snap-back,
borderless CA and ESD protection.
The values for the thick oxide can be used for a rough estimate for Vmax (dielectric integrity) as func-
tion of POH, Tj and area.
4.39.1 Latchup
Latchup susceptibility must be verified for the maximum voltage applied to the product under any conditions,
including burn-in. For 2.5 V tolerant I/O, latchup testing should be evaluated for sensitivities above 2.5 V. For
1.2 V internal/ 2.5 V external two power-supply chips, latchup evaluations should be for voltages over 1.8 V.
Product testing should quantify latch-up sensitivity to power-up and power-down sequencing. In general, the
burn-in voltage is 1.5X operating voltage. Therefore, latchup evaluation should be done accordingly (for more
information on burn-in, please refer to section 5.3 Front End Of Line (FEOL) Reliability Design Rules on
page 461 and section 6.2 Latchup Guidelines and Layout Constraints on page 508).
4.39.2 Snap-back
The applied voltages must not exceed the sustaining voltage of the transistors in the circuitry. Overvoltages
can be avoided by using NFETs in a series configuration (stacked transistors). Layout of interdigitated
stacked NFETs may have a snap-back voltage lower than the sum of the two transistors.
4.39.3 ESD Protection

ESD protection circuits are provided for mixed voltage interface circuit applications. ESD rules for stacked
NFETs are provided in the ESD section. For mixed voltage applications, ESD networks are needed
between the different power supply rails. For 1.2/2.5 V two-power-supply chips, diode strings or self bias well
ESD networks should be used between power supplies. See section 7.0 , Electrostatic Discharge (ESD) on
page 523.
ESDIODE is not supported within T3 isolation well. Salicide block ESD nfets (thin ox, thick ox 2.5-V or 3.3-V)
are allowed to be placed over T3 isolation well.
4.39.4 Hot Carrier Effects

Regular, LVT, and LP FETs which are exposed to source to drain bias higher than 1.5 V under nominal, nor-
mal operating conditions must be longer than the minimum channel length in design dimension. Thick oxide
devices (Regular IO and ZVT thick NFET) which are exposed to source to drain bias higher than 2.5 V under
nominal, normal operating conditions must be longer than the minimum channel length in design dimension.
In addition, the circuits must be rigorously analyzed for all Hot Carrier stress types for all the devices.

4.39.5 Reliability Screening

The need for effective Burn-in and Reliability Screens places constraints on mixed voltage I/O design.
The following are additional design requirements for mixed voltage I/O circuit designs.
For chips with I/O power supplies in addition to the 1.2 volt supply, design the chip and or application such
that when Vdd is lost, the I/O power supply is also turned off. This is to prevent chip damage.
Have the I/O design such that it does not depend on the voltage differential between Vdd and the I/O sup-
ply in order to function during Burn-in and voltage screens.
Have the I/O design such that it does not draw DC power during Burn-in, DVS, EVS and IddQ testing.
4.39.6 Maximum Junction Reverse Voltage

The maximum steady state voltage allowed between any two terminals (gate, source, drain, and body) of a
FET can not exceed the Vddmax as specified in Table 119, Available FETs, on page 335 Exception: The max-
imum reverse-bias junction voltage allowed during steady state conditions is 3.6 volts only for the 5.2nm thick
oxide devices. Please refer to Section 5.2.1 , Burn-in on page 459 for more information.
4.39.7 Vmax and Vos for 2.2 nm Gate Dielectric

The CMRF8SF 2.2 nm gate dielectrics have been qualified for a maximum use voltage of 1.6 V, for a total
oxide area of 20 mm2, at a temperature of 125o C, a lifetime of 175 KPOH and a 100% duty factor. Further-
more, the maximum voltage is dependent on the application conditions and gate areas. For example, the
absolute maximum voltage across the gate oxide at the aforementioned application conditions and an area of
0.2mm2, is estimated to be 1.77 V for NFETs and 1.80 V for PFETs. Exceeding these maximum conditions
may result in severe device degradation and gate oxide failure. Aside from gate oxide dielectric integrity and
NBTI, other aspects to consider for applied voltages are described throughout Section 4.0 , Electrical
Parameters and Models on page 335.
The maximum allowed voltages across the gate dielectric are defined as follows.
Vmax: maximum allowed dc voltage without transients (overshoot or undershoot)

Vos: maximum allowed transient voltage when used with a maximum high level of Vh (Vh < Vmax)

Equations are provided below to calculate these maximum voltages as a function of lifetime (KPOH), maxi-
mum junction temperature (Tj ) and total gate area for each device type listed in Table 196, Maximum Voltage
Parameters on page 453. These equations are valid only for junction temperatures above 30o C. The values
at 30o C should be used for applications below 30o C.
1 A A A T 175
V = V ref + ---- ln --------------------------------------
max G KPOH D f
1 A A A T A V 175 ( KPOH D f ) + t os
V os = V h + ---- ln ------------------------------------------------------------------------------------------------------------
G t os
1
------
2 B
Area { mm }
AA = ----------------------------------
A ref

Ea Eb 2 1 2
A T = exp ------------------------------- ------------------------------------- ---------- + ------------------------------- ------------------------------------- ----------
1 1 1
5 273 + T { C } 398 5 273 + T { C } 398
8.62 10 j 8.62 10 j
t os = KPOH S f D os
A V = exp [ G ( V h V ref ) ]
The constants Vref , Aref, B, G, Ea and Eb are listed in Table 196, Maximum Voltage Parameters on
page 453, for each device type and the following definitions apply:
Df: Fraction of product lifetime with dielectric voltage at Vh or switching to Vh

Sf: Fraction of total cycles where,
- overshoot: a switch to Vh occurs
- undershoot: a switch to the low-level occur
Dos: Fraction of a switching cycle where voltage across the dielectric exceeds Vh
Table 196. Maximum Voltage Parameters
Device Vref Aref B G Ea Eb
NFET, 2.2 nm 1.77 0.2 1.42 15.87 2.324 -290.7
PFET, 2.2 nm 1.80 0.2 1.42 13.53 1.608 -167.6
NFET, 5.2 nm 3.60 0.2 3.69 7.5 0.42 0
PFET, 5.2 nm 3.60 0.2 2.78 7.3 0.42 0
Table 197, Sample Vmax Calculations 2.2 nm FETs with a gate area of 0.2 mm2 and a duty factor of 100%
on page 453, provides an example of Vmax calculations for 2.2 nm FET applications with a gate area of 0.2
mm2 and a duty factor of 100%. For evaluation of product-specific applications, please contact the IBM Tech-
nical Representative.
Table 197. Sample Vmax Calculations 2.2 nm FETs with a gate area of 0.2 mm2 and a duty factor of 100%
POH (hrs) Tj (oC) NFET PFET POH (hrs) Tj (oC) NFET PFET
175K 125 1.77 1.80 60K 125 1.84 1.88
175K 105 1.85 1.88 60K 105 1.92 1.97
175K 85 1.93 1.98 60K 85 2.00 2.06

Table 197. Sample Vmax Calculations 2.2 nm FETs with a gate area of 0.2 mm2 and a duty factor of 100%
175K 65 2.01 2.07 60K 65 2.08 2.15
100K 125 1.81 1.84 40K 125 1.87 1.91
100K 105 1.89 1.93 40K 105 1.95 2.00
100K 85 1.97 2.02 40K 85 2.03 2.08
100K 65 2.05 2.11 40K 65 2.10 2.18
4.39.8 VMAX and VGS for 5.2nm Gate Dielectric

The 5.2 nm gate oxides have been qualified for a maximum use voltage of 3.60 V at a temperature of 125o C,
a total oxide area of 0.4 mm2, a lifetime of 175 KPOH and a 100% duty factor. For these conditions, the abso-
lute maximum voltage is 3.6 V. Exceeding these maximum conditions may result in severe device degradation
and gate oxide failure. The maximum allowed gate dielectric voltages under specific application conditions
may be calculated using the equations from section 4.39.7 , Vmax and Vos for 2.2 nm Gate Dielectric on
page 451 and the parameters for 5.2 nm FETs in Table 196, Maximum Voltage Parameters on page 453.
4.39.9 VMAX for Single and Dual Nitride MIM Capacitor (for MA or OL
with LD Metallization Options)
The CMOS8RF (CMRF8SF) Single and Dual MIM capacitor maximum allowed operating voltage is deter-
mined from the following equation.
0.036
C0 t
V
max
= ---------------------------------------------------------------------------------------------------------------------------------------------------------------
6 1.111 0.177 2837.545
[ ln ( 1 10 PPM ) ] [A P ] exp -----------------------------
273.15 + T
where t is time in Khours, PPM is parts per million failure criterion, T is the temperature in degrees centigrade,
A is the area in square microns and P is the perimeter in microns. The value of C0 for the single and dual MIM
is 3.040 x 10-31 and 5.680 x 10-30 respectively. The tables below show the results of an example calculations
given the following operation criterion.
Single MIM
Time: 100KPOH, 60KPOR, 40KPOR, 20KPOR
Fail Criterion: 10 PPM

Temperature: 125oC, 115oC,105oC, 85oC, 65oC, 45oC, 30oC
Area: 2,000,000m2
Perimeter: 5657m
T(oC) Vmax Vmax Vmax Vmax

100 KPOH 60 KPOH 40 KPOH 20 KPOH
125 7.5 7.6 7.7 7.9

115 7.5 7.7 7.8 8.0
105 7.6 7.7 7.8 8.0
85 7.6 7.8 7.9 8.2
75 7.8 7.9 8.0 8.2
65 7.8 8.0 8.1 8.3
45 8.0 8.1 8.2 8.4
30 8.1 8.3 8.4 8.6
Dual MIM
Area: 2,000,000m2
Perimeter: 5657m

125 6.7 6.9 7.0 7.1

115 6.8 6.9 7.0 7.2
105 6.8 6.9 7.0 7.2
85 6.9 7.1 7.2 7.3
75 7.0 7.1 7.2 7.4
65 7.0 7.2 7.3 7.5
45 7.2 7.3 7.4 7.6
30 7.3 7.4 7.5 7.7

4.39.10 VMAX for Hi-K MIM (for OL with LD Metallization Option)
The maximum allowed operating voltage is determined from the following equations.
For VHK > VQK,
0.0254
35
9.30 10 t
V
max
= -------------------------------------------------------------------------------------------------------------------------------------------------------------
0.1788
-
6 2.5 9461.41
{ ln [ 1 10 PPM ] } [ A P ] exp -----------------------------
273.15 + T
For VHK < VQK,
0.0254
33
6.82 10 t
V
max
= -------------------------------------------------------------------------------------------------------------------------------------------------------------
0.1788
-
6 2.5 9461.41
{ ln [ 1 10 PPM ] } [ A P ] exp -----------------------------
273.15 + T
where t is time in K-hours, PPM (parts per million) is the failure criterion, T is the temperature in degrees cen-
tigrade, A is the area in square microns and P is the perimeter in microns. Below is an example calculation for
the specified operating conditions (VHK > VQK)

Area: 2,000,000m2
Perimeter: 1,000,000m

125 5.05 5.11 5.17 5.26

115 5.13 5.19 5.25 5.34
105 5.21 5.28 5.33 5.43
85 5.40 5.47 5.53 5.63
75 5.50 5.58 5.63 5.73
65 5.62 5.69 5.75 5.85


45 5.88 5.95 6.01 6.12

30 6.10 6.18 6.24 6.35

Reliability Design Rules and Models Guidelines for Optimal Reliability IBM
5.0 Reliability Design Rules and Models
5.1 Guidelines for Optimal Reliability

CAUTION! The following guidelines do not replace the need for a thorough study of all of the rules in this
manual. They are intended to provide a brief summary of design practices that will result in a more robust
final product.
Recommendations:
Stay below the specified limits of the power supply: Vdd = 1.6 V (maximum) for Tox=2.2 nm, Vdd = 2.7 V
(maximum) for regular I/O devices and Vdd = 3.6 V (maximum) for 3.3V I/O devices.
Use power supplies with tighter tolerances (for example less than or equal to 1.2 0.1 V, 1.5 0.1 V, 2.5
0.2 V, 3.3 0.3 V) when possible. Most reliability mechanisms are strongly voltage dependent.
Stay within the specified temperature range: -55 to 125 C
Use minimum layout dimensions only when necessary.
Use minimum device lengths only when necessary. Many reliability mechanisms are strongly length
dependent.
All circuits must be designed to be functional at the worst-case design burn-in conditions. The details of
this are described in section 5.2 , Reliability Screening on page 459.
Review wear-out mechanism ground rules
Hot Carriers
Critical circuits are those with highly loaded devices, high duty factors, critical matching, analog
function or bidirectional operation
minimize switching times and currents in circuits
Electromigration
Critical circuits are those with highly loaded devices or high duty factors
Contacts to polysilicon must occur over RX space (STI).
A chip guard ring must be provided around the entire chip.
Avoid large areas of thin oxide capacitors. These increase the likelihood of defect related chip failure.
DC standby current screens are an effective means of detecting defects. Chips should be designed with
minimal DC standby current. If DC current is required for a particular application, then that current should
be brought to a separate pad.
If device matching is a concern, place devices in close proximity with the same orientation. Allow for at
least the minimum expected mismatch specified under Threshold Voltage Stability.
Vertical interconnects are mechanical and electrical weak points. Maximize areas of vertical intercon-
nects by using as much contact and via stud area as possible and by overlapping contacts and vias with
as much metal as possible.

Reliability Design Rules and Models Reliability Screening
Any device uses not specifically allowed by this manual must be reviewed with Reliability Engineering.
5.2 Reliability Screening

There are four reliability screens which require designers attention. However not all systems require optimal
reliability and hence do not have to pass all four screens. The four screens are:
1. Dynamic Voltage Screen (DVS)
2. Enhanced Voltage Screen (EVS)
3. Supply current screen (Idd)
4. Burn-in (100% of production) screens of the final packaged product
Either the first three or the last one must be addressed to achieve minimum reliability confidence. For maxi-
mum reliability, all four screens need to be addressed.
5.2.1 Burn-in
All circuits must be designed to be functional at the worst-case design burn-in conditions. IBMs requirement
for burn-in conditions is 1.5X Vdd 0.125 V (1.8 0.125 V) and 140 C. Therefore, the following conditions
should be used to assess functionality at burn-in. Any deviation from these conditions must be discussed with
IBM.
Vdd = 1.925V for 1.2V circuits, 2.375V for 1.5V circuits, 3.875V for 2.5V circuits and 5.075V for 3.3V cir-
cuits
Temperature = 140 C
Lp = 0.092 m NFET, 0.215 m for DGNFET, 0.40um for XNFET
Lp = 0.092 m PFET, 0.215 m for DGPFET, 0.40um for XPFET
Tcyc = 200-500 ns
Trise,fall = 60 ns
Other variables are at nominal conditions
The standard devices in I/O circuits that drive and receive voltages higher than 1.2 V can NOT have more
than 1.925 V across its terminals during burn-in. The reverse-bias junction voltages (N+ to substrate, N-Well
to P+), however, can be as high as 3.6 V.The thick oxide devices in I/O circuits that drive and receive voltages
higher than 2.5V can NOT have more than 3.875 V across its terminals during burn-in.
Burn-in function at the indicated elevated conditions requires a robust voltage distribution (including N well
and substrate contacts) and patterns which avoid large amounts of simultaneous switching.
Temperature control becomes a problem if the ICs themselves supply too much heat compared to the oven.
Power dissipation over about 3 watts (average) may have to be corrected with special burn-in modes.

Reliability Design Rules and Models Reliability Screening IBM
5.2.2 Wafer Screening
DVS, EVS, and Idd screens are fully integrated as one test at wafer final test as a customer option. Support for
the wafer screening options must be negotiated with IBM through the IBM product engineer. Dynamic Voltage
Screen (DVS) stresses by writing with high pattern coverage at supply voltage =2.55 V (max, actual based on
product testing, see Section 4.39.7 , Vmax and Vos for 2.2 nm Gate Dielectric on page 451 and Section
4.39.8 , VMAX and VGS for 5.2nm Gate Dielectric on page 454). EVS bumps the supply voltage to 3.0 V
(max, actual based on product testing) at the completion of each DVS pattern. Supply current (Idd) is used as
the main indicator of DVS/EVS failure along with loss of functionality.
EVS is extremely effective with pre burn-in reliability shorting mode defects. The normally dominant shorting
mode is reduced to a minority compared to open mode. Additional defect reduction is afforded since highly
defective wafers can be identified and scrapped. In many cases EVS has been successfully substituted for
burn-in.
Design Practices for Wafer Screening
Adherence to the following ground rules for voltage screening is highly recommended. EVS does not restrict
channel length.
Static data integrity with Vdd/Inputs at 3.0 V (maximum target, actual based on product testing).
Dynamic functionality with Vdd/Inputs at 2.55 V (maximum target, actual based on product testing), Tcycle
= 200-1000 ns.
Experience has shown that products properly designed for the burn-in conditions above will meet the
static/dynamic requirements for EVS/DVS.
Supply low Idd states with good node toggle and without DC current. Every potential DC path from Vdd to
ground should be blocked by at least one NFET or PFET with Vgs=0. Supply True/Complement states for
embedded SRAM and all latches.
Pass gate circuitry design must satisfy this DC path blockage requirement e.g. be a pass gate feeding a
latch, fully complementary pass gate design, or have an NFET pass gate pullup (half latch).
Grounded PFET circuitry design must also be DC free. For example there should be a test pin to undo
grounding of PFETs and an extra NFET pull down with gate tied to the same test pin. so that with the test
pin high, the PFET is OFF and the NFET ties the potentially floating node to ground.
The layout design and/or test design of MUX circuitry must be free of DC paths and floating nodes (inde-
terminate states).
Input and I/O circuitry must be designed such that input highs can be received without DC paths at no
more than Vdd volts during EVS where Vdd is projected at 3.0 V.
As with burn-in, DVS requires functionality at accelerated conditions of voltage and temperature. This func-
tionality needs to be verified by whoever is responsible for wafer test on the earliest available hardware. With
products becoming ever more complex, the conditions for this early assessment needs to be discussed with
Reliability Engineering.

Reliability Design Rules and Models Front End Of Line (FEOL) Reliability Design Rules
5.3 Front End Of Line (FEOL) Reliability Design Rules
5.3.1 Hot Carrier Effects

--NOTE-- Hot electron degradation can have a significant impact on circuit performance and functionality. It is
imperative that circuit designers carefully review their designs for hot electron degradation. Cumulative degra-
dation and process variation must be taken into account for both burn-in and field operation.
The burn-in conditions to use for simulations to assess functionality are determined from the worst case of the
following:
Case 1
1. VDD = 1.925V (2.375V for 1.5V supply, 3.875 V for 2.5V supply, 5.075V for 3.3V supply)
2. Temperature = 140o C
3. Lp = 0.092 m for NFET and PFET (0.215 m for DG devices, 0.40um for 3.3V I/O devices)
4. Duration = nominal burn in duration for your product; 200ns cycle time
5. Other variables are at nominal
Case 2
1. VDD=1.80 V (2.25V for 1.5V supply, 3.75 V for 2.5 supply, 4.95V for 3.3V supply)
2. Temperature = 140o C
4. Duration = nominal burn-in duration for your product; 200 ns cycle time
5. Other variables are at nominal
Case 3
1. VDD = 1.80V (2.25V for 1.5V supply, 3.75 V for 2.5 supply, 4.95V for 3.3V supply)
2. Temperature = 140 C
4. Duration = worst case duration for product; 200 ns cycle time
5. Other variables are at nominal with process variation (ACLV, Vt etc.) included
The field operating conditions:

1. VDD = VDDmax for your application
2. Temperature = lowest operating temperature for your application
4. Appropriate lifetime and duty cycle
5. Other variables are at nominal with process variation
For these cases there should be no significant loss of functionality of the product. For any product requiring
performance sorting at product test guardbands may be needed.
Minimum Lp typically produces the largest hot carrier shifts but may not be the most sensitive condition for cir-

Reliability Design Rules and Models Front End Of Line (FEOL) Reliability Design Rules IBM
cuit operation and performance. For example, chips with longer Lp that just meet time zero performance tar-
gets may degrade less than minimum Lp chips. With little or no performance margin, these chips are more
likely to fail during life than chips with shorter Lp, large degradation and large time zero performance margin.
Mechanism
Hot carriers are holes or electrons which have been accelerated to a high energy by local electric fields. If
such a carrier has kinetic energy in excess of the silicon-insulator barrier height, it may surmount the barrier
and enter the insulator. Once in the insulator, the electron or hole may become trapped. High energy carriers
can also produce interface states. The accumulation of trapped charge causes a shift in the Vt (threshold volt-
age) of the device and the accumulation of interface states can reduce device drain current, degrade sub-
threshold slope and increase device leakage.
Hot carriers are categorized into two types dependent on the origin of the carrier. These are CHC (Channel
Hot Carriers) and SHC (Substrate Hot Carriers). Channel hot carriers are broken down further into Conduct-
ing (Gate Voltage > Threshold Voltage) and Non-Conducting (Gate Voltage ~ 0).
Conducting Hot Carriers: Thin Oxide (2.2 nm) N-channel Devices

The NFET channel hot carrier effect is dominated by the generation of interface states. Significant degrada-
tion occurs when the gate voltage is above VT , and VDS is large. The device degradation is characterized by
both a threshold voltage increase and a reduction in device drain current over time. The device damage is
localized near the drain, resulting in an asymmetry in the post stress device characteristics.
The following is a model of the conducting NFET channel hot carrier effect. The model is derived at peak sub-
strate current (VGS ~ VDS/2). This is the maximum degradation point for Leffs larger than nominal. For Leffs
less than nominal, VGS= VDS is the worst DC case. However, in actual use the degradation will peak near VGS
~ VDS/2 even for low Leff since the dependence of the degradation on vGS is not very strong for low Leff and
at VGS=VDS, vDS normally will be significantly lower. This model does not include saturation effects, which
tend to reduce the degradation above 50 %. For Wdesign<1 um, or for temperatures above 30 C, corrections
must be applied as indicated.
Degradation Equation:
The degradation is given in percent by:
I D V 0
--------- = A L eff exp ------------ t eq
m n
ID V DD
in units of m, volts, and seconds. The time teq is defined below. The parameters A, m, V0 and n are given in
Table 198, NFET Hot Carrier Conducting Model Common Parameters Tox=2.2nm and Table 199, NFET
Hot Carrier Conducting Model A Parameter.

Table 198. NFET Hot Carrier Conducting Model Common Parameters

Tox=2.2nm
Use Mode m V0 n
Forward Saturation -3.31 29.1 .44

Reverse Saturation -3.31 29.1 .44
Table 199. NFET Hot Carrier Conducting Model A Parameter
Use Mode Mean Worst Case (+3)
Forward Saturation 68.5 110.0

Reverse Saturation 120.0 209.0
Time Calculations: Hot carrier effects occur in NFET devices when vDS is close to VDD and appreciable iD
is flowing. For typical CMOS circuits, these conditions occur only during switching transients. In this case,
equivalent stress time can be approximated by,
f sw
t eq = D --------- t use
f cl
where,
fsw = average switching freq (CYCLES/sec)
fcl = clock frequency
tuse = actual use time in sec and,
D = 0.003 for short vDS transition times ( < 0.05 x tcyc, 10-90%)
0.010 for moderate vDS transition times ( 0.05 to 0.15 x tcyc, 10-90%)
0.03 for long vDS transition times ( 0.15 to 0.30 x tcyc, 10-90%)
Another way of estimating teq is the total time spent between the following two waveform events: vGS reaching
VT, and vDS falling to VDD/(1+(VDD/2V0)).
Care must be taken when operating devices with persistent drain currents. In these cases, vDS must be kept
low, or associated circuits designed to tolerate significant degradations.
Narrow Device Correction: For device design widths of less than one m, the calculated degradation should
be multiplied by 1.75x
High Temperature Correction: For junction temperatures above 30 C, the calculated degradation does not
require correction.
Device Characteristics: The observed effect of hot carrier injection on an NFET device is dependent on the
measurement conditions applied after stress. Reverse mode refers to the situation where a device is mea-
sured with its source and drain connections reversed relative to those during stress. Thus, the reverse satura-

tion degradation is important when a device is used bidirectionally, as in a pass gate. Observed ID
degradation as a function of VGS increases as VGS decreases (down to VT). The net effect over the whole
VGS range (above VT) can be approximated by a simultaneous current multiplier (given by a dependent cur-
rent source), and an effective VT shift (given by a voltage source). The current source Jdeg is in parallel but
opposite direction to the Jds source in the device model (so as to lower the effective drain current), and the
voltage source Vdeg is in series with the gate, opposing the turn-on of the device (that is, negative towards
the gate.) The values of Jdeg and Vdeg are given by:

J deg = C ------------- J DS
1 +
V deg = B
where,
= ION/ION, expressed as a fraction, and the parameters C and B are given by:
Table 200. NFET Hot Carrier Degraded Model

Parameters
Device C B (V)
2.2nm Tox NFET 0.44 0.35

5.2nm Tox NFET 0.63 0.87
Note: Do not confuse Vdeg with the actual threshold shift, which is larger than Vdeg.
Example: A 2.2nm NFET in an inverter circuit is operated for 100,000 hour with switching transient of moder-
ate transition times once every 10 ns clock cycle. VDD = 1.5 v, and minimum Leff = 0.06 um. teq = 0.01 x
(50 MHz/100 MHz) x 3.6E8 sec = 1.8E6 sec. Using the model parameters for forward saturation yields a
Drain current degradation of 2.06% ( WC A=60.2) for the NFET. Jdeg=0.009*Jds, Vdeg=7mV.
Specific Device Concerns: The following are some specific NFET uses that must be examined in detail.
Burn-in conditions
Bidirectional devices - stressing a device in both directions is more severe than 2X the stress time in one
direction
D.C. current flow
Heavily loaded circuits such as Off-chip Drivers (OCDs) and Clock Drivers
Circuits such as OCDs which may see voltage overshoots or undershoots
Mixed voltage interface circuits or any circuit using greater than 1.95 V.

Circuits with long rise and/or fall times such as OCDs

Circuits where VT or ID matching is critical
Transconductance (Gm)
The degradation is given by (in percent):
G m V 0
------------- = A L eff exp ------------ t eq
m n
Gm V DD
The degradation was measured at VDS = 1.2V and VGS = 0.6V.

The following values apply to forward saturation:
A = 14 (nominal)
A = 21 (worst case, 3-sigma)
m = -2.9
Vo = 22.6
n = 0.45
Conductance (Gds)
The degradation is given by (in percent):
G ds V 0
-------------- = A exp ------------ t eq
n
G ds V DD
The above degradation is worst case for devices up to 0.24um design channel length, and above this value,
the degradation is negligible.
A = 3.34 x 10-4 (worst case)

Vo = 26.6
n = 0.48
Conducting Hot Carriers: Regular I/O Thick Oxide (DG, 5.2 nm) N-channel Devices
The DGNFET channel hot carrier effect is dominated by the generation of interface states. Significant degra-
dation occurs when the gate voltage is above VT , and VDS is large. The device degradation is characterized
by both a threshold voltage increase and a reduction in device drain current over time. The device damage is
localized near the drain, resulting in an asymmetry in the post stress device characteristics.
The following is a model of the conducting DGNFET channel hot carrier effect. The model is derived at peak
substrate current (VGS ~ VDS/2). This is the maximum degradation point.This model does not include satura-
tion effects, which tend to reduce the degradation above 50 %. These models are preliminary.

I D V 0
--------- = A L eff exp ------------ t eq
m n
ID V DD
Table 201, NFET Hot Carrier Conducting Model Common Parameters Tox=5.2nm and Table 202, NFET
Hot Carrier Conducting Model A Parameter.
Table 201. NFET Hot Carrier Conducting Model Common Parameters

Tox=5.2nm
Use Mode m V0 n
Forward Saturation -2.64 41 .48

Reverse Saturation -1.94 41 .48
Table 202. NFET Hot Carrier Conducting Model A Parameter
Forward Saturation 260 494

Reverse Saturation 1660 3154
Time Calculations: Hot carrier effects occur in NFET devices when vDS is close to VDD and appreciable iD
is flowing. For typical CMOS circuits, these conditions occur only during switching transients. In this case,
equivalent stress time can be approximated by,
f sw
t eq = D --------- t use
f cl
where,
D = 0.003 for short vDS transition times ( < 0.05 x tcyc, 10-90%)
0.010 for moderate vDS transition times ( 0.05 to 0.15 x tcyc, 10-90%)
0.03 for long vDS transition times ( 0.15 to 0.30 x tcyc, 10-90%)
Another way of estimating teq is the total time spent between the following two waveform events: VGS reaching
VT, and VDS falling to VDD/(1+(VDD/2V0)).
Care must be taken when operating devices with persistent drain currents. In these cases, vDS must be kept

Narrow Device Correction: For device design widths of less than one m, the calculated degradation should
be multiplied by 1.25x
.
High Temperature Correction: For junction temperatures above 30 C, the calculated degradation does not
require correction.
degradation is more severe than the average for VGS near VT and less severe for VGS near VDD. The
increase in inverse average drain current approximates the increase in the delay (rising vGS to falling vDS).
Example: An inverter circuit is operated for 50,000 hour with switching transient of longer transition times
once
every 10 ns clock cycle. VDD = 2.5v, and Leff = 0.17 um. teq = 0.03 x (50 MHz/100 MHz) x 1.8E8 sec =
2.7E6 sec. Using the model parameters for forward saturation yields a Drain current degradation =4.9 %
(A=494 WC).
Specific Device Concerns: The following are some specific NFET uses that must be examined in detail.
When Vds > 2.75 It is recommended to use stacked devices and/or longer channels
Burn-in conditions
direction
D.C. current flow
Conducting Hot Carriers: Thick Oxide 3.3V I/O N-channel Devices

The 3.3V I/O NFET channel hot carrier effect is dominated by the generation of interface states. Significant
degradation occurs when the gate voltage is above VT , and vDS is large. The device degradation is charac-
terized by both a threshold voltage increase and a reduction in device drain current over time. The device
damage is localized near the drain, resulting in an asymmetry in the post stress device characteristics.
The following is a model of the conducting 3.3V I/O NFET channel hot carrier effect. The model is derived at
peak substrate current (VGS ~ VDS/2). This is the maximum degradation point. These models are preliminary.

I D V 0
--------- = A L eff exp ------------ t eq
m n
ID V DD
in units of m, volts, and seconds. The time teq is the lifetime in sec with a duty cycle of 1%. Id is defined by
Vds=vdd/2, Vgs=Vth+200mV.
The parameters A, m, V0, L0, and n are given in Table 203, NFET Hot Carrier Conducting Model for 3.3V I/O
nFET operation.
Table 203. NFET Hot Carrier Conducting Model for 3.3V I/O nFET operation
Use Mode m V0 n
Forward -3.5 40 0.49

Linear -2.35 40 0.49
Table 204. 3.3V I/O NFET Hot Carrier Conducting Model A Parameter
Forward Saturation 7.3 12

Linear 135 257
Example: A 3.3V I/O NFET device in an inverter circuit is operated for 50,000 hour with switching transient of
longer transition times once
every 10 ns clock cycle. VDD = 3.3V, and Leff = 0.40 um, teq = 0.03 x (50 MHz/100 MHz) x 1.8E8 sec =
2.7E6 sec. Using the model parameters for forward saturation yields a Drain current degradation =2.29 %
(worst case, A equals 12).

Non-conducting hot carriers: Thin Oxide (2.2 nm) N-channel Devices

The non-conducting stress mode is one in which VGS = 0 and VDS is large. NFET devices in which significant
subthreshold or punchthrough current flows can exhibit hot carrier effects. The physical mechanism is similar
to the conducting NFET and is found in short channel length devices at elevated voltages and temperatures,
especially under burn-in conditions.
I D ( b Vd ) V 0
exp ---------- ( I off t eq )
n
--------- = A L eff VD
ID
in units of m, volts, second, Ioff in nA/m at stress condition (such as burn-in).
The parameters A, V0, b and n are given in Table 205, NFET Hot Carrier Non-conducting Model Parame-
ters.
Table 205. NFET Hot Carrier Non-conducting Model Parameters
Use Mode A (mean) A (2 WC) b V0 n
Forward Saturation 72 288 -7.86 46.6 0.54

Reverse Saturation 180 720 -7.86 46.6 0.54
Narrow Device Correction: For device design widths of less than one m, the multiplier 1.75x should be
applied
increase in inverse average drain current approximates the increase in the delay (rising vGS to falling vDS ).
Example: A logic part is burned-in for 10 hours at 140 C with VD=1.8 V. What is the worst case current degra-
dation for a (normal VT) device used unidirectionally? For minimum Leff = 0.075 um, Ioff = 80nA/um; assume
100% duty cycle worst case, t=36,000 sec. Using the model parameters for forward saturation yields a Id/Id
= 0.41% for the NFETs.
Non-conducting hot carriers: Regular I/O Thick Oxide (DG, 52A) and Thick Oxide
3.3V I/O N-channel Devices
The non-conducting stress mode is one in which vGS = 0 and vDS is large. NFET devices in which significant
subthreshold or punchthrough current flows can exhibit hot carrier effects. The physical mechanism is similar
to the conducting NFET and is found in short channel length devices at elevated voltages and temperatures,

especially under burn-in conditions. The degradation in I D is projected to be less than 1 % for a 48 hr burn-in
at T = 140 C, and Vdd = 3.8 V.
( b Vd ) V 0
exp ---------- ( I off t eq )
n
Y = A L eff
VD
SAT Y
I D = ------------------------
SAT + Y
in units of um, volts, second, Ioff in nA/m at stress condition (such as burn-in), Y in [%], SAT is a parameter
to account for saturation effects.
The parameters A, V0, b and n are given in Table 206, DG NFET Hot Carrier Non-conducting Model Param-
eters.
Table 206. DG NFET Hot Carrier Non-conducting Model Parameters
Use Mode A (mean) A (2 WC) b V0 n SAT
Forward Saturation 530 954 -5.1 50 0.50 15

Reverse Saturation 3000 4590 -4.6 50 0.45 22
Narrow Device Correction: For device design widths of less than one m, the multiplier 1.25x should be
applied
increase in inverse average drain current approximates the increase in the delay (rising vGS to falling vDS ).
Conducting hot carriers: Thin Oxide (2.2 nm) P-channel Devices

The PFET channel hot carrier effect is due to a mixture of interface state generation and charge trapping,
and is more complex than NFET behavior. Significant degradation occurs when the gate voltage is between
VT and VDS, and VDS is large. The device degradation is characterized by both a threshold voltage increase
and a reduction in device drain current over time. The device damage is localized near the drain, resulting in
an asymmetry in the post stress device characteristics.
The following is a model of the conducting PFET channel hot carrier effect. The model is derived at (VGS ~
VDS). This is the maximum degradation point for all Leffs. However, in actual use the degradation will peak

somewhat below vGS ~ vDS, making the effective duty cycle (or teq / tuse ) less than that for NFETs, as seen
below in the time calculation section. This model does not include saturation effects, which tend to reduce the
degradation above 50 %. This equation covers all use temperatures and design widths.
I D V 0
--------- = A L eff exp ------------ t eq
m n
ID V DD
Table 207, PFET Hot Carrier Conducting Model Common Parameters Tox=2.2 nm and Table 208, PFET
Hot Carrier Conducting Model A Parameter for Tox=2.2nm.
Table 207. PFET Hot Carrier Conducting Model Common Parameters Tox=2.2
nm
Use Mode m V0 n
Forward Saturation - 3.14 20.3 .305

Table 208. PFET Hot Carrier Conducting Model A Parameter for Tox=2.2nm

Time Calculations: Hot carrier effects occur in PFET devices when VDS is close to VDD and appreciable ID is
flowing. For typical CMOS circuits, these conditions occur only during switching transients. In this case, equiv-
alent stress time can be approximated by,
f sw
t eq = D --------- t use
f cl
where,
D= 0.001 for short VGS and VDS transition times ( < 0.05 x tcyc, 10-90%)
0.005 for moderate VGS or VDS transition times ( 0.05 to 0.15 x tcyc, 10-90%)
0.05 for long VGS or VDS transition times ( 0.15 to 0.30 x tcyc, 10-90%)
Another way of estimating teq is the total time spent between the following two waveform events: VGS reach-
ing VT, and |VDS| falling to VDD/(1+(VDD/V0)), times the factor exp 2.0(VDD-1-|VDSCO|-1), where VDSCO is the
voltage at which VDS crosses VGS.

Care must be taken when operating devices with persistent drain currents. In these cases, VDS must be kept
High Temperature Correction: For junction temperatures other than 30 C, the calculated degradation does
not require correction.
Device Characteristics: The observed effect of hot carrier injection on an PFET device is dependent on the
degradation as a function of VGS increases as VGS decreases (down to VT). The net effect over the whole
VGS range (above VT) can be approximated by a simultaneous current multiplier (given by a dependent cur-
rent source), and an effective VT shift (given by a voltage source). The current source Jdeg is in parallel but
opposite direction to the Jds source in the device model (so as to lower the effective drain current), and the
voltage source Vdeg is in series with the gate, opposing the turn-on of the device (that is, negative towards
the gate.) The values of Jdeg and Vdeg are given by:

J deg = C ------------- J DS
1 +
V deg = B
where,
= ION/ION, expressed as a fraction, and the parameters C and B are given by:
Table 209. PFET Hot Carrier Degraded Model

Parameters
Device C B (V)
2.2nm Tox NFET 0.37 0.35

5.2nm Tox NFET 0.55 0.72
Note: Do not confuse Vdeg with the actual threshold shift, which is larger than Vdeg.
Example: A 2.2nm Tox PFET in an inverter circuit is operated for 100,000 hour with switching transient of
moderate transition times once every 10 ns clock cycle. VDD = 1.5 V, and minimum Leff = 0.08 um. teq =
0.005 x (50 MHz/100 MHz) x 3.6E8 sec = 900,000 sec. Using the model parameters for forward saturation
yields a Drain current degradation= 0.77% (A=3.2 WC) for the PFET. Jdeg=0.003*Jds, Vdeg=2.5mV.
Specific Device Concerns: The following are some specific PFET uses that must be examined in detail.

Burn-in conditions
direction
D.C. current flow
Conducting hot carriers: Regular I/O Thick Oxide (DG, 5.2 nm) P-channel Devices
The DGPFET channel hot carrier effect is due to a mixture of interface state generation and charge trapping,
and is more complex than NFET behavior. Significant degradation occurs when the gate voltage is between
VT and VDS, and VDS is large. The device degradation is characterized by both a threshold voltage increase
and a reduction in device drain current over time. The device damage is localized near the drain, resulting in
an asymmetry in the post stress device characteristics.
The following is a model of the conducting DGPFET channel hot carrier effect. The model is derived at (VGS ~
VDS). This is the maximum degradation point for all Leffs. However, in actual use the degradation will peak
somewhat below VGS ~ VDS, making the effective duty cycle (or teq / tuse ) less than that for NFETs, as seen
below in the time calculation section. This model does not include saturation effects, which tend to reduce the
degradation above 50 %. These models are preliminary.
I D V 0
--------- = A L eff exp ------------ t eq
m n
ID V DD
Table 210, PFET Hot Carrier Conducting Model Common Parameters Tox=5.2nm and Table 211, PFET Hot
Carrier Conducting Model A Parameter for Tox=5.2nm.
Table 210. PFET Hot Carrier Conducting Model Common Parameters

Tox=5.2nm
Use Mode m V0 n
Forward Saturation -3.56 46.2 .45


Table 211. PFET Hot Carrier Conducting Model A Parameter for Tox=5.2nm
Forward Saturation 64.5 190

Reverse Saturation 85.5 252
Time Calculations: Hot carrier effects occur in PFET devices when vDS is close to VDD and appreciable iD is
flowing. For typical CMOS circuits, these conditions occur only during switching transients. In this case, equiv-
alent stress time can be approximated by,
f sw
t eq = D --------- t use
f cl
where,
B = 0.001 for short vGS and vDS transition times ( < 0.05 x tcyc, 10-90%)
0.005 for moderate vGS or vDS transition times ( 0.05 to 0.15 x tcyc, 10-90%)
0.05 for long vGS or vDS transition times ( 0.15 to 0.30 x tcyc, 10-90%)
Another way of estimating teq is the total time spent between the following two waveform events: VGS reach-
ing VT, and |VDS| falling to VDD/(1+(VDD/V0)), times the factor exp 2.0(VDD-1-|VDSCO|-1), where VDSCO is the
voltage at which VDS crosses VGS.
Care must be taken when operating devices with persistent drain currents. In these cases, VDS must be kept
High Temperature Correction: For junction temperatures other than 30 C, the calculated degradation does not
require correction.
Device Characteristics: The observed effect of hot carrier injection on an PFET device is dependent on the
increase in inverse average drain current approximates the increase in the delay (falling |VGS| to rising |VDS|).
Example: An inverter circuit is operated for 50,000 hour with switching transient of longer transition times
once every 10 ns clock cycle. VDD = 2.5 V, and Leff = 0.17 um, teq = 0.05 x (50 MHz/100 MHz) x 1.8E8 sec
= 4.5E6 sec. Using the model parameters for forward saturation yields a Drain current degradation = 0.48%
(worst case, A equals 94.6) for the DGPFET.
Specific Device Concerns: The following are some specific PFET uses that must be examined in detail.
When VDS > 2.75 It is recommended to use stacked devices and/or longer channels
Burn-in conditions

Bidirectional devices - stressing a device in both directions is more severe than 2x the stress time in one
direction
D.C. current flow
Devices operated with substantial n-well bias.
Conducting Hot Carriers: Thick oxide 3.3V I/O P-channel Devices

The 3.3V I/O PFET channel hot carrier effect is dominated by the generation of interface states and charge
trapping. Significant degradation occurs when the gate voltage is above VT , and vDS is large. Electron trap-
ping occurs when Vgs~Vds/5 and lead to an increase in drain current. However, for long stress times the
drain current tends to decrease. resulting in a low net drift. Hole trapping occurs at Vg~Vd leading to a
decrease of the drain current. Although hole trapping is more severe at high temperatures, electron trapping
leads to higher drift at very low temperatures. The device damage is localized near the drain, resulting in an
asymmetry in the post stress device characteristics.
I D V 0
--------- = A L eff exp ------------ t eq
m n
ID V DD
in units of m, volts, and seconds. The time teq is the lifetime in sec with a duty cycle of 1%. Id is defined by
Vds=vdd/2, Vgs=Vth+200mV.
The parameters A, m, V0, L0, and n are given in Table 212, 3.3V I/O PFET Hot Carrier Conducting Model.
Table 212. 3.3V I/O PFET Hot Carrier Conducting Model
Use Mode m V0 n
Forward Saturation -3.35 30 0.36

Reverse saturation -3.24 30 0.36

Table 213. PFET Hot Carrier Conducting Model A Parameter

Example: A 3.3V I/O PFET device in an inverter circuit is operated for 50,000 hour with switching transient of
longer transition times once every 10 ns clock cycle. VDD = 3.3V, and Leff = 0.40 um, teq = 0.03 x (50
MHz/100 MHz) x 1.8E8 sec = 2.7E6 sec. Using the model parameters for forward saturation yields a Drain
current degradation =0.7 % (worst case, A equals 1.4).
Non-conducting hot carriers: Thin Oxide P-channel Devices

No significant shifts during the high voltage and high temperature stresses are expected.
Non-conducting hot carriers: Regular I/O Thick Oxide (DG) and Thick Oxide 3.3V I/O
P-channel Devices
The Vt of DGPFETs under this condition decreases (a current increase) due to electron trapping effects.For a
wide device (W>5 um, each finger), the shift in I D is projected to be less than 1 % for a 48 hr burn-in at T =
140 C, and Vdd = 3.8 V. For a narrow device, the shift can be larger, for example, for W = 0.5 um, a shift as
high as 2-3% is possible. This current increase will tend to decay with use operation, and the conducting deg-
radation mechanism will dominate.
5.3.2 Gate Oxide Dielectric Integrity

Gate dielectric integrity is mainly driven by random process defects. Therefore, reliability failure rates will
depend on the total gate oxide area. To reduce the impact of reliability fails caused by these defects, the fol-
lowing rules need to be observed. The more RECOMMENDED rules one follows, the lower the impact of
gate oxide defects on overall chip reliability.
For maximum oxide voltages Vmax in I/O design, see section 4.39 , Mixed Voltage Interfaces on page 450.
Below is a list of two general categories of capacitors and the reliability rules that need to be applied.
Decoupling Capacitors
N-well to substrate capacitors are preferred for use as decoupling Vdd and ground
An alternative nFET-in-nwell design, described in section 4.19 , NCAP and DGNCAP Models on
page 389 has been qualified as well.

Capacitors used in leakage sensitive analog circuitry. (ex. Phase Locked Loop)
Large area thin oxide capacitors MUST be designed by connecting small area (230 m2 maximum for
polysilicon) plates in parallel. However, it is RECOMMENDED that 45 m2 plates be used instead.
(See Design Rules 132 and 132R)
All polysilicon gates (FETs and capacitors) MUST meet groundrules 130, 131 and 132.
It is RECOMMENDED that circuitry be implemented to allow voltage screen capability at wafer final
test to reduce reliability impact during life.
To minimize the contribution of gate to diffusion related failures, capacitors MUST be designed to
minimize gate to diffusion perimeter. (i.e. place polysilicon edges over isolation oxide where possi-
ble.)
Avoid large areas of thin oxide capacitors. These increase the likelihood of defect related chip failure.
A thin oxide capacitor device in the CMRF8SF technology is the PCDCAP (this device is also referred
to as ncap or nFET-in-N-Well MOS Capacitor).
Guidelines:
To assure that decoupling capacitors have a negligible effect on reliability and yield, it is recom-
mended that:
1. Total Active Area with decoupling capacitors / Total active area without decoupling capacitors
1.02
2. If a design requires more decoupling capacitors, the failure rate will scale approximately with
the ratio given above. For example: 100 K m2 total, including decoupling capacitors, divided
by 90 K m2 results in a failure rate that is 11% higher than if no decoupling capacitors are
used.
For the purpose of these guidelines, the following definitions apply:
Decoupling capacitor
- Any thin dielectric (oxide, nitride, or oxynitride) capacitor connected between a power supply
and ground for the purpose of noise reduction. These may be implemented as MIM capaci-
tors, or CMOS devices that are wired as capacitors (source and drain connected together as
one electrode and the gate as the other electrode).
Active Area
- Total gate area of CMOS transistors + Total capacitor area + (if present in the technology)
junction diodes.
5.3.3 Forward Bias Injection Threshold Shifts (FITS)

FITS refers to the trapping of carriers injected from forward biased junctions. Individual device degradation
due to FITS is highly layout dependent. Use of circuits which result in forward biased junctions is not recom-
mended because of FITS, Hot Carrier, and Latchup concerns.

5.3.4 Threshold Voltage Stability
Substrate Hot Carriers

The Substrate Hot Carrier mechanism refers to the device degradation that occurs as a result of thermally
generated carriers in the depletion regions of reverse biased junctions. These carriers can be injected into the
gate oxide of a device resulting in threshold voltage shifts.No significant shifts during the high voltage and
high temperature stresses have been measured.
Ionic
The presence of ionic contaminants in MOS devices introduces parametric instabilities. The threshold voltage
shifts caused by these mechanisms are listed in the following table. No ionic shifts have been observed to
date in this technology. The following table for the 5.2 nm devices is based on theoretical line control capabil-
ities. For the thin oxide (2.2 nm) shifts smaller than 1 mV are expected at end of life.
This table represents the maximum total shifts expected due to Substrate Hot Carriers and Ionic Contamina-
tion. Non-Ionic shifts for PFETs are not included and must be treated independently. All circuits must be
designed to tolerate the combined maximum shifts of all mechanisms.
Table 214. End-of-Life Vt Shifts (100,000 Power-on Hours)
Device Type Max Vt Shift Max Vt Mismatch
Adjacent Non-adjacent
5.2nm NFET -35/ +15 mV 15 mV 35 mV
5.2nm PFET -35/+35 mV 15 mV 35 mV
Non-Ionic (NBTI)
The PFET device exhibits an increase in non-mobile positive charge during symmetric (source=drain) stress
which is named Negative Bias Temperature Instability (NBTI). This shift results in larger magnitude threshold
voltages over time (|ID| decreases).
Thin oxide pFET devices with gate oxides in the 1.6-2.3 nm range
Nominal case is given by:
500xZ
V T (millivolts) = -------------------------
( 500 + Z )
Worst case is given by:

500xZ
V T (millivolts) = 1.6 -------------------------
( 500 + Z )
Where:
V g 2.976 0.202
Z = 1312.5 exp ------------------ ----------
0.199
1 + ---------------
0.188 0.117
t Vt0
k T j t ox W D
NBTI is more pronounced in narrow device smaller 1 um. The design width (WD) dependence is explicitly
given in the expression above. Designer are required to simulate their circuits under these conditions.
Regular I/O DG 52A pFET devices with gate oxides in the 4.6-5.3nm range
Nominal case is given by
600xZ
V T (millivolts) = -------------------------
( 600 + Z )
Worst case is given by

600xZ
V T (millivolts) = 1.6x -------------------------
( 600 + Z )
Where:
0.183 V g 2.744 0.253
Z = 1048 exp ------------------ ---------- 1 + ---------------
0.072
t
k T j t ox WD
with
WD = device width in micrometers

Vg = gate to source stress bias in volts
Tox = gate dielectric thickness (nm)
Tj = stress temperature in Kelvin
t = time in seconds
k = Boltzmanns constant (8.62E-5 eV/K)
Vto = Threshold voltage (at 70nA x W/L) at stress temperature.
Based on combined worst case conditions, all circuits must be designed to tolerate these maximum predicted
shifts.
Example: A logic part is burned-in for 5 hours at 140 C. What is the worst case threshold shift for a 5.2 nm
PFET with W = 2.0m Worst case |VGS| = 3.3V, t=18,000 sec. Using the model parameters yields a VT =
33.7 mV.

For 3.3V I/O pFET devices
Drift equation is given by
exp ------- exp ( 1.08Vg )

0.3 Ea
V T (millivolts) = 21.2 t
kT
with Ea=0.24 eV, T in Kelvin, t in sec, k the Boltzmann constant, Vg=gate to well voltage.
This equation is valid only for device lengths and width L>3xLnom and W>3xWnom respectively. Narrow
devices must not be used for threshold voltage sensitive applications.
Table 215, Analog PFET DVt provides a guideline for maximum expected Vt shifts as a function Tempera-
ture and Voltage, and a duty factor of 100%.
Table 215. Analog PFET Vt
POH [hours] Vdd [V] T0 [C] Vt [mV]

87K 2.5V 85 45
87K 2.5V 125 110
87K 3.3V 85 110
87K 3.3V 125 250
Corrections to the above DC Models:

The above models are developed under the conditions: constant DC gate bias and VDS = 0V. Under typical
ac conditions (for digital applications) in which the gate bias will switch off at least 10% of the time, a factor of
0.6 can be applied to these dc models (multiply by 0.6).
If the device is in saturation while the gate bias is applied (such as in an analog application), and LDES 2x
Lmin, then a factor of 0.5 may be applied.
Note: Analog modes such as power down, that apply high gate bias and no drain bias, will realize 100% of
the dc model predictions.
5.3.5 Using Device Degradation Data

The threshold voltage shifts and current degradations presented in this section are not all directly additive.
The ultimate threshold voltage or drain current is determined as follows:
NFET VT at End of Life (EOL) = VT(t0) + VT (stability)
NFET or PFET ID at EOL = ID (t0) x (1 - ID)

PFET VT at EOL = VT (t0) + VT (stability) + VT (hot carriers)
Degradation for different VD bias conditions (at a given stress mode: for instance, peak substrate current, or
peak gate current) in equations that are not linear in time cannot be added linearly. The Hot Carrier and
Non-Ionic Stability mechanisms fall into this category. In order to calculate total degradation for more than one
stress condition within a given stress mechanism, the user must linearize the degradation for each condition
by raising it to the 1/n power where n is the exponent in the time term (assuming all stress conditions have
the same n). These linearized degradations can then be added and the result converted back to a final degra-
dation by raising to the nth power. This is summarized below:
tot = ( 11 n + 21 n + 31 n ) n
VT (Stability) is additive. Use VT (Ionic) plus VT (Non- Ionic).
PFET degradations from Negative Bias Temperature Instability and Hot Carrier mechanisms are directly
additive. (Apply the threshold shift AND the current degradation.)
To add NFET degradations from non-conducting and conducting mechanisms, use the following approxima-
tion:
tot = ( NC
2 + 2 )1 / 2
C
For bidirectional stress, however, the degradations from forward and reverse stresses should be directly
added.
5.3.6 Soft Error Rate
The radiation induced soft error rate for all SRAM cells ( 4K bits) MUST be modeled by computer simulation
to estimate the fail rate, and thus the system impact. In this section, all dimensions are actual wafer dimen-
sion.
A soft error on a memory element occurs when a transient current spike flips a bit without physically damag-
ing the chip. Memory elements which are known to experience soft errors include SRAM cells, DRAM cells,
and some dynamic logic circuits. These errors typically result in a system error or crash, program error, or
loss of data integrity. Soft errors result from naturally occurring ionizing radiation, including alpha particles
from the radioactive decay of heavy elements and by-products of collisions between cosmic rays and silicon
nuclei.
The following table includes preliminary estimates of the Soft Error Rate (SER) for a particular CMOS8RF
(CMRF8SF) SRAM cell. By definition 1 FIT=1 x 10-9 failures per hour.

Table 216. Example of Modeled C4 alpha SER and Cosmic SER
2.48 um2 SRAM Cell Cosmic C4 (125 on 225) Package Factor

(1 alpha/cm2/Khr)
1.2 V 550 FIT/Mb 4000 FIT/Mb 2000 FIT/Mb
1.5 V 400 FIT/Mb 2000 FIT/Mb 1400 FIT/Mb
The largest alpha particle source on many logic chips is the lead-tin solder used to make C4 solder balls.
Lead 210, which can not be practically separated from the other lead isotopes, decays through 210Bi into
210Po. 210Po then decays with the emission of a 5.3 MeV alpha particle into 206Pb. Alpha particles interact
with the silicon atomic lattice, losing energy with the creation of electron-hole pairs at the rate of 3.6 eV/pair
(44fC/MeV). Linear charge densities approach 15fC/m along the alpha track, much of which is collected in
100 picoseconds. Low alpha lead may be available to minimize alpha SER to approximately one tenth the
rate.
Some ceramic substrates emit alpha particles, but in most products these alphas are stopped before they
reach active devices in the silicon with clean fillers (like epoxy) used between the chip and the substrate.
Most wirebond package materials have low alpha emissions. For most wirebond products, the alpha SER is
insignificant relative to the cosmic ray-induced SER.
The alpha induced SER is expressed as FIT per C4 over the array of SRAM cells. The SER is calculated
assuming a 4 mil C4, with epoxy used between the chip and the ceramic substrate. Chips with a 50% popu-
lated 4 mil C4 on a 9 mil pitch with the above cell sizes will have about 14 kbit per C4. If there are 5 C4s over
an array of Cell7.0 cells on a chip with 4LM (4 Level Metal), the C4 SER component would be 5 C4s x 585
FIT/C4 = 2925 FIT. The C4 induced SER is very sensitive to the charge in the storage node (Qcrit). A 10%
decrease in Qcrit (i.e. drop in voltage) will increase the C4 SER of Cell7.0 by approximately 50%. For this cell,
approximately 0.1% of the C4 induced soft errors are multiple bit fails.
The sensitivity to cell design results from the high sensitivity of C4 SER on Qcrit. SER can drop more than
100X with a small change in cell area. C4 SER is more sensitive to design than cell area. This complex
dependence on cell design explains why the SER needs to be modeled for each cell design. If the C4 alpha
SER is less than the cosmic SER there would be little advantage in removing C4s from over an array.
The alpha SER is increasing with each new technology. With smaller cell designs, fewer alphas hit the cell
area, but more of them cause fails. The charge produced by the alpha has not changed appreciably because
the vertical profiles have not been changed appreciably as the dimensions and operating voltages decrease.
Meanwhile, the capacitance and voltage on the SRAM node are decreasing, leading to a decreasing critical
charge required to flip the cell. The trend of increasing C4 alpha SER needs to be taken into account for
designs planning to migrate into future technologies.
Additional levels of wiring increase the amount of material between the C4 and the silicon. This reduces the
number of alphas reaching the silicon. When a filler is used between C4s (like epoxy), the alphas emitted
from the side of the C4 are harmlessly absorbed by the filler. Any sensitive circuits which are more than 30m
from the edge of the C4 (30m from the C4 ball, not the 47m TV window) will not be affected by the alpha
emitted from that C4. Thus, if alpha sensitive circuits are not placed under or near C4s, they will not suffer an
increased level of SER (above the background cosmic SER level).

Other logic circuits (especially dynamic logic and latches) may also be susceptible to C4 induced soft errors.
As a rough guide, circuits which can withstand 30fC of charge injected in a 50ps pulse (approx 5ps linear rise
time, exponential decay with a time constant of 40ps) are probably not susceptible to C4 induced SER.
Cosmic rays reach the surface of the earth in the form of high energy protons and neutrons. These particles
occasionally collide with silicon nuclei, producing alpha particles and heavier energetic nuclei. The heavier
nuclei behave similar to alphas, except they can produce up to 10 times the charge density produced by
alphas. Thus, circuits which are immune to alphas may still be sensitive to cosmic radiation. Shielding of cos-
mic radiation is not practical. Many dense cell designs have a cosmic SER of around 1FIT/kbit = 1 fails/1E12
bit hours = 1ppm/(kbit-kpoh). Cosmic ray induced SER is relatively insensitive to Qcrit. Evidence of the exist-
ence of cosmic ray induced SER was obtained by comparing soft fail rates of parts at high altitudes, sea level
and underground (T. OGorman, IEEE Trans. ED, Vol 41, No 4, p. 553).
Logic circuits may also be susceptible to cosmic ray induced soft errors. As a rough guide, circuits which can
withstand 200fC of charge injected in a 50ps pulse (approx 5ps linear rise time, exponential decay with a time
constant of 40ps) are probably not susceptible to terrestrial cosmic rays.
Many suppliers do not include cosmic ray induced soft errors in their SER estimates. Cosmic SER estimates
and sensitivities can not be determined from accelerated alpha particle testing.
Maximizing the critical charge required to flip the state of a node reduces the SER. The critical charge
required to flip the state of SRAM cells is determined by the operating voltage, the capacitance of the internal
nodes, and the current drive of the PFET in 6 device cells (4 NFET/2 PFET). Unit capacitance increases in
low voltage technologies (thinner oxides, narrower depletion widths) tend to offset the impact of lower operat-
ing voltage on Qcrit. In 6 device cells, the charge collected by the NFET diffusions accounts for the majority of
soft errors. This occurs because the NFET diffusions are larger than the PFET diffusions and the PFETs pro-
vide less current drive to maintain the node voltage. Wider PFETs reduce SER by increasing the current drive
which restores hits on the NFET diffusions and increasing node capacitance without significantly increasing
charge collection. Maximizing gate capacitance tied to a storage node will reduce the SER. Error recovery cir-
cuits can also be very effective for reducing SER. Arrays with error detection or recovery should be designed
such that bits in the same error check word are physically separated to minimize the impact of multi-bit SER
events. Parity detection may be used to protect data integrity.
5.3.7 Resistor Reliability
Front-End of Line Resistors

P+ polysilicon and RP Polysilicon resistors are limited to 0.4mA/m unless further limited by metal electromi-
gration as described below, under the assumption that the metal line is the same temperature as the resistor.
Resistors can heat up to a point where metal migration becomes an issue. Tabulated guidelines assume that
the resistors are laid out with the metal leading to the resistor as wide as the resistor. This is for DC conditions
for 100,000 hours of operation at the silicon temperature indicated.

P+ Polysilicon Resistor current limitations:
Table 217. P+ Poly Resistor current limitations
SiTemp C 3.6V 5.5V
125 0.31 mA/m 0.30 mA/m
120 0.37 mA/m 0.35 mA/m
115 0.40 mA/m 0.39 mA/m
110 0.40 mA/m 0.40 mA/m
RR Polysilicon Resistor current limitations:
With the allowed current density of 0.1mA/m and 1700 /, the maximum heat generated by the RR resis-
tor will be less than 5 degrees C.
RP Polysilicon Resistor current limitations:

Table 218. RP Polysilicon Resistor current limitations
SiTemp C 3.6V 5.5V
125 0.34 mA/m 0.33 mA/m
120 0.39 mA/m 0.38 mA/m
115 0.40 mA/m 0.40 mA/m
For P+ poly and RP polysilicon resistors, electromigration may be evaluated for specific cases by calculating
the temperature rise for the resistor and using the electromigration limits from the Back-End-Of-Line reliability
section under the assumption that the metal line is the same temperature as the resistor. AC operation can
have a much relaxed criteria but 0.40 mA/m absolute maximum should be maintained.
The formula for thermal resistance (THERMRES) is:
THERMRES = 144150 AREA2 0.87121
where,
AREA2 = (AREA + 5 x WIDTH)
AREA is the area of the resistor (m2)
WIDTH is the resistor width (m)
The Resistor temperature (ResTemp) is then:
ResTemp = SiTemp + ( THERMRE S Power )
where, SiTEMP is the base silicon temperature (degrees C) and Power is the dissipated power in the resistor
(Watts)

Back-End-Of-Line K2, K3, K4, K5, or K6 Resistors

Caution: Kx resistors, where x = 2,3,4,5 or 6, can produce high temperatures that can compromise integrity
of metal lines leading up to the resistor as well as metal lines adjacent to the resistor. Adjacent resistors can
heat each other compromising the resistor precision.
The maximum allowed current through any Kx resistor is 0.5mA/m of width unless the metal leading to the
resistor limits the current to a lower value or the change in resistance through life is more than the circuit can
tolerate.
Table 219. TaN Resistor maximum current limits any aspect ratio in ma/um of width
Si Temp C K2 K3 K4 K5 K6
90C 0.50 0.50 0.50 0.50 0.48
100C 0.50 0.50 0.48 0.45 0.43
110C 0.47 0.43 0.41 0.39 0.37
120C 0.38 0.35 0.33 0.32 0.30
125C 0.33 0.31 0.30 0.28 0.27
Some layouts can tolerate higher current densities (all must be less than 0.5mA/m). If the initial layout does
not meet the critical current density above then the following calculations can be done.
Calculate thermal resistance ThR
K2: ThR= 9.0878x105 x Area-0.93574
K3: ThR=8.669x105 x Area-0.88999
K4: ThR=7.0119x105 x Area-0.84326
K5:ThR=6.3921x105x Area-0.81166
K6: ThR=4.3178x105 x Area-0.7654
Where Area is the area of the resistor in microns squared. ThR is in Degrees C/Watt. The power in the resis-
tor should be calculated, then knowing the resistor area, the temperature increase of the resistor can be cal-
culated. By adding the resistor temperature increase to the Base Silicon temperature the temperature of the
resistor (and connecting metal) is then determined. The electromigration limitations for that temperature can
be calculated from section 5.4.2. Using the equations in Section 5.4.2 , Structures of Concern: ILCs and
Line Rules on page 491 trade-offs for duty cycle can also be made.
Metal lines or other resistors within 10m of the heated resistor will see 40% of the increase in temperature
caused by the heated resistor. Metal lines or resistors at 30um away will see a temperature rise of 20% of the
increase in temperature. Metal lines within these distances need to be designed wide enough to tolerate the
higher temperatures. The metal lines above or below the Kx resistor must be designed to tolerate the same
temperature as the heated resistor itself. Resistors requiring high precision should be kept far apart (>40m)
such that heating from adjacent resistors do not influence the high precision resistor value.

Back-End-Of-Line L1 Resistor:
Caution: L1 resistors can produce high temperatures that can compromise integrity of metal lines leading up
to the resistor as well as metal lines adjacent to the resistor. Adjacent resistors can heat each other compro-
mising the resistor precision.
Restrictions:
1. The maximum allowed current through any L1 resistor is 0.5 mA/m unless the MA metal line leading up
to the resistor limits the current to a lower value or the change in resistance through life is more than the
circuit can tolerate.
- Front-End-Of-Line (FEOL) or Back-End-Of-Line (BEOL) structures (for example; metal lines or active
devices) are NOT allowed over or under a L1 resistor, or within 10m from the edge of a L1 resistor,
whenever a L1 resistor is used with currents in the range of 0.10mA/m through 0.5mA/m (maxi-
mum) in a chip design.
The L1TEMP25 dummy design and utility level is not allowed to cover a L1 Resistor with currents
in the range of 0.10mA/m through 0.5mA/m (maximum) in a chip design.
The 10m FEOL and BEOL exclusion zone around the perimeter of a L1 Resistor, with a current
in the range of 0.10mA/m through 0.5mA/m, is not checked in the Design-Rule-Checking
(DRC) tool. The DRC tool defaults to a 45m checking criteria when the L1TEMP25 dummy
design and utility level is not present over a L1 Resistor.
Any FEOL and BEOL structures or wires placed between 10-45um from the perimeter of a L1
Resistor, with a current in the range of 0.10mA/m through 0.5mA/m, the temperature of these
structures or wires must be assessed as defined in this entire section on L1 Resistors.
An IBM Waiver will be required for any L1 Resistor currents that exceed 0.1mA/m or if struc-
tures are placed closer than 45m to a L1 Resistor with a current that exceeds 0.1mA/m.
For more information on L1 resistors, see section Additional Information on L1 Resistors on

page 487.
For additional information on L1TEMP25, see Table 6, Dummy Design Levels and Utility Levels,
on page 46 and Table 71, L1 RESISTOR Layout Rules, on page 222 and 4.18 Resistor Mod-
els on page 378.
2. In a chip design, the dummy design level L1TEMP25 can be used for L1 resistors that have a maximum
allowed current of less than or equal to 0.1mA/m.
- When the L1TEMP25 dummy design level is used in a chip design, the L1 resistor layout rules that
are checked in the Design-Rule-Checking (DRC) tool default to the least restrictive layout criteria.
- For more information on L1 resistors, see Additional Information on L1 Resistors on page 487.
For additional information on L1TEMP25, see Table 6, Dummy Design Levels and Utility Levels,
on page 46 and Table 71, L1 RESISTOR Layout Rules, on page 222 and 4.18 Resistor Mod-
els on page 378.

Additional Information on L1 Resistors

Note: This information applies to all L1 Resistors
L1 resistor minimum width and maximum widths are defined by Rules L11 and L11a, respectively (See
Table 71, on page 222).
E1 metal is not allowed under L1 resistors (See Rule L14 in Table 71, on page 222).
The metal line leading up to the resistor must be the greater than or equal to the width of the resistor (See
Rule L16 in Table 71, on page 222).
The L1TEMP25 dummy design and utility level must not overlap past the L1 resistor by greater than
45m unless adjacent L1TEMP25 shapes overlap each other (See Rule L19c in Table 71, on page 222).
The current allowed in the metal line leading up to the resistor is limited to:
For MA Aluminum metal)
Iallowed= (5.63 x (MetalWidth -0.27) x(exp ((5461/(273+TEMP))-14.64)) (in ma)
where TEMP is the temperature (Deg C) of the resistor and can be calculated as given below.
ResWidth is the width of the resistor in microns.
TEMP = TempSub + (((Current / 1000) 2 ) x (60 x Length / Width)) x300517 x ((Length x

Width)-0.5664)
Where Current is resistor current in ma
Length and Width are the length and width of the resistor in microns
TempSub is the Silicon substrate temperature in Deg C.
Temperature Considerations:
When the resistor is operating at high temperature, adjacent metal line integrity can also be compro-
mised.
1. With the line 10m away from the resistor, the allowed current in an adjacent MA line is:
TEMP10 = TempSub + 0.4x (((Current / 1000) 2 ) x (60 x Length / Width)) x 300517 x ((Length x
Width)-0.5664)
Iallowed10= (5.63 x ( MetalWidth-0.27)) x (exp ((5461/(273+TEMP10))-14.64) in ma
Where TEMP10 is the temperature of the metal line 10um away from the TaN resistor.
MetalWidth is the metal width of a MA metal line in microns.
Iallowed10 is the allowed current (ma) in a metal line 10um away from the resistor
2. With the line 30m away from the resistor the allowed current in an adjacent MA line is:

TEMP30 = TempSub +0.2x (((Current / 1000) 2 ) x (60 x Length / Width)) x 300517 x ((Length x
Width)-0.5664)
Iallowed30= (5.63 x ( MetalWidth-0.27)) x(exp ((5461/(273+TEMP30))-14.62)) in ma
Where TEMP30 is the temperature of the metal line 30um away from the TaN resistor.
MetalWidth is the metal width of a MA metal line in microns.
Iallowed30 is the allowed current (ma) in a metal line 30um away from the resistor.
3. For Cu and Al lines below and adjacent to the L1 Resistor, the following current limits should be
observed.
For a line 10m or 30m away the TEMP10 and TEMP30 can be calculated as above.
The formulae are from the design manual.
For E1:
Iallowed10=(16.02 x (MetalWidth-0.21) x (exp (9495/(273+TEMP10)) -25.45) (in mA)
I allowed30 is calculated in a similar fashion using TEMP30
For LY:
For MQ, MG
Iallowed30 is calculated in a similar fashion using TEMP30
For M2, M3, M4:
For M1:
Note: Standard short-line and power-on-hour adjustments can also be made. See the
BEOL reliability section of the design manual.
Adjacent resistors
- Due to the spread in temperature surrounding resistors adjacent resistors will tend to heat each

Reliability Design Rules and Models Back End Of Line (BEOL) Reliability Design Rules
other.
- Adjacent resistors operated at high current density (when the L1 resistor current density is greater
than > 0.1 ma/m of width) must be placed at least 30m away from each other.
Any metal lines placed between 30m spaced resistors will reach approximately the same temperature
as the resistors and the metal current density will need to be derated based on the temperature of the
resistors. The temperature of the resistors can be calculated as above. See the BEOL reliability section
for current derating as a function of temperature.
Resistor Shift
- The resistor itself will also shift as a function of temperature and time.
- Present data indicates the shift (increase) will be:
Percent Shift = 4.835E-9 x (exp (0.033105 x TEMP)) x ( ln 1000 x Time)4.1
Worst case is 3x the above value.
Where TEMP is the temperature (Deg C) of the resistor calculated from above
Time (hours) is the number of power on hours in that condition.
Example: A resistor at 135C for 100,000 hrs will change 0.065% (worst case 0.19%)
Notes:
1. Please contact IBM reliability engineering for L1 Resistor operation above 125oC or beyond 100,000
hour, or other special operating points.
2. The impact of Burn-In in lifetime is not included. Please contact IBM reliability engineering if the product
will be burned in.
3. The expressions above are valid for resistor width < 30 um and length <120 um.
4. A Spread sheet calculator will be available for designers to determine maximum current and resistance
change as a function of time, temperature, resistor size etc.
5.4 Back End Of Line (BEOL) Reliability Design Rules
5.4.1 Electromigration (EM)
Introduction
Electromigration refers to the gradual degradation of interconnects due to the combined effects of current and
temperature. The following rules give designers the information needed to assure that electromigration will
have a negligible impact on the reliability of CMOS8RF (CMRF8SF) designs.
The rules do not address protection of circuits against extraordinary current/temperature situations like elec-
trostatic discharge, electrical overloads, or latch up.

Reliability Design Rules and Models Back End Of Line (BEOL) Reliability Design Rules IBM
Design Analysis Strategy
Electromigration is analyzed by dividing interconnect networks into simplified elements: metal lines of a given
width, contacts and vias which serve as interlevel connections to lines. It is a duty of the designer to make
sure that the electromigration rules are followed for all elements of the design.
Designers should include the following activities in their design methodology:

Use the Electromigration rule adjustments (EM Rule Adjustments on page 495) to determine the
current limits for the circuit application being considered.
Use the capacitive load of the circuit and the operating frequency to calculate the currents expected
in the metal lines for comparison to the current limits.This simple check can be performed for each
circuit node capacitance listed in the chip timing simulations.
Use a circuit simulator to calculate the currents in the metal interconnects where an EM problem is
suspected or where greater accuracy is required. Particular attention should be paid to the follow-
ing cases (this is NOT an exhaustive list):
Off chip drivers, which may have to drive very large loads
Power buses. Check for hot spot where demands for current from several circuits may accu-
mulate along the length of a bus line
Any circuit where a DC current is present.
Because the EM rules are generic, they contain imbedded assumptions which might be overly conservative
for particular designs. Thus, in addition to general adjustments of the rules based on different applications, a
limited number of exceptions which allow marginal violation of the rules may be allowed in particular design
circumstances.
Application Assumptions and Rule Adjustments

The rules as listed are based on an assumed product life of 100,000 hours and an assumed junction tem-
perature of 100C. Adjustment factors for other life times and temperatures are given. When applications are
more stringent, the adjustment factors must be applied. When applications are less stringent, adjustment fac-
tors should be used only when it is absolutely certain that the designs will never be used at more stringent
conditions.
Terminology and Symbol Definitions

Contact (CA): stud connection from M1 to diffusion and polysilicon.
Via: connection between any 2 metal levels (M1 and above).
Interlevel Connection (ILC): general term for a contact or via
Fully Bordered ILC: ILC designed with enough metal bordering to assure full line/ILC intersection even
when maximum allowed line/ILC misalignment occurs.
Operating Switching Time (tsw): minimum time between successive current switching operations.
Current Operating Frequency (fsw): 1/ tsw
Switching Factor (s): fraction of operating cycles over the life of the product during which a given circuit
switches.

s
0
t sw
Equivalent Average DC Current (Idc): --------- i ( t ) dt Note that for the case of pure ac current,
t sw
Idc is zero. For pure ac applications, the maximum current is defined by the Irms limit.
0
t sw 2
RMS Current (Irms): sf sw i (t)dt
nLM: n levels of metal technology, where n is an integer (e.g., 3LM is a 3 level metal technology).
LM: planarized last metal.
5.4.2 Structures of Concern: ILCs and Line Rules

In general, the structural elements of concern are at or near interlevel connections (ILCs) to lines. The physi-
cal dimensions of importance are the cross sectional area of the line and the situation of the ILC with respect
to the end of the line. There is a significant penalty in allowed use current for the case of ILCs designed
using minimum design rules. These limits are outlined in the following sections. In the future there
may be a demonstrable benefit for ILCs designed with a full metal border or a metal extension as part
of robust design practice.
EM Fail Types and Corresponding Currents

Rules are given to protect against two types of current-induced fails: standard EM and local-heating
enhanced EM.
For standard EM, the rules define a maximum Idc.
For local-heating enhanced EM, the rules define a maximum Irms.
The values of any calculated Idc or Irms in any simplified elements of an interconnection network must not
exceed the values given in the tables.
Equivalent dc Average Current Translations into Capacitances

For the typical CMOS situation where circuits are used to charge and discharge capacitances, the following
I dc
formula may be used to translate Idc limits into capacitance limits: C max = ------------------------------
s f sw V
I rms
For the case of pure ac current: C max = ------------------------------
s f sw V
General Rules at 100C/100K POH

The following current limit values are subject to revision when additional qualification data has become avail-
able.
Table 220, Current Limits at 100C on page492 provides the maximum allowed I dc and Irms for each of the
wiring levels. Note that no Idc limit is stated for PC since it is not believed that standard EM is a concern for
these levels. Exceptions to these rules are listed in section , Exceptions to General Rules for Vias on
page 494. The general rules apply for all cases which are not listed in the exceptions tables.

In case of narrow stripes where a single via or contact is permitted along the width, the general rules can be
applied by using the maximum number of contacts or vias along the line length. The general rules can be
applied for cases of wide lines, provided the maximum number of contacts or vias allowed along the width are
used. For a wide line crossing over a wide line, the general rules can be applied by using the maximum num-
ber of contacts or vias to create an L shaped array (See Figure 106). Additional redundant vias are recom-
mended for use, where possible, subject to the constraints in section Q.2, Recommended Design Practices
Related to Generated FILL and HOLES Shapes on page 575.
Wide Line
Narrow Line
Required
Recommended
Wide Line
Figure 106. Recommended Via Placement for Wide Lines
Table 220. Current Limits at 100C
Metal Level Idc (mA)1 Irms (mA) Idc (mA) Irms2

min. W (mA)
min. W
4.54
N/A 0.61 ( W 0.015 ) 3.77 + -------------------------------- N/A 0.44
PC3 ( W 0.015 )
3.53
M1 2.80(W-0.06) 7.52 ( W 0.06 ) 1.19 + ----------------------------- 0.28 4.54
( W 0.06 )


min. W (mA)
min. W
3.05
M2 3.12(W-0.06) 7.90 ( W 0.06 ) 0.68 + ----------------------------- 0.44 5.24
( W 0.06 )
2.74
M3 3.12(W-0.06) 7.90 ( W 0.06 ) 0.46 + ----------------------------- 0.44 4.94
( W 0.06 )
2.53
M4 3.12(W-0.06) 7.90 ( W 0.06 ) 0.35 + ----------------------------- 0.44 4.74
( W 0.06 )
2.37
M5, 3.12(W-0.06) 7.90 ( W 0.06 ) 0.29 + ----------------------------- 0.44 4.59
( W 0.06 )
2.24
M6 3.12(W-0.06) 7.90 ( W 0.06 ) 0.24 + ----------------------------- 0.44 4.46
( W 0.06 )
2.59
MG 5.4(W-0.07) 10.35 ( W 0.06 ) 0.32 + ----------------------------- 1.78 8.86
( W 0.06 )
MQ4
LM 2.34
5.4(W-0.07) 10.35 ( W 0.06 ) 0.23 + ----------------------------- 1.78 8.72
( W 0.06 )
LY 2.06
0.52(W-0.13) 7.25 ( W 0.13 ) 0.15 + ----------------------------- 0.24 7.27
( W 0.13 )
E1 2.21
16.02(W-0.21) 24.18 ( W 0.21 ) 0.09 + ----------------------------- 20.66 41.88
( W 0.21 )
MA5 1.98
5.63(W-0.27) 20.94 ( W 0.27 ) 0.05 + ----------------------------- 20.99 59.52
( W 0.27 )
2.56
OL 32.58(W-0.19) 24.18 ( W 0.19 ) 0.15 + ----------------------------- 33.1 40.0
( W 0.19 )
2.31
LD 5.7(W-0.30) 20.94 ( W 0.30 ) 0.09 + ----------------------------- 9.69 42.8
( W 0.30 )


min. W (mA)
min. W
AM 1.98
5.63(W-0.27) 20.94 ( W 0.27 ) 0.05 + ----------------------------- 9.74 39.65
( W 0.27 )
1. W = design width. These numbers do not include the effects of Metal HOLE shapes. For wires wider than six times the minimum,
the linewidth W must be replaced by the Corrected Linewidth Wc, as calculated from Table 171, Corrected Linewidth for Wires
with HOLE Shapes, on page 419. For Wide lines, the Idc must not exceed the calculated Irms.
2. The Irms values are intended to control Joule heating caused by the current. Heating will be more severe for lines with greater underlying
thickness of dielectric between the line and the substrate. Irms values given are for the worst case dielectric thickness, and therefore
apply to all builds.
3. Limits apply to silicided polysilicon. For OP resistors, the current limits are identified in Table 140, Resistor Design Specifications, on
page 379 as also referenced in Section 5.3.7 , Resistor Reliability on page 483.
4. For Kx BEOL resistors, the current limits are identified in Section , Back-End-Of-Line K2, K3, K4, K5, or K6 Resistors on page 485 or
Table 140, Resistor Design Specifications, on page 379.
5. For L1 BEOL resistors, the current limits are identified in Section , Back-End-Of-Line L1 Resistor: on page 486 or Table 140, Resistor
Design Specifications, on page 379.
Exceptions to General Rules for Vias

The following tables describe the exceptions to the general rules for vias. The allowable limit for the dc and
rms current per via is given in Table 221. For multiple vias the allowed dc and rms currents are given by the
allowable current per via times the number of vias. For the case of stacked vias or any other configuration of
lines and vias, the current flowing through any single via may not exceed the values listed in Table 221. The
current limit for the line rule given in Table 220, Current Limits at 100Con page 492, must not be exceeded
for any case.
Table 221. Exceptions to General Idc and Irms Current Limits for Contacts and Vias at 100C
Level Idc Max Limit Irms Max Limit per Via (mA)
per Via (mA)
CA, V1 1.40 5.00
V2,V3,V4,V5 1.68 7.85
VL 3.56 13.37
VQ, VG 6.10 16.43
JT 25.5 39.2
JTBAR1, 5.4(L+1.93) 2.17

10.35 ( L + 1.93 ) 0.18 + --------------------------
( L + 1.93 )

Table 221. Exceptions to General Idc and Irms Current Limits for Contacts and Vias at 100C
Level Idc Max Limit Irms Max Limit per Via (mA)
per Via (mA)
VV 67.0 131.7
VVBAR 1, 5.7(L+1.75) 2.31

20.94 ( L + 1.75 ) 0.09 + ---------------------
L + 1.75
FY 2.80 28.50
FT 2.49 21.00
FTBAR 1 0.52(L+1.87) 2.06

7.25 ( L + 1.87 ) 0.15 + --------------------------
( L + 1.87 )
F12 3.6 53.55
F13 29.41 53.55

(with redundancy)
F1BAR 1,4 3.0 x L 1.98

20.94 ( L + 2.73 ) 0.05 + --------------------------
( L + 2.73 )
F1BAR5 5.63(L+2.73) 1.98

20.94 ( L + 2.73 ) 0.05 + --------------------------
(with redundancy) ( L + 2.73 )
FQ 0.63 5.25
1. L = Length of Via bar
2. Without redundant F1 vias. A waiver is required for Rule MAF1p in Table 54, F1 and F1BAR Layout Rules,
on page 171 to attain the reduced Idc Maximum Limit per Via listed. Contact your IBM Technical
Representative for more information.
3. With redundant F1 vias. Redundant vias are required per Rule MAF1p in Table 54, F1 and F1BAR Layout
Rules, on page 171.
4. Without redundant F1BAR vias. Redundant F1BAR via bars is not required.
5. With redundant F1BAR via bars. Use of redundant F1BAR via bars is a Recommended Design Rule. See
Rule MAF1qR in Table 54, F1 and F1BAR Layout Rules, on page 171.
EM Rule Adjustments
The Idc limits in the preceding tables may be adjusted for cases of isolated lines, product life times other than
100,000 hours, and junction temperature limits different from 100C as indicated in the following tables.
Notes:
1. Note that no adjustment for the local-heating EM (Irms) is allowed

2. Insure that the adjusted Idc current(s) in this section do not exceed the Irms current values given in
Table 220, Current Limits at 100C, on page 492 for the corresponding line widths.
Table 222. Adjustment Factors for I(dc) only, for Temperature and Time
Adjustment For: Multiplier
Temperature for Cu Wiring including CA, Mx, Vx, VL, ------------------------- 25.45
9495
MQ, VQ, MG,VG, LM, E1,OL and negative C4s where T max (K -)
F (T ) = e
wires into the C4 pad are Cu
Time for Cu Wiring including CA, Mx, Vx, VL, MQ, VQ, 0.909
F ( EO L actual ) = ---------------------------------------------------
110000
MG,VG, LM, E1,OL and negative C4s where wires into 10000 + EO L actual
the C4 pad are Cu
Temperature for Al wiring including FY, LY, FT, F1, MA, -------------------------
5461
14.64
VV, LD and negative C4s where wires into the C4 pad are T max (K -)
F (T ) = e
Al
Time for Al wiring including FY, LY, FT, F1, MA, VV, LD 0.588
F ( EO L actual ) = ---------------------------------------------------
110000
and negative C4s where wires into the C4 pad are Al 10000 + EO L actual
NOTE: Using the temperature and life time adjustment factors to justify higher current usages should be con-
templated only when the lower application end-of life or temperature is absolutely certain. Designing with
such a derivation in effect inherently limits the applications of the product.
Idc limit for interconnects for a given junction temperature, T, and for a given product lifetime, EOL actual, can
be calculated using the following relation:
I dc ( T , EOL actual ) = I dco F ( T ) F ( EOL actual )
where
( EOL actual ) = PO H I dc DutyFactor
where Idco = Idc limit at 100oC and for 100,000 POH product Life. The values of F(T) and F(EOLactual) for con-
tacts, vias, and lines are given in the following tables.
Table 223. Idc Temperature Adjustment Factors
Temperature (oC) Cu Al Positive C4

Multiplier Multiplier Multiplier
50 51.7 9.65 5.89
60 21.4 5.81 3.97
70 9.32 3.60 2.73

Table 223. Idc Temperature Adjustment Factors
Temperature (oC) Cu Al Positive C4

80 4.25 2.29 1.92
90 2.03 1.50 1.38
100 1.00 1.00 1.00
110 0.517 0.683 0.748
120 0.275 0.475 0.564
125 0.203 0.399 0.492
Table 224. Idc Time Adjustment Factors
POH Cu Al Positive C4
40,000 2.05 1.59 1.55
50,000 1.73 1.43 1.40
75,000 1.26 1.16 1.15
100,000 1.00 1.00 1.00
110,000 0.924 0.950 0.953
150,000 0.711 0.802 0.812
200,000 0.556 0.684 0.698
Idc Exceptions to General Rules for Short Lengths

Line lengths (L) <10 um with widths (W) <2xWmin (Wmin = minimum line width) could have increased Idc
values. Any Cu line on levels M1-M6, MG, MQ, or LM within these limits can operate at a higher Idc limit.
To calculate the Idc limit:
Use calculated Idc values from Table 220, Current Limits at 100C, on page 492 and Table 222,
Adjustment Factors for I(dc) only, for Temperature and Time, on page 496.
If Idc is less than the maximum current limits given in Table 225, Maximum Idc Current Limit
for Short Length Applications, apply the following equation:

Idc(Short Length) = Idc(Calculated) x (10/L)
Table 225. Maximum Idc Current Limit for Short Length Applications
Level Max. Current Limit (mA) Idc, Max @ 2xWmin (mA)
M1 5.83(W-0.06) 1.52
M2-M6 6.50(W-0.06) 2.21
MG, MQ, LM 11.25(W-0.07) 8.33
Note: E1 short length exceptions are not qualified
Exception Rules for C4 Terminals

In general, when wiring to C4 terminals, use of two or more metal wires with an equivalent line width, or use
four metal wires of equal line width wired to a C4 terminal from four different directions, where the sum of the
two or more line widths meet or exceed the guidelines identified in Table 226, Table 227 and Table 228, is
recommended. However, for certain conditions when using the LM metallization option, use of at least two
wires is required, as identified in Table 226, and Table 227.
Table 226. Ceramic Packaging Rules for C4 Terminals at 100 or 125 degrees C
Design Size Mask Line into Width of line into Max Idc (mA) Temperature (oC)
C4 DIA Level C4 pad C4 pad (m)
LV LD 44 98 mA per C4 125
47.0 LV LD 36 200 mA per C4 100
LV MA 46 98 mA per C4 125
LV MA 37 200 mA per C4 100
TV LM 90 98 mA per C4 1251
TV LM 37 200 mA per C4 100

1. The allowable LM width exceeds the Rule 635b maximum limit for a single wire (see Table 35, on page 147) at 125oC. To
support 98mA at 125oC, two or more LM lines must be used with an equivalent line width of 45m. Using LM lines of equal
22.5m width, wired to the C4 terminal from four different directions, is recommended.

Table 227. Laminate with Ni BLM Packaging Rules for C4 Terminals at 100 or 125 degrees C
47.0 LV LD 27 150 mA per C4 100
LV MA 28 150 mA per C4 100
TV LM 67 73mA per C4 1251
TV LM 28 150 mA per C4 100

1. The allowable LM width exceeds the Rule 635b maximum limit for a single wire (see Table 35, on page 147) at 125oC. To
support 73mA at 125oC, two or more LM lines must be used with an equivalent line width of 33.5m. Using LM lines of equal
16.75m width, wired to the C4 terminal from four different directions, is recommended.
Table 228. Laminate with CrCu BLM Packaging Rules for C4 Terminals at 100 or 125 degrees C
47.0 LV LD 18 100 mA per C4 100
LV MA 19 100 mA per C4 100
TV LM 45 49mA per C4 125
TV LM 19 100 mA per C4 100

MA W>46m LV
MA BEOL Metallization Option

Ceramic Page, 125 degrees C
LD W>44m LV
OL with LD BEOL Metallization Option

Ceramic Page, 125 degrees C
LM W>37m TV
LM BEOL Metallization Option

Ceramic Package, 100 degrees C
Figure 107. Examples of Designs which follow Exceptions Rules in Table 226, Ceramic Packaging Rules for C4
Terminals at 100 or 125 degrees C, on page 498
5.4.3 Electromigration for C4 Terminals

C4 terminal pad types are defined as:
Positive C4 pad (Vdd Pad)

C4 pad at a higher voltage potential than the chip metallization, current flowing from the chip
to the package.

Negative C4 pad (Ground Pad)

C4 pad at a higher voltage potential than the chip metallization, current flowing from the chip
to the package.
Leaded Bumps: Positive Feed

Table 229, Positive-Feed High-Lead C4 Terminals at 100 degrees C Operating Temperature for 100
KPOHs shows the maximum Idc values for electromigration for high lead C4 terminals with electron flow
from chip to carrier.
Current carrying capability must be verified for C4s with electron flow from the carrier, since this capability
varies based on the particular carrier pad preparation and chip join processes. In Table 229 on page 501 the
values are given for 100 KPOH, unless otherwise specified.
Definitions:
Package = C4 interconnect + carrier + associated hardware.
1 FIT = 1 ppm for 1000 hours.
Grade 1 Package Reliability is 1 FIT per device (not applicable for Lead-free C4 Termi-
nals).
Grade 3 Package Reliability is 10 FIT per device.
Table 229. Positive-Feed High-Lead C4 Terminals at 100 degrees C Operating Temperature for 100 KPOH
Electromigration for Positive Feed Lead C4 Terminals, with Electron Flow from Chip To Carrier
Carrier and Attach C4 Size / Design Size Maximum Idc Target

Solder C4 Pitch LV, TV
Diameter 97% Pb / 97% Pb /
(Minimum) 3% Sn C4 3% Sn C4
TiW/Cr-Cu/Cu TiW/Cr-Cu/Cu/
UBM 1m e-Ni
UBM
Ceramic 4 mil 47m

250mA1 250mA 1
200m and 225m
5 mil 47m
250mA 1 250mA 1
250m
Organic with eutectic 40 KPOH: 190mA

4 mil 47m
Solder 100mA2
200m and 225m
100 KPOH: 130mA
1. Package reliability grade 1 = 100 ppm for 100 KPOH
2. Package reliability grade 3= 1000 ppm for 100 KPOH.

Pb-Free Positive Feed
Table 230, Positive-Feed Lead-free C4 Terminals at 100 degrees C Operating Temperature for 100 KPOHs
shows the maximum Idc values for electromigration for lead-free C4 terminals with electron flow from chip to
carrier.
Current carrying capability must be verified for C4s with electron flow from the carrier, since this capability
varies based on the particular carrier pad preparation and chip join processes. In Table 230 on page 502 the
values are given for 100 KPOH, unless otherwise specified.
Definitions:
See section , Definitions: on page 501.
Table 230. Positive-Feed Lead-free C4 Terminals at 100 degrees C Operating Temperature for 100 KPOH
Electromigration for Positive Feed Lead Free C4 Terminals, with Electron Flow from Chip To Carrier
Carrier and Attach C4 Size / Design Size Maximum Idc Target

Solder C4 Pitch LV, TV
Diameter Lead Free: SnAg Solder
(Minimum)
Organic with Attach 4 mil 40 KPOH: 145mA1

47m
Solder 200m and
225m 100 KPOH: 100mA 1
1. Package reliability grade 1 = 100 ppm for 100 KPOH
C4 Redundancy
Note that C4 redundancy can be used to enable a higher current-carrying limit, assuming the following:
A set of n C4 pads is considered redundant when the failure of an arbitrary (n-1) pad creates a voltage
and current shifts that do not cause the chip to malfunction.
Unlimited use over the product lifetime is enabled only when the failure of an arbitrary (n-1) pad does not
cause the currents on the remaining pads to exceed the maximum current limit (corresponding to more
than 20 degrees C) of localized joule heating).
Table 231, C4 Redundancys shows the C4 redundancy corrections.
Table 231. C4 Redundancy
Number of Redundant C4s Current Increase (%)
1 0
2 5

Table 231. C4 Redundancy
Number of Redundant C4s Current Increase (%)
3 8
4 15
>5 20
Note: The allowable maximum adjusted current is 200mA per C4 for organic products and 350mA per
C4 for ceramic products.
5.4.4 Metal Corrosion

For corrosion protection, no exposed metal lines (other than wirebond pads, if applicable) are allowed.
5.4.5 No Polyimide Feature

While the use of the No Polyimide Feature is not believed to have a significant impact on the Reliability of the
part, IBM makes no claims to the reliability of the product when the No Polyimide feature is utilized.

Latchup Latchup Background and Experimental Data IBM
6.0 Latchup
6.1 Latchup Background and Experimental Data

These are not Latch-up guidelines. This is a description of Latch-up critical structures and the related
electrical parameters. Latch-up protection measures are available in additional documents. If a
design follows these recommendations, it will NOT automatically pass the JEDEC standard. The val-
ues in this chapter are subject to change. Please contact the Latch-up development of your company
for further details.
6.1.1 Latch-up (LU) Qualification Models

LU protection measures for CMOS8RF are designed to prevent damage to chip circuitry due to the occur-
rence of a Latch-up. LU protection must be achieved on all diffusion which are directly connected to a pad.
There are 2 LU tests used for qualification, current test at all input pins and overvoltage test at all voltage pins.
For designs with wide market applications, the Latch-up conformance should be demonstrated to JEDEC
(EIA/JESD78) standard. These standards are achievable by providing adequate Latchup protection. Testing
is done in conformance to the specific specifications upon request. Table 232, Latch-up Test Specification
and Requirements on page 504 summarizes the 2 tests and the typical requirement.
Table 232. Latch-up Test Specification and Requirements
Model Specifications Requirements.
IC Latchup Test JEDEC (EIA/JESD78) I=+/-100 mA

class II
V=1.5 Vsupply
6.1.2 Latch-up Fundamentals

Latchup occurs when diffusions in bulk CMOS are placed in close proximity to each other and they form a
PNPN or NPNP, often referred to as a silicon controlled rectifier (SCR) or thyristor. Figure 108, Parasitic SCR
with Equivalent Circuit on page 505 shows a cross section of a NFET and a PFET placed in close proximity
to each other. As can be seen in Figure 108, Parasitic SCR with Equivalent Circuit on page 505 a parasitic
NPN and PNP are formed. Figure 108, Parasitic SCR with Equivalent Circuit on page 505 also shows the
equivalent circuit with the parasitic resistances included for completeness. This figure is just one instance of a
parasitic SCR being formed between a NFET and a PFET, there are many more possible scenarios which
can occur between n-type and p-type structures to form parasitic SCRs in bulk CMOS.

Page 504 of 580 IBM Confidential--Do Not Copy Version Date: November 30, 2010
Latchup Latchup Background and Experimental Data
NFET PFET
VDD
Rn-well
P+ N+ N+ P+ P+ N+
p+
PNP n-well
NPN RNWell
NWell p-substrate
Rsubstrate
n+
PWell
Rpsub
P- Wafer
VSS
Figure 108. Parasitic SCR with Equivalent Circuit
6.1.3 Internal Latchup

The evaluation of internal latchup is done by testing on a typical four terminal latchup structure. Figure 109,
Internal Latchup test structure on page 506 shows the cross-section of such a four terminal structure.
Parasitics
During the triggering in a latchup event, the parasitic bipolar transistors effects the performance of the typical
thyristor structure. To avoid latchup it is necessary to know the betas of the parasitics (npn and pnp) signifi-
cantly determined by n+ to p+ spacing. Larger spaces lead to wider parasitic bipolar base widths, wider base
widths lead to lower betas, lower betas lead to higher trigger currents. The structure shown in Figure 109,
Internal Latchup test structure on page 506 is used for measuring the parasitics. The beta is determined by
the following equation B= IC/IB Table 233, Betas of Parasitics on page 506 lists the parasitic beta values.

Version Date: November 30, 2010 IBM Confidential--Do Not Copy Page 505 of 580
Latchup Latchup Background and Experimental Data IBM
W
Dsx Lsx Ln+ D1D2 Lp+ Lnw Dnw
SX N+ P+ NW
PNP
RNWell
NPN
Rsubstrate NWell
PWell
P- Wafer
Figure 109. Internal Latchup test structure
Table 233. Betas of Parasitics
NPN Definitions Bn PNP Definitions Bp
npn 1.2V reg VT @ 25C 2.2 pnp 1.2V reg VT @ 25C 1.35
npn 1.2V reg VT @ 140C 2.8 pnp 1.2V reg VT @ 140C 1.85
Other device dimensions for the structures evaluated at Ic=1mA in Table 233, Betas of Parasitics are given
below:
D1= 0.3um D2= 0.3um
Ln+= 1.2um Dsx= 1.2um
Lp+= 1.2um Dnw= 1.2um
Lsx= 38.0um W= 20.0um
Lnw=38.0um
The above measurements at 25C are at 1XVdd and the measurements at 140C are at 1.5XVdd
Internal Latchup triggering parameters

Internal latchup can occur via overshoots, undershoots or hot electron/hole generation.
1. Overshoot - P+ diffusion voltage exceeds NWell voltage, P+/NW diode forward biases turning on PNP and
then PNP triggers SCR).
Vdd noise

Latchup Latchup Background and Experimental Data
2. Undershoot - GND node goes below zero volts (fwd bias n+/substrate diode turns on NPN and then trigger-
ing of SCR occurs)
GND bounce
3. Hot electron/hole generation
PFET hot electron/hole generation (electrons lower local NWell potential), P+/NWell diode forward biases
turning on PNP and then PNP triggers SCR.
NFET hot electron generation (holes raise local pWell/substrate potential), Substrate/N+ diode forward
biases turning on NPN and then NPN triggers SCR.
The parasitic SCR I-V characteristics are shown in Figure 110, SCR I-V Characteristics on page 507. Curve
A shows the case when the PNP is triggered and then causes the SCR to trigger and curve B shows the case
when the NPN is triggered and then causes SCR to trigger. The key points are label on curves A,B on Figure
110, SCR I-V Characteristics on page 507. The key points are the trigger currents and voltages (volt-
age/current that the SCR turns on) and the holding/sustaining voltage (voltage that Vdd collapses to after
SCR is triggered). In all formations of the parasitic SCR the substrate resistance and Nwell resistance modu-
late the trigger voltages/currents and the holding/sustaining voltages of the SCR.
ABS(Ip+,In+)
Holding Voltage
Curve B Curve A
Trigger Voltage/Current Trigger Voltage/Current
Undershoot Overshoot
(NPN Triggers) (PNP Triggers)
Figure 110. SCR I-V Characteristics
The Overshoot test is done by ramping P+ positively with N+ and SX at ground, and NW at Vdd (1.5Vdd for
high temperature testing) on the structure shown in Figure 109, Internal Latchup test structure on page 506.
The Undershoot test is done by ramping N+ negatively with P+ and NW at Vdd (1.5Vdd for high temperature
testing) and SX at ground. The Holding test is done by ramping P+ until snapback with NW at Vdd (1.5Vdd for
high temperature testing) and SX at ground.
Table 234, Latch-up Test Specifications and Requirements on page 508 lists the internal latchup triggering
parameters.

Latchup Latchup Guidelines and Layout Constraints IBM
Table 234. Latch-up Test Specifications and Requirements
Definition Overshoot Undershoot Holding

voltage (v) voltage (v) voltage (v)
1.2V reg VT @ 25C 3.50 0.88 1.80
1.2V reg VT @ 140C 1.75 0.65 1.60
Other device dimensions for the structures evaluated in Table 234, Latch-up Test Specifications and Require-
ments on page 508 are given below:
D1= 0.3um D2= 0.3um
Lsx= 38.0um Lp+= 1.2um
Lnw= 38.0um Ln+= 1.2um
W= 20.0um Dsx= 1.2um
Dnw= 1.2um
The above measurements at 25C are at 1xVdd and the measurements at 140C are at 1.5xVdd
6.2 Latchup Guidelines and Layout Constraints

Latchup is considered to be potentially destructive if the holding/sustaining voltage is less than the Vdd sup-
ply that the parasitic SCR is connected to. Destruction will occur in this case when Vdd > Vholding after the
triggering signal goes away and the SCR is turned on. Vdd being greater than Vholding causes the SCR to
remain in a on state and current runaway occurs. The exception occurs in cases where the Vdd supply has a
low enough built in current compliance which ensures excessive current flow does not occur and lead to joule
heating and eventual melting/filamentation of elements in the path where the current flow occurs. The current
compliance value depends upon the power supply which is supplying the voltage/current for the Vdd rail. The
compliance of the power supply should NOT be relied upon to ensure non-destructive latchup occurs, the
emphasis should be placed on ensuring the SCR does not trigger.
In cases where the holding/sustaining voltage is greater than Vdd this can be a non-destructive or transient
latchup event as long as the current during the triggering event doesnt cause enough joule heating to cause
destruction in the current path where the current is flowing during the latchup event. In this case, once the
triggering pulse goes away, Vholding is greater than Vdd and the SCR shuts off.
Ideally one wants the triggering current and holding voltage to be infinity to ensure the SCR wont trigger how-
ever in todays bulk CMOS technologies the trigger currents are typically in the micro-Amp (uA) and/or
milli-Amp (mA) range and the holding voltages are again typically near or less than the Vdd supply value.
6.2.1 Latchup Prevention

There are two categories of latchup, internal latchup and external latchup. Internal latchup occurs to circuits
which are not connected to I/O or signal pads (C4 or wirebond pads) and external latchup occurs to circuits
which are connected to I/O or signal pads.

Latchup Latchup Guidelines and Layout Constraints
Internal Latchup Prevention

Internal latchup can occur via overshoots, undershoots or hot electron/hole generation. First consider the
variables a designer has control over when designing circuits as well as the general variables which modulate
latchup characteristics. The variables are the following:
1. Beta of the parasitic devices, determined by n+ to p+ spacing (determined by n+ to NW and p+ inside NW

spaces), for density purposes this one is typically set at the groundrule minimum. Larger spaces lead to wider
parasitic bipolar base widths, wider base widths lead to lower betas, lower betas lead to higher trigger cur-
rents.
2. Substrate resistance, this is determined by (5) components shown in Figure 111, Substrate Resistance
Components on page 510. The (5) components consist of the following resistances:
R1 - Vertical resistance of substrate guardring around chip
R2 - Horizontal resistance from substrate guardring around chip to the local device
R3 - Vertical resistance of the local substrate contact
R4 - Horizontal resistance of the local substrate contact to the device
R5 - Vertical resistance beneath the device channel
The resistances a designer has control over are R3 and R4. R3 is determined by the area of the local sub-
strate contact. The resistance is given in ohm-um2, the larger the area of the substrate contact, the lower the
value of R3. The resistance of R3 is given in Table 168, Contact Resistance on page 416 for the substrate
contact. R4 is determined by the distance the substrate contact is away from the device. R4 is given as a
sheet resistance and the sheet rho for R4 is given in Table 170, Conducting Film Thicknesses and Sheet
Resistances at 25C on page 417. Controlling the upper limit of R3 is addressed in latchup groundrules
LUP05-LUP08 and controlling the upper limit of R4 is addressed in groundrules LUP02 and LUP04 (see
Table 59, Latchup Rules on page 176).

NFET
P+ P+ N+ N+
R1 R3 R5
R2 R4 PWell
P- Wafer
Figure 111. Substrate Resistance Components
3. NWell resistance, this is determined by (3) components shown in Figure 112, NWell Resistance Compo-
nents on page 511. The (3) components consist of the following resistances:
R1 - Vertical resistance of the local NWell contact
R2 - Horizontal resistance of the local NWell contact to the device
R3 - Vertical NWell resistance beneath the device channel
The resistances a designer has control over are R1 and R2. R1 is determined by the area of the local NWell
contact. The resistance is given in ohm-um2, the larger the area of the NWell contact, the lower the value of
R1. Resistance of R1 is given in Table 168, Contact Resistance on page 416 for the nwell contact. R2 is
determined by the distance the NWell contact is away from the device. R2 is given as a sheet resistance and
the sheet rho for R2 is given in Table 170, Conducting Film Thicknesses and Sheet Resistances at 25C on
page 417. The upper limit of R1 is controlled by groundrules LUP05-LUP08 and the upper limit of R2 is con-
trolled by groundrules LUP02 and LUP04 see Table 59, Latchup Rules on page 176).
From a design point of view, the main things which a designer can do to help maximize the trigger cur-
rent/voltage is to make the substrate and NWell contacts as robust (proximity and area) as possible and
increase the n+ to p+ space if maximum density is not required.

PFET
N+ P+ P+
R1 R3
R2
NWell
P- Wafer
Figure 112. NWell Resistance Components
Internal Latchup Triggering Mechanisms

The highest probability of internal latchup could occur either during burn-in or during elevated voltage/temper-
ature screens/stresses in general. For instance, in burn-in, supplies are typically elevated to 1.5x their normal
value and temperatures increased to near 140C. In DVS/EVS voltages can be 1.3-2X their normal value and
temperatures can be => 85C. Under the elevated voltage/temperature screening/stressing the parasitic resis-
tances R1-R5 discussed back in Section Internal Latchup Prevention on page 509 will be increased signifi-
cantly due to their temperature coefficient of resistance (TCR) and the substrate/NWell injection current by
NFETs and/or PFETs increases with increasing drain to source voltage (Vds) due to avalanche multiplication
voltage/field dependence. To ensure internal latchup triggering does not occur the following guidelines should
be used for each of the (3) triggering modes defined previously in Section Internal Latchup Triggering Mech-
anisms on page 511 :
1. Overshoot
Limit voltages across P+/NW diodes (PFET drain or source to NWell) to less than 0.3V
Vdd bounce/noise minimized
Minimize NWell and Substrate resistances
2. Undershoot
Limit voltages across N+/Substrate diodes (NFET drain or source to Substrate) to less than 0.3V
GND bounce/noise minimized

Limit local substrate and NWell potentials (Vsub_local) to less than 0.3V
Vsub_local = Isx * Rsx
where Isx = Substrate/Nwell current generated by impact ionization from NFETs or PFETs respec-
tively
where Rsx = Substrate/Nwell resistance defined back in section , Internal Latchup Prevention on
page 509
Internal Latchup (Array N-Well, Special Case)

An Array N-well MUST have an N-well guard ring biased at Vdd and a substrate guard ring connected to
ground in the following cases:
The array N-well is biased by an on-chip bias generator.
Overshoot or undershoot is a concern.
This structure must exist on any edge where there is a concern for internal undershoot voltage or overshoot
voltage being generated. It is recommended that for large arrays a guard ring be used because of edge bit
leakage mechanisms. Results have shown that in large arrays with large STI volumes on the perimeter, edge
bit leakage can be worse than interior nodes for arrays without guard rings.
External Latchup Triggering Mechanisms

The highest probability of external latchup could occur either during burn-in or elevated voltage screen
stresses in general. For instance in burn-in supplies are typically elevated to 1.5x their normal value and tem-
peratures increased to near 140C. In DVS/EVS voltages can be 1.3-2X their normal value and temperatures
can be => 85C. Under the elevated voltage/temperature screening/stressing the parasitic resistances R1-R5
discussed back in section , Internal Latchup Prevention on page 509 will be increased significantly due to
their temperature coefficient of resistance (TCR) and the substrate/NWell injection current by NFETs and/or
PFETs increases with increasing drain to source voltage (Vds).
Other items to consider for external latchup are the Jedec Standard Latchup Test, power-up sequencing
issues and the Cable/Human Discharge Event (CDE/HMM) issues. For external latchup prevention all N+ dif-
fusions connected to wirebond or C4 pads must be surrounded by a NWell and Substrate guardring (groun-
drule LUP13A-LUP13B) where the NWell guardring is connected to Vdd and the substrate guardring is
connected to gnd. To ensure external latchup triggering does not occur the following guidelines should be
used for each of the (7) triggering modes listed below:
1. Overshoot
Limit voltages across P+/NW diodes (PFET drain or source to NWell) to less than 0.3V
Vdd bounce/noise minimized

NWell and Substrate guardrings (groundrule LUP13A-LUP13B)

2. Undershoot
Limit voltages across N+/Substrate diodes (NFET drain or source to Substrate) to less than 0.3V
Gnd bound/noise minimized
Limit local substrate & NWell potentials (Vsub_local) to less than 0.3V
Vsub_local = Isx * Rsx
where Isx = Substrate/Nwell current generated by impact ionization from NFETs or PFETs respec-
tively
where Rsx = Substrate/Nwell resistance defined back in section , Internal Latchup Prevention on
page 509
4. Jedec Latchup test
The Jedec latchup test is performed during qualification of all parts.
The current force part of the Jedec latchup test described simply, performs a pre-Iddq measurement,
forces into each I/O pin Iddq +/- 100mA, and then performs a post-Iddq measurement. If the post-Iddq is
1.5X larger than the pre-Iddq then latchup is assumed to have occurred, or if functionality is not achieved
after latchup testing a failure has occurred.
If a P+/NW diode based ESD protection is being used from signal to Vdd then a robust P+ substrate
guardring needs to surround these diodes. During the Jedec latchup test the current forced into the I/O
pad will go through the diodes from signal pad to Vdd, however since the P+/NW diode is also a vertical
PNP a significant portion of the current forced into the I/O pad wont actually go to the Vdd rail but will go
to the substrate due to this vertical PNP. To ensure the local substrate potential remains at 0.3v or lower a
robust substrate guardring needs to enclose the P+/NW diode(s). Groundrules LUP14, LUP15A and
LUP15B help to ensure an adequate substrate guardring is used.
NW/SX diodes from signal to gnd. are not recommended for ESD protection devices due to the low col-
lection efficiency of surrounding NWell guardrings. Instead N+/SX diodes are recommended from signal
to ground. If a N+/SX diode is used for ESD protection then the n+ diffusion should be enclosed in a
NWell guard ring.
5. Power-up Sequencing
To avoid latchup, it is recommended that power-up sequences be clearly defined for the application and
that the overshoot and undershoot criteria are met during power-up. Power up sequencing is a function of
the ESD design and the I/O circuitry. In applications, where multiple power supplies exist on the same
chip, the power up sequence should be defined so that no diode forward biases and no internal or I/O
NFET has more than the allowed NFET Vds or gate voltages for the technology. For the constraints, see
section 4.3.2 , Trigger and Sustaining Voltage on page 340, section 4.2 , Isolation Oxide (STI) Design
Specifications on page 338. The power up sequence is dependent on the ESD circuit used. Given a

sequence independent ESD design, this is not a concern for the Vdd(1) and Vdd(2) power supplies. In
designs with multiple grounds, it is critical that the sequencing of ALL grounds be taken into account in
power up strategy. This is critical when using supply-supply ESD protection circuits and ESD designs with
multiple Vss and Vdd rails tied to external pins.
6. Cable Discharge Event (CDE)
Cable discharge occurs due to hot-plugging of cables into systems. Many amps of current can be dis-
charged into a module pin if system level voltage clamps or current limiters are not used between the
systems outside connector and the integrated circuit chips inside the system. This event can occur when
the system is powered or unpowered.
7. Hand Metal Model Discharge Event (HMM)
Humans discharging via metal objects to a system are emulated using a system level test called the hand
metal model (HMM). Many amps of current can be discharged into a module pin if system level voltage
clamps or current limiters are not used between the systems outside connector and the integrated circuit
chips inside the system.
Design Guidelines for latchup prevention for CDE or HMM Events inside the I/O cell
Inside the I/O cell the following design practices should be followed for I/Os that will encounter CDE or HMM
events:
1. Any N+ diffusions connected either directly to I/O signal pads or connected to I/O signal pads via a
resistor should be enclosed by a NWell and SX guardring (see latchup groundrule LUP13). These
NWell guardring should be increased to a width => 2um and the SX guardring should be increased
also to a width => 2um. It is important that the NWell and the SX guardrings are strapped with con-
tacts and metal as much as possible and that the overall resistance from any spot on the guardring to
the actual supply pad is minimized, ideally something less than 1 ohm is optimal. Typical N+ diffu-
sions connected to pads in I/O cells consist of the ESD diodes (N+/SX or NW/SX), OP N+ diffusion
resistors and NFET drains. These N+ diffusions when fwd biased (negative voltage or current seen
at I/O pad) inject electrons into the SX and these guardrings are put in place to collect to minority car-
rier electrons in the SX.
2. Any P+ diffusions inside NW connected either directly to I/O signal pads or connected to I/O signal
pads via a resistor should be enclosed by a SX guardring (It is recommended that the SX guardring
width meet latchup groundrule LUP15A). It is important that the SX guardrings are strapped with
contacts and metal as much as possible and that the overall resistance from any spot on the
guardring to the actual supply pad is minimized, ideally something less than 1 ohm is optimal. Typical
P+ diffusions inside NW connected to pads in I/O cells consist of the ESD diodes (P+/NW) and PFET
drains. These P+ diffusions when fwd biased (positive voltage or current seen at I/O pad) inject holes
into the SX and the SX guardring is put in place to clamp the local SX potential as close to gnd (0v)
as possible.
3. For perimeter image chips the ESD device is recommended to be located as close to the outside
edge (bottom of I/O cell typically) of the chip as possible. For area array images, the ESD device is
recommended to be located as close to the center of the I/O cell as possible.
4. For circuits not connected to I/O signal pads however are inside the I/O cell itself (pre-drive circuits for
example), the N+/P+ spacing of the NFETs and PFETs should be backed off to 1.5X the minimum
spacing or a preferred solution is to make sure the NFETs and PFETs in these areas are separated
by NWell and SX guardrings.

Design Guidelines for latchup prevention for CDE or HMM Events outside the I/O cell
Outside (surrounding) the I/O cell the following design practices should be followed for I/Os that will encounter
CDE or HMM events:
1. A typical I/O cell layout and surrounding environment is shown in Figure 113, Typical I/O cell layout
and surrounding environment on page 515. It shows an n-type diffusion in the I/O connected to a
pad. Injection of minority carriers (electrons) from this diffusion into the substrate occurs during an
ESD event (CDE or HMM). These injected electrons spread into the substrate and are collected by
NWells in circuits adjacent to the I/O and pull down their potential locally causing p+ diffusions in the
NWells to forward bias. Forward biasing of the P+/NW diode can result in turning on the parasitic
pnps which can then trigger the SCR (formed between adjacent NFETs and PFETs) to cause
latchup.
2. Similarly, injection of majority carriers (holes) can result in locally raising the potential of PWell in the
circuits adjacent to the I/O resulting in forward biasing the P+ diffusions in the PWell. This can result
in turning on the npn which can then trigger the SCR resulting in latchup.
I/O Cell SX Guard ring
holes SX
P+ diffusion
in N-Well
N+ diffusion
in P-Well NW
electrons
NWell Guard ring

I/O Pad
Figure 113. Typical I/O cell layout and surrounding environment
3. The distance up to which the minority carriers (electrons) can diffuse in the substrate without recom-

bination is the minority carrier diffusion length. The electron diffusion length (Ln) in m is calculated
using the following expression: Ln= (Dnn)1/2, where Dn is the diffusion constant (cm2/s) and n is the
electron lifetime in sec. For a p- substrate doping of 5E15 cm-3, Dn is ~25 cm2/s and n is ~100S
resulting in a diffusion length of ~500 um. Resistance requirements from the upcoming model
should be applied out to approximately 500um in all directions surrounding the I/O cell.
4. The resistance of the NWell in the circuits adjacent to the I/O (e.g. gate array or inverters) is an
important factor in determining latchup (negative mode) as discussed in the section on section ,
Internal Latchup Prevention on page 509. A simple model has been formulated to calculate the
maximum NWell resistance (to prevent forward biasing of P+/NW diodes) as a function of distance
from the I/O (injector) for three different types of pulses (HBM, HMM and Cable model) applied to the
injector (Figure 114, Nwell Resistance as a function of distance from the injector for HBM, HMM and
Cable Models on page 517). The NWell resistance at a distance r from the injector is calculated as
follows:
The model assumes that the injected current spreads into the substrate uniformly in all directions. In the
DC model, the peak injected current is used to calculate the NWell resistance. The resistance Rdc in
ohm-m2 is given as 0.7/J, where J is the current density in A/m2. The current density J is calculated as
Ipeak/(2 r2), where Ipeak is the peak injected current for the three models (2 A in HBM (3000V, 100pF,
1500 ohms), 9 A in HMM (3000V, 150pF, 330 ohms) and 5 A in Cable Model (250V, 1500pF, 50 ohms))
and r is the distance from the injector.
The transient model takes into account the pulse width and the transit time of the electrons to provide
relief to the DC resistance value. The NWell resistance in the transient model is obtained as
Rdc/(1-exp(-t/)), where t is the pulse width (150 nS in HBM, 80 nS in HMM and Cable model) and is the
time constant calculated as r2/(4 Dn).
The transient model should be used for determining resistance values. The DC model has
been included in Figure 114, Nwell Resistance as a function of distance from the
injector for HBM, HMM and Cable Models on page 517 as a comparison with the
transient model.

Figure 114. Nwell Resistance as a function of distance from the injector for HBM, HMM and Cable Models
5. A sample calculation is given below using Figure 114, Nwell Resistance as a function of distance
from the injector for HBM, HMM and Cable Models on page 517 to design NWell in the circuits adja-
cent to the I/O that have to be robust for CDE/HMM:
At a distance r=100um from the I/O, the NWell resistance needs to be ~65 k ohms-m2 (from Figure 114,
Nwell Resistance as a function of distance from the injector for HBM, HMM and Cable Models on
page 517 using HMM, transient model) to prevent any p+/N-well diode from being forward biased. There-
fore, if the NWell is a rectangular strip of 400 m2 area (100 m x 4 m), the NWell resistance needs to
be (6.5x104/400)=~160 ohms. At a distance of r=500 m from the injector, required NWell resistance of
the rectangular strip (area=400 m2) increases to ~90 k ohms.
A sample NWell resistance calculation is shown below for two cases of NWell region adjacent to the I/O
cells (Figure 115, Schematic of Nwell Geometries for sample resistance calculation on page 518):

Lw
Ww Wc Ac
p+ p+
NWell
Lc
Case (i)
Lw
Ac Wc Ww Wc Ac
p+ p+
NWell
Lc Lc
Case (ii)
Figure 115. Schematic of Nwell Geometries for sample resistance calculation
For case (i) shown in Figure 115, Schematic of Nwell Geometries for sample resistance calculation
on page 518, the total NWell resistance measured from the edge of P+ diffusion is comprised of the
horizontal resistance and the vertical resistance. The horizontal resistance in ohms is calculated as
Rs (Lw/Ww), where Rs is is the sheet resistance of the NWell Table 170, Conducting Film Thick-
nesses and Sheet Resistances at 25C on page 417 in ohms/sq, Lw is the length of the NWell region
in m and Ww is the width of the NWell region in m. The vertical resistance is calculated as (Rv x
Ac), where Rv is the vertical resistance Table 170, Conducting Film Thicknesses and Sheet Resis-
tances at 25C on page 417 in ohms-m2 and Ac is the contact area in m2 (Lc x Wc). As an exam-
ple, for a N-well region with Lw=100m, Ww=4 m, Lc=1 m and Wc=3 m, the horizontal resistance
is 540 x (100/4)= ~13.5 k ohms and vertical resistance is 1500/(3x1)= ~0.5 k ohms resulting in a total
resistance of ~14 k ohms.
For case (ii), the total NWell resistance would be approximately half of case (i), i.e., 7k ohms.
6. Design guidelines
6a) Negative Mode/ Polarity:
Areas a distance1-100um from the edge of the injecting devices (N+ diffusions connected to I/O
pads)
Some example calculations (using HMM transient model, assuming NW area of 400um2)
show NWell resistances required down near160 ohms, this is nearly impossible to
achieve thus devices like decoupling capacitors (w/o control circuits), NFETs only or
PFETs only, or NFETs and PFETs with NWell and SX guardrings between them
should be designed in this region.

Areas a distance100-200um from the edge of the injecting devices (N+ diffusions connected to I/O
pads)
show NWell resistances required ~160 - 2.5k ohms, this is achievable however the
contact periodicity and contact area needs to be assessed and reduced periodicity
contacts along with larger area contacts in this region may be required (layout/meth-
odology dependent).
Areas a distance 200-500um from the edge of the injecting devices (N+ diffusions connected to I/O
pads)
show NWell resistances required in the 2.5k- 100kohm range, this is achievable
however the contact periodicity and contact area needs to be assessed and reduced
periodicity contacts and larger area contacts in this region may be required (lay-
out/methodology dependent).
6b) Positive Mode/ Polarity:
As far as an equal number of SX contact books are placed for every NW contact book, then
the positive mode/ polarity should be fine.
6.2.2 I/O and Array N-Well Guard Ring Rules

Figure 116, Guard Ring Layout for CMOS I/O and Array N-well Circuits on page 520 shows examples of
designing a NWell and/or substrate guardring around structures connected to I/O pads (groundrule
LUP13A,B) and examples of NWell guardrings around large arrays. The guardrings are designed to collective
potential carriers flowing in the substrate between the NFET and PFET. The guardrings collect these carriers
and there effectiveness is based on what is typically referred to as guardring efficiency (ratio of {carriers col-
lected by guardring/carriers injected}).
Some hints for improving guardring efficiency:

1. NWell guardrings, width of nwell guardring will improve its collection efficiency
2. NWell guardrings, the contacts and metal strapping improve its collection efficiency
3. Substrate guardrings, width of nwell guardring will improve its collection efficiency
4. Substrate guardrings, the contacts and metal strapping improve its collection efficiency as well as lowering
its effective resistance down to the actual substrate.

(A) Guard Ring for (B) Guard Ring

N-Channel Devices for P-Channel Devices
Array, N+ or NFET guard ring: Array, P+ or PFET guard ring: Separate
P+ diffusion and N+ / N-well ring N-well, with N+ diffusion ring tied to Vdd
NFET,
array or N+ P+, PFET, or
diffusion array structure
structure N-well
isolation isolation
P+ diffusion (Sub. Ring) P+ diffusion (Sub. Ring)
isolation isolation
N-well / N+ diffusion N-well / N+ diffusion Ring
Figure 116. Guard Ring Layout for CMOS I/O and Array N-well Circuits
The guard rings for NFETs and PFETs are shown in Figure (A) and (B) respectively. The
N+/N-well Guard Ring for both NFETs and PFETs is connected to Vdd.
The I/O guard rings protect circuits connected to I/O pads against latchup.
Rules for I/O Guard Rings:

1. Any N+ diffusion connected to an I/O pad MUST lie within a substrate (P+) and a NWell guardring
(groundrule LUP13A-LUP13B). These circuits include:
OCD (off-chip driver NFETs), protect diodes, ESD protect circuit, pass transistors, diodes, bleed
transistors, diffusion resistors, etc.
Note: The NWell guardrings around a specific I/O book are allowed to merge with adjacent I/Os
guardrings. Also, internal to a specific I/O the NFETs NWell guardring can merge with the ESD
devices NWell guardring and/or the PFETs NWell guardring.
2. The NWell guardring specified in item #1 above must obey the following groundrule:
ESD10 (N-well-to-RX distance rule)
3. All p-channel transistors, or P+ diodes attached to I/O circuitry MUST be in a separate N-well which is

separate from other chip circuitry.

For isolation, an N+/N-well guard ring surrounds the N-well tub of the P+ diffusion or PFET struc-
ture.
The N-well guard ring is to be tied to Vdd or Vdd(I/O).
Minimum well-well space can be used.
When using separate N-well guard ring structures outside of the p-channels well structure,
this structure can be abutted to other separate N-well ring structures.
4. Those portions of the substrate bias charge pump or well bias generator circuits where the voltage is
biased below ground potential or above the supply voltage must fulfill the rules above (see I/O cir-
cuits). The same applies for voltage regulator or bootstrap circuits.
6.2.3 Latchup Design Guidelines

The following sections gives examples of good and bad design practices from a latchup perspective.
Guardring Design
Guardrings (NWell or substrate) should be contacted as frequently as possible and strapped with
metal wherever possible as shown in Figure 117, Guardrings (contact and metal strapping recommenda-
tions) on page 521. Latchup groundrule LUP13A-LUP13B ensures N+ diffusions/NFETs connected to I/O
pads are enclosed in both substrate and Nwell guardrings.
Guardring (substrate or Nwell)
Guardring
Contact
Metal
Figure 117. Guardrings (contact and metal strapping recommendations)

Substrate Contacts Between Adjacent N-Wells
A common occurrence is to have a substrate contact satisfying groundrules LUP02 and LUP04 occurring
between Nwells which are spaced near minimum distance apart. In this case the substrate resistance will be
higher than expected and the substrate contact wont be as effective in controlling the local substrate poten-
tial. Figure 118, Substrate Contact Occurring Between Adjacent NWells on page 522 shows an example of
a substrate contact meeting groundrules LUP02 and LUP04 but the substrate distance is met only by going
between NWells spaced closely together. Paths to substrate contacts to satisfy LUP02 and LUP04 between
minimum spaced Nwells should be avoided.
Substrate Contact
Distance => LUP02 or LUP04
Distance <= LUP02 or LUP04

R
NWell NWell
NFET
Figure 118. Substrate Contact Occurring Between Adjacent NWells

Electrostatic Discharge (ESD) Salicide-blocked FETs for ESD
7.0 Electrostatic Discharge (ESD)
7.1 Salicide-blocked FETs for ESD
To enhance the ESD robustness of I/O transistors it is recommended to add an OP layer to the transistor.
See Table 15, Design Truth Table on page 68 for a list of devices where special salicide blocking can be
applied.
ESDIODE is not supported within T3 isolation well. Salicide block ESD nfets (thin ox, thick ox 2.5-V or 3.3-V)
are allowed to be placed over T3 isolation well.
To simulate the silicide-blocked FET use two calls to the sblkndres model (one for the source-side resistor,
one for the drain-side resistor) in series with the appropriate FET model (e.g. the nfet model for the
thin-oxide FET) as shown in the below lumped sub-circuit. The sblkndres model is identical to the opndres
model, except that the end resistance is removed from the side connected to the FET and also the parasitic
capacitance outside the non-silicided region is removed for extraction purposes. Note, the sblkndres model is
asymmetric with the three nodes ordered as follows: INPUT, FET, SX (i.e. connect the second node to the
FET).
Layout with S/D blocked

PC
725 727
Source
CA
733
731
dD dS
RX
OP OP
Draw Level SBLK

over entire RX shape
RDrain RSrc for Salicide Blocked
FET Layouts
See Rule 736a
Figure 119. Salicide Blocked FET Layouts

Electrostatic Discharge (ESD) ESD Background and Experimental Data IBM
7.2 ESD Background and Experimental Data

Refer to the separate ESD Reference Guide document.
Note: The Design Manual ES# and EC# does not apply to the separate ESD Reference Guide, as this docu-
ment is independent of the Design Manual.
7.3 ESD Schematic level checks
7.3.1 General
This chapter of the design guide covers ESD design requirement to be checked using a schematic level
checking tool.
7.3.2 Definitions
LC power supply pad: Low-capacitance (< 100nF) power supply pad
7.3.3 ESD Schematic Checks
Table 235. ESD Schematic Rules
Rule Description Des

Min.
ESD0e All LC power supply pads must be connected to one of the below combination: -
A single HBM down diode satisfying rule ESD01a and one or more HBM
up diode satisfying rule ESD01b, or
A single HBM down diode satisfying rule ESD01a and one ESD NFET sat-
isfying rule ESD01c, or
A RC-triggered Power clamp satisfying rule ESD01d and a single HBM
down diode satisfying rule ESD01a.
See Figure 121. ESD Schematic Rule ESD0e on page 527 for additional infor-
mation.
ESD0d All I/O signal pads must be connected to one of the below combination: -
One HBM down diode satisfying rule ESD01a and one or more HBM up
diode satisfying rule ESD01b, or
One HBM down diode satisfying rule ESD01a and one ESD NFET satisfy-
ing rule ESD01c.
See Figure 123. ESD Schematic Rule ESD0d on page 527 for additional infor-
mation.

Electrostatic Discharge (ESD) ESD Schematic level checks
Table 235. ESD Schematic Rules
Rule Description Des

Min.
ESD0f Any two different types of ground pads (e.g. Digital/Logic Ground and Analog -
Ground) must be connected with an ESD Back-to-Back diode with the following
combination:
A single HBM diode satisfying rule ESD01a and a single HBM diode satis-
fying rule ESD01b.
See Figure 124. ESD Schematic Rule ESD0f on page 527 for additional infor-
mation.
ESD01a HBM down diode minimum perimeter. 110

ESD01b HBM up diode minimum perimeter. 220
ESD01c HBM NFET minimum width. 200
ESD01d Minimum sum of the widths of the Big NFETs of all instances of RC-triggered 4000
power clamps.
ESD11a 1.2/1.5V driver NFET minimum gate length. 0.15

ESD11bR 2.5V driver NFET minimum gate length. 0.30
ESD11dR 1.2/1.5V ESD NFET maximum gate length. 0.15
ESD11eR 2.5V ESD NFET maximum gate length. 0.30
ESD15a HBM down diode maximum anode to cathode spacing. 1.00
ESD15b HBM up diode maximum anode to cathode spacing. 1.00
ESD21 Only the following ESD FET options are permitted: -

Drain/Source silicide-blocked, gate-silicided (GS) single NFET.
ESD23 ESD NFETs SBLK width. 0.44
ESD24 1.2/1.5V ESD NFETs minimum SBLK width 2.00

ESD24a 2.5V ESD NFETs minimum SBLK width 3.00
ESD30 All receiver gates connected to an I/O signal pad must be connected to a CDM -
resistor and CDM devices.

Electrostatic Discharge (ESD) ESD Schematic level checks IBM
Vddx
RVddx
HBM
Diodes
CDM
Diodes
Receiver
CDM
Resistor
ESD
CVddx
I/O Pad Power
GND
Clamp
Vddx
GND
RGND
Figure 120. Schematic showing bi-directional I/O signal pad with HBM and CDM double diodes. Schematic also shows
ESD Power Clamp connected to Power bus.

Electrostatic Discharge (ESD) ESD Schematic level checks
Option A Vdd Option C Vdd
HBM HBM
Down Up Internal RC Internal
Diode Diode Clamp HBM
Circuitry Circuitry
Down
Diode
Gnd Gnd
Figure 121. ESD Schematic Rule ESD0e
VDD
INV1 INV2 INV3 BIG FET
GND
Figure 122. Typical RC-Triggered Power Clamps: Single RC-triggered Power clamp (rc_clamp)
Option A Vdd
HBM
Up
Diode Internal
HBM Circuitry
Down
Diode
HBM Network Gnd

Figure 123. ESD Schematic Rule ESD0d
Logic Gnd Analog Gnd
ESD Back-
to-back Diode
Figure 124. ESD Schematic Rule ESD0f

Design for Manufactureability Yield Enhancement Design Techniques IBM
8.0 Design for Manufactureability
8.1 Yield Enhancement Design Techniques

This section describes seven approaches that designers can use to make designs less sensitive to the ran-
dom manufacturing defects that impact wafer yield. These design optimization guidelines were generated fol-
lowing the development and use of critical area analysis tools on a wide variety of designs
1. Make designs as small as possible.
Smaller designs have just as good yield as larger designs, and allow more to be fit on a wafer. Use mini-
mum design rules when it makes the design smaller.
Good Better
2. Space out elements as much as possible.
Unless this approach grows the design beyond the available space, move elements as far apart as possi-
ble. If the design is wiring limited, spread out the devices, and vice versa. If white space exists, use it.
Good Better
3. Even out the wiring.
Within a layer, spread out the wires, and balance the wiring between levels. Avoid a very dense level
matched with a very sparse level.
Good Better

Design for Manufactureability Yield Enhancement Design Techniques
4. Avoid shorts.
Wiring shorts are a worse problem than open circuits; so, when space is tight, widen the spacing rather
than the wire.
Good Better
5. Avoid open circuits.
Most opens occur at contacts or vias, so use redundant contacts and vias.
Good Better
6. Do not add unnecessary wiring.
Without a specific electromigration or performance requirement, avoid redundant wires or fattening

existing wires. If you find a better way to make a connection, delete the old connection. Resistance of
local wiring is normally negligible compared to device conductance.
Good Better
7. Do not add excess contacts.
Two or three contacts are sufficient redundancy. Contacts placed a few microns away from salicide are
sufficient for low resistance. So, do not create unnecessary risks of CA-PC shorts.
Good Better
CA Only

Design for Manufactureability Yield Enhancement Design Techniques IBM
8.1.1 Recommended Non-minimum Design Rules for Yield
Enhancement
Follow rule 2 (Space out elements as much as possible. on page 528) and always use larger than mini-
mum design dimensions whenever possible, unless it results in increased chip size or decreased perfor-
mance. Using the following recommended rules will result in improved yields.
Table 236. Recommended Non-minimum Design Rules
Item Priority1 Description Non-minimum Design
50R 1 RX width 0.24
51R 1 RX area (m2) 0.14

52R 1 RX to RX space 0.26
100R 3 PC width not over RX 0.19
102R 3 PC to PC space 0.26
104R 2 (PC to PC) over RX 0.26
110R 2 RX overlap PC 0.33
111R 2 PC overlap past RX, when [(PC 0.25

intersect RX) to RX corner
0.08um] and [PC(END) area not
over RX < 0.046m2]
112R 4 PC overlap past RX, when (PC 0.30

intersect RX) to RX corner < 0.08
m
113R 4 PC to RX for low PC wiring capaci- 0.08

tance (except where PC is tied to
RX)
114R 4 PC to RX corner, for constant Weff 0.24
115R 4 PC corner to RX, when gate corner 0.24

and RX are on same FET; for con-
stant Leff.
132R 3 ((PC intersect RX) must have an 45.00

area (m2)
204R 3 CA within RX for no border leakage 0.14
207R 1 CA (over RX) to adjacent PC 0.14
209R 3 CA within PC 0.09

Design for Manufactureability Yield Enhancement Design Techniques

214R 2 Maximum percent (%) union (CA, 10
CABAR) permitted over a 25m x
25m localized area stepped in
12.5m increments
252dR 2 NW-NW space for area >300 m2 1.48

and NW width >6.0m
260aR 1 RX P+ within NW for [NW width 0.52

18.0m and ((not NW) width
18.0m)]
265aR 2 RX n+ to adjacent NW for (NW 0.52
width 18.0m)
266R - RX Substrate Contact to NW - Rec- 0.20

ommended for low resistance con-
tact
504R 1 M1 to M1 space ; (if at least one 0.36

metal line is >1.04 m wide)
506aR 2 M1 overlap past CA (for two oppo- 0.06

site sides)
571aR 2 M1 overlap past V1 for two opposite 0.06

sides
604R 1 M2 to M2, M3 to M3, M4 to M4, M5 0.36

to M5, M6 to M6 space ; (if at least
one metal line is >1.0m wide)
609R2,3 1 [(Mx width > 2.8m) intersect = -

M(x+1)] density must be 50% over
local 200m x 200m areas,
stepped in 100m increments,
where Mx = M1,M2, M3, M4, M5,
M6 and where M(x+1) = M2, M3,
M4, M5, M6 or MQ.
610R 2 Vx must be within Mx, for at least 2 0.09

sides, preferably opposite sides,
where x = 2-5
610aR 2 Vx must be within Mx for two oppo- 0.00

site sides, where x = 2-5
612R 1 Use redundant vias when possible = -

for Vx, where x = 1,2,3,4,5

Design for Manufactureability Design for Manufactureability Initiatives IBM
DG8cR 3 (PC touching DG) minimum space

to adjacent PC
1. A design rule with a lower number in this column is more important for yield enhancement than a design rule with a higher number.
This list is based on experience with prior CMOS generations.
2. This local density requirement is calculated using the intersection of consecutive metal shapes over which the checking box is
stepped. When the box steps over the chip boundary, the box is moved back in bounds. The metal density is calculated using
design layout data prior to IBM design services MxHOLE or MxFILL. See also Table 11, LM last metal Back End Of Line (BEOL)
Metallization Options on page 64 or Table 12, MA last metal Back End Of Line (BEOL) Metallization Options on page 65 for
consecutive level of metal information
3. This local density requirement limits the stacked metal pattern (directly above and below) using an intersection methodology for
compatibility with available checking tools.
8.2 Design for Manufactureability Initiatives

A key semiconductor manufacturing metric is good modules (packaged devices) per wafer start. This metric
id defined as follows:
(wafers to test/wafers started) x (die to test/wafers to test) x (good die / die to test) x (modules to test /
good die) x modules to burn-in / modules to test) x (good modules out / modules to burn-in) = good mod-
ules / wafer start.
Each of these ratios is either completely controlled by design team or jointly controlled by the design and
manufacturing teams. Good modules per wafer start really measures both design productivity and manu-
facturing operations productivity.
Significant productivity enhancements can be achieved by incorporating the following Design For Manufac-
tureability (DFM) initiatives into product designs. Tables 237 through Table 240 provide a brief description of
the DFM design actions: for further detail, consult your IBM technical representative.
Table 237. Design for Manufactureability Initiatives - Physical Design
DFM Description
Item
Number
AdjCheck (Paint) routing tool used on the back-end-of-line (BEOL) design to improve product
1.1
electrical performance and productivity.
Metal fill (and hole for copper) tools used to fill white space and cheese wide copper lines with
1.2
IBM-generated patterns to improve uniformity and productivity.
IBM electronic design automation (EDA) XRouter routing tool, with wire spreading enabled,
1.3
used on the BEOL design to improve product electrical performance and productivity.
Larger than minimum spacing used between wide metal bus lines and adjacent lines to
1.4
improve productivity.

Design for Manufactureability Design for Manufactureability Initiatives
Table 237. Design for Manufactureability Initiatives - Physical Design
DFM Description
Item
Number
IBM EDA Wirebender tool used on the BEOL design to improve product electrical perfor-
1.5
mance and productivity.
Redundant CAs and vias used wherever possible. IBM EDA via redundancy tool used on the
1.6
BEOL design to improve product reliability.
IBM-generated shapes used on front-end-of-line (FEOL) design at PC/RX levels to improve

1.7
uniformity and productivity.
Optimized WL/BL/subarray redundancy employed on array products and on imbedded cache

1.8
arrays in logic products. IDDQ test specifications consider the impact of failing bits.
Design optimized to improve defect resistance by using critical area analysis tools on array
1.9
cells and logic macros. Approved SRAM cells used.
1.10 Not applicable to CMRF8SF.
Product migration strategy (for example, photo shrinks) defined for both silicon and package
1.11
as part of the high-level product design step.
A cleanup design pass, test program update, and qualification scheduled for the produc-
1.12
tion-level design.
A chip size and chip aspect ratio that maximize the number of chips per wafer and the number
1.13
of chips within a stepper field have been chosen.
Polysilicon width expanded at PC/BP intersections to improve local PC series resistor (Rs)
1.14
control at intersection point.
Process monitoring structures included on-chip for failure analysis characterization and post-
1.15 dicing process history determination. Discrete devices wired to LM within the chip parameter
can be probed to determine, for example, Vt and Leff.
The design of test clock trees optimized to provide minimum scan path propagation delays,
1.16
and to allow minimum scan cycle times to reduce test time.
A suite of programs, Swampfinder, can be run to identify design sensitivities not covered by
1.17
design rule checking.
Customization of standard products is performed as late in the process as possible to maxi-

1.18
mize inventory flexibility and minimize postcustomization turnaround time.
Levels affected by RTM B have been minimized by reusing C4 and design levels to reduce
1.19
postcustomization turnaround time.

Table 238. Design for Manufactureability Initiatives - Electrical Design
DFM Description
Item
Simulations demonstrate that the design will have 100% circuit limited yield (CLY) at func-
2.1 tional test conditions (that is, the design is process window clean at all process corners: nomi-
nal, best case, and worst case).
Simulations indicate that critical design components and macros are functional at all process,
2.2 voltage, and temperature corners and at test, DVS, EVS, and BI applied conditions. Use of
tools such as ASX/Q encouraged.
Product performance at nominal process and VDD conditions is higher than the market perfor-
2.3 mance objective. Performance 2s above the target market performance requirement is the
objective so that line tailoring is unnecessary and sort requirements can be minimized.
If this design is a follow-on design (for example, GR to GQ to GP, and so forth), then the new
2.4 design incorporates fixes for all functionality and CLY issues documented in the previous
products integrated product development (IPD) problem log.
Performance monitoring techniques are included on-chip for die-by-die performance screen-
ing. Monitor techniques capable of detecting both FEOL and BEOL performance contributions
2.5
are recommended. A minimum of five flushable scan chains are included to enable
across-chip performance measurements at wafer level functional test.
Logic synthesis tools such as IBM BooleDozer II are used for improved product perfor-
2.6
mance, time to market, and productivity.
Array products, and logic products with large cache designs, selectively use Vt adjustment
2.7 implants to control Ioff and IDD. Contact your IBM technical representative for information on
the availability of Vt adjustment process options for the technology of interest.
Electronic chip ID (ECID) circuitry is integrated into a scan chain design so that lot, wafer, and
2.8 chip ID are available at chip and module assembly points post fuse blow. ECID latches are
located at the end of a scan chain.
The design supports IDDQ testing by eliminating dc paths in logic other than reference voltage
generation and limited ground-to-PFET NOR structures. An IDDQ control pin is used to shut
2.9
off components such as all IDD paths, ratioed logic, PLLs, other internal oscillators, and resis-
tors.
A thorough analysis of the impact of noise upon product function has been completed. Noise
limits have been established for OVDD, AVDD, and VDD. The impact of the BEOL attributes
2.10
(for example, wire length, parallel wiring runs, IR drops at interconnects, and asynchronous
coupling voltages) upon noise generation have been considered and found acceptable.
For analog and mixed-signal designs, a full four-corner simulation has been conducted around
2.11
critical parameter pairs (for example, beta and resistance).
Dual-port arrays have been replaced by single-port double-clocked arrays to reduce critical
2.12
area for equivalent function.
2.13 I/O reduction techniques on I/O-limited designs have been considered.

Table 239. Design for Manufactureability Initiatives - Test/Characterization Design
DFM Description
Item
Array and logic products with large caches employ physical, electrical, and test design
3.1 approaches that enable filibuster testing to detect and eliminate VDD to ground shorts within
the array.
Array and logic products with caches of 32 K bits or larger follow array built-in self test (ABIST)
3.2 diagnosable design rules, so that bit mapping of memory defects is possible at wafer level
testing.
Prefuse testing of redundant elements is conducted on all redundant elements in array and
3.3
logic products.
For high-performance products, maximum di/dt during test has been used to validate DIB
3.4
design to eliminate yield losses resulting from VDD drop during testing.
Forward-bias contact tests have been designed with sufficiently high Iforce to ensure accept-
3.5
able (that is, low) levels of contact resistance for the device under test.
Product T2/SQ characterization plan includes sufficient hardware and process splits to gener-
3.6 ate the data necessary to support the launch DCP and the required manufacturing volume
ramp.
Product design supports level-sensitive scan design (LSSD) testing to enable high fault cover-
age, reduced test engineering resources, and improved problem resolution turnaround time.
3.7 The number of scan chains must fit the target tester, and the scan chains must contain a bal-
anced number of latches to minimize test times. Scan-in and scan-out operations should be
overlapped.
Built-in self-test (BIST) is used for embedded SRAM and DRAM, logic, and analog macros to
3.8
reduce test equipment requirements and enable parallel test.
The number of test vectors should be minimized, and vector order and IDDQ tests should be
3.9 optimized to reduce test cost on high-volume programs. (Diagnostic considerations may dic-
tate alternate solutions to support initial program debug and failure analysis.)
The test design includes reduced pin count test (RPCT), I/O wrap, pin dotting, pin banking,
3.10
and parallel test (multi-DUT).
AC testing is most efficiently implemented using LSSD-based delay testing to provide high
3.11 fault coverage with reasonable test equipment requirements. The product design enables ac
delay testing by including on-product clock generation (OPCG), and ac I/O wrap.
3.12 For all ac or at-speed testing, the test environment is completely modeled and understood.
Test methodology for the design, including embedded digital and analog macros, has been
3.13
reviewed with the DFT team and approved by test analysis engineering.
For high-volume programs, consider the Reliability Optimized for Characterization, Kost, and
3.14 Yield (ROCKY) process, where additional data is collected before volume ramp and statistical
data analysis are used to determine the optimal test screens and limits.

Table 240. Design for Manufactureability Initiatives - Diagnostics /Debug/FA-Friendly Design
DFM Description
Item
The design includes a diagnostic/failure analysis (FA) strategy jointly developed by the prod-
uct design, test, diagnostics (D/G42), and failure analysis groups. The design adheres to the
scan rules as verified by IBM TestBench TSV, and BIST design rules maintained by G42.
4.1
Deliverables to the BTV manufacturing and FA team include logical and physical design
descriptions, L2L logical to physical cross-mapping database, and information required to per-
form wafer-scale electrical and physical failure analysis of failures.
4.2 A diagnostic solution has been identified and documented in manufacturing for each AVP test.
On-chip structures that facilitate FIB device modification are in the design where appropriate.
These include backside and/or frontside structures to support FIB work, such as navigation
4.3 references, memory address verification marks, probe points, severable links, spare wires,
spare logic, and backside FIB DM circuits. Fill-shape exclusion zones are used to protect FIB
areas as needed.
ABIST test patterns are available that enable logical-to-physical bit failure map verification
4.4 using a photon emission technique to view the activated cell. This technique has an improved
turnaround time compared to traditional FIB verification techniques.
Physical failure analysis design data and documentation requirements:

L2L logical to physical cross-mapping database
4.5 Design description document describing test modes, scan chain configurations, pattern
odometers for IDDQ
patterns.
Shapes (gl1 or gds2)
Table 241. Design for Manufactureability Initiatives - Packaging Design
DFM Description
Item
5.1 The design uses an existing off-the-shelf package.
5.2 Newly designed package lids are designed for automation.
New chip/package designs maximize interconnect pitches where possible without creating I/O
5.3
limited designs and increasing die area.
5.4 The design employs a shrink invariant wire-bond pad footprint.
5.5 The design employs a shrink invariant C4 pad footprint.
5.6 The design uses a common pad footprint for wire-bond designs.
5.7 The design uses a common pad footprint for C4 designs.
5.8 The design uses optimized C4 diameter/design for the specific package chosen.

Table 241. Design for Manufactureability Initiatives - Packaging Design
DFM Description
Item
An economic analysis of system-on-a-chip (SoC) versus system-in-package (SiP) architecture

5.9
has been completed.
5.10 An economic analysis of wire-bond versus C4 options has been conducted.
5.11 Enable reuse of existing C4 masks by using an existing image/package

Standard and Dense SRAM Designs IBM
I.0 Standard and Dense SRAM Designs

IBM has designed and qualified recommended static random access memory (SRAM) designs for the
CMRF8SF technology. The recommended cells for this technology have the characteristics shown in Table
242.
Table 242. Recommended SRAM Cell Characteristics
Cell Type WL Pitch (m) BL Pitch (m) Area (m2) Bit Line WL Strap
Standard 1.90 1.30 2.47 M2 M1
Dense 1.70 1.20 2.04 M2 M1
Note: SRAMxx levels may be required to prevent mask process data preparation on the SRAM itself. Consult
your IBM technical representative for specific SRAM requirements and detailed information about these
designs.

Guidelines for Optimal Model-Hardware Correlation
J.0 Guidelines for Optimal Model-Hardware Correlation

Listed below are some general guidelines (not all-inclusive) for achieving good model-to-hardware correla-
tion.
1. Avoid device widths less than 0.30 m.
2. Include N-well sheet resistance in simulations to reflect local transient bias variations.
3. Avoid using minimum width polysilicon and diffusions where resistance is critical to performance. Sheet
resistance is generally higher and more variable in minimum width lines. (See Section 4.29 , Conducting
Film Thickness on page 412.)
4. Avoid using single source or drain contact placement on wide devices. Avoid situations where any PC
gate edge is greater than 1 m from a contact. The FETs drive current is particularly sensitive to extra
resistances coming from CA and silicide at the source side. It is a good practice to put as many CAs as
possible at a relaxed PC to CA distance of 0.14um. The area junction capacitance of the source side in
general does not contribute to the capacitive loading, so increase the source side diffusion area to avoid
CAs landing partially on STI under worst case process tolerances. This reduces the CA resistance toler-
ance.
5. Avoid minimum values of rules 114 and 115; use the recommended rules 114R and 115R. Minimum val-
ues of these rules result in device width uncertainties.
6. Avoid use of bent gates. Although permitted, bent gates can degrade models.
7. Model long runs of wire as distributed wire delays.
8. Ensure that n-well proximity effects are either negligible (that is the n-well edge is at least 3m from the
FET). Additional information on dummy design level VTSENS is in Table 30, VTSENS (Threshold Volt-
age) Layout Rules, on page 127. Note that thick oxide devices are very sensitive to proximity effects as
described in Section 4.3.6.6 , Threshold Voltage Near NW or BF or BT edges on page 345, and Section
4.3.6.8 , Guidelines for Device Matching on page 345.
9. Consider the impact of mechanical stress induced during wafer processing on FET devices (see Section
4.3.6.7 , Mechanical stress effect on FETs on page 345).

Total Standby Current (Idd) IBM
K.0 Total Standby Current (Idd)

The standby current in short channel MOSFETs (Lpoly >0.07 m) due to subthreshold leakage may be
approximated by Ioff(Lp) for W > 0.4 um and 0.9 V Vds 2.1 V :
( L p dL ) L 1 ( L p dL ) L 2 (1)
I off (L p) = ( I 1 ( T )e + I 2 ( T )e )(1 + )
where, = A1 exp ( A2 ( ( Lp dL ) ) ) exp ( Vds 0.9 ) exp ( A3 ( 25 T ) ) ( Vds 0.9 )
B 1 ( T 140C )
I 1 ( T ) = I 10 e (A/m) (2)
B 2 ( T 140C )
I 2 ( T ) = I 20 e (A/m) (3)
L1 = L11 + L12 ( T 140 )
L2 = L21 + L22 ( T 140 )
and where Lp is the (wafer level) gate length, dL=-0.003, and I1 and I2 are a function of temperature (T). A die
centered at an Lp of Ldie-mean contains MOSFETs with Lp varying about this mean by an amount described
by the ACLV specifications in Table 121, Gate Length Variation for thin oxide FETs (3s) on page 342. Inte-
gration of this ACLV distribution (presumed to be gaussian) against the above Ioff equation summed with the
leakage component yields:
I ddFET = W tot ( C 1 + C 2 ) (4)
1 1
--- ( ACLV L 1 ) 2 --- ( ACLV L 2 ) 2
( L p dL ) L 1 2 ( L p dL ) L 2 2
C 1 = I 1(T ) e e + I 2(T ) e e
1 1
--- ( ACLV L 3 ) 2 --- ( ACLV L 4 ) 2
( L p dL ) L 3 2 ( L p dL ) L 4 2

C 2 = --------------------------------- I 1(T ) e e + I 2(T ) e e
exp ( A2L p )

L1
with L3 = ------------------------
1 + L1A2
L2
L4 = ------------------------
1 + L2A2
where CLV is ACLV/3 (ACLV is a 3-sigma number). Table 121, Gate Length Variation for thin oxide FETs
(3s) on page 342, characterizes the variation in MOSFET channel length about the die-mean Lp. Wtot is the
total width of all MOSFETs in standby state per device type.

Total Standby Current (Idd)
Table 243: Idd Parameters
Device type I10 I20 L11 L12 B1 B2 L21 L22 A1 A2 A3

(A/m) (A/m) (m) (m) (/C) (/C) (m) (m) (-) (1/um) (1/C)
Reg Vt NFET 0.0015 2.1e-8 0.0065 2e-5 -0.019 0.038 0.12 0.0 100 50 0.0005
Reg Vt PFET 0.005 7e-8 0.006 1.5e-5 -0.006 0.025 0.05 1.6e-4 15 30 0.0005
The following is an example of how the standby current Idd would be calculated for a chip with Wtotal =107m
per device type, nFET Ldie-mean=0.07/0.081/0.092 m at T=85C. For simplicity, the total width of MOSFETs
that have VDS=1.5V in the standby state is assumed to divide evenly between NFET and PFET.
The chip standby current caused by the regular-Vt FETs can be calculated from equation (4) where:
Ldie-mean = 0.07m, 0.081um, 0.092 um

Wtotal = 107m of NFETs+107m of PFETs
CLV = 1 sigma of ACLV =0.014/3 m = 0.0047
The total standby current is calculated to be 750mA, 144mA, and 64mA respectively. We used for ACLV 14nm
instead of the target of 11nm. This larger number is to be used for chips entering the technology in the
pre-production mode. During maturity of the technology, this will go down to the target.
For some other leakage components, the following guidelines can be used (3-sigma values are given) per unit
design width (@25C):
Fet Ioff : 600pA/um
Igate : 25 pA/um
IGIDL : 5 pA/um
junction : 1 pA/um
Minimum design rules are assumed. Check Section 4.0 , Electrical Parameters and Models on page 335 for
more detailed numbers.

Design Hierarchy Guidelines IBM
L.0 Design Hierarchy Guidelines

The following general guidelines and practices significantly improve hierarchical verification run time and
ease of debugging. Not following these guidelines can adversely impact mask house and data preparation
turn around time.
1. Wherever possible, design to facilitate reuse of circuits. For example, if a 2 way NAND gate is needed,
reuse one that is already designed if possible.
2. Put all needed shapes to make a circuit in the same cell. Don't create transistors by bumping poly from
one cell over RX in another cell. Put the NW and BP shapes in the cell where the transistors are formed.
3. Make each cell ground rule correct. For example, don't place contacts in a cell without metal covering
them.
4. When a cell lower in the hierarchy must be intruded upon, do it as low in the hierarchy as possible. For
example, don't wait until the prime cell to program decoders. Place the programmed decoders in the next
higher level of the hierarchy.
5. Strive for rectangular shaped circuits. L shaped circuit layouts have lots of intrusions which slow down
the checker.
6. Don't do anything at the top (prime) cell which changes things like transistor width, length or connectivity
at the bottom.
7. Large hollow structures like substrate rings (which basically intrude on the entire chip) should be built by
placing 4 cells in the prime. One would be the top one might be the left, the right and the bottom.
This way there is no interference with anything these cells don't actually come near.
8. Avoid any names with special characters. Use 0-9 and a-z on cell names, level names and port names.
Always start with an alphabetic character.
9. Make connections as low in the hierarchy as possible. The closer to the prime, the harder it will be to
debug any wiring errors.
10. Avoid 'holding levels' of hierarchy where there are only transforms and no shapes. Some tools spend a lot
of time resolving nothing.
11. Too much hierarchy of the wrong kind may be a problem. For example, circuits laid out with each individ-
ual shape residing in it's own cell would be self-defeating.
12. Only output 1 prime cell. Some design tools (like IBM's IGS) allow multiple primes to be output.
13. Nest each large discrete design component (such as a cache or FPU) as an individually named model.
This is particularly helpful if the structure occupies a large fraction of the chip (20 percent or more). Also,
nest repeated sub-units of large discrete design components as individually named models.
14. Avoid overlapping large models. For instance, avoid using overlapping registration marks to align mod-
els.
15. For large chips (>200 mm2), making preliminary data available to the mask house is strongly encouraged.

Rule Syntax (Definitions)
M.0 Rule Syntax (Definitions)

The terms below are useful in understanding and applying the layout ground rules.
45 DEGREE - When applied to an edge of a shape, it means an edge that is 45 degrees from the X/Y
design grid axis. When applied to a shape, it means a shape with a 45 degree edge.
ABUTS - Specifies the condition whereby a shape on one level(A) shares an edge with any shape on
another level(B) such that the shapes do not have any area in common, and they only touch along a com-
mon edge.
AREA - Rule applies to shape area, not a linear dimension. See Figure 125, Figures for Definitions on
page 545.
BUTTING - See ABUTS.
CENTER - Describes the center point of a shape. Most commonly used for the center of a circle or octa-
gon.
COINCIDENT: The condition whereby a shape on one level (A) shares an edge with any shape on
another level (B) such that the shapes have area in common.
COMMON RUN - Distance that two shapes run parallel. This applies even if the shapes turn, so long as
the minimum space between them does not effectively change. (UNBENDED COMMON RUN refers to
the distance of run segments that do not turn.) This applies to one or two shapes, not more than two. See
Figure 125, Figures for Definitions on page 545.
COVERED, COVERED BY, MUST BE COVERED, MUST BE COVERED BY, See WITHIN or MUST BE
WITHIN
DIFFERENCE - Difference [A,B] means the same as the boolean A minus (subtract) B. Same as A not
over B.
ENCLOSED AREA - See Figure 125, Figures for Definitions on page 545.
EXACT - rule can have no other values than that specified exactly
FLOATING GATE - A gate that is not electrically connected to N+ or P+ junction by M1.
INTERSECT - Boolean AND. See Figure 125, Figures for Definitions on page 545.
LENGTH - The long dimension of a rectangle.

NOTCH - Space from outside edge to outside edge on a single polygon
OVER - Equivalent to INTERSECT. NOT OVER implies the inverse of OVER, or COMPLIMENT INTER-
SECT.
OVERLAP OF - The minimum distance from the inside of shape L to the inside edge of M when L inter-
sects M. See Figure 125, Figures for Definitions on page 545.
OVERLAP PAST - The minimum distance from the outside edge of J to the inside edge of K when J inter-
sects K. See Figure 125, Figures for Definitions on page 545. For example, M1 overlap past CA for at
least two sides 0.10 means that M1 and CA intersect, and that the M1 must extend beyond two or more
sides of the CA square by 0.10 m.

Rule Syntax (Definitions) IBM
PC - PC is a vector of length less than or equal to Rule-102 at design dimension measured between two
90 degree corners inside the shape.
SIZED BY - the statement C sized by n m means that all shapes on level C sized by n m per edge,
where n is either positive (expanded) or negative (shrunk).
SPACE - see TO.
STRADDLES - Crosses the border of a shape. For example, RX straddles NW means that part of the RX
shape overlaps the NW and part of the RX shape extends beyond the edge of the NW.
TO - Distance between two shapes. See Figure 125, Figures for Definitions on page 545. This fixes a
space (>zero) between two shapes. A spacing =0.00 is not allowed unless explicitly stated.
TO ADJACENT (WHEN SHAPES DO NOT INTERSECT) - Same as TO except shapes that intersect
are not subject to checking.
TO ADJACENT (DIFFERENT NET) - Same as TO except that shapes which are electrically on the
same net are not subject to checking. The net connection may be through any level up through the final
level of metal.
TOUCH, TOUCHING - When any part of one shape shares any part of the area or edge or even point of
another shape, they are touching. They are touching even if they only share one common vertex.
TOUCH is also sometimes referred to as HIT.
UNDER - Equivalent to INTERSECT.
UNION - Boolean OR. See Figure 125, Figures for Definitions on page 545.
VERTEX/VERTICES/CORNER - Intersection of two edges of same shape. Includes 45 and 90 degree

corners.
WIDTH - Distance between inside edges of a shape. Width is measured on edges that are parallel or
form an angle of less than 90 degrees.
WITHIN - For example, CA within M1 0.10 means that shape M1 encompasses shape CA and that every
point of CA must be at least 0.10 inside the nearest point on shape M1.
WITHIN (or COVERED or COVEREDBY) means that either of the two shapes can be present by itself
without the other shape being present.
MUST BE WITHIN (or COVERED or COVEREDBY)- This is the same as WITHIN except that, for exam-
ple, CA must be within M1 requires each and every CA shape to have an M1. CA cannot exist without M1.
However M1 can be present without CA.

Rule Syntax (Definitions)
C
Shape A
D
Shape B
Area of shape A Enclosed Area of shape B C intersect D
K
E
G J K overlap
past J
J overlap past K
F
H
Union (E,F) K overlap past J

G within H
L L
L
GR 100
M PCEND
M M
PC GR 100
L overlap of M equivalent to M overlap of L
P Q P Q P
x z
y
LM
xyz
111 P to Q
011 P to adjacent Q (where P does not intersect Q)
001 P to adjacent Q (different net)
Common Run=
(0 means it is not checked; 1 means it is checked)
A A A B
B =
A abuts B
difference (A,B)
Figure 125. Figures for Definitions

Definitions of Process-Related Terms IBM
N.0 Definitions of Process-Related Terms

BIAS - Bias is the difference between the design dimension and the nominal wafer dimension:
Bias = Wafer Nominal (WAF NOM) - Design Dimension (DES DIM) (GL1)
BIAS SIGN - A positive bias means the dimension of the image on the wafer is bigger than the corre-
sponding design shape in GL1. A negative bias means the dimension of the image on the wafer is
smaller than the corresponding design shape in GL1.
BLM: Bump Limiting Metallurgy
DESIGN MINIMUM (DES MIN) - The minimum design dimension allowed by photo, etch, fill and electrical
considerations. This is the design minimum given in the layout rules.
FORESHORTENING - A more negative bias at the end of a narrow line than at the sides.
HOLE - Where resist is removed by the photo process.
ISLAND - Where resist remains after photo process.
LDD - Lightly Doped Drain
NET BIAS AND TOLERANCE - The bias and tolerance used in Layout Rules are the net biases and tol-
erances. For bias, this is the algebraic sum of the component biases. For tolerance, this is the root-sum-
square (RSS) of the component tolerances. Components are photo, etch, slope, film thickness, etc.
TOLERANCE (TOL) - Variation in the process gives rise to variation in the feature dimension specified in
the layout rules tables. The extent of this variation above or below the nominal is called the tolerance. Tol-
erance as used in this publication means net tolerance. The Tol specified in this document is a 3
value. For calculating layout ground rules, the Tol is multiplied by 4/3 to arrive at a 4 value, which is
approximated to be the 4.5 for a batch population that is used in the Motorola 6methodology.
TOTAL BIAS - Same as Net Bias.
UBM - Under Bump Metallurgy
WAFER NOMINAL or WAF NOM or WAF or NOM - The nominal or target dimension of a design shape
as measured on the wafer.

Migration into Future Technologies
O.0 Migration into Future Technologies

There are concerns for migrating designs into future technologies that are known but cannot be fully quanti-
fied at this time. The following is a list of concerns for migrating designs into future technologies.
1. There are a number of PC line interactions over oxide that could be problematic for implementing
future mask techniques. PC rules are only now being developed for future technologies. In general,
one should use a more relaxed PC width when it is used for PC wiring (over oxide). PC wiring can be
defined as PC (Rule#115R) away from RX. As these complex rules evolve, more design conditions
could be forbidden. Also, PC wiring rule mentioned above may be too restrictive in some design
cases.
2. Device interactions for rules like111, 112, 113, 114, 115, 207 and 208 have been difficult to shrink
into subsequent technologies. These rules should be relaxed if such scaling is desired.
3. As in past technology migrations, the Terminal Metal (TV, DV, LV) rules do not scale. In general, this
impacts Fuse, C4, Wirebond and Chip Guard Ring rules.
4. ESD rules will not scale into future technologies.
5. Other IO related devices have not been scaled in the past; OP and DG rules should be relaxed if
future scaling is desired.

Design Preparation Complex Optical Manipulations IBM
P.0 Design Preparation

Section 2.5 , Level Generation and Design Preparation on page 59 as well as this section briefly describes
the pre-mask DataPrep routines required prior to mask build. Compensations are given in m per edge.
P.1 Complex Optical Manipulations

OPC (Optical Proximity Correction), SLB (Selective Linewidth Bias) and other complex optical manipulations
are outside the scope of this document. Information may be obtained from your technical representative.
P.2 Dense SRAM Design

The Dataprep for Dense SRAM builds may require the generation of D1 and CF and VE levels for M1 and CA
and V1 mask layers, respectively. Consult your technical representative for more detail.
P.3 PC
Other more complex OPC manipulations are done for PC layer. Consult the Data Preparation Specification or
your technical representative for more detail.
P.3.1 DGxxGATE
DGNGATE = [({[PC over (RX sized by 0.08)] over DG} not over BP) not over ZEROVT] sized by 0.005
DGPGATE = [({[PC over (RX sized by 0.08)] over DG} over BP) not over ZEROVT] sized by 0.005
P.3.2 PC Fuse
The PCFUSE shape is merged onto the PC mask in DataPrep.
P.4 Far BEOL Manipulation

TV:(C4 builds only)
TV = TV octagon converted to a circle; expand TV circle radius by +8.5um.
TD: (C4 builds only)

TD = least enclosing orthogonal rectangle of TV octagons sized by +15.0um per edge.
FV:(C4 builds only)
FV = FV octagon converted to a circle; expand FV circle radius by -0.74um.

Pattern Fill Rules xxFILL and xxHOLE Generation
Q.0 Pattern Fill Rules

Consult your IBM technical representative to obtain the most up-to-date pattern fill information.
Q.1 xxFILL and xxHOLE Generation

These rules are included to provide the designer guidance when checking and simulating designs that have
received IBM generated RX, PC and Metal FILL, and Metal HOLE shapes. For more information Section
2.10 , Pattern Density Rules on page 87. For designs using the IBM Mask House facility, these routines will
be run within IBM; consult your PE representative for more detail.
Note that any nominal violations of these rules indicate a deficiency with the IBM FILL and HOLE generation
tools. Nominal violations of these rules are primarily the responsibility of IBM Manufacturing and IBM Design
Services to resolve, particularly rules PD1a, PD2, PD4a, PD4a1, and PD4b. The customer will only be asked
to reexamine the design if a nominal violation can not be waived and can not be brought into compliance by
modifications to the Design Services Shapes Generation tools. Such problems can be best avoided by careful
attention to the rules in section Q.2, Recommended Design Practices Related to Generated FILL and
HOLES Shapes on page 575.
The following levels are not filled during standard IBM FILL generation: LY, E1, MA, AM, OL, and LD. IBM
FILL is available by special request but requires manual intervention in the automated Foundry Release pro-
cess. Such manual intervention will typically cause a delay in mask build. Fill placement is done in accor-
dance with the rules laid out in Table 244. xxFILL Rules on page 549; consult your PE representative for
more detail.
Table 244. xxFILL Rules
Rule Description Design Current

Min Practice.
(Rule
Number)
DS100 RXFILL must not touch {RXFILL, RX, PC, PCING, PCFUSE, - -
(LOGOBND1 not touching CHIPEDGE), PROTECT, KERFEXCL,
RXEXCLUD2}
DS100a3 RXFILL must not touch (MTFUSE, LMFUSE) - -
DS101 RXFILL minimum space to RX 0.40 0.60

DS102 RXFILL minimum space to {PC, PCING, ((LOGOBND 1 not touch- 0.20 0.60
ing CHIPEDGE) with straddling prohibited), PROTECT, KER-
FEXCL, RXEXCLUD 2}
DS103 3 RXFILL minimum space to (MTFUSE, LMFUSE) 9.00 9.00
DS104 RXFILL minimum space to PCFUSE 2.00 3.00

DS105 RXFILL minimum space 0.20 0.30

Pattern Fill Rules xxFILL and xxHOLE Generation IBM

Min Practice.
(Rule
Number)
DS105a4 (RXFILL touching (IND or BFMOAT or IND_FILT or BONDPAD)) 0.20 0.60

minimum space
DS106 (RXFILL not touching (IND or BFMOAT or IND_FILT or BONDPAD)) 0.32 0.90
minimum width
DS107 (RXFILL not touching (IND or BFMOAT or IND_FILT or BONDPAD) 1.80 0.90
maximum width
DS108 (RXFILL touching (IND or BFMOAT or IND_FILT or BONDPAD)) 0.32 0.60
minimum width
DS109 (RXFILL touching (IND or BFMOAT or IND_FILT or BONDPAD)) 1.80 0.60
maximum width
DS110 RXFILL within NW 0.30 0.40
DS111 RXFILL minimum space to NW with straddling prohibited 0.30 0.40
DS120 RXFILL within JD 0.80 0.80
DS121 RXFILL minimum space to JD with straddling prohibited 3.00 3.00
DS130 RXFILL within BB 1.50 1.50
DS131 RXFILL minimum space to BB with straddling prohibited 0.56 0.56
DS135 RXFILL minimum space to RN with touching prohibited 1.00 1.00
DS198 RXFILL must be square - -
DS199 RXFILL must be within CHIPEDGE 0.00 0.00
DS200 PCFILL must not touch (PCFILL, RX, PC, PCFUSE, LOGOBND, - -
PROTECT, KERFEXCL, PCING, PCEXCLUD 2)
DS200a 3 PCFILL must not touch (MTFUSE, LMFUSE) - -
DS201 PCFILL minimum space to (PC, PCING) 0.40 0.60

DS202 PCFILL minimum space to (RX, LOGOBND, PROTECT, KER- 0.20 0.60
FEXCL, PCEXCLUD 2)
DS203 3 PCFILL minimum space to (MTFUSE, LMFUSE) 9.00 9.00
DS204 PCFILL minimum space to PCFUSE 2.00 3.00

DS205 PCFILL minimum space 0.20 0.52
DS205a 4 (PCFILL not touching (BFMOAT or IND or IND_FILT or ((LM inter- 0.20 0.52
sect LM_RFLINE) sized by 3.1m) or ((MA intersect MA_RFLINE)
sized by 3.1m) or BONDPAD)) minimum space


Min Practice.
(Rule
Number)
DS205b 4 (PCFILL touching (BFMOAT not over (IND or IND_FILT or ((LM 0.20 0.60
intersect LM_RFLINE) sized bY 3.1m) or ((MA intersect
MA_RFLINE) sized by 3.1m) or BONDPAD))) minimum space
DS205c 4 (PCFILL touching ((IND or IND_FILT or ((LM intersect LM_RFLINE) 0.20 0.68
sized by 3.1m) or ((MA intersect MA_RFLINE) sized by 3.1m) or
BONDPAD) or (BFMOAT over (IND or IND_FILT or ((LM intersect
LM_RFLINE) sized by 3.1m) or ((MA intersect MA_RFLINE) sized
by 3.1m) or BONDPAD)))) minimum space
DS206 (PCFILL not touching (BFMOAT or IND or IND_FILT or ((LM inter- 0.33 0.68
sized by 3.1m) or BONDPAD)) minimum width
DS207 (PCFILL not touching (BFMOAT or IND or IND_FILT or ((LM inter- 1.80 0.68
sized by 3.1m) or BONDPAD)) maximum width
DS208 (PCFILL (touching (BFMOAT not over (IND or IND_FILT or ((LM 0.33 0.60
intersect LM_RFLINE) sized by 3.1m) or ((MA intersect
MA_RFLINE) sized by 3.1m) or BONDPAD)))) minimum width
DS209 (PCFILL (touching (BFMOAT not over (IND or IND_FILT or ((LM 1.80 0.60
intersect LM_RFLINE) sized by 3.1m) or ((MA intersect
MA_RFLINE) sized by 3.1m) or BONDPAD)))) maximum width
DS210 (PCFILL touching ((IND or IND_FILT or ((LM intersect LM_RFLINE) 0.33 0.52
by 3.1m) or BONDPAD)))) minimum width
DS211 (PCFILL touching ((IND or IND_FILT or ((LM intersect LM_RFLINE) 1.80 0.52
by 3.1m) or BONDPAD)))) maximum width
DS220 PCFILL within JD 0.80 0.80
DS221 PCFILL minimum space to JD with straddling prohibited 3.00 3.00
DS230 PCFILL within BB 1.50 1.50
DS231 PCFILL minimum space to BB with straddling prohibited 1.50 1.50
DS235 PCFILL minimum space to RN with touching prohibited 1.00 1.00
DS298 PCFILL must be square - -


Min Practice.
(Rule
Number)
DS299 PCFILL must be within CHIPEDGE 0.00 0.00
DS500 MxFILL must not touch (Mx, MxFILL, KERFEXCL, LOGOBND, - -
PROTECT, MxEXCLUD 2); Mx = M1-M6, MQ, MG, LM
DS502 (M1FILL, M2FILL) minimum space to PCFUSE with touching pro- 2.00 3.00
hibited
DS511 MxFILL minimum space to Mx; Mx = M1-M6 0.30 0.40
DS512 MxFILL minimum space to (LOGOBND, PROTECT, KERFEXCL, 0.20 0.40
MxEXCLUD 2 ); Mx = M1-M6
DS513 3 MxFILL minimum space (MTFUSE, LMFUSE); Mx = M1- M6 9.00 9.00
DS515 MxFILL minimum space; Mx = M1- M6 0.20 0.30
DS515a 4 (MxFILL touching (IND or IND_FILT or BONDPAD)) minimum 0.20 1.20

space; Mx = M1- M6
DS515b MxFILL minimum space to (LM over LM_RFLINE) with touching 2.90 2.90
prohibited; Mx = M1- M6
Notes:
1. (LM_RFLINE not over LM) is allowed to touch MxFILL
2. MA_RFLINE is allowed to touch MxFILL
DS515c (MxFILL touching (RF_MODFILL not over(IND or IND_FILT or 0.20 1.00
BONDPAD))) minimum space; Mx = M1-M6
DS515d MxFILL minimum space to Kx with touching prohibited; Mx = 1.00 1.25
M2-M6, Kx = K2-K6 (x must be the same number in each term)
DS516 (MxFILL not touching (IND or IND_FILT or BONDPAD or 0.35 0.90
RF_MODFILL)) minimum width; Mx = M1- M6
RF_MODFILL)) maximum width; Mx = M1- M6
DS518 (MxFILL touching (IND or IND_FILT or BONDPAD)) minimum width 0.35 0.60
; Mx = M1- M6
DS519 (MxFILL touching (IND or IND_FILT or BONDPAD)) maximum width 2.40 0.60
; Mx = M1- M6
DS519a (MxFILL touching (RF_MODFILL not over (IND or IND_FILT or 0.35 0.80
BONDPAD)) minimum width; Mx = M1- M6
DS519b (MxFILL touching (RF_MODFILL not over (IND or IND_FILT or 2.40 0.80
BONDPAD)) maximum width; Mx = M1- M6


Min Practice.
(Rule
Number)
Note: See Rule DS500 for MQ, MG, LM must not touch requirements = - = -
DS521 MxFILL minimum space to Mx; Mx = MQ, MG, LM 0.40 0.80
DS522 MxFILL minimum space to (KERFEXCL, LOGOBND, PROTECT, 0.40 0.80
MxEXCLUD 2; Mx = MQ, MG, LM
DS522a5 MxFILL minimum space to (BONDPAD touching LM) with touching 4.90 4.90
prohibited; Mx = MQ, MG, LM.
DS522b MxFILL minimum space to (LM over LM_RFLINE) with touching 3.30 3.30
prohibited; Mx = MQ, MG
Notes:
1. (LM_RFLINE not over LM) is allowed to touch MxFILL
2. MA_RFLINE is allowed to touch MxFILL
DS522c6 LMFILL minimum space to (LM over LM_RFLINE) with touching 3.30 3.30
prohibited
Note: (LM_RFLINE not over LM) is allowed to touch MxFILL
DS523 3 MxFILL minimum space (MTFUSE, LMFUSE); Mx = MQ, MG, LM 9.00 9.00
DS525 MxFILL minimum space ; Mx = MQ, MG, LM 0.40 0.40
DS525a 4 (MxFILL not touching (IND or IND_FILT or BONDPAD or 0.40 0.40

RF_MODFILL)) minimum space ; Mx = MQ, MG
DS525b 4 (LMFILL not touching (IND or RF_MODFILL)) minimum space 0.40 0.40
DS525c 4 (MxFILL touching (IND or IND_FILT or BONDPAD)) minimum 0.40 1.20

space ; Mx = MQ, MG
DS525d 4 (LMFILL touching IND) minimum space 0.40 1.20

RF_MODFILL)) minimum width; Mx = MQ, MG
DS526a (LMFILL not touching (IND or RF_MODFILL)) minimum width 0.70 1.20
RF_MODFILL)) maximum width; Mx = MQ, MG
DS527a (LMFILL not touching (IND or RF_MODFILL)) maximum width 3.20 1.20
DS528 (MxFILL touching (IND or IND_FILT or BONDPAD)) minimum width; 0.70 0.80
Mx = MQ, MG
DS528a (LMFILL touching IND) minimum width 0.70 0.80
DS529 (MxFILL touching (IND or IND_FILT or BONDPAD)) maximum 3.20 0.80
width; Mx = MQ, MG


Min Practice.
(Rule
Number)
DS529a (LMFILL touching IND) maximum width 3.20 0.80
DS529b1 (MxFILL touching (RF_MODFILL not over(IND or IND_FILT or 0.40 1.30
BONDPAD))) minimum space; Mx = MQ, MG
BONDPAD))) minimum width; Mx = M1- M6
BONDPAD))) maximum width; Mx = M1- M6
DS529c1 (LMFILL touching (RF_MODFILL not over IND)) minimum space; 0.40 1.30
DS529c2 (LMFILL touching (RF_MODFILL not over IND)) minimum width; 0.70 1.10
DS529c3 (LMFILL touching (RF_MODFILL not over IND)) maximum width; 3.20 1.10
DS530 LYFILL must not touch (LY, LYFILL, KERFEXCL,LOGOBND, PRO- - -
TECT, LYEXCLUD, IND_FILT, BONDPAD, MA_RFLINE,
RF_MODFILL)
DS531 LYFILL minimum space to LY 0.60 4.00
DS532 LYFILL minimum space to (KERFEXCL, LOGOBND, PROTECT, 0.60 4.00
LYEXCLUD, IND_FILT, MA_RFLINE, RF_MODFILL)
DS532b LYFILL minimum space to (DV covered by MA) with touching pro- 6.50 10.50
hibited.
DS532c LYFILL minimum space to BONDPAD 4.90 4.90
DS5337 LMFILL minimum space to FUSE with touching prohibited > 0.00 > 0.00
DS535 LYFILL minimum space 0.60 2.00

DS536 LYFILL minimum width 0.60 6.00
DS537 LYFILL maximum width 10.00 6.00
DS538 LYFILL minimum area (m2) 1.10 36.00
DS539 LYFILL maximum area (m2) 100.00 36.00
DS540 E1FILL must not touch (E1, E1FILL, L1, KERFEXCL, LOGOBND, - -
PROTECT, E1EXCLUD, IND_FILT, BONDPAD, MA_RFLINE,
RF_MODFILL)
DS541 E1FILL minimum space to E1 2.00 4.00
DS542 E1FILL minimum space to (LOGOBND, PROTECT, KERFEXCL, 2.00 4.00
E1EXCLUD, IND_FILT, MA_RFLINE, RF_MODFILL)


Min Practice.
(Rule
Number)
DS542b E1FILL minimum space to (DV covered by MA) with touching pro- 6.50 10.50
hibited
DS542c E1FILL minimum space to BONDPAD 4.90 4.90
DS542d E1FILL minimum space to L1 2.00 6.00
DS545 E1FILL minimum space 2.00 2.00
DS546 E1FILL minimum width 1.50 6.00
DS547 E1FILL maximum width 10.00 6.00
DS548 E1FILL minimum area (m2) 6.00 36.00
DS549 E1FILL maximum area (m2) 100.00 36.00
DS550 OLFILL must not touch (OL, OLFILL, KERFEXCL, LOGOBND, - -

PROTECT, OLEXCLUD, IND_FILT, BONDPAD, RF_MODFILL)
DS551 OLFILL minimum space to OL 2.00 4.00
DS552 OLFILL minimum space to (LOGOBND, PROTECT, KERFEXCL, 2.00 4.00
OLEXCLUD, IND_FILT, RF_MODFILL)
DS552b OLFILL minimum space to (DV covered by LD) with touching pro- 6.50 10.50
hibited
DS552c OLFILL minimum space to BONDPAD 4.90 4.90
DS555 OLFILL minimum space 2.00 2.00
DS556 OLFILL minimum width 1.50 6.00
DS557 OLFILL maximum width 10.00 6.00
DS558 OLFILL minimum area (m2) 4.32 36.00
DS559 OLFILL maximum area (m2) 100.00 36.00
DS560 MAFILL must not touch (MA, MAFILL, KERFEXCL, LOGOBND, - -

PROTECT, MAEXCLUD, IND_FILT, BONDPAD, MA_RFLINE,
RF_MODFILL)
DS561 MAFILL minimum space to MA 5.00 8.00
DS562 MAFILL minimum space to (LOGOBND, PROTECT, KERFEXCL, 5.00 8.00
MAEXCLUD, IND_FILT, BONDPAD, MA_RFLINE, RF_MODFILL)
DS562b MAFILL minimum space to (DV covered by MA) with touching pro- 14.50 14.50
hibited
DS565 MAFILL minimum space 5.00 5.00


Min Practice.
(Rule
Number)
DS566 MAFILL minimum width 4.00 11.00
DS567 MAFILL maximum width 12.00 11.00
DS568 MAFILL minimum area (m2) 16.00 121.00
(Note: Rule is not verified in DRC since this Rule is satisfied by
related Rule DS566)
DS569 MAFILL maximum area (m2) 144.00 121.00
(Note: Design Min supersedes MA guideline listed in related Rule
F27c in Table 20 for the actual MAFILL IBM reserved level)
DS570 LDFILL must not touch (LD, LDFILL, KERFEXCL, LOGOBND, - -
PROTECT, LDEXCLUD, IND_FILT, BONDPAD, RF_MODFILL)
DS571 LDFILL minimum space to LD 5.00 8.00
DS572 LDFILL minimum space to (LOGOBND, PROTECT, KERFEXCL, 5.00 8.00
LDEXCLUD, IND_FILT, BONDPAD, RF_MODFILL)
DS572b LDFILL minimum space to (DV covered by LD) with touching pro- 14.50 14.50
hibited
DS575 LDFILL minimum space 2.80 4.50
DS576 LDFILL minimum width 2.00 4.50
DS577 LDFILL maximum width 12.00 4.50
DS578 LDFILL minimum area (m2) 10.00 20.25
DS579 LDFILL maximum area (m2) 144.00 20.25

(Note: Design Min supersedes LD guideline listed in related Rule
F27c in Table 20 for the actual LDFILL IBM reserved level)
DS581 MQFILL minimum space to QT with touching prohibited (for designs 1.00 1.00
without MG)
DS582 MGFILL minimum space to QT with touching prohibited (for designs 1.00 1.00
with MG)
DS584 OLFILL minimum space to HT with straddling prohibited 0.00 1.20
DS584a OLFILL minimum space to KT with straddling prohibited 0.00 1.20
DS586 OLFILL within HT 1.00 1.20
DS586a OLFILL within KT 1.00 1.20
DS590 AMFILL must not touch (AM, AMFILL, KERFEXCL, LOGOBND, - -
PROTECT, AMEXCLUD, IND_FILT, BONDPAD, RF_MODFILL)


Min Practice.
(Rule
Number)
DS591 AMFILL minimum space to AM 5.00 8.00
DS592 AMFILL minimum space to (LOGOBND, PROTECT, KERFEXCL, 5.00 8.00
AMEXCLUD, IND_FILT, BONDPAD, RF_MODFILL)
DS592b AMFILL minimum space to (DV covered by AM) with touching pro- 14.50 14.50
hibited
DS593 AMFILL minimum space 5.00 5.00
DS594 AMFILL minimum width 4.00 11.00
DS595 AMFILL maximum width 12.00 11.00
DS596 AMFILL minimum area (m2) 16.00 121.00
(Note: Rule is not verified in DRC since this Rule is satisfied by
related Rule DS5x6)
DS597 AMFILL maximum area (m2) 144.00 121.00
(Note: Design Min supersedes AM guideline listed in related Rule
F27c in Table 20 for the actual AMFILL IBM reserved level)
DS598 xxFILL must be square; where xx = M1- M6, MQ, MG, LM, LY, E1, = - = -
MA, OL, LD, AM
DS599 xxFILL must be within CHIPEDGE, where xx = M1- M6, MQ, MG, 0.00 0.00
LM, LY, E1, MA, OL, LD, AM
1. LOGOBND within CHIPEDGE receives RXFILL. LOGOBND used in the IBM KERF shall not receive RXFILL (with straddling
prohibited).
2. Rule may be coded as (xxEXCLUD not over FUSE) for common code use; where xx = RX or PC or Mx. The Dummy Design and Utility
Level FUSE is prohibited in this technology per Rule RL07a.
3. Rules are listed in Table 244 that have a shaded GRAY background are not applicable to this technology, but may be included in the
actual Design Services code for common code re-use. These rules are not required to be included in the IBM Design Services Design
Rule Checking (DRC) deck. For additional information of the RL0x series of rules checked in the Design Kit DRC deck, see Table 18.
Reserved Level Layout Rules on page 83.
4. Rule is not required to be verified in IBM Design Services Design Rule Checking (DRC) deck. Rule is included to document that as
xxFILL is width is reduced, when xxFILL is touching specific Dummy Design and Utility Levels to intentionally lower the pattern density
in the chip design. the xxFILL space is increased the same incremental amount.
5. Rule DS522a supersedes Rules DS525a, DS5258, DS529 only when LM touches the BONDPAD shape. The intent of this rule is that
modelled wirebond or C4 structures for the LM BEOL only do not receive MQFILL, MGFILL or LMFILL.
6. LMFILL is not altered by the presence of the MA_RFLINE Dummy Design Level.
7. Rule may be included for common code use. FUSE is prohibited in this technology per Rule RL07a.

Table 245. xxHOLE Rules

Min Practice.
(Rule
Number)
DSNOTE1 The term incurring is used in this table, and the syntax for incurring - -
is defined as:
A incurring B means A such that A has any area in common with B
DS600 MxHOLE must not touch (MxHOLE, MxCHEXCL); - -
Mx = M1-M6, MQ, MG, LM
DS600a2 MxHOLE must not touch FUSE - -
DS608 M1HOLE must not touch ((CABAR, V1BAR) not touching IND) - -


Min Practice.
(Rule
Number)
DS609 MxHOLE must not touch ((VxBAR, VwBAR) not touching IND) ; - -
Mx = M2-M6, MQ, MG, LM ;
Vx3 = via level above Mx; Rule does not apply to TV4; Vw = via level
below Mx
----------------------------------------------------------
The abbreviated rule description above is verified as follows:
M2HOLE must not touch ((VLBAR, V1BAR) not touching IND)
when M3 is not present
M2HOLE must not touch ((V2BAR, V1BAR) not touching IND)
when M3 is present
when M4 is present
when M5 is present
when M6 is present
when M6 is present
MQHOLE must not touch (FYBAR, (VLBAR not touching IND)),
when MG is not present
MQHOLE must not touch (JTBAR, (VLBAR not touching IND))
when MG is not present
MQHOLE must not touch ((VQBAR, VLBAR) not touching IND)
when MG is present
LMHOLE must not touch (VQBAR not touching IND) when MG is
not present
MQHOLE must not touch (FQBAR, (VLBAR not touching IND))
-----------------------
When MG is present:
MGHOLE must not touch ((VGBAR, VQBAR) not touching IND)
MGHOLE must not touch (FYBAR, (VQBAR not touching IND))
MGHOLE must not touch (JTBAR, (VQBAR not touching IND))
LMHOLE must not touch (VGBAR not touching IND)
DS609c MQHOLE must not touch JTBAR when MG is not present - -
DS609d MGHOLE must not touch JTBAR when MG is present - -
DS609h5 MQHOLE must not touch MQDUMHOL - -

MGHOLE must not touch MGDUMHOL


Min Practice.
(Rule
Number)
DS609h1 MxHOLE minimum space to MxDUMHOL; Mx = MQ,MG 0.80 0.80
DS611 MxHOLE must be within Mx ; Mx = M1-M6 0.30 0.40
DS612 MxHOLE minimum space to MxCHEXCL ; Mx = M1-M6 > 0.00 > 0.00
DS615 MxHOLE minimum space ; Mx = M1-M6 0.60 0.60
DS616 MxHOLE minimum width ; Mx = M1-M6 0.60 0.60
DS617 MxHOLE maximum width ; Mx = M1-M6 0.60 0.60
DS618 (CA touching M1HOLE) must touch (((((CA not touching M1HOLE) - -
sized by 1.80m) over RX) over M1) not PC)
DS619 [Vx incurring (MxHOLE, MyHOLE)] must touch [{[Vx not incurring - -
(MxHOLE, MyHOLE)] sized by +1.80m} over intersect (Mx,My)];
Vx = V1-V5; Mx = metal below Vx ; and My = metal above Vx.
DS6206 [Vx touching (MyHOLE sized by -0.10m)] must touch [ {([Vx not - -
touching (MyHOLE sized by -0.10m)] not incurring MxHOLE)
sized by +1.80m} over intersection (Mx, My)];
Vx = V1-V5; Mx = metal below Vx ; My = metal above Vx.
DS621 MxHOLE must be within Mx ; Mx = MQ, MG, LM 0.40 0.80
DS622 MxHOLE minimum space to MxCHEXCL ; Mx = MQ, MG, LM > 0.00 > 0.00
DS625 MxHOLE minimum space ; Mx = MQ, MG, LM 0.60 0.80
DS626 MxHOLE minimum width ; Mx = MQ, MG, LM 0.80 0.80
DS627 MxHOLE maximum width; Mx = MQ, MG, LM 0.80 0.80
DS628 [Vx incurring (MxHOLE or MyHOLE)] must touch [{[Vx not incurring - -
(MxHOLE or MyHOLE)] sized by +3.60m} over intersection (Mx,
My)]; Vx = VQ, VG ; Mx = metal below Vx ; My = metal above Vx.
DS630 [VL incurring MxHOLE] must touch [{[VL not incurring MxHOLE] - -
Mx = metal below VL ; My = metal above VL.
DS631 [VL incurring MyHOLE] must touch [{[VL not incurring MyHOLE] - -
Mx = metal below VL ; My = metal above VL.
DS6327 [Vx touching (MyHOLE sized by -0.20m)] must touch [{([Vx not - -
touching (MyHOLE sized by -0.20m)] not incurring MxHOLE)
sized by 3.60m} over intersection (Mx,My)];
Vx = VL, VQ, VG ; Mx = metal below Vx ; My = metal above Vx.


Min Practice.
(Rule
Number)
DS633 Any ((M1 over RX) not PC) that has a CA incurring M1HOLE must - -
have at least 3 CAs that do not incur M1HOLE
DS634 Any (Mx over My) that has a (Vx incurring on either (MxHOLE or - -
MyHOLE)) must have at least 3 (Vx not incurring on either
(MxHOLE or MyHOLE)).
Vx = V1-V5, VL, VQ, VG; Mx = metal below Vx; My = metal above
Vx
DS634a Any (MQ over LY) that has an (FY incurring on MQHOLE) must - -
have at least 4 (FY not incurring on MQHOLE); when MG is not
present within CHIPEDGE
DS634b Any (MG over LY) that has an (FY incurring on MGHOLE) must - -
have at least 4 (FY not incurring on MGHOLE); when MG is present
within CHIPEDGE
DS634c Any (MQ over OL) that has a (JT incurring on MQHOLE) must have - -
at least 3 (JT not incurring MQHOLE); when MG is not present
within CHIPEDGE
DS634d Any (MG over OL) that has a (JT incurring on MGHOLE) must have - -
at least 3 (JT not incurring on MGHOLE); when MG is present
within CHIPEDGE
DS634e Any (MQ over AM) that has an (FQ incurring on MQHOLE) must - -
have at least 4 (FQ not incurring on MQHOLE)
DS671 LMHOLE not touching ((least enclosing rectangle (FV octagon)) 0.80 0.80
sized by 8.52m) minimum width
DS672 LMHOLE not touching ((least enclosing rectangle (FV octagon)) 0.80 0.80
sized by 8.52m) maximum width
DS673 LMHOLE touching ((least enclosing rectangle (FV octagon)) sized 1.60 1.60
by 8.52m) minimum width
by 8.52m) maximum width
by 8.52m) minimum space to Vx with touching prohibited; Vx = via
below LM
DS676 Number of square LMHOLE touching ((least enclosing rectangle 0 0
(FV octagon)) sized by 6.2m)
DS678 LMHOLE to (TV not touching FV) with touching prohibited 0.80 0.80


Min Practice.
(Rule
Number)
DS697 LMHOLE not touching ((least enclosing rectangle (FV octagon)) - -
sized by 8.52m) must be square
DS698 MxHOLE must be square ; Mx = M1-M6, MQ, MG, LM - -
DS810 VxHOLE must be within Vx ; 0 0
Vx = V1-V5, VL, VQ, VG
DS820 VxHOLE must be within MyHOLE ; 0.00 > 0.00
Vx = V2-V5; My = metal level above Vx
DS821 V1HOLE must be within M2HOLE 0.00 > 0.00
DS830 VxHOLE must be within MyHOLE ; -0.19 -0.19
Vx = VL, VQ, VG ; My = metal level above Vx
DS860 OLHOLE must not touch OL - -
DS861 (JTHOLE, OLHOLE, OLCHEXCL) must not touch CHIPEDGE - -
1. This is not a Rule. It is included in this table as a unique definition to aid in verification of the DSxxx Rule in Design Rule Checking
(DRC).
2. Rule is shaded GRAY background and is not applicable to this technology, but may be included in the actual Design Services code for
common code re-use. These rules are not required to be included in the IBM Design Services Design Rule Checking (DRC) deck.
For additional information of the RL0x series of rules checked in the Design Kit DRC deck, see Table 18. Reserved Level Layout
Rules on page 83.
3. See Rule DS609a when the via level above Mx is the FY mask level (FYBAR). See Rule DS609b when the via level above Mx is the JT
mask level (JTBAR)
4. See Rule DS678 for the Via above LM. TVBAR is not a supported design level. For wirebond, TV is drawn in the form of a bar per as
defined in Rule 650a as well as Rule 946a.
5. Rule intentionally omits LMDUMHOL and MxDUMHOL(x=1-6,T) since LMDUMHOL is used for a different purpose in this technology,
and MTDUMHOL is a reserved level and would be used for a different purpose if enabled, and MxHOLES (x = 1-6) must always
receive MxHOLE shapes.
6. For Vx, DS620 is a more relaxed check for DS619 in the event of a DS619 error.
7. For VQ and VG, DS632 is a more relaxed check for DS628 in the event of a DS628 error.
Table 246. Pattern Density Rules (Post Cheese and Fill)

Min Practice.
PD1a1 (RX, RXFILL) minimum local density (%) 20 20
PD1b (RX, RXFILL) minimum global density (%) 25 25

PD2 (PC, PCFILL) minimum density (%) within CHIPEDGE 15 15
PD2a2 (PC, PCFILL) minimum density (%) 5 5

Table 246. Pattern Density Rules (Post Cheese and Fill)

Min Practice.
PD4a3 (Mx, MxFILL) minimum density (%); 10 10

Mx = M1, M2, M3, M4, M5, M6, MQ, MG, LM
Exemption: Tile touching IND, IND_FILT, BONDPAD, PROTECT,
LOGOBND, QT (for Mx = MG), QT (for Mx = MQ, if there is no MG
in the design data)
PD4a14 (Mx, MxFILL) minimum density (%) for all boxes touching IND, 8 8
IND_FILT, BONDPAD
Mx = M1, M2, M3, M4, M5, M6, MQ, MG, LM
Exemption: Tile touching QT (for Mx = MG), QT (for Mx = MQ, if
there is no MG in the design data)
PD4b5 (Mx not over MxHOLE) maximum density (%); 85 85

Mx = M1, M2, M3, M4, M5, M6, MQ, MG, LM
Exemptions:
Tile touching wirebond (TD intersect DV) or C4 pad (LM intersect
FV); for LM only, where LM is the last metal level prior to the final
passivation levels.
PD5a (LY, LYFILL) minimum Global density (%) 27 27
PD5c6,7 (E1,E1FILL) minimum local density (%) 10 10
PD5d2 (E1, E1FILL) minimum Global density (%) 23 23
PD5g 6,8 (OL,OLFILL) minimum local density (%) 10 10
PD5h2 (OL,OLFILL) minimum Global density (%) 23 23

PD5i (LD, LDFILL) minimum Global density (%) 27 27
PD5k (MA, MAFILL) minimum Global density (%) 27 27
PD5m (AM, AMFILL) minimum Global density (%) 27 27
1. For this local density requirement, the checking box is 126m x 126m stepped in 63m increments. Rule PD1a is not in force
for any checking box that touches PROTECT which is outside of CHIPEDGE. Rule PD1a is presently not in force for any
checking box that touches LOGOBND. In the future, the exemption for checking boxes that touch LOGOBND may be
eliminated, since IBM includes RXFILL within LOGOBND regions. If a designer places an RXEXCLUD within LOGOBND, it is
expected that the checking box touching the (RXEXCLUD over LOGOBND) still comply with the minimum density value
specified. The only exception for RX local density is within the IBM KERF LOGOBND area, since RXFILL is not automatically
included in this region. The interpretation of (RX, RXFILL) in this description is the equivalent of Union (RX, RXFILL), which is
the sum of the Design Level RX and the Reserved Level RXFILL, for checking purposes of this rule. The Current Practice value
specified is the value that is to be coded into the IBM Release Team Design Rule checking decks used by IBM, and represents
the minimum density acceptable after Design Services is applied to a chip during the IBM release process.
2. For this local density requirement, the checking box is 400m x 400m stepped in 200m increments. Rule PD2a is not in force for
any checking box that touches PROTECT or LOGOBND. The interpretation of (PC, PCFILL) in this description is the equivalent of
Union (PC, PCFILL), which is the sum of the Design Level PC and the Reserved Level PCFILL, for checking purposes of this rule.
The Current Practice value specified is the value that is to be coded into the IBM Release Team Design Rule checking decks used
by IBM, and represents the minimum density acceptable after Design Services is applied to a chip during the IBM release process.

3. For this local density requirement, the checking box is 126m x 126m stepped in 63m increments. Rule PD4a is not in force for any
checking box that touches IND, IND_FILT, BONDPAD, PROTECT or LOGOBND. Rule PD4a is not applicable for tiles touching QT
where Mx = MG, or for tiles touching QT where Mx = MQ if there is no MG in the design data. For IND, IND_FILT, BONDPAD, see
separate Rule PD4a1. The interpretation of (Mx, MxFILL) in this description is the equivalent of Union (Mx, MxFILL), which is the
sum of the Design Level Mx and the Reserved Level MxFILL, for checking purposes of this rule. The Current Practice value specified
is the value that is to be coded into the IBM Release Team Design Rule checking decks used by IBM, and represents the minimum
density acceptable after Design Services is applied to a chip during the IBM release process.
4. For this local density requirement, the checking box is 126m x 126m stepped in 63m increments. Rule PD4a1. Rule PD4a1 is not
applicable for tiles touching QT where Mx = MG, or for tiles touching QT where Mx = MQ if there is no MG in the design data.
5. For this local density requirement, the checking box is 50m x 50m stepped in 25m increments. The Current Practice value specified
is the value that is to be coded into the IBM Release Team Design Rule checking decks used by IBM, and represents the maximum
density acceptable after Design Services is applied to a chip during the IBM release process. However, predictive density tools in
the Technology Design Kit may actually be on the order of 5% lower than the Current Practice specified, to account for tool-to-tool
consistency considerations.
6. For this local density requirement the checking box is 400m x 400m areas stepped in 400m increments across the chip. Checking
boxes either touching or placed under a wirebond pad are exempt from this density rule
7. For this local density requirement the checking box should only flag an error when checking boxes with < 10% E1 pattern adjoin or hit
any other box (in 8 directions) with < 10% E1 density.
8. For this local density requirement the checking box should only flag an error when checking boxes with < 10% OL pattern adjoin or hit
any other box (in 8 directions) with < 10% OL density.

Q.1.1 Estimated Pattern Density Generation

Estimated pattern density algorithms are listed below to assist with verification during design layout. These
algorithms estimate the final design pattern density after IBM Design Services FILL shapes have been added
to a layout. These density estimations provide an early warning to customers for regions of low density. The
algorithms are provided in detail below in order to give designers additional understanding of how various
layout shapes affect the placement of IBM generated FILL.
Table 247. Estimated Pattern Density Rules
Rule Notes Description

Rule EPDL_RX: (rx_estimated) minimum local density, with 126m tiling stepped in
63m increments within CHIPEDGE >= 20%
DS101=0.60, DS102=0.60, DS104=3.00, DS105=0.30, DS106=0.90, DS110=0.40,

DS111=0.40, DS120=0.80, DS121=3.00, DS130=1.50, DS131=0.56, DS135=1.00.
A = rx_ds102 = (union{ PC, PCING, PROTECT, RXEXCLUD, KERFEXCL,

LOGOBND}) sized by +DS102
B = rx_ds101 = (RX sized by +DS101)
C = rx_ds104 = (PCFUSE sized by +DS104)
D = rx_nw_excl = difference [((NW sized by +DS111), (NW sized by -DS110)]
E = rx_jd_excl = difference [(JD sized by +DS121), (JD sized by -DS120)]
F = rx_bb_excl = difference [(BB sized by +DS131), (BB sized by -DS130)]
1,2 G = rx_rn_excl = (RN sized by +DS135)
EPDL_RX H = rx_inshape_excl = difference [(rx_inshape sized by +0.6 um), (rx_inshape sized by
-0.6 um)]
rx_inshape = union { BONDPAD, BFMOAT, IND_FILT, IND }

rx_limit = ( DS106 + rx_pitch)
rx_pitch = ( DS106 + DS105) / 2
rx_slivr = rx_pitch / 6
rx_no_fill = [(union { A,B,C,D,E,F,G,H}) sized by +(rx_limit/2) ] sized by -(rx_pitch/2 -
rx_slivr)
rx_std_fill = difference [ CHIPEDGE sized by -DS102 , union {rx_no_fill, rx_inshape}]
rx_fill_ind = difference [ rx_inshape, rx_no_fill ]
rx_estimated = [area (RX) + (0.45 * area(rx_std_fill)) + (0.20 * area(rx_fill_ind))] /

(126 * 126)


Rule EPDG_PC = (pc_estimated) global density within CHIPEDGE >= 15%
DS201=0.60, DS202=0.60, DS204=3.00, DS205=0.52, DS205a=0.52, DS205b=0.60,

DS206=0.68, DS210=0.52, DS211=0.52, DS220=0.80, DS221=3.00, DS230=1.50,
DS231=1.50, DS235=1.00.
A = pc_ds202 = (union{ RX, LOGOBND, PROTECT, KERFEXCL, PCEXCLUD }) sized

by +DS202
B = pc_ds201 = (union{ PC, PCING} sized by +DS201)
C = pc_ds204 = (PCFUSE sized by +DS204)
D = pc_jd_excl = difference [(JD sized by +DS221), (JD sized by -DS220)]
E = pc_bb_excl = difference [(BB sized by +DS231), (BB sized by -DS230)]
F = pc_rn_excl = (RN sized by +DS235)
G = pc_bfm_excl = difference [(BFMOAT sized by DS205a), (BFMOAT sized by
EPDG_PC -DS205b)]
pc_lowdens = union(IND, IND_FILT, [(LM intersect LM_RFLINE) sized by 3.1um], [(MA

intersect MA_RFLINE) sized by 3.1 um], BONDPAD)
pc_limit = ( DS206 + pc_pitch)
pc_pitch = ( DS206 + DS205a) / 2
pc_slivr = pc_pitch / 6
pc_no_fill = ( union {A,B,C,D,E,F,G} sized by +(pc_limit/2) ) sized by -(pc_pitch/2 -
pc_slivr)
pc_std_fill = difference [ CHIPEDGE sized by -DS202 , union {pc_no_fill, pc_lowdens,
BFMOAT}]
pc_bfm_fill = difference [ BFMOAT, pc_no_fill ]
pc_low_fill = difference [ pc_lowdens, pc_no_fill ]
pc_estimated = [ area(PC) + area(PCING) + (0.257 * area(pc_std_fill)) + (0.15 *

area(pc_low_fill)) + (0.2 * area(pc_bfm_fill)) ] / area(CHIPEDGE)
Rule EPDL_PC = (pc_estimated) local density with 400m tiling stepped in 200m
increments within CHIPEDGE >= 5%
pc_estimated = [ area(PC) + area(PCING) + (0.257 * area(pc_std_fill)) + (0.15 *

3 area(pc_low_fill)) + (0.2 * area(pc_bfm_fill)) ] / (126 * 126)
EPDL_PC
where pc_std_fill, pc_low_fill, and pc_bfm_fill are defined in EPDG_PC.
EPDL_PC is not in force for any checking box that touches PROTECT or LOGOBND;
in the future the LOGOBND exclusion may be eliminated.


Rule EPDL_M1 = (m1_estimated) local density with 126m tiling stepped in 63m
DS502=3.00, DS511=0.40, DS512=0.40, DS515=0.30, DS515b=2.90, DS515d=1.25,

DS516=0.90.
A = m1_ds502 = PCFUSE sized by +DS502

B = m1_ds511 = M1 sized by +DS511
C = m1_ds512 = (union{ LOGOBND,PROTECT, KERFEXCL, M1EXCLUD }) sized by
+DS512
m1_lowdens = union { BONDPAD, IND_FILT, IND, [ (LM_RFLINE intersect LM) sized by

4
EPDL_M1 +DS515b ] }
m1_modfill = RF_MODFILL
m1_limit = ( DS516 + m1_pitch)
m1_pitch = ( DS516 + DS515) / 2
m1_slivr = m1_pitch / 6
m1_no_fill = (union{A,B,C} sized by +(m1_limit/2)) sized by -(m1_pitch/2 - m1_slivr)
m1_std_fill = difference [ CHIPEDGE sized by -DS512, union{m1_no_fill, m1_lowdens,
m1_modfill} ]
m1_low_fill = difference [ m1_lowdens, m1_no_fill ]
m1_m_fill = difference [ m1_modfill, m1_no_fill ]
m1_estimated = area(M1) + 0.45 * area(m1_std_fill) + 0.089 * area(m1_low_fill) +

0.158 * area(m1_m_fill) ] / (126 * 126)
Rule EPDLi_M1 = (m1_estimated) local density with 126m tiling stepped in 63m
5
EPDLi_M1 increments within CHIPEDGE >= 8% for all boxes that touch IND, IND_FILT, or BOND-
PAD.


DS502=3.00, DS511=0.40, DS512=0.40, DS515=0.30, DS515b=2.90, DS515d=1.25,

DS516=0.90.

+DS512
D = m2_ds515d = K2 sized by +DS515d
4 m2_lowdens = union { BONDPAD, IND_FILT, IND, [ (LM_RFLINE intersect LM) sized by

EPDL_M2
+DS515b ] }
m2_pitch = ( DS516 + DS515) / 2
m2_no_fill = (union{A,B,C,D} sized by +(m2_limit/2)) sized by -(m2_pitch/2 - m2_slivr)
m2_modfill} ]

0.158 * area(m2_m_fill) ] / (126 * 126)
5
PAD.


DS502=3.00, DS511=0.40, DS512=0.40, DS515=0.30, DS515b=2.90, DS515d=1.25,

DS516=0.90.
+DS512

4
EPDL_M3 +DS515b ] }
m3_pitch = ( DS516 + DS515) / 2
m3_modfill} ]

0.158 * area(m3_m_fill) ] / (126 * 126)
5
PAD.


DS502=3.00, DS511=0.40, DS512=0.40, DS515=0.30, DS515b=2.90, DS515d=1.25,

DS516=0.90.
+DS512

4
EPDL_M4 +DS515b ] }
m4_pitch = ( DS516 + DS515) / 2
m4_modfill} ]

0.158 * area(m4_m_fill) ] / (126 * 126)
5
PAD.


DS502=3.00, DS511=0.40, DS512=0.40, DS515=0.30, DS515b=2.90, DS515d=1.25,

DS516=0.90.

+DS512
4 m5_lowdens = union { BONDPAD, IND_FILT, IND, [ (LM_RFLINE intersect LM) sized by

EPDL_M5
+DS515b ] }
m5_pitch = ( DS516 + DS515) / 2
m5_modfill} ]

0.158 * area(m5_m_fill) ] / (126 * 126)
5
PAD.


DS502=3.00, DS511=0.40, DS512=0.40, DS515=0.30, DS515b=2.90, DS515d=1.25,

DS516=0.90.
+DS512

4
EPDL_M6 +DS515b ] }
m6_pitch = ( DS516 + DS515) / 2
m6_modfill} ]

0.158 * area(m6_m_fill) ] / (126 * 126)
5
PAD.


Rule EPDL_MQ = (mq_estimated) local density with 126m tiling stepped in 63m
DS521=0.80, DS522=0.80, DS522a=4.90, DS522b=3.30, DS526=1.20, DS581=1.00
A = mq_ds521 = MQ sized by +DS521

B = mq_ds522 = union{ KERFEXCL, LOGOBND, PROTECT, MQEXCLUD } sized by
+DS522
C = mq_ds522a = (BONDPAD touching LM) sized by +DS522a
D = mq_ds522b = intersection { LM, LM_RFLINE } sized by +DS522b
if MG is in the stack, then E = nothing

if MG is not in the stack, then E = QT sized by +DS581
4,6
EPDL_MQ
mq_pitch = ( DS526 + DS522 ) / 2
mq_limit = ( DS526 + mq_pitch )
mq_slivr = mq_pitch / 6
mq_no_fill = (union { A, B, C, D, E } sized by +(mq_limit/2)) sized by -(mq_pitch/2 -
mq_slivr)
mq_modfill = RF_MODFILL sized by -(DS522)
mq_inductor = union { BONDPAD, IND_FILT, IND } sized by -(DS522)
mq_fill_std = difference [ CHIPEDGE sized by -(DS522), union { mq_no_fill,
mq_modfill, mq_inductor } ]
mq_fill_modfill = difference [ mq_modfill , mq_no_fill ]
mq_fill_ind = difference [ mq_inductor , mq_no_fill ]
mq_estimated = [ area (MQ) + (0.45 * area(mq_fill_std)) + (0.1681 *
area(mq_fill_modfill)) + (0.0889 * area(mq_fill_ind)) ] / (126 * 126)
Rule EPDLi_MQ = (mq_estimated) local density with 126m tiling stepped in 63m
5, 6
EPDLi_MQ increments within CHIPEDGE >= 8% for all boxes that touch IND, IND_FILT, or BOND-
PAD.


Rule EPDL_MG: (mg_estimated) minimum density, with 126m stepped in 63m incre-
ments tiling within CHIPEDGE >= 10%
DS521=0.80, DS522=0.80, DS522a=4.90, DS522b=3.30, DS526=1.20, DS582=1.00
A = mg_ds521 = MG sized by +DS521

B = mg_ds522 = union{ KERFEXCL, LOGOBND, PROTECT, MGEXCLUD } sized by
+DS522
C = mg_ds522a = (BONDPAD touching LM) sized by +DS522a
D = mg_ds522b = intersection { LM, LM_RFLINE } sized by +DS522b
E = mg_ds582 = QT sized by +DS582
F = mg_ht_excl = difference [ (HT sized by +(DS582) ), (HT sized by -(DS582) ]
4,7
EPDL_MG mg_pitch = ( DS526 + DS522 ) / 2
mg_limit = ( DS526 + mg_pitch )
mg_slivr = mg_pitch / 6
mg_no_fill = (union { A, B, C, D, E, F }sized by +(mg_limit/2)) sized by -(mg_pitch/2 -
mg_slivr)
mg_modfill = RF_MODFILL sized by -(DS522)
mg_inductor = union { BONDPAD, IND_FILT, IND } sized by -(DS522)
mg_fill_std = difference [ CHIPEDGE sized by -(DS522), union { mg_no_fill,
mg_modfill, mg_inductor } ]
mg_fill_modfill = difference [ mg_modfill , mg_no_fill ]
mg_fill_ind = difference [ mg_inductor , mg_no_fill ]
mg_estimated = [ area (MG) + (0.45 * area(mg_fill_std)) + (0.1681 *

area(mg_fill_modfill)) + (0.0889 * area(mg_fill_ind)) ] / (126 * 126
Rule EPDLi_MG = (mg_estimated) local density with 126m tiling stepped in 63m
5, 7
EPDLi_MG increments within CHIPEDGE >= 8% for all boxes that touch IND, IND_FILT, or BOND-
PAD.
1. EPDL_RX is not in force for any checking box that touches PROTECT which is outside of CHIPEDGE. EPDL_RX is not currently
in force for any box that touches LOGOBND; in the future the LOGOBND exclusion may be eliminated.
2. See footnote 4 for rule EPDL_RX on page 95.
3. EPDL_PC is not in force for any checking box that touches PROTECT or LOGOBND; in the future the LOGOBND exclusion may be
eliminated.
4. Rule EPDL_Mx (where x=1,2,3,4,5,6,Q or G) is not in force for any checking box that touches IND, IND_FILT, BONDPAD, PROTECT
or LOGOBND. For checking boxes that touch IND, IND_FILT, and BONDPAD see separate Rule EPDLi_Mx.
5. Rule EPDLi_Mx (where x=1,2,3,4,5,6,Q or G) is not in force for any checking box that touches PROTECT or LOGOBND.
6. Rule is not applicable for boxes touching QT when MG is not present in the design data.
7. Rule is not applicable for boxes touching QT when MG is present in the design data.

Pattern Fill Rules Recommended Design Practices Related to Generated FILL and
Q.2 Recommended Design Practices Related to Generated

FILL and HOLES Shapes
Designers are encouraged to follow the following recommendations. Disregard for these recommendations
may result in designs that cannot be adequately treated by the IBM FILL and HOLE generation tools.
Violations of rules PD1a, PD2, PD4a, PD4a1 or PD4b may occur, resulting in potential delays of the product.
Certain of the discouraged design practices enumerated below can be tolerated if their extent is small and the
distance between them is large. If the recommended Design Practices can not be observed in every case,
contact IBM Product Engineering for assistance defining acceptable limits and assessing the incumbent risks
to the design.
Avoid long or dense runs of RX wiring or PC wiring. RX and PC wiring inhibit the placement of
RXFILL and PCFILL generated shapes, potentially leading to violations of PD1 and PD2. RX wiring and
PC wiring are generally inefficient current-carrying members, by virtue of the high resistance and high Rs
tolerances, relative to M1 or other general-purpose metal wiring levels. Long or dense runs of RX wiring
or PC wiring are generally discouraged, apart from the mentioned pattern-density issues.
Avoid the use of dummy shapes on RX, PC, and all metal levels. Designer-added dummy shapes
inhibit the placement of IBM-generated FILL shapes, potentially leading to violations of PD1, PD2, and
PD4a. IBM-generated Fill shapes are structurally and hierarchically optimized to provide maximum yield
and manufacturability improvement with minimum perturbation to the circuit. Large designer-added
dummy shapes are less useful to manufacturing, and more disruptive to the circuit. Small
designer-added dummy shapes are more burdensome for Design Services, DataPrep and Mask Manu-
facturing, and can be also be problematic for wafer manufacturing.
Avoid the use of slotted or otherwise precheesed wiring for Copper levels. Slotted or precheesed
metal inhibits the effective placement of Metal Hole shapes, potentially leading to violations of PD4b.
IBM-generated Metal Hole shapes are structurally and hierarchically optimized to provide maximum yield
and manufacturability improvement with minimum penalty. Precheesed metal can greatly increase the
computational burden for Design Services and DataPrep, increasing the cycle time for these processes,
or causing the job steps to fail completely. For practical wiring structures, IBM-generated Metal Hole
shapes provide lower resistance and Rs tolerance than any allowable slotted or precheesed structure.
Whenever possible, it is recommended that collections of vias connecting the same two pieces of metal
be drawn as simple linear or 2D arrays. For linear arrays, it is recommended that the individual vias have
zero offset from one another in one dimension, and be evenly spaced in the other. For 2D arrays of
redundant vias, it is not necessary to use the same pitch in the X and Y directions, but it is strongly rec-
ommended that the vias be drawn so as to neatly line up in each direction. Double or single rings of vias
are an acceptable alternative to regular 2D arrays of redundant vias.
Whenever possible, it is recommended that collections of vias on adjacent levels be drawn so as to line
up vertically. It is not recommended to have collections of vias on adjacent levels be offset from one
another, except where such an arrangement is unavoidable. Vertical alignment is not necessary for VL
and the via level immediately beneath it.

Index IBM
Dummy Design Levels 45
Index DV Layout Rules 149
Dynamic circuits 84
E
Numerics E1 Metal Layout Rules 168
3.3V HiVt NFET (JN) Rules 235 Electrical Programmable Fuse 243
3.3V HiVt PFET (JP) Rules 236 ESD 523
ESD Rules 190
A External Latchup Rules 184
ACLV 341
AM BONDPAD Layout Rules 312 F
AM Inductor 268 F1 Via Layout Rules 171
AM Metal Layout Rules 173 Feature Group 11
Antenna Rules 113 Feature Part Numbers 11
Film Thickness 417
B FQ & FQBAR Via Layout Rules 174
Back-End-Of-Line Resistor Layout Rules 222 FT Via Layout Rules 168
BFMOAT Design Rules 230 FV Layout Rules 149
Bondpads 309 FY Via Layout Rules 166
BP Layout Rules 128
Breakdown Voltage 376 G
Butted Junction Layout Rules 131 Gate oxide 346
Generated Levels 58
C Geometry Restrictions 82
C4 276 Global Pattern Density 87
C4 Terminals with AM BEOL 291 Grid 27
CA Layout Rules 115 Guard Ring 318
Chamfer 318
Channel length tolerance 341 H
Channel Length Variation 367, 370 HiVt 3.3V NFET 11
Check List 17 HiVt 3.3V PFET 11
Chip Guard Ring 318 HiVt NFET 8
Chip mean variation 341 HiVt PFET 8
Chip Size, Maximum 333 HT 257, 260
CHIPEDGE 47 HT Layout Rules 257, 260
Contact Layout Rules 115 I
Contact Resistance 416 Important Design Guidelines 84
Copyright Notice 331 Inductor Layout Rules 267
Crackstop 328 IO Pads 276
Cross Sections 23
J
D JD Layout Rules 250
Data Preparation Levels 37 JN 8, 11, 29, 235
Definitions of Ground Rule Terms 543 JP 8, 11, 29, 236
Design Level 27 JT Via Layout Rules 156
Design Preparation 59 Junction Layout Rules 115
Design Services Levels 37 Junction Varactor Layout Rules 250
Device Width and Length 355, 360, 363, 367, 370
DG Layout Rules 230 K
Dual Gate 3.3V I/O Device Rules 234 KERF Dummy Design Levels 43
Dual MIM 251 KT 257, 260
Dual Nitride MIM 256 KT Layout Rules 257, 260

Index
Kx Resistor Layout Rules 223 Physical Layout Information 27

Polysilicon and Isolation Layout Rules 95
L
Process-Related Terms 546
L1 Resistor Layout Rules 222
Product Labels 328
Labels 328
Protect Layer 325
Latchup 504
Latchup Rules 176 Q
Layout Rules 95 QT 257
LD Metal Layout Rules 164 QT Layout Rules 257, 260
LM Metal Layout Rules 147
R
Local Pattern Density 89
Recommended Rules 85
LOGOBND Rules 330
Recommended rules 86
Low Leakage 3.3V I/O FET 235
Reliability 458
Low Power FET Layout Rules 122
Reliability Screening 459
LV Layout Rules 150
Reserved Level Rules 83
LY Metal Layout Rules 166
RF Interconnect Line 274
M RP Rules 215
M1 Metal Layout Rules 133 RR Rules 213
MA Metal Layout Rules 173
S
Mask Level 27
Sheet Resistance 417
Mask Levels 58
Silicide Polysilicon Resistor 219
Mask Process Control Images 174
SILPCRES 55, 219
Maskwork Notice 331
Single DUT (Device Under Test) 314
Metallization Options 63
Single Hi-K MIM 255
MG Metal Inductor Layout Rules 153
Single MIM 251
MG Metal Layout Rules 151
Single MIM Capacitor 255
MIM Capacitor 257, 260
Single Nitride MIM 256
MIM Capacitor Layout Rules 254
Size, Allowable Chip 333
MIM Layout Rules 251
Slots in Wide Metal 317
Mixed Voltage Interfaces 450
Modelled Bondpads 309 T
MQ Metal Inductor Layout Rules 153 T3 Isolation Well 104
MQ Metal Layout Rules 151 temperature range 9
Multiple DUT (Device Under Test) 315 Terminals 276
Mx Metal Layout Rules 141 Threshold Voltage Layout Rules 127
Transmission Line 274
N
Triple Well Layout Rules 239
NFET-in-Nwell Layout Rules 237 Truth Table 68, 75
Non-Design Levels 58
TV Layout Rules 149
N-well Layout Rules 115
N-well Resistor Rules 217 U
Utility Levels 45
O
OL Metal Layout Rules 156 V
Origin 86 Vertical Natural Capacitor 261
VG Via Layout Rules 151
P
Via Resistance 416
Packaging Restrictions 313
VNCAP 261
Pad Identification 181, 196
voltage range 9
Part Testing 313
VQ Via Layout Rules 151
Pattern Density Rules 87
VV Via Layout Rules 164
PCI 174
Vx Via Layout Rules 133
PD Rules 213

Index IBM
W
Wirebond 276
Wirebond Rules
Fine Pitch In-Line (LM) 300
In-Line (LD) 305
In-line and Staggered (LM) 296
Wirebond with AM BEOL 307
Wiring capacitance 421
Z
Zero Vt NFET Layout Rules 121

Index

IBM
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CMOS8RF (CMRF8SF)

Owner: Department 9G8A

Version Date: November 30, 2010

Engineering Specification Changes

Manufacturing TPRS Name: CMRF8SF

IBM Confidential -- Do Not Copy

V 1.8.0.0 (Version Date: November 30, 2010)

Analog and Mixed Signal Technology Development

IBM Corporation, 2010. All rights reserved. ES#57P9006 EC# L86842

2.0 Physical Layout Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.0 Layout Rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

ES#57P9006 EC# L86842 IBM Corporation, 2010. All rights reserved.

4.0 Electrical Parameters and Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335

IBM Corporation, 2010. All rights reserved. ES#57P9006 EC# L86842

4.31 Wiring Capacitance Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421

5.0 Reliability Design Rules and Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458

6.0 Latchup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504

7.0 Electrostatic Discharge (ESD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523

8.0 Design for Manufactureability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528

I.0 Standard and Dense SRAM Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538

J.0 Guidelines for Optimal Model-Hardware Correlation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539

K.0 Total Standby Current (Idd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540

L.0 Design Hierarchy Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542

M.0 Rule Syntax (Definitions) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543

N.0 Definitions of Process-Related Terms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546

O.0 Migration into Future Technologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547

P.0 Design Preparation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548

Q.0 Pattern Fill Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549

ES#57P9006 EC# L86842 IBM Corporation, 2010. All rights reserved.

1.0 Technology Introduction

General CMOS Process

Low resistance Co salicided N+ and P+ polysilicon and diffusion areas.

- Two or three thick copper levels

MQ (with LY, E1, MA)

MQ and MG (with LY, E1, MA)

MQ (with OL, LD)

MQ and MG (with OL, LD)

IBM Corporation, 2010. All rights reserved. ES#57P9006 EC# L86842

- One thick copper level with one thick Aluminum level

Planarized passivation and interlevel dielectrics with a low-K value.

Wire-bond pads or controlled collapse chip connections (C4s)

Optional Electronic Fuse

List of supported base feature devices:

- Vertical PNP (P+/NW diode)

- Bondpads (C4 and Wirebond)

Thin Oxide MOS Varactor

PCDCAP Thin Oxide (similar to Thin Oxide MOS Varactor)

Vertical Natural Capacitor

ES#57P9006 EC# L86842 IBM Corporation, 2010. All rights reserved.

Thin PI Triple Well NFET (requires 1 additional mask; PI)

Schottky Barrier Diode (requires 1 additional mask; NS)

- n+ diffusion (requires one additional mask; OP)

- p+ polysilicon (requires one additional mask; OP)

- OP RR PC Poly Resistor (requires two additional masks; OP and RR)

- OP RP Poly Resistor (requires two additional masks; OP and RP)

IBM Corporation, 2010. All rights reserved. ES#57P9006 EC# L86842

- Single Nitride MIM Capacitor (requires 2 additional masks; QT and HT).

- Single HP (High Performance) MIM (requires one additional mask; QY)

Maximum HA Varactor use voltage = 3.6V

Maximum MIM use voltage:

ES#57P9006 EC# L86842 IBM Corporation, 2010. All rights reserved.

For BEOL L1 resistor limitation, see Back-End-Of-Line L1 Resistor: on page 486.

Operating temperature range of -55 to 125C (junction Temp.)