5780 Thornwood Drive Report No.

R186
Goleta, California 93117 U.S.A. August 31, 1995

OPERATING MANUAL FOR A 6-SCR GENERAL PURPOSE

GATE FIRING BOARD, PART NO. FCOG630D REV. D

INTRODUCTION
This manual is intended to familiarize the user with the salient features and specifications of
the firing board. A simple checkout procedure is included together with typical firing circuit
signal waveforms and connection diagrams. Please note that all component numbers refer to
schematic diagram number E820 Revision D.

PRODUCT DESCRIPTION
GENERAL

The FCOG630D general purpose firing board is designed to be used in a variety of 50Hz and
60Hz applications. Therefore, the FCOG630D may be easily configured by the customer to
optimize its performance. This is accomplished by the use of jumpers, a programming plug,
and component changes.

The compact size of the FCOG630D (152 mm high, 191 mm wide, and 32 mm deep),
enables the OEM or End User to easily incorporate the board in their product design.
Thereby, significantly reducing development costs and time-to-market.

APPLICATION

The general purpose firing board responds to a voltage or milliamp current signal to produce
a delayed set of six, 60 spaced, high current SCR gate pulses. A programming plug adapts
the board to suit various types of SCR controllers or converters (rectifiers). The range of
applications is further enhanced by the use of Auxiliary Firing Board's. These board's extend
the usage to the gating of paralleled SCRs or to remote operation of SCRs.

LSI LOGIC DEVICE

All of the firing circuit logic is contained in a custom 40-pin (U5 - EP1011) or 24-pin (U5A -
EP1014) CMOS LSI gate array. The use of a LSI greatly reduces the component count,
thereby minimizing the board size and maximizing reliability. Additional detail on the firing
circuit theory is contained in an engineering society paper.1 The 12-pulse and four-quadrant
capabilities described in the engineering society paper are not supported by the FCOG630D
general purpose gate firing board. The FCOG6100 general purpose gate firing board is
available for four-quadrant applications. The FCOG1200 or FCOP1200 twelve pulse firing
board/package is available for use in 12-pulse applications.
BOARD MOUNTED CONNECTORS

1 Bourbeau, F. J., "Phase Control Thyristor Firing Circuit: Theory and Applications", Power Quality '89, Long
Beach, California. This report details the operation of the FCOG6100 firing board which is similar to the
FCOG630D.
Rev.5/2/96 p. 1 of 17 Report R186
In order to facilitate installation in the customers equipment, WAGO connectors have been
provided for all customer connections. These connectors utilize a cage-clamp spring to
secure the customers wire. The WAGO connectors will accept a AWG 26 - 14 wire which
has been stripped for 5 to 6 mm. In addition, these connectors can be operated with a screw
driver, eliminating the need for additional tools and hardware.

Gate/Cathode Connectors

The SCR gate/cathode interface is provided by six 2-position WAGO connectors, J1A
through J2C. Jacks J1A through J1C access the gates and cathodes of the three SCRs having
load connected cathodes when the SCRs are arranged in the in-line ac controller or bridge
converter configurations. Similarly, jacks J2A through J2C access the gates and cathodes of
the three SCRs having line connected cathodes.

Power/Control Signal Connector

The firing board is powered by applying either 24Vac or +30Vdc to a 12-position WAGO
connector designated as J3. In addition J3 provides the interface between the customer gate
delay command and inhibit controls. This connector also accesses the outputs of the 30Vdc
rectifier, the regulated +12Vdc and the regulated +5Vdc outputs.

Off-Board Phase Reference Connector

Due to the variety of mains voltages available, the FCOG630D board has been configured to
allow easy access to the phase reference attenuation resistors, R37 - R39. These resistors are
factory selected at 2.0M which is the desired value for mains voltages of 240 to 600Vac. If
operation at mains voltages less than 240Vac is required, please consult schematic diagram
E820 for the recommended values of R37 - R39.

It is essential that the phase reference signals applied to J5 agree with the SCR configuration.
Equipment damage may result if the phase sequence is reversed.

Test Signal Input Connector

A 3-position MTA style cable header, J7, is used to inject low level 3-phase test reference
signals from a firing board test fixture into the delay generator circuit. This allows the board
checkout to proceed without connection to high voltage power.

Auxiliary Firing Board Connector

An 8-position cable header, J6, is provided to connect the six gate command logic signals, as
well as 30Vdc power and common, to the FCOAUX60 Auxiliary Firing Board for gating an
additional set of six SCRs (the FCOAUX60 can be ganged if additional SCRs are required)
in parallel2 with the primary set of SCRs .

GATE DELAY COMMAND

2. The FCOREM60 Auxiliary Firing Board is designed to provide high output gate pulses in order to increase
the reliability of SCR firing in parallel applications. This auxiliary board requires a 30Vac power supply
and utilizes the FCOG630D gate outputs as an input. Both the FCOAUX60 and theFCOREM60 use AMP
Mate-N-Lok connectors and is equipped with two sets of input connectors to facilitate "ganging" for use
in circuits with multiple parallel SCRs.
Rev.5/2/96 p. 2 of 17 Report R186
The gate delay command signal, SIG HI, is factory set for 0.0 to 5.0Vdc. Additional voltage
ranges, or a current signal with an upper limit of 50mA, may be accommodated. The input
resistance presented to the delay command signal is determined by resistor R65, connected in
shunt with the control signal input. The value of R65 is selected at 10 k when the control
signal is a voltage source. As an option, a 0.9Vdc to 5.9Vdc input signal may be used by
changing R47 to 249 k. When the gate delay command is a current signal, R65 is selected
to give a 5.0Vdc level at the maximum delay command signal current.

GATE INHIBITS

SCR gating is inhibited by making either or both of the inhibit signal points, designated as I1
and I2 and appearing at pins 4 and 12 of J3, a logic zero.

In the case of the instantaneous inhibit, I1, resistor RN2-3,4 on the firing board is provided to
pull the I1 signal point low if the connection between I1 and +12Vdc is opened. In
applications where the instantaneous gate inhibit function is not utilized, a jumper wire is
installed between positions 4 and 6 of J3 to hold I1 at +12Vdc.

The inhibit signal I2 is connected to +12Vdc through pull-up resistor RN2-5,6 on the firing
board. When I2 is grounded, the gate delay angle is ramped to the maximum delay angle
before gating is inhibited. This is termed the "Soft-Stop" shutdown mode. Removing the
ground on I2 causes gating to be enabled with the delay angle set to the maximum limit. The
delay angle then ramps down to the commanded angle. This is termed the "Soft-Start" turn-
on mode. The Soft-Stop and Soft-Start periods are determined by timing resistors R63 and
R64, and capacitor C4.3

PHASE-LOSS INHIBIT

A phase loss circuit operates to instantly inhibit SCR gating if one phase is missing. Gating
is enabled when the mains voltage is restored and initiates at the maximum delay angle. The
delay angle then ramps down to the commanded angle at a rate determined by the Soft-Start
RC time constant.

The phase-loss inhibit circuit is also activated when three phase power is initially applied to
the SCRs. Gating is inhibited until the power supply voltage has stabilized. Gating then
commences at the delay angle limit and ramps down to the commanded angle at a rate
determined by the Soft-Start RC time constant.

PHASE REFERENCE SENSING

Low level phase reference signals are produced by resistive attenuators and low pass filters
which operate on the three-phase mains voltage. The mains voltages are accessed at J5. The
reference voltage attenuators consist of 2.0 megohm precision resistors, R37 - R39, and
board mounted low resistance, RN1 -- typically 15.0kohm, precision resistors.

The attenuated mains voltage reference signals are processed by low pass filters having an
attenuation of 6 dB and a phase shift of 60 at the 50 Hz mains frequency. These filters
remove distortion in the attenuated mains voltage signals caused by the non-linear loading of
the mains by the thyristor converter.

The attenuated and filtered mains voltage reference signal from the appropriate mains phases

3. See electrical specifications table for formula's.

Rev.5/2/96 p. 3 of 17 Report R186
are selected by means of CMOS switches, U7, in order to cancel the 60 phase lag caused by
the reference filters. These selected reference signals are then applied to voltage comparators
to produce three phase reference logic signals for input to the phase locked loop.

REFERENCE PHASE ANGLE SELECTION

A programming plug, PP1, is installed to select phase reference logic signals which are either
in-phase with, or 30 lagging, the mains line-to-neutral voltage. In-phase references (PP1
positions 1, 2, and 3 open: positions 4, 5,6,and 7 closed) serve for phase delay control of in-
line antiparallel pairs of SCRs (AC controllers). 30 lagging references (PP1 positions 1, 2,
and 3 closed: positions 4, 5,6,and 7 open) are used with SCR rectifiers (converters).

GATE PULSE PROFILE SELECTION

PP1,position 8, serves to select one of two SCR gate current pulse patterns:

PP1 8 Status Pulse Profile

OPEN One 120-wide burst of 19,200 Hz carrier.
CLOSED Two 30-wide bursts of 19,200 Hz carrier spaced by 30.

The firing circuit uses a phase-locked loop (PLL) circuit locked to the three mains phases.
The PLL oscillator output is counted down and decoded into six 120-wide delayed logic
signals. In pulse pattern #1 above, the 120-wide delayed logic signals are modulated by the
19,200 Hz PLL Voltage Controlled Oscillator (VCO) output signal. The double burst pattern
is formed by modulating the 120-wide delayed logic signals with the 19,200 Hz VCO output
and the 300 Hz output of a divide-by-64 counter. The transformers saturate after
approximately 100s but this is of no consequence because of the current limiting resistor in
series with each of the transformer primary windings.

GATE PULSE AMPLIFIER

Circuitry shown in E820 consisting of transistor array U4, resistors R2 and R4 through R6,
capacitors C11 through C13, and gate pulse isolation modules PM1 through PM6 amplify
and shape the thyristor gate current pulses. Each pulse module consists of a 1.67:1 ratio pulse
transformer tested for 3500Vrms isolation, two secondary diodes, and noise suppression
resistors across the primary and across the gate drive output.

FREQUENCY SELECTION

The jumper, J8, serves to select 50 or 60Hz operation. Install P8 for operation at 60Hz mains
frequency. Installing P8 readjusts the bias of the Voltage Controlled Oscillator (VCO) by
inserting R50, 115k, in parallel with R58.

ENABLE STATUS (L) OR END-OF-RAMP (R) STATUS OUTPUT

A NPN Darlington connected transisor, U4-16, is provided for driving an external lamp or
relay. The transistor is capable of providing external indication of either enable or ramp
status. Installing P9, pins 1 and 2, will configure U4-16 to provide enable status. While
installing P9, pins 2 and 3, will configure U4-16 to provide an end-of-ramp signal for use
with bypass contactors.

U4-16 is capable of sinking 500 mA, current limiting resistor R1 should be selected to
provide proper operation of the external load.

Rev.5/2/96 p. 4 of 17 Report R186

ELECTRICAL SPECIFICATIONS
The electrical specifications of the General Purpose Firing Board are summarized in the
table below. Part numbers refer to drawing E820, rev. D.

Characteristic Performance Requirement. Supporting. Information

1. Line voltage Resistive attenuators and 60 Reference signals automatically
reference phase shift single pole filters. interchanged for negative phase
sensing sequence.
2. Load voltage Resistive attenuators produce Useful for load voltage feedback
sensing. low level replica of load control.
voltage.
3. PLL reference Application: PP1 programming plug:
signal. phasing
w.r.t. mains
line-to-neutral
voltage:
a. ref. signals in a. AC controllers with high a. #1,2,3 open
phase with power factor loads. #4,5,6,7 closed
mains voltage.
b. ref. signals b. Converters of AC b. #1,2,3 closed
lagging mains controllers with low power #4,5,6,7 open
voltage by 30. factor loads.
4. SCR gate Pulse Profile: PP1 #8 status:
waveform. (19,200 Hz carrier)
a. Mode 1 a. 120 burst of 128 pulses a. OPEN
b. Mode 2 b. two 30 bursts of 32 pulses b. CLOSED
5. Input control 0 Vdc to 5.0Vdc control Option 1: 0.9 Vdc to 5.9Vdc
signal. signal. control signal.
Load resistance is 8.33 k. Option 2: a Shunt resistance (R65)
across signal input can be selected
for milliamp control signal.
6. Control signal 653 k Produced by the three 2.00 M
isolation from mains voltage sense resistors @ J5.
ground.
7. Gate delay Increase in command voltage max and min change equally
steady-state produces a proportional with change in Rbias (R48 or
transfer decrease in gate delay angle, R53). ( max-min) changes with
function. .
Rspan (R42).
8. Gate delay Attenuation = -3dB at 119Hz. Frequency response can be
dynamic transfer Phase shift = -45 @ 68Hz. modified by changing summing
function amplifier parameters.
bandwidth.
9. Gate delay angle Gate pulses for same polarity Assumes balanced line-to-line
balance. SCRs are displaced by 120 mains voltage. Balance
1.0. Gate pulses for opposite determined by reference
polarity SCRs are displaced by comparator offset and
180 1.0. attenuator/filter component
tolerances.
10. Effect of D/Df = 1.5/Hz. Due to Type I PLL and 60 phase
frequency. shift low pass reference filters.

Rev.5/2/96 p. 5 of 17 Report R186

11. Effect of phase none SCR gating sequence matches
rotation. mains voltage sequence.
12. Effect of mains 1) unaffected by false 1) No PLL response to short-time
voltage reference voltage zero false reference logic states.
distortion. crossing.
2) 60 filter attenuates 5th 2) Reference filter attenuates the
harmonic by 12.8dB 5th, 7th, 11th, etc. harmonics
relative to fundamental. from 6-pulse SCR switching.
13. Lock acquisition Approximately 29ms. Gating is inhibited for 20ms or
time. longer at power-on.
Inhibit period depends on Soft-
Start time constant.
14. Soft-Start Gating commences at max Soft-Start time constant is set by
and exponentially decays to C4 and R63. R63 20.0k.
the commanded delay when T = (1.5k + R63)(C4)(0.579)
<I2> is ungrounded (J3-12). T = msec, R = k, C = F
15. Soft-Stop Gate-delay angle ramps to Soft-Stop time constant is set by
max before being inhibited C4 and R64. R64 1.0k.
when <I2> is grounded. T = R64(C4)(1.84)
T = msec, R = k, C = F
16. Phase loss Loss of a mains voltage or Gating resumes with = max.
inhibit. severe phase unbalance causes ramps to the commanded delay
gate inhibit. angle as determined by the Soft-
Start time constant.
17. Power-on Phase loss inhibit circuit is Same delay angle response as with
inhibit. activated at power-on. phase loss inhibit.
18. Instantaneous Opening the connection of
inhibit. <I1> to +12V instantly inhibits
SCR gating. Closing the
connection of <I1> to +12V
instantly enables SCR gating.
19. SCR gate Ton and Toff vary from 24s Gate current ON and OFF times
current to 26s. vary with gate delay angle because
individual pulse of 300Hz FM in the
width. VCO output.
20. Peak gate drive 15V With a 30Vdc supply voltage
open circuit
voltage
21. Peak gate drive 2.0A Measured with a 30Vdc supply
short circuit voltage and a 1.0 load resistor
current.
22. Gate drive .5A in .5s Measured with a 30Vdc supply
current voltage and a 1.0 load resistor
risetime(short
circuit)
23. Ambient 0C to 70C
temperature.
23. Gate pulse EP1019NF pulse transformer
isolation. modules: 3500 Vrms, 60s.

Rev.5/2/96 p. 6 of 17 Report R186

 INSTALLATION AND CHECKOUT
The following procedure should be followed to ensure proper operation prior to the
application of mains power to the SCR unit.

1. Ensure that the power is off! Connect mains voltage to J5-1, J5-3, and J5-5.

2. Connect board power and control signals to J3.

3. Energize the board power supply.

4. Verify the presence of regulated +12Vdc 2.5% at J3-6 and regulated +5Vdc 5% at
J3-7.

5. Energize the mains voltage.

6. Verify that the PLL is in lock by noting the response of the A-phase detector output at
TP3 to a full-scale change in the delay command signal voltage applied to pins 10 and
11 of J3.

7. Verify that the DC level of the VCO control voltage at TP2 is approximately 5.0Vdc.
This voltage is factory set by selection of R58.

8. Determine the PLL gate delay angle from the pulse width of the A-phase detector
output at TP3: Calibrate the oscilloscope timebase at 20/div. Read the gate delay
angle directly from the TP3 pulse off time.

9. Vary the delay command voltage from 0Vdc to 5.0Vdc. Observe that the gate delay
angle at TP3 has the desired minimum and maximum values.

10. To increase the minimum and maximum gate delay angles by an equal amount,
increase the value of the delay bias resistor, R48. To increase the difference between
the maximum and minimum delay angles, reduce the value of the delay span resistor,
R42.

Rev.5/2/96 p. 7 of 17 Report R186

 FIRING BOARD WAVEFORMS
The following waveforms were obtained with the firing board connected to 240 Vac 50 Hz
balanced 3-phase power via J2A-1, J2B-1, and J2C-1. All logic signals are shown with a
scale factor of 10 V/div. The time (X) axis scale factor is 40/div. unless otherwise noted.
Component designations U7 etc. refer to drawing number E820, Rev. NC. Component pins
are designated U7-1, etc.

A. Mains Voltage Signals, A phase.

Trace: 1. Line to neutral mains voltage, 150 V/div.

2. Attenuated and filtered mains voltage at RN5-5, .2 V/div.
3. Reference comparator output at TP5, U7-15

a. 0 references b. -30 references

B. Phase Detector Signals, A phase.

Trace: 1. A-phase reference at TP5 (U7-15).

2. Delayed ring counter output at TP6 (U5-26)
3. Phase detector output at TP3 (U5-22).

a. = 175 b. = 18

Rev.5/2/96 p. 8 of 17 Report R186

C. PLL Summing Amplifier Signals

Trace: 1. A phase detector output at U5-22 (TP3)

2. B phase detector output at U5-21
3. C phase detector output at U5-20
4. Summing amplifier output at U6-8 (TP2), 2 V/div.

a. = 175 b. = 18

D. Phase Loss Comparator Signals

Trace: 1. Upper threshold voltage at U3-7

2. Summed and filtered A-B-C reference signal at U3-5 (TP8)
3. Lower threshold at U3-4

4. comparator output at U3-1 ( PL logic signal)

a. normal operation b. one mains phase missing

Rev.5/2/96 p. 9 of 17 Report R186

E. Pulse Transformer Output into 1.0 load (.5 A/div.)

1. 120 burst of 19kHz 2. Two 30 bursts

3. Initial pulse detail (.5 A/div., 2 s/div.)

Rev.5/2/96 p. 10 of 17 Report R186

 A B C B C
A

zig-zag

Rev.5/2/96
transformer
+
k LOAD
+ g -A -B -C
k
-
g LOAD
-A -B -C
- k g
k g -A -B -C
-A -B -C 1 2 1 2 1 2 1 2 1 2 1 2
1 2 1 2 1 2 1 2 1 2 1 2 J1A J1B J1C J2A J2B J2C
J1A J1B J1C J2A J2B J2C
1 J5
1 J5 3 FCOG630D
3 FCOG630D FIRING BOARD
FIRING BOARD 5
5

p. 11 of 17
J3
J3 7 10 8 12 11 4 6 1 2
I1

I2

10 8 12 11 4 6 2
+5

7 1
+12

com

com

I1

I2

+5
24

+12

com
on

com
on
on 24 VAC
on off off
VAC
off off
DELAY SOFT INSTANT
DELAY SOFT INSTANT COMMAND INHIBIT INHIBIT
COMMAND INHIBIT INHIBIT

Firing Board Setup (Recommended): Firing Board Setup (Recommended):

30 phase references. 30 phase references.

2-30 burst gating. 2-30 burst gating.
6 to 176 delay angle range (R42 = 16.5k, R48 = 107k). 6 to 176 delay angle range (R42 = 16.5k, R48 = 107k).

2. 6-Pulse 1-Quadrant Bridge Semi-Converter

Report R186
1. 3-Pulse 2-Quadrant Half Bridge Converter
 B A B C
A C

Rev.5/2/96
zig-zag
g transformer
+A +B +C
+
LOAD
k -
g
-B
-
-A -C
LOAD
+A +B +C -A -B -C +
k g k g
+A +B +C -A -B -C +A +B +C -A -B -C
1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2
J1A J1B J1C J2A J2B J2C J1A J1B J1C J2A J2B J2C

1 J5 1 J5
3 FCOG630D 3 FCOG630D
5
FIRING BOARD 5 FIRING BOARD

p. 12 of 17
J3 J3
7 10 8 12 11 4 6 1 2 7 10 8 12 11 4 6 1 2
I1

I2

+5

I1

I2

+5
+12

com

+12
com

com

com
on 24 24
on on on
VAC VAC
off off off off

DELAY SOFT INSTANT DELAY SOFT INSTANT

COMMAND INHIBIT INHIBIT COMMAND INHIBIT INHIBIT

Firing Board Setup (Recommended): Firing Board Setup (Recommended):

30 phase references. 30 phase references.

2-30 burst gating. 2-30 burst gating.
12 to 144 delay angle range (R42 = 23.7k, R48 = 75.0k). 6 to 176 delay angle range (R42 = 16.5k, R48 = 107k).
Jumper pads 7&15 of J4.
Obtain phase references from the AC mains (J5).

Report R186
3. 6-Pulse 2-Quadrant Bridge Full-Converter 4. 6-Pulse 2-Quadrant Star Converter
 A B C A B C

+
zig-zag

Rev.5/2/96
transformer LOAD
-

high voltage
- k diode rectifier
g
LOAD +A +B +C
+A +B +C -A -B -C +

k g IPT -A -B -C
+A +B +C -A -B -C
1 2 k g
1 2 1 2 1 2 1 2 1 2
+A +B +C -A -B -C
J1A J1B J1C J2A J2B J2C
1 2 1 2 1 2 1 2 1 2 1 2
1 J5 J1A J1B J1C J2A J2B J2C
3 FCOG630D
5
FIRING BOARD 1 J5
FCOG630D

p. 13 of 17
3
J3 5 FIRING BOARD
7 10 8 12 11 4 6 1 2

I1

I2
J3

+5
+12

com

com
24 7 10 8 12 11 4 6 1 2
on on
I1

I2

+5

VAC
+12

com

com

off off
on 24
on
DELAY SOFT INSTANT VAC
off off
COMMAND INHIBIT INHIBIT
DELAY SOFT INSTANT
COMMAND INHIBIT INHIBIT

Firing Board Setup (Recommended): Firing Board Setup (Recommended):

0 phase references. 30 phase references.
2-30 burst gating. 2-30 burst gating.
6 to 165 delay angle range (R42 = 16.9k, R48 = 93.1k). 6 to 165 delay angle range (R42 = 16.9k, R48 = 93.1k).
Positive phase sequence only. Obtain phase references from the AC mains (J5).
Obtain phase references from the AC mains (J5). 6. 6-Pulse Neutral Point Converter

Report R186
5. 6-Pulse 2-Quadrant Star Converter with IPT
 A B C A B C

Rev.5/2/96
g k g k

-A +A -A +A
+ +
LOAD -B LOAD
-B +B +B
- -
-C +C -C +C
k g k g
+A +B +C -A -B-C +A +B +C -A -B -C
1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2
J1A J1B J1C J2A J2B J2C J1A J1B J1C J2A J2B J2C

1 J5 1 J5

p. 14 of 17
3 FCOG630D 3 FCOG630D
5 FIRING BOARD 5 FIRING BOARD
J3 J3
7 10 8 12 11 4 6 1 2 7 10 8 12 11 4 6 1 2

I1
I1

I2
I2

+5
+5

+12
+12

com
com

com
com

on 24 on 24
on on
VAC VAC
off off off off

DELAY SOFT INSTANT DELAY SOFT INSTANT

COMMAND INHIBIT INHIBIT COMMAND INHIBIT INHIBIT

Firing Board Setup (Recommended):

Firing Board Setup (Recommended):
30 phase references.
30 phase references.
2-30 burst gating.
2-30 burst gating.
6 to 165 delay angle range (R42 = 16.9k, R43 = 93.1k).
6 to 165 delay angle range (R42 = 16.9k, R43 = 93.1k).
7. 6-Pulse Controlled and Uncontrolled Converters

Report R186
in Series 8. 6-Pulse Semi-Converters in Series
 A B C
A

k -A

Rev.5/2/96
g
+A1 +B1 +C1 +A2 +B2 +C2
B k g THREE
+ PHASE
-B LOAD
LOAD
-A1 -B1 -C1 -A2 -B2 -C2
-
C
k g
+A2 +B2 +C2 -A2 -B2 -C2 -C
1 2 1 2 1 2 1 2 1 2 1 2
J1A J1B J1C J2A J2B J2C k g
J3 -A -B -C
FCOAUX60 AUXILIARY 1 2
1 2 1 2 1 2 1 2 1 2
FIRING BOARD
k g J1A J1B J1C J2A J2B J2C
+A1 +B1 +C1 -A1 -B1 -C1
1 J5
1 2 1 2 1 2 1 2 1 2 1 2 FCOG630D
3
J1A J1B J1C J2A J2B J2C J6 5
FIRING BOARD

p. 15 of 17
1 J5
J3
3 FCOG630D 7 10 8 12 11 4 6 1 2
5 FIRING BOARD
I1

I2

+5
+12

com

com

J3 on 24
on
7 10 8 12 11 4 6 1 2 VAC
off off

I1

I2

+5
+12

com

com
on 24 DELAY SOFT INSTANT
on
VAC COMMAND INHIBIT INHIBIT
off off

DELAY SOFT INSTANT

COMMAND INHIBIT INHIBIT
Firing Board Setup (Recommended):

Firing Board Setup (Recommended): 0 phase references.

120 burst gating.
30 phase references. 6 to 176 delay angle range (R42 = 16.5k, R48 = 107k).
2-30 burst gating.
6 to 130 delay angle range (R42 = 26.7k, R48 = 61.9k).
10. 3-Thyristor/3-Diode In-Line AC Controller

Report R186
9. 6-Pulse 2-Quadrant Parallel Bridge Converters (thyristors load-to-line)
 g k g k
A A
+A +A -A

Rev.5/2/96
B THREE B THREE
PHASE PHASE
+B LOAD +B -B LOAD

C C
+C +C -C

k g k g
+A +B +C +A +B +C -A -B -C
1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2
J1A J1B J1C J2A J2B J2C J1A J1B J1C J2A J2B J2C
1 J5 1 J5
3 FCOG630D 3 FCOG630D
5 FIRING BOARD 5
FIRING BOARD

p. 16 of 17
J3 J3
7 10 8 12 11 4 6 1 2 7 10 8 12 11 4 6 1 2

I1

I2

+5
I1

I2

+5

+12
+12

com
com

com
com

24 24
on on on on
VAC VAC
off off off off

DELAY SOFT INSTANT DELAY SOFT INSTANT

COMMAND INHIBIT INHIBIT COMMAND INHIBIT INHIBIT

Firing Board Setup (Recommended): Firing Board Setup (Recommended):

0 phase references. 0 phase references.

120 burst gating. 120 burst gating.
6 to 176 delay angle range (R42 = 16.5k, R48 = 107k). 6 to 176 delay angle range (R42 = 16.5k, R48 = 107k).
Obtain phase references from AC mains (J5).
11. 3-Thyristor/3-Diode In-Line AC Controller

Report R186
(thyristors line-to-load) 12. 6-Thyristor In-Line AC Controller
 A B C

A B C

Rev.5/2/96
g k g k
+A +B +C +A +B +C

-A -B -C -A -B -C

k g k g
+A +B +C -A -B -C +A +B +C -A -B -C
1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2
J1A J1B J1C J2A J2B J2C J1A J1B J1C J2A J2B J2C

1 J5 1 J5
3 FCOG630D 3 FCOG630D
5
FIRING BOARD 5
FIRING BOARD

p. 17 of 17
J3 J3
7 10 8 12 11 4 6 1 2 7 10 8 12 11 4 6 1 2
I1

I2

+5

I1

I2

+5
+12

com

+12
com

com

com
on 24 on 24
on on
VAC VAC
off off off off

DELAY SOFT INSTANT DELAY SOFT INSTANT

COMMAND INHIBIT INHIBIT COMMAND INHIBIT INHIBIT

Firing Board Setup (Recommended): Firing Board Setup (Recommended):

0 phase references. 0 phase references.

120 burst gating. 120 burst gating.
6 to 176 delay angle range (R42 = 16.5k, R48 = 107k). 6 to 176 delay angle range (R42 = 16.5k, R48 = 107k).
Obtain phase references from AC mains (J5).

Report R186
13. 6-Thyristor Inside-the-Delta AC Controller 14. 6-Thyristor Inside-the-Neutral AC Controller