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The Case of the Closing Eyes

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 Agenda
Introductions
Market Overview
Design Engineering
Test & Measurement
Panel Discussion
 Market Adoption
400G 100G
 The top-to-bottom 400G standards
Distance Standard Modulation/signaling e.g.
X,000 km OIF, OTN, ITU Complex optical DP-QPSK
100M (MMF) Ethernet PAM2 at 25 GBd 400GBASE-SR16
10 km Ethernet PAM4 at 25 GBd 400GBASE-LR8
2 km Ethernet PAM4 at 25 GBd 400GBASE-FR8
500 m Ethernet PAM4 at 56 GBd 400GBASE-DR4
Backplane < 1m OIF CEI PAM4 at 25 GBd CEI LR
Interconnect Ethernet NRZ CDAUI-16,
module to chip, OIF CEI PAM4 CDAUI-8
chip to chip CAUI-4
CEI VSR
Ransom Stephens
 How we got here
Photonics ? 100G: 425 Gb/s
1000

PAM4

Serdes
Serdes
FEC
Data rate (Gb/s)

100

Eyes Close 400G: 850 Gb/s

10
Equalization

Serdes
Serdes
1 Differential signaling + clock recovery
2000 2005 2010 2015 2020
 PAM4
4 level Pulse Amplitude Modulation

T
T

PAM4 has 4 levels but half the bandwidth of NRZ-PAM2

PAM4 is complicated
2 bits/symbol
4 symbol levels
6 rising/falling edges
12 transitions
3 eye diagrams per UI
75% average transition
density
 Pros and cons of PAM4
Good news:
2x data rate at same baud/bandwidth
Bad news:
Signal to noise ratio < 1/3
Good news:
BER requirements are way up!
10-6 instead of 10-12 or 10-15
Bad news: FEC takes time, power, and space
Cathy Liu
 Path and Solution from 25G to 56G - PAM4 SerDes
Complexity of PAM4 SerDes Design
Operate 25Gb/s NRZ channels at twice the data rate with PAM4 detection penalty
Low power for high density integration
Post FEC performance

Avago 58G PAM4 SerDes Silicon Solution

Multiple generations PAM4 SerDes in silicon
Support OIF CEI-56G-VSR/MR/LR, IEEE 400GE and 64GFC emerging standards
TX: 56.25 Gb/s PAM4

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RX: 56Gb/s, 25dB Insertion Loss, PRBS31, Pre-FEC BER = 7E-12

eBert
Inner Eye
RX: 51.56Gb/s, 32dB Insertion Loss, PRBS31, Pre-FEC BER = 1E-6

eBert
Inner Eye
Mark Marlett
 Near End Eyes: short channel

Near End Eyes: Lots of Pre and Post Cursor EQ needed for long channel
Channel response: ~-33dB at Nyquist
Left: Scope Near and Far end channel
Right: Chip Eye Contour (raw BER ~1e-7)
Note: Channel running error free
Mike Peng Li
 FEC Kills DJ and RJ ?
False !!
FEC is NOT everywhere
FEC latency prohibitive for high performance computing (HPC) and high performance memory
(HPM)
For those links, BER of 1e-15 is required, so does DJ and RJ
Even with FEC
Pre-FEC BER needs to be at 1e-6, and DJ and RJ are needed to provide statistical RSS link jitter
margin maximizing, even though TJ could be measured directly with an sampling scope

Forward Error Correction (FEC)

H FER L FER
FEC

1e-6 <1e-15
Ref: http://www.ieee802.org/3/bs/public/15_01/nicholl_3bs_01b_0115.pdf
 FEC is Deterministic and Equal?
False !!
Smiths FEC model (A) differs from Johnsons FEC model (B)
FEC model assumptions are deterministic, but bit error is statistical
Who is right ?
Needs FEC measurement data

(B)
(A)
=
First FEC model vs measurement comparison by Altera/Intel
Marty Miller
 T&M challenges
How to know if your Tx is doing what you intend?
In this case 1-pre, 1-post emphasis closes eye (left)

Additional features built-in to help designer integrator to explore

scenarios.
Same emphasis using noise/jitter-free (using PRBS 15)
Making sense of signals at the Tx
Open the eye by training an emulated equalizer (FFE)
 More than recording demanded
Recording Channel emulation (embedding)
cable de-embedding

Receiver emulation:
virtual probing
CTLE, FFE, CDR, DFE (including training)
Behavioral simulation of Transmitter
Analysis
Noise, Jitter, BWL, emphasis, test Patterns, etc.
Pavel Zivny
 Looking at the mask test it doesnt look too good
Take a nice PAM2 signal Mask Margin = 53% @ Hit Ratio = 5.0E-05
Add an LSB, and what have you got?
Mask Margin = -35% @ Hit Ratio = 5.0E-05
Note the horizontal margin also goes down.
Overall, 3x worse
vertical, 2x worse
horizontal so its
6x worse

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 So it is painful to move to PAM4.
We can measure instead of extrapolate the bathtub
Actually the bad PAM4 eye is better than it looks:
most designs add FEC (Forward Error
Correction) code, and the link works even if the
raw BER (before FEC) is BER= 10-6 (instead of
the BER= 10-12 or BER= 10-15)
And the oscilloscope can now measure the
bathtub @BER, not just extrapolate it.
So measuring the bathtub is an option instead
of mask. Or some form of bathtub, like TDEC .
But its still harder.
The eye closes fast!
The vertical eye closure
vs the T&M BW:
Paper Wed. at 8:30 am

2
 Problem of what to measure
We measure so many things (Rise-times fall-times measurement)
We emulate the channel
We de-embed the fixture
We equalize with FFE/DFE/CTLE
Is that the forest, or the trees?
BUT
What is the best measure?
Is it still the eye diagram?
If yes, with a mask?
Or is it TDEC?
Or is it COM?

2
Greg LeCheminant
 We still need to test the PAM4 receiver
The basic premise: Will the receiver achieve
the desired BER when paired with the worst
case allowed TX paired with the worst case
allowed channel
What did we learn from NRZ?
Stressed Receiver Sensitivity
Creating the precision degraded eye is
1) expensive to build
2) difficult to verify
3) difficult to maintain over time (especially for
optical systems)

From IEEE 802.3ba

 PAM4 receiver test will be difficult
The PAM4 stress signal: Harder to
create, harder to measure
The bad news
True PAM4 BERTs in infancy for
25Gbaud, yet we now also need 50+
Gbaud BERTs
More stress parameters likely to be Dispersion/ISI Nonlinearity
employed compared to NRZ
Some good news:
Start with an ideal signal
Only need to test to high BER (generally
> 1e-6, much faster test times) and intentionally distort it
Internal error counting can offer some to emulate what actual
help system signals will exist at
AWG paired with a DCA can create a the receiver
calibrated PAM4 stress signal
 Questions for T&M
How do we characterize Near End Eye? How do we characterize Far End Eye?
Tx Pre and Post Cursor accuracy Clock Recovery
DCD or MSB/LSB accuracy or deviations Ideal Eq vs Si EQ.
Jitter/Noise Decomposition? Is part doing what is expected?
SNDR Scope Rx sensitivity
Including EQ effects Small signal clock recovery
Jitter separated by transitions Noise characterization
Where and When 400G BERT/Scope Seems Si is better than Scope at clock
be Available? recovery sometimes
FPGA could be alternative? How do we create a calibrated stressed
Creation of a clean reference eye PAM4 EYE?
Full complement of stressors for PAM4?
ISI + TX EQ
Noise + Jitter
Crosstalk
CRU