DDR3 To DDR4 03202013

DDR4 Technology
DDR3 to DDR4 Transition
2012 Micron Technology, Inc. All rights reserved. Products are warranted only to meet Microns production data sheet specifications. Information, products, and/or specifications
are subject to change without notice. All information is provided on an AS IS basis without warranties of any kind. Dates are estimates only. Drawings are not to scale. Micron and
the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners.
March 20, 2013 Micron Confidential | 2012 Micron Technology, Inc. | 1

DDR3 to DDR4 Comparison
Features/Options DDR3 DDR4 Comments
Voltage (core, /IO) 1.5V 1.2V Reduces memory power demand
Vref Inputs 2 DQs and CMD/ADDR 1 CMD/ADDR VREFDQ now internal
Yes Probably
Low Voltage Std. Memory power reductions
(DDR3L at 1.35V) (likely 1.05V)
Better enable large capacity

Densities 512Mb8Gb 2Gb16Gb
memory subsystems
Internal Banks 8 16 More banks
Bank Groups (BG) 0 4 Faster burst accesses
Page Size x4/x8/16 1KB/1KB/2KB 512B/1KB/2KB X4 use less activation current
tCK 667MHz to 1.6GHz

DLL enabled 300MHz to 800MHz Higher data rates
(625MHz minimum)
10MHz to 125MHz
tCK DLL disabled undefined to 125MHz DLLoff fully supported
(optional)
2
3/20/2013 Micron Confidential | 2012 Micron Technology, Inc. | 2
800, 1066, 1333 1600, 1866, 2133

Data Rate - Mb/s Migration to higherspeed I/O
1600, 1866, 2133 2400, 2667, 3200
Prefetch 8-bits 8-bits

Similar default bursting format
(MIN READ burst) (4 clocks) (4 clocks)
Burst length BC4, BL8 BC4, BL8 Same functionality
(1) Fixed, via MRS (1) Fixed, via MRS

Burst type Similar default bursting format
(2) OTF (2) OTF
Access (CL,tRCD,tRP) 14ns+/- 14ns+/- Similar access timing
Additive Latency 0, CL-1, CL-2 0, CL-1, CL-2 Same programmability
READ Latency AL + CL AL + CL DDR4 has more values, same concept
WRITE Latency AL + CWL AL + CWL DDR4 has more values, same concept
Data Strobes Differential Only Differential Only Reduce data strobe crosstalk
Driver / ODT 240 External 240 External Improves accuracy over voltage and
Calibration Resistor Resistor temperature; same methodology
3
DQ Driver (STD) 34 34 Optimized for DIMM applications
DQ Driver (ALT) 40 48 Optimized for PtP applications
DQ Bus Termination ODT ODT Optimized for higher data rates
DQ Bus SSTL15 POD12 Mitigate I/O noise and power
120, 60, 240, 120, 80, 60,

Rtt Values Support higher data rates
40, 30, 20 48, 40, 34
Disables during
Rtt not allowed READ bursts Ease of use
READ bursts
Nominal, Dynamic, Additional control mode,

ODT Modes Nominal, Dynamic
Park Supports OTF value change
ODT signaling ODT signaling Ease of ODT control, allows non-

ODT Control
required not required ODT routing on PtP applications
4
MultiPurpose Register Four registers 1 Four registers 3 Provides additional specialty

(MPR) Defined, 3 RFU Defined, 1 RFU readout
DQS captures CK, DQS captures CK, De-skews fly-by layout used
Write Leveling
DQ drives CK state DQ drives CK state by modules
RESET# Dedicated input Dedicated input Disable outputs, Resets DRAM
VPP Supply none 2.5V Power efficiency to array
VREFDQ Calibration none supported Optimize internal VREFDQ
Bank Group none four Faster burst accesses
Low-power Auto Self

None (ASR opt.) supported Lower SR Current
Refresh
Temperature Controlled Lower refresh current without

none supported
Refresh (TCR) impacting controller
Fine Granularity Refresh none supported Efficient Refresh scheduling

5
CMD/ADDR Latency (CAL) none supported Efficient command scheduling
Data Bus Write CRC none supported Error detection of data traffic
Data Bus Inversion (DBI) none supported Mitigate I/O noise and power
Per DRAM Addressability none supported Optimize calibration
C/A Parity none supported Error detection of CMD/ADDR bus
Gear-Down Mode none supported Support CMD/ADDR @ faster tCK
Connectivity Test Mode Improved part down

none supported
Boundary Scan (x16) manufacturability
Maximum Power Savings none supported Very low powered-on state
Programmable READ and

none supported Improved data bus signaling
WRITE Preambles
6
READ Preamble
none supported Improved READ training
Training
Quicker exiting of SR
Self Refresh Abort none supported
mode
Command Input
none supported Multiplexes 3 inputs
(ACT_n)
Pin-out/Package 78-ball; x4, x8 78-ball; x4, x8

Small package sizes
(FBGA only) 96-ball; x16 96-ball; x16
240pin UDIMM, RDIMM 288pin UDIMM, RDIMM; Improve Power:Ground

Modules - pins
204pin SODIMM 256pin SODIMM ratio, reduce xTLK
240pin 1.0mm 284pin 0.85mm Improve Power:Ground

Modules pin pitch
204pin 0.6mm 256pin 0.5mm ratio, reduce xTLK
7
DDR4 Options: MR0 MR3
= New for DDR4
MRx Feature / Option MRx Feature / Option

0[12] RFU 1[0] DLL Enable
0[11:9] WR / RTP 2[12] WRITE data bus CRC
0[8] DLL Reset 2[11:9] Dynamic ODT (RTT_Wr)
0[7] Test Mode (Supplier use only) 2[7:6] Low-power Auto Self Refresh Mode
0[6:4,2] CAS latency (CL) 2[5:3] CAS Write Latency (CWL)
0[3] Burst Type 3[12:11] MultiPurpose Register (MPR)
0[1:0] Burst Length 3[10:9] Write CMD when DM
1[12] Data output disable (Qoff) 3[8:6] Fine Granularity Refresh Mode
1[11] Termination DQ strobe (TDQS) 3[5] Temp Sensor Readout
1[10:8] Nominal ODT (RTT_Nom) 3[4] Per DRAM Addressability
1[7] Write Leveling Mode 3[3] Gear-Down Mode
1[4:3] Additive Latency 3[2] MultiPurpose Register Access
1[2:1] Output driver Impedance (ODI Ron) 3[1:0] MultiPurpose Register Page Select
8
DDR4 Options: MR4 - MR6
= New for DDR4
MRx Feature / Option MRx Feature / Option

4[12] Write Preamble 5[10] Data mask (DM)
4[11] Read Preamble 5[8:6] Park ODT (RTT_Park)
4[10] Read Preamble Train mode 5[5] ODT Input Buffer Power Down
4[9] Self Refresh Abort 5[4] C/A Parity error status
4[8:6] CMD ADDR Latency (CAL) 5[3] CRC Error Status
4[4] Internal VREFDQ monitor 5[2:0] C/A Parity Latency Mode
4[3] TCR 6[12:10] tCCD_L
4[2] TCR Range 6[7] VREFDQ Calibration Enable
4[1] Maximum Power Savings 6[6] VREFDQ Calibration Range
5[12] READ DBI Enable 6[5:0] VREFDQ Calibration Value
5[11] WRITE DBI Enable
9
DDR3 and DDR4 = Same x4/x8 Dimensions
JEDEC max package footprint shown
DDR3 DDR4
10
DDR3 and DDR4 = Same x16 Dimensions
JEDEC max package footprint shown
DDR3 DDR4
11
DDR3 vs. DDR4 x8 Pin Comparison x8
DDR3 DDR4
DDR4 Pins added VSS
VDD
12
9
9
8
VDDQ (2)
VPP 0 1
VSSQ 5 4
VDDQ 4 6
VPP VREFCA 1 1
VREFDQ 1 0
Bank Group (2) Bank Group 0 2
Bank Address 3 2
DBI_n Address 16 16
DQ 8 8
ACT_n DQS/DQS# 2 2
CK/CK# 2 2
PAR
CKE 1 1
CS 1 1
ODT 1 1
Alert_n ACT 0 1
RAS 1 1
TEN CAS 1 1
WE 1 1
DDR3 Pins eliminated DM/TDQS/DBI
ZQ
2
1
2
1
VREFDQ
Reset 1 1
TEN 0 1
PAR 0 1
Bank Address (1 of 3) Alert 0 1
Total 73 75
VDD (1), VSS (3), VSSQ (1) New for DDR4
12
New DDR4 Pins
ACT_n
Active command input
ACT_n low: RAS/CAS/WE pins treated as address pins (A16:A14)
RA16, RA15, RA14
ACT_n High: RAS/CAS/WE pins treated as command pins

RAS_N, CAS_n, WE_n
VPP
Power supply for internal word line driver

Improves activation current efficiency
2.5V (-2.375V to 2.75V)
Allows VDD to operate at lower voltage level
Approx. 10% power savings
13
New DDR4 Pins
TEN (Active high, input)

Connectivity Test Mode (Boundary Scan)
Some CMOS rail-to-rail inputs, some loose SSTL based
PAR (Active high, input)

Parity bit - Even Parity
Total # of 1s in transmitted signal, including Parity, is even
Alert_n (Active low, output)

Output signal indicates an error event
Both C/A Parity Mode and CRC Data Mode
14
New DDR4 Pins
DBI_n (Active low, I/O)

Data Bus Inversion Mode
Input Low = DRAM inverts WRITE Data received at DQ inputs
Output Low = READ Data from DQ outputs is inverted data
Power savings possible due to POD I/O
BG[1:0] Bank Group Address

Split 16 banks in to groups of four
Allows for fast bank to bank access when to a different group
C0/CKE1, C1/CS1_n, C2/ODT1

Supports single load stacking, up to 8high
For x4 and x8 use only
15
DDR4 Target Speed Bins
Data rate tRCD/tRP/

(MT/s) CL (clocks) tRCD (ns) tRP (ns) CL (ns)
1600 (-125E) 11-11-112 13.75 13.75 13.75
1866 (-107E) 13-13-131, 2 13.92 13.92 13.92
2133 (-093E) 15-15-151, 2 14.06 14.06 14.06
2400 (-083E) 16-16-161, 2 13.32 13.32 13.32
2666 (-075E) TBD TBD TBD TBD
3200 (-063E) TBD TBD TBD TBD
Note 1 Timing is backwards compatible with slower speed bin

Note 2 CL9 at tCK of 1.5ns (1333MT/s bit rate) likely supported
16
DDR4 Densities and Addressing
Bank
Groups Banks Page
tRFC (BG) (in BG) Row Col Size
Configuration
x4 160ns 4 4 15 10 512B
2Gb x8 160ns 4 4 14 10 1KB
x16 160ns 2 4 14 10 2KB
x4 260ns 4 4 16 10 512B
4Gb x8 260ns 4 4 15 10 1KB
x16 260ns 2 4 15 10 2KB
x4 350ns 4 4 17 10 512B
8Gb x8 350ns 4 4 16 10 1KB
x16 350ns 2 4 16 10 2KB
x4 TBD 4 4 18 10 512B
16Gb
x8 TBD 4 4 17 10 1KB
x16 TBD 2 4 17 10 2KB
17
DDR4 Features
New DDR4 and Significantly Changed DDR3
DDR3 Features Essentially Not Altered Omitted

DDR4 New Features Discussed
DDR4 Feature DDR4 Feature
Interfaces (VDD termination) Temperature Controlled Refresh (TCR)
Output driver (POD) Fine Granularity Refresh (FGR)
Bank Group Architecture MPR Function and readout
ODT - Rtt_Park ACT_n Control
ODT Buffer Disable Mode Command/Address Latency (CAL)
VREFDQ Supply & Calibration Data Bus Inversion (DBI)
Data Input Specification Per DRAM Addressability (PDA)
Programmable WRITE Preamble Gear-Down Mode
Programmable READ Preamble Maximum Power Savings Mode (MPSM)
READ Preamble Training CRC Data Bus
DLLoff Mode C/A Parity
Self Refresh Abort Connectivity Test Mode
Low Power Auto Self Refresh (LPASR)

19
DDR4 Interfaces
Clock
Proven DDR3 scheme - Differential interface
Command and Address
Proven DDR3 scheme - SSTL based interface
Terminated to VDD/2 (VTT), series R if PtP if not fly-by
ALERT_n used to qualify RAS_n/A16, CAS_n/A15, and WE_n/A14
Databus
Proven GDDR scheme - POD12 interface (Pseudo-Open-Drain)
Terminated to VDDQ
No additional supply required, just add PU resistor
Reduces system power - power {only} consumed when driving low
DBI allows majority ones providing extra power savings
Similar 34 driver impedance with optional 48 instead of 40
20
DDR4 Output Driver
DDR3 Push-Pull DDR4 Pseudo Open Drain
21
x4/x8 DDR4 Bank Group Architecture
16 banks (4 x 4) for x4 and x8 configurations
(4 x 4) defined as 4 bank groups, each having 4 banks

DDR4 vs DDR3 Bank Architecture
Internal
DDRx MT/s (min) MT/s (max) tCK (max) tCK (min) Preftech
Access (min)
1 200 400 10ns 5ns 2n 10ns
2 400 800 5ns 2.5ns 4n 10ns
3 800 1600 2.5ns 1.25ns 8n 10ns
4 1600 3200 1.25ns 0.625ns 16n 10ns
4 1600 3200 1.25ns 0.625ns 8n 5ns
tCCD_S @ 4CK = 5ns
tCCD_L @ 5CK = 6.25ns
DDR4 adder if like DDR3

DDR3 DDR4
tCCD_s
tCCD_L

DDR4 Bank Architecture Specs
DDRx Parameter 1600 1866 2133 2400
3 tCCD 4nCK 4nCK 4nCK na
4 tCCD_S 4nCK 4nCK 4nCK 4nCK
4 tCCD_L 5nCK 5nCK 6nCK 6nCK
3 tRRD (1K) 4nCK, 5ns 4nCK, 5ns 4nCK, 5ns na
4 tRRD_S (1K) 4nCK, 5ns 4nCK, 4.2ns 4nCK, 3.7ns 4nCK, 3.3ns
4 tRRD_L (1K) 4nCK, 6ns 4nCK, 5.3ns 4nCK, 5.3ns 4nCK, 4.9ns
3 tWTR 4nCK, 7.5ns 4nCK, 7.5ns 4nCK, 7.5ns na
4 tWTR_S 2nCK, 2.5ns 2nCK, 2.5ns 2nCK, 2.5ns 2nCK, 2.5ns
4 tWTR_L 4nCK, 7.5ns 4nCK, 7.5ns 4nCK, 7.5ns 4nCK, 7.5ns

x16 DDR4 Bank Group Architecture
8 banks (2 x 4) for x16 configuration
(2 x 4) defined as 2 bank groups, each having 4 banks

ODT (On-Die Termination)
DDR4 added an additional ODT mode (MR5) from what DDR3
provided (Rtt_Nom and RTT_Wr)
Rtt_Park - value is applied when the ODT pin is not high (active)
Dynamic ODT, when enabled, overrides during WRITE burst
DDR4 automatically turns ODT termination off during READ bit

time regardless of ODT input or Rtt_Park and Rtt_Nom mode
register settings (DDR3 required ODT pin low)
DDR4 uses the WRITE command to turn-on Rtt_WR when

enabled via MRS (DDR3 required ODT pin high)
Rtt_WR value applied during WRITE bit time regardless of ODT
input or Rtt_Park and Rtt_Nom mode register settings
26
Rtt_Park Advantage
Two ODT termination values available without having to drive

ODT pin active {high}
Dynamic ODT (Rtt_Wr) WRITE command automatically turns on/off
Nominal ODT (Rtt_Park) Provides nominal termination when in standby
DDR4 allows two different nominal ODT termination values

when not being written to
Toggling ODT pin effectively switches the two values on-the-fly
27
ODT State Table
DRAM
RTT_Park RTT_Nom ODT Pin Termination State Notes
High RTT_Nom 1, 2
Enabled
Disabled Low Off (Hi-Z) 1, 2
1, 2
Disabled Dont Care3 Off (Hi-Z)
High RTT_Nom 1, 2
Enabled Enabled
Notes: Low RTT_Park 1, 2
Disabled Dont Care3 RTT_Park 1, 2
1. When a READ command is executed, DRAM termination state will be Hi-Z for defined period independent
of ODT pin and MR setting of RTT_PARK/RTT_NOM
2. If RTT_WR is enabled, RTT_WR will be activated by Write command for defined period time independent
of ODT pin and MR setting of RTT_PARK /RTT_NOM
3. If RTT_NOM is disabled, ODT input buffer will be turned off to save power
28
ODT Buffer Disable Mode (OBD)
Rtt_NOM termination is not provided during power down if

OBD is enabled via MR5 [5]
Dram controller must drive ODT continuously either low or
high when entering power down
Accounts for DRAM internal delay on CKE line to disable the ODT
buffer and block the sampled output
ODT may be floating after tCPDEDmin has been satisfied
In OBD mode, RTT_NOM termination becomes uncertain

as early as tANPD prior to CKE first registered low

ODT Buffer Disabled Mode (OBD)

VREF Supplies
VREFCA is similar to DDR3; supported by supply 50% of VDD

Should be referenced to same ground as command/address pins
VREFDQ is generated by the DRAM internally
Internal DQ reference is expected to provide a cleaner reference
Reduces number of pins required to be routed and on module
Provides the ability to individually set the VREFDQ level for each
DRAM
Compensates for board variations
31
VREFDQ Calibration
The internal VREFDQ reference must be calibrated prior to use
The memory controller should calibrate VREFDQ using a training

method
Supports DRAM DQ input timing and voltage margin optimizations
Calibration sequence is system dependent, but needs to adhere

to normal DRAM operations and timings, i.e. Writes, Reads, etc.
When used in conjunction with MRS Mask Mode (Per DRAM
Addressability), each DRAM can be adjusted individually to
account for any DRAM-to-DRAM channel variation
32
VREFDQ Calibration Settings
Internal VREFDQ reference has two ranges to select in MR6 [6]

Range 1 (MR6 [6] 0) - adjustable range is 60%-92% of VDDQ
Expected to be the operational range
Range 2 (MR6 [6] 1) - adjustable range is 45%-77% of VDDQ
VrefDQ adjustments are made via MRS commands

VrefDQ step size is 0.65% (0.15%) of VDDQ
11 0011 to
MR6 [5:0] 00 0000 00 0001 00 0010 00 0011 11 0001 11 0010 11 1111
Range 1 60.00% 60.65% 61.30% 61.95% 91.85% 92.50% Reserved
Reserved
Range 2 45.00% 45.65% 46.30% 46.95% 76.85% 77.50%
33
VREFDQ Step Timing
VrefDQ step timing has both a long or short time window

VREF_time_short is an MRS command to increment/decrement of
one VrefDQ step size (60ns)
VREF_time_long is an MRS command to increment/decrement
multiple step sizes, up to the full range of VrefDQ (150ns)
34
VREFDQ Tolerance
VREFDQ Set Tolerance
Variation in voltage from ideal setting
Accounts for accumulation error over multiple steps
2 ranges that are a function of the number of steps (n)
For n 4, Vref_set_tol = +/- 0.15% VDDQ.
For n > 4, Vref_set_tol = +/- 1.625% VDDQ
Measured from ideal line
Endpoints are min/max VrefDQ values for a specified range
Vref_new = Vref_old + n*Vref_step
n = number of steps; if decrement use "-"
35
VREFDQ Set Tolerance Example
36
VREFDQ Settings (VDDQ = 1.2V)
Vx Target Target
Ron ODT (Vin Low) VrefDQ (mV) VrefDQ (%VDDQ)
34 600 900 75%
34 60 434 817 68%
240 149 674 56%
See next page for full listing of options
37
VREFDQ Target with 34 Driver (VDDQ = 1.2V)
38
VREFDQ Settings (VDDQ = 1.2V)
Vx Target Target
Ron ODT (Vin Low) VrefDQ (mV) VrefDQ (%VDDQ)
34 600 900 75%
40 551 876 73%
48 498 849 71%
34
60 434 817 68%
80 358 779 65%
120 265 732 61%
240 149 674 56%
34 702 951 79%
40 655 927 77%
48 600 900 75%
48
60 533 867 72%
80 450 825 69%
120 343 771 64%
240 200 700 58%
39
Programmable WRITE Preamble
Write Read preamble modes of 1CK (default) and 2CK are allowed
Selected by MR4[12]
In 2CK Write Preamble Mode; CWL, tWTR, and tWR must be

programmed 1CK greater than required for 1CK mode
40
New Data Input Specification Rx Mask
The Data bus timing has changed from the classical setup/hold
relationship to data-eye mask
The memory controller must satisfy the data receiver mask
The Rx mask is centered around a calibrated value of VrefDQ
The DRAM input specification is only applicable around the

calibrated VREFDQ value
The theory is to define acceptable BER rate to take full advantage
May not be beneficial from a DRAM device perspective
To utilize the Rx Mask specifications Data training must

be used
41
Receiver Data Mask
VDDQ
90% VDDQ
Rx Mask
75% VDDQ
Random
Minimum AC
Rx Mask
VrefDQ Deterministic (VdIVW_total)
Input Swing
(VIHL_AC)
(prog.
Range 1
value)
Range 2
60% VDDQ
VDDQ/2
45% VDDQ
DQ Rx Deterministic
(tdIVW_dj)
Total DQ Rx Window
(tdIVW_total)
42 Micron Confidential | 2012 Micron Technology, Inc. | 42

3/21/2013
Receiver Data Mask 1600 through 2133
Rx Mask
Rx Mask
Deterministic (VdIVW_total)
Total DQ Rx Window
(tdIVW_total)
Rx Mask: Random and Deterministic have virtually same maskso far
43
Receiver Data Mask 1600 through 2133
Rx Mask
Rx Mask
Deterministic (VdIVW_total)
Total DQ Rx Window
(tdIVW_total)
Rx Mask: Random and Deterministic have virtually same maskso far
44
Rx Data Mask Defined at DRAM Balls
45
Rx Data Mask Defined at DRAM Latch
This defines Variation allowed within the DRAM package
46
Receiver Data Mask - Defined
47
Receiver Data Mask Slew Rate
Slow Slew Rate
Fast Slew Rate
48
Receiver Calibration VCENT_DQ(mean)
VCENT_DQ(mean) is determined by VREFDQ
calibration process
Calibrating VREFDQ determining optimum
VREFDQ setting for each DQ
VCENT_DQ(mean) is the level half way between the
lowest DQ setting and the highest DQ setting
VCENT_DQ(mean) is undefined if there is no VREFDQ
calibration
49
Rx Data Mask vs Data-Eye
The RX mask is essentially the keep out area
Signal transitioning within the keep out area, that is violate the mask
risks being bad data
The RX mask is essentially the opposite of a data-eye
Data-eye limits are minimums how small of signal allowed
The Mask limits are maximums how large of keep out area defined
Supports incorporation of jitter affects
50
Receiver Data with Mask after Training
Slew rate plays an important role between TdiVW and TdiPW
51
Receiver Data Mask Why Train
52
Receiver Data Mask No Training
53
Programmable READ Preamble
Read preamble modes of 1CK (default) and 2CK are allowed

Selected by MR4[11]
54
READ Preamble Training
MR4 [9] 1 to enable Read Preamble Training (RPT)
In RPT mode (must be in MPR Readout first), DRAM DQS pins are driven
with special READ Preamble
Data bus DQ pins are held quiet or driven HIGH
After tDSO (tMOD+9ns) from MRS entry, DQS_t and DQS_c signals are
driven LOW and HIGH, respectively, until a READ command is issued and
CAS latency (CL) has been satisfied
The DQS signals will then toggle as defined by the BL setting
The data pattern during this mode is TBD
MR4 [9] 0 to disable is issued to RPT mode
55
DDR4 DLL Off Mode
DLL Off Mode is a JEDEC DDR4 Standard

Optional feature for DDR3
High priority feature for DDR4
Function will be similar to DDR3

DLL disabled via mode register bit
DLL Off affects Clock to Data Strobe relationship (tDQSCK), but

not Data Strobe to Data relationship (tDQSQ, tQH)
The maximum clock frequency is bounded at 125MHz
The minimum clock frequency must satisfy the refresh interval
May have lower limit in range of 10MHz

DDR4 DLL Off Mode (cont)
DLL On timing specification is for 667Mhz and above
625MHz is minimum for boundary corner
1333MT/s data rate
DLL On/Off switching
Protocol is similar to DDR3
DLL control for fast/slow IDD2P exit does not have much value
Not supported
Disable DLL -> Enter Self Refresh -> Change Frequency ->
Exit Self Refresh -> Operation with DLL off
DLL On/Off switching
Similar DDR3 protocol as well
ODT timing is asynchronous when DLL is off
Self Refresh Abort
MR4 [9] allows self refresh mode to exit immediately as

oppose to waiting for internal refresh to complete
When the Self Refresh Mode Abort is disabled then the
controller uses tXS timings
If the bit is enabled then the DRAM aborts any ongoing
refresh and does not increment the refresh counter upon
Self Refresh Exit
The controller can issue a valid command not requiring a locked
DLL after a delay of tXS_abort
A savings in the range of 70ns to 190ns, depending on density

In Self Refresh mode (SRF), the refresh rate requirement is

based on temperature
LPASR provides both manual and automatic SRF control
Incorporating these DDR3 features

Self Refresh Temperature (SRT)
Increases SRF refresh rate to allow operation in extended
o o
temperature range (0 - 95 C) regardless of temperature
Auto Self Refresh (ASR)
Automatically increases SRF refresh rate when internal temperature
o
sensor measures above 85 C

LPASR has four options, three manual and one automatic

Selected via MR2 [7,6]
Manual mode
o o
Normal temperature (0 85 C), MR2 [7,6] 00 {1X rate}
o o
Extended temperature (0 95 C), MR2 [7,6] 01 {2X rate}
o o
Reduced temperature (0 45 C ), MR2 [7,6] 10 { X rate}
ASR mode
Automatically switches between modes based on internal
o o
temperature sensor measurement, (0 95 C ), MR2 [7,6] 11
Power savings by reducing refresh rate opportunistically

Micron Confidential Rs part

Temperature Controlled Refresh (TCR)
TCR varies internal refresh intervals based on temperature
o o
Normal temperature mode (0 85 C),
Refresh commands issued to DRAM with refresh period tREFI
7.8 sec of normal temperature range
o
System must guarantee temperature to be 85 C
o o
Extended temperature mode (0 95 C)
Refresh commands issued to DRAM with refresh period tREFI
3.9 sec of extended temperature range
The internal refresh period will be automatically adjusted for
correct operating temperature

TCR
TCR Mode Normal Extended
Temperature MR4[3] Temperature Range Temperature Range
0 Disabled na na
TCR Range
1 Enabled MR4 [2] = 0 MR4 [2] = 1
o o 0 Disabled na na 2x 2x
85 C<T95 C
1 Enabled na na 2x 2x
o o 0 Disabled 1x 1x 2x 2x
45 CT85 C
1 Enabled 1x 1x 2x 1x
o o 0 Disabled 1x 1x 2x 2
0 CT<45 C
1 Enabled 1x x 2x x
Refresh Period External Internal External Internal
Note: x Refresh rate 15.6s (must be 7.8s)

1x Refresh rate = 7.8s
2x Refresh rate = 3.9s
* Change to 1X allowed

TCR Extended Temperature Example
o o o o o
Controller 85 C to 95 C 45 C to 85 C Below 45 C
External
tREFI
3.9 sec Internal
tREFI Internal
7.8 sec tREFI
further increased
at lower
temperatures
Internal
tREFI
3.9 sec
Controller issues REFRESH External REFRESH Every other At low temperature, more
commands at Extended commands not external REFRESH commands can
Temperature rate ignored REFRESH ignored be ignored
Micron Confidential | 2012 Micron Technology, Inc. | 65

Fine Granularity Refresh
Enables efficient Refresh scheduling
Increase effective bandwidth
Refresh cycle time (tRFC) and Refresh interval (tREFI) are
programmable via MRS command
1x External Refresh commands issued at tREFI
2x External Refresh commands issued at tREFI/2
4x External Refresh commands issued at tREFI/4
tRFC will be reduced with these settings as well
Fixed mode of 1x, 2x, and 4x
Dynamic mode (on-the-fly)
When selected, status of BG0 determines refresh rate mode
either 1x/2x or 1x/4x
Refresh
Mode Parameter Tcase 2Gb 4Gb 8Gb 16Gb
o o
0 C<Tc85 C 7.8s 7.8s 7.8s tREFI
tREFI1
o o
1X 85 C<Tc95 C 3.9s 3.9s 3.9s tREFI/2
tRFC1 o o
0 C<Tc95 C 160ns 260ns 350ns TBD
o o
0 C<Tc85 C 3.90s 3.90s 3.90s tREFI/2
tREFI2
o o
2x 85 C<Tc95 C 1.95s 1.95s 1.95s tREFI/4
tRFC2 o o
o o
0 C<Tc85 C 1.950s 1.950s 1.950s tREFI/4
tREFI4
o o
4x 85 C<Tc95 C 0.975s 0.975s 0.975s tREFI/8
tRFC4 o o
Note: tREFIbase = 7.800s (TBD for 16Gb)

tREFI
base/2= 3.900s (TBD for 16Gb)
tREFI
tREFI

4Gb Fine Granularity Refresh

MPR

MPR
Four Page, each Page has four 8-bit registers

MPR Function
Multi-Purpose Register (MPR) selected via MR3
MR3[2] 0 = normal operation, 1 = MPR data flow enabled
MR3[1:0] 00=Page 0, 01=Page 1, 10=Page 2, 11=Page 3
MPR Operation by logical page

MPR Page 0 Training Patterns (Read/Write)
MPR Page 1 C/A Parity Error Frame (Read only)
MPR Page 2 MRS readout (Read only)
MPR Page 3 DRAM Manufacture Use only (do not use)
MPR data flow has three readout modes

(1) Serial, (2) Parallel, and (3) Staggered

MPR Operation
Multi-Purpose Register is a useful tool that can be used for
various ways
Training
DRAM controller receiver training
DRAM controller DQS to DQ phase training
Clock to address phase training
Debug
MPR provides a known response when rest is uncertain
RAS Support
Logging of C/A parity and CRC error information
Mode Register Confirmation
MPR Registers
MPR Bit Write Location [7:0]
Logical Page MPR Location 7 6 5 4 3 2 1 0
Description
MR3[1:0] [BA1:BA0] Read Burst Order (serial mode)
UI0 UI1 UI2 UI3 UI4 UI5 UI6 UI7
00 = MPR0 0 1 0 1 0 1 0 1
Training 01 = MPR1 0 0 1 1 0 0 1 1
00 = Page 0
Patterns 10 = MPR2 0 0 0 0 1 1 1 1
11 = MPR3 0 0 0 0 0 0 0 0
00 = MPR0 A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0]
A[15]/ A[14]/
01 = MPR1 A[13] A[12] A[11] A[10] A[9] A[8]
CAS_n WE_n
A[16]/
C/A Parity 10 = MPR2 PAR ACT_n BG[1] BG[0] BA[1] BA[0] A[17]
01 = Page 1 RAS_n
Error Log
C/A
CRC Error Parity
11 = MPR3 C/A Parity Latency C[2] C[1] C[0]
Status Error
Status
CRC
Rtt_WR Temp Sensor Rtt_WR
00 = MPR0 PPR RFU Write
Setting Status Setting
Enable
MRS VrefDQ Gear-
10 = Page 2
Readout 01 = MPR1 Training VrefDQ Training Value down
Range Enable
10 = MPR2 CAS Latency RFU CAS Write Latency
11 = MPR3 Rtt_Nom Setting Rtt_Park Setting Driver Impedance
00 = MPR0 RFU RFU RFU RFU RFU RFU RFU RFU
11 = Page 3 RFU

MPR Serial Mode Readout
Same Data Pattern is returned on all DQ lanes

x8 example MR0[7:0] = 0111 1111
Serial UI0 UI1 UI2 UI3 UI4 UI5 UI6 UI7

DQ0 0 1 1 1 1 1 1 1
DQ1 0 1 1 1 1 1 1 1
DQ2 0 1 1 1 1 1 1 1
DQ3 0 1 1 1 1 1 1 1
DQ4 0 1 1 1 1 1 1 1
DQ5 0 1 1 1 1 1 1 1
DQ6 0 1 1 1 1 1 1 1
DQ7 0 1 1 1 1 1 1 1

MPR Parallel Mode Readout
Data is returned on first UI and then repeated
X4 only returns the 1st 4 bits
X16 repeats for lower/upper byte
Only Data Pattern Location 0 can be used
X8 example: MR0[7:0] = 0111 1111

Parallel UI0 UI1 UI2 UI3 UI4 UI5 UI6 UI7
DQ0 0 0 0 0 0 0 0 0
DQ1 1 1 1 1 1 1 1 1
DQ2 1 1 1 1 1 1 1 1
DQ3 1 1 1 1 1 1 1 1
DQ4 1 1 1 1 1 1 1 1
DQ5 1 1 1 1 1 1 1 1
DQ6 1 1 1 1 1 1 1 1
DQ7 1 1 1 1 1 1 1 1

MPR Staggered Mode Readout
Data returned from different pattern locations on each DQ
For x8/x16 modes, DQ pattern is repeated

Reads can occur from different MPRx locations on
consecutive reads
x4 (Read MPR0 x4 (Read MPR1 x4 (Read MPR2 x4 (Read MPR3

Command) Command) Command) Command)
Stagger UI0-7 Stagger UI0-7 Stagger UI0-7 Stagger UI0-7
DQ0 MPR0 DQ0 MPR1 DQ0 MPR2 DQ0 MPR3

ACT_n Control
Activation Command Input

ACT_n qualifies the Activation command at CS_n
Determine RAS_n/A16, CAS_n/A15 and WE_n/A14 status
ACT_n Low = RAS_n/A16, CAS_n/A15 and WE_n/A14 are
addresses A16, A15, and A14; respectively and selected
bank is activated
ACT_n High = RAS_n/A16, CAS_n/A15 and WE_n/A14 are
command pins RAS_n, CAS_n and WE_n; respectively, for
Read, Write, and other commands defined in command
truth table

Command/Address Latency (CAL)
Delay between CS_n low and CMD / ADDR input

CMD / ADDR receivers can be disabled to save power
CS_n low enables CMD / ADDR receivers for input CAL
cycles later
CAL gives the DRAM time to enable receivers before
command is issued

IDD Savings Using CAL (Approximate)
Up to 10% for Activate-Precharge (IDD0)

Up to 7% for Activate-Read-Precharge (IDD1)
Up to 40% for Precharge Standby (IDD2N)

Percentages are based on initial analysis
Actual savings will be vary from system to system
10% to 15% module savings is likely

DBI (Data Bus Inversion)
Opportunistically invert data bits
Fewer bits driven low
Maximum of half of the bits driven low (including DBI_n pin)
Less Power - power only consumed by bits driven low
Fewer bits switching less noise better data eye
Read and write can be enabled separately
Controlled by MR5
DBI set per-byte
One DBI_n pin for x8
UDBI_n, LDBI_n pins for x16
X4 do not support DBI

DBI (Data Bus Inversion)

DM vs. DBI vs. TDQS
Data Mask (DM) Write DBI Read DBI TDQS (x8 only)
Enabled Disabled Enabled or Disabled Disabled
Enabled Enabled or Disabled Disabled
Disabled Enabled Disabled

Disabled
Disabled Disabled Enabled
Disabled Disabled Disabled
Notes:
1. DM , DBI, and TDQS share same pin
1. X4 has only DBI function, No DM function
2. X8 has DM, DBI, and TDQS function
3. X16 has DM and DBI function, per byte
82
PDA (Per DRAM Addressability)
A single DRAMs mode registers can be programmed

Same rank devices share ADDR/CMD, have separate DQs
DRAMs require Write Leveling to be done prior to entry

Only MRS commands allowed in PDA mode
When MRS Command Mask is enabled
MRS Command is qualified with DQ0
DQ0=1, MRS is ignored
DQ0=0, MRS commands are executed {on that device}

PDA Mode Entry

PDA Mode Exit

Gear-down Mode
DDR4 faster clock rates are challenging 1N Control bus

ie. rate
Speeds greater than DDR4-2400 likely to require gearing
down of Control bus
Gear-down mode allows gearing down Control bus from
1N to 2N
From rate to rate
With Gear-down mode enabled, DRAM internal clock is
reduced 2x
CMD/ADDR bus from 1N to 2N
Gear-down Operation
Normal Operation Gear-down mode Operation

Rate external clock Rate external clock
Control 1N Control 2N
(CS_n, CKE, and ODT) (CS_n, CKE, and ODT)
Address/Command 1N or 2N Address/Command 2N
CTL, CMD, and ADDR CTL, CMD, and ADDR
sampled every rising edge sampled every other rising
edge
CS_n sync pulse qualifies
correct rising clock edge

Gear-Down Operation
Normal Operation Gear-down mode Operation

Rate external clock Rate external clock

Gear-down Operation

Maximum Power Savings Mode (MPSM)
Lowest power mode

Data retention not maintained
Does not ensure data will be loss either
Only CKE, CS_n and RESET_n inputs are recognized
No response to any other input pins
Useful to disable unused powered devices for power savings
Enabled by MR4 [1] = 1

DQ0 usage similar to Per DRAM Addressability to
independently enable devices in a single rank
DQ0 must be low to be qualified

MPSM Entry
Enter mode with MRS after tMPED (28CKs)
After tMPED, DRAM responds to only CKE, CS_n, and
RESET_n; all other inputs are disabled
Clocks may be turned off after tCKMPE (38CKs)

MPSM Maintenance
MPSM may be maintained even with CKE toggling

To prevent exit, CS_n should be High at CKE low-to high edge
Appropriate setup and hold timings required

MPSM Exit
CS_n should be Low at the CKE low-to-high transition
Appropriate setup and hold timings required
CS_n = Low is captured by the rising edge of CKE
If CS_n is detected Low, the DRAM clears MRS bit and exits
the MPSM mode
DRAM must have valid clocks at beginning of tCKMPX

Cyclic Redundancy Check (CRC)
CRC provides real time error detection on the DDR4 data bus
Improves system reliability during Writes
DDR4 CRC polynomial is ATM-8 HEC
8-bit CRC Header Error Control: X8+X2+X+1
All Write Bursts are extended by 2 ticks
Both BC4 and BL8 require 10 DQS ticks
Additional ticks required for CRC checksum

Write CRC Error Checking
DRAM generates checksum per Write Burst per DQS lane
8 bits per Write Burst (CR0 through CR7)
CRC using 72-bits of data
Unallocated transfer bits are 1s
Compares against controller checksum
If two checksums do not match, DRAM flags an error

Write CRC Error

CRC Error Type #1
DDR4 CRC error type #1
Data Mask (DM) disabled
Data captured by DRAM Write is written to the DRAM memory
cells when error was flagged
CRC computation does not delay memory Write
Controller should retry errant write transactions
Controller is responsible for data coherency

CRC Error Type - #2
DDR4 CRC error type #2
Data Mask (DM) enabled
Data captured by DRAM Write is NOT written to DRAM
memory when error was flagged
CRC computation causes a memory Write delay
Controller should retry errant write transaction
DRAM memory integrity maintained

Write Data CRC Enablement
CRC via MR2[12]

0 = Write CRC disabled
1 = Write CRC enabled
Data Mask via MR5[10]

0 = Data Mask disabled
Write Command Latency = 0
WCL is not same as CWL
1 = Data Mask enabled (CRC and DM enabled)
Write Command Latency = MR3[10:9]

Write Data CRC Enablement
Data Mask via MR5[10]
MR5[10] = 0 DM disabled
Write Command Latency = 0

Use tWR, tWTR_S, tWTR_L
MR5[10] = 1 DM enabled (CRC and DM enabled)
*or 3.75ns
Write Command Latency = MR3[10:9] 4nCK to 6nCK*

tWR + WCL tWR_CRC_DM
tWTR_S + WCL tWTR_S_CRC_DM
tWTR_L + WCL tWTR_L_CRC_DM

Write CRC Data Bit Mapping x8
The system memory controller must send 1s on 9th bit
(transfer) when CRC is enabled;

DM/DBI_n must have 1s in both transfer-8 and transfer-
9 when enabled
A x8 DRAM has a 72 bit CRC tree
The upper 8-bits are used for DM/DBI inputs if DBI is
enabled

CRC Data Bit Mapping x8
BL=8
Transfer
X8
0 1 2 3 4 5 6 7 8 9
DQ0 d0 d1 d2 d3 d4 d5 d6 d7 CRC 0 1
DQ1 d8 d9 d10 d11 d12 d13 d14 d15 CRC 1 1
DQ2 d16 d17 d18 d19 d20 d21 d22 d23 CRC 2 1
DQ3 d24 d25 d26 d27 d28 d29 d30 d31 CRC 3 1
DQ4 d32 d33 d34 d35 d36 d37 d38 d39 CRC 4 1
DQ5 d40 d41 d42 d43 d44 d45 d46 d47 CRC 5 1
DQ6 d48 d49 d50 d51 d52 d53 d54 d55 CRC 6 1
DQ7 d56 d57 d58 d59 d60 d61 d62 d63 CRC 7 1
DM*/DBI_n d64 d65 d66 d67 d68 d69 d70 d71 1 1
No DM* or DBI_n 1 1 1 1 1 1 1 1 1 1

BC=4 (A2=0)
Transfer
X8
0 1 2 3 4 5 6 7 8 9
DQ0 d0 d1 d2 d3 1 1 1 1 CRC 0 1
DQ1 d8 d9 d10 d11 1 1 1 1 CRC 1 1
DQ2 d16 d17 d18 d19 1 1 1 1 CRC 2 1
DQ3 d24 d25 d26 d27 1 1 1 1 CRC 3 1
DQ4 d32 d33 d34 d35 1 1 1 1 CRC 4 1
DQ5 d40 d41 d42 d43 1 1 1 1 CRC 5 1
DQ6 d48 d49 d50 d51 1 1 1 1 CRC 6 1
DQ7 d56 d57 d58 d59 1 1 1 1 CRC 7 1
DM*/DBI_n d64 d65 d66 d67 1 1 1 1 1 1
No DM* or DBI_n 1 1 1 1 1 1 1 1 1 1

BC=4 (A2=1)
Transfer
X8
0 1 2 3 4 5 6 7 8 9
DQ0 d4 d5 d6 d7 1 1 1 1 CRC 0 1
DQ1 d12 d13 d14 d15 1 1 1 1 CRC 1 1
DQ2 d20 d21 d22 d23 1 1 1 1 CRC 2 1
DQ3 d28 d29 d30 d31 1 1 1 1 CRC 3 1
DQ4 d36 d37 d38 d39 1 1 1 1 CRC 4 1
DQ5 d44 d45 d46 d47 1 1 1 1 CRC 5 1
DQ6 d52 d53 d54 d55 1 1 1 1 CRC 6 1
DQ7 d60 d61 d62 d63 1 1 1 1 CRC 7 1
DM*/DBI_n d68 d69 d70 d71 1 1 1 1 1 1
No DM* or DBI_n 1 1 1 1 1 1 1 1 1 1

A x4 device has a 32-bit CRC tree

The input for the upper 40-bits D[71:32] are 1s
X4 does not have DM or DBI_n
Transfer
X4
0 1 2 3 4 5 6 7 8 9
DQ0 d0 d1 d2 d3 d4 d5 d6 d7 CRC 0 CRC 4

Transfer
X16
0 1 2 3 4 5 6 7 8 9
DQ0 d0 d1 d2 d3 d4 d5 d6 d7 CRC 0 1
DQ1 d8 d9 d10 d11 d12 d13 d14 d15 CRC 1 1
DQ2 d16 d17 d18 d19 d20 d21 d22 d23 CRC 2 1
DQ3 d24 d25 d26 d27 d28 d29 d30 d31 CRC 3 1
DQ4 d32 d33 d34 d35 d36 d37 d38 d39 CRC 4 1
DQ5 d40 d41 d42 d43 d44 d45 d46 d47 CRC 5 1
DQ6 d48 d49 d50 d51 d52 d53 d54 d55 CRC 6 1
DQ7 d56 d57 d58 d59 d60 d61 d62 d63 CRC 7 1
LDM/DBI_n d64 d65 d66 d67 d68 d69 d70 d71 1 1
DQ8 d72 d73 d74 d75 d76 d77 d78 d79 CRC 8 1
DQ9 d80 d81 d82 d83 d84 d85 d86 d87 CRC 9 1
DQ10 d88 d89 d90 d91 d92 d93 d94 d95 CRC 10 1
DQ11 d96 d97 d98 d99 d100 d101 d102 d103 CRC 11 1
DQ12 d104 d105 d106 d107 d108 d109 d110 d111 CRC 12 1
DQ13 d112 d113 d114 d115 d116 d117 d118 d119 CRC13 1
DQ14 d120 d121 d122 d123 d124 d125 d126 d127 CRC 14 1
DQ15 d128 d129 d130 d131 d132 d133 d134 d135 CRC 15 1
UDM/DBI_n d136 d137 d138 d139 d140 d141 d142 d143 1 1

CRC Logic Equations
Combinatorial logic block implementation
272 two-input XOR gates ^ in 6-gate deep trees
CRC 0 = d69 ^ d68 ^ d67 ^ d66 ^ d64 ^ d63 ^ d60 ^ d56 ^ d54 ^ d53 ^ d52^ d50 ^ d49 ^ d48 ^ d45 ^ d43 ^ d40 ^ d39 ^ d35 ^ d34 ^
d31 ^d30 ^ d28 ^ d23 ^ d21 ^ d19 ^ d18 ^ d16 ^ d14 ^ d12 ^ d8 ^ d7 ^ d6 ^ d0
CRC 1= d70 ^ d66 ^ d65 ^ d63 ^ d61 ^ d60 ^ d57 ^ d56 ^ d55 ^ d52 ^ d51 ^ d48 ^ d46 ^ d45 ^ d44 ^ d43 ^ d41 ^ d39 ^ d36 ^ d34 ^
d32 ^ d30 ^ d29 ^ d28 ^ d24 ^ d23 ^ d22 ^ d21 ^ d20 ^ d18 ^ d17 ^ d16 ^ d15 ^ d14 ^ d13 ^ d12 ^ d9 ^ d6 ^ d1 ^ d0
d33 ^ d29 ^ d28 ^ d25 ^ d24 ^ d22 ^ d17 ^ d15 ^ d13 ^ d12 ^ d10 ^ d8 ^ d6 ^ d2 ^ d1 ^ d0
d30 ^ d29 ^ d26 ^ d25 ^ d23 ^ d18 ^ d16 ^ d14 ^ d13 ^ d11 ^ d9 ^ d7 ^ d3 ^ d2 ^ d1
CRC 4= d71 ^ d70 ^ d65 ^ d64 ^ d63 ^ d62 ^ d60 ^d59 ^ d56 ^ d52 ^ d50 ^ d49 ^ d48 ^ d46 ^d45 ^ d44 ^ d41 ^ d39 ^ d36 ^ d35 ^
d31 ^ d30 ^ d27 ^ d26 ^ d24 ^ d19 ^ d17 ^ d15 ^ d14 ^ d12 ^ d10 ^ d8 ^ d4 ^ d3 ^ d2
d31 ^ d28 ^ d27 ^ d25 ^ d20 ^ d18 ^ d16 ^ d15 ^ d13 ^ d11 ^ d9 ^ d5 ^ d4 ^ d3
d29 ^ d28 ^ d26 ^ d21 ^ d19 ^ d17 ^ d16 ^ d14 ^ d12 ^ d10 ^ d6 ^ d5 ^ d4
d30 ^ d29 ^ d27 ^ d22 ^ d20 ^ d18 ^ d17 ^ d15 ^ d13 ^ d11 ^ d7 ^ d6 ^ d5

CRC Logic Example: CRC bit5

Write CRC Timing
WRITE - CRC Disabled WRITE - CRC/DM* Enabled
Transfer: 01 2 3 4 5 6 7 8 9 Transfer: 01 2 3 4 5 6 7 8 9
If DM* disabled: tWR_CRC_DM = tWR; tWTR_S_CRC_DM = tWTR_S; tWTR_L_CRC_DM = tWTR_L

CRC Fault Coverage
DRAM error flag uses ALERT_n signal

short low pulse
C/A Parity error uses a long pulse
CRC Error Detection Coverage:
Error Type Detection Capability
Random Single-Bit Errors 100%
Random Double-Bit Errors 100%
Random Odd Count Errors 100%
Random Multi-bit UI error detection

100%
(excluding DBI bits)

CRC Error Reporting
When the DRAM detects a CRC error, in addition to
driving ALERT_n LOW
Sets CRC Error flag MR5[3] to a 1
CRC Error Clear where 0 = clear, 1 = error
Resetting to zero will clear PAGE-1, MPR3[7] to zero
Sets CRC Error status PAGE-1, MPR3[7] to a 1

CRC Error status where 0 = clear, 1 = error
Identifies which device had CRC error
MR5[3] must be reset to a 0 by the controller before

CRC Error status will clear

CRC Error Reporting
If Error occurs and CRC and C/A Parity are enabled
at the same time

Controller can check PAGE-1, MPR3[7] to determine if
ALERT_n low is an CRC error
Both CRC and C/A Parity signal an error via ALERT_n LOW
Error identification also by ALERT_n low time
Low for 6 to 10 clocks CRC error
low for 48 to 144+ clocks C/A Parity error

CRC Error Reporting
DDR4-
1600/1866/2133/2400
Parameter Symbol min max Unit
CRC error to ALERT_n latency tCRC_ALERT 3 13 ns
CRC ALERT_n pulse width CRC ALERT_PW 6 10 nCK

DDR4 Writes - CRC Flow

C/A Parity Feature
C/A Parity provides parity checking of command and

address buses
ACT_n, RAS_n, CAS_n, WE_n and the address bus
Control signals CKE, ODT, CS_n are not checked
Parity Latency (PL) is added to command timing covered by

parity check
MR5[2:0] enables the mode when a delay is selected
PL ranges from 4nCK to 6nCK, depending on clock rate
Only DES are allowed between valid commands

C/A Parity Feature
C/A Parity uses even parity

The parity bit is chosen so that the total number of 1s in the transmitted
signal, including the parity bit is even
Alert_n is used to flag error to Memory Controller
Register Settings required to enable C/A Parity

MR5[2:0] non-zero value required to enable C/A Parity Mode
MR5[4] must be set to zero to clear C/A Parity Error status bit
Must be re-set to zero when clearing a fail
MR5[9] determines Standard or Persistent mode

C/A Parity Entry/Exit
MRS commands must use modified tMRD and tMOD timing when
entering and exiting C/A Parity Mode
tMRD_PAR before issuing another MRS command

tMRD_PAR = tMOD+PL
tMOD_PAR before issuing any another command

tMOD_PAR = tMOD+PL

C/A Parity Mode Register Settings
Register Operating Mode Purpose Access
Disable 000
Enable 001 PL = 4 (1600 2133)
Enable 010 PL = 5 (2400)
MR5[2:0] C/A Parity, with Latency Written
Enable 011 PL = 6 (RFU)
Enable 100 PL = 8 (RFU)
Reserved 101, 110, 111
C/A Parity control: Clear (0) Error (1)

MR5[4] C/A Parity Error Status Written
Status read from PAGE-1 MPR3 [6]
Written
MR5[9] C/A Parity Persistent Mode Disable (0) Enable (1)

C/A Parity MPR Readouts
C/A Parity error information can be readout from DRAM
MPR Page 1 contains information of interest
If multiple errors occur prior to Parity Error Status is reset, data in MPR
Page 1 must be considered no longer accurate
Register Operating Mode Purpose Access

MPR3 [6] C/A Parity Error Status C/A Parity flag: Clear (0) Error (1) Read
MPR3 [5:3] C/A Parity Latency = [5:3], Programmed PL value Read
MPR3 [2:0] D/C for monolithic = [2:0] Reserved for stacked die Read
MPR Page 1
C/A Parity Error Log: ACT_n, PAR,

MPR2 [7:0] C/A Parity bits resulting in error Read
BG[1:0], BA[1:0], A17,RAS_n/A16
C/A Parity Error Log: CAS_n/A15,
MPR1 [7:0] C/A Parity bits resulting in error Read
WE_n/A14, A[13:8]
MPR0 [7:0] C/A Parity Error Log: A[7:0] C/A Parity bits resulting in error Read

C/A Parity Operation
There two basic modes of operation
Normal or non-persistent mode
Persistent mode
Special C/A Parity Error cases
During Self Refresh Mode
During Power Down Mode

C/A Parity - Normal Operation
2. Command execution is unknown; the corresponding DRAM internal state change may
or may not occur
Rest of the DRAM, memory or registers, does not get corrupted
The DRAM controller should consider both cases and make sure that the command sequence
meets the specifications
1. DRAM is emptying queues
Precharge all and parity checking off until Parity Error Status bit cleared
3. Parity checking is off until Parity Error Status bit cleared
Set MR5[4] to 0 to clear {by user} when next C/A needs to be parity checked
2 2 2 2 2 3
2 1
Larger of 2nCK or 3ns PL+6ns

48 to 96 nCKs1600
PL = 4 nCK for 1600, 1866, 2133
PL = 5 nCK for 2400 72 to 144 nCKs2400

Persistent C/A Parity
2. Command execution is unknown; the corresponding DRAM internal state change may or
may not occur
Rest of the DRAM, memory or registers, does not get corrupted
The DRAM controller should consider both cases and make sure that the command sequence
meets the specifications
1. DRAM is emptying queues
Precharge all and parity check re-enable finished by tPAR_ALERT_PW
3. Parity checking remains on, even with Parity Error Status bit not cleared
Set MR5[4] to 0 to clear {by user} when next error needs to be logged
2 2 2 3
2 43 to 64 nCKs(max)
Larger of 2nCK or 3ns PL+6ns 1

PL = 4 nCK for 1600, 1866, 2133
PL = 5 nCK for 2400 48 to 96 nCKs1600
72 to 144 nCKs2400

C/A Parity - Power Down
2. Error could be Precharge or Activate
1. DES commands only allowed
5. DES only allowed; CKE may go high prior to Td2 as long as DES are issued
4. Command execution is unknown; the corresponding DRAM internal state change may or
may not occur
The DRAM controller should consider both cases
3. Normal operation with parity latency (CA Parity Persistent Error Mode disabled)
Parity checking is off until Parity Error Status bit cleared
2 1 1 5 5 4 3

C/A Parity - Self Refresh Attempt
1. DES only allowed
5. Command execution is unknown; the corresponding DRAM internal state change may
or may not occur
2. Self Refresh command error
DRAM masks the intended SRE command and enters Precharge Power Down
4. Controller cannot disable clock until it has been able to confirm there was not a C/A
Parity error with SRE command
6. DES command only; CKE may go high prior to Td2 as long as DES are issued
Parity checking is off until Parity Error Status bit cleared
1,5 2 1 6 6 5 3
PL+6ns 4 1
PL = 4 nCK for 1600, 1866, 2133

PL = 5 nCK for 2400

C/A Parity - Self Refresh Exit
1. Case where Self Refresh Abort = Disable : MR4 [A9 = 0]
8. This figure shows the case from which the error occurred after tXS_FAST
An error may also occur after tXS_ABORT and tXS.
2. Input commands are bounded by tXSDLL, tXS, tXS_ABORT and tXS_FAST timing
3. Command execution is unknown; the corresponding DRAM internal state change may or may not
occur
Parity checking off until Parity Error Status bit cleared
5. Only MRS (limited to those in Self-Refresh Operation), ZQCS, or ZQCL allowed
6. Valid commands not requiring a locked DLL
7. Valid commands requiring a locked DLL
2,4,5 2,4,6 2,4,7
1 2 2 2 2 2,3 2,3

C/A Parity Parity Error Readout
C/A parity fail log is located in MPR Page 1, MPR2
Once a C/A parity error occurs, the fail information can be obtained via an
MPR Read from Page1, MPR2
If C/A Parity Persistent mode is enabled and a subsequent Parity error is
encountered prior to the Parity Error Status bit being cleared; information in
Error Log becomes no longer accurate
MPR Bit Write Location [7:0]
Logical Page MPR Location 7 6 5 4 3 2 1 0
Description
MR3[1:0] [BA1:BA0] Read Burst Order (serial mode)
UI0 UI1 UI2 UI3 UI4 UI5 UI6 UI7
00 = Page 0 Patterns C/A Parity will use one of four patterns refer to MPR Readout
00 = MPR0 A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0]
A[15]/ A[14]/
01 = MPR1 A[13] A[12] A[11] A[10] A[9] A[8]
CAS_n WE_n
C/A Parity A[16]/
01 = Page 1 10 = MPR2 PAR ACT_n BG[1] BG[0] BA[1] BA[0] A[17]
Error Log RAS_n
C/A Parity
CRC Error
11 = MPR3 Error C/A Parity Latency Not used with monolithic parts
Status
Status
10 = Page 2 MRS Readout NA for C/A Parity Function

11 = Page 3 RFU NA for C/A Parity Function

C/A Parity Flow

Connectivity Test Mode
(Formally Boundary Scan)
Testing the electrical continuity of pin interconnections
Mode allows test patterns to be entered in parallel into the

test inputs and the test results read out in parallel from the
test outputs of the DRAM at the same time
Assertion of TEN pin causes DRAM to enter mode
Upon exiting, reset initialization sequence is required

Connectivity Test Pins
Pin Type
Normal Operation Pin Names Switching Level
{CT Mode}
Test Enable TEN CMOS (20% / 80% VDD)
Chip Select CS_n VrefCA1 200mV
BA0-1, BG0-1, A0-A9, A10/AP, A11, A12/BC_n, A13,

WE_n/A14, CAS_n/A15, RAS_n/A16, CKE, ACT_n, VrefCA1 200mV
ODT, CLK_t, CLK_c, Parity
Test Inputs
DML_n, DBIL_n, DMU_n/DBIU_n, DM/DBI VrefDQ2 300mV
Alert_n3 CMOS (20% / 80% VDD)
RESET_n CMOS (80% VDD)
Test Outputs DQ0-DQ15, DQSU_t, DQSU_c, DQSL_t, DQSL_c VTT4 +/- 100mV
Recommend 1. VrefCA should be at VDD/2

2. VrefDQ should be at VDDQ/2 JEDEC issue
3. TBD, recommend these levels
4. VTT should be set to VDDQ/2

Connectivity Test Mode Equations
Originally x16 only
X4, and x8 defined for 8Gb and larger; as optional feature
MTx represents an internal signal used to generate the signal to drive the
output signals
x16 and x8 signals are internal signal indicating the density of the device
MT0 = XOR (A1, A6, PAR)

MT1 = XOR (A8, ALERT_n, A9)
MT2 = XOR (A2, A5, A13)
MT3 = XOR (A0 A7, A11)
MT4 = XOR (CK_c, ODT, CAS_n/A15)
MT5 = XOR (CKE, RAS_n,/A16, A10/AP)
MT6 = XOR (ACT_n, A4, BA1)
MT7 = x16: XOR (DMU_n / DBIU_n , DML_n / DBIL_n, CK_t)
= x8: XOR (BG1, DML_n / DBIL_n, CK_t))
= x4: XOR (BG1, CK_t)
MT8 = XOR (WE_n / A14, A12 / BC, BA0)
MT9 = XOR (BG0, A3, RESET_n)

Connectivity Test Mode Equations
X16 Output Eq. X8 Output Eq. X4 Output Eq.
DQ0 = MT0 DQ0 = MT0 DQ0 = XOR(MT0, MT1)
DQ1 = !DQ0 MT1 DQ1 = MT1 DQ1 = XOR(MT2, MT3)
DQ2 = MT1 MT2 DQ2 = MT2 DQ2 = XOR(MT4, MT5
DQ3 = !DQ2 MT3 DQ3 = MT3 DQ3 = XOR(MT6, MT7)
DQ4 = MT2 MT4 DQ4 = MT4 DQS_t = MT8
DQ5 = !DQ4 MT5 DQ5 = MT5 DQS_c = MT9
DQ6 = MT3 MT6 DQ6 = MT6
DQ7 = !DQ6 MT7 DQ7 = MT7
DQ8 = MT4 !DQ0 DQS_t = MT8
DQ9 = !DQ8 !DQ1 DQS_c = MT9
DQ10 = MT5 !DQ2
DQ11 = ! DQ10 !DQ3
DQ12 = MT6 !DQ4
DQ13 = MT7 !DQ5
DQ14 = MT8 !DQ6 DQ1 = !DQ0 MT1
DQ15 = !DQ14 !DQ7 !DQ0 = JESD79-4
DQSL_t = MT9 MT8 MT1 = JESD79-4A
DQSL_c = !DQ12 MT9
DQSU_t = !DQSL_t ! = Invert
DQSU_c = !DQ13 !DQSL_c

Connectivity Test Mode Example
DQ0 = MT0
= XOR (A1, A6, PAR)
DQ8 = !DQ0
A1,A6,PAR DQ0 DQ8

000 0 1
001 1 0
010 1 0
011 0 1
100 1 0
101 0 1
110 0 1
111 1 0

Connectivity Test Mode Timing
First power-up then initiate CT Mode after completing the

reset procedure

Connectivity Test Mode Timing
tCT_Enable (min) = 200ns, tCT_Valid = 200ns

DDR4 Functional Matrix by width
Functions x4 x8 x16
Write Leveling
Temperature Controlled Refresh
Low Power Auto Self Refresh
Multi Purpose Register
Data Mask no
Data Bus Inversion no
TDQS na na
ZQ calibration
DQ Vref Training
Per DRAM Addressability
Mode Register Readout
CAL
WRITE CRC
CA Parity
Control Gear Down Mode
Programmable Preamble
Maximum Power Down Mode no
Connectivity Test Mode optional optional
Additive Latency no
DDR4 Functional Matrix speed
Functions -1600 -1866 -2133 -2400 -2666 -3200
Write Leveling
Temperature Controlled Refresh
Low Power Auto Self Refresh
Multi Purpose Register
Data Mask
Data Bus Inversion
TDQS
ZQ calibration
DQ Vref Training
Per DRAM Addressability
Mode Register Readout
CAL
WRITE CRC
CA Parity
Control Gear-Down Mode no no no no
Programmable Preamble (2tCK) no no no
Maximum Power Down Mode
Connectivity Test Mode
Additive Latency
Typical DRAM Training Sequence
1. DRAM power-up
2. Connectivity test
3. Gear-Down mode training
1. DDR4-2666 or higher speeds
4. DRAM initialization Set mode registers
5. CLK to ADDR/CMD training
6. DRAM controller DQS receiver training
7. Write leveling minimize CK to DQS skew induced by fly-by
8. Write DQS to DQ phase training
9. Read DQS to DQ phase training
1. Read strobe training using Read Preamble Training mode
2. Read DQ training using MPR patterns
10. DRAM VREFDQ calibration
1. Per-DRAM mode optional for enhanced training
137
Memory Power
DDR4 Power Analysis
Volume manufacturing IDD data not available yet
Once available, data should be better than DDR3L
From high level, DDR4 clearly out distances DDR3L for

power savings
1.35V to 1.2V 11% reduction due to just voltage reduction
If comparing to DDR3, then 20% initial reduction
POD interface and DBI will significantly reduce I/O power
Individual Vpp supply
Lower Self Refresh power with new LPASR mode
DDR4 can be expected to require 25% to 40% less power

than DDR3L at the same speed
DQ Bus
Pseudo Open Drain

Very little switching or biasing current when a 1
DBI minimizes zero transitions

DBI
Using power Calculator
READ I/O about 39% reduction with DBI
Write I/O about 35% reduction with DBI
CMMD/ADDR Bus
Similar to DDR3
If daisy chain
One VTTr to VTT per pin
Requires switching current
Approx. 600mV/ (34ohm+37ohm)
If Tree
One pull-up, one pull-down
Requires switching and biasing current
Approx. 600mV/ (34ohm+60ohm)
If layout allows, series R can reduction current by about 50%
CAL would save about 10% input power

VDD / VDDq
Pretty straight forward, similar to DDR3

IDD listed in specs
IDDQ generally not listed, per JEDEC spec

IDDQ is negligible on Micron DRAMs
except IDD4R, but then that is load dependant
VPP
New to DDR4
IPP listed in some specs
Cover worst cases
IPP has three basic values

Standby approx. 1.7mA
Active approx. 2.7mA
Refresh approx. 14mA
DDR4 POWER CALCULATOR
DDR3L vs DDR4 Power (with VPP)
DDR3L vs DDR4 IDD
specs
Both 30nm 4Gb x8
1866
DDR4 power includes
both IDD and IPP current
DDR3U vs DDR4 Power (with VPP)
DDR3L vs DDR4 IDD
specs
Both 30nm 4Gb x8
1866
DDR4 includes both IDD
and IPP current
DDR3L VDD set at 1.2V
for apple to apple
compare
ie. direct power savings
from VPP
4Gb IDD Typicals
with offsets to base IDD test
IDD @ 1866 IDD @ 2133
2na = 2n with CL-1

2nd = 2n with DLL disabled
2ng = 2n with Gear-down
2nl = 2n with Cal enabled
2npar = 2n with CA Parity
3na = 3n with CL-1
4ra = 4r with CL-1

4rb = 4r with DBI (no VDDQ affects)
4wa = 4w with CL-1

4wb = 4w with DBI (no VDDQ affects)
4wc = 4w with Write CRC
4wpar = 4w with CA Parity
5f2 = 5B at 2X ref
5f4 = 5B at 4X ref
q4rb = q4r with DBI
p5f2 = p5B at 2X ref

p5f4 = p5B at 4X ref
DDR4 IDD Power Analysis
used by permission from Intel
DDR4 Modules
Overview
UDIMM, RDIMM, LRDIMM Physical
288 pin connector at 0.85 mm pitch (currently balloted)
Module Height 31.25 +/- 0.15 mm
DDR3 is 30.0mm
VLP and LP share the same latching
HP requested send latching notch similar to DDR3 VLP (added)
Bottom edge of board outline will have a step and ramp feature to
reduce insertion force relative to DDR3
Module thickness to be 1.40 mm +/- 0.1 mm
DDR3 is 1.27mm
VPP supplied directly from connector
No regulator
Initial JEDEC designs not likely to be based on large DRAM packages
DDR4 MO-309 for DIMM
Single latching notch

VLP notch in the same position
Chamfer at the alignment notch
Red line is where the VLP module stops (18.75 mm)
31.25 mm tall
Step and ramp feature; 0.5 mm step
Reduces insertion force
MO will likely be updated for 288 pins assuming ballot passes
SO-DIMM Physical
PCB thickness is 1.2+/- 0.1mm

DDR3 is 1.0mm
Connector pin pitch is 0.5mm
Module width 1mm wider than DDR3 to 68.6mm
Module height the same as DDR3 - 30.0mm
SA0 on connector
SA1 and SA2 not on connector today
Can support 2 high 3DS stack (C0)
VPP supplied directly from connector
No regulator
Connector Signal Features
DQ signals have ground on each side

1:1 signal-to-power ratio
Reduce crosstalk
Should also reduce SSO
Module ground will be closer to motherboard ground
Address still 2:1 ratio with power (Same as DDR3)
C0, C1, C2 support 3DS stacking as die selects
Allows support of up to an 8 high DRAM stack
SO-DIMM
Has ECC defined from the start
Only C0 present for 3DS stacking
Only SA0 (SPD) present
JEDEC and Micron DDR4 Modules
Status 3/18/2013
DDR4 RDIMMs JEDEC Status
Reference
Raw Module JEDEC
Design Ranks DRAM Status Comments
Card Height Balloting
Owner
A Samsung 31.25 2 4 Revision 0.3 Jun 2013 Vertical DRAM
B Elpida 31.25 2 4 Revision 0.1 Jun 2013 Flower
C SK Hynix 31.25 1 4 Revision 0.3 Jun 2013
D Micron 31.25 1 8 Revision 0.8 Jun 2013
Smart
E 31.25 2 8 Revision 0.1 Jun 2013
Modular
F Micron 18.75 1 4 Revision 0.3 Jun 2013
G Elpida 18.75 1 8 Revision 0.5 Jun 2013
H Micon 18.75 2 8 Revision 0.1 Sep 2013
J Micron 18.75 2 4 Revision 0.3 Jun 2013 Conventional DDP

March 18, 2013
DDR4 RDIMMs Micron Modules
RDIMM
Raw Micron JEDEC Module DRAM Bus

Ranks Status In Test Comments
Card Project Owner Height Width Width
B 1506 31.25 2 4 72 Built Jan '13 Tested 3DS
C 1393 SK Hynix 31.25 1 4 72 Built Feb '13 Tested
D 1361 Micron 31.25 1 8 72 Built Dec '12 Tested JEDEC
E 1398 Smart 31.25 2 8 72 Waiting
F 1437 Micron 18.75 1 4 72 In Design May '13 JEDEC
G 1407 Elpida 18.75 1 8 72 Waiting JEDEC
H 1403 Micron 18.75 2 8 72 Waiting July '13
J 1433 Micron 18.75 2 4 72 In Design Apr '13 Uses conventional DDP
All designs will be revised to have a 288 pin connector.

Existing cards useable in 288 pin sockets.

March 18, 2013
DDR4 SO-DIMM JEDEC Status
DDR4 SO-DIMMs
Raw Card
Raw Module Bus JEDEC
(JEDEC Ranks DRAM Status JEDEC Balloting Comments
Card Height Width Revision
Owner)
Ready for
A Micron 30 1 8 64 0.80 Jun, 2013
ballot
B Samsung 30 2 8 64 No file Jun, 2013
C SK Hynix 30 1 16 64 No file Jun, 2013
Ready for
D Micron 30 1 8 72 0.80 Jun, 2013
ballot
E Samsung 30 2 8 72 No file Jun, 2013 DRAMs placed vertical
F Elpida 30 2 8 72 No file Jun, 2013 DRAMs Flower
G 30 2 8 72 No file Jun, 2013 DRAMs placed vertical, 3DS
H 30 2 8 72 No file Jun, 2013 DRAMs Flower, 3DS

March 18, 2013
DDR4 SO-DIMM Micron Modules
Raw Micron JEDEC DRAM Bus
Ranks Status In test Comments
Card Project Owner Width Width
A 1424 Micron 1 8 64 100% Apr '13 Non-JEDEC version available - 1319
B 1392 Samsung 2 8 64 No file No Sch
C 1507 SK Hynix 1 16 64 No file No Sch Non-JEDEC version available - 1320 - No PCBs ordered
D 1425 Micron 1 8 72 100% Dec '12 Rev B in April
E 1488 Samsung 2 8 72 No file No Sch Non-JEDEC version available - 1395
F Elpida 2 8 72 No file No Sch
For items with No Sch, a schedule will be defined once a

JEDEC reference design is available.
There are test cards available for each configuration.
Timing should be similar based on placement being
projected to be similar to the reference designs.

March 18, 2013
DDR4 UDIMM JEDEC Status
DDR4 UDIMMs
Reference
Raw Module DRAM Bus JEDEC
Design Ranks Status JEDEC Balloting Comments
Card Height Width Width Revision
Owner
A SK Hynix 31.25 1 8 64 50% Rev 0.5 Jun 2013
B Micron 31.25 2 8 64 100% Rev 0.3 Jun 2013
C 31.25 1 16 64 No file
D SK Hynix 31.25 1 8 72 100% Rev 0.5 Jun 2013
E Samsung 31.25 2 8 72 50% Rev 0.5 Jun 2013
JEDEC balloting to be counted in June is an based on ballot

authorization.
Design must be updated for 288 pin connector.

March 18, 2013
DDR4 UDIMM Micron Modules
Raw Micron JEDEC Module DRAM Bus
Ranks Status In Test Comments
Card Project Owner Height Width Width
A 1508 SK Hynix 31.25 1 8 64 50% May '13 Non-JEDEC version available - 1321 - no PCB ordered
B 1447 Micron 31.25 2 8 64 100% Dec 2012 Working on next revision
C 31.25 1 8 64 Non-JEDEC version available - 1323
D 1389 SK Hynix 31.25 1 8 72 10% May '13 Pre-release version availale
E 1487 Samsung 31.25 2 8 72 100% May '13 Pre-release version available
Based on limit placement options non-JEDEC cards should

have timing close to the related JEDEC cards.
R/C D will require a pin to comply with final JEDEC
specification.

March 18, 2013
DDR4 LRDIMM JEDEC Status
DDR4 LRDIMMs
Reference
Raw Module DRAM Bus JEDEC
Design Ranks Status Comments
Card Height Width Width Balloting
Owner
A Samsung 31.25 2, 4, 8, 16 4 72 No file Sep '13 DRAMs Vertical, 3DS
B Micron 31.25 2, 4, 8, 16 4 72 No file 'Sep '13 DRAMs Flower, 3DS
C 18.75 1, 2, 4, 8 4 72 No file Not expected to be done.
D SK Hynix 31.25 4 4 72 No file 'Sep '13 DRAMs Vertical, DDP
E Micron 31.25 4 4 72 No file Sep '13 DRAMs Flower, DDP
3DS modules may have 1, 2, 4 or 8 die in a stack.

VLP (C) not expected to exist.
September schedule based on design decisions not finalized.

March 18, 2013
DDR4 LRDIMM Micron Modules
Reference
Raw Micron DRAM Bus
Design Ranks Status In Test Comments
Card Project Width Width
Owner
A 1400 Samsung 2 4 72 No File No Sch Vertical DRAM
Flower DRAM
B 1408 Micron 2 4 72 30% 'Jul '13
Test Card available in December - 1517
C 1 4 72 No file No Sch VLP. Not expected to be done.
D SK Hynix 4 4 72 No File No Sch Vertical DRAM, DDP
E 1465 Micron 4 4 72 30% Jul '13 Flower DRAM, DDP
Decision on series resistor required before completion of

module designs.

March 18, 2013
Development
LRDIMM: Currently deciding if a series resistor is required
for the host side data bus. This request is based on
improving margins with 3 DIMMs on a channel. If a series
resistor is required this will have a cost impact to the
LRDIMM designs for the larger DRAM packages.
Do not expect any other significant issues. Some boards
will likely have minor updates as problems are found. No
projection at this time as to what may come up.

March 18, 2013
DDR4 IPP At Boot
2012 Micron Technology, Inc. All rights reserved. Products are warranted only to meet Microns production data sheet specifications. Information, products, and/or specifications
are subject to change without notice. All information is provided on an AS IS basis without warranties of any kind. Dates are estimates only. Drawings are not to scale. Micron and
the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners.
New Reliability Features
New Reliability Features in TG Discussion
JEDEC DDR4 TG discussing these features

May be come part of the specand may not
Premature to know if either will be part of the spec

Let alone what the final mode actually does
PPR Mode (Post Package Repair)

DRAM able to perform row repair after it leaves DRAM
manufacturer
TRR Mode (Target Row Refresh)
DRAM able to perform refresh to a specific row(s)
TRR Mode (Target Row Refresh)
Microns plan of
implementation
PPR Mode
PPR Post Package Repair Mode
DRAM able to perform row repair after it leaves DRAM

manufacturer
After DRAMs are soldered in system and if a device with a

bad row is detected, PPR mode can be used to repair bad
row
172
PPR Mode
JEDEC Ballot up for vote in March 2013 committee meeting
Committee: JC42.3B
Committee Item Number: 1795.81
Optional on 4Gb parts, required on 8Gb and above
Came in late, missed first die designs
Micron parts will support JEDEC PPR Mode per JEDEC ballot
All DDR4 parts except initial 4Gb device
173
PPR Mode
Microns plan of implementation
Repair Support
PPR can repair 1Row per Bank Group
PPR support is identified via a MPR read
0 = PPR not supported

DDR4 MPR Page 2 MPR0 A7
1 = PPR supported
174
PPR Mode
The controller provides the failing row address in a sequence to

the DRAM to perform a row repair
PPR mode allows for Refresh operations
A REF command will refresh all banks except the one in
repair mode.
PPR Mode enabled via MRS command
DDR4 Value Description

0 Disable PPR Mode
MR4 [13]
1 Enable PPR Mode
175
DDR4 PPR Mode
176

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DDR3 to DDR4 Transition

March 20, 2013 Micron Confidential | 2012 Micron Technology, Inc. | 1

Features/Options DDR3 DDR4 Comments

Voltage (core, /IO) 1.5V 1.2V Reduces memory power demand

Vref Inputs 2 DQs and CMD/ADDR 1 CMD/ADDR VREFDQ now internal

Better enable large capacity

Internal Banks 8 16 More banks

Bank Groups (BG) 0 4 Faster burst accesses

Page Size x4/x8/16 1KB/1KB/2KB 512B/1KB/2KB X4 use less activation current

tCK 667MHz to 1.6GHz

Features/Options DDR3 DDR4 Comments

800, 1066, 1333 1600, 1866, 2133

Prefetch 8-bits 8-bits

Burst length BC4, BL8 BC4, BL8 Same functionality

(1) Fixed, via MRS (1) Fixed, via MRS

Access (CL,tRCD,tRP) 14ns+/- 14ns+/- Similar access timing

Additive Latency 0, CL-1, CL-2 0, CL-1, CL-2 Same programmability

READ Latency AL + CL AL + CL DDR4 has more values, same concept

Features/Options DDR3 DDR4 Comments

DQ Driver (STD) 34 34 Optimized for DIMM applications

DQ Driver (ALT) 40 48 Optimized for PtP applications

DQ Bus Termination ODT ODT Optimized for higher data rates

DQ Bus SSTL15 POD12 Mitigate I/O noise and power

120, 60, 240, 120, 80, 60,

Nominal, Dynamic, Additional control mode,

ODT signaling ODT signaling Ease of ODT control, allows non-

Features/Options DDR3 DDR4 Comments

MultiPurpose Register Four registers 1 Four registers 3 Provides additional specialty

RESET# Dedicated input Dedicated input Disable outputs, Resets DRAM

VPP Supply none 2.5V Power efficiency to array

VREFDQ Calibration none supported Optimize internal VREFDQ

Bank Group none four Faster burst accesses

Low-power Auto Self

Temperature Controlled Lower refresh current without

Fine Granularity Refresh none supported Efficient Refresh scheduling

Features/Options DDR3 DDR4 Comments

CMD/ADDR Latency (CAL) none supported Efficient command scheduling

Per DRAM Addressability none supported Optimize calibration

C/A Parity none supported Error detection of CMD/ADDR bus

Gear-Down Mode none supported Support CMD/ADDR @ faster tCK

Connectivity Test Mode Improved part down

Maximum Power Savings none supported Very low powered-on state

Programmable READ and

Features/Options DDR3 DDR4 Comments

Pin-out/Package 78-ball; x4, x8 78-ball; x4, x8

240pin UDIMM, RDIMM 288pin UDIMM, RDIMM; Improve Power:Ground

240pin 1.0mm 284pin 0.85mm Improve Power:Ground

MRx Feature / Option MRx Feature / Option

0[11:9] WR / RTP 2[12] WRITE data bus CRC

0[8] DLL Reset 2[11:9] Dynamic ODT (RTT_Wr)

0[6:4,2] CAS latency (CL) 2[5:3] CAS Write Latency (CWL)

0[3] Burst Type 3[12:11] MultiPurpose Register (MPR)

0[1:0] Burst Length 3[10:9] Write CMD when DM

1[11] Termination DQ strobe (TDQS) 3[5] Temp Sensor Readout

1[10:8] Nominal ODT (RTT_Nom) 3[4] Per DRAM Addressability

1[7] Write Leveling Mode 3[3] Gear-Down Mode

1[4:3] Additive Latency 3[2] MultiPurpose Register Access

MRx Feature / Option MRx Feature / Option

4[11] Read Preamble 5[8:6] Park ODT (RTT_Park)

4[9] Self Refresh Abort 5[4] C/A Parity error status

4[8:6] CMD ADDR Latency (CAL) 5[3] CRC Error Status

4[4] Internal VREFDQ monitor 5[2:0] C/A Parity Latency Mode