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1(a). What you would use in RTL a 'boolean' type or a 'std_logic' type and why.
1(b). What are/may be the implications of using an 'integer' type in RTL.
2). What you would use a RAM or a regfile discuss:
RAM: Low Power, Low Area
REGFILE: better timing.
3). A timing path fails: what are your options?
Ans: a). Look for parallelism in RTL.
b). Look for small RAMs which might be synthesized
c). Look for better placement
d). Look for Pipelining opportunity
e). Look for moving logic before the Reg
f). Look for replicating the drivers to reduce load if the delay is
caused by loading
g). '< or >' are better than -, when comparators are used in RTL
h). Look for if..elsif..elseif..elsif
i). Use One Hot instead of Binary coded State Registers
4). Any example you can provide in which verilog might be a prob
5). What are VHDL structures, give an example to exploit them
6). What is grey coding, any example where they are used
7). Discuss Async interfaces
8). Metastability
9). Synopsys unwanted latch
10). Verilog blocking vs non-blocking
11). VHDL variables: example where you have to use them
12). What is pipelining and how it may improve the performance
13). What are multicycle paths.
14). What are false paths
15). What are Async counters, what are advantages of using these
over sync counters. and what are the disadvantages
16). q_in : IN std_logic
variable q0 : std_logic
variable q1 : std_logic
variable q2 : std_logic
q_out : OUT std_logic;
if(rising_edge(clk)) then
q0 := q_in;
q1 := q0;
q2 := q1;
q_out <= q2;
endif;
18). process(a_sig,b_sig)
begin
if(a_sig = '1' and b_sig = '0') then
sig_out <= '1';
else
sig_out <= '0';
end if;
end process
process(c_sig,d_sig)
begin
if(c_sig = '1' and d_sig = '0') then
sig_out <= '1';
else
sig_out <= '0';
end if;
end process
process(a_sig,bsig)
variable c_sig : std_logic_vector(n downto 0);
begin
c_sig := a_sig-bsig;
a_is_smaller <= c_sig(c_sig'high);
end process;
process(a_sig,bsig)
variable c_sig : std_logic_vector(n downto 0);
begin
if(asig < bsig) then
a_is_smaller <= '1';
else
a_is_smaller <= '0';
end if;
end process;
27). Simulation Problem. Register going 'X' even when RTL has reset
pin defining the state of register at power up reset. And such
a reset has been applied in simulation.
28). Generally dc_shell tries to optimise the path with worst violation.
Is there any thing that you can do to make it work on more paths
parallely
Ans :Use group_path may be with 'critical_range' on that group
30). What is the difference between transport delays and inertial delays in VHDL
31). What determines the max frequency a digital design may work on.
Why thold(hold time) is not included in the calculation for the above.
35). Draw DC curve of inverter and Re-Draw it if pmos and nmos are
equal
36). What is Latch-up
39). Design a state machine which divides the input frequency of a clock by 3.
Given that the phase change in the output due to propogation delay in of the
flip flop is acceptable up to a delay offered by a single flip flop only.
40). Why does a pass gate requires two transistors(1 N and 1 P type) Can we use a
single transistor N or P type in a pass gate? If not why? and if yes then in what conditions?
41). Why CMOS why not N-MOS or P-MOS logic, when we know that the number
of gates required in CMOS are grater than in n-mos or p-mos logic.
42). How much is the max fan out of a typical CMOS gate. Or alternatively,
discuss the limiting factors.
43). What are dynamic logic gates? What are their advantages over conventional logic gates
44). Design a digital circuit to delay the negative edge of the input signal by 2 clock cycles
45). What is the relation between binary encoding and grey(or gray) encoding.
46). Write a vhdl function to implement a length independent grey code counter.
alternatively, discuss the logic to do that.
47). How you will constraint a combinational logic path through your design
in dc_shell.
49). How you will make a Nand Gate function like an inverter.
51). From a CMOS logic gate IC, the 40xx series, Take an inverter IC,
power it up, and leave the input of the inverter floating. Comment upon the
ouput of this inverter.
Similarly take a TTL logic gate IC, the 74xx series. Take an inverter IC,
power it up, and leave the input of the inverter floating. Comment upon the
output of this inverter.
52). What are LFSRs, example usage?
These interview questions test the knowledge of x86 Intel architecture and 8086 microprocessor
specifically.
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The following questions are used for screening the candidates during the first interview. The
questions apply mostly to fresh college grads pursuing an engineering career at Intel.
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1. What is pipelining?
2. What are the five stages in a DLX pipeline?
3. For a pipeline with ‘n’ stages, what’s the ideal throughput? What prevents us from achieving this
ideal throughput?
4. What are the different hazards? How do you avoid them?
5. Instead of just 5-8 pipe stages why not have, say, a pipeline with 50 pipe stages?
6. What are Branch Prediction and Branch Target Buffers?
7. How do you handle precise exceptions or interrupts?
8. What is a cache?
9. What’s the difference between Write-Through and Write-Back Caches? Explain advantages and
disadvantages of each.
10. Cache Size is 64KB, Block size is 32B and the cache is Two-Way Set Associative. For a 32-bit
physical address, give the division between Block Offset, Index and Tag.
11. What is Virtual Memory?
12. What is Cache Coherency?
13. What is MESI?
14. What is a Snooping cache?
15. What are the components in a Microprocessor?
16. What is ACBF(Hex) divided by 16?
17. Convert 65(Hex) to Binary
18. Convert a number to its two’s compliment and back
19. The CPU is busy but you want to stop and do some other task. How do you do it?