FPGA IMPLEMENTATION OF OFDM MODEM

LAKSHMIDEVI T R
Asst. Prof, Department of ECE, DBIT, Mysore Road, Bangalore-560074

BABITHA S
Asso. Prof, Department of ECE, DBIT, Mysore Road, Bangalore-560074

ABSTRACT: The objective of this paper is to design and implement a base band OFDM
transmitter and receiver on FPGA hardware. This paper concentrates on developing Fast Fourier
Transform (FFT) and Inverse Fast Fourier Transform (IFFT). All modules are designed using
VHDL programming language and implement using Xilinx FPGA board Orthogonal Frequency
Division Multiplexing (OFDM) is a multi-carrier modulation technique which divides the
available spectrum into many carriers. OFDM uses the spectrum efficiently compared to FDMA
by spacing the channels much closer together and making all carriers orthogonal to one another to
prevent interference between the closely spaced carriers. The main advantage of OFDM is their
robustness to channel fading in wireless environment.

KEYWORDS: OFDM, QAM, FFT, IFFT, FPGA.

INTRODUCTION

Implementation On FPGA
With the rapid growth of digital communication in recent years, the need for high-speed data
transmission has been increased. The mobile telecommunications industry faces the problem of
providing the technology that be able to support a variety of services ranging from voice
communication with a bit rate of a few kbps to wireless multimedia in which bit rate up to 2 Mbps.
Many systems have been proposed and OFDM system has gained much attention for different
reasons.Although OFDM was first developed in the 1960s, only in recent years, it has been
recognized as an outstanding method for high-speed cellular data communication where its
implementation relies on very high-speed digital signal processing. This method has only recently
become available with reasonable prices versus performance of hardware implementation.

Since OFDM is carried out in the digital domain, there are several methods to implement the
system. One of the methods to implement the system is using ASIC (Application Specific
Integrated Circuit). ASICs are the fastest, smallest, and lowest power way to implement OFDM
into hardware. The main problem using this method is inflexibility of design process involved and
the longer time to market period for the designed chip.

Another method that can be used to implement OFDM is general purpose Microprocessor or
Micro Controller. Power PC 7400 and DSP Processor is an example of microprocessor that is
capable to implement fast vector operations. This processor is highly programmable and flexible in
term of changing the OFDM design into the system. The disadvantages of using this hardware are,
it needs memory and other peripheral chips to support the operation. Beside that, it uses the most
power usage and memory space, and would be the slowest in term of time to produce the output
compared to other hardware.
.
Statement Of The Problem
The previous work involved and is focused on the design of the core processing block using 8
point Fast Fourier Transform (FFT) for receiver and 8 point Inverse Fast Fourier Transform (IFFT)
for transmitter part. The implementation of this design into FPGA hardware is to no avail for
several reasons encountered during the integration process from software into FPGA hardware.

The work was done up to simulation level FFT and IFFT processing module. Some of the problem
encountered is that the design of FFT and IFFT was not fitting on FPGA hardware. The design
used a large number of gates and causes this problem to arise. Logic gates are greatly consumed if
the number of multiplier and divider are increase. One method to overcome this problem is by
decreasing the number of multiplier and divider in the VHDL design.

Beside that, the design does not include control signal which cause difficulties in controlling the
data processing in FFT or IFFT module. The control signal is use to select the process executed for
each computation process during VHDL design. As a result, the design is not applicable for
hardware implementation in the FPGA development board. New design is required to overcome
this problem. Since the design is not possible to use, this paper will concentrate on designing the
FFT and IFFT module which can be implement in the dedicated FPGA board. To ensure that the
program can be implemented, the number of gates used in the design must be small or at least less
than the hardware can support. Otherwise the design module is not able to implement into the
dedicated board.

Introduction To OFDM
OFDM is a multi-carrier system where data bits are encoded to multiple sub-carriers. Unlike single
carrier systems, all the frequencies are sent simultaneously in time. OFDM offers several
advantages over single carrier system like better multipath effect immunity, simpler channel
equalization and relaxed timing acquisition constraints. But it is more susceptible to local
frequency offset and radio front-end non-linearity. The frequencies used in OFDM system are
orthogonal. Neighboring frequencies with overlapping spectrum can therefore be used. This
property is shown in the figure1 where f1, f2 and f3 orthogonal. This results in efficient usage of
BW. The OFDM is therefore able to provide higher data rate for the same BW.

Figure 1: OFDM signal representation

OFDM TRANSMITTER AND RECEIVER

Simplified Transmitter and Receiver

Figure 2.1 and 2.2 above show the simplified block diagram of OFDM transmitter and receiver. It
can be seen that the block is divided into several parts with each block function differently and this

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is to ensure that the system works effectively. Since the main component is processing block, so,
the work is started from this part. All block set function is implemented in the FPGA development
board. To avoid confusion with the binary case , each transmitted level here is called a symbol
rather than a bit.

Cyclic prefix is a module, which is used to concatenate partial end of information bit and put at the
beginning of the information frame.

Figure 2.1: Simplified Transmitter Block Diagram

Figure 2. 2 : Simplified Receiver Block Diagram

MODULATION AND DEMODULATION OF QAM MAPPING TECHNICQUE

In case of higher constellation the QAM have less BER than other technicques.In [1] the
architecture of the modulator can be separate in several functional blocks, witch can be studied
separately:

-The block of serial to parallel: the binary sequence (serial data) is converted to N-bit (M=2N).-
The generation block of M-levels (modulator i(t)/q(t)) produces the two ways In-phase i(t) and
Quadrature phase q(t) The phasors of the M-level constellation may be decomposed into N/2
independent N-level AM signals that are transmitted on quadrature components of the same
carrier.Each AM carrier is transmitted with an amplitude of either -(N-1)d,, -3d, -d, d,
3d,.., (N-1)d, where d is the coordinate spacing shown in Fig2.4. The N-level AM
components are binary encoded using N/2 Gray coded bits for each level. For example, the4-level
AM components of 16-QAM are binary encoded using two Gray coded bits for each level; Gray
codes 01, 00, 10 and 11, are assigned to levels3d, d, -d and 3d, respectively. The demodulation of
QAM is the reverse process of modulation .

Figure 2.3: Transmitter M-QAM

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 Figure 2.4: M-ary QAM constellation, M=16

8 POINT FFT AND IFFT

The implementation of an 8 point FFT and IFFT processor involved few modules All this module
are combined together to produce an 8 point FFT and IFFT processor. Figure2.5 and.2.6 shows an
8 point FFT and IFFT block diagram and their interconnections. Figure 3.1 shows the complete
functional block diagram where the inputs are passed into the design synchronously at every
positive edge triggered. Then, the path module shows the arithmetic computation for each
respective output.

In the FFT and IFFT algorithm (generally), the even and odd outputs are computed
Separately in two main groups . The odd output blocks computation is more complex compared to
the even group computation. The odd output computations are represented by Path 1, Path 3, Path
5 and Path 7. The even output computations are 31 Path 0, Path2, Path 4 and Path 6. In the even
outputs, the twiddle factor at the output equations has been simplified. [2]

In the sub-modules, few digital circuitries are implemented. The most important components are
adder, subtractor and multiplier. The maximum summation value which can be supported ranges
from -32768 to +32767.

Figure 2.5 :IFFT block diagram

One of the most important properties of OFDM transmission is its robustness against multi path
delay. This is especially important if the signals sub-carriers are to retain their orthogonality
through the transmission process. Addition of a guard period between transmitted symbols can be
used to accomplish this. The guard Figure 2.4: Block diagram for OFDM communications period
allows time for multipath signals from the previous symbol to dissipate before information from
the current symbol is recorded.

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 Figure 2.6: FFT block diagram

CYCLIC PREFIX INSERTION AND REMOVAL

Figure 2.7 Implementation of cyclic prefix

The most effective guard period is a cyclic prefix, which is appended at the front of every
OFDM symbol. The cyclic prefix is a copy of the last part of the OFDM symbol, and is of equal or
greater length than the maximum delay spread of the channel as shown in fig. 2.7. Although the
insertion of the cyclic prefix imposes a penalty on bandwidth efficiency, it is often the best
compromise between performance and efficiency in the presence of inter-symbol interference.

RESULT AND DISCUSSION

For proposed architecture the experimental results as shown in fig3.1 and fig3.2 . The below
results shows that QAM with OFDM give rise to less BER, ISI, Bandwidth utilization.

Figure3.1 QAM without OFDM O/P Figure 3.2 QAM with OFDM O/P

CONCLUSION

The paper will be focused on the design of the 16-QAM modulation and demodulation block along
with processing block which is 8 point IFFT and FFT function. All design need to be verified to

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ensure that no error in VHDL programming before being simulated. The second scope is to
implement the design into FPGA hardware development board. This process is implemented if all
designs are correctly verified and simulated using particular software. Implementation includes
hardware programming on FPGA or downloading hardware design into FPGA and software
programming. Creating test vector program also include in this paper. Test vector is a program
developed and is intended as the input interface for user as well as to control data processing
performed by the hardware. Creating this software required in understanding the operation of the
FFT and IFFT computation process. The last works is to verify the result of the output for each
module which has been developed. Test vector program is used to deliver the computation result if
input value is provided by the user. These computation values should be verified and tested to
ensure the correctness of the developed module. Appropriate software is used to compare the
computation performed by the FPGA hardware with the software.

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