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PIII INTERNAL BLOCK DIAGRAM

IVth Quad. IIIrd Quad.

CLOCK
PFAU
PIC BBL
EBL FAU

PMH MOB

IEU MIU
DTLB
DCU
RAT SIMD
ALLOC

IInd
TAP Ist Quad. RS
Quad.

BAC ROB

B
T ID
B MS
IFU

Pentium III implements large number of complex functions. Intel’s processor designer
approaches the design task the way all engineers do, by partitioning the overall
complex function into smaller well-defined units.

The function of each quadrant is as follows: -

1. The bottom left quadrant implements the front end of the instruction
processing
Pipeline:
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a. IFU - Instruction fetch unit. Instructions fetch logic and 16KB four
way set associative level 1 instruction cache resides in this block.
Instruction data from the IFU is then forwarded to the ID.

b. BTB - Branch Target Buffer. This block is responsible for dynamic

branch prediction based on the history of past branch decisions path.

c. BAC - Branch Address Calculator. Static branch prediction is

performed here to handle the BTB miss.

d. TAP - Testability Access Port. Various testability and debug

mechanisms resides within this block

2. The bottom-right quadrant implements the instruction decode, scheduling

dispatch and refinement functions:

a. ID – Instruction decoder. This unit is capable of decoding up to three

instructions per cycle.

b. MS – Microinstruction Sequencer. This holds the micro code ROM

and sequencer for more complex instruction flows. The micro code
update functionality is also located here.

c. RS – Reservation Station. Micro instructions and source data are held

here for scheduling and dispatch to the execution ports.

d. ROB – Re-Order Buffer. This supports a 40 entry physical register file

that holds temporary write-back results that can complete out of order.

3. The top-right quadrant implements the execution data path:

a. SIMD - SIMD integer execution unit for MMX instruction.

b. MIU – Memory interface unit. This is responsible for data conversion

and formatting for floating-point data types.

c. IEU - Integer Execution Unit

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d. FAU – Floating Point Arithmetic Unit. This performs floating point

related calculations for existing scalar instructions along with support
for some of the SIMD-FP instructions.

e. PFAU – Packed Floating Point Arithmetic Unit. This contains

arithmetic execution data-path functionality for SIMD-FP specific
instruction.

4. The top-left quadrant contains functions including the bus interface, data
cache access and allocation.

a. ALLOC – Allocator. The RS performs allocation of various resources

such as ROB, MOB and RS entries here prior to micro-instruction
dispatch.

b. RAT – Register Alias Table. During resource allocation, the renaming

of logical to physical registers is performed here.

c. MOB – Memory Order Buffer. Acts as a separate schedule and

dispatch engine for data loads and stores. Also temporarily holds the
state of outstanding loads and stores for dispatch until completion.

d. DTLB – Data Translation Look-Aside Buffer. Performs the translation

from linear address to physical address required to support of virtual
memory.

e. PMH – Page Miss Handler. Hardware engine for performing a page

table walk – in the event of a DTLB miss.

f. DCU – Data Cache Unit. Contains the non-blocking 17KB four – way
set associative level 1 data cache along with associated fill and write-
back buffering.

g. BBL – Back Side Bus Logic. Logic for interface to the backside bus
for access to the external unified level 2-processor cache.

h. EBL – External Bus Logic. Logic for interface to the backside bus for
access to the external unified level 2-processor cache.

i. PIC – Programmable Interrupt Controller. Local Interrupt controller

logic for multiprocessor interrupts distribution and boot-up
communication.