MOSFET scaling

Can we just keep miniaturizing conventional FETs?

No - new physical effects kick in at small length scales.

Not all these effects are bad, but certainly make
design more complicated.

Some can be mitigated by particular scaling
schemes.
What kind of variations on CMOS are proposed, and why?
How far can these variations take us - when does it
become essential to change to a new architecture based on
new operating principles?

What happens in smaller transistors?

If we simply shrink all length scales, a number of physical effects
can become relevant that are unimportant in larger MOSFETs:
Channel shortening
Punch-through
Tunneling / thermionic leakage
Threshold voltage variation with drain bias
Finite width effects
Velocity saturation
Field-dependent mobility
Avalanche breakdown
Oxide failure

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Where is all the action?

We derived transistor
characteristics (e.g. square law)
by looking at the charge in this
box area under the gate.

Gate Charge Approximation (GCA): assumes that charge

distribution in that box is dominated by effects from gate field.
That is, Fy >> Fx for electric fields in that region.

Anything that affects charge distribution in or very near

this box will produce changes away from our simple
model predictions.

Channel shortening
First example happens when VD approaches (VG-VT). In long
channel devices, we get pinchoff and saturation of ID:

L-L L
In really short devices, L can be a significant fraction of L!
What happens then?
Remember, Fx is large over L - thats where most of the source-
drain voltage is dropped.
While inversion layer is gone, drift is enhanced by high electric
field there: result is a boost in ID as VD is increased beyond Vdsat.

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Channel shortening
Semiempirical formula based on square law picture:
WC x VD2
ID = (VG VT )VD (1 + VD )
L 2
WC x (VG VT ) 2 VD
I Dsat (1 + VD )
L 2

No true saturation.
Can even have problems at
gate voltages that should be
below threshold!

Punch-through
In sufficiently small devices, the depletion
regions from the source and drain can
actually merge.
This is particularly awkward since the
drain depletion region is strongly altered
by VD.
Gate only influences small volume near
surface.
Current can flow through depletion zone
- space-charge-limited ~ VD2.
How to mitigate? Higher doping
concentration in bulk wafer leads to
shorter depletion widths, though there is an
upper limit to reasonable doping.

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Tunneling / thermionic leakage
Consider an n-MOSFET below threshold, but with a finite
source-drain bias.
Plot the energy of the conduction band as a function of
position along the channel.

decreasing
device length,
increasing bias.

Drain-Induced Barrier Lowering (DIBL).

Thermionic leakage / tunneling

Both processes can be relevant.

Tunneling matters more for smaller devices;
thermionic emission matters more for higher
temperatures.
Biggest problem is that these can lead to
substantial off-currents and power dissipation!

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 Threshold voltage variation

Consider electrostatic
potential contours as devices
are shortened.
For fixed VG, shorter
channel means more
dominated by VD, just from
geometry.
Result: Apparent VT can be
quite different in short
devices!
Trends:
Shorter channel = lower threshold voltage
Higher VD = lower threshold voltage.
Thinner oxide = higher threshold voltage.

Finite width effects

Top view of MOSFET:

source

gate

drain

W
Some kind of isolation, to prevent gate from affecting
more semiconductor than desired.
As overall devices shrink, isolation becomes
increasingly important to avoid parasitic effects.

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Finite width effects
source

gate

drain

Best forms of isolation:

oxide oxide

Field-dependent mobility
We mentioned this briefly before.

To keep up with source-drain field, we must scale

oxide to be thinner.
Thinner oxide = higher gate field.
Higher gate field = enhanced surface scattering at
channel-oxide interface = lower effective mobility.
eff ~ FG1/ 3

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 Velocity saturation

Electric fields can get quite large in short channel devices.

Does our simple mobility picture still work?
No: if velocity of carriers becomes large enough, they can lose
energy by inelastic processes (e.g. shedding optical phonons).
If L is long compared to the inelastic scattering length, one sees
velocity saturation:
I Dsat WC x (VG VT )vsat

Results:
This is a significant reduction in current.
Saturation current now depends linearly on VG-VT rather
than almost quadratically.

Velocity saturation

Some example numbers:

Si, 300 K vsat ~ 107 cm/s
when Fx > ~ 3 x 104 V/cm for electrons,
when Fx > ~ 105 V/cm for holes.

real data model with vsat model with no vsat

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 Velocity overshoot
What happens if channel is shorter than inelastic scattering
length?
Velocity overshoot: can get channel velocities higher than
what would be expected for simple equilibrium transport
Result can be odd features in transistor characteristics:

Nonmonotonic
behavior of ID due
to overshoot.
Higher fields =
more inelastic
scattering =
shorter inelastic
length.

Other potential problems:

Avalanche breakdown:
At high enough energies (regions with big electric fields,
like drain pinch-off area) carriers can collisionally produce
electron-hole pairs.
These pairs may not be bound, and can then also
accelerate, leading to more pairs.
Result is runaway ID not controlled by VG.
Parasitic transistor action:
Can get odd unintentional bipolar transistor behavior
between source, drain, and bulk:

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 Oxide failure
Unsurprisingly, very thin gate oxides tend to be fragile.
Short-term failure: static electricity can easily cause local
electric fields high enough to kill oxides.
Mechanism: high energy electrons accelerated by large fields
can actually break bonds - can effectively introduce enough
defect states in gap to permit sufficient conduction to get
runaway failure.

Oxide failure
Long term failure caused by accumulated damage:

Certain probability per

electron of damage (~ Fy).
As damage accumulates,
leakage currents go up,
increasing damage rate.

field-emission from defect

sites.

initial leakage (tunneling

+thermionic emission)

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 Oxide failure

Still not well-understood microscopically.

Can see weird things - soft breakdown, healing
On one hand, would think this will be less of a problem
when one switches to thicker layers of alternative (high-K)
dielectrics materials.
However: thermal SiO2 has among the best breakdown field
properties of any oxide. Typical fields for failure are several
109 V/m. In contrast, alumina can be as much as 5 times
worse, and only has a dielectric constant of ~ 9.
Also, band offset concerns: SiO2 works well because its
bands dont line up with doped Si. More exotic high-K
materials (SrTiO3) may not be so fortunate.

Contact resistances

The source and drain ohmic contacts (metal to

polysilicon to highly doped wafer material) are ohmic,
but have some specific contact resistivity.
Current requirements: Rcont < 4.7 x 10-7 -cm2.
As cross-sections of contacts decrease, the actual resistance
goes up like 1/contact area unless materials are modified.
Remember, our FET formulae are all derived assuming
negligible series resistance from sources other than the
channel.

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General scaling approaches
Two major scaling approaches:
Constant field scaling - reduces both sizes and
voltages to maintain constant relative electric fields.

Pro: avoids nasty high field issues, plus
competition between gate and drain.

Con: cant keep reducing voltages forever.
Constant voltage scaling - keeps voltages fixed as
dimensions are scaled.

Pro: maintains voltages at reasonable levels.

Con: run into all the high field effects
described above.

General scaling approaches

Consider reducing all FET linear dimensions by a factor .
Heres the table of how things must scale:

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Empirical scaling formulae
Assuming effective channel length l in microns,
empirical data on good transistors predicts:
t ox max(21 l 0.77 ,14 l 0.55 ) oxide thickness (nm)
VDD 5 l 0.75 supply voltage (V)
N B 4 1016 l 1.6 dopant density in bulk (cm-3)

Dopant density must go up to avoid punch-through.

From these empirical formula, can derive other quantities:
U g C xV 2 / 2 = 2.2 10 4 l 2.75 minimal switching energy (can run
into discreteness of levels.)

Vth 0.55l 2.3 threshold decrease due to DIBL.

Summary:

A number of device physics issues crop up if one attempts to

aggressively scale standard Si MOSFETs.
Typical resulting problems:
gate no longer effectively controls source-drain current
substantial currents even when device should be off
carrier behavior differs from that in larger devices
There are ways of scaling that minimize these effects, but theres no
avoiding the eventual impending demise of scaling this device
configuration.

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Next time:

There are a number of competing candidate CMOS solutions to try

and get around both the device engineering problems discussed
today, and some of the fabrication and diagnostic issues mentioned
last time.
Typical approaches:
Change the gate geometry substantially to mitigate field
problems.
Change overall device shape to improve fabrication process
and yield.
Materials changes.

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