Lecture 070 - Digital Phase Lock Loops (DPLL) Digital Phase Locked Loops (DPLL)

Lecture 070 DPLLs - I (5/15/03) Page 070-1
LECTURE 070 DIGITAL PHASE LOCK LOOPS (DPLL)

(Reference [2])
DIGITAL PHASE LOCKED LOOPS (DPLL)
Outline
Building Blocks of the DPLL
Dynamic Performance of the DPLL
Noise Performance of the DPLL
DPLL Design Procedure
DPLL System Simulation
ECE 6440 - Frequency Synthesizers P.E. Allen - 2003
BUILDING BLOCKS OF THE DPLL

Block Diagram of the DPLL
v1, 1
Digital vd Analog vf v2, 2
v2', 2' Phase Lowpass VCO
Detector Filter
N Counter
(Optional)
Fig. 2.2-01
The only digital block is the phase detector and the remaining blocks are similar to the
LPLL
The divide by N counter is used in frequency synthesizer applications.
2
2 = 1 = N 2 = N 1

DIGITAL PHASE DETECTORS

Introduction
Key assumption in digital phase detectors: v1(t) and v2(t) are square waves. This may
require amplification and limiting.
vin(t) vout vin(t)
VOH VOH
VIH VIL
t vin t
VIL VIH
VOL VOL
Fig. 2.2-02
Types of digital phase detectors:

1.) EXOR gate
2.) The edge-triggered JK flip-flop
3.) The phase-frequency detector
The EXOR Gate

v1 v2 vd
v1 vd 0 0 0
G1 0 1 1
v2'
Fig. 2.2-03 1 0 1
1 1 0
Zero Phase Error:
v1
t
v2'
t
vd
vd
t Fig. 2.2-04
Positive Phase Error:
v1
t
v2'
t
e>0
vd
vd
t Fig. 2.2-05
EXOR Gate Continued

Assume that the average value of vd, is shifted to zero for zero phase error, e. vd can be
plotted as,
vd
VOH
- V -V
2
- e Kd = OH OL

2
VOL Fig. 2.2-06
If v1 and v2 are asymmetrical (have different duty cycles), then vd becomes,

vd
VOH
v1
t
-
2
v2' - e
t 2
vd
vd
Fig. 2.2-07
t VOL
The effect of waveform asymmetry is to reduce the loop gain of the DPLL and also results
in a smaller lock range, pull-in range, etc.
JK Flip-Flop
The JK Flip-Flop is not sensitive to waveform asymmetry
because it is edge-triggered. v1 v2 Qn+1
vd
0 0 Qn
v1 J Q 0 1 0
FF
v2' K Q 1 0 1
1 1 Qn
Fig. 2.2-08
Zero Phase Error (Assume rising edge triggered):
v1
t
v2'
t
vd
vd
t Fig. 2.2-09
Positive Phase Error:
v1
t
v2'
e>0 t
vd
vd
t Fig. 2.2-10
JK Flip-Flop Phase Detector Continued

Input-Output Characteristic:
vd
VOH
V -VOL
- e Kd = OH
2

VOL
Fig. 2.2-11
Comments:
Symmetry of v1 and v2 is unimportant
Both the EXOR and the JK flip-flop have a severely limited pull-in range if the loop filter
does not have a pole at zero.
The Phase-Frequency Detector (PFD)

The PFD can detect both the phase and frequency difference between v1 and v2.
Conceptual diagram:
PD LPF1 VLPF1
Phase Feedback
Vin Vout
out VCO
in
Frequency Feedback
FD LPF2 VLPF2
The output signal of the PFD depends on the phase error in the locked state and on the
frequency error in the unlocked state.
Consequently, the PFD will lock under any condition, irrespective of the type of loop filter
used.

The PFD Continued

PFD implementation:
VDD
No AND Gate With AND Gate
D
FFA Q QA Up QA QB QA QB
v1 Clk R 0 0 1 0State=+1
1 0 0 0State = 0
D R QB Dn 0 1 0 1State=-1
v2' FFB Q 1 1
Clk Fig. 2.2-12
PFD State Diagram:

State II B State 0 A State I
QA= 0 QA= 0 QA= 1

B A
QB= 1 QB= 0 QB= 0
A B Fig. 2.2-13
Unlike the EXOR gates and the R-S latches, the PFD generates two outputs which are
not complementary.
Illustration of a PFD
PFD (A = B):
A QA
PFD
B QB
(Rising edge triggered) Fig. 2.2-14
A>B: A<B:
A A
B B
QA QA
QB QB
Time Time
Fig. 2.2-15

Illustration of the PFD- Continued
A<B: A>B:
A A
B B
QA QA
QB
QB
Time Time
Fig. 2.2-16
PFD Continued
Plot of the PFD output versus phase error:
vd
VOH
-4 -2
e
2 4
VOL
Fig. 2.2-17
When e exceeds 2, the PFD behaves as if the phase error recycled at zero.
VOH-VOL
Kd = 4
A plot of the averaged duty cycle of vd Average Duty Cycle
versus 1/2 (A/B) in the unlocked 1
state of the DPLL: Fraction of time
0.5 QA=1 and QB=0
(+1 state)
0
1/2'
1 2
Fraction of time
-0.5 QA=0 and QB=1
(-1 state)
-1
Fig. 2.2-18

CHARGE PUMPS
Charge Pumps
A charge pump consists of two switched current sources controlled by QA and QB
which drive a capacitor or a combination of a resistor and a capacitor to form a filter for
the PLL with a pole at the origin.
A
VDD
I1 B
QA X QA and QB are
A S1 Vout QA simultaneously
PFD QB high for the
B S2 QB duration given
Y Cp
I1=I2=I by the delay
Vout
I2 of the AND gate
and the reset path
of the flip-flops.
t Fig. 2.2-19
A > B or A = B but A > B: S1 is on and Vout increases.
A < B or A = B but A < B: S2 is on and Vout decreases.
A Charge-Pump PLL
Block diagram:
VDD
I1
x(t) QA
S1 y(t)
PFD VCO
QB
S2
Cp
I2
Fig. 2.2-20
The charge pump and capacitor Cp serve as the loop filter for the PLL.
The charge pump can provide infinite gain for a static phase shift.

Step Response of a Charge Pump PLL

Assume that the period of the input is A
T1 and the charge pump provides a
current of Ip to the capacitor Cp. B
T1
QA
QB e
Detector gain? Vout

Ip
Slope =
Since the steady-state gain = , it is Cp T1 IpT1e
Increase/period =
more meaningful to define Kd as 2Cp
t
follows, Fig. 2.2-195
Ip e Ip T1e
Amount of vd(t) increase per period (T1) = C x 2/T = 2C
p 1 p
Ip T1e 1 Ip e
Average slope per period = 2Cp x T1 = 2Cp
Ip
vd(t) = Average Slope = 2C e(t)
p
Taking the Laplace transform gives,
Ip e Ip V
Vd(s) = 2Cps s Kd = 2Cp rads
A Charge-Pump PLL Continued

Y(s) V2(s)
X(s) = V1 (s) = ?
Ko KoKd Y(s) KoKd
Y(s) = s Vd(s) = s2 [X(s) Y(s)] X(s) = s2 + K K
o d
which has poles at j KoKd . To avoid instability, a zero must
be introduced by the resistor in series with Cp. VDD
I 1 I Kd I1
Vd(s) = 2 R+ sCp = s2Cp (sRCp +1) = s (sp +1)

Ko KoKd S1 Vout
Y(s) = s Vd(s) = s2 (sp +1) [X(s) Y(s)]
S2 Cp

KoKd

KoKd
Y(s) 1 + s2 (sp +1) = s2 (sp +1)X(s) R
I2
Y(s) KoKd(sp +1)
=
X(s) s2 + KoKdps + KoKd Fig. 2.2-21
Equating to the standard second-order denominator gives,

np
n = KoKd and = 2

Nonideal Effects of Charge-Pumps vd
1.) Dead zone. Dead

A dead zone occurs when QA or QB do not reach their full logic Zone
e
levels. This is due to delay differences in the AND gate and the flip-
flops. It is easily removed by proper synchronization of the delays.
Fig. 2.2-22
2.) Mismatch between I1 and I2.

A
To eliminate the dead zone, QA and QB can be simultaneously
B
high for a small time. If I1 I2, the output varies even though e = 0.
(Can introduce spurs.) QA
QB
vd
3.) Charge injection. t
Fig. 2.2-23
When the S1 and S2 switches turn off, they can inject/remove
VDD
charge from Cp. Changes 2.
I1
Cx
X
4.) Charge sharing. S1 vd
Cy
If X VDD and Y = 0 when S1 and S2 are off, the VCO will S2
Y Cp
experience a jump when S1 or S2 turns on. This periodic effect I2
introduces sidebands (spurs) at the output.
Fig. 2.2-24
DYNAMIC PERFORMANCE OF THE DPLL

Types of PLLs
Type I Open-loop transfer function has one pole at the origin.
Type II Open-loop transfer function has two poles at the origin.
The above transfer functions may also have other roots but not at the origin.
Model for the DPLL
PD LPF VCO
1(s)
Ko 2(s)
2'(s) Kd F(s)
s
Optional
N Counter
1
N Fig. 2.2-25
Various configurations of the DPLL:

1.) Phase detector EXOR, J-K flip-flop, or PFD
2.) Filter
Passive lag with or without a charge pump
Active lag with or without a charge pump
Active PI with or without a charge pump
Loop Filters
1.) Passive lag-
1 + s2
PD F(s) = 1 + s( + )
1 2
1 + s2
PFD F(s) s(1 + 2)
Experimental results using the PFD with a passive lag filter show that the gain of the
passive filter is not constant. As a result, the filter dynamics become nonlinear.
2.) Active lag-
1 + s2
PD F(s) = Ka1 + s1
1 + s2
PFD F(s) s1
3.) Active PI-
1 + s2
PD or PFD F(s) = s1
The Hold Range, H

The hold range, H, is the frequency range within which the PLL operation is
statically stable. The hold range for various types of DPLLs are:
Type of PD EXOR EXOR EXOR JK-FF JK-FF JK-FF PFD

Loop Filter Passive Active Active Passive Active Active All
Lag Lag PI Lag Lag PI Filters
H KoKd(/2) KoKd(/2) KoKd KoKdKa
N N N N

The Lock Range, L

The lock range is the offset between 1 and 2/N that causes the DPLL to acquire lock
with one beat note between 1 and 2 = 2/N.
1.) PD = EXOR vd Recall that L(LPLL) = 2n
0.5Kd
t
and L Range of e = e
-0.5Kd 2/
But, e(EXOR)=0.5 e(LPLL)
2'
1
L = 0.5(2n) = n

o 2'(t) L = n
t
Fig. 2.2-26
vd
Kd
2.) PD =JK-Flip flop e(EXOR) = e(LPLL)
t
-Kd
L = (2n)
2/
2'
1
L = 2n

o 2'(t)
t
3.) PD = PFD Fig. 2.2-27
e(PFD) = 2 e(LPLL) L = 2(2n) L = 4n

The lock time for all cases is Tp 2/n.
The Pull-In Range, p, and the Pull-In Time, Tp

The pull-in range, p, is the largest = |12| for which an unlocked loop will lock.
The pull-in time, Tp, is the time required for the loop to lock.
EXOR as the PD:
Waveforms-
vd 2'
T1 T2 1
0.5Kd
(t) 2 '
t
o
-0.5Kd t
T = 2/ T = 2/ Fig. 2.2-28
T1 > T2 because is smaller when vd is positive and larger when vd is negative.

Results-
Type of Filter p (Low loop gains) p (High loop gains) Pull-in Time, Tp
4 o2
Passive Lag 2 2 K K
n o d - n
2 K K
n o d
2 2 n3
n2 4 o2
Active Lag K K
n o d
2 2nKoKd - Ka 2 2 n3
Active PI 4 o2
2 n3
The Pull-In Range, p, and the Pull-In Time, Tp-Continued

JK Flip-Flop as the PD:
Waveforms-
vd 2' 1
T1 T2
Kd
(t) 2'
t
o
-Kd
T = 2/ t
T = 2/ Fig. 2.2-29
T1 > T2 because is smaller when vd is positive and larger when vd is negative.

Results-
Type of Filter p (Low loop gains) p (High loop gains) Pull-in Time, Tp
Passive Lag 2nKoKd - n2 2 nKoKd 1 o2
2 n2
Active Lag n2 2 nKoKd 1 o2
2nKoKd - Ka 2 n2
Active PI 4 o2
2 n2
p and Tp for the PFD

Assume that the PFD uses a single power supply of VDD. The various waveforms are,
v1
v2'
vd
VDD
vd High
0.5VDD Impedance
State
0 t
vd(eq.)
VDD
0.5VDD
(If the filter time constant >> the duty cycle, this waveform simplifies the analysis.)
0 t
vf
VDD
1

Ko
0.5VDD
t
TP Fig. 2.2-30
vd(eq.) is a 50% duty cycle model of the PFD to find Tp.

p and Tp for the PFD Continued

Since p = , let us find Tp using the following model for the passive lag filter:
+ R1+R2 + + R1+R2 +
VDD VDD
vd C vf vd 2C vf
2 2
- - - -
PFD Filter PFD Filter
100% Duty Cycle 50% Duty Cycle Fig. 2.2-31
Use the 50% duty cycle model, solve for the time necessary to increase vf by /Ko.
1.) Loop filter = Passive lag

KoVDD/2
Tp = 2(1+2) lnKoVDD/2 - o

2.) Loop filter = Active lag

KoKaVDD/2
Tp = 21 lnKoKaVDD/2 - o

3.) Loop filter = Active PI

21o
Tp = K V /2
o DD
For split power supplies, replace VDD with (VOH-VOL).
The Pull-Out Range, po

The pull-out range is the size of the frequency step applied to the reference input that
causes the PLL to lose phase tracking.
1.) EXOR: po 2.46n( + 0.65) for 0.1 < < 3
2.) JK Flip-flop:

1-2

po = n exp tan-1 , < 1
1-2
po = ne, =1 po 5.78n( + 0.5) for all
2
1-
po = n exp -1
tanh , > 1
1-2
3.) PFD:
2
1-
po = 2n exp -1
tan , < 1
1-2
po = 2ne, =1
po 11.55n( + 0.5) for all

1-2

po = 2n exp tanh-1 , > 1
1-2

NOISE PERFORMANCE OF THE DPLL

Combination of Noise and Information
In the LPLL, the noise and information signals are added because of the linear
multiplier PD.
The noise supression of DPLLs is generally better than LPLLs but no theory of noise
exists for the DPLL.
The following pages provide some insight into the noise performance of the DPLL.
Noise Performance of a DPLL with an EXOR PD

j Phase noise at
a given inband
frequency
t
v1 Ideal Input
Input with
v1j phase noise
superimposed
j j j j j j (phase jitter)
v2'
Detector
vd Ouput
vd vd is proportional
100% to the phase noise.
LPLL noise theory
50%
DPLL noise theory.
0% t Fig. 2.2-32

Phase Noise in a Communication Signal

Consider the following simple noise model-
Noiseless binary information signal:
v1
t
Above signal after transmission through a bandlimited system:
v1b
t
Superposition of noise:
v1n
Vupper
;; ; ;; ;; ; ;
Vlower
t
Reshaped signal:
;;; ;;;;;;
v1r
t
Phase Fig. 2.2-33
Jitter
Input Signal-to-Noise Ratio

The input signal noise ratio of a pulse with phase jitter is defined as,
1
SNRi =
2 n12
where
W2
n12 36
where,
v1
t
W

Phase Noise in a DPLL with a JK Flip-Flop and a PFD

The basic difference is that the JK Flip-flop and PFD are edge-triggered.
When the input signal fades (v10), the reshaped signal can stick at a distinct logic
level.
Conclusion:
The noise suppression of the DPLL is about the same for all phase detectors as long as
none of the edges of the reference get lost by fading. If fading occurs, the EXOR offers
better noise performance.
Summary of DPLL Noise Performance:
Ps = input signal power
Pn = input noise power
Bi = input noise bandwidth
n 1
BL = noise bandwidth 2 + 4
Ps
SNRi = SNR of the input signal = P
n
Bi
SNRL = SNR of the loop = SNRi 2BL
DPLL DESIGN PROCEDURE

Design Procedure
Objective: Design Ko, Kd, , and F(s)
Given: Phase detector and VCO
Steps:
1.) Specify f1(min), f1(max), f2(min), and f2(max).
2.) Design N unless otherwise specified.
Given: n(min) < n < n(max) and min < < max
For these ranges we get approximately,
n(max) Nmax max Nmax
n(min) = Nmin and min = Nmin N = Nmean = NmaxNmin
3.) Determine . Typically, 0.7.
4.) If noise is of concern, continue with the next step, otherwise go to step 12.
5.) If there are missing edges in the input signal (fading), go to step 6, otherwise go to
step 7.
6.) Choose an EXOR phase detector. Continue with step 8.
VOH-VOL
Kd =
Design Procedure Continued

7.) Choose the JK Flip-flop or PFD as the phase detector.
VOH-VOL
Kd = 2 (JK flip-flop)
VOH-VOL
Kd = 4 (PFD)
8.) Specify BL.
Bi
BL should be chosen so that SNRi 2B 4
L
n12 SNRi and Bi BL
If N changes, this can create a problem because
n 1
BL = 2 + 4
and both n and vary with N.
Need to check that BL(min) is large enough.
If BL is too small, then N should be increased.

9.) Find Ko.
2(max)-2(min)
Ko = v (max)-v (min)
f f
10.) Find n given BL and .
8BL
n = 1+4
If N is variable, use BL and correspondingly to N = Nmean.
11.) Specify the loop filter.
Given n, , Ko, Kd, and N find 1, 2, and Ka (Ka>1).
Go to step 19.
12.) Continued from step 4.
VOH-VOL
Choose the PFD Kd = 4
13.) Find Ko.
2(max)-2(min)
Ko = v (max)-v (min)
f f


14.) Specify the type of loop filter. Use the passive lag filter as the others offer no
benefits.
15.) Determine n.
a.) Fast switching (Tp). Go to step 16.
b.) DPLL does not lock out when switching from Nofref to (No+1) fref. po<fref.
Go to step 20.
c.) Neither the pull-in time nor the pull-out range are critical. Go to step 21.
16.) Given the maximum Tp allowed for the largest frequency step, solve for 1 or 1+2.
17.) Find n.
KoKd
Loop filter is passive: n = N(1+2)
KoKdKa
Active lag filter: n = N1
KoKd
Active PI filter: n = N1

18.) Given n and , find 2.
2
2 = n
If the system cannot be realized (negative values of 1 or 2), modify n and
appropriately.
19.) Given 1 and 2 (and Ka), determine the filter components.
20.) Given po and , find n.
po
n 11.55(+0.5)
21.) Given TL, find n from n 2/TL.
22.) Given n, find 1 and 1+2.
KoKd
Passive lag filter: 1+2 = N 2
n
KoKdKa
Active lag filter: 1 = N 2
n
KoKd
Active PI filter: 1 = N 2
n
Go to step 18.).
Flowchart of the DPLL Design Procedure
Specify the range of f1 and f2

Determine N or range of N
Determine or range of
Yes No
Is Noise Suppression Required?
Yes No
Are there missing edges? Choose the PFD, design the VCO and the loop filter
Use EXOR Use PFD
TP Given TP, po, or TL
po TL
Specify the noise bandwidth, BL Use TP to find 1or 1+2
Use po and to find n Use TL to find n
Design the VCO Estimate n from 1
Use n and to find 1

Use BL and to find n
Select the loop filter and determine 1, 2, (Ka) Use n and to find 2
Calculate the loop filter values Fig. 2.2-37
Design Example A Frequency Synthesizer Using the 74HC/HCT4076

Design a DPLL frequency synthesizer using the CMOS 74HC/HCT4076 PLL. The
frequency sythesizer should be able to produce a set of frequencies in the range of 1MHz
to 2MHz with a channel spacing of 10kHz. Use a PFD and a passive lag-lead filter.
Design:
1.) Determine the ranges of the input and output frequencies.
f1 is constant at 10kHz. f2(min) = 1MHz and f2(max) = 2MHz
2.) Choose N.
2MHz 1MHz
Nmax = 10kHz = 200 and Nmin = 10kHz = 100
Nmean = NmaxNmin = 141
3.) Find . Start by choosing = 0.7 and find max and min.
max Nmax
max = Nmin = 2 and = maxmin = 0.7
min2 2 =0.49 min = 0.59 and max = 0.59 2 = 0.83
0.59 < < 0.83 which is consistent with our choice of .
4.) Select the PFD as the phase detector. For the 74HC/HCT4076, VOH = 5V and
VOL=0V. This gives a Kd = 5V/4 = 0.4 V/rad.

Design Example Continued

5.) According to the data sheet of the f2 (MHz)
74HC4046A, the VCO operates linearly in the
voltage range of vf = 1.1V to 3.9V as shown. 2
2x106x2
Ko = 3.9-1.1 = 2.2x106 rads/Vsec 1
1.1V 3.9V
The data sheet also requires calculation of
vf(V)
two resistors, R1 and R2, and a capacitor, C1. 0 1 2 3 4 5
Fig. 2.2-35
Using the graphs from the data sheet gives,
R1 = 47k, R2 = 130k, and C1 = 100pF.
6.) Assume the loop should lock with 1ms.
TL = 1ms n = 2/TL = 6280 rads/sec.
7.) Using a passive loop filter we get,
KoKd 2.2x1060.4
1+2 = N 2 = 14162802 = 161s
n
2 20.7
8.) 2 = n = 6280 = 223s !!! (The problem is that 1+2 is too small)
Go back and choose TL = 2ms n = 2/TL = 3140 rads/sec.
KoKd 2.2x1060.4 2 20.7
1+2 = N 2 = 14131402 = 633s and 2 = n = 3140 = 446s 1 = 187s
n
Design Problem Continued

9.) Design the loop filter.
For optimum sideband supression, C should be large. Choose C = 0.33F.
1 187x10-6 2 446x10-6
R1 = C = 0.33x10-6 = 567 and R2 = C = 0.33x10-6 = 1.351
The data sheet requires that R1+R2 470 which is satisfied.
Block diagram of the DPLL frequency synthesizer design of this example:
C1=100pF
C1A C1B
v1(10kHz) SIGin 74HC4046A Data N
PC1
COMPin (EXOR) P0P7 PE
v2'
PC2 VCOout 74HC40102 TC v '
(PFD) PCPout VCO (40103) 2
CP
PC3
TE PL MR
(JK)
PC2out VCOin R1 R2
+5V
R1= R2=
R1=567
47k 130k
R2=1.35k
C = 0.33F
Fig. 2.2-36

Simulation of the DPLL Example

The block diagram of this example is shown below.
PD LPF VCO
1(s)
Ko 2(s)
2'(s) Kd F(s)
s
Optional
N Counter
1
N Fig. 2.2-25
The PFD-charge pump combination can be approximated as

Kd(1+s2)
K dF(s) = s(1+2)
Therefore, the loop gain becames
KoKd(1+s2) Kv (1+s2)
LG(s) = s2( + ) = (s+)2( + ) (the factor is used for simulation purposes)
1 2 1 2
For this problem,
Kd = 0.4V/rad., Ko = 2.2x106, 2 = 446s, and 2+2 = 633s. Also choose = 0.01.
R.E. Best, Phase-Locked Loops Design, Simulation, and Applications, 4th Ed., McGraw-Hill, NY, p. 103
Simulation of the DPLL Example Continued

PSPICE Input File
DPLLDesignProblem-OpenLoopResponse-Best
VS10AC1.0
R11010K
*Loopbandwidth=Kv=8.8x10E5sec.-1Tau1=187E-6Tau2=446E-6N=141
ELPLL20LAPLACE{V(1)}={8.8E+6/(S+0.01)/141*(0.446E-3*S+1)/(S+0.01)/0.633E-3}
R22010K
*SteadystateACanalysis
.ACDEC2010100K
.PRINTACVDB(2)VP(2)
.PROBE
.END
100
Simulation Results:
80
60
dB or Degrees
40
LG Phase
20
Phase
|LG|
0 Margin
84
Note that the phase is very -20 c
close to 0 and |LG|>>1 at -40
low frequencies which is 10 100 1000 10 4 10 5
Frequency (Hz)
typical of type II systems.
DPLL SYSTEM SIMULATION

Examples of Case Studies using the Best Software
PLL Parameters-
Supply voltages:
Positive supply = 5V Negative supply = -5V
Phase detector:
Vsat+ = 4.5V Vsat- = 0.5V
Loop filter:
1 = 500s 2 = 50s
Oscillator:
Ko = 130,000 rads/Vsec Vsat+ = 4.5V Vsat- = 0.5V
The simulation program will be used to verify the following calculated values:
n = 17,347 rads/sec.
= 0.486
fpo = 7719 Hz
fp = 13,192 Hz
Roland E. Best, Phase-Locked Loops Design, Simulation, and Applications, 4th ed., McGraw-Hill Book Co., 1999, New York, NY
Case 1 System Benchmark
vd
vd(mV)
vf
t(s)

Case 2 - f = 8000Hz
vd

Phase error
vd(V) 90
vf
Case 3 Loop Just Locks Out
vf
vf
vd vd
vd(V)
Loop pulls out

Case 4 Pull-In Range Verification
vf
4.5
4.0
3.5 vd
3.0
vd(V) 2.5
2.0
1.5
1.0
0.5
Loop will not pull back in for df > 14,200 Hz

Case 5 PFD and Illustration of a Virtually Infinite Pull-In Range

fp = 40kHz f = 35 kHz to avoid clipping of vf.
vf
vd(V) vd
Tp 1.5ms
Case 6 EXOR with Active PI Filter

4.5
vf
4.0
3.5
3.0
2.5
vd(V)
2.0 vd
1.5
1.0
0.5
Tp 5ms
SUMMARY
The DPLL has a digital phase detector and the remainder of the blocks are analog
Digital phase detectors
- EXOR Gate
- JK Flip-Flop
- Phase-Frequency Detector
Charge pump a filter implementation using currents sources and a capacitor that
works with the PFD
Charge pumps implement a pole at the origin to result in zero phase error
The DPLL is much more compatible with IC technology and is the primary form of PLL
used for frequency synthesizers

Lecture 070 - Digital Phase Lock Loops (DPLL) Digital Phase Locked Loops (DPLL)

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Lecture 070 - Digital Phase Lock Loops (DPLL) Digital Phase Locked Loops (DPLL)

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Lecture 070 DPLLs - I (5/15/03) Page 070-1

LECTURE 070 DIGITAL PHASE LOCK LOOPS (DPLL)

ECE 6440 - Frequency Synthesizers P.E. Allen - 2003

Lecture 070 DPLLs - I (5/15/03) Page 070-2

BUILDING BLOCKS OF THE DPLL

ECE 6440 - Frequency Synthesizers P.E. Allen - 2003

DIGITAL PHASE DETECTORS

vin(t) vout vin(t)

Types of digital phase detectors:

ECE 6440 - Frequency Synthesizers P.E. Allen - 2003

Lecture 070 DPLLs - I (5/15/03) Page 070-4

The EXOR Gate

EXOR Gate Continued

VOL Fig. 2.2-06

If v1 and v2 are asymmetrical (have different duty cycles), then vd becomes,

Lecture 070 DPLLs - I (5/15/03) Page 070-6

JK Flip-Flop Phase Detector Continued

ECE 6440 - Frequency Synthesizers P.E. Allen - 2003

Lecture 070 DPLLs - I (5/15/03) Page 070-8

The Phase-Frequency Detector (PFD)

ECE 6440 - Frequency Synthesizers P.E. Allen - 2003

The PFD Continued

PFD State Diagram:

QA= 0 QA= 0 QA= 1

Lecture 070 DPLLs - I (5/15/03) Page 070-10

ECE 6440 - Frequency Synthesizers P.E. Allen - 2003

Illustration of the PFD- Continued

ECE 6440 - Frequency Synthesizers P.E. Allen - 2003

Lecture 070 DPLLs - I (5/15/03) Page 070-12

ECE 6440 - Frequency Synthesizers P.E. Allen - 2003

ECE 6440 - Frequency Synthesizers P.E. Allen - 2003

Lecture 070 DPLLs - I (5/15/03) Page 070-14

ECE 6440 - Frequency Synthesizers P.E. Allen - 2003

Step Response of a Charge Pump PLL

Detector gain? Vout

Lecture 070 DPLLs - I (5/15/03) Page 070-16

A Charge-Pump PLL Continued

Equating to the standard second-order denominator gives,

ECE 6440 - Frequency Synthesizers P.E. Allen - 2003

Nonideal Effects of Charge-Pumps vd

1.) Dead zone. Dead

2.) Mismatch between I1 and I2.

ECE 6440 - Frequency Synthesizers P.E. Allen - 2003

Lecture 070 DPLLs - I (5/15/03) Page 070-18

DYNAMIC PERFORMANCE OF THE DPLL

Various configurations of the DPLL:

ECE 6440 - Frequency Synthesizers P.E. Allen - 2003

Lecture 070 DPLLs - I (5/15/03) Page 070-20

The Hold Range, H

Type of PD EXOR EXOR EXOR JK-FF JK-FF JK-FF PFD

ECE 6440 - Frequency Synthesizers P.E. Allen - 2003

The Lock Range, L

e(PFD) = 2 e(LPLL) L = 2(2n) L = 4n

Lecture 070 DPLLs - I (5/15/03) Page 070-22

The Pull-In Range, p, and the Pull-In Time, Tp

T1 > T2 because is smaller when vd is positive and larger when vd is negative.

The Pull-In Range, p, and the Pull-In Time, Tp-Continued

T1 > T2 because is smaller when vd is positive and larger when vd is negative.

ECE 6440 - Frequency Synthesizers P.E. Allen - 2003

Lecture 070 DPLLs - I (5/15/03) Page 070-24

p and Tp for the PFD

vd(eq.) is a 50% duty cycle model of the PFD to find Tp.

p and Tp for the PFD Continued