Beruflich Dokumente
Kultur Dokumente
Applications
Gaming and virtual reality input devices
Motion control with MMI (man-machine
interface)
GPS navigation systems
LGA-16 (3x3x1 mm) Appliances and robotics
Description
Features The L3GD20H is a low-power three-axis angular
Wide supply voltage, 2.2 V to 3.6 V rate sensor.
Wide extended operating temperature range It includes a sensing element and an IC interface
(from -40 C to 85 C) able to provide the measured angular rate to the
Low voltage compatible IOs, 1.8 V external world through digital interface (I2C/SPI).
Contents
3 Application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5 Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.1 I2C serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.1.1 I2C operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.2 SPI bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.2.1 SPI read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.2.2 SPI write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.2.3 SPI read in 3-wires mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.1 WHO_AM_I (0Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.2 CTRL1 (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.3 CTRL2 (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.4 CTRL3 (22h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.5 CTRL4 (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.6 CTRL5 (24h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7.7 REFERENCE (25h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7.8 OUT_TEMP (26h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7.9 STATUS (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.10 OUT_X_L (28h), OUT_X_H (29h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.11 OUT_Y_L (2Ah), OUT_Y_H (2Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.12 OUT_Z_L (2Ch), OUT_Z_H (2Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.13 FIFO_CTRL (2Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.14 FIFO_SRC (2Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
7.15 IG_CFG (30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
7.16 IG_SRC (31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
7.17 IG_THS_XH (32h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
7.18 IG_THS_XL (33h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
7.19 IG_THS_YH (34h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
7.20 IG_THS_YL (35h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
7.21 IG_THS_ZH (36h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
7.22 IG_THS_ZL (37h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
7.23 IG_DURATION (38h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
8 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
List of tables
List of figures
+
x,y,z
X+
CHARGE MIXER LOW-PASS
Y+
AMP FILTER F
Z+ D
I I
L CS
M A G
D T I2C SCL/SPC
U I
X C E SPI SDA/SDI/SDO
Z- T SDO/SA0
1 A R
Y- I
L N
X- G
T
E
M
S
P
E E A
N D
DRIVING MASS R
S C
A
O 2
T
R
U
Feedback loop R
E
AM12689V1
The vibration of the structure is maintained by a drive circuitry in a feedback loop. The
sensing signal is filtered and appears as digital signal at the output.
+
Z
Cap
RES
Vdd
1
X 14 16
+
Y GND 13 1 Vdd_IO
GND BOTTOM SCL/SPC
RES VIEW SDA/SDI/SDO
RES SDO/SA0
RES 9 5 CS
+
X 8 6
DEN
INT1
DRDY/INT2
(TOP VIEW)
DIRECTIONS OF THE
DETECTABLE
ANGULAR RATE
AM12690V1
245
FS Measurement range User selectable 500 dps
2000
8.75
So Sensitivity 17.50 mdps/digit
70.00
11.9/23.7/
47.3/94.7/
Digital output data
ODR 189.4/ Hz
rate(3)
378.8/
757.6
Operating temperature
Top -40 +85 C
range
1. Typical specifications are not guaranteed.
2. Guaranteed by design.
3. The period (1/ODR), length of time between two consecutive sampling, must be derived by the reciprocal of the maximum.
and minimum ODR limits: for example for ODR = 189.4 Hz, sampling period range will be within [4591 s, 6211 s] (where
ODR minimum and maximum have been approximated at 162 Hz, 219 Hz respectively).
a. The product is factory calibrated at 3.0 V. The operational power supply range is specified in Table 4.
CS
SPC
tsu(SI) th(SI)
d. Measurement points are done at 0.2Vdd_IO and 0.8Vdd_IO, for both Input and Output port.
tsu(SR)
tw(SP:SR) START
SDA
tsu(SP) STOP
SCL
e. Measurement points are done at 0.2Vdd_IO and 0.8Vdd_IO, for both ports.
This is a mechanical shock sensitive device, improper handling can cause permanent
damage to the part.
This is an ESD sensitive device, improper handling can cause permanent damage to
the part.
2.6 Terminology
2.6.1 Sensitivity
An angular rate gyroscope is a device that produces a positive-going analog output for
counterclockwise rotation around the sensitive axis considered. Sensitivity describes the
gain of the sensor and can be determined by applying a defined angular velocity to it. This
value changes very little over temperature and time.
3 Application hints
+
Z
Vdd
10nF(25V)*
1 C1
X
+ 100nF 10F GND
Y
GND
Vdd_IO 16 14
+
X
1 13
(TOP VIEW) SCL/SPC
DRDY/INT2
INT1
DEN
GND
Rpu = 10kOhm
Rpu
SCL/SPC
SDA_SDI_SDO
GAMS080220130927FSR
00
01 DataReg
0
FIFO
LPF2 10 32x16x3
11
ADC LPF1 HPF 1 I2C
SPI
HPen INT_Sel
10
11
Interrupt
01 generator
00
SCR REG
CONF REG
INT1
AM07230v1
4.2 FIFO
L3GD20H embeds 32 slots of 16-bit data FIFO for each of the three output channels: yaw,
pitch and roll. This allows consistent power saving for the system, since the host processor
does not need to continuously poll data from the sensor, but it can wakeup only when
needed and burst the significant data out from the FIFO. This buffer can work accordingly to
seven different modes: Bypass mode, FIFO-mode, Stream mode, Stream-to-FIFO mode,
Bypass-to-Stream, Dynamic-Stream, Bypass-to-FIFO. Each mode is selected by the FM2:0
bits in FIFO_CTRL register. Programmable FIFO threshold level, FIFO empty or FIFO
overrun events are available on FIFO_SRC register and can be set to generate dedicated
interrupts on DRDY/INT2 pin.
FIFO_SRC(EMPTY) is equal to '1' when no samples are available.
FIFO_SRC(FTH) goes to '1' if a new data arrives and FIFO_SRC(FSS4:0) is greater than or
equal to FIFO Threshold configured to FTH4:0 into FIFO_CTRL (2Eh). FIFO_SRC(FTH)
goes to '0' if reading Yaw, Pitch and Roll data slot from FIFO and FIFO_SRC(FSS4:0) is
minor than or equal to FIFO_CTRL(FTH4:0).
[L\L]L
[ \ L ]
[ \ ]
[ \ ]
HPSW\
[ \ ]
$0Y
[L\L]L
[ \ L ]
[ \ ]
[ \ ]
[ \ ]
$0Y
[L\L]L
[ \ ]
[ \ ]
[ \ ]
[ \ ]
[ \ ]
$0Y
In the latter case reading all FIFO content before an overrun interrupt has occurred, the
first data read is equal to the last already read in previous burst, so the number of new data
available in FIFO depends on previous reading (see FIFO_SRC behavior depicted in next
figures).
GAMS310120131021FSR
In dynamic-stream mode (FIFO_CTRL(FM2:0) = 110) after emptying the FIFO the first new
sample that arrives becomes the first to be read in subsequent read burst. In this way in
GAMS310120131023FSR
x1 y1 z1
x1 y1 z1
x2 y2 z2
x2 y2 z2
Empty
x 30 y 30 z30
x 31 y 31 z31
x 31 y 31 z31
[ \ ]
[ \ ]
[ \ ]
[ \ ]
(PSW\
[ \ ]
[ \ ]
[ \ ]
%\SDVVPRGH 6WUHDPPRGH
7ULJJHUHYHQW $0Y
x,y,z
Read #n OUT_X OUT_Y OUT_Z
(28-29) (2A-2B) (2C-2D)
GAMS290120131638FSR
Level-sensitive xi,yi,zi D
Trigger enabled xi(15-1) E yi(15-0) Zi(15-0)
on X-Axis
d N
Xen=1,Yen=Zen=0 xi-N+1 D yi-N+1 zi-N+1
(15-1) E
N (15-0) (15-0)
Level-sensitive
xi,yi,zi D
Trigger enabled xi(15-0) yi(15-1) E Zi(15-0)
on Y-axis N
Yen=1, Xen=Zen=0 D
xi-N+1 yi-N+1 Zi-N+1
E
(15-0) (15-1) N (15-0)
Level-sensitive xi,yi,zi D
Trigger enabled xi(15-0) yi(15-0) Zi(15-1) E
on Z-axis N
Zen=1, Xen=Yen=0 D
xi-N+1 yi-N+1 zi-N+1
E
(15-0) (15-0) (15-1)
N
GAMS290120131645FSR
Once enabled, FIFO is filled with the Pitch, Roll and Yaw data on the rising edge of DEN
input signal. When ODR selected is 800 Hz, maximum DEN sample frequency is
fDEN =1/TDEN = 400 Hz.
GAMS310120131026FSR
5 Digital interfaces
The registers embedded inside the L3GD20H may be accessed through both the I2C and
SPI serial interfaces. The latter may be SW configured to operate either in 3-wire or 4-wire
interface mode.
The serial interfaces are mapped onto the same pins. To select/exploit the I2C interface, CS
line must be tied high (i.e connected to Vdd_IO).
SPI enable
CS
I2C/SPI mode selection (1: I2C mode; 0: SPI enabled)
I2C Serial Clock (SCL)
SCL/SPC
SPI Serial Port Clock (SPC)
I2C Serial Data (SDA)
SDA/SDI/SDO SPI Serial Data Input (SDI)
3-wire Interface Serial Data Output (SDO)
SPI Serial Data Output (SDO)
SDO/SA0
I2C less significant bit of the device address
There are two signals associated with the I2C bus: the serial clock line (SCL) and the serial
data line (SDA). The latter is a bidirectional line used for sending and receiving the data
to/from the interface. Both the lines must be connected to Vdd_IO through external pull-up
resistor. When the bus is free both the lines are high.
The I2C interface is compliant with fast mode (400 kHz) I2C standards as well as with the
normal mode.
Table 15. Transfer when Master is receiving (reading) one byte of data from slave
Master ST SAD + W SUB SR SAD + R NMAK SP
Slave SAK SAK SAK DATA
Table 16. Transfer when Master is receiving (reading) multiple bytes of data from slave
Master ST SAD+W SUB SR SAD+R MAK MAK NMAK SP
Slave SAK SAK SAK DATA DATA DATA
Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number
of bytes transferred per transfer is unlimited. Data is transferred with the Most Significant bit
(MSb) first. If a receiver cant receive another complete byte of data until it has performed
some other function, it can hold the clock line, SCL LOW to force the transmitter into a wait
state. Data transfer only continues when the receiver is ready for another byte and releases
the data line. If a slave receiver doesnt acknowledge the slave address (i.e. it is not able to
receive because it is performing some real time function) the data line must be left HIGH by
the slave. The Master can then abort the transfer. A LOW to HIGH transition on the SDA line
while the SCL line is HIGH is defined as a STOP condition. Each data transfer must be
terminated by the generation of a STOP (SP) condition.
In order to read multiple bytes, it is necessary to assert the most significant bit of the sub-
address field. In other words, SUB(7) must be equal to 1 while SUB(6-0) represents the
address of first register to be read.
In the presented communication format MAK is Master Acknowledge and NMAK is No
Master Acknowledge.
In order to disable the I2C block it is needed to write '1' in bit 3 of register located in address
39h.
CS
SPC
SDI
RW DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
MS AD5 AD4 AD3 AD2 AD1 AD0
SDO
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
AM10129V1
CS is the Serial Port Enable and it is controlled by the SPI master. It goes low at the start of
the transmission and goes back high at the end. SPC is the Serial Port Clock and it is
controlled by the SPI master. It is stopped high when CS is high (no transmission). SDI and
SDO are respectively the Serial Port Data Input and Output. Those lines are driven at the
falling edge of SPC and should be captured at the rising edge of SPC.
Both the Read Register and Write Register commands are completed in 16 clock pulses or
in multiple of 8 in case of multiple bytes read/write. Bit duration is the time between two
falling edges of SPC. The first bit (bit 0) starts at the first falling edge of SPC after the falling
edge of CS while the last bit (bit 15, bit 23, ...) starts at the last falling edge of SPC just
before the rising edge of CS.
bit 0: RW bit. When 0, the data DI(7:0) is written into the device. When 1, the data DO(7:0)
from the device is read. In latter case, the chip will drive SDO at the start of bit 8.
bit 1: MS bit. When 0, the address will remain unchanged in multiple read/write commands.
When 1, the address will be auto incremented in multiple read/write commands.
bit 2-7: address AD(5:0). This is the address field of the indexed register.
bit 8-15: data DI(7:0) (write mode). This is the data that will be written into the device (MSb
first).
bit 8-15: data DO(7:0) (read mode). This is the data that will be read from the device (MSb
first).
In multiple read/write commands further blocks of 8 clock periods will be added. When MS
bit is 0 the address used to read/write data remains the same for every block. When MS bit
is 1 the address used to read/write data is incremented at every block.
The function and the behavior of SDI and SDO remain unchanged.
CS
SPC
SDI
RW
MS AD5 AD4 AD3 AD2 AD1 AD0
SDO
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
AM10130V1
The SPI Read command is performed with 16 clock pulses. Multiple byte read command is
performed adding blocks of 8 clock pulses at the previous one.
CS
SPC
SDI
RW
M S A D5 A D4 AD 3 A D2 A D1 A D0
SD O
DO 7 DO 6 DO 5 DO 4 DO 3 DO 2 DO 1 DO 0 DO 15 DO 14 DO 13 DO 12 DO 11 DO 10 D O9 D O8
AM10131V1
CS
SPC
SDI
RW D I7 D I6 D I5 D I4 DI3 DI2 DI1 DI0
MS AD5 AD 4 AD 3 AD2 AD 1 AD0
AM10132V1
The SPI Write command is performed with 16 clock pulses. Multiple byte write command is
performed adding blocks of 8 clock pulses at the previous one.
bit 0: WRITE bit. The value is 0.
bit 1: MS bit. When 0 do not increment address, when 1 increment address in multiple
writing.
bit 2 -7: address AD(5:0). This is the address field of the indexed register.
bit 8-15: data DI(7:0) (write mode). This is the data that will be written inside the device
(MSb first).
bit 16-... : data DI(...-8). Further data in multiple byte writing.
CS
SPC
SDI
DI7 D I6 DI5 D I4 DI3 DI2 DI1 DI0 DI15 D I1 4DI13 D I1 2DI11 DI10 DI9 DI8
RW
MS AD5 AD4 AD3 AD2 AD1 AD 0
AM10133V1
CS
SPC
SDI/O
RW D O7 D O6 D O5 DO4 DO3 DO2 DO1 DO0
MS AD5 AD 4 AD 3 AD2 AD1 AD 0
AM10134V1
The table given below provides a listing of the 8 bit registers embedded in the device and
the related addresses:
Reserved - 00-0E - -
WHO_AM_I r 0F 000 1111 11010111
Reserved - 10-1F - -
CTRL1 rw 20 010 0000 00000111
CTRL2 rw 21 010 0001 00000000
CTRL3 rw 22 010 0010 00000000
CTRL4 rw 23 010 0011 00000000
CTRL5 rw 24 010 0100 00000000
REFERENCE rw 25 010 0101 00000000
OUT_TEMP r 26 010 0110 Output
STATUS r 27 010 0111 Output
OUT_X_L r 28 010 1000 Output
OUT_X_H r 29 010 1001 Output
OUT_Y_L r 2A 010 1010 Output
OUT_Y_H r 2B 010 1011 Output
OUT_Z_L r 2C 010 1100 Output
OUT_Z_H r 2D 010 1101 Output
FIFO_CTRL rw 2E 010 1110 00000000
FIFO_SRC r 2F 010 1111 Output
IG_CFG rw 30 011 0000 00000000
IG_SRC r 31 011 0001 Output
IG_THS_XH rw 32 011 0010 00000000
IG_THS_XL rw 33 011 0011 00000000
IG_THS_YH rw 34 011 0100 00000000
IG_THS_YL rw 35 011 0101 00000000
IG_THS_ZH rw 36 011 0110 00000000
IG_THS_ZL rw 37 011 0111 00000000
IG_DURATION rw 38 011 1000 00000000
LOW_ODR rw 39 011 1001 00000000
Registers marked as Reserved must not be changed. The writing to those registers may
cause permanent damages to the device.
The content of the registers that are loaded at boot should not be changed. They contain the
factory calibration values. Their content is automatically restored when the device is
powered-up.
7 Register description
The device contains a set of registers which are used to control its behavior and to retrieve
angular rate data. The registers address, made of 7 bits, is used to identify them and to write
the data through serial interface.
DR<1:0> is used to set ODR selection. BW <1:0> is used to set bandwidth selection.
In the following table are reported all frequency resulting in combination of DR / BW bits.
1 00 00 12.5 n.a.
1 00 01 12.5 n.a.
1 00 10 12.5 n.a.
1 00 11 12.5 n.a.
1 01 00 25 n.a.
1 01 01 25 n.a.
1 01 10 25 n.a.
1 01 11 25 n.a.
1 1X 00 50 16.6
1 1X 01 50 16.6
1 1X 10 50 16.6
1 1X 11 50 16.6
0 00 00 100 12.5
0 00 01 100 25
0 00 10 100 25
0 00 11 100 25
0 01 00 200 12.5
0 01 01 200 -
0 01 10 200 -
0 01 11 200 70
0 10 00 400 20
0 10 01 400 25
0 10 10 400 50
0 10 11 400 110
0 11 00 800 30
0 11 01 800 35
0 11 10 800 -
0 11 11 800 100
1. this bit is described in register LOW_ODR (39h register).
2. values in the table are indicative and they can vary proportionally with the specific ODR value.
Combination of PD, Zen, Yen, Xen are used to set device in different modes (power down /
normal / sleep mode) according with the following table.
Power down 0 - - -
Normal 1 - - -
Sleep 1 0 0 0
Table 26. High pass filter cut off frequency configuration [Hz](1)
ODR=12.5 ODR=25 ODR=50 ODR =100 ODR =200 ODR =400 ODR =800
HPCF3-0 Hz Hz Hz Hz Hz Hz Hz
0000 1 2 4 8 15 30 56
0001 0.5 1 2 4 8 15 30
0010 0.2 0.5 1 2 4 8 15
0011 0.1 0.2 0.5 1 2 4 8
Table 26. High pass filter cut off frequency configuration [Hz](1) (continued)
ODR=12.5 ODR=25 ODR=50 ODR =100 ODR =200 ODR =400 ODR =800
HPCF3-0 Hz Hz Hz Hz Hz Hz Hz
0100 0.05 0.1 0.2 0.5 1 2 4
0101 0.02 0.05 0.1 0.2 0.5 1 2
0110 0.01 0.02 0.05 0.1 0.2 0.5 1
0111 0.005 0.01 0.02 0.05 0.1 0.2 0.5
1000 0.002 0.005 0.01 0.02 0.05 0.1 0.2
1001 0.001 0.002 0.005 0.01 0.02 0.05 0.1
1. values in the table are indicative and they can vary proportionally with the specific ODR value
00
01 DataReg
0 FIFO
10 32x16x3
LPF2
11
ADC LPF1 HPF 1
AM08592V1
0 0 0 Bypass mode
0 0 1 FIFO mode
0 1 0 Stream mode
0 1 1 Stream-to-FIFO mode
1 0 0 Bypass-to-stream mode
1 1 0 Dynamic stream mode
1 1 1 Bypass-to-FIFO mode
D6 - D0 bits set the minimum duration of the Interrupt event to be recognized. Duration
steps and maximum values depend on the ODR chosen.
8 Package information
A1 1
A2 0.785
A3 0.200
D1 2.850 3.000 3.150
E1 2.850 3.000 3.150
L1 1.000 1.060
L2 2.000 2.060
N1 0.500
N2 1.000
M 0.040 0.100
P1 0.875
P2 1.275
T1 0.290 0.350 0.410
T2 0.190 0.250 0.310
d 0.150
k 0.050
7983231_M
9 Revision history
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