Experiment name: Realize a Boolean expression Y=NOT ((A+B) (C+D)E)in DSCH

schematic and draw mask layout and simulate.

Objectives: The objectives of this experiment are:

To realize a Boolean expression Y=NOT ((A+B) (C+D) E) in DSCH and simulate.

Realize its VERILOG codes.
Realize its mask layout diagram in MICROWIND and identifying different sections
of the circuit.

Procedure:

Design the following schematic in DSCH platform as shown in figure 1 and simulate its logic
function with clocks like below this figure.

2. Generate its VERILOG codes.

// DSCH 2.7f
// 7/6/2017 6:02:45 PM
// Z:\MW2\Export dsch2\Lab 04.sch
module Lab 04( clk5,clk3,clk2,clk1,clk4,out1);
input clk5,clk3,clk2,clk1,clk4;
output out1;
pmospmos(w2,vdd,clk1); // 2.0u 0.12u
pmospmos(out1,w2,clk2); // 2.0u 0.12u
pmospmos(w6,vdd,clk3); // 2.0u 0.12u
pmospmos(out1,w6,clk4); // 2.0u 0.12u
pmospmos(out1,vdd,clk5); // 2.0u 0.12u
nmosnmos(out1,w9,clk2); // 1.0u 0.12u
nmosnmos(w9,w10,clk3); // 1.0u 0.12u
nmosnmos(w10,vss,clk5); // 1.0u 0.12u
nmosnmos(out1,w9,clk1); // 1.0u 0.12u
nmosnmos(w9,w10,clk4); // 1.0u 0.12u
endmodule
// Simulation parameters in Verilog Format always
#16000 clk5=~clk5;
#4000 clk3=~clk3;
#2000 clk2=~clk2;
3. Draw layout mask layout diagram in MICROWIND and identify its different sections.
VERILOG CODE:

// DSCH 2.7f
// 7/6/2017 6:38:02 PM
// Z:\lab4.sch
module lab4( F,A,B,C,E,D,out3);
input F,A,B,C,E,D;
output out3;
nmosnmos(out3,w1,B); // 1.0u 0.12u
nmosnmos(w1,w4,C); // 1.0u 0.12u
nmosnmos(w1,w4,E); // 1.0u 0.12u
nmosnmos(w4,vss,F); // 1.0u 0.12u
pmospmos(w9,vdd,A); // 2.0u 0.12u
pmospmos(out3,w9,B); // 2.0u 0.12u
pmospmos(w10,vdd,C); // 2.0u 0.12u
pmospmos(out3,w10,E); // 2.0u 0.12u
nmosnmos(out3,w1,A); // 1.0u 0.12u
pmospmos(w12,vdd,D); // 2.0u 0.12u
pmospmos(out3,w12,F); // 2.0u 0.12u
nmosnmos(w4,vss,D); // 1.0u 0.12u
endmodule
// Simulation parameters in Verilog Format
always
#32000 F=~F;
#1000 A=~A;
#2000 B=~B;
#4000 C=~C;
#16000 E=~E;
#8000 D=~D;
// Simulation parameters
// F CLK 320.000 320.000
// A CLK 10.000 10.000
// B CLK 20.000 20.000
// C CLK 40.000 40.000
// E CLK 160.000 160.000
// D CLK 80.000 80.000

Discussion: Here we implement,Boolean expression in DSCH .In DSCH we built a circuit of

Boolean expression Y=not((A+B)(C+D)E). In DSCH, we find schematic of Boolean
expression Y. We generate VERILOG code from the DSCH platform an implement this code
to find mask layout of the Boolean expression. From this layout we justify the output of the
Boolean expression. In the same procedure we done Y=not((A+B)(C+D)(E+F)).
 Lab-01

Course: ETE401

Course Code: VLSI Circuit Deign

Sec: 01

Submitted By:

Abdul Waaje
2014-1-55-009

Submitted To:

Dr. Hamidur Rahman

Dated: 30/07/2017
Experiment name: Realize a Boolean expression Y=NOT ((A+B) (C+D)E)in DSCH
schematic and draw mask layout and simulate.

Objectives: The objectives of this experiment are:

To realize a Boolean expression Y=NOT ((A+B) (C+D) E) in DSCH and simulate.

Realize its VERILOG codes.
Realize its mask layout diagram in MICROWIND and identifying different sections
of the circuit.

Procedure:

Design the following schematic in DSCH platform as shown in figure 1 and simulate its logic
function with clocks like below this figure.

2. Generate its VERILOG codes.

// DSCH 2.7f
// 7/6/2017 6:02:45 PM
// Z:\MW2\Export dsch2\Lab 04.sch
module Lab 04( clk5,clk3,clk2,clk1,clk4,out1);
input clk5,clk3,clk2,clk1,clk4;
output out1;
pmospmos(w2,vdd,clk1); // 2.0u 0.12u
pmospmos(out1,w2,clk2); // 2.0u 0.12u
pmospmos(w6,vdd,clk3); // 2.0u 0.12u
pmospmos(out1,w6,clk4); // 2.0u 0.12u
pmospmos(out1,vdd,clk5); // 2.0u 0.12u
nmosnmos(out1,w9,clk2); // 1.0u 0.12u
nmosnmos(w9,w10,clk3); // 1.0u 0.12u
nmosnmos(w10,vss,clk5); // 1.0u 0.12u
nmosnmos(out1,w9,clk1); // 1.0u 0.12u
nmosnmos(w9,w10,clk4); // 1.0u 0.12u
endmodule
// Simulation parameters in Verilog Format always
#16000 clk5=~clk5;
#4000 clk3=~clk3;
#2000 clk2=~clk2;
3. Draw layout mask layout diagram in MICROWIND and identify its different sections.
VERILOG CODE:

// DSCH 2.7f
// 7/6/2017 6:38:02 PM
// Z:\lab4.sch
module lab4( F,A,B,C,E,D,out3);
input F,A,B,C,E,D;
output out3;
nmosnmos(out3,w1,B); // 1.0u 0.12u
nmosnmos(w1,w4,C); // 1.0u 0.12u
nmosnmos(w1,w4,E); // 1.0u 0.12u
nmosnmos(w4,vss,F); // 1.0u 0.12u
pmospmos(w9,vdd,A); // 2.0u 0.12u
pmospmos(out3,w9,B); // 2.0u 0.12u
pmospmos(w10,vdd,C); // 2.0u 0.12u
pmospmos(out3,w10,E); // 2.0u 0.12u
nmosnmos(out3,w1,A); // 1.0u 0.12u
pmospmos(w12,vdd,D); // 2.0u 0.12u
pmospmos(out3,w12,F); // 2.0u 0.12u
nmosnmos(w4,vss,D); // 1.0u 0.12u
endmodule
// Simulation parameters in Verilog Format
always
#32000 F=~F;
#1000 A=~A;
#2000 B=~B;
#4000 C=~C;
#16000 E=~E;
#8000 D=~D;
// Simulation parameters
// F CLK 320.000 320.000
// A CLK 10.000 10.000
// B CLK 20.000 20.000
// C CLK 40.000 40.000
// E CLK 160.000 160.000
// D CLK 80.000 80.000

Discussion: Here we implement,Boolean expression in DSCH .In DSCH we built a circuit of

Boolean expression Y=not((A+B)(C+D)E). In DSCH, we find schematic of Boolean
expression Y. We generate VERILOG code from the DSCH platform an implement this code
to find mask layout of the Boolean expression. From this layout we justify the output of the
Boolean expression. In the same procedure we done Y=not((A+B)(C+D)(E+F)).
 Lab-01

Course: ETE401

Course Code: VLSI Circuit Deign

Sec: 01

Submitted By:

Tamanna Akter
2014-1-55-003

Submitted To:

Dr. Hamidur Rahman

Dated: 30/07/2017