2 CMOS

1. CMOS digital switches use

(a). n-channel and p-channel D-MOSFETs in series

(b). n-channel and p-channel D-MOSFETs in parallel
(c). n-channel and p-channel E-MOSFETs in series
(d). n-channel and p-channel E-MOSFETs in parallel

2. The circuit shown in figure

+VDD
(a) NAND

(b) NOR Y
A M2
(c) AND
B M1
(d) OR

3. The above shown NMOS circuit is a gate of the type

V (EE-IES 2003)
(a) NAND
(b) NOR
(c) AND Y
A
(d) EXCLUSIVE-OR

4. For CMOS implementation of 2 input XOR logic gate, how

many nMOS and pMOS transistors are required?
(ISRO SET-2010)
(a) 2 nMOS and 2 pMOS
(d) 3 nMOS and 3 pMOS
(c) 6 nMOS and 6 pMOS
(d) 8 nMOS and 8 pMOS

5. The circuit shown in fig. acts as a +VDD

(a) NAND
M3
(b) NOR
Y
(c) AND
A M1 M2 B
(d) OR

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ACE CLASS ROOM PRACTICE QUESTIONS 55

6. In the circuit shown 5Volts (EC-GATE 2012)

A
(a) Y A B C
C
B
(b) Y (A B)C
Y

(c) Y A BC C

(d) Y AB C
A B

7. Consider the CMOS circuit shown in fig. The output Y is

+VDD
(a) A CB

(b) A BC C
A

B
(c) AB + C
Y
C
(d) AB C
A B

8. An NMOS circuit is shown in the above figure. The logic

function for the output (o/p) is (EC-IES 2001)

(a) A B .C D . E +V DD

(b) AB C
. D E output

(c) A.( B C.) DE A D

(d) ABCDE C
B E

+5V
9. The CMOS shown in fig. implement
Logic Input PMOS
(a) ( AB CD) E A to E Network
Y

(b) (A B) (C D) E C
A
(c) AB + CD + E
B D
(d) (A + B) (C + D) E
E

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56 CNOS ACE

10. The circuit shown in fig. implements the function

+VDD
(a) (A + B)C + D

A
(b) AB C D
C
B

(c) A BC D
D
Y
A B
D
(d) AB CD C

11. The CMOS equivalent of the following nMOS gate (in

figure) is ______ (draw the circuit). (EC-GATE 1991)
+VDD

O/P

A C

12. If X1 and X2 are the inputs to the circuit as shown in the

below figure, then what is the output Q? (EC-GATE 2009)
VDD

Q
X1
X2

(a) X 1 X 2 (b) X1 X 2
(c) X 1 X2 (d) X1 X2

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13. If figure, T1, T2, and T3 are p-channel MOS transistors, and
T4, and T5 and T6 are n-channel MOS transistor. A, B are C
are binary signals. The output (A, B, C) is

VDD (JTO -2001)

(a) AB C
A T1
C
(b) A + BC T2 T3
B f
T4 T6
(c) A(B + C) A

C T5
(d) ABC

14. The logic function implemented by the following circuit at

he terminal OUT is (EC-GATE 2008)

(a) P NOR Q (b) P NAND Q

(c) P OR Q (d) P AND Q

15. For the NMOS logic gate sown in figure, the logic function
implemented is (EC-GATE 1997)
VDD

(a) ABCDE

(b) AB C . D E F

(c) A.B C D.E A D

(d) A B .C D. E B C E

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58 CNOS ACE

16. Write a Boolean expression for Z in terms of A, B, C, D and

E. You need not simplify the expression. (ISRO SET-2010)

(a) A B. D.E C
(d) A.B D. E .C
(c) A.B D E.C
(d) False

17. The circuit shown in fig. implements the function

+VDD

A B C +VDD

A B C
B Y

A A
B
B B

C C

(a) ABC ABC (b) ABC A B C

(c) ABC A B C (d) None of the above

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ACE CLASS ROOM PRACTICE QUESTIONS 59

18. Which of the following statements is true? A CMOS inverter

is made using (JTO -2002)
(a) Two NMOS transistors
(b) Two PMOS transistors
(c) One n-channel and one p-channel JFET
(d) Using one NMOS transistor and one PMOS transistor.

19. The voltage gain of basic CMOS is approximately

ISRO SET-2009)
(a) (gmro)/2 (b) 2gmro (c) 1/(2gmro) (d) 2ro/gm

20. Consider the following statements in connection with the

CMOS inverter in where both the MOSFETs are of
enhancement type and both have a threshold voltage of 2V.
Statement 1: T1 conducts when Vi 2V.
Statement 2: T1 is always in saturation when V0 = 0V

Which of the following is correct (EC-GATE 2003)

(a) Only statement 1 is TRUE
(b) Only statement 2 is TRUE
(c) Both the statements are TRUE
(d) Both the statements are FALSE

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21. A CMOS Inverter is shown below in

the figure
For Vin = Vout = 2.5, which one of the
following is true if the threshold
voltage of the NMOS transistor is 1V
and that of PMOS transistor is -1V.
(JTO -2001)

(a) NMOS is Linear region, PMOS in saturation

(b) NMOS in saturation region, POMS in saturation
(c) NMOS is saturation, POMS in linear region
(d) NMOS in Linear region, POMS in Linear region

22. Figure is the voltage transfer characteristic of

Vout (EC-GATE 2004)

Vin
0
(a) an NMOS inverter with enhancement mode transistor as
load
(b) an NMOS inverter with depletion mode transistor as load
(c) A CMOS inverter
(d) A BJT inverter

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23. In the CMOS inverter circuit shown, if the transconductance

parameters of the NMOS and PMOS transistor are
W W
K n K p n COX n PC ox , P 40 A / V 2 and
Ln LP
their threshold voltages are VTM = 1 V, the current I is.
(EC-GATE 2007)
5V
(a) 0A
(b) 25 A PMOS

(c) 45 A I
(d) 90 A 2.5V
NMOS

24. Assertion(A): For same drain current rating N-channel

MOSFET occupies more area than p-channel MOSFET.
Reason(R): Electron mobility is much higher than hole
mobility (EC-IES-2009)

(a) Both A and R are true and R is the correct explanation of A

(b) Both A and R are true but R is NOT a correct explanation
of A
(c) A is true but R is false
(d) A is false but R is true

25. In the CMOS circuit shown, electron and hole mobilities are
equal, and M1 and M2 are equally sized. The device M1 is
in the linear region if (EC-GATE 2012)
5V
(a) Vin < 1.875 V M1
(b) 1.875 V < Vin < 3.125 V | VTp | 1 V
Vin
(c) Vin > 3.125 V
VTn 1 V
(d) 0 < Vin < 5 V
M2

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26. In a CMOS CS amplifier, the active load is obtained by

connecting a (EC-IES 2009)
(a) p channel current mirror circuit
(b) n channel transistor
(c) p channel transistor
(d) BJT current mirror

27. For the ring oscillator shown in Figure the propagation delay
of each inverter is 100 pico second. What is the fundamental
frequency of the oscillator output? (EC-GATE 2001)
(a) 10 MHz
(b) 100 MHz V0
(c) 1 GHz
(d) 2 GHz

28. The threshold voltage for each transistor in Figure is 2V. For
this circuit to work as an inverter, Vi must take the values
(EC-GATE 1998)

Vi V0

-5V
(a) 5V and 0V (b) 5V and 5V
(c) 0V and 3V (d) 3V and 5V

29. Consider the following statements about CMOS:

1. CMOS logic inverter has maximum signal swing of 0V to

VDD
2. The output signal swing is independent of exact value of
aspect ratio and other device parameters.
3. It is a fast switching device with the noise margins.
4. It has zero input resistance and infinite output resistance.
Which of these statements are correct? (EC-IES 2011)
(a) 1, 2, 3 and 4 (b) 1, 2 and 4 only
(c) 2, 3 and 4 only (d) 1, 2 and 3 only

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30. A CMOS amplifier when compared to an N-channel

MOSFET, has the advantage of (EC-IES 2003)
(a) Higher cut-off frequency
(b) Higher voltage gain
(c) Higher current gain
(d) Lower current drain from the power supply, thereby less
dissipation
31. The threshold voltage for each transistor in the figure shown
above is 20V. What are the values of Vi for this circuit to
work as an inverter? (EC-IES 2008)

(a) 5V and 0V
(b) 5V and 5V V0
Vi
(c) 0V and 5V
(d) 3V and 3V

5V
32. Consider the following statements describing the property of
a complementary MOS (CMOS) inverter

1. It is a combination of an n-channel FET and a p-channel

FET
2. There is power dissipation when the input carries the
logical I signal.
3. There is no power dissipation when the input carries the
logical 0 signal.
4. There is power dissipation during transition from 0 to 1 or
from 1 to 0
Which of the statements given above are correct?
(EC-IES 2006)
(a) 1, 2 & 3 (b) 2, 3 & 4
(c) 1, 3 & 4 (d) 1, 2 & 4

33. The circuit shown in the given figure (EC-IES 2001)

(a) is an oscillating circuit and its output is a square wave

(b) is one whose output remains stable in 1 state
(c) is one whose output remains stable in0 state
(d) gives a single pulse of 3 times propagation delay

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64 CNOS ACE

34. In the CMOS inverter, the power dissipation is

(EE-IES 2001)
(a) Low only when VEN is low
(b) Low only when VEN is high
(c) High during dynamic operation
(d) Low during dynamic operation

35. The inverters in the ring oscillator circuit shown below are
identical. If the output waveform has a frequency of 10MHz,
the propagation delay pf each inverter is
output
(a) 5 ns
(b) 10 ns
(c) 20 ns
(d) 50 ns

36. A logic family has threshold voltage VT = 2V, minimum

guaranteed output high voltage VOH = 4V, minimum
accepted input high voltage VIH = 3V, maximum guaranteed
output low voltage VOL = 1V, and maximum accepted input
low voltage VIL = 1.5V; Its noise margin is

(a) 2V (b) 1V (c) 1.5V (d) 0.5V

37. Given that for a logic family,

VOH is the minimum output high-level voltage
VOL is the maximum output low-level voltage
VIH is the minimum acceptable input high-level voltage and
VIL is the maximum acceptable input low-level voltage
The correct relationship is:

a)VIH > VOH > VIL > VOL b) VOH > VIH > VIL > VOL
c) VIH > VOH > VOL > VIL d) VOH > VIH > VOL > VIL

38. In the following circuit employing pass transistor logic, all

NMOS transistors are identical with a Threshold voltage of
1V. Ignoring the body-effect, the output voltage at P, Q and
R are,

a) 4V, 3V, 2V b) 5V, 5V, 5V

c) 4V, 4V, 4V d) 5V, 4V, 3V

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39. The output (Y) of the circuit shown in the figure is

a) A B C
b) A B C A.C
c) A BC
d) A.B .C

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