Core Instructions

Programming Environments Manual
PowerPC RISC Microprocessor Family
addx addx
Add (x7C00 0214)
add rD,rA,rB (OE = 0 Rc = 0)

add. rD,rA,rB (OE = 0 Rc = 1)
addo rD,rA,rB (OE = 1 Rc = 0)
addo. rD,rA,rB (OE = 1 Rc = 1)
[POWER mnemonics: cax, cax., caxo, caxo.]
rD (rA) + (rB)
The sum (rA) + (rB) is placed into rD.
The add instruction is preferred for addition because it sets few status bits.
Other registers altered:

Condition Register (CR0 field):
Affected: LT, GT, EQ, SO (if Rc = 1)
Note: CR0 field may not reflect the infinitely precise result if overflow occurs (see XER below).
XER:
Affected: SO, OV (if OE = 1)
Note: The setting of the affected bits in the XER is mode-dependent, and reflects overflow of the 64-bit
result in 64-bit mode and overflow of the low-order 32-bit result in 32-bit mode. For further information
about 64-bit mode and 32-bit mode in 64-bit implementations, see 4.1.2 , Computation Modes.
PowerPC Architecture Level Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form
UISA XO
pem8.fm.2.0 Instruction Set

June 10, 2003 Page 377 of 785
addcx addcx
Add Carrying (x7C00 0014)
addc rD,rA,rB (OE = 0 Rc = 0)

addc. rD,rA,rB (OE = 0 Rc = 1)
addco rD,rA,rB (OE = 1 Rc = 0)
addco. rD,rA,rB (OE = 1 Rc = 1)
[POWER mnemonics: a, a., ao, ao.]
rD (rA) + (rB)
The sum (rA) + (rB) is placed into rD.

Affected: LT, GT, EQ, SO(if Rc = 1)
XER:
Affected: CA
Affected: SO, OV(if OE = 1)
UISA XO
Instruction Set pem8.fm.2.0

Page 378 of 785 June 10, 2003
addex addex
Add Extended (x7C00 0114)
adde rD,rA,rB (OE = 0 Rc = 0)

adde. rD,rA,rB (OE = 0 Rc = 1)
addeo rD,rA,rB (OE = 1 Rc = 0)
addeo. rD,rA,rB (OE = 1 Rc = 1)
[POWER mnemonics: ae, ae., aeo, aeo.]
rD (rA) + (rB) + XER[CA]

The sum (rA) + (rB) + XER[CA] is placed into rD.

XER:
Affected: CA
UISA XO

June 10, 2003 Page 379 of 785
addi addi
Add Immediate (x3800 0000)
addi rD,rA,SIMM
[POWER mnemonic: cal]
if rA = 0 then rD EXTS(SIMM)
else rD rA + EXTS(SIMM)
The sum (rA|0) + SIMM is placed into rD.
The addi instruction is preferred for addition because it sets few status bits. Note that addi uses the value 0,
not the contents of GPR0, if rA = 0.

None
Simplified mnemonics:
li rD,value equivalent to addi rD,0,value

la rD,disp(rA) equivalent to addi rD,rA,disp
subi rD,rA,value equivalent to addi rD,rA,value
UISA D

Page 380 of 785 June 10, 2003
addic addic
Add Immediate Carrying (x3000 0000)
addic rD,rA,SIMM
[POWER mnemonic: ai]
rD (rA) + EXTS(SIMM)
The sum (rA) + SIMM is placed into rD.

XER:
Affected: CA
subic rD,rA,valueequivalent toaddicrD,rA,value
UISA D

June 10, 2003 Page 381 of 785
addic. addic.
Add Immediate Carrying and Record (x3400 0000)
addic. rD,rA,SIMM
[POWER mnemonic: ai.]
rD (rA) + EXTS(SIMM)
The sum (rA) + SIMM is placed into rD.

Affected: LT, GT, EQ, SO
XER:
Affected: CA
subic.rD,rA,valueequivalent toaddic.rD,rA,value
UISA D

Page 382 of 785 June 10, 2003
addis addis
Add Immediate Shifted (x3C00 0000)
addis rD,rA,SIMM
[POWER mnemonic: cau]
if rA = 0 then rD EXTS(SIMM || (16)0)

else rD (rA) + EXTS(SIMM || (16)0)
The sum (rA|0) + (SIMM || 0x0000) is placed into rD.
The addis instruction is preferred for addition because it sets few status bits. Note that addis uses the value
0, not the contents of GPR0, if rA = 0.

None
lisrD,valueequivalent toaddisrD,0,value
subisrD,rA,valueequivalent toaddisrD,rA,value
UISA D

June 10, 2003 Page 383 of 785
addmex addmex
Add to Minus One Extended (x7C00 01D4)
addme rD,rA (OE = 0 Rc = 0)

addme. rD,rA (OE = 0 Rc = 1)
addmeo rD,rA (OE = 1 Rc = 0)
addmeo. rD,rA (OE = 1 Rc = 1)
[POWER mnemonics: ame, ame., ameo, ameo.]
rD (rA) + XER[CA] 1
The sum (rA) + XER[CA] + 0xFFFF_FFFF_FFFF_FFFF is placed into rD.

XER:
Affected: CA
UISA XO

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addzex addzex
Add to Zero Extended (x7C00 0194)
addze rD,rA (OE = 0 Rc = 0)

addze. rD,rA (OE = 0 Rc = 1)
addzeo rD,rA (OE = 1 Rc = 0)
addzeo. rD,rA (OE = 1 Rc = 1)
[POWER mnemonics: aze, aze., azeo, azeo.]
rD (rA) + XER[CA]
The sum (rA) + XER[CA] is placed into rD.

XER:
Affected: CA
UISA XO

June 10, 2003 Page 385 of 785
andx andx
AND (x7C00 0038)
and rA,rS,rB (Rc = 0)

and. rA,rS,rB (Rc = 1)
rA (rS) & (rB)

The contents of rS are ANDed with the contents of rB and the result is placed into rA.

UISA X

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andcx andcx
AND with Complement (x7C00 0078)
andc rA,rS,rB (Rc = 0)

andc. rA,rS,rB (Rc = 1)
rA (rS) + (rB)
The contents of rS are ANDed with the ones complement of the contents of rB and the result is placed into
rA.

UISA X

June 10, 2003 Page 387 of 785
andi. andi.
AND Immediate (x7000 0000)
andi. rA,rS,UIMM
[POWER mnemonic: andil.]
rA (rS) & ((4816)0 || UIMM)

The contents of rS are ANDed with 0x0000_0000_0000 || UIMM and the result is placed into rA.

UISA D

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andis. andis.
AND Immediate Shifted (x7400 0000)
andis. rA,rS,UIMM
[POWER mnemonic: andiu.]
rA (rS) + ((32)0 || UIMM || (16)0)

The contents of rS are ANDed with 0x0000_0000 || UIMM || 0x0000 and the result is placed into rA.

UISA D

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bx bx
Branch (x4800 0000)
b target_addr (AA = 0 LK = 0)
ba target_addr (AA = 1 LK = 0)
bl target_addr (AA = 0 LK = 1)
bla target_addr (AA = 1 LK = 1)
if AA then NIA iea EXTS(LI || 0b00)

else NIA iea CIA + EXTS(LI || 0b00)
if LK then LR iea CIA + 4
target_addr specifies the branch target address.
If AA = 0, then the branch target address is the sum of LI || 0b00 sign-extended and the address of this
instruction, with the high-order 32 bits of the branch target address cleared in 32-bit mode of 64-bit implemen-
tations.
If AA = 1, then the branch target address is the value LI || 0b00 sign-extended, with the high-order 32 bits of
the branch target address cleared in 32-bit mode of 64-bit implementations.
If LK = 1, then the effective address of the instruction following the branch instruction is placed into the link
register.
Affected: Link Register (LR)(if LK = 1)
UISA I

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bcx bcx
Branch Conditional (x4000 0000)
bc BO,BI,target_addr (AA = 0 LK = 0)
bca BO,BI,target_addr (AA = 1 LK = 0)
bcl BO,BI,target_addr (AA = 0 LK = 1)
bcla BO,BI,target_addr (AA = 1 LK = 1)
16 BO BI BD AA LK
0 5 6 10 11 15 16 29 30 31
if (64-bit implementation) & (64-bit mode)

then m 0
else m 32
if BO[2] then CTR CTR 1
ctr_ok BO[2] | ((CTR[m63] 0) BO[3])
cond_ok BO[0] | (CR[BI] BO[1])
if ctr_ok & cond_ok then
if AA then NIA iea EXTS(BD || 0b00)
else NIA iea CIA + EXTS(BD || 0b00)
The BI field specifies the bit in the condition register (CR) to be used as the condition of the branch. The BO
field is encoded as described in . Additional information about BO field encoding is provided in Section 4.2.4.2
Conditional Branch Control.
Table 8-6. BO Operand Encodings

BO Description
0000y Decrement the CTR, then branch if the decremented CTR[M63] 0 and the condition is FALSE.
0001y Decrement the CTR, then branch if the decremented CTR[M63] = 0 and the condition is FALSE.
001zy Branch if the condition is FALSE.
0100y Decrement the CTR, then branch if the decremented CTR[M63] 0 and the condition is TRUE.
0101y Decrement the CTR, then branch if the decremented CTR[M63] = 0 and the condition is TRUE.
011zy Branch if the condition is TRUE.
1z00y Decrement the CTR, then branch if the decremented CTR[M63] 0.
1z01y Decrement the CTR, then branch if the decremented CTR[M63] = 0.
1z1zz Branch always.

M = 32 in 32-bit mode, and M = 0 in the default 64-bit mode. If the BO field specifies that the CTR is to be decremented, the entire 64-
bit CTR is decremented regardless of the 32-bit mode or the default 64-bit mode.
In this table, z indicates a bit that is ignored.
Note that the z bits should be cleared, as they may be assigned a meaning in some future version of the PowerPC architecture.
The y bit provides a hint about whether a conditional branch is likely to be taken, and may be used by some PowerPC implementations
to improve performance.

June 10, 2003 Page 391 of 785
target_addr specifies the branch target address.
If AA = 0, the branch target address is the sum of BD || 0b00 sign-extended and the address of this instruc-
tion, with the high-order 32 bits of the branch target address cleared in 32-bit mode of 64-bit implementations.
If AA = 1, the branch target address is the value BD || 0b00 sign-extended, with the high-order 32 bits of the
branch target address cleared in 32-bit mode of 64-bit implementations.
If LK = 1, the effective address of the instruction following the branch instruction is placed into the link
register.
Affected: Count Register (CTR)(if BO[2] = 0)
blt target equivalent to bc 12,0,target

bne cr2,target equivalent to bc 4,10,target
bdnz target equivalent to bc 16,0,target
UISA B

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bcctrx bcctrx
Branch Conditional to Count Register (x4C00 0420)
bcctr BO,BI (LK = 0)

bcctrl BO,BI (LK = 1)
[POWER mnemonics: bcc, bccl]

if cond_ok then
NIA iea CTR[061] || 0b00
The BI field specifies the bit in the condition register to be used as the condition of the branch. The BO field is
encoded as described in . Additional information about BO field encoding is provided in Section 4.2.4.2 ,
Conditional Branch Control.
.

BO Description
The y bit provides a hint about whether a conditional branch is likely to be taken, and may be used by some PowerPC implementa-
tions to improve performance.
The branch target address is CTR[061] || 0b00, with the high-order 32 bits of the branch target address
cleared in 32-bit mode of 64-bit implementations.
If LK = 1, the effective address of the instruction following the branch instruction is placed into the link
register.
If the decrement and test CTR option is specified (BO[2] = 0), the instruction form is invalid.

June 10, 2003 Page 393 of 785
bltctr equivalent to bcctr 12,0

bnectr cr2 equivalent to bcctr 4,10
UISA XL

Page 394 of 785 June 10, 2003
bclrx bclrx
Branch Conditional to Link Register (x4C00 0020)
bclr BO,BI (LK = 0)

bclrl BO,BI (LK = 1)
[POWER mnemonics: bcr, bcrl]
if (64-bit implementation) & (64-bit mode)

then m 0
else m 32
if BO[2] then CTR CTR 1
ctr_ok BO[2] | ((CTR[m63] 0) BO[3])
if ctr_ok & cond_ok then
NIA iea LR[061] || 0b00
The BI field specifies the bit in the condition register to be used as the condition of the branch. The BO field is
encoded as described in Table 8-8. Additional information about BO field encoding is provided in
Section 4.2.4.2 Conditional Branch Control.

BO Description

The y bit provides a hint about whether a conditional branch is likely to be taken, and may be used by some PowerPC implementations
to improve performance.
The branch target address is LR[061] || 0b00, with the high-order 32 bits of the branch target address
cleared in 32-bit mode of 64-bit implementations.

June 10, 2003 Page 395 of 785
If LK = 1, then the effective address of the instruction following the branch instruction is placed into the link
register.
Affected: Count Register (CTR) (if BO[2] = 0)
Affected: Link Register (LR) (if LK = 1)
bltlr equivalent to bclr 12,0

bnelr cr2 equivalent to bclr 4,10
bdnzlr equivalent to bclr 16,0
UISA XL

Page 396 of 785 June 10, 2003
cmp cmp
Compare (x7C00 0000)
cmp crfD,L,rA,rB
if L = 0 then a EXTS(rA[3263])
b EXTS(rB[3263])
else a (rA)
b (rB)
if a b then c 0b010
else c 0b001
CR[4 crfD4 crfD + 3] c || XER[SO]
The contents of rA (or the low-order 32 bits of rA if L = 0) are compared with the contents of rB (or the low-
order 32 bits of rB if L = 0), treating the operands as signed integers. The result of the comparison is placed
into CR field crfD.
In 32-bit implementations, if L = 1 the instruction form is invalid.

Condition Register (CR field specified by operand crfD):
cmpd rA,rB equivalent to cmp 0,1,rA,rB

cmpw cr3,rA,rB equivalent to cmp 3,0,rA,rB
UISA X

June 10, 2003 Page 397 of 785
cmpi cmpi
Compare Immediate (x2C00 0000)
cmpi crfD,L,rA,SIMM
if L = 0 then a EXTS(rA[3263])
elsea (rA)
if a < EXTS(SIMM) then c 0b100
else if a > EXTS(SIMM) then c 0b010
else c 0b001
The contents of rA (or the low-order 32 bits of rA sign-extended to 64 bits if L = 0) are compared with the sign-
extended value of the SIMM field, treating the operands as signed integers. The result of the comparison is
placed into CR field crfD.

cmpdi rA,value equivalent to cmpi 0,1,rA,value

cmpwi cr3,rA,value equivalent to cmpi 3,0,rA,value
UISA D

Page 398 of 785 June 10, 2003
cmpl cmpl
Compare Logical (x7C00 0040)
cmpl crfD,L,rA,rB
if L = 0 then a (32)0 || rA[3263]

b (32)0 || rB[3263]
elsea (rA)
b (rB)
if a U b then c 0b010
else c 0b001
The contents of rA (or the low-order 32 bits of rA if L = 0) are compared with the contents of rB (or the low-
order 32 bits of rB if L = 0), treating the operands as unsigned integers. The result of the comparison is placed
into CR field crfD.

cmpld rA,rB equivalent to cmpl 0,1,rA,rB

cmplw cr3,rA,rB equivalent to cmpl 3,0,rA,rB
UISA X

June 10, 2003 Page 399 of 785
cmpli cmpli
Compare Logical Immediate (x2800 0000)
cmpli crfD,L,rA,UIMM
10 crfD 0 L A
if L = 0 then a (32)0 || rA[3263]

else a (rA)
if a U ((4816)0 || UIMM) then c 0b010
else c 0b001
The contents of rA (or the low-order 32 bits of rA zero-extended to 64-bits if L = 0) are compared with
0x0000_0000_0000 || UIMM, treating the operands as unsigned integers. The result of the comparison is
placed into CR field crfD.

cmpldi r A,value equivalent to cmpli 0,1,rA,value

cmplwi cr3,rA,value equivalent to cmpli 3,0,rA,value
UISA D

Page 400 of 785 June 10, 2003
cntlzdx 64-Bit Implementations Only cntlzdx

Count Leading Zeros Double Word (x7C00 0074)
cntlzd rA,rS (Rc = 0)

cntlzd. rA,rS (Rc = 1)
Reserved
31 S A 0000 0 58 Rc
0 5 6 10 11 15 16 20 21 30 31
n 0
do while n < 64
if rS[n] = 1 then leave
n n + 1
rA n
A count of the number of consecutive zero bits starting at bit 0 of register rS is placed into rA. This number
ranges from 0 to 64, inclusive.
This instruction is defined only for 64-bit implementations. Using it on a 32-bit implementation will cause the
system illegal instruction error handler to be invoked.

Affected: LT, GT, EQ, SO(Rc = 1)
Note: If Rc = 1, then LT is cleared in the CR0 field.
UISA X

June 10, 2003 Page 401 of 785
cntlzwx cntlzwx
Count Leading Zeros Word (x7C00 0034)
cntlzw rA,rS (Rc = 0)

cntlzw. rA,rS (Rc = 1)
[POWER mnemonics: cntlz, cntlz.]
Reserved
31 S A 0000 0 26 Rc
0 5 6 10 11 15 16 20 21 30 31
n 320
do while n < 6432
if rS[n] = 1 then leave
n n + 1
rA n 32
A count of the number of consecutive zero bits starting at bit 320 of rS (bit 0 in 32-bit implementations) is
placed into rA. This number ranges from 0 to 32, inclusive.

Note: If Rc = 1, then LT is cleared in the CR0 field.
UISA X

Page 402 of 785 June 10, 2003
crand crand
Condition Register AND (x4C00 0202)
crand crbD,crbA,crbB
CR[crbD] CR[crbA] & CR[crbB]

The bit in the condition register specified by crbA is ANDed with the bit in the condition register specified by
crbB. The result is placed into the condition register bit specified by crbD.

Condition Register:
Affected: Bit specified by operand crbD
UISA XL

June 10, 2003 Page 403 of 785
crandc crandc
Condition Register AND with Complement (x4C00 0102)
crandc crbD,crbA,crbB
Reserved
19 crbD crbA crbB 129 0
0 5 6 10 11 15 16 20 21 30 31
CR[crbD] CR[crbA] & CR[crbB]

The bit in the condition register specified by crbA is ANDed with the complement of the bit in the condition
register specified by crbB and the result is placed into the condition register bit specified by crbD.

Condition Register:
UISA XL

Page 404 of 785 June 10, 2003
creqv creqv
Condition Register Equivalent (x4C00 0242)
creqv crbD,crbA,crbB
Reserved

0 5 6 10 11 15 16 20 21 30 31
CR[crbD] CR[crbA] CR[crbB]

The bit in the condition register specified by crbA is XORed with the bit in the condition register specified by
crbB and the complemented result is placed into the condition register bit specified by crbD.

Condition Register:
crset crbD equivalent to creqv crbD,crbD,crbD
UISA XL

June 10, 2003 Page 405 of 785
crnand crnand
Condition Register NAND (x4C00 01C2)
crnand crbD,crbA,crbB
Reserved

0 5 6 10 11 15 16 20 21 30 31
CR[crbD] (CR[crbA] & CR[crbB])

The bit in the condition register specified by crbA is ANDed with the bit in the condition register specified by

Condition Register:
UISA XL

Page 406 of 785 June 10, 2003
crnor crnor
Condition Register NOR (x4C00 0042)
crnor crbD,crbA,crbB
Reserved
0 5 6 10 11 15 16 20 21 30 31
CR[crbD] (CR[crbA] | CR[crbB])

The bit in the condition register specified by crbA is ORed with the bit in the condition register specified by

Condition Register:
crnot crbD,crbA equivalent to crnor crbD,crbA,crbA
UISA XL

June 10, 2003 Page 407 of 785
cror cror
Condition Register OR (x4C00 0382)
cror crbD,crbA,crbB
Reserved

0 5 6 10 11 15 16 20 21 30 31
CR[crbD] CR[crbA] | CR[crbB]

The bit in the condition register specified by crbA is ORed with the bit in the condition register specified by
crbB. The result is placed into the condition register bit specified by crbD.

Condition Register:
crmove crbD,crbA equivalent to cror crbD,crbA,crbA
UISA XL

Page 408 of 785 June 10, 2003
crorc crorc
Condition Register OR with Complement (x4C00 0342)
crorc crbD,crbA,crbB
Reserved
0 5 6 10 11 15 16 20 21 30 31
CR[crbD] CR[crbA] | CR[crbB]

The bit in the condition register specified by crbA is ORed with the complement of the condition register bit
specified by crbB and the result is placed into the condition register bit specified by crbD.

Condition Register:
UISA XL

June 10, 2003 Page 409 of 785
crxor crxor
Condition Register XOR (x4C00 0182)
crxor crbD,crbA,crbB
Reserved
0 5 6 10 11 15 16 20 21 30 31
CR[crbD] CR[crbA] CR[crbB]

The bit in the condition register specified by crbA is XORed with the bit in the condition register specified by
crbB and the result is placed into the condition register specified by crbD.

Condition Register:
Affected: Bit specified by crbD
crclr crbD equivalent to crxor crbD,crbD,crbD
UISA XL

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dcba dcba
Data Cache Block Allocate (x7C00 05EC)
dcba rA,rB
Reserved
31 00 000 A B 758 0
0 5 6 10 11 15 16 20 21 30 31
EA is the sum (rA|0) + (rB).
The dcba instruction allocates the block in the data cache addressed by EA, by marking it valid without
reading the contents of the block from memory; the data in the cache block is considered to be undefined
after this instruction completes. This instruction is a hint that the program will probably soon store into a
portion of the block, but the contents of the rest of the block are not meaningful to the program (eliminating
the need to read the entire block from main memory), and can provide for improved performance in these
code sequences.
The dcba instruction executes as follows:

If the cache block containing the byte addressed by EA is in the data cache, the contents of all bytes are
made undefined but the cache block is still considered valid. Note that programming errors can occur if
the data in this cache block is subsequently read or used inadvertently.
If the cache block containing the byte addressed by EA is not in the data cache and the corresponding
memory page or block is caching-allowed, the cache block is allocated (and made valid) in the data
cache without fetching the block from main memory, and the value of all bytes is undefined.
If the addressed byte corresponds to a caching-inhibited page or block (i.e. if the I bit is set), this instruc-
tion is treated as a no-op.
If the cache block containing the byte addressed by EA is in coherency-required mode, and the cache
block exists in the data cache(s) of any other processor(s), it is kept coherent in those caches (i.e. the
processor performs the appropriate bus transactions to enforce this).
This instruction is treated as a store to the addressed byte with respect to address translation, memory
protection, referenced and changed recording and the ordering enforced by eieio or by the combination of
caching-inhibited and guarded attributes for a page (or block). However, the DSI exception is not invoked for
a translation or protection violation, and the referenced and changed bits need not be updated when the page
or block is cache-inhibited (causing the instruction to be treated as a no-op).
This instruction is optional in the PowerPC architecture.

None
In the PowerPC OEA, the dcba instruction is additionally defined to clear all bytes of a newly established
block to zero in the case that the block did not already exist in the cache.

June 10, 2003 Page 411 of 785
Additionally, as the dcba instruction may establish a block in the data cache without verifying that the associ-
ated physical address is valid, a delayed machine check exception is possible. See 6. , Exceptions, for a
discussion about this type of machine check exception.
VEA X

Page 412 of 785 June 10, 2003
dcbf dcbf
Data Cache Block Flush (x7C00 00AC)
dcbf rA,rB
Reserved
31 00 000 A B 86 0
0 5 6 10 11 15 16 20 21 30 31
The dcbf instruction invalidates the block in the data cache addressed by EA, copying the block to memory
first, if there is any dirty data in it. If the processor is a multiprocessor implementation (for example, the 601,
604,and 604e and 620) and the block is marked coherency-required, the processor will, if necessary, send an
address-only broadcast to other processors. The broadcast of the dcbf instruction causes another processor
to copy the block to memory, if it has dirty data, and then invalidate the block from the cache.
The action taken depends on the memory mode associated with the block containing the byte addressed by
EA and on the state of that block. The list below describes the action taken for the various states of the
memory coherency attribute (M bit).
Coherency required
Unmodified blockInvalidates copies of the block in the data caches of all processors.
Modified blockCopies the block to memory. Invalidates copies of the block in the data caches of all
processors.
Absent blockIf modified copies of the block are in the data caches of other processors, causes
them to be copied to memory and invalidated in those data caches. If unmodified copies are in the
data caches of other processors, causes those copies to be invalidated in those data caches.
Coherency not required
Unmodified blockInvalidates the block in the processors data cache.
Modified blockCopies the block to memory. Invalidates the block in the processors data cache.
Absent block (target block not in cache)No action is taken.
The function of this instruction is independent of the write-through, write-back and caching-inhibited/allowed
modes of the block containing the byte addressed by EA.
This instruction is treated as a load from the addressed byte with respect to address translation and memory
protection. It is also treated as a load for referenced and changed bit recording except that referenced and
changed bit recording may not occur.

None
VEA X

June 10, 2003 Page 413 of 785
dcbi dcbi
Data Cache Block Invalidate (x7C00 03AC)
dcbi rA,rB
Reserved
31 00 000 A B 470 0
0 5 6 10 11 15 16 20 21 30 31
The action taken is dependent on the memory mode associated with the block containing the byte addressed
by EA and on the state of that block. The list below describes the action taken if the block containing the byte
addressed by EA is or is not in the cache.
Coherency required
Unmodified blockInvalidates copies of the block in the data caches of all processors.
Modified blockInvalidates copies of the block in the data caches of all processors. (Discards the
modified contents.)
Absent blockIf copies of the block are in the data caches of any other processor, causes the copies
to be invalidated in those data caches. (Discards any modified contents.)
Coherency not required
Unmodified blockInvalidates the block in the processors data cache.
Modified blockInvalidates the block in the processors data cache. (Discards the modified con-
tents.)
Absent block (target block not in cache)No action is taken.
When data address translation is enabled, MSR[DR] = 1, and the virtual address has no translation, a DSI
exception occurs.
The function of this instruction is independent of the write-through and caching-inhibited/allowed modes of the
block containing the byte addressed by EA. This instruction operates as a store to the addressed byte with
respect to address translation and protection. The referenced and changed bits are modified appropriately.
This is a supervisor-level instruction.

None
OEA X

Page 414 of 785 June 10, 2003
dcbst dcbst
Data Cache Block Store (x7C00 006C)
dcbst rA,rB
Reserved
31 00 000 A B 54 0
0 5 6 10 11 15 16 20 21 30 31
The dcbst instruction executes as follows:

If the block containing the byte addressed by EA is in coherency-required mode, and a block containing
the byte addressed by EA is in the data cache of any processor and has been modified, the writing of it to
main memory is initiated.
If the block containing the byte addressed by EA is in coherency-not-required mode, and a block contain-
ing the byte addressed by EA is in the data cache of this processor and has been modified, the writing of
it to main memory is initiated.
The function of this instruction is independent of the write-through and caching-inhibited/allowed modes of the
block containing the byte addressed by EA.
The processor treats this instruction as a load from the addressed byte with respect to address translation
and memory protection. It is also treated as a load for referenced and changed bit recording except that refer-
enced and changed bit recording may not occur.

None
VEA X

June 10, 2003 Page 415 of 785
dcbt dcbt
Data Cache Block Touch (x7C00 022C)
dcbt rA,rB
Reserved
31 00 000 A B 278 0
0 5 6 10 11 15 16 20 21 30 31
This instruction is a hint that performance will possibly be improved if the block containing the byte addressed
by EA is fetched into the data cache, because the program will probably soon load from the addressed byte.
If the block is caching-inhibited, the hint is ignored and the instruction is treated as a no-op. Executing dcbt
does not cause the system alignment error handler to be invoked.
This instruction is treated as a load from the addressed byte with respect to address translation, memory
protection, and reference and change recording except that referenced and changed bit recording may not
occur. Additionally, no exception occurs in the case of a translation fault or protection violation.
The program uses the dcbt instruction to request a cache block fetch before it is actually needed by the
program. The program can later execute load instructions to put data into registers. However, the processor
is not obliged to load the addressed block into the data cache. Note that this instruction is defined architectur-
ally to perform the same functions as the dcbtst instruction. Both are defined in order to allow implementa-
tions to differentiate the bus actions when fetching into the cache for the case of a load and for a store.

None
VEA X

Page 416 of 785 June 10, 2003
dcbtst dcbtst
Data Cache Block Touch for Store (x7C00 01EC)
dcbtst rA,rB
Reserved
31 00 000 A B 246 0
0 5 6 10 11 15 16 20 21 30 31
This instruction is a hint that performance will possibly be improved if the block containing the byte addressed
by EA is fetched into the data cache, because the program will probably soon store from the addressed byte.
If the block is caching-inhibited, the hint is ignored and the instruction is treated as a no-op. Executing dcbtst
does not cause the system alignment error handler to be invoked.
This instruction is treated as a load from the addressed byte with respect to address translation, memory
protection, and reference and change recording except that referenced and changed bit recording may not
occur. Additionally, no exception occurs in the case of a translation fault or protection violation.
The program uses dcbtst to request a cache block fetch to potentially improve performance for a subsequent
store to that EA, as that store would then be to a cached location. However, the processor is not obliged to
load the addressed block into the data cache. Note that this instruction is defined architecturally to perform
the same functions as the dcbt instruction. Both are defined in order to allow implementations to differentiate
the bus actions when fetching into the cache for the case of a load and for a store.

None
VEA X

June 10, 2003 Page 417 of 785
dcbz dcbz
Data Cache Block Clear to Zero (x7C00 07EC)
dcbz rA,rB
[POWER mnemonic: dclz]
Reserved
31 00 000 A B 1014 0
0 5 6 10 11 15 16 20 21 30 31
The dcbz instruction executes as follows:

If the cache block containing the byte addressed by EA is in the data cache, all bytes are cleared.
If the cache block containing the byte addressed by EA is not in the data cache and the corresponding
memory page or block is caching-allowed, the cache block is allocated (and made valid) in the data
cache without fetching the block from main memory, and all bytes are cleared.
If the page containing the byte addressed by EA is in caching-inhibited or write-through mode, either all
bytes of main memory that correspond to the addressed cache block are cleared or the alignment excep-
tion handler is invoked. The exception handler can then clear all bytes in main memory that correspond to
the addressed cache block.
If the cache block containing the byte addressed by EA is in coherency-required mode, and the cache
block exists in the data cache(s) of any other processor(s), it is kept coherent in those caches (i.e. the
processor performs the appropriate bus transactions to enforce this).
This instruction is treated as a store to the addressed byte with respect to address translation, memory
protection, referenced and changed recording. It is also treated as a store with respect to the ordering
enforced by eieio and the ordering enforced by the combination of caching-inhibited and guarded attributes
for a page (or block).

None
The PowerPC OEA describes how the dcbz instruction may establish a block in the data cache without veri-
fying that the associated physical address is valid. This scenario can cause a delayed machine check excep-
tion; see 6. , Exceptions, for a discussion about this type of machine check exception.
VEA X

Page 418 of 785 June 10, 2003
divdx 64-Bit Implementations Only divdx

Divide Double Word (x7C00 03D2)
divd rD,rA,rB (OE = 0 Rc = 0)

divd. rD,rA,rB (OE = 0 Rc = 1)
divdo rD,rA,rB (OE = 1 Rc = 0)
divdo. rD,rA,rB (OE = 1 Rc = 1)
31 D A B OE 489 Rc
0 5 6 10 11 15 16 20 21 22 30 31
dividend[063] (rA)
divisor[063] (rB)
rD dividend + divisor
The 64-bit dividend is the contents of rA. The 64-bit divisor is the contents of rB. The 64-bit quotient is placed
into rD. The remainder is not supplied as a result.
Both the operands and the quotient are interpreted as signed integers. The quotient is the unique signed
integer that satisfies the equationdividend = (quotient divisor) + rwhere 0 r < |divisor| if the dividend is
non-negative, and |divisor| < r 0 if the dividend is negative.
If an attempt is made to perform the divisions0x8000_0000_0000_0000 1 or <anything> 0the

contents of rD are undefined, as are the contents of the LT, GT, and EQ bits of the CR0 field (if Rc = 1). In this
case, if OE = 1 then OV is set.
The 64-bit signed remainder of dividing (rA) by (rB) can be computed as follows, except in the case that (rA)
= 263 and (rB) = 1:
divd rD,rA,rB # rD = quotient

mulld rD,rD,rB # rD = quotient * divisor
subf rD,rD,rA # rD = remainder

XER:
Note: The setting of the affected bits in the XER is mode-independent, and reflects overflow of the 64-bit
result.
UISA XO

June 10, 2003 Page 419 of 785
divdux 64-Bit Implementations Only divdux

Divide Double Word Unsigned (x7C00 0392)
divdu rD,rA,rB (OE = 0 Rc = 0)

divdu. rD,rA,rB (OE = 0 Rc = 1)
divduo rD,rA,rB (OE = 1 Rc = 0)
divduo. rD,rA,rB (OE = 1 Rc = 1)
31 D A B OE 457 Rc
0 5 6 10 11 15 16 20 21 22 30 31
dividend[063] (rA)
divisor[063] (rB)
rD dividend + divisor
The 64-bit dividend is the contents of rA. The 64-bit divisor is the contents of rB. The 64-bit quotient of the
dividend and divisor is placed into rD. The remainder is not supplied as a result.
Both the operands and the quotient are interpreted as unsigned integers, except that if Rc is set to 1 the first
three bits of CR0 field are set by signed comparison of the result to zero. The quotient is the unique unsigned
integer that satisfies the equationdividend = (quotient divisor) + rwhere 0 r < divisor.
If an attempt is made to perform the division<anything> 0the contents of rD are undefined as are the
contents of the LT, GT, and EQ bits of the CR0 field (if Rc = 1). In this case, if OE = 1 then OV is set.
The 64-bit unsigned remainder of dividing (rA) by (rB) can be computed as follows:
divdu rD,rA,rB # rD = quotient

mulld rD,rD,rB # rD = quotient * divisor

XER:
result.
UISA XO

Page 420 of 785 June 10, 2003
divwx divwx
Divide Word (x7C00 03D6)
divw rD,rA,rB (OE = 0 Rc = 0)

divw. rD,rA,rB (OE = 0 Rc = 1)
divwo rD,rA,rB (OE = 1 Rc = 0)
divwo. rD,rA,rB (OE = 1 Rc = 1)
31 D A B OE 491 Rc
0 5 6 10 11 15 16 20 21 22 30 31
dividend[063] EXTS(rA[3263])
divisor[063] EXTS(rB[3263])
rD[3263] dividend divisor
rD[031] undefined
The 64-bit dividend is the sign-extended value of the contents of the low-order 32 bits of rA. The 64-bit divisor
is the sign-extended value of the contents of the low-order 32 bits of rB. The 6432-bit quotient is formed and
placed in rD. The low-order 32 bits of the 64-bit quotient are placed into the low-order 32 bits of rD. The
contents of the high-order 32 bits of rD are undefined. The remainder is not supplied as a result.
Both the operands and the quotient are interpreted as signed integers. The quotient is the unique signed
integer that satisfies the equationdividend = (quotient * divisor) + r where 0 r < |divisor| (if the dividend is
non-negative), and |divisor| < r 0 (if the dividend is negative).
If an attempt is made to perform either of the divisions0x8000_0000 1 or

<anything> 0, then the contents of rD are undefined, as are the contents of the LT, GT, and EQ bits of the
CR0 field (if Rc = 1). In this case, if OE = 1 then OV is set.
The 32-bit signed remainder of dividing the contents of the low-order 32 bits of rA by the contents of the low-
order 32 bits of rB can be computed as follows, except in the case that the contents of the low-order 32 bits of
rA = 231 and the contents of the low-order 32 bits of rB = 1.
divw rD,rA,rB # rD = quotient

mullw rD,rD,rB # rD = quotient divisor

LT, GT, EQ undefined(if Rc =1 and 64-bit mode)
XER:
Note: The setting of the affected bits in the XER is mode-independent, and reflects overflow of the low-
order 32-bit result.
UISA XO

June 10, 2003 Page 421 of 785
divwux divwux
Divide Word Unsigned (x7C00 0396)
divwu rD,rA,rB (OE = 0 Rc = 0)

divwu. rD,rA,rB (OE = 0 Rc = 1)
divwuo rD,rA,rB (OE = 1 Rc = 0)
divwuo. rD,rA,rB (OE = 1 Rc = 1)
31 D A B OE 459 Rc
0 5 6 10 11 15 16 20 21 22 30 31
dividend[063] (32)0 || (rA)[3263]

divisor[063] (32)0 || (rB)[3263]
rD[3263] dividend divisor
rD[031] undefined
The 64-bit dividend is the zero-extended value of the contents of the low-order 32 bits of rA. The 64-bit divisor
is the zero-extended value the contents of the low-order 32 bits of rB. A 6432-bit quotient is formed. The low-
order 32 bits of the 6432-bit quotient areis placed into the low-order 32 bits of rD. The contents of the high-
order 32 bits of rD are undefined. The remainder is not supplied as a result.
Both operands and the quotient are interpreted as unsigned integers, except that if Rc = 1 the first three bits
of CR0 field are set by signed comparison of the result to zero. The quotient is the unique unsigned integer
that satisfies the equationdividend = (quotient divisor) + r (where 0 r < divisor). If an attempt is made to
perform the division<anything> 0then the contents of rD are undefined as are the contents of the LT,
GT, and EQ bits of the CR0 field (if Rc = 1). In this case, if OE = 1 then OV is set.
The 32-bit unsigned remainder of dividing the contents of the low-order 32 bits of rA by the contents of the
low-order 32 bits of rB can be computed as follows:
divwurD,rA,rB# rD = quotient
mullw rD,rD,rB# rD = quotient divisor

XER:
UISA XO

Page 422 of 785 June 10, 2003
eciwx eciwx
External Control In Word Indexed (x7C00 026C)
eciwx rD,rA,rB
Reserved
31 D A B 310 0
0 5 6 10 11 15 16 20 21 30 31
The eciwx instruction and the EAR register can be very efficient when mapping special devices such as
graphics devices that use addresses as pointers.
if rA = 0 then b 0
else b (rA)
EA b + (rB)
paddr address translation of EA
send load word request for paddr to device identified by EAR[RID]
rD (32)0 || word from device
A load word request for the physical address (referred to as real address in the architecture specification)
corresponding to EA is sent to the device identified by EAR[RID], bypassing the cache. The word returned by
the device is placed in the low-order 32 bits of rD. The contents of the high-order 32 bits of rD are cleared.
EAR[E] must be 1. If it is not, a DSI exception is generated.
EA must be a multiple of four. If it is not, one of the following occurs:

A system alignment exception is generated.
A DSI exception is generated (possible only if EAR[E] = 0).
The results are boundedly undefined.
The eciwx instruction is supported for EAs that reference memory segments in which SR[T] = 1 (or STE[T] =
1) and for EAs mapped by the DBAT registers. If the EA references a direct-store segment (SR[T] = 1 or
STE[T] = 1), either a DSI exception occurs or the results are boundedly undefined. However, note that the
direct-store facility is being phased out of the architecture and will not likely be supported in future devices.
Thus, software should not depend on its effects.
If this instruction is executed when MSR[DR] = 0 (real addressing mode), the results are boundedly unde-
fined. This instruction is treated as a load from the addressed byte with respect to address translation,
memory protection, referenced and changed bit recording, and the ordering performed by eieio. This instruc-
tion is optional in the PowerPC architecture.

None
VEA X

June 10, 2003 Page 423 of 785
ecowx ecowx
External Control Out Word Indexed (x7C00 036C)
ecowx rS,rA,rB
Reserved
31 S A B 438 0
0 5 6 10 11 15 16 20 21 30 31
The ecowx instruction and the EAR register can be very efficient when mapping special devices such as
graphics devices that use addresses as pointers.
if rA = 0 then b 0
else b (rA)
EA b + (rB)
paddr address translation of EA
send store word request for paddr to device identified by EAR[RID]
send rS[3263] to device
A store word request for the physical address corresponding to EA and the contents of the low-order 32 bits
of rS are sent to the device identified by EAR[RID], bypassing the cache.
EAR[E] must be 1, if it is not, a DSI exception is generated. EA must be a multiple of four. If it is not, one of
the following occurs:
A system alignment exception is generated.
A DSI exception is generated (possible only if EAR[E] = 0).
The ecowx instruction is supported for effective addresses that reference memory segments in which SR[T]
= 0 (or STE[T] = 0), and for EAs mapped by the DBAT registers. If the EA references a direct-store segment
(SR[T] = 1 or STE[T] = 1), either a DSI exception occurs or the results are boundedly undefined. However,
note that the direct-store facility is being phased out of the architecture and will not likely be supported in
future devices. Thus, software should not depend on its effects.
If this instruction is executed when MSR[DR] = 0 (real addressing mode), the results are boundedly unde-
fined. This instruction is treated as a store from the addressed byte with respect to address translation,
memory protection, and referenced and changed bit recording, and the ordering performed by eieio. Note
that software synchronization is required in order to ensure that the data access is performed in program
order with respect to data accesses caused by other store or ecowx instructions, even though the addressed
byte is assumed to be caching-inhibited and guarded. This instruction is optional in the PowerPC architec-
ture.

None
VEA X

Page 424 of 785 June 10, 2003
eieio eieio
Enforce In-Order Execution of I/O (x7C00 06AC)
Reserved
31 00 000 0 0000 0000 0 854 0

0 5 6 10 11 15 16 20 21 30 31
The eieio instruction provides an ordering function for the effects of load and store instructions executed by a
processor. These loads and stores are divided into two sets, which are ordered separately. The memory
accesses caused by a dcbz or a dcba instruction are ordered like a store. The two sets follow:
1. Loads and stores to memory that is both caching-inhibited and guarded, and stores to memory that is
write-through required.
The eieio instruction controls the order in which the accesses are performed in main memory. It ensures
that all applicable memory accesses caused by instructions preceding the eieio instruction have com-
pleted with respect to main memory before any applicable memory accesses caused by instructions fol-
lowing the eieio instruction access main memory. It acts like a barrier that flows through the memory
queues and to main memory, preventing the reordering of memory accesses across the barrier. No
ordering is performed for dcbz if the instruction causes the system alignment error handler to be invoked.
All accesses in this set are ordered as a single setthat is, there is not one order for loads and stores to
caching-inhibited and guarded memory and another order for stores to write-through required memory.
Stores to memory that have all of the following attributescaching-allowed, write-through not required,
and memory-coherency required.
The eieio instruction controls the order in which the accesses are performed with respect to coherent
memory. It ensures that all applicable stores caused by instructions preceding the eieio instruction have
completed with respect to coherent memory before any applicable stores caused by instructions following
the eieio instruction complete with respect to coherent memory.
With the exception of dcbz and dcba, eieio does not affect the order of cache operations (whether caused
explicitly by execution of a cache management instruction, or implicitly by the cache coherency mechanism).
For more information, refer to 5. , Cache Model and Memory Coherency. The eieio instruction does not
affect the order of accesses in one set with respect to accesses in the other set.
The eieio instruction may complete before memory accesses caused by instructions preceding the eieio
instruction have been performed with respect to main memory or coherent memory as appropriate.
The eieio instruction is intended for use in managing shared data structures, in accessing memory-mapped
I/O, and in preventing load/store combining operations in main memory. For the first use, the shared data
structure and the lock that protects it must be altered only by stores that are in the same set (1 or 2; see
previous discussion). For the second use, eieio can be thought of as placing a barrier into the stream of
memory accesses issued by a processor, such that any given memory access appears to be on the same
side of the barrier to both the processor and the I/O device.
Because the processor performs store operations in order to memory that is designated as both caching-
inhibited and guarded (refer to Section 5.1.1 , Memory Access Ordering), the eieio instruction is needed for
such memory only when loads must be ordered with respect to stores or with respect to other loads.

June 10, 2003 Page 425 of 785
Note that the eieio instruction does not connect hardware considerations to it such as multiprocessor imple-
mentations that send an eieio address-only broadcast (useful in some designs). For example, if a design has
an external buffer that re-orders loads and stores for better bus efficiency, the eieio broadcast signals to that
buffer that previous loads/stores (marked caching-inhibited, guarded, or write-through required) must
complete before any following loads/stores (marked caching-inhibited, guarded, or write-through required).

None
VEA X

Page 426 of 785 June 10, 2003
eqvx eqvx
Equivalent (x7C00 0238)
eqv rA,rS,rB (Rc = 0)

eqv. rA,rS,rB (Rc = 1)
31 S A B 284 Rc
0 5 6 10 11 15 16 21 22 30 31
rA (rS) (rB)
The contents of rS are XORed with the contents of rB and the complemented result is placed into rA.

UISA X

June 10, 2003 Page 427 of 785
extsbx extsbx
Extend Sign Byte (x7C00 0774)
extsb rA,rS (Rc = 0)

extsb. rA,rS (Rc = 1)
Reserved
31 S A 0000 0 954 Rc
0 5 6 10 11 15 16 20 21 30 31
S rS[5624]
rA[566324-31] rS[566324-31]
rA[05523] (5624)S
The contents of the low-order eight bits of rS[24-31] are placed into the low-order eight bits of rA[24-31]. Bit
5624 of rS is placed into the remaining bits of rA[0-23].

UISA X

Page 428 of 785 June 10, 2003
extshx extshx
Extend Sign Half Word (x7C00 0734)
extsh rA,rS (Rc = 0)

extsh. rA,rS (Rc = 1)
[POWER mnemonics: exts, exts.]
Reserved
31 S A 0000 0 922 Rc
0 5 6 10 11 15 16 20 21 30 31
S rS[4816]
rA[486316-31] rS[486316-31]
rA[0470-15] (4816)S
The contents of the low-order 16 bits of rS[16-31] are placed into the low-order 16 bits of rA[16-31]. Bit 4816
of rS is placed into the remaining bits of rA[015].

UISA X

June 10, 2003 Page 429 of 785
extswx 64-Bit Implementations Only extswx

Extend Sign Word (x7C00 07B4)
extsw rA,rS (Rc = 0)

extsw. rA,rS (Rc = 1)
Reserved
31 S A 0000 0 986 Rc
0 5 6 10 11 15 16 20 21 30 31
S rS[32]
rA[3263] rS[3263]
rA[031] (32)S
The contents of the low-order 32 bits of rS are placed into the low-order 32 bits of rA. Bit 32 of rS is placed
into the high-order 32 bits of rA.

UISA X

Page 430 of 785 June 10, 2003
fabsx fabsx
Floating Absolute Value (xFC00 0210)
fabs frD,frB (Rc = 0)

fabs. frD,frB (Rc = 1)
Reserved
63 D 0 0000 B 264 Rc
0 5 6 10 11 15 16 20 21 30 31
The contents of frB with bit 0 cleared are placed into frD.
Note that the fabs instruction treats NaNs just like any other kind of value. That is, the sign bit of a NaN may
be altered by fabs. This instruction does not alter the FPSCR.

Affected: FX, FEX, VX, OX(if Rc = 1)
UISA X

June 10, 2003 Page 431 of 785
faddx faddx
Floating Add (Double-Precision) (xFC00 002A)
fadd frD,frA,frB (Rc = 0)

fadd. frD,frA,frB (Rc = 1)
[POWER mnemonics: fa, fa.]
B 000 00 21 Rc
The floating-point operand in frA is added to the floating-point operand in frB. If the most- significant bit of the
resultant significand is not a one, the result is normalized. The result is rounded to double-precision under
control of the floating-point rounding control field RN of the FPSCR and placed into frD.
Floating-point addition is based on exponent comparison and addition of the two significands. The exponents
of the two operands are compared, and the significand accompanying the smaller exponent is shifted right,
with its exponent increased by one for each bit shifted, until the two exponents are equal. The two signifi-
cands are then added or subtracted as appropriate, depending on the signs of the operands. All 53 bits in the
significand as well as all three guard bits (G, R, and X) enter into the computation.
If a carry occurs, the sum's significand is shifted right one bit position and the exponent is increased by one.
FPSCR[FPRF] is set to the class and sign of the result, except for invalid operation exceptions when
FPSCR[VE] = 1.

Affected: FX, FEX, VX, OX (if Rc = 1)

Floating-Point Status and Control Register:
Affected: FPRF, FR, FI, FX, OX, UX, XX,VXSNAN, VXISI
UISA A

Page 432 of 785 June 10, 2003
faddsx faddsx
Floating Add Single (xEC00 002A)
fadds frD,frA,frB (Rc = 0)

fadds. frD,frA,frB (Rc = 1)
Reserved
59 D A B 000 00 21 Rc
0 5 6 10 11 15 16 20 21 25 26 30 31
The floating-point operand in frA is added to the floating-point operand in frB. If the most-significant bit of the
resultant significand is not a one, the result is normalized. The result is rounded to the single-precision under
control of the floating-point rounding control field RN of the FPSCR and placed into frD.
Floating-point addition is based on exponent comparison and addition of the two significands. The exponents
of the two operands are compared, and the significand accompanying the smaller exponent is shifted right,
with its exponent increased by one for each bit shifted, until the two exponents are equal. The two signifi-
cands are then added or subtracted as appropriate, depending on the signs of the operands. All 53 bits in the
significand as well as all three guard bits (G, R, and X) enter into the computation.
If a carry occurs, the sum's significand is shifted right one bit position and the exponent is increased by one.
FPSCR[VE] = 1.


Affected: FPRF, FR, FI, FX, OX, UX, XX,VXSNAN, VXISI
UISA A

June 10, 2003 Page 433 of 785
fcfidx 64-Bit Implementations Only fcfidx

Floating Convert from Integer Double Word (xFC00 069C)
fcfid frD,frB (Rc = 0)

fcfid. frD,frB (Rc = 1)
Reserved
63 D 0 0000 B 846 Rc
0 5 6 10 11 15 16 20 21 30 31
The 64-bit signed fixed-point operand in register frB is converted to an infinitely precise floating-point integer.
The result of the conversion is rounded to double-precision using the rounding mode specified by
FPSCR[RN] and placed into register frD.
FPSCR[FPRF] is set to the class and sign of the result. FPSCR[FR] is set if the result is incremented when
rounded. FPSCR[FI] is set if the result is inexact.
The conversion is described fully in Section D.4.3 , Floating-Point Convert from Integer Model.

Affected: FX, VX, FEX, OX(if Rc = 1)

Floating-point Status and Control Register:
Affected: FPRF, FR, FI, FX, XX
UISA X

Page 434 of 785 June 10, 2003
fcmpo fcmpo
Floating Compare Ordered (xFC00 0040)
fcmpo crfD,frA,frB
Reserved
63 crfD 00 A B 32 0
0 5 6 8 9 10 11 15 16 20 21 30 31
if (frA) is a NaN or
(frB) is a NaN then c 0b0001
else if (frA)< (frB) then c 0b1000
else if (frA)> (frB) then c 0b0100
else c 0b0010
FPCC c
CR[4 crfD4 crfD + 3] c
if (frA) is an SNaN or
(frB) is an SNaN then
VXSNAN 1
if VE = 0 then VXVC 1
else if (frA) is a QNaN or
(frB) is a QNaN then VXVC 1
The floating-point operand in frA is compared to the floating-point operand in frB. The result of the compare is
placed into CR field crfD and the FPCC.
If one of the operands is a NaN, either quiet or signaling, then CR field crfD and the FPCC are set to reflect
unordered. If one of the operands is a signaling NaN, then VXSNAN is set, and if invalid operation is disabled
(VE = 0) then VXVC is set. Otherwise, if one of the operands is a QNaN, then VXVC is set.

Affected: LT, GT, EQ, UN

Affected: FPCC, FX, VXSNAN, VXVC
UISA X

June 10, 2003 Page 435 of 785
fcmpu fcmpu
Floating Compare Unordered (xFC00 0000)
fcmpu crfD,frA,frB
Reserved
63 crfD 00 A B 0000000000 0
0 5 6 8 9 10 11 15 16 20 21 30 31
if (frA) is a NaN or
(frB) is a NaN then c 0b0001
else if (frA) < (frB) then c 0b1000
else if (frA) > (frB) then c 0b0100
else c 0b0010
FPCC c
CR[4 crfD4 crfD + 3] c
if (frA) is an SNaN or
(frB) is an SNaN then
VXSNAN 1
The floating-point operand in register frA is compared to the floating-point operand in register frB. The result
of the compare is placed into CR field crfD and the FPCC.
If one of the operands is a NaN, either quiet or signaling, then CR field crfD and the FPCC are set to reflect
unordered. If one of the operands is a signaling NaN, then VXSNAN is set.

Affected: LT, GT, EQ, UN

Affected: FPCC, FX, VXSNAN
UISA X

Page 436 of 785 June 10, 2003
fctidx 64-Bit Implementations Only fctidx

Floating Convert to Integer Double Word (xFC00 065C)
fctid frD,frB (Rc = 0)

fctid. frD,frB (Rc = 1)
Reserved
63 D 0 0000 B 814 Rc
0 5 6 10 11 15 16 20 21 30 31
The floating-point operand in frB is converted to a 64-bit signed fixed-point integer, using the rounding mode
specified by FPSCR[RN], and placed into frD.
If the operand in frB is greater than 263 1, then frD is set to 0x7FFF_FFFF_FFFF_FFFF. If the operand in
frB is less than 263, then frD is set to 0x8000_0000_0000_0000.
Except for enabled invalid operation exceptions, FPSCR[FPRF] is undefined. FPSCR[FR] is set if the result is
incremented when rounded. FPSCR[FI] is set if the result is inexact.
The conversion is described fully in Section D.4.2 , Floating-Point Convert to Integer Model.


Affected: FPRF (undefined), FR, FI, FX, XX, VXSNAN, VXCVI
UISA X

June 10, 2003 Page 437 of 785
fctidzx 64-Bit Implementations Only fctidzx

Floating Convert to Integer Double Word with Round toward Zero (xFC00 065E)
fctidz frD,frB (Rc = 0)

fctidz. frD,frB (Rc = 1)
Reserved
63 D 0 0000 B 815 Rc
0 5 6 10 11 15 16 20 21 30 31
The floating-point operand in frB is converted to a 64-bit signed fixed-point integer, using the rounding mode
round toward zero, and placed into frD.
If the operand in frB is greater than 263 1, then frD is set to 0x7FFF_FFFF_FFFF_FFFF. If the operand in
frB is less than 263, then frD is set to 0x8000_0000_0000_0000.
Except for enabled invalid operation exceptions, FPSCR[FPRF] is undefined. FPSCR[FR] is set if the result is
incremented when rounded. FPSCR[FI] is set if the result is inexact.


UISA X

Page 438 of 785 June 10, 2003
fctiwx fctiwx
Floating Convert to Integer Word (xFC00 001C)
fctiw frD,frB (Rc = 0)

fctiw. frD,frB (Rc = 1)
Reserved
63 D 0 0000 B 14 Rc
0 5 6 10 11 15 16 20 21 30 31
The floating-point operand in register frB is converted to a 32-bit signed integer, using the rounding mode
specified by FPSCR[RN], and placed in bits 3263 of frD. Bits 031 of frD are undefined.
If the operand in frB are greater than 231 1, bits 3263 of frD are set to 0x7FFF_FFFF.
If the operand in frB are less than 231, bits 3263 of frD are set to 0x8000_0000.
Except for trap-enabled invalid operation exceptions, FPSCR[FPRF] is undefined. FPSCR[FR] is set if the
result is incremented when rounded. FPSCR[FI] is set if the result is inexact.


UISA X

June 10, 2003 Page 439 of 785
fctiwzx fctiwzx
Floating Convert to Integer Word with Round toward Zero (xFC00 001E)
fctiwz frD,frB (Rc = 0)

fctiwz. frD,frB (Rc = 1)
Reserved
63 D 0 0000 B 15 Rc
0 5 6 10 11 15 16 20 21 30 31
The floating-point operand in register frB is converted to a 32-bit signed integer, using the rounding mode
round toward zero, and placed in bits 3263 of frD. Bits 031 of frD are undefined.
If the operand in frB is greater than 231 1, bits 3263 of frD are set to 0x7FFF_FFFF.
If the operand in frB is less than 231, bits 3263 of frD are set to 0x 8000_0000.
Except for trap-enabled invalid operation exceptions, FPSCR[FPRF] is undefined. FPSCR[FR] is set if the
result is incremented when rounded. FPSCR[FI] is set if the result is inexact.


UISA X

Page 440 of 785 June 10, 2003
fdivx fdivx
Floating Divide (Double-Precision) (xFC00 0024)
fdiv frD,frA,frB (Rc = 0)

fdiv. frD,frA,frB (Rc = 1)
[POWER mnemonics: fd, fd.]
Reserved
63 D A B 000 00 18 Rc
0 5 6 10 11 15 16 20 21 25 26 30 31
The floating-point operand in register frA is divided by the floating-point operand in register frB. The
remainder is not supplied as a result.
If the most-significant bit of the resultant significand is not a one, the result is normalized. The result is
rounded to double-precision under control of the floating-point rounding control field RN of the FPSCR and
placed into frD.
Floating-point division is based on exponent subtraction and division of the significands.
FPSCR[VE] = 1 and zero divide exceptions when FPSCR[ZE] = 1.


Affected: FPRF, FR, FI, FX, OX, UX, ZX, XX, VXSNAN, VXIDI, VXZDZ
UISA A

June 10, 2003 Page 441 of 785
fdivsx fdivsx
Floating Divide Single (xEC00 0024)
fdivs frD,frA,frB (Rc = 0)

fdivs. frD,frA,frB (Rc = 1)
Reserved
59 D A B 000 00 18 Rc
0 5 6 10 11 15 16 20 21 25 26 30 31
The floating-point operand in register frA is divided by the floating-point operand in register frB. The
remainder is not supplied as a result.
rounded to single-precision under control of the floating-point rounding control field RN of the FPSCR and
placed into frD.
Floating-point division is based on exponent subtraction and division of the significands.


Affected: FPRF, FR, FI, FX, OX, UX, ZX, XX, VXSNAN, VXIDI, VXZDZ
UISA A

Page 442 of 785 June 10, 2003
fmaddx fmaddx
Floating Multiply-Add (Double-Precision) (xFC00 003A)
fmadd frD,frA,frC,frB (Rc = 0)

fmadd. frD,frA,frC,frB (Rc = 1)
[POWER mnemonics: fma, fma.]
63 D A B C 29 Rc
0 5 6 10 11 15 16 20 21 25 26 30 31
The following operation is performed:

frD (frA frC) + frB
The floating-point operand in register frA is multiplied by the floating-point operand in register frC. The
floating-point operand in register frB is added to this intermediate result.
placed into frD.
FPSCR[VE] = 1.


Affected: FPRF, FR, FI, FX, OX, UX, XX, VXSNAN, VXISI, VXIMZ
UISA A

June 10, 2003 Page 443 of 785
fmaddsx fmaddsx
Floating Multiply-Add Single (xEC00 003A)
fmadds frD,frA,frC,frB (Rc = 0)

fmadds. frD,frA,frC,frB (Rc = 1)
59 D A B C 29 Rc
0 5 6 10 11 15 16 20 21 25 26 30 31

frD (frA frC) + frB
floating-point operand in register frB is added to this intermediate result.
placed into frD.
FPSCR[VE] = 1.


UISA A

Page 444 of 785 June 10, 2003
fmrx fmrx
Floating Move Register (Double-Precision) (xFC00 0090)
fmr frD,frB (Rc = 0)

fmr. frD,frB (Rc = 1)
Reserved
63 D 0 0000 B 72 Rc
0 5 6 10 11 15 16 20 21 30 31
frD (frB)
The contents of register frB are placed into frD.

UISA X

June 10, 2003 Page 445 of 785
fmsubx fmsubx
Floating Multiply-Subtract (Double-Precision) xFC00 0038)
fmsub frD,frA,frC,frB (Rc = 0)

fmsub. frD,frA,frC,frB (Rc = 1)
[POWER mnemonics: fms, fms.]
63 D A B C 28 Rc
0 5 6 10 11 15 16 20 21 25 26 30 31
frD [frA frC] frB

floating-point operand in register frB is subtracted from this intermediate result.
placed into frD.
FPSCR[VE] = 1.


UISA A

Page 446 of 785 June 10, 2003
fmsubsx fmsubsx
Floating Multiply-Subtract Single (xEC00 0038)
fmsubs frD,frA,frC,frB (Rc = 0)

fmsubs. frD,frA,frC,frB (Rc = 1)
59 D A B C 28 Rc
0 5 6 10 11 15 16 20 21 25 26 30 31
frD [frA frC] frB

placed into frD.
FPSCR[VE] = 1.


UISA A

June 10, 2003 Page 447 of 785
fmulx fmulx
Floating Multiply (Double-Precision) (xFC00 0032)
fmul frD,frA,frC (Rc = 0)

fmul. frD,frA,frC (Rc = 1)
[POWER mnemonics: fm, fm.]
Reserved
63 D A 0000 0 C 25 Rc
0 5 6 10 11 15 16 20 21 25 26 30 31
The floating-point operand in register frA is multiplied by the floating-point operand in register frC.
placed into frD.
Floating-point multiplication is based on exponent addition and multiplication of the significands.
FPSCR[VE] = 1.


Affected: FPRF, FR, FI, FX, OX, UX, XX, VXSNAN, VXIMZ
UISA A

Page 448 of 785 June 10, 2003
fmulsx fmulsx
Floating Multiply Single (xEC00 0032)
fmuls frD,frA,frC (Rc = 0)

fmuls. frD,frA,frC (Rc = 1)
Reserved
59 D A 0000 0 C 25 Rc
0 5 6 10 11 15 16 20 21 25 26 30 31
The floating-point operand in register frA is multiplied by the floating-point operand in register frC.
placed into frD.
Floating-point multiplication is based on exponent addition and multiplication of the significands.
FPSCR[VE] = 1.


Affected: FPRF, FR, FI, FX, OX, UX, XX, VXSNAN, VXIMZ
UISA A

June 10, 2003 Page 449 of 785
fnabsx fnabsx
Floating Negative Absolute Value (xFC00 0110)
fnabs frD,frB (Rc = 0)

fnabs. frD,frB (Rc = 1)
Reserved
63 D 0 0000 B 136 Rc
0 5 6 10 11 15 16 20 21 25 26 30 31
The contents of register frB with bit 0 set are placed into frD.
Note that the fnabs instruction treats NaNs just like any other kind of value. That is, the sign bit of a NaN may
be altered by fnabs. This instruction does not alter the FPSCR.

UISA X

Page 450 of 785 June 10, 2003
fnegx fnegx
Floating Negate (xFC00 0050)
fneg frD,frB (Rc = 0)

fneg. frD,frB (Rc = 1)
Reserved
63 D 0 0000 B 40 Rc
0 5 6 10 11 15 16 20 21 30 31
The contents of register frB with bit 0 inverted are placed into frD.
Note that the fneg instruction treats NaNs just like any other kind of value. That is, the sign bit of a NaN may
be altered by fneg. This instruction does not alter the FPSCR.

UISA X

June 10, 2003 Page 451 of 785
fnmaddx fnmaddx
Floating Negative Multiply-Add (Double-Precision) (xFC00 003E)
fnmadd frD,frA,frC,frB (Rc = 0)

fnmadd. frD,frA,frC,frB (Rc = 1)
[POWER mnemonics: fnma, fnma.]
63 D A B C 31 Rc
0 5 6 10 11 15 16 20 21 25 26 30 31
frD ([frA frC] + frB)

floating-point operand in register frB is added to this intermediate result. If the most-significant bit of the
resultant significand is not a one, the result is normalized. The result is rounded to double-precision under
control of the floating-point rounding control field RN of the FPSCR, then negated and placed into frD.
This instruction produces the same result as would be obtained by using the Floating Multiply-Add (fmaddx)
instruction and then negating the result, with the following exceptions:
QNaNs propagate with no effect on their sign bit.
QNaNs that are generated as the result of a disabled invalid operation exception have a sign bit of zero.
SNaNs that are converted to QNaNs as the result of a disabled invalid operation exception retain the sign
bit of the SNaN.
FPSCR[VE] = 1.


UISA A

Page 452 of 785 June 10, 2003
fnmaddsx fnmaddsx
Floating Negative Multiply-Add Single (xEC00 003E)
fnmadds frD,frA,frC,frB (Rc = 0)

fnmadds. frD,frA,frC,frB (Rc = 1)
59 D A B C 31 Rc
0 5 6 10 11 15 16 20 21 25 26 30 31
frD ([frA frC] + frB)

floating-point operand in register frB is added to this intermediate result. If the most-significant bit of the
resultant significand is not a one, the result is normalized. The result is rounded to single-precision under
control of the floating-point rounding control field RN of the FPSCR, then negated and placed into frD.
This instruction produces the same result as would be obtained by using the Floating Multiply-Add Single
(fmaddsx) instruction and then negating the result, with the following exceptions:
bit of the SNaN.
FPSCR[VE] = 1.


UISA A

June 10, 2003 Page 453 of 785
fnmsubx fnmsubx
Floating Negative Multiply-Subtract (Double-Precision) (xFC00 003C)
fnmsub frD,frA,frC,frB (Rc = 0)

fnmsub. frD,frA,frC,frB (Rc = 1)
[POWER mnemonics: fnms, fnms.]
63 D A B C 30 Rc
0 5 6 10 11 15 16 20 21 25 26 30 31
frD ([frA frC] frB)

If the most-significant bit of the resultant significand is not one, the result is normalized. The result is rounded
to double-precision under control of the floating-point rounding control field RN of the FPSCR, then negated
and placed into frD.
This instruction produces the same result obtained by negating the result of a Floating Multiply-Subtract
(fmsubx) instruction with the following exceptions:
bit of the SNaN.
FPSCR[VE] = 1.

Condition Register (CR1 field)

UISA A

Page 454 of 785 June 10, 2003
fnmsubsx fnmsubsx
Floating Negative Multiply-Subtract Single (xEC00 003C)
fnmsubs frD,frA,frC,frB (Rc = 0)

fnmsubs. frD,frA,frC,frB (Rc = 1)
)
59 D A B C 30 Rc
0 5 6 10 11 15 16 20 21 25 26 30 31
frD ([frA frC] frB)

If the most-significant bit of the resultant significand is not one, the result is normalized. The result is rounded
to single-precision under control of the floating-point rounding control field RN of the FPSCR, then negated
and placed into frD.
This instruction produces the same result obtained by negating the result of a Floating Multiply-Subtract
Single (fmsubsx) instruction with the following exceptions:
bit of the SNaN.
FPSCR[VE] = 1.

Condition Register (CR1 field)

UISA A

June 10, 2003 Page 455 of 785
fresx fresx
Floating Reciprocal Estimate Single (xEC00 0030)
fres frD,frB (Rc = 0)

fres. frD,frB (Rc = 1)
Reserved
59 D 0 0000 B 000 00 24 Rc
0 5 6 10 11 15 16 20 21 25 26 30 31
A single-precision estimate of the reciprocal of the floating-point operand in register frB is placed into register
frD. The estimate placed into register frD is correct to a precision of one part in 256 of the reciprocal of frB.
That is,
estimate 1---
x 1
ABS ---------------------------------- ---------
1--- 256
x
where x is the initial value in frB. Note that the value placed into register frD may vary between implementa-
tions, and between different executions on the same implementation.
Operation with various special values of the operand is summarized below:

Operand Result Exception
0 None
0 * ZX
+0 +* ZX
+ +0 None
SNaN QNaN** VXSNAN
QNaN QNaN None
Notes: * No result if FPSCR[ZE] = 1
** No result if FPSCR[VE] = 1
Note that the PowerPC architecture makes no provision for a double-precision version of the fresx instruc-
tion. This is because graphics applications are expected to need only the single-precision version, and no
other important performance-critical applications are expected to require a double-precision version of the
fresx instruction.

Page 456 of 785 June 10, 2003

Affected: FPRF, FR (undefined), FI (undefined), FX, OX, UX, ZX, VXSNAN
UISA A

June 10, 2003 Page 457 of 785
frspx frspx
Floating Round to Single (xFC00 0018)
frsp frD,frB (Rc = 0)

frsp. frD,frB (Rc = 1)
Reserved
63 D 0 0000 B 12 Rc
0 5 6 10 11 15 16 20 21 30 31
The floating-point operand in register frB is rounded to single-precision using the rounding mode specified by
FPSCR[RN] and placed into frD.
The rounding is described fully in Section D.4.1 , Floating-Point Round to Single-Precision Model.
FPSCR[VE] = 1.


Affected: FPRF, FR, FI, FX, OX, UX, XX, VXSNAN
UISA X

Page 458 of 785 June 10, 2003
frsqrtex frsqrtex
Floating Reciprocal Square Root Estimate (xFC00 0034)
frsqrte frD,frB (Rc = 0)

frsqrte. frD,frB (Rc = 1)
Reserved
63 D 0 0000 B 000 00 26 Rc
0 5 6 10 11 15 16 20 21 25 26 30 31
A double-precision estimate of the reciprocal of the square root of the floating-point operand in register frB is
placed into register frD. The estimate placed into register frD is correct to a precision of one part in 32 of the
reciprocal of the square root of frB. That is,
estimate ------ 1-
x 1
ABS -------------------------------------- ------
------
1- 32
x
where x is the initial value in frB. Note that the value placed into register frD may vary between implementa-
tions, and between different executions on the same implementation.

QNaN** VXSQRT
<0 QNaN** VXSQRT
0 * ZX
+0 +* ZX
+ +0 None
SNaN QNaN** VXSNAN
QNaN QNaN None
Notes: * No result if FPSCR[ZE] = 1
** No result if FPSCR[VE] = 1
Note that no single-precision version of the frsqrte instruction is provided; however, both frB and frD are
representable in single-precision format.

June 10, 2003 Page 459 of 785

Affected: FPRF, FR (undefined), FI (undefined), FX, ZX, VXSNAN, VXSQRT
UISA A

Page 460 of 785 June 10, 2003
fselx fselx
Floating Select (xFC00 002E)
fsel frD,frA,frC,frB (Rc = 0)

fsel. frD,frA,frC,frB (Rc = 1)
63 D A B C 23 Rc
0 5 6 10 11 15 16 20 21 25 26 30 31
if (frA) 0.0 then frD (frC)

else frD (frB)
The floating-point operand in register frA is compared to the value zero. If the operand is greater than or
equal to zero, register frD is set to the contents of register frC. If the operand is less than zero or is a NaN,
register frD is set to the contents of register frB. The comparison ignores the sign of zero (that is, regards +0
as equal to 0).
Care must be taken in using fsel if IEEE compatibility is required, or if the values being tested can be NaNs or
infinities.
For examples of uses of this instruction, see Section D.3 , Floating-Point Conversions, and Section D.5 ,
Floating-Point Selection.

UISA A

June 10, 2003 Page 461 of 785
fsqrtx fsqrtx
Floating Square Root (Double-Precision) (xFC00 002C)
fsqrt frD,frB (Rc = 0)

fsqrt. frD,frB (Rc = 1)
Reserved
63 D 0 0000 B 000 00 22 Rc
0 5 6 10 11 15 16 20 21 25 26 30 31
The square root of the floating-point operand in register frB is placed into register frD.
If the most-significant bit of the resultant significand is not a one the result is normalized. The result is
rounded to the target precision under control of the floating-point rounding control field RN of the FPSCR and
placed into register frD.

QNaN* VXSQRT
<0 QNaN* VXSQRT
0 0 None
+ + None
SNaN QNaN* VXSNAN
QNaN QNaN None
Notes: * No result if FPSCR[VE] = 1
FPSCR[VE] = 1.


Affected: FPRF, FR, FI, FX, XX, VXSNAN, VXSQRT
UISA A

Page 462 of 785 June 10, 2003
fsqrtsx fsqrtsx
Floating Square Root Single (xEC00 002C)
fsqrts frD,frB (Rc = 0)

fsqrts. frD,frB (Rc = 1)
Reserved
59 D 0 0000 B 000 00 22 Rc
0 5 6 10 11 15 16 20 21 25 26 30 31
The square root of the floating-point operand in register frB is placed into register frD.
If the most-significant bit of the resultant significand is not a one the result is normalized. The result is
rounded to the target precision under control of the floating-point rounding control field RN of the FPSCR and
placed into register frD.
Operation with various special values of the operand is summarized below.

QNaN* VXSQRT
<0 QNaN* VXSQRT
0 0 None
+ + None
SNaN QNaN* VXSNAN
QNaN QNaN None
Notes: * No result if FPSCR[VE] = 1
FPSCR[VE] = 1.


Affected: FPRF, FR, FI, FX, XX, VXSNAN, VXSQRT
UISA A

June 10, 2003 Page 463 of 785
fsubx fsubx
Floating Subtract (Double-Precision) (xFC00 0028)
fsub frD,frA,frB (Rc = 0)

fsub. frD,frA,frB (Rc = 1)
[POWER mnemonics: fs, fs.]
Reserved
63 D A B 000 00 20 Rc
0 5 6 10 11 15 16 20 21 25 26 30 31
The floating-point operand in register frB is subtracted from the floating-point operand in register frA. If the
most-significant bit of the resultant significand is not a one, the result is normalized. The result is rounded to
double-precision under control of the floating-point rounding control field RN of the FPSCR and placed into
frD.
The execution of the fsub instruction is identical to that of fadd, except that the contents of frB participate in
the operation with its sign bit (bit 0) inverted.
FPSCR[VE] = 1.


Affected: FPRF, FR, FI, FX, OX, UX, XX, VXSNAN, VXISI
UISA A

Page 464 of 785 June 10, 2003
fsubsx fsubsx
Floating Subtract Single (xEC00 0028)
fsubs frD,frA,frB (Rc = 0)

fsubs. frD,frA,frB (Rc = 1)
Reserved
59 D A B 000 00 20 Rc
0 5 6 10 11 15 16 20 21 25 26 30 31
The floating-point operand in register frB is subtracted from the floating-point operand in register frA. If the
most-significant bit of the resultant significand is not a one, the result is normalized. The result is rounded to
single-precision under control of the floating-point rounding control field RN of the FPSCR and placed into
frD.
The execution of the fsubs instruction is identical to that of fadds, except that the contents of frB participate
in the operation with its sign bit (bit 0) inverted.
FPSCR[VE] = 1.


Affected: FPRF, FR, FI, FX, OX, UX, XX, VXSNAN, VXISI
UISA A

June 10, 2003 Page 465 of 785
icbi icbi
Instruction Cache Block Invalidate (x7C00 07AC)
icbi rA,rB
Reserved
31 00 000 A B 982 0
0 5 6 10 11 15 16 20 21 30 31
If the block containing the byte addressed by EA is in coherency-required mode, and a block containing the
byte addressed by EA is in the instruction cache of any processor, the block is made invalid in all such
instruction caches, so that subsequent references cause the block to be refetched.
If the block containing the byte addressed by EA is in coherency-not-required mode, and a block containing
the byte addressed by EA is in the instruction cache of this processor, the block is made invalid in that instruc-
tion cache, so that subsequent references cause the block to be refetched.
The function of this instruction is independent of the write-through, write-back, and caching-inhibited/allowed
modes of the block containing the byte addressed by EA.
This instruction is treated as a load from the addressed byte with respect to address translation and memory
protection. It may also be treated as a load for referenced and changed bit recording except that referenced
and changed bit recording may not occur. Implementations with a combined data and instruction cache treat
the icbi instruction as a no-op, except that they may invalidate the target block in the instruction caches of
other processors if the block is in coherency-required mode.
The icbi instruction invalidates the block at EA (rA|0 + rB). If the processor is a multiprocessor implementa-
tion (for example, the 601, 604, or 620) and the block is marked coherency-required, the processor will send
an address-only broadcast to other processors causing those processors to invalidate the block from their
instruction caches.
For faster processing, many implementations will not compare the entire EA (rA|0 + rB) with the tag in the
instruction cache. Instead, they will use the bits in the EA to locate the set that the block is in, and invalidate
all blocks in that set.

None
VEA X

Page 466 of 785 June 10, 2003
isync isync
Instruction Synchronize (x4C00 012C)
isync
[POWER mnemonic: ics]
Reserved
19 00 000 0 0000 0000 0 150 0
0 5 6 10 11 15 16 20 21 30 31
The isync instruction provides an ordering function for the effects of all instructions executed by a processor.
Executing an isync instruction ensures that all instructions preceding the isync instruction have completed
before the isync instruction completes, except that memory accesses caused by those instructions need not
have been performed with respect to other processors and mechanisms. It also ensures that no subsequent
instructions are initiated by the processor until after the isync instruction completes. Finally, it causes the
processor to discard any prefetched instructions, with the effect that subsequent instructions will be fetched
and executed in the context established by the instructions preceding the isync instruction. The isync instruc-
tion has no effect on the other processors or on their caches.
This instruction is context synchronizing.
Context synchronization is necessary after certain code sequences that perform complex operations within
the processor. These code sequences are usually operating system tasks that involve memory management.
For example, if an instruction A changes the memory translation rules in the memory management unit
(MMU), the isync instruction should be executed so that the instructions following instruction A will be
discarded from the pipeline and refetched according to the new translation rules.
Note that all exceptions and the rfi and rfid instructions are also context synchronizing.

None
VEA XL

June 10, 2003 Page 467 of 785
lbz lbz
Load Byte and Zero (x8800 0000)
lbz rD,d(rA)
34 D A d
0 5 6 10 11 15 16 31
if rA = 0 then b 0
else b (rA)
EA b + EXTS(d)
rD (5624)0 || MEM(EA, 1)
EA is the sum (rA|0) + d. The byte in memory addressed by EA is loaded into the low-order eight bits of rD.
The remaining bits in rD are cleared.

None
UISA D

Page 468 of 785 June 10, 2003
lbzu lbzu
Load Byte and Zero with Update (x8C00 0000)
lbzu rD,d(rA)
35 D A d
0 5 6 10 11 15 16 31
EA (rA) + EXTS(d)
rD (5624)0 || MEM(EA, 1)
rA EA
EA is the sum (rA) + d. The byte in memory addressed by EA is loaded into the low-order eight bits of rD. The
remaining bits in rD are cleared.
EA is placed into rA.
If rA = 0, or rA = rD, the instruction form is invalid.

None
UISA D

June 10, 2003 Page 469 of 785
lbzux lbzux
Load Byte and Zero with Update Indexed (x7C00 00EE)
lbzux rD,rA,rB
Reserved
31 D A B 119 0
0 5 6 10 11 15 16 20 21 30 31
EA (rA) + (rB)
rD (5624)0 || MEM(EA, 1)
rA EA
EA is the sum (rA) + (rB). The byte in memory addressed by EA is loaded into the low-order eight bits of rD.
If rA = 0 or rA = rD, the instruction form is invalid.

None
UISA X

Page 470 of 785 June 10, 2003
lbzx lbzx
Load Byte and Zero Indexed (x7C00 00AE)
lbzx rD,rA,rB
Reserved
31 D A B 87 0
0 5 6 10 11 15 16 20 21 30 31
if rA = 0 then b 0
else b (rA)
EA b + (rB)
rD (5624)0 || MEM(EA, 1)
EA is the sum (rA|0) + (rB). The byte in memory addressed by EA is loaded into the low-order eight bits of rD.

None
UISA X

June 10, 2003 Page 471 of 785
ld 64-Bit Implementations Only ld

Load Double Word (xE800 0000)
ld rD,ds(rA)
58 D A ds 00
0 5 6 10 11 15 16 29 30 31
if rA = 0 then b 0
else b (rA)
EA b + EXTS(ds || 0b00)
rD MEM(EA, 8)
EA is the sum (rA|0) + (ds || 0b00). The double word in memory addressed by EA is loaded into rD.

None
UISA DS

Page 472 of 785 June 10, 2003
ldarx 64-Bit Implementations Only ldarx

Load Double Word and Reserve Indexed (x7C00 00A8)
ldarx rD,rA,rB
Reserved
31 D A B 84 0
0 5 6 10 11 15 16 20 21 30 31
if rA = 0 then b 0
else b (rA)
EA b + (rB)
RESERVE 1
RESERVE_ADDR physical_addr(EA)
rD MEM(EA, 8)
EA is the sum (rA|0) + (rB). The double word in memory addressed by EA is loaded into rD.
This instruction creates a reservation for use by a Store Double Word Conditional Indexed (stdcx.) instruc-
tion. An address computed from the EA is associated with the reservation, and replaces any address previ-
ously associated with the reservation.
EA must be a multiple of eight. If it is not, either the system alignment exception handler is invoked or the
results are boundedly undefined. For additional information about alignment and DSI exceptions, see
Section 6.4.3 , DSI Exception (0x00300).

None
UISA X

June 10, 2003 Page 473 of 785
ldu 64-Bit Implementations Only ldu

Load Double Word with Update (xE800 0001)
ldu rD,ds(rA)
58 D A ds 01
0 5 6 10 11 15 16 29 30 31
EA (rA) + EXTS(ds || 0b00)

rD MEM(EA, 8)
rA EA
EA is the sum (rA) + (ds || 0b00). The double word in memory addressed by EA is loaded into rD.

None
UISA DS

Page 474 of 785 June 10, 2003
ldux 64-Bit Implementations Only lduxx

Load Double Word with Update Indexed (x7C00 006A)
ldux rD,rA,rB
Reserved
31 D A B 53 0
0 5 6 10 11 15 16 20 21 30 31
EA (rA) + (rB)
rD MEM(EA, 8)
rA EA
EA is the sum (rA) + (rB). The double word in memory addressed by EA is loaded into rD.
system illegal instruction to be invoked.

None
UISA X

June 10, 2003 Page 475 of 785
ldx 64-Bit Implementations Only ldx

Load Double Word Indexed (x7C00 002A)
ldx rD,rA,rB
Reserved
31 D A B 21 0
0 5 6 10 11 15 16 20 21 30 31
if rA = 0 then b 0
else b (rA)
EA b + (rB)
rD MEM(EA, 8)
EA is the sum (rA|0) + (rB). The double word in memory addressed by EA is loaded into rD.

None
UISA X

Page 476 of 785 June 10, 2003
lfd lfd
Load Floating-Point Double (xC800 0000)
lfd frD,d(rA)
50 D A d
0 5 6 10 11 15 16 31
if rA = 0 then b 0
else b (rA)
EA b + EXTS(d)
frD MEM(EA, 8)
EA is the sum (rA|0) + d.
The double word in memory addressed by EA is placed into frD.

None
UISA D

June 10, 2003 Page 477 of 785
lfdu lfdu
Load Floating-Point Double with Update (xCC00 0000)
lfdu frD,d(rA)
51 D A d
0 5 6 10 11 15 16 31
EA (rA) + EXTS(d)
frD MEM(EA, 8)
rA EA
EA is the sum (rA) + d.
If rA = 0, the instruction form is invalid.

None
UISA D

Page 478 of 785 June 10, 2003
lfdux lfdux
Load Floating-Point Double with Update Indexed (x7C00 04EE)
lfdux frD,rA,rB
Reserved
31 D A B 631 0
0 5 6 10 11 15 16 20 21 30 31
EA (rA) + (rB)
frD MEM(EA, 8)
rA EA
EA is the sum (rA) + (rB).

None
UISA X

June 10, 2003 Page 479 of 785
lfdx lfdx
Load Floating-Point Double Indexed (x7C00 04AE)
lfdx frD,rA,rB
Reserved
31 D A B 599 0
0 5 6 10 11 15 16 20 21 30 31
if rA = 0 then b 0
else b (rA)
EA b + (rB)
frD MEM(EA, 8)

None
UISA X

Page 480 of 785 June 10, 2003
lfs lfs
Load Floating-Point Single (xC000 0000)
lfs frD,d(rA)
48 D A d
0 5 6 10 11 15 16 31
if rA = 0 then b 0
else b (rA)
EA b + EXTS(d)
frD DOUBLE(MEM(EA, 4))
The word in memory addressed by EA is interpreted as a floating-point single-precision operand. This word is
converted to floating-point double-precision (see Section D.6 , Floating-Point Load Instructions) and placed
into frD.

None
UISA D

June 10, 2003 Page 481 of 785
lfsu lfsu
Load Floating-Point Single with Update (xC400 0000)
lfsu frD,d(rA)
49 D A d
0 5 6 10 11 15 16 31
EA (rA) + EXTS(d)
rA EA
into frD.

None
UISA D

Page 482 of 785 June 10, 2003
lfsux lfsux
Load Floating-Point Single with Update Indexed (x7C00 046E)
lfsux frD,rA,rB
Reserved
31 D A B 567 0
0 5 6 10 11 15 16 20 21 30 31
EA (rA) + (rB)
rA EA
into frD.

None
UISA X

June 10, 2003 Page 483 of 785
lfsx lfsx
Load Floating-Point Single Indexed (x7C00 042E)
lfsx frD,rA,rB
Reserved
31 D A B 535 0
0 5 6 10 11 15 16 20 21 30 31
if rA = 0 then b 0
else b (rA)
EA b + (rB)
into frD.

None
UISA X

Page 484 of 785 June 10, 2003
lha lha
Load Half Word Algebraic (xA800 0000)
lha rD,d(rA)
42 D A d
0 5 6 10 11 15 16 31
if rA = 0 then b 0
else b (rA)
EA b + EXTS(d)
rD EXTS(MEM(EA, 2))
EA is the sum (rA|0) + d. The half word in memory addressed by EA is loaded into the low-order 16 bits of rD.
The remaining bits in rD are filled with a copy of the most-significant bit of the loaded half word.

None
UISA D

June 10, 2003 Page 485 of 785
lhau lhau
Load Half Word Algebraic with Update (xAC00 0000)
lhau rD,d(rA)
43 D A d
0 5 6 10 11 15 16 31
EA (rA) + EXTS(d)
rD EXTS(MEM(EA, 2))
rA EA
EA is the sum (rA) + d. The half word in memory addressed by EA is loaded into the low-order 16 bits of rD.
The remaining bits in rD are filled with a copy of the most-significant bit of the loaded half word.

None
UISA D

Page 486 of 785 June 10, 2003
lhaux lhaux
Load Half Word Algebraic with Update Indexed (x7C00 02EE)
lhaux rD,rA,rB
Reserved
31 D A B 375 0
0 5 6 10 11 15 16 20 21 30 31
EA (rA) + (rB)
rD EXTS(MEM(EA, 2))
rA EA
EA is the sum (rA) + (rB). The half word in memory addressed by EA is loaded into the low-order 16 bits of
rD. The remaining bits in rD are filled with a copy of the most-significant bit of the loaded half word.

None
UISA X

June 10, 2003 Page 487 of 785
lhax lhax
Load Half Word Algebraic Indexed (x7C00 02AE)
lhax rD,rA,rB
Reserved
31 D A B 343 0
0 5 6 10 11 15 16 20 21 30 31
if rA = 0 then b 0
else b (rA)
EA b + (rB)
rD EXTS(MEM(EA, 2))
EA is the sum (rA|0) + (rB). The half word in memory addressed by EA is loaded into the low-order 16 bits of
rD. The remaining bits in rD are filled with a copy of the most-significant bit of the loaded half word.

None
UISA X

Page 488 of 785 June 10, 2003
lhbrx lhbrx
Load Half Word Byte-Reverse Indexed (x7C00 062C)
lhbrx rD,rA,rB
Reserved
31 D A B 790 0
0 5 6 10 11 15 16 20 21 30 31
if rA = 0 then b 0
else b (rA)
EA b + (rB)
rD (4816)0 || MEM(EA + 1, 1) || MEM(EA, 1)
EA is the sum (rA|0) + (rB). Bits 07 of the half word in memory addressed by EA are loaded into the low-
order eight bits of rD. Bits 815 of the half word in memory addressed by EA are loaded into the subsequent
low-order eight bits of rD. The remaining bits in rD are cleared.
The PowerPC architecture cautions programmers that some implementations of the architecture may run the
lhbrx instructions with greater latency than other types of load instructions.

None
UISA X

June 10, 2003 Page 489 of 785
lhz lhz
Load Half Word and Zero (xA000 0000)
lhz rD,d(rA)
40 D A d
0 5 6 10 11 15 16 31
if rA = 0 then b 0
else b (rA)
EA b + EXTS(d)
rD (4816)0 || MEM(EA, 2)
EA is the sum (rA|0) + d. The half word in memory addressed by EA is loaded into the low-order 16 bits of rD.

None
UISA D

Page 490 of 785 June 10, 2003
lhzu lhzu
Load Half Word and Zero with Update (xA400 0000)
lhzu rD,d(rA)
41 D A d
0 5 6 10 11 15 16 31
EA rA + EXTS(d)
rD (4816)0 || MEM(EA, 2)
rA EA
EA is the sum (rA) + d. The half word in memory addressed by EA is loaded into the low-order 16 bits of rD.

None
UISA D

June 10, 2003 Page 491 of 785
lhzux lhzux
Load Half Word and Zero with Update Indexed (x7C00 026E)
lhzux rD,rA,rB
Reserved
31 D A B 311 0
0 5 6 10 11 15 16 20 21 30 31
EA (rA) + (rB)
rD (4816)0 || MEM(EA, 2)
rA EA
EA is the sum (rA) + (rB). The half word in memory addressed by EA is loaded into the low-order 16 bits of
rD. The remaining bits in rD are cleared.

None
UISA X

Page 492 of 785 June 10, 2003
lhzx lhzx
Load Half Word and Zero Indexed (x7C00 022E)
lhzx rD,rA,rB
Reserved
31 D A B 279 0
0 5 6 10 11 15 16 20 21 30 31
if rA = 0 then b 0
else b (rA)
EA b + (rB)
rD (4816)0 || MEM(EA, 2)
EA is the sum (rA|0) + (rB). The half word in memory addressed by EA is loaded into the low-order 16 bits of
rD. The remaining bits in rD are cleared.

None
UISA X

June 10, 2003 Page 493 of 785
lmw lmw
Load Multiple Word (xB800 0000)
lmw rD,d(rA)
[POWER mnemonic: lm]
46 D A d
0 5 6 10 11 15 16 31
if rA = 0 then b 0
else b (rA)
EA b + EXTS(d)
r rD
do while r 31
GPR(r) (32)0 || MEM(EA, 4)
rr + 1
EA EA + 4
n = (32 rD).
n consecutive words starting at EA are loaded into the low-order 32 bits of GPRs rD through r31. The high-
order 32 bits of these GPRs are cleared.
EA must be a multiple of four. If it is not, either the system alignment exception handler is invoked or the
If rA is in the range of registers specified to be loaded, including the case in which rA = 0, the instruction form
is invalid.
Note that, in some implementations, this instruction is likely to have a greater latency and take longer to
execute, perhaps much longer, than a sequence of individual load or store instructions that produce the same
results.

None
UISA D

Page 494 of 785 June 10, 2003
lswi lswi
Load String Word Immediate (x7C00 04AA)
lswi rD,rA,NB
[POWER mnemonic: lsi]
if rA = 0 then EA 0
else EA (rA)
if NB = 0 then n 32
elsen NB
r rD 1
i 320
do while n > 0
if i = 32 then
r r + 1 (mod 32)
GPR(r) 0
GPR(r)[ii + 7] MEM(EA, 1)
i i + 8
if i = 6432 then i 320
EA EA + 1
n n 1
EA is (rA|0).
Let n = NB if NB 0, n = 32 if NB = 0; n is the number of bytes to load.
Let nr = CEIL(n 4); nr is the number of registers to be loaded with data.
n consecutive bytes starting at EA are loaded into GPRs rD through rD + nr 1. Data is loaded into the low-
order four bytes of each GPR; the high-order four bytes are cleared.
Bytes are loaded left to right in each register. The sequence of registers wraps around to r0 if required. If the
low-order 4 bytes of register rD + nr 1 are only partially filled, the unfilled low-order byte(s) of that register
are cleared.
If rA is in the range of registers specified to be loaded, including the case in which rA = 0, the instruction form
is invalid.
Under certain conditions (for example, segment boundary crossing) the data alignment exception handler
may be invoked. For additional information about data alignment exceptions, see Section 6.4.3 , DSI Excep-
tion (0x00300).
Note that, in some implementations, this instruction is likely to have greater latency and take longer to
results.

June 10, 2003 Page 495 of 785

None
UISA X

Page 496 of 785 June 10, 2003
lswx lswx
Load String Word Indexed (x7C00 042A)
lswx rD,rA,rB
[POWER mnemonic: lsx]
if rA = 0 then b 0
else b (rA)
EA b + (rB)
n XER[2531]
r rD 1
i 32
rD undefined
do while n > 0
if i = 32 then
r r + 1 (mod 32)
GPR(r) 0
GPR(r)[ii + 7] MEM(EA, 1)
i i + 8
if i = 6432 then i 320
EA EA + 1
n n 1
EA is the sum (rA|0) + (rB). Let n = XER[2531]; n is the number of bytes to load. Let
nr = CEIL(n 4); nr is the number of registers to receive data. If n > 0, n consecutive bytes starting at EA are
loaded into GPRs rD through rD + nr 1. Data is loaded into the low-order four bytes of each GPR; the high-
order four bytes are cleared.
Bytes are loaded left to right in each register. The sequence of registers wraps around through r0 if required.
If the low-order four bytes of rD + nr 1 are only partially filled, the unfilled low-order byte(s) of that register
are cleared. If n = 0, the contents of rD are undefined.
If rA or rB is in the range of registers specified to be loaded, including the case in which rA = 0, either the
system illegal instruction error handler is invoked or the results are boundedly undefined.
If rD = rA or rD = rB, the instruction form is invalid.
If rD and rA both specify GPR0, the form is invalid.
tion (0x00300).
results.

June 10, 2003 Page 497 of 785

None
UISA X

Page 498 of 785 June 10, 2003
lwa 64-Bit Implementations Only lwa

Load Word Algebraic (xE800 0002)
lwa rD,ds(rA)
58 D A ds 10
0 5 6 10 11 15 16 29 30 31
if rA = 0 then b 0
else b (rA)
rD EXTS(MEM(EA, 4))
EA is the sum (rA|0) + (ds || 0b00). The word in memory addressed by EA is loaded into the low-order 32 bits
of rD. The contents of the high-order 32 bits of rD are filled with a copy of bit 0 of the loaded word.

None
UISA DS

June 10, 2003 Page 499 of 785
lwarx lwarx
Load Word and Reserve Indexed (x7C00 0028)
lwarx rD,rA,rB
Reserved
31 D A B 20 0
0 5 6 10 11 15 16 20 21 30 31
if rA = 0 then b 0
else b (rA)
EA b + (rB)
RESERVE 1
RESERVE_ADDR physical_addr(EA)
rD (32)0 || MEM(EA,4)
The word in memory addressed by EA is loaded into the low-order 32 bits of rD. The contents of the high-
order 32 bits of rD are cleared.
This instruction creates a reservation for use by a store word conditional indexed (stwcx.)instruction. The
physical address computed from EA is associated with the reservation, and replaces any address previously
associated with the reservation.
When the RESERVE bit is set, the processor enables hardware snooping for the block of memory addressed
by the RESERVE address. If the processor detects that another processor writes to the block of memory it
has reserved, it clears the RESERVE bit. The stwcx. instruction will only do a store if the RESERVE bit is set.
The stwcx. instruction sets the CR0[EQ] bit if the store was successful and clears it if it failed. The lwarx and
stwcx. combination can be used for atomic read-modify-write sequences. Note that the atomic sequence is
not guaranteed, but its failure can be detected if CR0[EQ] = 0 after the stwcx. instruction.

None
UISA X

Page 500 of 785 June 10, 2003
lwaux 64-Bit Implementations Only lwaux

Load Word Algebraic with Update Indexed (x7C00 02EA)
lwaux rD,rA,rB
Reserved
31 D A B 373 0
0 5 6 10 11 15 16 20 21 30 31
EA (rA) + (rB)
rD EXTS(MEM(EA, 4))
rA EA
EA is the sum (rA) + (rB). The word in memory addressed by EA is loaded into the low-order 32 bits of rD.
The high-order 32 bits of rD are filled with a copy of bit 0 of the loaded word.

None
UISA X

June 10, 2003 Page 501 of 785
lwax 64-Bit Implementations Only lwax

Load Word Algebraic Indexed (x7C00 02AA)
lwax rD,rA,rB
Reserved
31 D A B 341 0
0 5 6 10 11 15 16 20 21 30 31
if rA = 0 then b 0
else b (rA)
EA b + (rB)
rD EXTS(MEM(EA, 4))
EA is the sum (rA|0) + (rB). The word in memory addressed by EA is loaded into the low-order 32 bits of rD.
The high-order 32 bits of rD are filled with a copy of bit 0 of the loaded word.

None
UISA X

Page 502 of 785 June 10, 2003
lwbrx lwbrx
Load Word Byte-Reverse Indexed (x7C00 042C)
lwbrx rD,rA,rB
[POWER mnemonic: lbrx]
Reserved
31 D A B 534 0
0 5 6 10 11 15 16 20 21 30 31
if rA = 0 then b 0
else b (rA)
EA b + (rB)
rD (32)0 || MEM(EA + 3, 1) || MEM(EA + 2, 1) || MEM(EA + 1, 1) || MEM(EA, 1)
EA is the sum (rA|0) + rB. Bits 07 of the word in memory addressed by EA are loaded into the low-order 8
bits of rD. Bits 815 of the word in memory addressed by EA are loaded into the subsequent low-order 8 bits
of rD. Bits 1623 of the word in memory addressed by EA are loaded into the subsequent low-order eight bits
of rD. Bits 2431 of the word in memory addressed by EA are loaded into the subsequent low-order 8 bits of
rD. The high-order 32 bits of rD are cleared.
The PowerPC architecture cautions programmers that some implementations of the architecture may run the
lwbrx instructions with greater latency than other types of load instructions.

None
UISA X

June 10, 2003 Page 503 of 785
lwz lwz
Load Word and Zero (x8000 0000)
lwz rD,d(rA)
[POWER mnemonic: l]
32 D A d
0 5 6 10 11 15 16 31
if rA = 0 then b 0
else b (rA)
EA b + EXTS(d)
rD (32)0 || MEM(EA, 4)
EA is the sum (rA|0) + d. The word in memory addressed by EA is loaded into the low-order 32 bits of rD. The
high-order 32 bits of rD are cleared.

None
UISA D

Page 504 of 785 June 10, 2003
lwzu lwzu
Load Word and Zero with Update (x8400 0000)
lwzu rD,d(rA)
[POWER mnemonic: lu]
33 D A d
0 5 6 10 11 15 16 31
EA rA + EXTS(d)
rD (32)0 || MEM(EA, 4)
rA EA
EA is the sum (rA) + d. The word in memory addressed by EA is loaded into the low-order 32 bits of rD. The
high-order 32 bits of rD are cleared.

None
UISA D

June 10, 2003 Page 505 of 785
lwzux lwzux
Load Word and Zero with Update Indexed (x7C00 006E)
lwzux rD,rA,rB
[POWER mnemonic: lux]
Reserved
31 D A B 55 0
0 5 6 10 11 15 16 20 21 30 31
EA (rA) + (rB)
rD (32)0 || MEM(EA, 4)
rA EA
EA is the sum (rA) + (rB). The word in memory addressed by EA is loaded into the low-order 32 bits of rD.
The high-order 32 bits of rD are cleared.

None
UISA X

Page 506 of 785 June 10, 2003
lwzx lwzx
Load Word and Zero Indexed (x7C00 002E)
lwzx rD,rA,rB
[POWER mnemonic: lx]
Reserved
31 D A B 23 0
0 5 6 10 11 15 16 20 21 30 31
if rA = 0 then b 0
else b (rA)
EA b + rB
rD (32)0 || MEM(EA, 4)
EA is the sum (rA|0) + (rB). The word in memory addressed by EA is loaded into the low-order 32 bits of rD.
The high-order 32 bits of rD are cleared.

None
UISA X

June 10, 2003 Page 507 of 785
mcrf mcrf
Move Condition Register Field (x4C00 0000)
mcrf crfD,crfS
CR[4 crfD4 crfD + 3] CR[4 crfS4 crfS + 3]

The contents of condition register field crfS are copied into condition register field crfD. All other condition
register fields remain unchanged.

UISA XL

Page 508 of 785 June 10, 2003
mcrfs mcrfs
Move to Condition Register from FPSCR (xFC00 0080)
mcrfs crfD,crfS
Reserved
63 crfD 00 crfS 00 0000 0 64 0
0 5 6 8 9 10 11 13 14 15 16 20 21 30 31
The contents of FPSCR field crfS are copied to CR field crfD. All exception bits copied (except FEX and VX)
are cleared in the FPSCR.

Affected: FX, FEX, VX, OX

Affected: FX, OX (if crfS = 0)
Affected: UX, ZX, XX, VXSNAN (if crfS = 1)
Affected: VXISI, VXIDI, VXZDZ, VXIMZ (if crfS = 2)
Affected: VXVC (if crfS = 3)
Affected: VXSOFT, VXSQRT, VXCVI (if crfS = 5)
UISA X

June 10, 2003 Page 509 of 785
mcrxr mcrxr
Move to Condition Register from XER (x7C00 0400)
mcrxr crfD
Reserved
31 crfD 00 00000 0000 0 512 0
0 5 6 8 9 10 11 16 20 21 30 31
CR[* crfD-4 * crfD +3]
The contents of XER[0-3] are copied into the condition register field designated by crfD.
All other fields of the condition register remain unchanged. XER[0-3] is cleared.


XER[0-3]
UISA X

Page 510 of 785 June 10, 2003
mfcr mfcr
Move from Condition Register (x7C00 0026)
mfcr rD
Reserved
31 D 00000 0000 0 19 0
0 5 6 10 11 15 16 20 21 30 31
rD (32)0 || CR
The contents of the condition register (CR) are placed into the low-order 32 bits of rD. The high-order 32 bits
of rD are cleared.

None
UISA X
pem8b.fm.2.0
June 10, 2003 Page 511 of 785
mffsx mffsx
Move from FPSCR (xFC00 048E)
mffs frD (Rc = 0)

mffs. frD (Rc = 1)
Reserved
63 D 00000 0 0000 0 583 Rc
0 5 6 10 11 15 16 20 21 30 31
frD[32-63] FPSCR
The contents of the floating-point status and control register (FPSCR) are placed into the low-order bits of
register frD. The high-order bits of register frD are undefined.

UISA X
pem8b.fm.2.0
Page 512 of 785 June 10, 2003
mfmsr mfmsr
Move from Machine State Register (x7C00 00A6)
mfmsr rD
Reserved
31 D 0 0000 0000 0 83 0
0 5 6 10 11 15 16 20 21 30 31
rD MSR
The contents of the MSR are placed into rD.

None
OEA X
pem8b.fm.2.0
June 10, 2003 Page 513 of 785
mfspr mfspr
Move from Special-Purpose Register (x7C00 02A6)
mfspr rD,SPR
Reserved
31 D spr* 339 0
0 5 6 10 11 20 21 30 31
*Note: This is a split field.
n spr[59] || spr[04]
if length (SPR(n)) = 64 then
rD SPR(n)
else
rD (32)0 || SPR(n)
In the PowerPC UISA, the SPR field denotes a special-purpose register, encoded as shown in Table 8-9. .
The contents of the designated special-purpose register are placed into rD.
For special-purpose registers that are 32 bits long, the low-order 32 bits of rD receive the contents of the
special-purpose register and the high-order 32 bits of rD are cleared.
Table 8-9. PowerPC UISA SPR Encodings for mfspr
SPR**
Register Name
Decimal spr[59] spr[04]
1 00000 00001 XER
8 00000 01000 LR
9 00000 01001 CTR
Note: ** The order of the two 5-bit halves of the SPR number is reversed compared with the actual instruction coding.
If the SPR field contains any value other than one of the values shown in Table 8-9. (and the processor is in
user mode), one of the following occurs:
The system illegal instruction error handler is invoked.
The system supervisor-level instruction error handler is invoked.

None
mfxer rD equivalent to mfspr rD,1

mflr rD equivalent to mfspr rD,8
mfctr rD equivalent to mfspr rD,9
pem8b.fm.2.0
Page 514 of 785 June 10, 2003
In the PowerPC OEA, the SPR field denotes a special-purpose register, encoded as shown in Table 8-10. .
The contents of the designated SPR are placed into rD. For SPRs that are 32 bits long, the low-order 32 bits
of rD receive the contents of the SPR and the high-order 32 bits of rD are cleared.
SPR[0] = 1 if and only if reading the register is supervisor-level. Execution of this instruction specifying a
defined and supervisor-level register when MSR[PR] = 1 will result in a privileged instruction type program
exception.
If MSR[PR] = 1, the only effect of executing an instruction with an SPR number that is not shown in
Table 8-10. and has SPR[0] = 1 is to cause a supervisor-level instruction type program exception or an illegal
instruction type program exception. For all other cases, MSR[PR] = 0 or SPR[0] = 0. If the SPR field contains
any value that is not shown in Table 8-10. , either an illegal instruction type program exception occurs or the
results are boundedly undefined.

None
Table 8-10. PowerPC OEA SPR Encodings for mfspr

1
SPR
Register Name Access
1 00000 00001 XER User
8 00000 01000 LR User
9 00000 01001 CTR User

18 00000 10010 DSISR Supervisor
19 00000 10011 DAR Supervisor
22 00000 10110 DEC Supervisor

25 00000 11001 SDR1 Supervisor
26 00000 11010 SRR0 Supervisor
272 01000 10000 SPRG0 Supervisor
280 01000 11000 ASR2 Supervisor
282 01000 11010 EAR Supervisor
287 01000 11111 PVR Supervisor
528 10000 10000 IBAT0U Supervisor
529 10000 10001 IBAT0L Supervisor
pem8b.fm.2.0
June 10, 2003 Page 515 of 785
Table 8-10. PowerPC OEA SPR Encodings for mfspr (Continued)

1
SPR
536 10000 11000 DBAT0U Supervisor
537 10000 11001 DBAT0L Supervisor

1013 11111 10101 DABR Supervisor

1Note that the order of the two 5-bit halves of the SPR number is reversed compared with actual instruction coding.
For mtspr and mfspr instructions, the SPR number coded in assembly language does not appear directly as a 10-bit binary number in
the instruction. The number coded is split into two 5-bit halves that are reversed in the instruction, with the high-order five bits appearing
in bits 1620 of the instruction and the low-order five bits in bits 1115.
264-bit implementations only.
UISA/OEA * XFX
* Note that mfspr is supervisor level only if SPR[0] = 1
pem8b.fm.2.0
Page 516 of 785 June 10, 2003
mfsr mfsr
Move from Segment Register (x7C00 04A6)
mfsr rD,SR
Reserved
31 D 0 SR 0000 0 595 0
0 5 6 10 11 12 15 16 20 21 30 31
rD SEGREG(SR)
The contents of segment register SR are placed into rD.
This instruction is defined only for 32-bit implementations; using it on a 64-bit implementation causes an
illegal instruction type program exception.

None
T EMPORARY 64-B IT BRIDGE

rD SLB(SR)
The contents of the SLB entry selected by SR are placed into rD; the contents of rD correspond to a
segment table entry containing values as shown in Table 8-11.
Table 8-11. GPR Content Format Following mfsr
SLB Double Word Bit(s) Contents Description
031 0x0000_0000 ESID[031]
3235 SR ESID[3235]
0
5759 rD[3234] T, Ks, Kp
6061 rD[3536] N, reserved bit, or b0
024 rD[731] VSID[024] or reserved

1
2551 rD[3763] VSID[2551], or b1, CNTLR_SPEC
None rD[06] 0b0000_000
pem8b.fm.2.0
June 10, 2003 Page 517 of 785
If the SLB entry selected by SR was not created by an mtsr, mtsrd, or mtsrdin instruction, the con-
tents of rD are undefined.

None
OEA X
pem8b.fm.2.0
Page 518 of 785 June 10, 2003
mfsrin mfsrin
Move from Segment Register Indirect (x7C00 0526)
mfsrin rD,rB
Reserved
31 D 0 0000 B 659 0
0 5 6 10 11 15 16 20 21 30 31
rD SEGREG(rB[03])
The contents of the segment register selected by bits 03 of rB are copied into rD.
This instruction is defined only for 32-bit implementations. Using it on a 64-bit implementation causes an
Note that the rA field is not defined for the mfsrin instruction in the PowerPC architecture. However, mfsrin
performs the same function in the PowerPC architecture as does the mfsri instruction in the POWER archi-
tecture (if rA = 0).

None
pem8b.fm.2.0
June 10, 2003 Page 519 of 785

rD SLB(rB[32-35])
The contents of the SLB entry selected by rB[3235] are placed into rD; the contents of rD correspond to
a segment table entry containing values as shown in Table 8-12
:
Table 8-12. GPR Content Format Following mfsrin
Doubleword Bit(s) Contents Description
0-31 0x0000_0000 ESID[031]
32-35 rB[3235] ESID[3235]

0
57-59 rD[3234] T, Ks, Kp
60-61 rD[3536] N, reserved bit, or b0
0-24 rD[731] VSID[024] or reserved

1
25-51 rD[3763] VSID[2551], or b1, CNTLR_SPEC
none 70 rD[06] 0b0000_000
If the SLB entry selected by rB[3235] was not created by an mtsr, mtsrd, or mtsrdin instruction, the
contents of rD are undefined.

None
OEA X
pem8b.fm.2.0
Page 520 of 785 June 10, 2003
mftb mftb
Move from Time Base (x7C00 02E6)
mftb rD,TBR
Reserved
31 D tbr* 371 0
0 5 6 10 11 20 21 30 31
n tbr[59] || tbr[04]
if n = 268 then
if (64-bit implementation) then
rD TB
else
rD TBL
else if n = 269 then
if (64-bit implementation) then
rD (32)0 || TBU
else
rD TBU
When reading the time base lower (TBL) on a 64-bit implementation, the contents of the entire time base
(TBU || TBL) is copied into rD. Note that when reading time base upper (TBU) on a 64-bit implementation the
high-order 32 bits of rD are cleared. The contents of TBL or TBU are copied into rD, as designated by the
value in TBR, encoded as shown in The TBR field denotes either the TBL or TBU, encoded as shown in
Table 8-13. .
Table 8-13. TBR Encodings for mftb

TBR* Register
Access
Decimal tbr[59] tbr[04] Name
268 01000 01100 TBL User
269 01000 01101 TBU User
Note: *The order of the two 5-bit halves of the TBR number is reversed.
If the TBR field contains any value other than one of the values shown in Table 8-13. , then one of the
following occurs:
The system supervisor-level instruction error handler is invoked.
It is important to note that some implementations may implement mftb and mfspr identically, therefore, a
TBR number must not match an SPR number.
For more information on the time base refer to Section 2.2 , PowerPC VEA Register SetTime Base.
pem8b.fm.2.0
June 10, 2003 Page 521 of 785
None
mftb rD equivalent to mftb rD,268

mftbu rD equivalent to mftb rD,269
VEA XFX
pem8b.fm.2.0
Page 522 of 785 June 10, 2003
mtcrf mtcrf
Move to Condition Register Fields (x7C00 0120)
mtcrf CRM,rS
Reserved
31 S 0 CRM 0 144 0
0 5 6 10 11 12 19 20 21 30 31
mask (4)(CRM[0]) || (4)(CRM[1]) ||... (4)(CRM[7])

CR (rS[3263] & mask) | (CR & mask)
The contents of the low-order 32 bits of rS are placed into the condition register under control of the field
mask specified by CRM. The field mask identifies the 4-bit fields affected. Let i be an integer in the range 0
7. If CRM(i) = 1, CR field i (CR bits 4 i through 4 i + 3) is set to the contents of the corresponding field of
the low-order 32 bits of rS.
Note that updating a subset of the eight fields of the condition register may have substantially poorer perfor-
mance on some implementations than updating all of the fields.

CR fields selected by mask
mtcr rS equivalent to mtcrf 0xFF,rS
UISA XFX
pem8b.fm.2.0
June 10, 2003 Page 523 of 785
mtfsb0x mtfsb0x
Move to FPSCR Bit 0 (xFC00 008C)
mtfsb0 crbD (Rc = 0)

mtfsb0. crbD (Rc = 1)
Reserved
63 crbD 0 0000 0000 0 70 Rc
0 5 6 10 11 15 16 20 21 30 31
Bit crbD of the FPSCR is cleared.

Affected: FPSCR bit crbD
Note: Bits 1 and 2 (FEX and VX) cannot be explicitly cleared.
UISA X
pem8b.fm.2.0
Page 524 of 785 June 10, 2003
mtfsb1x mtfsb1x
Move to FPSCR Bit 1 (xFC00 004C)
mtfsb1 crbD (Rc = 0)

mtfsb1. crbD (Rc = 1)
Reserved
63 crbD 0 0000 0000 0 38 Rc
0 5 6 10 11 15 16 20 21 30 31
Bit crbD of the FPSCR is set.

Affected: FPSCR bit crbD and FX
Note: Bits 1 and 2 (FEX and VX) cannot be explicitly set.
UISA X
pem8b.fm.2.0
June 10, 2003 Page 525 of 785
mtfsfx mtfsfx
Move to FPSCR Fields (xFC00 058E)
mtfsf FM,frB (Rc = 0)

mtfsf. FM,frB (Rc = 1)
Reserved
63 0 FM 0 B 711 Rc
0 5 6 7 14 15 16 20 21 30 31
The low-order 32 bits of frB are placed into the FPSCR under control of the field mask specified by FM. The
field mask identifies the 4-bit fields affected. Let i be an integer in the range 07. If FM[i] = 1, FPSCR field i
(FPSCR bits 4 * i through 4 * i + 3) is set to the contents of the corresponding field of the low-order 32 bits of
register frB.
FPSCR[FX] is altered only if FM[0] = 1.
Updating fewer than all eight fields of the FPSCR may have substantially poorer performance on some imple-
mentations than updating all the fields.
When FPSCR[03] is specified, bits 0 (FX) and 3 (OX) are set to the values of frB[32] and frB[35] (that is,
even if this instruction causes OX to change from 0 to 1, FX is set from frB[32] and not by the usual rule that
FX is set when an exception bit changes from 0 to 1). Bits 1 and 2 (FEX and VX) are set according to the
usual rule and not from frB[3334].

Affected: FPSCR fields selected by mask
UISA XFL
pem8b.fm.2.0
Page 526 of 785 June 10, 2003
mtfsfix mtfsfix
Move to FPSCR Field Immediate (xFC00 010C)
mtfsfi crfD,IMM (Rc = 0)

mtfsfi. crfD,IMM (Rc = 1)
Reserved
63 crfD 00 0 0000 IMM 0 134 Rc
0 5 6 8 9 10 11 12 15 16 19 20 21 30 31
FPSCR[crfD] IMM
The value of the IMM field is placed into FPSCR field crfD.
FPSCR[FX] is altered only if crfD = 0.
When FPSCR[03] is specified, bits 0 (FX) and 3 (OX) are set to the values of IMM[0] and IMM[3] (that is,
even if this instruction causes OX to change from 0 to 1, FX is set from IMM[0] and not by the usual rule that
FX is set when an exception bit changes from 0 to 1). Bits 1 and 2 (FEX and VX) are set according to the
usual rule and not from IMM[12].

Affected: FPSCR field crfD
UISA X
pem8b.fm.2.0
June 10, 2003 Page 527 of 785
mtmsr mtmsr
Move to Machine State Register (x7C00 0124)
mtmsr rS
Reserved
31 S 0 0000 0000 0 146 0
0 5 6 10 11 15 16 20 21 30 31
MSR (rS)
The contents of rS are placed into the MSR.
This is a supervisor-level instruction. It is also an execution synchronizing instruction except with respect to
alterations to the POW and LE bits. Refer to Section 2.3.18 , Synchronization Requirements for Special
Registers and for Lookaside Buffers, for more information.
In addition, alterations to the MSR[EE] and MSR[RI] bits are effective as soon as the instruction completes.
Thus if MSR[EE] = 0 and an external or decrementer exception is pending, executing an mtmsr instruction
that sets MSR[EE] = 1 will cause the external or decrementer exception to be taken before the next instruc-
tion is executed, if no higher priority exception exists.

MSR

The mtmsr instruction may optionally be provided by a 64-bit implementation. The operation of the
mtmsr instruction in a 64-bit implementation is identical to operation in a 32-bit implementation, except
as described below:
Bits 3263 of rS are placed into the corresponding bits of the MSR. The high-order 32 bits of the
MSR are unchanged.
Note that there is no need for an optional version of the mfmsr instruction, as the existing instruction
copies the entire contents of the MSR to the selected GPR.
When the optional mtmsr instruction is provided in a 64-bit implementation, the optional rfi instruction is
also provided. Refer to the rfi instruction description for additional detail about the operation of the rfi
instruction in 64-bit implementations.
OEA X
pem8b.fm.2.0
Page 528 of 785 June 10, 2003
mtmsrd 64-Bit Implementations Only mtmsrd

Move to Machine State Register Double Word (x7C00 0164)
mtmsrd rS
Reserved
31 S 0 0000 0000 0 178 0
0 5 6 10 11 15 16 20 21 30 31
MSR (rS)
The contents of rS are placed into the MSR.
This is a supervisor-level instruction. It is also an execution synchronizing instruction except with respect to
alterations to the POW and LE bits. Refer to Section 2.3.18 , Synchronization Requirements for Special
Registers and for Lookaside Buffers, for more information.
In addition, alterations to the MSR[EE] and MSR[RI] bits are effective as soon as the instruction completes.
Thus if MSR[EE] = 0 and an external or decrementer exception is pending, executing an mtmsrd instruction
that sets MSR[EE] = 1 will cause the external or decrementer exception to be taken before the next instruc-
tion is executed, if no higher priority exception exists.

MSR
OEA X
pem8b.fm.2.0
June 10, 2003 Page 529 of 785
mtspr mtspr
Move to Special-Purpose Register (x7C00 03A6)
mtspr SPR,rS
Reserved
31 S spr* 467 0
0 5 6 10 11 20 21 30 31
n spr[59] || spr[04]
if length (SPR(n)) = 64 then
SPR(n) (rS)
else
SPR(n) rS[3263]
In the PowerPC UISA, the SPR field denotes a special-purpose register, encoded as shown in Table 8-14. .
The contents of rS are placed into the designated special-purpose register. For special-purpose registers that
are 32 bits long, the low-order 32 bits of rS are placed into the SPR.
Table 8-14. PowerPC UISA SPR Encodings for mtspr

SPR**
Register Name
1 00000 00001 XER
8 00000 01000 LR
9 00000 01001 CTR
Note: ** The order of the two 5-bit halves of the SPR number is reversed compared with actual instruction coding.
If the SPR field contains any value other than one of the values shown in Table 8-14. , and the processor is
operating in user mode, one of the following occurs:
The system supervisor instruction error handler is invoked.

See Table 8-14. .
mtxer rD equivalent to mtspr 1,rD

mtlr rD equivalent to mtspr 8,rD
mtctr rD equivalent to mtspr 9,rD
In the PowerPC OEA, the SPR field denotes a special-purpose register, encoded as shown in Table 8-15. .
The contents of rS are placed into the designated special-purpose register. For special-purpose registers that
are 32 bits long, the low-order 32 bits of rS are placed into the SPR.
pem8b.fm.2.0
Page 530 of 785 June 10, 2003
For this instruction, SPRs TBL and TBU are treated as separate 32-bit registers; setting one leaves the other
unaltered.
The value of SPR[0] = 1 if and only if writing the register is a supervisor-level operation. Execution of this
instruction specifying a defined and supervisor-level register when MSR[PR] = 1 results in a privileged
instruction type program exception.
If MSR[PR] = 1 then the only effect of executing an instruction with an SPR number that is not shown in
Table 8-15. and has SPR[0] = 1 is to cause a privileged instruction type program exception or an illegal
instruction type program exception. For all other cases, MSR[PR] = 0 or SPR[0] = 0, if the SPR field contains
any value that is not shown in Table 8-15. , either an illegal instruction type program exception occurs or the
results are boundedly undefined.

See Table 8-15. .
Table 8-15. PowerPC OEA SPR Encodings for mtspr

1
SPR
1 00000 00001 XER User
8 00000 01000 LR User
9 00000 01001 CTR User

18 00000 10010 DSISR Supervisor
19 00000 10011 DAR Supervisor
22 00000 10110 DEC Supervisor

25 00000 11001 SDR1 Supervisor

280 01000 11000 ASR2 Supervisor
282 01000 11010 EAR Supervisor
284 01000 11100 TBL Supervisor
285 01000 11101 TBU Supervisor

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June 10, 2003 Page 531 of 785
Table 8-15. PowerPC OEA SPR Encodings for mtspr (Continued)

1
SPR

1013 11111 10101 DABR Supervisor

1Note that the order of the two 5-bit halves of the SPR number is reversed. For mtspr and mfspr instructions, the SPR
number coded in assembly language does not appear directly as a 10-bit binary number in the instruction. The number
coded is split into two 5-bit halves that are reversed in the instruction, with the high-order five bits appearing in bits 16
20 of the instruction and the low-order five bits in bits 1115.
264-bit implementations only.
UISA/OEA * XFX
* Note that mtspr is supervisor level only if SPR[0] = 1
pem8b.fm.2.0
Page 532 of 785 June 10, 2003
mtsr mtsr
Move to Segment Register (x7C00 01A4)
mtsr SR,rS
Reserved
31 S 0 SR 0000 0 210 0
0 5 6 10 11 12 15 16 20 21 30 31
SEGREG(SR) (rS)
The contents of rS are placed into SR.

None

SLB(SR) (rS[32-63])
The SLB entry selected by SR is set as though it were loaded from a segment table entry, as shown in
Table 8-16.
Table 8-16. SLB Entry Following mtsr
Double Word Bit(s) Contents Description
031 0x0000_0000 ESID[031]

3235 SR ESID[3235]
0 56 0b1 V
5759 rS[32-34] T, Ks, Kp

6061 rS[35-36] N, reserved bit, or b0
024 0x0000_00||0b0 VSID[024] or reserved

1
2551 rS[37-63] VSID[2551], or b1, CNTLR_SPEC
pem8b.fm.2.0
June 10, 2003 Page 533 of 785
Note that when creating an ordinary segment (T = 0) using the mtsr instruction, rS[3639] should be set
to 0x0, as these bits correspond to the reserved bits in the T = 0 format for a segment register.

None
OEA X
pem8b.fm.2.0
Page 534 of 785 June 10, 2003
mtsrd 64-Bit Implementations Only mtsrd

Move to Segment Register Double Word (x7C00 00A4)

mtsrd SR,rS
Reserved
31 S 0 SR 0000 0 82 0
0 5 6 10 11 12 15 16 20 21 30 31
SLB(SR) (rS)
The contents of rS are placed into the SLB selected by SR. The SLB entry is set as though it were loaded
from an STE, as shown in Table 8-17.
Table 8-17. SLB Entry Following mtsrd

031 0x0000_0000 ESID[031]
3235 SR ESID[3235]
0 56 0b1 V
5759 rS[3234] T, Ks, Kp
6061 rS[3536] N, reserved bit, or b0

024 rS[731] VSID[024] or reserved
1
2551 rS[3763] VSID[2551], or b1, CNTLR_SPEC
This instruction is optional, and is defined only for 64-bit implementations. If the mtsrd instruction is imple-
mented, the mtsrdin instruction will also be implemented. Using it on a 32-bit implementation causes an

None
OEA X
pem8b.fm.2.0
June 10, 2003 Page 535 of 785
mtsrdin 64-Bit Implementations Only mtsrdin

Move to Segment Register Double Word Indirect (x7C00 00E4)

mtsrdin rS,rB
Reserved
31 S 0 0000 B 114 0
0 5 6 10 11 15 16 20 21 30 31
SLB(rB[32-35]) (rS)
The contents of rS are copied to the SLB selected by bits 3235 of rB. The SLB entry is set as though it were
loaded from an STE, as shown in Table 8-18.
Table 8-18. SLB Entry following mtsrdin

031 0x0000_0000 ESID[031]

3235 rB[3235] ESID[3235]
0 56 0b1 V
5759 rS[3234] T, Ks, Kp

024 rS[731] VSID[0-24] or reserved

1
This instruction is optional, and defined only for 64-bit implementations. If the mtsrdin instruction is
implemented, the mtsrd instruction will also be implemented. Using it on a 32-bit implementation causes
an illegal instruction exception.

None
OEA X
pem8b.fm.2.0
Page 536 of 785 June 10, 2003
mtsrin mtsrin
Move to Segment Register Indirect (x7C00 01E4)
mtsrin rS,rB
[POWER mnemonic: mtsri]
Reserved
31 S 0 0000 B 242 0
0 5 6 10 11 15 16 20 21 30 31
SEGREG(rB[03]) (rS)
The contents of rS are copied to the segment register selected by bits 03 of rB.
Note that the PowerPC architecture does not define the rA field for the mtsrin instruction. However, mtsrin
performs the same function in the PowerPC architecture as does the mtsri instruction in the POWER archi-
tecture (if rA = 0).

None
pem8b.fm.2.0
June 10, 2003 Page 537 of 785

SLB(rB[32-35]) (rS[32-63])
The SLB entry selected by bits 32-35 of rB is set as though it were loaded from a segment table entry,
as shown in Table 8-19.
Table 8-19. SLB Entry Following mtsrin

031 0x0000_0000 ESID[031]
3235 rB[3235] ESID[3235]
0 56 0b1 V
5759 rS[3234] T, Ks, Kp
024 0x0000_00||0b0 VSID[024] or reserved

1
Note that when creating an ordinary segment (T = 0) using the mtsrin instruction, rS[3639] should be
set to 0x0, as these bits correspond to the reserved bits in the T = 0 format for a segment register.

None
OEA X
pem8b.fm.2.0
Page 538 of 785 June 10, 2003
mulhdx 64-Bit Implementations Only mulhdx

Multiply High Double Word (x7C00 0092)
mulhd rD,rA,rB (Rc = 0)

mulhd. rD,rA,rB (Rc = 1)
31 D A B 0 73 Rc
0 5 6 10 11 15 16 20 21 22 30 31
prod[0127] (rA) (rB)

rD prod[063]
The 64-bit operands are (rA) and (rB). The high-order 64 bits of the 128-bit product of the operands are
placed into rD.
Both the operands and the product are interpreted as signed integers.
This instruction may execute faster on some implementations if rB contains the operand having the smaller
absolute value.

Note: The setting of CR0 bits LT, GT, and EQ is mode-dependent, and reflects overflow of the 64-bit
result.
UISA XO
pem8b.fm.2.0
June 10, 2003 Page 539 of 785
mulhdux 64-Bit Implementations Only mulhdux

Multiply High Double Word Unsigned (x7C00 0012)
mulhdu rD,rA,rB (Rc = 0)

mulhdu. rD,rA,rB (Rc = 1)
31 D A B 0 9 Rc
0 5 6 10 11 15 16 20 21 22 30 31

rD prod[063]
The 64-bit operands are (rA) and (rB). The high-order 64 bits of the 128-bit product of the operands are
placed into rD.
Both the operands and the product are interpreted as unsigned integers, except that if
Rc = 1 the first three bits of CR0 field are set by signed comparison of the result to zero.
absolute value.

result.
UISA XO
pem8b.fm.2.0
Page 540 of 785 June 10, 2003
mulhwx mulhwx
Multiply High Word (x7C00 0096)
mulhw rD,rA,rB (Rc = 0)

mulhw. rD,rA,rB (Rc = 1)
Reserved
31 D A B 0 75 Rc
0 5 6 10 11 15 16 20 21 22 30 31
prod[063] rA[3263] rB[3263]

rD[3263] prod[031]
rD[031] undefined
The 6432-bit product is formed from the contents of the low-order 32 bits of rA and rB. The high-order 32 bits
of the 64-bit product of the operands are placed into the low-order 32 bits of rD. The high-order 32 bits of rD
are undefined.
Both the operands and the product are interpreted as signed integers.
absolute value.

result.
UISA XO
pem8b.fm.2.0
June 10, 2003 Page 541 of 785
mulhwux mulhwux
Multiply High Word Unsigned (x7C00 0016)
mulhwu rD,rA,rB (Rc = 0)

mulhwu. rD,rA,rB (Rc = 1)
Reserved
31 D A B 0 11 Rc
0 5 6 10 11 15 16 20 21 22 30 31
prod[063] rA[3263] rB[3263]

rD[3263] prod[031]
rD[031] undefined
The 32-bit operands are the contents of the low-order 32 bits of rA and rB. The high-order 32 bits of the 64-bit
product of the operands are placed into the low-order 32 bits of rD. The high-order 32 bits of rD are unde-
fined.
Both the operands and the product are interpreted as unsigned integers, except that if
Rc = 1 the first three bits of CR0 field are set by signed comparison of the result to zero.
absolute value.

result.
UISA XO
pem8b.fm.2.0
Page 542 of 785 June 10, 2003
mulldx 64-Bit Implementations Only mulldx

Multiply Low Double Word (x7C00 01D2)
mulld rD,rA,rB (OE = 0 Rc = 0)

mulld. rD,rA,rB (OE = 0 Rc = 1)
mulldo rD,rA,rB (OE = 1 Rc = 0)
mulldo. rD,rA,rB (OE = 1 Rc = 1)
31 D A B OE 233 Rc
0 5 6 10 11 15 16 20 21 22 30 31

rD prod[64127]
The 64-bit operands are the contents of rA and rB. The low-order 64 bits of the 128-bit product of the oper-
ands are placed into rD.
Both the operands and the product are interpreted as signed integers. The low-order 64 bits of the product
are independent of whether the operands are regarded as signed or unsigned 64-bit integers. If OE = 1, then
OV is set if the product cannot be represented in 64 bits.
absolute value.

XER:
result.
UISA XO
pem8b.fm.2.0
June 10, 2003 Page 543 of 785
mulli mulli
Multiply Low Immediate (x1C00 0000)
mulli rD,rA,SIMM
[POWER mnemonic: muli]
07 D A SIMM
0 5 6 10 11 15 16 31
prod[012748] (rA) EXTS(SIMM)

rD prod[6412716-48]
The 6432-bit first operand is (rA). The 6416-bit second operand is the sign-extended value of the SIMM field.
The low-order 6432-bits of the 12848-bit product of the operands are placed into rD.
Both the operands and the product are interpreted as signed integers. The low-order 64 bits (or 32 bits) of the
product are calculated independently of whether the operands are treated as signed or unsigned 64-bit (or
32-bit) integers.
This instruction can be used with mulhdx or mulhwx to calculate a full 128-bit (or 64-bit) product.
The low-order 32 bits of the product are the correct 32-bit product for 32-bit implementations and for 32-bit
mode in 64-bit implementations.

None
UISA D
pem8b.fm.2.0
Page 544 of 785 June 10, 2003
mullwx mullwx
Multiply Low Word (x7C00 01D6)
mullw rD,rA,rB (OE = 0 Rc = 0)

mullw. rD,rA,rB (OE = 0 Rc = 1)
mullwo rD,rA,rB (OE = 1 Rc = 0)
mullwo. rD,rA,rB (OE = 1 Rc = 1)
[POWER mnemonics: muls, muls., mulso, mulso.]
31 D A B OE 235 Rc
0 5 6 10 11 15 16 20 21 22 30 31
rD rA[3263] rB[3263]
The 32-bit operands are the contents of the low-order 32 bits of rA and rB. The low-order 32 bits of the 64-bit
product (rA) * (rB) are placed into rD.
The low-order 32 bits of the product are the correct 32-bit product for 32-bit mode of 64-bit implementations
and for 32-bit implementations. The low-order 32-bits of the product are independent of whether the operands
are regarded as signed or unsigned 32-bit integers.
If OE = 1, then OV is set if the product cannot be represented in 32 bits. Both the operands and the product
are interpreted as signed integers.
This instruction can be used with mulhwx to calculate a full 64-bit product.
Note that this instruction may execute faster on some implementations if rB contains the operand having the
smaller absolute value.

XER:
UISA XO
pem8b.fm.2.0
June 10, 2003 Page 545 of 785
nandx nandx
NAND (x7C00 03B8)
nand rA,rS,rB (Rc = 0)

nand. rA,rS,rB (Rc = 1)
31 S A B 476 Rc
0 5 6 10 11 15 16 20 21 30 31
rA ((rS) & (rB))

The contents of rS are ANDed with the contents of rB and the complemented result is placed into rA.
nand with rS = rB can be used to obtain the one's complement.

UISA X
pem8b.fm.2.0
Page 546 of 785 June 10, 2003
negx negx
Negate (x7C00 00D0)
neg rD,rA (OE = 0 Rc = 0)

neg. rD,rA (OE = 0 Rc = 1)
nego rD,rA (OE = 1 Rc = 0)
nego. rD,rA (OE = 1 Rc = 1)
Reserved
31 D A 0000 0 OE 104 Rc
0 5 6 10 11 15 16 20 21 22 30 31
rD (rA) + 1
The value 1 is added to the complement of the value in rA, and the resulting twos complement is placed into
rD.
If executing in the default 64-bit mode and rA contains the most negative 6432-bit number
(0x8000_0000_0000_0000), the result is the most negative number and, if OE = 1, OV is set. Similarly, if
executing in 32-bit mode of a 64-bit implementation (or on a 32-bit implementation) and the low-order 32 bits
of rA contains the most negative 32-bit number (0x8000_0000), the low-order 32 bits of the result contain the
most negative 32-bit number and, if OE = 1, OV is set.

XER:
Affected: SO OV(if OE = 1)
UISA XO
pem8b.fm.2.0
June 10, 2003 Page 547 of 785
norx norx
NOR (x7C00 00F8)
nor rA,rS,rB (Rc = 0)

nor. rA,rS,rB (Rc = 1)
31 S A B 124 Rc
0 5 6 10 11 15 16 20 21 30 31
rA ((rS) | (rB))
The contents of rS are ORed with the contents of rB and the complemented result is placed into rA.
nor with rS = rB can be used to obtain the ones complement.

not rD,rS equivalent to nor rA,rS,rS
UISA X
pem8b.fm.2.0
Page 548 of 785 June 10, 2003
orx orx
OR (x7C00 0378)
or rA,rS,rB (Rc = 0)
or. rA,rS,rB (Rc = 1)
31 S A B 444 Rc
0 5 6 10 11 15 16 20 21 30 31
rA (rS) | (rB)
The contents of rS are ORed with the contents of rB and the result is placed into rA.
The simplified mnemonic mr (shown below) demonstrates the use of the or instruction to move register
contents.

mr rA,rS equivalent to or rA,rS,rS
UISA X
pem8b.fm.2.0
June 10, 2003 Page 549 of 785
orcx orcx
OR with Complement (x7C00 0338)
orc rA,rS,rB (Rc = 0)

orc. rA,rS,rB (Rc = 1)
31 S A B 412 Rc
0 5 6 10 11 15 16 20 21 30 31
rA (rS) | (rB)
The contents of rS are ORed with the complement of the contents of rB and the result is placed into rA.

UISA X
pem8b.fm.2.0
Page 550 of 785 June 10, 2003
ori ori
OR Immediate (x6000 0000)
ori rA,rS,UIMM
[POWER mnemonic: oril]
24 S A UIMM
0 5 6 10 11 15 16 31
rA (rS) | ((4816)0 || UIMM)

The contents of rS are ORed with 0x0000_0000_0000 || UIMM and the result is placed into rA.
The preferred no-op (an instruction that does nothing) is ori 0,0,0.

None
nop equivalent to ori 0,0,0
UISA D
pem8b.fm.2.0
June 10, 2003 Page 551 of 785
oris oris
OR Immediate Shifted (x6400 0000)
oris rA,rS,UIMM
[POWER mnemonic: oriu]
25 S A UIMM
0 5 6 10 11 15 16 31
rA (rS) | ((32)0 || UIMM || (16)0)

The contents of rS are ORed with 0x0000_0000 || UIMM || 0x0000 and the result is placed into rA.

None
UISA D
pem8b.fm.2.0
Page 552 of 785 June 10, 2003
rfi rfi
Return from Interrupt (x4C00 0064)
Reserved
19 00 000 0 0000 0000 0 50 0
0 5 6 10 11 15 16 20 21 30 31
MSR[1623, 2527, 3031] SRR1[1623, 2527, 3031]

NIA iea SRR0[029] || 0b00
Bits SRR1[1623, 2527, 3031] are placed into the corresponding bits of the MSR. If the new MSR value
does not enable any pending exceptions, then the next instruction is fetched, under control of the new MSR
value, from the address SRR0[029] || 0b00. If the new MSR value enables one or more pending exceptions,
the exception associated with the highest priority pending exception is generated; in this case the value
placed into SRR0 by the exception processing mechanism is the address of the instruction that would have
been executed next had the exception not occurred. Note that an implementation may define additional MSR
bits, and in this case, may also cause them to be saved to SRR1 from MSR on an exception and restored to
MSR from SRR1 on an rfid (or rfi).
This is a supervisor-level, context synchronizing instruction. This instruction is defined only for 32-bit imple-
mentations. Using it on a 64-bit implementation causes an illegal instruction type program exception.

MSR

The rfi instruction may optionally be provided by a 64-bit implementation. The operation of the rfi
instruction in a 64-bit implementation is identical to the operation in a 32-bit implementation, except as
described below:
The SRR1 bits that are copied to the corresponding bits of the MSR are bits 4855, 5759 and 62
63 of SRR1. Note that depending on the implementation, additional bits from SRR1 may be restored
to the MSR. The remaining bits of the MSR, including the high-order bits, are unchanged.
If the new MSR value does not enable any pending exceptions, then the next instruction is fetched
under control of the new MSR value from the address SRR0[061 || 0b00 (when SF = 1 in the new
MSR value), or from 0x0000_0000 || SRR[3261] ||0b00 (when SF = 0 in the new MSR value).
When the optional rfi instruction is provided in a 64-bit implementation, the optional mtmsr instruction is
also provided. Refer to the mtmsr instruction description for additional detail about the operation of the
mtmsr instruction in 64-bit implementations.
OEA XL
pem8b.fm.2.0
June 10, 2003 Page 553 of 785
rfid 64-Bit Implementations Only rfid

Return from Interrupt Double Word (x4C00 0024)
Reserved
19 00 000 0 0000 0000 0 18 0
0 5 6 10 11 15 16 20 21 30 31
MSR[0, 4855, 5759, 6263] SRR1[0, 4855, 5759, 6263]

NIA iea SRR0[061] || 0b00
Bits SRR1[0, 4855, 5759, 6263] are placed into the corresponding bits of the MSR. If the new MSR value
does not enable any pending exceptions, then the next instruction is fetched, under control of the new MSR
value, from the address SRR0[061] || 0b00 (when
MSR[SF] = 1) or 0x0000_0000 || SRR0[3261] || 0b00 (when MSR[SF] = 0). If the new MSR value enables
one or more pending exceptions, the exception associated with the highest priority pending exception is
generated; in this case the value placed into SRR0 by the exception processing mechanism is the address of
the instruction that would have been executed next had the exception not occurred. Note that an implementa-
tion may define additional MSR bits, and in this case, may also cause them to be saved to SRR1 from MSR
on an exception and restored to MSR from SRR1 on an rfid.
This is a supervisor-level, context synchronizing instruction.

MSR
OEA XL
pem8b.fm.2.0
Page 554 of 785 June 10, 2003
rldclx 64-Bit Implementations Only rldclx

Rotate Left Double Word then Clear Left (x7800 0010)
rldcl rA,rS,rB,MB (Rc = 0)

rldcl. rA,rS,rB,MB (Rc = 1)
30 S A B mb* 8 Rc
0 5 6 10 11 15 16 20 21 26 27 30 31
n rB[5863]
r ROTL[64](rS, n)
b mb[5] || mb[04]
m MASK(b, 63)
rA r & m
The contents of rS are rotated left the number of bits specified by operand in the low-order six bits of rB. A
mask is generated having 1 bits from bit MB through bit 63 and 0 bits elsewhere. The rotated data is ANDed
with the generated mask and the result is placed into rA.
Note that the rldcl instruction can be used to extract and rotate bit fields using the methods shown below:
To extract an n-bit field, that starts at variable bit position b in register rS, right-justified into rA (clearing
the remaining 64 n bits of rA), set the low-order six bits of rB to b + n and MB = 64 n.
To rotate the contents of a register left by variable n bits, set the low-order six bits of rB to n and MB = 0,
and to shift the contents of a register right, set the low-order six bits of rB to(64 n), and MB = 0.

rotld rA,rS,rB equivalent to rldcl rA,rS,rB,0
UISA MDS
pem8b.fm.2.0
June 10, 2003 Page 555 of 785
rldcrx 64-Bit Implementations Only rldcrx

Rotate Left Double Word then Clear Right (x7800 0012)
rldcr rA,rS,rB,ME (Rc = 0)

rldcr. rA,rS,rB,ME (Rc = 1)
30 S A B me* 9 Rc
0 5 6 10 11 15 16 20 21 26 27 30 31
n rB[5863]
r ROTL[64](rS, n)
e me[5] || me[04]
m MASK(0, e)
rA r & m
The contents of rS are rotated left the number of bits specified by the low-order six bits of rB. A mask is
generated having 1 bits from bit 0 through bit ME and 0 bits elsewhere. The rotated data is ANDed with the
generated mask and the result is placed into rA.
Note that rldcr can be used to extract and rotate bit fields using the methods shown below:
To extract an n-bit field, that starts at variable bit position b in register rS, left-justified into rA (clearing the
remaining 64 n bits of rA), set the low-order six bits of rB to b and ME = n 1.
To rotate the contents of a register left by variable n bits, set the low-order six bits of rB to n and ME = 63,
and to shift the contents of a register right, set the low-order six bits of rB to(64 n), and ME = 63.

For a detailed list of simplified mnemonics for the rldcr instruction, refer to Appendix F. , Simplified
Mnemonics.
UISA MDS
pem8b.fm.2.0
Page 556 of 785 June 10, 2003
rldicx 64-Bit Implementations Only rldicx

Rotate Left Double Word Immediate then Clear (x7800 0008)
rldic rA,rS,SH,MB (Rc = 0)

rldic. rA,rS,SH,MB (Rc = 1)
30 S A sh* mb* 2 sh* Rc

0 5 6 10 11 15 16 20 21 26 27 29 30 31
n sh[5] || sh[04]
r ROTL[64](rS, n)
b mb[5] || mb[04]
m MASK(b, n)
rA r & m
The contents of rS are rotated left the number of bits specified by operand SH. A mask is generated having 1
bits from bit MB through bit 63 SH and 0 bits elsewhere. The rotated data is ANDed with the generated
mask and the result is placed into rA.
Note that rldic can be used to clear and shift bit fields using the methods shown below:
To clear the high-order b bits of the contents of a register and then shift the result left by n bits, set SH = n
and MB = b n.
To clear the high-order n bits of a register, set SH = 0 and MB = n.

clrlsldi rA,rS,b,nequivalent torldicrA,rS,n,b n
For a more detailed list of simplified mnemonics for the rldic instruction, refer to Appendix F. , Simplified
Mnemonics.
UISA MD
pem8b.fm.2.0
June 10, 2003 Page 557 of 785
rldiclx 64-Bit Implementations Only rldiclx

Rotate Left Double Word Immediate then Clear Left (x7800 0000)
rldicl rA,rS,SH,MB (Rc = 0)

rldicl. rA,rS,SH,MB (Rc = 1)

0 5 6 10 11 15 16 20 21 26 27 29 30 31
n sh[5] || sh[04]
r ROTL[64](rS, n)
b mb[5] || mb[04]
m MASK(b, 63)
rA r & m
bits from bit MB through bit 63 and 0 bits elsewhere. The rotated data is ANDed with the generated mask and
the result is placed into rA.
Note that rldicl can be used to extract, rotate, shift, and clear bit fields using the methods shown below:
To extract an n-bit field, that starts at bit position b in rS, right-justified into rA (clearing the remaining 64
n bits of rA), set SH = b + n and MB = 64 n.
To rotate the contents of a register left by n bits, set SH = n and MB = 0; to rotate the contents of a regis-
ter right by n bits, set SH = (64 n), and MB = 0.
To shift the contents of a register right by n bits, set SH = 64 n and MB = n.
To clear the high-order n bits of a register, set SH = 0 and MB = n.

extrdi rA,rS,n,b (n > 0) equivalent to rldicl rA,rS,b + n,64 n

rotldi rA,rS,n equivalent to rldicl rA,rS,n,0
rotrdi rA,rS,n equivalent to rldicl rA,rS,64 n,0
srdi rA,rS,n (n < 64) equivalent to rldicl rA,rS,64 n,n
clrldi rA,rS,n (n < 64) equivalent to rldicl rA,rS,0,n
UISA MD
pem8b.fm.2.0
Page 558 of 785 June 10, 2003
rldicrx 64-Bit Implementations Only rldicrx

Rotate Left Double Word Immediate then Clear Right (x7800 0004)
rldicr rA,rS,SH,ME (Rc = 0)

rldicr. rA,rS,SH,ME (Rc = 1)
30 S A sh* me* 1 sh* Rc

0 5 6 10 11 15 16 20 21 26 27 29 30 31
n sh[5] || sh[04]
r ROTL[64](rS, n)
e me[5] || me[04]
m MASK(0, e)
rA r & m
bits from bit 0 through bit ME and 0 bits elsewhere. The rotated data is ANDed with the generated mask and
the result is placed into rA.
Note that rldicr can be used to extract, rotate, shift, and clear bit fields using the methods shown below:
To extract an n-bit field, that starts at bit position b in rS, left-justified into rA (clearing the remaining 64
n bits of rA), set SH = b and ME = n 1.
To rotate the contents of a register left (right) by n bits, set SH = n (64 n) and
ME = 63.
To shift the contents of a register left by n bits, by setting SH = n and ME = 63 n.
To clear the low-order n bits of a register, by setting SH = 0 and ME = 63 n.

extldi rA,rS,n,b equivalent to rldicr rA,rS,b,n 1

sldi rA,rS,n equivalent to rldicr rA,rS,n,63 n
clrrdi rA,rS,n equivalent to rldicr rA,rS,0,63 n
UISA MD
pem8b.fm.2.0
June 10, 2003 Page 559 of 785
rldimix 64-Bit Implementations Only rldimix

Rotate Left Double Word Immediate then Mask Insert (x7800 000C)
rldimi rA,rS,SH,MB (Rc = 0)

rldimi. rA,rS,SH,MB (Rc = 1)

0 5 6 10 11 15 16 20 21 26 27 29 30 31
n sh[5] || sh[04]
r ROTL[64](rS, n)
b mb[5] || mb[04]
m MASK(b, n)
rA (r & m) | (rA & m)
bits from bit MB through bit 63 SH and 0 bits elsewhere. The rotated data is inserted into rA under control of
the generated mask.
Note that rldimi can be used to insert an n-bit field, that is right-justified in rS, into rA starting at bit position b,
by setting SH = 64 (b + n) and MB = b.

insrdi rA,rS,n,b equivalent to rldimi rA,rS,64 (b + n),b
For a more detailed list of simplified mnemonics for the rldimi instruction, refer to Appendix F. , Simplified
Mnemonics.
UISA MD
pem8b.fm.2.0
Page 560 of 785 June 10, 2003
rlwimix rlwimix
Rotate Left Word Immediate then Mask Insert (x5000 0000)
rlwimi rA,rS,SH,MB,ME (Rc = 0)

rlwimi. rA,rS,SH,MB,ME (Rc = 1)
[POWER mnemonics: rlimi, rlimi.]
20 S A SH MB ME Rc
0 5 6 10 11 15 16 20 21 25 26 30 31
n SH
r ROTL[32](rS[3263], n)
m MASK(MB + 32, ME + 32)
rA (r & m) | (rA & m)
bits from bit MB + 32 through bit ME + 32 and 0 bits elsewhere. The rotated data is inserted into rA under
control of the generated mask.
Note that rlwimi can be used to insert a bit field into the contents of rA using the methods shown below:
To insert an n-bit field, that is left-justified in the low-order 32 bits of rS, into the high-order 32 bits of rA
starting at bit position b, set SH = 32 b, MB = b, and
ME = (b + n) 1.
To insert an n-bit field, that is right-justified in the low-order 32 bits of rS, into the high-order 32 bits of rA
starting at bit position b, set SH = 32 (b + n), MB = b, and ME = (b + n) 1.

inslwi rA,rS,n,b equivalent to rlwimirA,rS,32 b,b,b + n 1

insrwi rA,rS,n,b (n > 0)equivalent to rlwimi rA,rS,32 (b + n),b,(b + n) 1
UISA M
pem8b.fm.2.0
June 10, 2003 Page 561 of 785
rlwinmx rlwinmx
Rotate Left Word Immediate then AND with Mask (x5400 0000)
rlwinm rA,rS,SH,MB,ME (Rc = 0)

rlwinm. rA,rS,SH,MB,ME (Rc = 1)
[POWER mnemonics: rlinm, rlinm.]
21 S A SH MB ME Rc
0 5 6 10 11 15 16 20 21 25 26 30 31
n SH
r ROTL[32](rS[3263], n)
m MASK(MB + 32, ME + 32)
rA r & m
The contents of rS[32-63] are rotated left the number of bits specified by operand SH. A mask is generated
having 1 bits from bit MB + 32 through bit ME + 32 and 0 bits elsewhere. The rotated data is ANDed with the
generated mask and the result is placed into rA. The upper 32 bits of rA are cleared.
Note that rlwinm can be used to extract, rotate, shift, and clear bit fields using the methods shown below:
To extract an n-bit field, that starts at bit position b in the high-order 32 bits of rS, right-justified into rA
(clearing the remaining 32 n bits of rA), set SH = b + n,
MB = 32 n, and ME = 31.
To extract an n-bit field, that starts at bit position b in the high-order 32 bits of rS, left-justified into rA
(clearing the remaining 32 n bits of rA), set SH = b, MB = 0, and ME = n 1.
To rotate the contents of a register left (or right) by n bits, set SH = n (32 n),
MB = 0, and ME = 31.
To shift the contents of a register right by n bits, by setting SH = 32 n, MB = n, and ME = 31. It can be
used to clear the high-order b bits of a register and then shift the result left by n bits by setting SH = n, MB
= b n and ME = 31 n.
To clear the low-order n bits of a register, by setting SH = 0, MB = 0, and
ME = 31 n.
For all uses mentioned, the high-order 32 bits of rA are cleared.

extlwi rA,rS,n,b (n > 0) equivalent torlwinm rA,rS,b,0,n 1

extrwi rA,rS,n,b (n > 0) equivalent torlwinm rA,rS,b + n,32 n,31
rotlwi rA,rS,n equivalent to rlwinm rA,rS,n,0,31
rotrwi rA,rS,n equivalent to rlwinm rA,rS,32 n,0,31
slwi rA,rS,n (n < 32) equivalent torlwinm rA,rS,n,0,31n
srwi rA,rS,n (n < 32) equivalent torlwinm rA,rS,32 n,n,31
pem8b.fm.2.0
Page 562 of 785 June 10, 2003
clrlwi rA,rS,n (n < 32) equivalent torlwinm rA,rS,0,n,31

clrrwi rA,rS,n (n < 32) equivalent torlwinm rA,rS,0,0,31 n
clrlslwi rA,rS,b,n (n b < 32) equivalent torlwinm rA,rS,n,b n,31 n
UISA M
pem8b.fm.2.0
June 10, 2003 Page 563 of 785
rlwnmx rlwnmx
Rotate Left Word then AND with Mask (x5C00 0000)
rlwnm rA,rS,rB,MB,ME (Rc = 0)

rlwnm. rA,rS,rB,MB,ME (Rc = 1)
[POWER mnemonics: rlnm, rlnm.]
23 S A B MB ME Rc
0 5 6 10 11 15 16 20 21 25 26 30 31
n rB[596327-31]
r ROTL[32](rS[3263], n)
m MASK(MB + 32, ME + 32)
rA r & m
The contents of rS are rotated left the number of bits specified by the low-order five bits of rB. A mask is
generated having 1 bits from bit MB + 32 through bit ME + 32 and 0 bits elsewhere. The rotated data is
ANDed with the generated mask and the result is placed into rA.
Note that rlwnm can be used to extract and rotate bit fields using the methods shown as follows:
To extract an n-bit field, that starts at variable bit position b in the high-order 32 bits of rS, right-justified
into rA (clearing the remaining 32 n bits of rA), by setting the low-order five bits of rB to b + n, MB = 32
n, and ME = 31.
To extract an n-bit field, that starts at variable bit position b in the high-order 32 bits of rS, left-justified into
rA (clearing the remaining 32 n bits of rA), by setting the low-order five bits of rB to b, MB = 0, and ME
= n 1.
To rotate the contents of a register left (or right) by n bits, by setting the low-order five bits of rB to n (32
n), MB = 0, and ME = 31.
For all uses mentioned, the high-order 32 bits of rA are cleared.

rotlw rA,rS,rB equivalent to rlwnm rA,rS,rB,0,31
UISA M
pem8b.fm.2.0
Page 564 of 785 June 10, 2003
sc sc
System Call (x4400 0002)
[POWER mnemonic: svca]
Reserved
17 00 000 0 0000 0000 0000 0000 00 1 0
0 5 6 10 11 15 16 29 30 31
In the PowerPC UISA, the sc instruction calls the operating system to perform a service. When control is
returned to the program that executed the system call, the content of the registers depends on the register
conventions used by the program providing the system service.
This instruction is context synchronizing, as described in Section 4.1.5.1 , Context Synchronizing Instruc-
tions.

Dependent on the system service
In PowerPC OEA, the sc instruction does the following:

SRR0 iea CIA + 4
SRR1[33361-4, 424710-15] 0
SRR1[0, 48551623, 57592527, 62633031] MSR[0, 48551623, 57592527, 626330
31]
MSR new_value (see below)
NIA iea base_ea + 0xC00 (see below)
The EA of the instruction following the sc instruction is placed into SRR0. Bits 0, 48551623, 57592527,
and 62633031 of the MSR are placed into the corresponding bits of SRR1, and bits 33361-4 and 42
4710-15 of SRR1 are set to undefined values. Note that an implementation may define additional MSR bits,
and in this case, may also cause them to be saved to SRR1 from MSR on an exception and restored to MSR
from SRR1 on an rfid (or rfi).
Then a system call exception is generated. The exception causes the MSR to be altered as described in
Section 6.4 , Exception Definitions.
The exception causes the next instruction to be fetched from offset 0xC00 from the physical base address
determined by the new setting of MSR[IP].

SRR0
SRR1
MSR
UISA/OEA SC
pem8b.fm.2.0
June 10, 2003 Page 565 of 785
slbia 64-Bit Implementations Only slbia

SLB Invalidate All (x7C00 03E4)
Reserved
31 00 000 0 0000 0000 0 498 0

0 5 6 10 11 15 16 20 21 30 31
All SLB entries invalid

The entire segment lookaside buffer (SLB) is made invalid (that is, all entries are removed).
The SLB is invalidated regardless of the settings of MSR[IR] and MSR[DR].
This instruction is supervisor-level.
This instruction is defined only for 64-bit implementations. Using it on a 32-bit implementation will cause an
It is not necessary that the ASR point to a valid segment table when issuing slbia.

None
OEA X
pem8b.fm.2.0
Page 566 of 785 June 10, 2003
slbie 64-Bit Implementations Only slbie

SLB Invalidate Entry (x7C00 0364)
slbie rB
Reserved
31 00 000 0 0000 B 434 0
0 5 6 10 11 15 16 20 21 30 31
EA (rB)
if SLB entry exists for EA, then
SLB entry invalid
EA is the contents of rB. If the segment lookaside buffer (SLB) contains an entry corresponding to EA, that
entry is made invalid (that is, removed from the SLB).
The SLB search is done regardless of the settings of MSR[IR] and MSR[DR].
Block address translation for EA, if any, is ignored.
This instruction is supervisor-level and optional in the PowerPC architecture.
This instruction is defined only for 64-bit implementations. Using it on a 32-bit implementation will cause an
It is not necessary that the ASR point to a valid segment table when issuing slbie.
Note that bits 1115 of this instruction (ordinarily the position of an rA field) must be zero. This provides
implementations the option of using (rA|0) + rB address arithmetic for this instruction.

None
OEA X
pem8b.fm.2.0
June 10, 2003 Page 567 of 785
sldx 64-Bit Implementations Only sldx

Shift Left Double Word (x7C00 0036)
sld rA,rS,rB (Rc = 0)

sld. rA,rS,rB (Rc = 1)
31 S A B 27 Rc
0 5 6 10 11 15 16 20 21 30 31
n rB[5863]
r ROTL[64](rS, n)
if rB[57] = 0 then
m MASK(0, 63 n)
else m (64)0
rA r & m
The contents of rS are shifted left the number of bits specified by the low-order seven bits of rB. Bits shifted
out of position 0 are lost. Zeros are supplied to the vacated positions on the right. The result is placed into rA.
Shift amounts from 64 to 127 give a zero result.

UISA X
pem8b.fm.2.0
Page 568 of 785 June 10, 2003
slwx slwx
Shift Left Word (x7C00 0030)
slw rA,rS,rB (Rc = 0)

slw. rA,rS,rB (Rc = 1)
[POWER mnemonics: sl, sl.]
31 S A B 24 Rc
0 5 6 10 11 15 16 20 21 30 31
n rB[596327-31]
r ROTL[32](rS[3263], n)
if rB[58] = 0 then
m MASK(32, 63 n)
else m (64)0
rA r & m
The contents of the low-order 32 bits of rS are shifted left the number of bits specified by the low-order six bits
of rB. Bits shifted out of position 32 are lost. Zeros are supplied to the vacated positions on the right. The 32-
bit result is placed into the low-order 32 bits of rA. The high-order 32 bits of rA are cleared. Shift amounts
from 32 to 63 give a zero result.
If bit 26 of rB = 0, the contents of rS are shifted left the number of bits specified by
rB[2731]. Bits shifted out of position 0 are lost. Zeros are supplied to the vacated positions on the right. The
32-bit result is placed into rA. If bit 26 of rB = 1, 32 zeros are placed into rA.

UISA X
pem8b.fm.2.0
June 10, 2003 Page 569 of 785
sradx 64-Bit Implementations Only sradx

Shift Right Algebraic Double Word (x7C00 0634)
srad rA,rS,rB (Rc = 0)

srad. rA,rS,rB (Rc = 1)
31 S A B 794 Rc
0 5 6 10 11 15 16 20 21 30 31
n rB[5863]
r ROTL[64](rS, 64 n)
if rB[57] = 0 then
m MASK(n, 63)
else m (64)0
S rS[0]
rA (r & m) | (((64)S) & m)
XER[CA] S & ((r & m) 0)
The contents of rS are shifted right the number of bits specified by the low-order seven bits of rB. Bits shifted
out of position 63 are lost. Bit 0 of rS is replicated to fill the vacated positions on the left. The result is placed
into rA. XER[CA] is set if rS is negative and any 1 bits are shifted out of position 63; otherwise XER[CA] is
cleared. A shift amount of zero causes rA to be set equal to rS, and XER[CA] to be cleared. Shift amounts
from 64 to 127 give a result of 64 sign bits in rA, and cause XER[CA] to receive the sign bit of rS.
Note that the srad instruction, followed by addze, can by used to divide quickly by 2n. The setting of the CA
bit, by srad, is independent of mode.

XER:
Affected: CA
UISA X
pem8b.fm.2.0
Page 570 of 785 June 10, 2003
sradix 64-Bit Implementations Only sradix

Shift Right Algebraic Double Word Immediate (x7C00 0674)
sradi rA,rS,SH (Rc = 0)

sradi. rA,rS,SH (Rc = 1)
31 S A sh* 413 sh* Rc
0 5 6 10 11 15 16 20 21 30 31
n sh[5] || sh[04]
m MASK(n, 63)
S rS[0]
rA (r & m) | (((64)S) & m)
XER[CA] S & ((r & m) 0)
The contents of rS are shifted right SH bits. Bits shifted out of position 63 are lost. Bit 0 of rS is replicated to
fill the vacated positions on the left. The result is placed into rA. XER[CA] is set if rS is negative and any 1 bits
are shifted out of position 63; otherwise XER[CA] is cleared. A shift amount of zero causes rA to be set equal
to rS, and XER[CA] to be cleared.
Note that the sradi instruction, followed by addze, can by used to divide quickly by 2n. The setting of the
XER[CA] bit, by sradi, is independent of mode.

XER:
Affected: CA
UISA XS
pem8b.fm.2.0
June 10, 2003 Page 571 of 785
srawx srawx
Shift Right Algebraic Word (x7C00 0630)
sraw rA,rS,rB (Rc = 0)

sraw. rA,rS,rB (Rc = 1)
[POWER mnemonics: sra, sra.]
31 S A B 792 Rc
0 5 6 10 11 15 16 20 21 30 31
n rB[596327-31]
r ROTL[32](rS[3263], 64 n)
if rB[5826] = 0 then
m MASK(n + 32, 63)
else m (6432)0
S rS[32]
rA r & m | (64)S & m
XER[CA] S & (r & m[3263] 0
The contents of the low-order 32 bits of rS are shifted right the number of bits specified by the low-order six
bits of rB. Bits shifted out of position 63 are lost. Bit 32 of rS is replicated to fill the vacated positions on the
left. The 32-bit result is placed into the low-order 32 bits of rA. Bit 32 of rS is replicated to fill the high-order 32
bits of rA. XER[CA] is set if the low-order 32 bits of rS contain a negative number and any 1 bits are shifted
out of position 63; otherwise XER[CA] is cleared. A shift amount of zero causes rA to receive the sign-
extended value of the low-order 32 bits of rS, and XER[CA] to be cleared. Shift amounts from 32 to 63 give a
result of 64 sign bits, and cause XER[CA] to receive the sign bit of the low-order 32 bits of rS.If rB[26] =
0,then the contents of rS are shifted right the number of bits specified by
rB[2731]. Bits shifted out of position 31 are lost. The result is padded on the left with sign bits before being
placed into rA. If rB[26] = 1, then rA is filled with 32 sign bits (bit 0) from rS. CR0 is set based on the value
written into rA. XER[CA] is set if rS contains a negative number and any 1 bits are shifted out of position 31;
otherwise XER[CA] is cleared. A shift amount of zero causes XER[CA] to be cleared.
Note that the sraw instruction, followed by addze, can by used to divide quickly by 2n. The setting of the
XER[CA] bit, by sraw, is independent of mode.

XER:
Affected: CA
UISA X
pem8b.fm.2.0
Page 572 of 785 June 10, 2003
srawix srawix
Shift Right Algebraic Word Immediate (x7C00 0670)
srawi rA,rS,SH (Rc = 0)

srawi. rA,rS,SH (Rc = 1)
[POWER mnemonics: srai, srai.]
31 S A SH 824 Rc
0 5 6 10 11 15 16 20 21 30 31
n SH
r ROTL[32](rS[3263], 6432 n)
m MASK(n + 32, 63)
S rS[32]
rA r & m | (64)S & m
XER[CA] S & ((r & m)[3263] 0)
The contents of the low-order 32 bits of rS are shifted right SH bits. Bits shifted out of position 63 are lost. Bit
32 of rS is replicated to fill the vacated positions on the left. The 32-bit result is placed into the low-order 32
bits of rA. Bit 32 of rS is replicated to fill the high-order 32 bits of rA. XER[CA] is set if the low-order 32 bits of
rS contain a negative number and any 1 bits are shifted out of position 63; otherwise XER[CA] is cleared. A
shift amount of zero causes rA to receive the sign-extended value of the low-order 32 bits of rS, and XER[CA]
to be cleared.The contents of rS are shifted right the number of bits specified by operand SH. Bits shifted out
of position 31 are lost. The shifted value is sign-extended before being placed in rA. The 32-bit result is
placed into rA. XER[CA] is set if rS contains a negative number and any 1 bits are shifted out of position 31;
otherwise XER[CA] is cleared. A shift amount of zero causes XER[CA] to be cleared.
Note that the srawi instruction, followed by addze, can be used to divide quickly by 2n. The setting of the CA
bit, by srawi, is independent of mode.

XER:
Affected: CA
UISA X
pem8b.fm.2.0
June 10, 2003 Page 573 of 785
srdx 64-Bit Implementations Only srdx

Shift Right Double Word (x7C00 0436)
srd rA,rS,rB (Rc = 0)

srd. rA,rS,rB (Rc = 1)
31 S A B 539 Rc
0 5 6 10 11 15 16 20 21 30 31
n rB[5863]
if rB[57] = 0 then
m MASK(n, 63)
else m (64)0
rA r & m
The contents of rS are shifted right the number of bits specified by the low-order seven bits of rB. Bits shifted
out of position 63 are lost. Zeros are supplied to the vacated positions on the left. The result is placed into rA.
Shift amounts from 64 to 127 give a zero result.

UISA X
pem8b.fm.2.0
Page 574 of 785 June 10, 2003
srwx srwx
Shift Right Word (x7C00 0430)
srw rA,rS,rB (Rc = 0)

srw. rA,rS,rB (Rc = 1)
[POWER mnemonics: sr, sr.]
31 S A B 536 Rc
0 5 6 10 11 15 16 20 21 30 31
n rB[586327-31]
r ROTL[32](rS[3263], 6432 n)
if rB[58] = 0 then
m MASK(n + 32, 63)
else m (64)0
rA r & m
The contents of the low-order 32 bits of rS are shifted right the number of bits specified by the low-order six
bits of rB. Bits shifted out of position 6331 are lost. Zeros are supplied to the vacated positions on the left. The
32-bit result is placed into the low-order 32 bits of rA. The high-order 32 bits of rA are cleared. Shift amounts
from 32 to 63 give a zero result.

UISA X
pem8b.fm.2.0
June 10, 2003 Page 575 of 785
stb stb
Store Byte (x9800 0000)
stb rS,d(rA)
38 S A d
0 5 6 10 11 15 16 31
if rA = 0 then b 0
else b (rA)
EA b + EXTS(d)
MEM(EA, 1) rS[566324-31]
EA is the sum (rA|0) + d. The contents of the low-order eight bits of rS are stored into the byte in memory
addressed by EA.

None
UISA D
pem8b.fm.2.0
Page 576 of 785 June 10, 2003
stbu stbu
Store Byte with Update (x9C00 0000)
stbu rS,d(rA)
39 S A d
0 5 6 10 11 15 16 31
EA (rA) + EXTS(d)
MEM(EA, 1) rS[566324-31]
rA EA
EA is the sum (rA) + d. The contents of the low-order eight bits of rS are stored into the byte in memory
addressed by EA.

None
UISA D
pem8b.fm.2.0
June 10, 2003 Page 577 of 785
stbux stbux
Store Byte with Update Indexed (x7C00 01EE)
stbux rS,rA,rB
Reserved
31 S A B 247 0
0 5 6 10 11 15 16 21 22 30 31
EA (rA) + (rB)
MEM(EA, 1) rS[566324-31]
rA EA
EA is the sum (rA) + (rB). The contents of the low-order eight bits of rS are stored into the byte in memory
addressed by EA.

None
UISA X
pem8b.fm.2.0
Page 578 of 785 June 10, 2003
stbx stbx
Store Byte Indexed (x7C00 01AE)
stbx rS,rA,rB
Reserved
31 S A B 215 0
0 5 6 10 11 15 16 21 22 30 31
if rA = 0 then b 0
else b (rA)
EA b + (rB)
MEM(EA, 1) rS[566324-31]
EA is the sum (rA|0) + (rB). The contents of the low-order eight bits of rS are stored into the byte in memory
addressed by EA.

None
UISA X
pem8b.fm.2.0
June 10, 2003 Page 579 of 785
std 64-Bit Implementations Only std

Store Double Word (xF800 0000)
std rS,ds(rA)
62 S A ds 00
0 5 6 10 11 15 16 29 30 31
if rA = 0 then b 0
else b (rA)
(MEM(EA, 8)) (rS)
EA is the sum (rA|0) + (ds || 0b00). The contents of rS are stored into the double word in memory addressed
by EA.

None
UISA DS
pem8b.fm.2.0
Page 580 of 785 June 10, 2003
stdcx. 64-Bit Implementations Only stdcx.

Store Double Word Conditional Indexed (x7C00 01AD)
stdcx. rS,rA,rB
31 S A B 214 1
0 5 6 10 11 15 16 20 21 30 31
if rA = 0 then b 0
else b (rA)
EA b + (rB)
if RESERVE then
if RESERVE_ADDR = physical_addr(EA)
MEM(EA, 8) (rS)
CR0 0b00 || 0b1 || XER[SO]
else
u undefined 1-bit value
if u then MEM(EA, 8) (rS)
CR0 0b00 || u || XER[SO]
RESERVE 0
else
CR0 0b00 || 0b0 || XER[SO]
If a reservation exists, and the memory address specified by the stdcx. instruction is the same as that speci-
fied by the load and reserve instruction that established the reservation, the contents of rS are stored into the
double word in memory addressed by EA and the reservation is cleared.
If a reservation exists, but the memory address specified by the stdcx. instruction is not the same as that
specified by the load and reserve instruction that established the reservation, the reservation is cleared, and it
is undefined whether the contents of rS are stored into the double word in memory addressed by EA.
If no reservation exists, the instruction completes without altering memory.
CR0 field is set to reflect whether the store operation was performed as follows.
CR0[LT GT EQ S0] = 0b00 || store_performed || XER[SO]
EA must be a multiple of eight. If it is not, either the system alignment exception handler is invoked or the
Note that, when used correctly, the load and reserve and store conditional instructions can provide an atomic
update function for a single aligned word (load word and reserve and store word conditional) or double word
(load double word and reserve and store double word conditional) of memory.
In general, correct use requires that load word and reserve be paired with store word conditional, and load
double word and reserve with store double word conditional, with the same memory address specified by
both instructions of the pair. The only exception is that an unpaired store word conditional or store double
word conditional instruction to any (scratch) EA can be used to clear any reservation held by the processor.
Examples of correct uses of these instructions, to emulate primitives such as fetch and add, test and set, and
compare and swap can be found in Appendix E. , Synchronization Programming Examples.
pem8b.fm.2.0
June 10, 2003 Page 581 of 785
A reservation is cleared if any of the following events occurs:

The processor holding the reservation executes another load and reserve instruction; this clears the first
reservation and establishes a new one.
The processor holding the reservation executes a store conditional instruction to any address.
Another processor executes any store instruction to the address associated with the reservation.]
Any mechanism, other than the processor holding the reservation, stores to the address associated with
the reservation.

UISA X
pem8b.fm.2.0
Page 582 of 785 June 10, 2003
stdu 64-Bit Implementations Only stdu

Store Double Word with Update (xF800 0001)
stdu rS,ds(rA)
62 S A ds 01
0 5 6 10 11 15 16 29 30 31
EA (rA) + EXTS(ds || 0b00)

(MEM(EA, 8)) (rS)
rA EA
EA is the sum (rA) + (ds || 0b00). The contents of rS are stored into the double word in memory addressed by
EA.

None
UISA DS
pem8b.fm.2.0
June 10, 2003 Page 583 of 785
stdux 64-Bit Implementations Only stdux

Store Double Word with Update Indexed (x7C00 016A)
stdux rS,rA,rB
Reserved
31 S A B 181 0
0 5 6 10 11 15 16 20 21 30 31
EA (rA) + (rB)
MEM(EA, 8) (rS)
rA EA
EA is the sum (rA) + (rB). The contents of rS are stored into the double word in memory addressed by EA.

None
UISA X
pem8b.fm.2.0
Page 584 of 785 June 10, 2003
stdx 64-Bit Implementations Only stdx

Store Double Word Indexed (x7C00 012A)
stdx rS,rA,rB
Reserved
31 S A B 149 0
0 5 6 10 11 15 16 20 21 30 31
if rA = 0 then b 0
else b (rA)
EA b + (rB)
(MEM(EA, 8)) (rS)
EA is the sum (rA|0) + (rB). The contents of rS are stored into the double word in memory addressed by EA.

None
UISA X
pem8b.fm.2.0
June 10, 2003 Page 585 of 785
stfd stfd
Store Floating-Point Double (xD800 0000)
stfd frS,d(rA)
54 S A d
0 5 6 10 11 15 16 30 31
if rA = 0 then b 0
else b (rA)
EA b + EXTS(d)
MEM(EA, 8) (frS)
The contents of register frS are stored into the double word in memory addressed by EA.

None
UISA D
pem8b.fm.2.0
Page 586 of 785 June 10, 2003
stfdu stfdu
Store Floating-Point Double with Update (xDC00 0000)
stfdu frS,d(rA)
55 S A d
0 5 6 10 11 15 16 31
EA (rA) + EXTS(d)
MEM(EA, 8) (frS)
rA EA

None
UISA D
pem8b.fm.2.0
June 10, 2003 Page 587 of 785
stfdux stfdux
Store Floating-Point Double with Update Indexed (x7C00 05EE)
stfdux frS,rA,rB
Reserved
31 S A B 759 0
0 5 6 10 11 15 16 20 21 30 31
EA (rA) + (rB)
MEM(EA, 8) (frS)
rA EA

None
UISA X
pem8b.fm.2.0
Page 588 of 785 June 10, 2003
stfdx stfdx
Store Floating-Point Double Indexed (x7C00 05AE)
stfdx frS,rA,rB
Reserved
31 S A B 727 0
0 5 6 10 11 15 16 20 21 30 31
if rA = 0 then b 0
else b (rA)
EA b + (rB)
MEM(EA, 8) (frS)
EA is the sum (rA|0) + rB.

None
UISA X
pem8b.fm.2.0
June 10, 2003 Page 589 of 785
stfiwx stfiwx
Store Floating-Point as Integer Word Indexed (x7C00 07AE)
stfiwx frS,rA,rB
Reserved
31 S A B 983 0
0 5 6 10 11 15 16 20 21 30 31
if rA = 0 then b 0
else b (rA)
EA b + (rB)
MEM(EA, 4) frS[3263]
The contents of the low-order 32 bits of register frS are stored, without conversion, into the word in memory
addressed by EA.
If the contents of register frS were produced, either directly or indirectly, by an lfs instruction, a single-preci-
sion arithmetic instruction, or frsp, then the value stored is undefined. The contents of frS are produced
directly by such an instruction if frS is the target register for the instruction. The contents of frS are produced
indirectly by such an instruction if frS is the final target register of a sequence of one or more floating-point
move instructions, with the input to the sequence having been produced directly by such an instruction.
This instruction is defined as optional by the PowerPC architecture to ensure backwards compatibility with
earlier processors; however, it will likely be required for subsequent PowerPC processors.

None
UISA X
pem8b.fm.2.0
Page 590 of 785 June 10, 2003
stfs stfs
Store Floating-Point Single (xD000 0000)
stfs frS,d(rA)
52 S A d
0 5 6 10 11 15 16 31
if rA = 0 then b 0
else b (rA)
EA b + EXTS(d)
MEM(EA, 4) SINGLE(frS)
The contents of register frS are converted to single-precision and stored into the word in memory addressed
by EA. Note that the value to be stored should be in single-precision format prior to the execution of the stfs
instruction. For a discussion on floating-point store conversions, see Section D.7 , Floating-Point Store
Instructions.

None
UISA D
pem8b.fm.2.0
June 10, 2003 Page 591 of 785
stfsu stfsu
Store Floating-Point Single with Update (xD400 0000)
stfsu frS,d(rA)
53 S A d
0 5 6 10 11 15 16 31
EA (rA) + EXTS(d)
rA EA
The contents of frS are converted to single-precision and stored into the word in memory addressed by EA.
Note that the value to be stored should be in single-precision format prior to the execution of the stfsu
instruction. For a discussion on floating-point store conversions, see Section D.7 , Floating-Point Store
Instructions.

None
UISA D
pem8b.fm.2.0
Page 592 of 785 June 10, 2003
stfsux stfsux
Store Floating-Point Single with Update Indexed (x7C00 056E)
stfsux frS,rA,rB
Reserved
31 S A B 695 0
0 5 6 10 11 15 16 20 21 30 31
EA (rA) + (rB)
rA EA
The contents of frS are converted to single-precision and stored into the word in memory addressed by EA.
For a discussion on floating-point store conversions, see Section D.7 , Floating-Point Store Instructions.

None
UISA X
pem8b.fm.2.0
June 10, 2003 Page 593 of 785
stfsx stfsx
Store Floating-Point Single Indexed (x7C00 052E)
stfsx frS,rA,rB
Reserved
31 S A B 663 0
0 5 6 10 11 15 16 20 21 30 31
if rA = 0 then b 0
else b (rA)
EA b + (rB)
The contents of register frS are converted to single-precision and stored into the word in memory addressed
by EA. For a discussion on floating-point store conversions, see Section D.7 , Floating-Point Store Instruc-
tions.

None
UISA X
pem8b.fm.2.0
Page 594 of 785 June 10, 2003
sth sth
Store Half Word (xB000 0000)
sth rS,d(rA)
44 S A d
0 5 6 10 11 15 16 31
if rA = 0 then b 0
else b (rA)
EA b + EXTS(d)
MEM(EA, 2) rS[486316-31]
EA is the sum (rA|0) + d. The contents of the low-order 16 bits of rS are stored into the half word in memory
addressed by EA.

None
UISA D
pem8b.fm.2.0
June 10, 2003 Page 595 of 785
sthbrx sthbrx
Store Half Word Byte-Reverse Indexed (x7C00 072C)
sthbrx rS,rA,rB
Reserved
31 S A B 918 0
0 5 6 10 11 15 16 20 21 30 31
if rA = 0 then b 0
else b (rA)
EA b + (rB)
MEM(EA, 2) rS[566324-31] || rS[485516-23]
EA is the sum (rA|0) + (rB). The contents of the low-order eight bits of rS are stored into bits 07 of the half
word in memory addressed by EA. The contents of the subsequent low-order eight bits of rS are stored into
bits 815 of the half word in memory addressed by EA.

None
UISA X
pem8b.fm.2.0
Page 596 of 785 June 10, 2003
sthu sthu
Store Half Word with Update (xB400 0000)
sthu rS,d(rA)
45 S A d
0 5 6 10 11 15 16 31
EA (rA) + EXTS(d)
MEM(EA, 2) rS[486316-31]
rA EA
EA is the sum (rA) + d. The contents of the low-order 16 bits of rS are stored into the half word in memory
addressed by EA.

None
UISA D
pem8b.fm.2.0
June 10, 2003 Page 597 of 785
sthux sthux
Store Half Word with Update Indexed (x7C00 036E)
sthux rS,rA,rB
Reserved
31 S A B 439 0
0 5 6 10 11 15 16 20 21 30 31
EA (rA) + (rB)
MEM(EA, 2) rS[486316-31]
rA EA
EA is the sum (rA) + (rB). The contents of the low-order 16 bits of rS are stored into the half word in memory
addressed by EA.

None
UISA X
pem8b.fm.2.0
Page 598 of 785 June 10, 2003
sthx sthx
Store Half Word Indexed (x7C00 032E)
sthx rS,rA,rB
Reserved
31 S A B 407 0
0 5 6 10 11 15 16 20 21 30 31
if rA = 0 then b 0
else b (rA)
EA b + (rB)
MEM(EA, 2) rS[486316-31]
EA is the sum (rA|0) + (rB). The contents of the low-order 16 bits of rS are stored into the half word in
memory addressed by EA.

None
UISA X
pem8b.fm.2.0
June 10, 2003 Page 599 of 785
stmw stmw
Store Multiple Word (xBC00 0000)
stmw rS,d(rA)
[POWER mnemonic: stm]
47 S A d
0 5 6 10 11 15 16 31
if rA = 0 then b 0
else b (rA)
EA b + EXTS(d)
r rS
do while r 31
MEM(EA, 4) GPR(r)[3263]
r r + 1
EA EA + 4
n = (32 rS).
n consecutive words starting at EA are stored from the low-order 32 bits of GPRs rS through r31. For
example, if rS = 30, 2 words are stored.
results.

None
UISA D
pem8b.fm.2.0
Page 600 of 785 June 10, 2003
stswi stswi
Store String Word Immediate (x7C00 05AA)
stswi rS,rA,NB
[POWER mnemonic: stsi]
Reserved
31 S A NB 725 0
0 5 6 10 11 15 16 20 21 30 31
if rA = 0 then EA 0
else EA (rA)
if NB = 0 then n 32
else n NB
r rS 1
i 32
do while n > 0
if i = 32 then r r + 1 (mod 32)
MEM(EA, 1) GPR(r)[ii + 7]
i i + 8
if i = 64 then i 32
EA EA + 1
n n 1
EA is (rA|0). Let n = NB if NB 0, n = 32 if NB = 0; n is the number of bytes to store. Let nr = CEIL(n 4); nr is

the number of registers to supply data.
n consecutive bytes starting at EA are stored from GPRs rS through rS + nr 1. Data is stored from the low-
order four bytes of each GPR. Bytes are stored left to right from each register. The sequence of registers
wraps around through r0 if required.
tion (0x00300).
results.

None
UISA X
pem8b.fm.2.0
June 10, 2003 Page 601 of 785
stswx stswx
Store String Word Indexed (x7C00 052A)
stswx rS,rA,rB
[POWER mnemonic: stsx]
Reserved
31 S A B 661 0
0 5 6 10 11 15 16 20 21 30 31
if rA = 0 then b 0
else b (rA)
EA b + (rB)
n XER[2531]
r rS 1
i 32
do while n > 0
if i = 32 then r r + 1 (mod 32)
MEM(EA, 1) GPR(r)[ii + 7]
i i + 8
if i = 64 then i 32
EA EA + 1
n n 1
EA is the sum (rA|0) + (rB). Let n = XER[2531]; n is the number of bytes to store. Let
nr = CEIL(n 4); nr is the number of registers to supply data.
n consecutive bytes starting at EA are stored from GPRs rS through rS + nr 1. Data is stored from the low-
order four bytes of each GPR. Bytes are stored left to right from each register. The sequence of registers
wraps around through r0 if required. If n = 0, no bytes are stored.
tion (0x00300).
results.

None
UISA X
pem8b.fm.2.0
Page 602 of 785 June 10, 2003
stw stw
Store Word (x9000 0000)
stw rS,d(rA)
[POWER mnemonic: st]
36 S A d
0 5 6 10 11 15 16 31
if rA = 0 then b 0
else b (rA)
EA b + EXTS(d)
MEM(EA, 4) rS[3263]
EA is the sum (rA|0) + d. The contents of the low-order 32 bits of rS are stored into the word in memory
addressed by EA.

None
UISA D
pem8b.fm.2.0
June 10, 2003 Page 603 of 785
stwbrx stwbrx
Store Word Byte-Reverse Indexed (x7C00 052C)
stwbrx rS,rA,rB
[POWER mnemonic: stbrx]
Reserved
31 S A B 662 0
0 5 6 10 11 15 16 20 21 30 31
if rA = 0 then b 0
else b (rA)
EA b + (rB)
MEM(EA, 4) rS[566324-31] || rS[485516-23] || rS[40478-15] || rS[32390-7]
EA is the sum (rA|0) + (rB). The contents of the low-order eight bits of rS are stored into bits 07 of the word
in memory addressed by EA. The contents of the subsequent eight low-order bits of rS are stored into bits 8
15 of the word in memory addressed by EA. The contents of the subsequent eight low-order bits of rS are
stored into bits 1623 of the word in memory addressed by EA. The contents of the subsequent eight low-
order bits of rS are stored into bits 2431 of the word in memory addressed by EA.

None
UISA X
pem8b.fm.2.0
Page 604 of 785 June 10, 2003
stwcx. stwcx.
Store Word Conditional Indexed (x7C00 012D)
stwcx. rS,rA,rB
31 S A B 150 1
0 5 6 10 11 15 16 20 21 30 31
if rA = 0 then b 0
else b (rA)
EA b + (rB)
if RESERVE then
if RESERVE_ADDR = physical_addr(EA)
MEM(EA, 4) rS[3263]
CR0 0b00 || 0b1 || XER[SO]
else
u undefined 1-bit value
if u then MEM(EA, 4) rS[3263]
CR0 0b00 || u || XER[SO]
RESERVE 0
else
CR0 0b00 || 0b0 || XER[SO]
EA is the sum (rA|0) + (rB). If the reserved bit is set, the stwcx. instruction stores rS to effective address (rA
+ rB), clears the reserved bit, and sets CR0[EQ]. If the reserved bit is not set, the stwcx. instruction does not
do a store; it leaves the reserved bit cleared and clears CR0[EQ]. Software must look at CR0[EQ] to see if the
stwcx. was successful.
The reserved bit is set by the lwarx instruction. The reserved bit is cleared by any stwcx. instruction to any
address, and also by snooping logic if it detects that another processor does any kind of store to the block
indicated in the reservation buffer when reserved is set.
If a reservation exists, and the memory address specified by the stwcx. instruction is the same as that speci-
fied by the load and reserve instruction that established the reservation, the contents of the low-order 32 bits
of rS are stored into the word in memory addressed by EA and the reservation is cleared.
If a reservation exists, but the memory address specified by the stwcx. instruction is not the same as that
specified by the load and reserve instruction that established the reservation, the reservation is cleared, and it
is undefined whether the contents of the low-order 32 bits of rS are stored into the word in memory addressed
by EA.
If no reservation exists, the instruction completes without altering memory.
CR0 field is set to reflect whether the store operation was performed as follows.
CR0[LT GT EQ S0] = 0b00 || store_performed || XER[SO]
pem8b.fm.2.0
June 10, 2003 Page 605 of 785
The granularity with which reservations are managed is implementation-dependent. Therefore, the memory
to be accessed by the load and reserve and store conditional instructions should be allocated by a system
library program.

UISA X
pem8b.fm.2.0
Page 606 of 785 June 10, 2003
stwu stwu
Store Word with Update (x9400 0000)
stwu rS,d(rA)
[POWER mnemonic: stu]
37 S A d
0 5 6 10 11 15 16 31
EA (rA) + EXTS(d)
MEM(EA, 4) rS[3263]
rA EA
EA is the sum (rA) + d. The contents of the low-order 32 bits of rS are stored into the word in memory
addressed by EA.

None
UISA D
pem8b.fm.2.0
June 10, 2003 Page 607 of 785
stwux stwux
Store Word with Update Indexed (x7C00 016E)
stwux rS,rA,rB
[POWER mnemonic: stux]
Reserved
31 S A B 183 0
0 5 6 10 11 15 16 20 21 30 31
EA (rA) + (rB)
MEM(EA, 4) rS[3263]
rA EA
EA is the sum (rA) + (rB). The contents of the low-order 32 bits of rS are stored into the word in memory
addressed by EA.

None
UISA X
pem8b.fm.2.0
Page 608 of 785 June 10, 2003
stwx stwx
Store Word Indexed (x7C00 012E)
stwx rS,rA,rB
[POWER mnemonic: stx]
Reserved
31 S A B 151 0
0 5 6 10 11 15 16 20 21 30 31
if rA = 0 then b 0
else b (rA)
EA b + (rB)
MEM(EA, 4) rS[3263]
EA is the sum (rA|0) + (rB). The contents of the low-order 32 bits of rS are is stored into the word in memory
addressed by EA.

None
UISA X
pem8b.fm.2.0
June 10, 2003 Page 609 of 785
subfx subfx
Subtract From (x7C00 0050)
subf rD,rA,rB (OE = 0 Rc = 0)

subf. rD,rA,rB (OE = 0 Rc = 1)
subfo rD,rA,rB (OE = 1 Rc = 0)
subfo. rD,rA,rB (OE = 1 Rc = 1)
31 D A B OE 40 Rc
0 5 6 10 11 15 16 20 21 22 30 31
rD (rA) + (rB) + 1
The sum (rA) + (rB) + 1 is placed into rD.
The subf instruction is preferred for subtraction because it sets few status bits.

XER:
sub rD,rA,rB equivalent to subf rD,rB,rA
UISA XO
pem8b.fm.2.0
Page 610 of 785 June 10, 2003
subfcx subfcx
Subtract from Carrying (x7C00 0010)
subfc rD,rA,rB (OE = 0 Rc = 0)

subfc. rD,rA,rB (OE = 0 Rc = 1)
subfco rD,rA,rB (OE = 1 Rc = 0)
subfco. rD,rA,rB (OE = 1 Rc = 1)
[POWER mnemonics: sf, sf., sfo, sfo.]
31 D A B OE 8 Rc
0 5 6 10 11 15 16 20 21 22 30 31
rD (rA) + (rB) + 1
The sum (rA) + (rB) + 1 is placed into rD.

XER:
Affected: CA
about 64-bit mode and 32-bit mode in 64-bit implementations, see 3. , Operand Conventions.
subc rD,rA,rB equivalent to subfc rD,rB,rA
UISA XO
pem8b.fm.2.0
June 10, 2003 Page 611 of 785
subfex subfex
Subtract from Extended (x7C00 0110)
subfe rD,rA,rB (OE = 0 Rc = 0)

subfe. rD,rA,rB (OE = 0 Rc = 1)
subfeo rD,rA,rB (OE = 1 Rc = 0)
subfeo. rD,rA,rB (OE = 1 Rc = 1)
[POWER mnemonics: sfe, sfe., sfeo, sfeo.]
31 D A B OE 136 Rc
0 5 6 10 11 15 16 20 21 22 30 31
rD (rA) + (rB) + XER[CA]

The sum (rA) + (rB) + XER[CA] is placed into rD.

XER:
Affected: CA
UISA XO
pem8b.fm.2.0
Page 612 of 785 June 10, 2003
subfic subfic
Subtract from Immediate Carrying (x2000 0000)
subfic rD,rA,SIMM
[POWER mnemonic: sfi]
08 D A SIMM
0 5 6 10 11 15 16 31
rD (rA) + EXTS(SIMM) + 1
The sum (rA) + EXTS(SIMM) + 1 is placed into rD.

XER:
Affected: CA
UISA D
pem8b.fm.2.0
June 10, 2003 Page 613 of 785
subfmex subfmex
Subtract from Minus One Extended (x7C00 01D0)
subfme rD,rA (OE = 0 Rc = 0)

subfme. rD,rA (OE = 0 Rc = 1)
subfmeo rD,rA (OE = 1 Rc = 0)
subfmeo. rD,rA (OE = 1 Rc = 1)
[POWER mnemonics: sfme, sfme., sfmeo, sfmeo.]
Reserved
31 D A 0000 0 OE 232 Rc
0 5 6 10 11 15 16 20 21 22 30 31
rD (rA) + XER[CA] 1
The sum (rA) + XER[CA] + (6432)1 is placed into rD.

XER:
Affected: CA
UISA XO
pem8b.fm.2.0
Page 614 of 785 June 10, 2003
subfzex subfzex
Subtract from Zero Extended (x7C00 0190)
subfze rD,rA (OE = 0 Rc = 0)

subfze. rD,rA (OE = 0 Rc = 1)
subfzeo rD,rA (OE = 1 Rc = 0)
subfzeo. rD,rA (OE = 1 Rc = 1)
[POWER mnemonics: sfze, sfze., sfzeo, sfzeo.]
Reserved
31 D A 0000 0 OE 200 Rc
0 5 6 10 11 15 16 20 21 22 30 31
rD (rA) + XER[CA]
The sum (rA) + XER[CA] is placed into rD.

XER:
Affected: CA
UISA XO
pem8b.fm.2.0
June 10, 2003 Page 615 of 785
sync sync
Synchronize (x7C00 04AC)
[POWER mnemonic: dcs]
Reserved
31 00 000 0 0000 0000 0 598 0
0 5 6 10 11 15 16 20 21 30 31
The sync instruction provides an ordering function for the effects of all instructions executed by a given
processor. Executing a sync instruction ensures that all instructions preceding the sync instruction appear to
have completed before the sync instruction completes, and that no subsequent instructions are initiated by
the processor until after the sync instruction completes. When the sync instruction completes, all external
accesses caused by instructions preceding the sync instruction will have been performed with respect to all
other mechanisms that access memory. For more information on how the sync instruction affects the VEA,
refer to 5. , Cache Model and Memory Coherency.
Multiprocessor implementations also send a sync address-only broadcast that is useful in some designs. For
example, if a design has an external buffer that re-orders loads and stores for better bus efficiency, the sync
broadcast signals to that buffer that previous loads/stores must be completed before any following
loads/stores.
The sync instruction can be used to ensure that the results of all stores into a data structure, caused by store
instructions executed in a critical section of a program, are seen by other processors before the data struc-
ture is seen as unlocked.
The functions performed by the sync instruction will normally take a significant amount of time to complete,
so indiscriminate use of this instruction may adversely affect performance. In addition, the time required to
execute sync may vary from one execution to another.
The eieio instruction may be more appropriate than sync for many cases.
This instruction is execution synchronizing. For more information on execution synchronization, see
Section 4.1.5 , Synchronizing Instructions.

None
UISA X
pem8b.fm.2.0
Page 616 of 785 June 10, 2003
td 64-Bit Implementations Only td

Trap Double Word (x7C00 0088)
td TO,rA,rB
Reserved
31 TO A B 68 0
0 5 6 10 11 15 16 20 21 30 31
a (rA)
b (rB)
if (a < b) & TO[0] then TRAP
if (a > b) & TO[1] then TRAP
if (a = b) & TO[2] then TRAP
if (a U b) & TO[4] then TRAP
The contents of rA are compared with the contents of rB. If any bit in the TO field is set and its corresponding
condition is met by the result of the comparison, then the system trap handler is invoked.

None
tdge rA,rB equivalent to td 12,rA,rB

tdlnl rA,rB equivalent to td 5,rA,rB
UISA X
pem8b.fm.2.0
June 10, 2003 Page 617 of 785
tdi 64-Bit Implementations Only tdi

Trap Double Word Immediate (x0800 0000)
tdi TO,rA,SIMM
02 TO A SIMM
0 5 6 10 11 15 16 31
a (rA)
if (a < EXTS(SIMM)) & TO[0] then TRAP
if (a > EXTS(SIMM)) & TO[1] then TRAP
if (a = EXTS(SIMM)) & TO[2] then TRAP
if (a U EXTS(SIMM)) & TO[4] then TRAP
The contents of rA are compared with the sign-extended value of the SIMM field. If any bit in the TO field is
set and its corresponding condition is met by the result of the comparison, then the system trap handler is
invoked.

None
tdlti rA,value equivalent to tdi 16,rA,value

tdnei rA,value equivalent to tdi 24,rA,value
UISA D
pem8b.fm.2.0
Page 618 of 785 June 10, 2003
tlbia tlbia
Translation Lookaside Buffer Invalidate All (x7C00 02E4)
Reserved
31 00 000 0 0000 0000 0 370 0

0 5 6 10 11 15 16 20 21 30 31
All TLB entries invalid

The entire translation lookaside buffer (TLB) is invalidated (that is, all entries are removed).
The TLB is invalidated regardless of the settings of MSR[IR] and MSR[DR]. The invalidation is done without
reference to the SLB, segment table, or segment registers.
This instruction does not cause the entries to be invalidated in other processors.
This is a supervisor-level instruction and optional in the PowerPC architecture.

None
OEA X
pem8b.fm.2.0
June 10, 2003 Page 619 of 785
tlbie tlbie
Translation Lookaside Buffer Invalidate Entry (x7C00 0264)
tlbie rB
[POWER mnemonic: tlbi]
Reserved
31 00 000 0 0000 B 30k6 0
0 5 6 10 11 15 16 20 21 30 31
VPS rB[36514-19]
Identify TLB entries corresponding to VPS
Each such TLB entry invalid
EA is the contents of rB. If the translation lookaside buffer (TLB) contains an entry corresponding to EA, that
entry is made invalid (that is, removed from the TLB).
Multiprocessing implementations (for example, the 601, and 604) send a tlbie address-only broadcast over
the address bus to tell other processors to invalidate the same TLB entry in their TLBs.
The TLB search is done regardless of the settings of MSR[IR] and MSR[DR]. The search is done based on a
portion of the logical page number within a segment, without reference to the SLB, segment table, or segment
registers. All entries matching the search criteria are invalidated.
Block address translation for EA, if any, is ignored. Refer to Section 7.5.3.4 , Synchronization of Memory
Accesses and Referenced and Changed Bit Updates, and Section 7.6.3 , Page Table Updates, for other
requirements associated with the use of this instruction.
This is a supervisor-level instruction and optional in the PowerPC architecture.

None
OEA X
pem8b.fm.2.0
Page 620 of 785 June 10, 2003
tlbsync tlbsync
TLB Synchronize (x7C00 046C)
Reserved
31 00 000 0 0000 0000 0 566 0

0 5 6 10 11 15 16 20 21 30 31
If an implementation sends a broadcast for tlbie then it will also send a broadcast for tlbsync. Executing a
tlbsync instruction ensures that all tlbie instructions previously executed by the processor executing the
tlbsync instruction have completed on all other processors.
The operation performed by this instruction is treated as a caching-inhibited and guarded data access with
respect to the ordering done by eieio.
Note that the 601 expands the use of the sync instruction to cover tlbsync functionality.
Refer to Section 7.5.3.4 , Synchronization of Memory Accesses and Referenced and Changed Bit Updates,
and Section 7.6.3 , Page Table Updates, for other requirements associated with the use of this instruction.
This instruction is supervisor-level and optional in the PowerPC architecture.

None
OEA X
pem8b.fm.2.0
June 10, 2003 Page 621 of 785
tw tw
Trap Word (x7C00 0008)
tw TO,rA,rB
[POWER mnemonic: t]
Reserved
31 TO A B 4 0
0 5 6 10 11 15 16 20 21 30 31
a EXTS(rA[3263])
b EXTS(rB[3263])
if (a < b) & TO[0] then TRAP
if (a > b) & TO[1] then TRAP
if (a = b) & TO[2] then TRAP
if (a U b) & TO[4] then TRAP
The contents of the low-order 32 bits of rA are compared with the contents of the low-order 32 bits of rB. If
any bit in the TO field is set and its corresponding condition is met by the result of the comparison, then the
system trap handler is invoked.

None
tweq rA,rB equivalent to tw 4,rA,rB

twlge rA,rB equivalent to tw 5,rA,rB
trap equivalent to tw 31,0,0
UISA X
pem8b.fm.2.0
Page 622 of 785 June 10, 2003
twi twi
Trap Word Immediate (x0C00 0000)
twi TO,rA,SIMM
[POWER mnemonic: ti]
03 TO A SIMM
0 5 6 10 11 15 16 31
a EXTS(rA[3263])
if (a < EXTS(SIMM)) & TO[0] then TRAP
if (a > EXTS(SIMM)) & TO[1] then TRAP
if (a = EXTS(SIMM)) & TO[2] then TRAP
if (a U EXTS(SIMM)) & TO[4] then TRAP
The contents of the low-order 32 bits of rA are compared with the sign-extended value of the SIMM field. If
any bit in the TO field is set and its corresponding condition is met by the result of the comparison, then the
system trap handler is invoked.

None
twgti rA,value equivalent to twi 8,rA,value

twllei rA,value equivalent to twi 6,rA,value
UISA D
pem8b.fm.2.0
June 10, 2003 Page 623 of 785
xorx xorx
XOR (x7C00 0278)
xor rA,rS,rB (Rc = 0)

xor. rA,rS,rB (Rc = 1)
31 S A B 316 Rc
0 5 6 10 11 15 16 20 21 30 31
rA (rS) (rB)
The contents of rS is XORed with the contents of rB and the result is placed into rA.

UISA X
pem8b.fm.2.0
Page 624 of 785 June 10, 2003
xori xori
XOR Immediate (x6800 0000)
xori rA,rS,UIMM
[POWER mnemonic: xoril]
26 S A UIMM
0 5 6 10 11 15 16 31
rA (rS) ((4816)0 || UIMM)

The contents of rS are XORed with 0x0000_0000_0000 || UIMM and the result is placed into rA.

None
UISA D
pem8b.fm.2.0
June 10, 2003 Page 625 of 785
xoris xoris
XOR Immediate Shifted (x6C00 0000)
xoris rA,rS,UIMM
[POWER mnemonic: xoriu]
27 S A UIMM
0 5 6 10 11 15 16 31
rA (rS) ((32)0 || UIMM || (16)0)

The contents of rS are XORed with 0x0000_0000 || UIMM || 0x0000 and the result is placed into rA.

None
UISA D
pem8b.fm.2.0
Page 626 of 785 June 10, 2003

Core Instructions

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Programming Environments Manual

PowerPC RISC Microprocessor Family

add rD,rA,rB (OE = 0 Rc = 0)

Other registers altered:

Affected: LT, GT, EQ, SO (if Rc = 1)

Affected: SO, OV (if OE = 1)

pem8.fm.2.0 Instruction Set

PowerPC RISC Microprocessor Family

addc rD,rA,rB (OE = 0 Rc = 0)

Other registers altered:

Affected: LT, GT, EQ, SO(if Rc = 1)

Affected: SO, OV(if OE = 1)

Instruction Set pem8.fm.2.0

PowerPC RISC Microprocessor Family

adde rD,rA,rB (OE = 0 Rc = 0)

rD (rA) + (rB) + XER[CA]

Other registers altered:

Affected: LT, GT, EQ, SO (if Rc = 1)

Affected: SO, OV (if OE = 1)

pem8.fm.2.0 Instruction Set

PowerPC RISC Microprocessor Family

Other registers altered:

li rD,value equivalent to addi rD,0,value

Instruction Set pem8.fm.2.0

PowerPC RISC Microprocessor Family

Other registers altered:

subic rD,rA,valueequivalent toaddicrD,rA,value

pem8.fm.2.0 Instruction Set

PowerPC RISC Microprocessor Family

Other registers altered:

Affected: LT, GT, EQ, SO

Instruction Set pem8.fm.2.0

PowerPC RISC Microprocessor Family

if rA = 0 then rD EXTS(SIMM || (16)0)

Other registers altered:

pem8.fm.2.0 Instruction Set

PowerPC RISC Microprocessor Family

addme rD,rA (OE = 0 Rc = 0)

Other registers altered:

Affected: LT, GT, EQ, SO(if Rc = 1)

Affected: SO, OV(if OE = 1)

Instruction Set pem8.fm.2.0

PowerPC RISC Microprocessor Family

addze rD,rA (OE = 0 Rc = 0)

Other registers altered:

Affected: LT, GT, EQ, SO(if Rc = 1)

Affected: SO, OV(if OE = 1)

pem8.fm.2.0 Instruction Set

PowerPC RISC Microprocessor Family

and rA,rS,rB (Rc = 0)

rA (rS) & (rB)

Other registers altered:

Affected: LT, GT, EQ, SO(if Rc = 1)

Instruction Set pem8.fm.2.0

PowerPC RISC Microprocessor Family

andc rA,rS,rB (Rc = 0)

Other registers altered:

Affected: LT, GT, EQ, SO(if Rc = 1)

pem8.fm.2.0 Instruction Set

PowerPC RISC Microprocessor Family

rA (rS) & ((4816)0 || UIMM)

Other registers altered:

Affected: LT, GT, EQ, SO

Instruction Set pem8.fm.2.0