Beruflich Dokumente
Kultur Dokumente
(EMISY)
Tomasz Starecki
1
Organization of the course
group representative?
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Tomasz Starecki
2
Getting credits for the course
begin
if (((test1 + test2) >= 5.0) or (last_chance_test >= 2.5))
and (project >= 2.5)) then
passing_the_course := true
else
passing_the_course := false;
end;
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Tomasz Starecki
3
Tests
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4
Project
P individual topics
P teaching based on consultations
P proposed solution must be based on a '51 family
microcontroller (use of e.g. AVR will result in failing the
project)
P project score (PS) is based on project report (max. 5 points)
P deadline for the project reports - one week before the last
lecture, 12:00 noon
P for being late: minus 0.5 point from the project score for every
started working day (counting from the deadline)
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Project report contents
6
Labs
P two options: stationary labs or work with the labkits taken out
P individual topics
P all the labkits are based on '51 family microcontrollers
P simple program written in assembler
P it is possible to pass the course with the labs failed, but score
for the labs has impact on the final score for the course
P the stationary labs start at about half of the semester
P score for the labs (LS) is plus/minus one or zero
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Final score for the course
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References (books)
9
Other references
10
INTRODUCTION
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Historical and "philosophical" background
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Basic logic circuits
Gates
NAND
NOR
AND
OR
XOR
3-state
buffer (unidirectional), transceiver
flip-flop, latch, shift register (SIPO, PISO)
multiplexer, demultiplexer / decoder
counter
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13
3-bus architecture
Bus?
P address bus
P data bus
P control bus
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14
Internal architecture of a microprocessor /
microcontroller (simplified)
ROM+RAM+I/O
ALU registers
(optional)
timing
& control
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15
Microprocessor architecture
and control bus signals
Number of control bus signals and their functions depend on the
microprocessor - in particular on its architecture, e.g.:
P Z80, 8085 - separated I/O and memory address
space, common program and data memory address
space, Intel control signals convention
P 8051 - common I/O and data memory address
space, separated program memory address space,
Intel control signals convention
P 6800 - common address space for all devices,
Motorola control signals convention
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Web-based concept of communication
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Intel and Motorola control signals conventions
Intel:
separate, negative strobes for write (WR) and read (RD)
Motorola:
control signal for operation mode - read/not write (R/W)
and positive enable (E) strobe
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Write operation timing (Motorola mode)
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Write operation timing (Intel mode)
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Read operation timing (Motorola mode)
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Read operation timing (Intel mode)
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ADDRESS DECODING
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Memory map
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Memory map example
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Address decoding
ROM: 0000H - 7FFFH
RAM1: 8000H - 9FFFH
RAM2: 0A000H - 0BFFFH
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Partial address decoding
Step1:
RAM1: A15=1, A14=0, A13=0
RAM2: A15=1, A14=0, A13=1
Step2:
RAM1: A15=1, A14=0, A13=0
RAM2: A15=1, A14=1, A13=0
Step3:
RAM1: A15=1, A14=0, A13=X
RAM2: A15=1, A14=1, A13=X
Step2a ?
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Most common methods of address decoding
implementation
P gates
P direct control by address lines
P decoders / demultiplexers
P programmable chip selects
P programmable logic circuits (GALs) "0" A13
A13 "1"
A13
A14
A15
"1"
"0"
"0"
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Combined address decoding and control
Combined address
decoding and control is
used when the controlled
device has no chip select
inputs, eg. output registers,
input buffers, etc.
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29
Simple system with Z80
gates-based address decoding
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30
Simple system with Z80
decoder-based address decoding
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31
Bus multiplexing
latch
or
D flip-flop?
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Simple system with 8085
gates-based address decoding
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Simple system with 8085
decoder-based address decoding
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BUFFERING
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Buffering
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Characteristics of the most common
digital logic families
37
Insufficient driving capabilities example
driving capabilities of
8085A signal lines:
38
Capacitive loading of the signal lines
2.0 V
30 pF ' 37.5 ns
1.6 mA
2.0 V
30 pF ' 1 s
60 A
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Output current driving capabilities of buffers
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40
The most common buffers/transceivers
41
Interaction of circuits from different logic families
VOH $ VIH
VOL # VIL
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Interaction of logic circuits powered from
different voltages
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43
Simple system with Z80;
address bus and data bus buffered
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Simple system with Z80; address bus, data bus
and control signals buffered
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Simple system with 8085;
address bus and data bus buffered
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Simple system with 8085; address bus, data bus
and control signals buffered
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Simple system with 80C51
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TIME DEPENDENCIES
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49
Checking time dependencies
P determine connections between the circuits being checked
P get appropriate time charts from the datasheets
P find corresponding time markers on the time charts
P for each required time dependency define formulas describing
the same timing on both time charts
P from each pair of such formulas calculate value of the
parameter being analysed
P from all the calculated values select the one considered as the
worst case
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Program memory timing example:
determination of connections
O 0..7 = PORT 0
OE = PSEN
CE = "0"
A 8..15 = PORT 2
A 0..7 = Q 0..7 (LATCH)
D 0..7 (LATCH) = PORT 0
C (LATCH) = ALE
OC (LATCH) = "0"
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Program memory timing example:
finding corresponding time markers
O 0..7 = PORT 0
OE = PSEN
CE = "0"
A 8..15 = PORT 2
A 0..7 = Q 0..7 (LATCH)
D 0..7 (LATCH) = PORT 0
C (LATCH) = ALE
OC (LATCH) = "0"
tACC = tAVIV
tOE = tPLIV
tOH = tPXIX
tDF = tPXIZ
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Program memory timing example:
using microprocessor timing specifications
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Program memory timing example:
finding appropriate memory
For fOSC = 10 MHz, tCK = 1/fOSC = 100 ns
For fOSC = 20 MHz, tCK = 1/fOSC = 50 ns
tACC = tAVIV = 5 tCK 105 [ns] = 500 105 = 395 [ns] = 250 105 = 145 [ns]
tOE = tPLIV = 3 tCK 105 [ns] = 300 105 = 195 [ns] = 150 105 = 45 [ns]
tOH = tPXIX = 0
tDF = tPXIZ = tCK 25 [ns] = 100 25 = 75 [ns] = 50 25 = 25 [ns]
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Program memory timing example:
calculating maximum system clock frequency
tACC = tAVIV = 5 tCK 105 [ns] tCK = (tACC + 105) / 5 = (120 + 105) / 5 = 45 [ns]
tOE = tPLIV = 3 tCK 105 [ns] tCK = (tOE + 105) / 3 = (50 + 105) / 3 = 51.67 [ns]
tOH = tPXIX = 0
tDF = tPXIZ = tCK 25 [ns] tCK = tDF + 25 = 40 + 25 = 65 [ns]
55
Influence of latch on the timing characteristics
tACC = tAVIV
tACC = tAVIV ! tLATCH
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INTRODUCTION TO
8051 ARCHITECTURE
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Addressing modes
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Immediate addressing
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Register addressing
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Direct addressing
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Indirect addressing
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Indirect addressing with offset
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Basic information about 80C51 microcontroller
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Program memory in '51
MOV A, #37H
MOVC A, @A+PC
MOVC A, @A+DPTR
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Internal data memory in '51
MOV A, R5
MOV A, 17H
MOV A, SBUF
MOV A, @R1
PUSH ACC
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SFRs and internal peripheral circuits in '51
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External data memory (and I/O) address space
in '51
Interface:
P0 - multiplexed lower byte of address / data bus
P2 - higher byte of address
P3.7 - negative read strobe
P3.6 - negative write strobe
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I/O PORTS
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Internal structure of the I/O port lines in 80C51
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Structure of the I/O output stage in 80C51
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Read-modify-write instructions
P ANL P2, A
P ORL P1, #10
P XRL P3, A
P JBC P1.3, next
P CPL P1.0
P INC P2
P DEC P3
P DJNZ P2, alpha
P MOV Px.y, C (eg. MOV P1.0, C)
P CLR Px.y (eg. CLR P1.1)
P SETB Px.y (eg. SETB P2.3)
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Differences between read-modify-write and
read/write instructions
read/write instructions:
MOV A, P1
ANL A, #0FFH
MOV P1, A
read-modify-write instruction:
ANL P1, #0FFH
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Another approach to digital I/O lines control
on the example of AVR microcontrollers
DDxn PORTxn I/O mode Pull-up Description
0 0 input no Hi-Z (tri-state)
0 1 input yes the pin will source current if
externally pulled low
1 0 output no push-pull low (sinking current)
1 1 output no push-pull high (sourcing current)
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Typical output characteristics of digital I/O lines
in AVR microcontrollers
75
SYSTEM CLOCK
AND RESET
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System clock
Problems:
P high frequency crystal resonators
P power consumption
P input pins for external clock
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System reset
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INTERRUPTS
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Basic philosophy of interrupts
80
Servicing of an interrupt
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81
Hardware-generated instructions concept
(Intel 8080)
INT interrupt input pin (the only
interrupt input in 8080)
INTA interrupt acknowledge signal
used as a strobe for putting onto the
data bus a byte of code (instruction)
to be executed in response to the
interrupt
typically RSTn (n = 0..7) instructions
were used for this purpose, but any
other can also be used (including
multi-byte instructions)
INT state is tested once every
machine cycle; if it is noticed as
active, the acknowledge signal is
generated in the following cycle
the interrupt is level sensitive
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Problems with level-sensitive interrupts
Potential solutions:
P convert the interrupt into edge-triggered (requires additional
hardware)
P mask the interrupt
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Edge-triggered interrupts
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Masking interrupts
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Multiple interrupt sources
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Fixed-address interrupt vector system
in Intel 8085
In the fixed-address interrupt vector system the address vectors of the
interrupts are fixed and cannot be changed, eg. in 8085:
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Priority of interrupts
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Zilog Z80 interrupts
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Motorola 6800 interrupts
0FFFFH (LSB)
0FFFEH (MSB) } restart
0FFFDH (LSB)
0FFFCH (MSB) } NMI
0FFFBH (LSB)
0FFFAH (MSB) } software interrupt
0FFF9H (LSB)
0FFF8H (MSB) } INT
90
Interrupt system in 80C51
1 1 1 0 1 1
INT0
SI
T0
INT1
T1
SI T1 INT1 T0 INT0
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Saving and restoring PSW
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Returning from interrupt
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Priority inversion
wrong
right
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Peripheral event controller and some interrupt
features in 'C166 family of microcontrollers
Interrupt control register for source xx: Interrupt control functions in PSW:
xxIR xxIE ILVL GLVL xxIC ILVL IEN ) ) ) PSW (MSB)
95
TIMERS & COUNTERS
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Timers / counters in 80C51 (mode 0, 1)
T1 T0 TMOD (89H)
TCON (88H)
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Timers / counters in 80C51 (mode 2)
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Timers / counters in 80C51 (mode 3)
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Timer 2 in 80C52 (autoreload mode)
T2CON (0C8H)
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Timer 2 in 80C52 (capture mode)
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Timer 2 in 80C52 (baudrate generator mode)
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USER INTERFACE
(KEYBOARD)
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Simple keyboard
VCC
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Key debouncing
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Matrix keyboard
01
1 01
001 VCC
outputs
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Small keyboard as external I/O
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Keyboard with serial input
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USER INTERFACE
(DISPLAY)
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Most common display components
P LED displays
< LED diode
< 7-segment display
< 16-segment display
P LCD displays
< LCD display with individually driven segments
< alphanumeric LCD module
< graphic LCD display (monochrome or colour)
P fluorescent displays
< alphanumeric module
< graphic module
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LED diode
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LED diode characteristics
112
7-segment and 16-segment displays
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Simple LED display (static)
A B C D
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Typical output characteristics of digital I/O lines
in AVR microcontrollers
115
Dynamic LED display
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Peripheral driver ICs examples (ULN2803A)
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ULN2803A characteristics
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Peripheral driver ICs examples (TPIC6A595)
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Peripheral driver ICs examples (NE590 / 591)
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LED control ICs examples (NE587)
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LED control ICs examples
(NE587 in dynamic mode)
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LED control ICs examples
(NE587 and NE591 in dynamic display)
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LED control ICs examples (MAX7221)
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LED control ICs examples (SAA1064)
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LED control ICs examples
(SAA1064 in dynamic mode)
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Simple LCD display (non-multiplexed)
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Simple LCD display (multiplexed)
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Alphanumeric LCD modules
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LCD interface timing
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LCD in the external data memory space
89S8252
1 39 7 2
2 T2 P0.0 38 8 D0 VCC VCC
3 T2EX P0.1 37 9 D1
P1.2 P0.2 D2
4 P1.3 P0.3 36 10 D3
5 SS P0.4 35 11 D4
6 MOSI P0.5 34 12 D5
7 MISO P0.6 33 13 D6
8 SCK P0.7 32 14 D7
VCC 9 RST EA 31 VCC 6 E
ALE 30 5 RD/-WR
2u2 10 29 4
11 RXD PSEN 3 RS 1
TXD VO GND GND
12 INT0 P2.7 28 1 4
13 27 3 6 LCD1
14 INT1 P2.6 26 2 5
15 T0 P2.5 25
T1 P2.4
16 WR P2.3 24 74HC00 74HC00
17 RD P2.2 23
P2.1 22
21
P2.0
X X
2 1
VCC GND
1 1
8 9 1 10K
GND GND 1
27p 27p
10MHz 74HC00
1 1
2 3
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LCD in 8-bit mode
connected to the I/O lines
89C2051
1 19 7 2
VCC 2 RST P1.7 18 8 D0 VCC VCC
2u2 3 RXD P1.6 17 9 D1
6 TXD P1.5 16 10 D2
7 INT0 P1.4 15 11 D3
8 INT1 P1.3 14 12 D4
9 T0 P1.2 13 13 D5
T1 P1.1 D6
11 P3.7 P1.0 12 14 D7
X X 6
1 2 5 E
5 4 4 RD/-WR
3 RS 1
VO GND GND
LCD1
GND GND
27p 27p
10MHz
VCC GND
10K
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LCD in 4-bit mode
connected to the I/O lines
7 2
8 D0 VCC VCC
9 D1
D2
89C2051 10 D3
1 19 11
VCC 2 RST P1.7 18 12 D4
2u2 3 RXD P1.6 17 13 D5
6 TXD P1.5
16 D6
INT0 P1.4 14 D7
7 INT1 P1.3 15
8 T0 P1.2
14 6
9 13 5 E
11 T1 P1.1 12 4 RD/-WR
P3.7 P1.0 RS
3 VO GND 1 GND
X X
1 2 LCD1
5 4
GND GND
27p 27p
10MHz
VCC GND
10K
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SERIAL INTERFACES
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Internal serial interfaces most commonly used
in microprocessor systems
P UART / USART
P SPI
P I2C
P 1-Wire
P CAN
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USART in 8051 in mode 0 (synchronous)
SBUF (99H)
SCON (98H)
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USART in 8051 in mode 1 (asynchronous)
SCON (98H)
137
USART in 8051 in mode 2, 3 (asynchronous)
2SMOD fOSC
BR2 '
64
2SMOD fOSC
BR1, 3 '
32 @ 12 @ (256 & TH1)
fOSC
BR1, 3 '
32 @ (65536 & RCAP2)
SCON (98H)
138
Multiprocessor communication;
enhanced serial port in 8051
P set SM2 in all the processors and put them in 2 or 3 USART mode
P master sends slave address with 8th bit set
P all the slaves interpret the address; the addressed slave clears SM2, all the
other set their SM2 bits
P master and the addressed slave perform uni- or bidirectional transmission of
data with 8th bit cleared
P master starts another transmission (repeat the steps above)
SADDR = 1 1 0 0 0 0 0 1 SADDR = 1 1 0 0 0 0 1 0
SADEN = 1 1 1 1 1 1 1 0 SADEN = 1 1 1 1 1 1 0 1
11000001 - the first; 11000010 - the second; 11000000 - both; XXXXXX11 - none
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SPI
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1-Wire
initialization
write
read
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I2C
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INDUSTRIAL AND COMPUTER
INTERFACES
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Most common industrial and computer interfaces
P RS-232
P RS-485
P Centronics, Bitronics (IEEE 1284)
P Firewire (IEEE 1394)
P SCSI
P PCI
P PCI Express
P (E)IDE
P SATA
P IEEE488
P VXI
P USB
P Ethernet
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Single-ended and differential data transmission
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Data transmission topologies
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RS-232
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Example of RS-232 implementation
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RS-485
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Comparison of RS-232, RS-422, RS-423
and RS-485
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USB
151
Ethernet
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D/A CONVERTERS
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D/A converter
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Basic DAC selection criteria
P resolution
P INL and DNL, gain and offset errors
P output signal (current or voltage)
P bipolar or unipolar output
P output voltage/current range
P internal or external reference voltage
P bandwidth of the reference signal in the DAC is multiplying
P maximum output current
P speed
P number of channels
P microprocessor interface
P power consumption
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Specialized DAC examples
P digital potentiometer
< wiper resistance is definitely of non-zero value
< works properly only if powered
< works properly only with signals within the supply rails
< settings are usually lost when power is off
< bandwidth depends on the input code
< temperature coefficients are often relatively high
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Internal DACs (in microcontrollers)
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PWM based DAC implementation;
example of dedicated PWM outputs in 80C552
P use a square wave of a
frequency f, duty factor DF
and voltage levels equal
GND and Vcc
P pass the signal through a
low-pass filter, which corner
frequency is much lower
than f
fosc
fPWM '
2 @ 255 @ (1 % PWMP)
PWMn
PWMnduty factor ' Vout . Vcc @ DF
255
158
A/D CONVERTERS
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A/D converter
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ADC errors
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Most common A/D conversion methods
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Flash ADCs
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Pipelined ADCs
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Integrating ADCs
165
Sigma-delta ADCs
The sigma-delta ADCs offer moderate speed (up to a The Sigma-delta Modulator
few Msps), high resolution (16-32 bits), line rejection,
low power consumption, low price, and low noise.
The density of 1s at the modulator output is
proportional to the input signal. The integrator acts as
a lowpass filter to the input signal and a highpass
filter to the quantization noise. Thus, most of the
quantization noise is pushed into higher frequencies.
Oversampling has changed not the total noise power,
but its distribution.
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Successive approximation ADCs
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Internal ADCs (in microcontrollers)
P successive approximation:
kbps to Msps @ 8-16 bits
P sigma-delta:
usually much slower (100-1000 times)
but with higher resolution (16-24 bits)
P usually multiple (multiplexed) analog
inputs
168
Specialized ADC examples
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POWER CONSUMPTION
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Influence of CMOS technology
on power consumption
P % C @ VCC2 @ f
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Power reduction modes - Idle
172
Power consumption vs. system clock frequency
in active and idle modes of '51
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Power reduction modes - Power Down
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Power consumption vs. supply voltage of '51
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Power reduction modes - Slow Down
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Power consumption of different microprocessors
and microcontrollers
P common sensor node processors: AVR, 8051, StrongARM, XScale, ARM
Thumb, SH Risc, MSP430, PIC
P exemplary values of power consumption:
< 4 nJ/instr ATMega128L @ 4 MHz, 3.0 V
< 2 nJ/instr AVR32 UC3A @ 66 MHz, 3.3 V
< 2.1 nJ/instr ARM Thumb @ 40 MHz, 3.0 V
< 1.0 nJ/instr Cygnal C8051F35x @ 50 MHz, 3.0 V
< 0.5 nJ/instr MSP430x20xx @ 1 MHz, 2.2 V
< 0.11 nJ/instr PIC16LF72X @ 4 MHz, 1.8 V
< 0.8 nJ/instr TMS320VC5510 @ 200 MHz, 1.5 V
< 1.3 nJ/instr IBM 405LP @ 380 MHz, 1.8 V
< 0.35 nJ/instr IBM 405LP @ 152 MHz, 1.0 V
< 1.1 nJ/instr Xscale PXA250 @ 400 MHz, 1.3 V
< 1.9 nJ/instr Xscale PXA250 @ 130 MHz, 0.85 V
The above values dont take into consideration operand size differences!
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Selecting energy-efficient components
P eg. when looking for an ADC capable of working with the speed of 100 ksps
< AD 7853 (12-bit; 200 ksps max) - 6.0 mW @ 3.0 V, 100 ksps; 6.5 - 12$
< AD 7694 (16-bit; 250 ksps max) - 1.7 mW @ 3.0 V, 100 ksps; 6.1 - 7.6$
P modern solutions and higher level of integration usually result in lower power
consumption
P display:
< alphanumeric LCD: 0.5 - 1.0 mA (but the backlight can draw 30 mA!)
< single LED: 1.0 - 2.0 mA
P all the peripherals which are not needed at the moment can be powered
down or switched off (but care should be taken about the inputs of such
components)
P resistor values should be increased if possible
P etc.
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Power supply design - use of linear regulators
179
Power supply design - use of DC-DC regulators
(MAX1951A example)
MAX1951A features:
P Efficiency Up to 94%
P 1.5% Output Accuracy Over
Load, Line, and Temperature
P Guaranteed 2A Output Current
P Operates from 2.6V to 5.5V
Supply
P Adjustable Output from 0.8V to
VIN
P Internal Digital Soft-Soft
P Short-Circuit and Thermal-
Overload Protection
P 1MHz Switching Frequency
Reduces Component Size
P Enable Input Audio Shutdown for
Reducing Power Consumption
92-93%@ 3.3/5.0 V
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Basic hints in reducing power consumption in
microprocessor systems (summary)
P use CMOS whenever possible
P never leave CMOS inputs floating; connect unused inputs to GND or VCC
P use power saving modes efficiently
P use lower frequency of operation
P use lower supply voltage
P select energy-efficient components (in particular low-power microprocessor)
P switch off (power off) all the peripherals which you don't need at the moment
P use LCD instead of LEDs, don't use graphic LCD, neither backlight if it is not
critical
P modern technology and higher level of integration usually result in lower
power consumption
P remember that pull-ups, polarization resistors, etc. also draw current
P use high-efficiency DC/DC instead of linear regulators
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PROGRAM MEMORY
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Program memory options
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Program memory protection
P lock bits
P encryption table
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Data EEPROM
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WATCHDOG CIRCUITS
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Purpose of watchdog circuits
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Watchdog timer
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Watchdog oscillator
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Power supply monitoring circuit
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Microprocessor supervisory circuits
(example of MAX 69x)
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Other watchdog issues
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DEBUGGING
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General classification of debugging tools
P hardware tools
< oscilloscopes
< logic probes
< logic state analysers
< short-circuit testers
< microprocessor bus testers
P software tools
< assemblers + linkers
< high-level language compilers (eg. C, Java, Modula, Ada, Pascal)
< microprocessor simulators
P mixed tools
< EPROM memory emulators
< in-circuit debuggers
< microprocessor emulators
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Typical sequence of debugging
195