Minato, S., Muroga, S.

"Binary Decision Diagrams"

The VLSI Handbook.
Ed. Wai-Kai Chen
Boca Raton: CRC Press LLC, 2000

2000 by CRC PRESS LLC

 26
Binary Decision
Diagrams

26.1 Basic Concepts

Shin-ichi Minato 26.2 Construction of BDD Based on a Logic Expression
NTT Network Innovation Binary logic operation Complement Edges Derivation of
Laboratories a Logic Expression from a BDD
Saburo Muroga 26.3 Data Structure
University of Illinois 26.4 Ordering of Variables for Compact BDDs
at Urbana-Champaign 26.5 Remarks

26.1 Basic Concepts

Binary decision diagrams (BDDs), which were introduced in Chapter 23, Section 23.1, are a powerful
means for computer processing of logic functions because in many cases, with BDDs, smaller memory
space is required for storing logic functions and values of functions can be calculated faster than with
truth tables or logic expressions. As logic design has been done in recent years with computers, BDDs
are extensively used because of these features. BDDs are used in computer programs for automation
of logic design, verification (i.e., identifying whether two logic networks represent the identical logic
functions), diagnosis of logic networks, simplification of transistor circuits (such as ECL and MOSFET
circuits, as explained in Chapters 35, 36, and 37), and other areas, including those not related to
logic design.
In this chapter, we discuss the basic data structures and algorithms for manipulating BDDs. Then we
describe the variable ordering problem, which is important for the effective use of BDDs. The concept
of BDD was devised by Lee in 1959.15 Binary decision programs that Lee discussed are essentially binary
decision diagrams. Then, in 1978, its usefulness for expressing logic functions was shown by Akers.3,4
But since Bryant6 developed a reduction method in 1986, it has been extensively used for design auto-
mation for logic design and related areas.
From a truth table, we can easily derive the corresponding binary decision diagram. For example, the
truth table shown in Fig. 26.1(a) can be converted into the BDD in Fig. 26.1(b). But there are generally
many BDDs for a given truth table, that is, the logic function expressed by this truth table. For example,
all BDDs shown in Fig. 26.1(c) through (e) represent the logic function that the truth table in Fig. 26.1(a)
expresses. Here, note that in each of Figs. 26.1 (b), (c), and (d), the variables appear in the same order
and none of them appears more than once in every path from the top node. But in (e), they appear in
different orders in different paths. BDDs in Figs. 26.1(b), (c), and (d) are called ordered BDDs (or
OBDDs). But the BDD in Fig. 26.1(e) is called an unordered BDD. These BDDs can be reduced into a
simple BDD by the following procedure.
In a BDD, the top node is called the root that represents the given function f(x1, x2, , xn). Rectangles
that have 1 or 0 inside are called terminal nodes. They are also called 1-terminal and 0-terminal.

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FIGURE 26.1 Truth table and BDDs for x1x2 x 2 x 3 .

Other nodes are called non-terminal nodes denoted by circles with variables inside. They are also
called simply nodes, differentiating themselves from the 0- and 1-terminals. From a node with xi
inside, two lines go down. The solid line is called 1-edge, representing xi = 1; and the dotted line is
called 0-edge, representing xi = 0.
In an OBDD, the value of the function f can be evaluated by following a path of edges from the root
node to one of the terminal nodes. If the nodes in every path from the root node to a terminal node are
assigned with variables, x1, x2, x3, , and xn, in this order, then f can be expressed as follows, according
to the Shannon expansion (described in Chapter 24). By branching with respect to x1 from the root node,
f(x1, x2, , xn) can be expanded as follows, where f(0, x2, , xn) and f(1, x2, , xn) are functions that
the nodes at the low ends of 0-edge and 1-edge from the root represent, respectively:

f ( x 1, x 2, , x n ) = x 1 f ( 0, x 2, , x n ) x 1 f ( 1, x 2, , x n )

Then, by branching with respect to x2 from each of these two nodes that f(0, x2, , xn) and f(1, x2, ,
xn) represent, each f(0, x2, , xn) and f(1, x2, , xn) can be expanded as follows:

f ( 0, x 2, x n ) = x 2 f ( 0, 0, x 3, , x n ) x 2 f ( 0, 1, x 3, , x n )

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and

f ( 1, x 2, , x n ) = x 2 f ( 1, 0, x 3, , x n ) x 2 f ( 1, 1, x 3, , x n )

And so on. As we go down from the root node toward the 0- or 1-terminal, more variables of f are set to
0 or 1. Each term excluding xi or x i in each of these expansions [i.e., f(0, x2, , xn) and f(1, x2, , xn) in
the first expansion, f(0, 0, , xn) and f(0, 1, , xn) in the second expansion, ect.], are called cofactors.
Each node at the low ends of 0-edge and 1-edge from a node in an OBDD represents cofactors of the
Shannon expansion of the logic function at the node, from which these 0-edge and 1-edge come down.
Procedure 26.1: Reduction of a BDD
1. For the given BDD, apply the following steps in any order.
a. If two nodes, va and vb , that represent the same variable xi, branch to the same nodes in a lower
level for each of xi = 0 and xi = 1, then combine them into one node that still represents variable xi.
In Fig. 26.2(a), two nodes, va and vb , that represent variable xi, go to the same node vu for xi = 0 and
the same node vv for xi = 1. Then, according to Step a, two nodes, va and vb, are merged into one node
vab, as shown in Fig. 26.2(b). The node vab represents variable xi.

FIGURE 26.2 Step 1(a) of Procedure 26.1.

b. If a node that represents a variable xi branches to the same node in a lower level for both xi =
0 and xi = 1, then that node is deleted, and the 0- and 1-edges that come down to the former
are extended to the latter.
In Fig. 26.3(a), node va that represents variable xi branches to the same node vb for both xi = 0 and xi
= 1. Then, according to Step b, node va is deleted, as shown in Fig. 26.3(b), where the node va is a
dont-care for xi, and the edges that come down to va are extended to vu.
c. Terminals nodes with the same value, 0 or 1, are merged into the terminal node with the same
original value.
All the 0-terminals in Fig. 26.1(b) are combined into one 0-terminal in each of Figs. 26.1(c), (d), and
(e). All the 1-terminals are similarly combined.
2. When we cannot apply any step after repeatedly applying these steps (a), (b), and (c), the reduced
ordered BDD (i.e., ROBDD) or simply called the reduced BDD (i.e., RBDD), is obtained for the
given function.

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FIGURE 26.3 Step 1(b) of Procedure 26.1.

The following process is faster than the repeated application of Step 1(a) of Procedure 26.1. Suppose
a BDD contains two nodes, va and vb, both of which represent xi, such that a sub-BDD, B1, that stretches
downward from va is completely identical to another sub-BDD, B2, that stretches downward from vb. In
this case, each sub-BDD is said to be isomorphic to the other. Then the two sub-BDDs can be merged.
For example, the two sub-BDDs, B1 and B2, shown in the two dotted rectangles in Fig. 26.4(a), both
representing x4, can be merged into one, B3, as shown in Fig. 26.4(b).

FIGURE 26.4 Merger of two isomorphic sub-BDDs.

Theorem 26.1: Any completely or incompletely specified function has a unique reduced ordered
BDD and any other ordered BDD for the function in the same order of variables (i.e., not reduced)
has more nodes.

2000 by CRC Press LLC

 According to this theorem, the ROBDD is unique for a given logic function when the order of the
variables is fixed. (A BDD that has dont-cares can be expressed with addition of the d-terminal or two
BDDs for the ON-set and OFF-set completely specified functions, as explained with Fig. 23.5. For details,
see Ref. 24.) Thus, ROBDDs give canonical forms for logic functions. This property is very important
to practical applications, as we can easily check the equivalence of two logic functions by only checking
the isomorphism of their ROBDDs. Henceforth in this chapter, ROBDDs will be referred to as BDDs
for the sake of simplicity.
It is known that a BDD for an n-variable function requires an exponentially increasing memory space
in the worst case, as n increases.16 However, the size of memory space for the BDD varies with the types
of functions, unlike truth tables which always require memory space proportional to 2n. But many logic
functions that we encounter in design practice can be shown with BDDs without large memory space.14
This is an attractive feature of BDDs. Fig. 26.5 shows the BDDs representing typical functions, AND,
OR, and the parity function with three and n input variables. The parity function for n variables, x1
x2 xn, can be shown with the BDD of 2(n 1) + 1 nodes and 2 terminals; whereas, if a truth
table or a logic expression is used, the size increases exponentially as n increases.

FIGURE 26.5 BDDs for typical logic functions.

A set of BDDs representing many functions can be combined into a graph that consists of BDDs
sharing sub-graphs among them, as shown in Fig. 26.6. This idea saves time and space for duplicating
isomorphic BDDs. By sharing all the isomorphic sub-graphs completely, no two nodes that express the
same function coexist in the graph. We call it shared BDDs (SBDDs),25 or multi-rooted BDDs. In a
shared BDD, no two root nodes express the same function.
Shared BDDs are now widely used and those algorithms are more concise than ordinary BDDs. In the
remainder of this chapter, we deal with shared BDD only.

f1 = x1 x2 ,
f2 = x1 x2 ,
f3 = x2 ,
f4 = x1 x2

FIGURE 26.6 A shared BDD.

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26.2 Construction of BDD Based on a Logic Expression
Procedure 26.1 shows a way of constructing compact BDDs from the truth table for a function f of n
variables. This procedure, however, is not efficient because the size of its initial BDD is always of the
order of 2n, even for a very simple function. To avoid this problem, Bryant6 presented a method to
construct BDDs by applying a sequence of logic operations in a logic expression. Figure 26.7 shows a
simple example of constructing a BDD for f = (x2 x3) x1. First, trivial BDDs for x2 x3, and x3 are
created in Fig. 26.7(a). Next, applying the AND operation between x2 and x3, the BDD for x2 x3 is then
generated. Then, the BDD for the entire expression is obtained as the result of the OR operation between
(x2 x3) and x1. After deleting the nodes that are not on the paths from the root node for f toward the
0- or 1-terminal, the final BDD is shown in Fig. 26.7(b).

FIGURE 26.7 Generation of BDDs for f = (x2 x3) x1.

In the following, we show a formal algorithm for constructing BDDs for an arbitrary logic expression.
This algorithm is generally far more efficient than that based on a truth table.

Binary logic operation

Suppose we perform a binary operation between two functions, g and h, and this operation is denoted
by g  h, where  is one of OR, AND, Exclusive-OR, and others. Then by the Shannon expansion of a
function explained previously, g  h can be expanded as follows:

g  h = xi g h x g h
xi = 0 x = 0
i
x = 1 x = 1

i i i

with respect to variable xi, which is the variable of the node that is in the highest level among all the
nodes in g and h. This expansion creates the 0- and 1-edges which go to the next two nodes from the
node for the variable xi, by operations g xi = 0  h xi = 0 and g xi = 1  h xi = 1 . The two subgraphs

whose roots are these two nodes represent the cofactors derived by the Shannon expansion,
g  h xi = 0 and g xi = 1  h xi = 1 . Repeating this expansion for all the variables, as we go down
xi = 0
0ntually trivial operations, such as g 1 = g, g g = 0, and
h 0 = h, finishing the construction of a BDD for g  h.

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 When BDDs for functions g and h are given, we can derive a new BDD for function f = g  h by the
following procedure.
Procedure 26.2: Construction of a BDD for Function f = g  h, Given BDDs for g and h.
Given BDDs for functions g and h (e.g., Fig. 26.8(a)), let us construct a new BDD (e.g., Fig. 26.8(b))
with respect to the specified logic operation g  h and then reduce it by the previous Procedure 26.1
(e.g., Fig. 26.8(d)).

FIGURE 26.8 Procedure of binary operation.

1. Starting with the root nodes for g and h and going down toward to the 0- or 1-terminal, apply
repeatedly steps a and b in the following, considering steps c and d.
a. When the node under consideration, say Na, in one of the two BDDs for g and h is in a higher
level than the other node, Nb:
If Na and Nb are for variables xa and xb, respectively, and

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 if the 0-edge from Na for xa = 0 goes to node Na0 and the 1-edge from Na for xa = 1 goes to
node Na1,
then we create the following two new nodes, to which the 0- and 1-edges go down from the
corresponding node Na for the variable xa in the new BDD (i.e., Na corresponds to this
combination of Na and Nb), as a part of the new BDD:
One new node for the operation  between Na0 and Nb for xa = 0, and
the other new node for the operation  between Na1 and Nb for xa = 1.
The variable for the first node, i.e., the node for Na0  Nb will be the one in the higher level of
the two nodes, Na0 and Nb, in the BDDs for g and h; and the variable for the second node (i.e.,
the node for Na1  Nb) will be the one in the higher level of the two nodes, Na1 and Nb, in the
BDDs for g and h.
In this case, creation of edges is not considered with respect to Nb in the original BDDs.
For example, suppose binary operation g  h is to be performed on the functions g and h in the BDD
shown in Fig. 26.8(a) and furthermore,  is OR in this case. We need to start the OR operation with
the root nodes for g and h (i.e., N8 and N7 respectively). N8 is in a higher level than N7. So, in Fig.
26.8(b) which explains how to construct the new BDD according to this procedure, we create two new
nodes; one for OR(N4, N7) for the 0-edge for x1 = 0 from the node for OR(N8, N7) and the other for
OR(N6, N7) for the 1-edge for x1 = 1 from the node for OR(N8, N7), corresponding to this step (a).
Thus, we need next to form the OR between N4 and N7 and also the OR between N6 and N7 at these
nodes in the second level in Fig. 26.8(b). These two nodes are both for variable x2.
For OR(N4, N7), N7 is now in a higher level than N4. So, corresponding to this step (a), we create the
new nodes for OR(N4, N2) and also for OR(N4, N5) for 0- and 1-edge, respectively, in the third level
in Fig. 26.8(b).
b. When the node under consideration, say Na, in one of the BDDs for g and h is in the same level
as the other node, Nb. (If Na is for a variables xa, these two nodes are for the same variable xa
because both g and h have this variable.):
If the 0-edge from Na for xa = 0 goes to node Na0 and the 1-edge from Na for xa = 1 goes to
node Na1, and
if the 0-edge from Nb for xb = 0 goes to node Nb0 and the 1-edge from Nb for xb = 1 goes to
node Nb1,
then we create the following two new nodes, to which the 0- and 1-edges come down from the
corresponding node Na for the variable xa in the new BDD (i.e., Na corresponds to this combination
of Na and Nb), as a part of the new BDD:
one new node for the operation  between Na0 and Nb0 for xa = 0, and
the other new node for the operation  between Na1 and Nb1 for xa = 1.
The variable for the first node, i.e., the node for Na0  Nb0 will be the one in the higher level of the
two nodes, Na0 and Nb0, in the BDDs for g and h; and the variable for the second node, i.e., the node
for Na1  Nb1 will be the one in the higher level of the two nodes, Na1 and Nb1, in the BDDs for g and h.
For the example in Fig. 26.8(b), we need to create two new nodes for the operations, OR(N4, N2) and
OR(N2, N5) to which the 0- and 1-edges go for x2 = 0 and x2 = 1, respectively, from the node OR(N6,
N7) because N6 and N7 are in the same level for variable x2 in Fig. 26.8(a). These two nodes are both
for variable x3.
c. In the new BDD for the operation g  h, we need not have more than one subgraph that
represent the same logic function. So, during the construction of the new BDD, whenever a
new node (i.e., a root node of a subgraph) is for the same operation as an existing node, we
need not continue creation of succeeding nodes from that new node.

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 For the example, in Fig. 26.8(b), the node for operation OR(N4, N2) appears twice, as shown with a
dotted arc, and we do not need to continue the creation of new nodes from the second and succeeding
nodes for OR(N4, N2). OR(N2, N3) also appears twice, as shown with a dotted arc.
d. In the new BDD for the operation g  h, if one of Na and Nb is the 0- or 1-terminal, or Na
and Nb are the same, i.e., Na = Nb, then we can apply the logic operation that g  h defines.
If g  h is for AND operation, for example, the node for AND(N1, Na) represents Na because
N1 is the 1-terminal in Fig. 26.8(a), and furthermore, if Na represents function g, this node
represents g.
Also, it is important to notice that only this step (d) is relevant to the logic operation defined by g 
h, whereas all other steps from (a) through (c) are irrelevant of the logic operation g  h.
For the example in Fig. 26.8(b), the node for operation OR(N0, N2) represents N2, which is for variable
x4. Also, the node for operation OR(N0, N1) represents constant value 1 because N0 and N1 are the 0-
and 1-terminals, respectively, and consequently, 0 1.
By using binary operation f 1, f can be performed and its processing time is linearly proportional
to the size of a BDD. However, it is improved to a constant time by using the complement edge, which
is discussed in the following. This technique is now commonly used.
2. Convert each node in the new BDD that is constructed in Step 1 to a node with the corresponding
variable inside. Then derive the reduced BDD by Procedure 26.1.
For the example, each node for operation OR(Na, Nb) in Fig. 26.8(b) is converted to a node with the
corresponding variable inside in Fig. 26.8(c), which is reduced to the BDD in Fig. 26.8(d).

Complement Edges
Complement edge is a technique to reduce computation time and memory requirement of BDDs by
using edges that indicates to complement the function of the subgraph pointed to by the edge, as shown
in Fig. 26.9(a). This idea was first shown by Akers3 and later discussed by Madre and Billon.18 The use
of complement edges brings the following outstanding merits.
The BDD size is reduced by up to a half
Negation can be performed in constant time
Logic operations are sped by applying the rules, such as f f = 0, f f = 1, and f f = 1
Use of complement edges may break the uniqueness of BDDs. Therefore, we have to adopt the two
rules, as illustrated in Fig. 26.9(b):

FIGURE 26.9 Complement edges.

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 1. Using the 0-terminal only.
2. Not using a complement edge as the 0-edge of any node (i.e., use it on 1-edge only). If necessary,
the complement edges can be carried over to higher nodes.

Derivation of a Logic Expression from a BDD

A logic expression for f can be easily derived from a BDD for f. A path from the root node for f to the
1-terminal in a BDD is called 1-path, where the values of the variables on the edges on this path make
f equal 1. For each 1-path, a product of literals is formed by choosing xi for xi = 1 or its complement,
x i for xi = 0. The disjunction of such products for all 1-paths yields a logic expression for f. For example,
in Fig. 26.8(a), the sequence of nodes, N8-N6-N4-N2-N1, is a 1-path and the values of variables on this
path, x1 = 1, x2 = 0, x3 = 1, and x4 = 1, make the value of f (g for this example) equal 1. Finding all 1-
paths, a logic expression for f is derived as f = x 1 x 2 x 3 x 4 x1x2x4 x 1 x 3 x 4 . It is important to notice that
logic expressions that are derived from all 1-paths are usually not minimum sums for the given functions.

26.3 Data Structure

In a typical realization of a BDD manipulator, all the nodes are stored in a single table in the main
memory of the computer. Figure 26.10 is a simple example of realization for the BDD shown in Fig.
26.6. Each node has three basic attributes: input variable and the next nodes accessed by the 0- and 1-
edges. Also, 0- and 1-terminals are first allocated in the table as special nodes. The other non-terminal
nodes are created one by one during the execution of logic operations.

FIGURE 26.10 Table-based realization of a shared BDD.

Before creating a new node, we check the reduction rules of Procedure 26.1. If the 0- and 1-edges go
to the same next node (Step 1(b) of Procedure 26.1) or if an equivalent node already exists (Step 1(a)),
then we do not create a new node but simply copy that node as the next node. To find an equivalent
node, we check a table which displays all the existing nodes. The hash table technique is very effective
to accelerate this checking. (It can be done in a constant time for any large-scale BDDs, unless the table
overflows in main memories.)
When generating BDDs for logic expressions, such as Procedure 26.2, many intermediate BDDs are
temporarily generated. It is important for memory efficiency to delete such unnecessary BDDs. In order
to determine the necessity of the nodes, a reference counter is attached to each node, which shows the
number of incoming edges to the node.
In a typical implementation, the BDD manipulator consumes 20 to 30 bytes of memory for each node.
Today, there are personal computers and workstations with more than 100 Mbytes of memory, and those
facilitate us to generate BDDs containing as many as millions of nodes. However, the BDDs still grow
beyond the memory capacity in some practical applications.

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26.4 Ordering of Variables for Compact BDDs
BDDs are a canonical representation of logic functions under a fixed order of input variables. A change
of the order of variable, however, may yield different BDDs of significantly different sizes for the same
function. The effect of variable ordering depends on logic functions, changing sometimes dramatically
the size of BDDs. Variable ordering is an important problem in using BDDs.
It is generally very time consuming to find the best order.30 Currently known algorithms are
limited to run on the small size of BDDs with up to about 17 variables.13 It is difficult to find the
best order for larger problems in reasonably short processing time. However, if we can find a fairly
good order, it is useful for practical applications. There are many research works on heuristic
methods of variable ordering.
Empirically, the following properties are known on the variable ordering.
1. Closely-related variables:
Variables that are in close relationship in a logic expression should be close in variable order (e.g.,
x1 in x1 x2 x3 x4 is in closer relationship with x2 than x3). The logic network of AND-OR gates
with 2n inputs in 2-level shown in Fig. 26.11(a) has 2n nodes in the best order with the expression
(x1 x2) (x3 x4) (x2n 1 x2n), as shown for n = 2 in Fig. 26.11(b), while it needs (2n + 1
2) nodes in the worst order, as shown in Fig. 26.11(c). If the same order of variables as the one
in Fig. 26.11(b) is kept on the BDD, Fig. 26.11(c) represents the function (x1 xn + 1) (x2 xn + 2)
(xn x2n).

FIGURE 26.11 BDDs for 2-level logic network with AND/OR gates.

2. Influential variables:
The variables that greatly influence the nature of a function should be at higher position. For
example, the 8-to-1 selector shown in Fig. 26.12(a) can be represented by a linear size of BDD
when the three control inputs are ordered high, but when the order is reversed, it becomes of
exponentially increasing size as the number of variables (i.e., the total number of data inputs and
control inputs) increases, as shown in Fig. 26.12(b).

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FIGURE 26.12 BDDs for 8-to-1 selector.

Based on empirical rules like this, Fujita et al.9 and Malik et al.20 presented methods; in these
methods, an output of the given logic networks is reached, traversing in a depth-first manner, then
an input variable that can be reached by going back toward the inputs of the network is placed at
highest position in variable ordering. Minato25 devised another heuristic method in which each output
function of the given logic networks is weighted and then input variables are ordered by the weight
of each input variable determined by how each input can be reached from an output of the network.
Butler et al.8 proposed another heuristic based on a measure which uses not only the connection
configuration of the network, but also the output functions of the network. These methods probably
find a good order before generating BDDs. They find good orders in many cases, but there is no
method that is always effective to a given network.
Another approach reduces the size of BDDs by reordering input variables. A greedy local exchange
(swapping adjacent variables) method was developed by Fujita et al.10 Minato22 presented another reor-
dering method which measures the width of BDDs as a cost function. In many cases, these methods find
a fairly good order using no additional information. A drawback of the approach of these methods is
that they cannot start if an initial BDD is too large.
One remarkable work is dynamic variable ordering, presented by Rudell.27 In this technique, the BDD
package itself determines and maintains the variable order. Every time the BDDs grow to a certain size,
the reordering process is invoked automatically. This method is very effective in terms of the reduction
of BDD size, although it sometimes takes a long computation time.
Table 26.1 shows experimental results on the effect of variable ordering. The logic network sel8 is
an 8-bit data selector, and enc8 is an 8-bit encoder. add8 and mult6 are an 8-bit adder and a 6-bit
multiplier. The rest is chosen from the benchmark networks in MCNC90.1 Table 26.1 compares four
different orders: the original order, a random order, and two heuristic orders. The results show that the
heuristic ordering methods are very effective except for a few cases which are insensitive to the order.

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 TABLE 26.1 Effect of Variable Ordering
Network Feature BDD Size (with complement edges)
No. of
No. of No. of Inputs to
Name Inputs Outputs All Gates Original Random Heur-1 Heur-2

sel8 12 2 29 16 88 23 19
enc8 9 4 31 28 29 28 27
add8 17 9 65 83 885 41 41
mult6 12 12 187 2183 2927 2471 2281
vg2 25 8 97 117 842 97 86
c432 36 7 203 3986 (>500k) 27302 1361
c499 41 32 275 115654 (>500k) 52369 40288
c880 60 26 464 (>500k) (>500k) 23364 9114

Note: Heuristic-1: Heuristic order based on connection configuration.5

Heuristic-2: BDD reduction by exchanging variables.14

Unfortunately, there are some hard examples where variable ordering is powerless. For example,
Bryant6 proved that an n-bit multiplier function requires an exponentially increasing number of BDD
nodes for any variable order, as n increases. However, for many other practical functions, the variable
ordering methods are useful for generating compact BDDs in a reasonably short time.

26.5 Remarks
Several groups developed BDD packages, and some of them are open to the public. For example, the
CUDD package12 is well-known to BDD researchers in the U.S. Many other BDD packages may be found
on the Internet. BDD packages, in general, are based on the quick search of hash tables and linked-list
data structures. They greatly benefit from the property of the random access machine model,2 where
any data in main memory can be accessed in constant time.
Presently, considerable research is in progress. Detection of total or partial symmetry of a logic function
with respect to variables has been a very time-consuming problem, but now it can be done in a short
time by BDDs.26,29 Also, decomposition of a logic function, which used to be very difficult, can be quickly
solved with BDD.5,21 A number of new types of BDDs have been proposed in recent years. For example,
the Zero-Suppressed BDD (ZBDD)23 is useful for solving covering problems, which are used in deriving
a minimal sum and other combinatorial problems. The Binary Moment Diagram (BMD)7 is another
type of BDD that is used for representing logic functions for arithmetic operations. For those who are
interested in more detailed techniques related to BDDs, several good surveys11,24,28 are available.

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