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Course Code: 13EC1146/ 2013 R-2013 Reg. No.

GAYATRI VIDYA PARISHAD COLLEGE OF ENGINEERING (AUTONOMOUS)


Madhurawada, Visakhapatnam
Affiliated to JNT University K, Kakinada
B. Tech. V Semester Regular Examinations, November 2015
Linear and Digital IC Applications
(Electrical & Electronics Engineering)
Date: 05/11/2015 Time: 3 Hours Max. Marks: 70
1. Answer ONE Question from each UNIT
2. All parts of a Question must be answered in one place to get valued.
3. All questions carry equal marks.
UNIT-I
1. a) Compare Ideal and practical Op-Amp in detail. 7 Marks
b) Explain different types of Voltage regulators. 7 Marks

2. a) Design a Differentiator to differentiate an input signal that varies in frequency 100Hz to 10KHz 7 Marks
b) Explain the operation of Triangular wave generator using Op-Amp. 7 Marks

UNIT-II
3. a) Derive the frequency of oscillations for Astable mode using 555 timer with timing wave form? 7 Marks
b) Explain the operation of PLL with its individual blocks 7 Marks

4. a) Draw and Explain the functional block diagram of 555 timer. 7 Marks
b) Explain any two applications of PLL. 7 Marks
UNIT-III

5. a) A 4bit R-2R ladder type D/A converter having resistor values of R=10 k and 2R=20K used 5 Marks
VR of 10V. Find
i) the resolution of D/A converter
ii) IO through the feed back resistance for a digital input of 1101.
b) Explain the functional diagram of successive Approximation ADC. 9 Marks

6. a) Explain different important specifications of A/D converter? 7 Marks


b) Realize counter type ADC and explain the operation with neat diagram. 7 Marks
UNIT-IV
7. a) Realize a NMOS AND-OR-INVERT gate and write its functional table. 7 Marks
b) Realize NAND gate using TTL and explain its operation with functional table. 7 Marks

8. a) Compare various logic families. 7 Marks


b) Explain the concept of tri state device in detail. 7 Marks
UNIT-V
9. a) Design a 4-bit synchronous down counter that counts through all states from 1111 to 0000 7 Marks
b) Compare Encoder and Decoder in detail. 7 Marks
10. a) Design a 5 to 32 decoder using 74 x138s and 74 x 139? 7 Marks
b) Design 32:1 mux using 8:1 muxs and 3 to 8 decoder. 7 Marks

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