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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 53, NO.

4, APRIL 2006 897

Compact Modeling of High-Voltage LDMOS


Devices Including Quasi-Saturation
Annemarie C. T. Aarts and Willy J. Kloosterman

AbstractThe surface-potential-based compact transistor an operating regime generally referred to as quasi-saturation.


model, MOS Model 20 (MM20), has been extended with a In that case, the saturation characteristics of the device are
quasi-saturation, an effect that is typical for LDMOS devices with controlled by the drift region instead of by the channel region.
a long drift region. As a result, MM20 extends its application
range from low-voltage LDMOS devices up to high-voltage The main limitation of the present MM20 model thus is that it
LDMOS devices of about 100 V. In this paper, the new dc is not applicable to these high-voltage devices.
model of MM20, including quasi-saturation, is presented. The So far, various LDMOS models have been developed, which
addition of velocity saturation in the drift region ensures the take the quasi-saturation into account [3][11]. In the subcircuit
current to be controlled by either the channel region or the drift models [3][8], the internal potentials of the device are solved
region. A comparison with dc measurements on a 60-V LDMOS
device shows that the new model provides an accurate description by the circuit simulator, in which case no control can be
in all regimes of operation, ranging from subthreshold to executed on the convergence during circuit simulation. In the
superthreshold, in both the linear and saturation regime. Thus, compact models [9][11], the internal potentials are solved by
owing to the inclusion of quasi-saturation also the regime of high- a numerical iteration procedure inside the model itself. The
gate and high-drain bias conditions for high-voltage LDMOS drawback of most models, however, is that accumulation in
devices is accurately described.
the drift region is neglected ([4], [9], and [10]), and that the
Index TermsHigh-voltage MOS, integrated-circuit design, subthreshold regime is not included ([3], [4], [9], and [11]).
LDMOS, modeling, quasi-saturation. The aim of this paper is to present a new model for MM20
which includes the effect of quasi-saturation. To that end,
I. INTRODUCTION velocity saturation in the drift region is included, which limits
the dc current at high gate- and high drain-bias conditions.
T ODAY, high-voltage LDMOS devices are extensively used
in all kinds of integrated-power circuits for automotive
and consumer applications. Optimal design of these power
Furthermore, in addition to accumulation occurring in the drift
region, also pinchoff of the drift region through depletion has
circuits requires high-voltage LDMOS models for circuit sim- been included. The capacitances are described according to
ulation, which describe the device characteristics accurately. the original MM20 model [1]. Through the inclusion of quasi-
Inclusion of specific LDMOS transistor aspects, like the quasi- saturation, however, in the new model, the internal-drain poten-
saturation effect, is therefore necessary. tial may obtain different values, affecting the capacitance values
Recently, a new compact LDMOS transistor model called accordingly. Thus, the new model combines all the benefits of
MOS Model 20 (MM20) has been developed [1]. This model the original model with the ability to accurately describe quasi-
describes the currents of an LDMOS device in surface-potential saturation. As a result, a new MM20 model is obtained, which
formulations, thereby including accumulation in the drift re- can be used for both low-voltage and high-voltage LDMOS
gion. As a result, MM20 gives an accurate description in all devices.
regimes of operation, ranging from subthreshold to superthresh-
old, in both the linear and saturation regime. The original II. HIGH-VOLTAGE LDMOS DEVICES
MM20 model is aimed at low-voltage LDMOS devices (which
consequently have a relatively short drift region). For such In Fig. 1, a cross section of a high-voltage LDMOS transistor
an LDMOS device, velocity saturation always occurs in the is given. The p-well bulk (B) is diffused from the source side
channel region of the device, the reason why velocity satu- under the gate (G), and thus forms a graded-channel region (of
ration occurring in the drift region has not been included in length Lch ). The internal-drain Di represents the point where
the original MM20 model. For high-voltage LDMOS devices the graded channel turns into the lightly doped n -drift region
(which consequently have a long drift region), however, the (of total length Ldr + LLOCOS ). To withstand the high voltages
velocity saturation can occur in the drift region of the device [2], between source (S) and drain (D), the drift region is long and
it comprises two different sections: the first section is the thin-
gate-oxide drift region (of length Ldr ), and the second is the
Manuscript received June 3, 2005; revised December 14, 2005. The review thick-field-oxide drift region (of length LLOCOS ). The length
of this paper was arranged by Editor M. A. Shibib.
A. C. T. Aarts was with Philips Research Laboratories, Eindhoven 5656 AA, of the gate on the thin gate-oxide only, is denoted by LPSOD .
The Netherlands. She is now with the Faculty of Mathematics and Computer Above the threshold voltage of the channel region, electrons
Science, Eindhoven University of Technology, Eindhoven, The Netherlands. flow from the source through an inversion channel towards
W. J. Kloosterman is with Philips Semiconductors, Nijmegen 6534 AE,
The Netherlands. the drift region. With the gate extending over the drift re-
Digital Object Identifier 10.1109/TED.2006.870423 gion, subsequently, an accumulation layer forms at the surface

0018-9383/$20.00 2006 IEEE


898 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 53, NO. 4, APRIL 2006

Fig. 1. Cross section of a high-voltage LDMOS transistor, comprising two


different drift region sections.
Fig. 3. Measured (symbols) drain-to-source current IDS in comparison
to MM20 without quasi-saturation (solid lines), at VGS = 2.4, 3.4, 4.4,
6, 8, 10, and 12 V and VSB = 0 V, for Wmask = 20 m, LPSOD = 2.6 m,
and LLOCOS = 3.5 m.

gate voltage diminishes, which indicates the onset of quasi-


saturation. The reason for the occurrence of quasi-saturation
at high-gate voltages is that the conductivity of the channel
Fig. 2. Equivalent circuit for the high-voltage LDMOS device of Fig. 1. region is high, whereas that of the thin-gate-oxide drift region
MM20 describes the total region underneath the thin gate-oxide. The constant is low due to depletion in the drift region. For further increasing
resistance Rdrift represents the drift region underneath the thick LOCOS oxide. drain voltages, the depletion layer widens, and the current
through the drift region becomes confined to a limited effective
underneath the thin gate-oxide of the drift region. At a certain cross section [3], which leads to velocity saturation in the
point in the thin gate-oxide drift region, depletion occurs and drift region.
the accumulation layer vanishes. Consequently, the electrons Since velocity saturation occurring in the drift region has not
gradually flow into the bulk of the drift region (see [3]). Further been included in the present dc model of MM20, it is impossible
towards the drain, in the thick-field-oxide drift region, the to adequately describe quasi-saturation with this model. In
electrons are spread out across the whole body of the drift Fig. 3, the simulated current obtained with MM20 without
region. Since the LOCOS oxide is very thick compared to quasi-saturation is plotted in comparison to the measurements.
the thin gate-oxide, the potential applied to the gate terminal We observe that for low-gate voltages, the model accurately
has hardly any influence on the electrons in the drift region describes the device characteristics. The reason is that for these
underneath this LOCOS oxide. low-gate voltages, the saturation of the current is controlled by
For simulation of the high-voltage LDMOS devices, the the channel region. For high gate-voltages, however, the current
subcircuit depicted in Fig. 2 is used. In this subcircuit, MM20 is strongly over estimated by the model, since in the present
describes the total region underneath the thin-gate oxide. Since model the current cannot be controlled by the drift region.
the gate voltage has hardly any influence on the electrons in the
drift region underneath the LOCOS oxide, the current through
the thick-field-oxide drift region is represented by a constant III. MODEL DESCRIPTION INCLUDING QUASI-SATURATION
resistance Rdrift . The value of this resistance is given by In our compact modeling approach, first expressions for
LLOCOS the current Ich through the inversion channel as well as
Rdrift = Rsheet (1) for the current Idr through the drift region are derived (see
W
Sections III-A and B), both in terms of the known terminal-
where W is the width of the device and Rsheet is the sheet drain, gate, source, and bulk voltages VD , VG , VS , and VB ,
resistance of the thick-field-oxide drift region. The temperature respectively, as well as of the unknown internal-drain voltage
rise due to self-heating is taken into account via a thermal VDi . Subsequently, the internal-drain voltage VDi is derived by
network (not shown here) [7]. equating Ich to Idr . Since inclusion of the velocity saturation
Low-voltage LDMOS devices lack a thick-field-oxide drift in the drift region makes the current expression for Idr more
region, and thus have a relatively short drift region; see [1]. complex, an iteration procedure is included inside the model
In these devices, the conductivity of the drift region is always for the calculation of the internal-drain potential. As the current
larger than that of the channel region, so that saturation of the difference Ich Idr is a monotonically increasing function of
current is controlled by the channel region [8]. In high-voltage VDi , with exactly one zero between the source and the external-
LDMOS devices, on the other hand, the currentvoltage char- drain potential, the standard NewtonRaphson scheme is used
acteristics are affected at high-gate-bias conditions; see Fig. 3. combined with a bisection procedure to speed up the iteration
In this figure, the measured drain-to-source current of a high- process and to ensure that the internal-drain potential remains
voltage (60 V) LDMOS device is plotted versus drain voltage, within its domain. In this way, a fast and robust iteration
over the whole gate-bias range. We observe that for high- procedure is obtained for the calculation of the internal-drain
gate voltages, the increase of saturation current with increasing potential. Next, the internal-drain voltage is used to calculate
AARTS AND KLOOSTERMAN: COMPACT MODELING OF LDMOS DEVICES INCLUDING QUASI-SATURATION 899

the surface potential sL at the internal drain according to [12]. B. Drift Region Current
Finally, the drift and diffusion component of the channel-region
To take the velocity saturation into account in the drift region,
current is calculated, both in terms of its surface potentials. Sub-
its current is given in a continuous way as [14]
sequently, second-order effects like channel-length modulation,
drain-induced barrier lowering, and static feedback, are added.  
e Qn
dr dVC
dr dx
Notice that expression of the final current in surface potential Idr = W dr
, VDi < VC < VD (6)
eff dVC
formulations yields an accurate current description, also in the 1 + vsat dx
subthreshold regime.
where dr
e is the effective electron mobility in the drift region,
Qn is the charge density per unit area, and VC is the quasi-Fermi
A. Channel Current potential in the drift region. For the drift region, we take both
accumulation and depletion underneath the thin-gate oxide into
For the calculation of the internal-drain quasi-Fermi potential account, so that
VDi , the channel current Ich is expressed as (see [1] with the
surface-potential drop s replaced by VDiS ) Qdr
n = qND tSieff Qacc Qdep
dr dr
(7)
  where q is the electron charge, ND is the doping concentration
e Cox Vinv0 2 VDiS VDiS
1
W ch
Ich = . (2) of the drift region, tSieff is the effective drift region thickness
Lch 1 + 3 VDiS (taking into account the reduction due to depletion from the
p-n junction), Qdracc is the accumulation charge per unit area
Here, ch e is the effective electron mobility in the channel at the surface of the drift region, and Qdr dep is the depletion
region, Cox = ox /tox is the thin-gate-oxide capacitance per charge per unit area at the surface of the drift region. Both the
unit area (with tox the thickness of the thin-gate oxide, and accumulation and depletion charge depend on the potential drop
ox its permittivity), Vinv0 = Qinv0 /Cox represents the inver- VGC between gate and drift region, according to (see [15])
sion charge Qinv per unit area at the source side, and 3 =  
acc = Cox VGC VFB
Qdr dr
ch
0 /(Lch vsat ) represents velocity saturation in the channel
(8)
region, with ch0 the zero-field electron mobility in the channel dr
region and vsat the saturated drift velocity of electrons. The valid for VGC > VFB , and
factor = (Qinv /s )/Cox reflects the variation of inversion


dr dr 2  
chargewith surface potential, and is taken as = [1 + (1/2 Qdr dr
dep = Cox

+
dr (9)
VGC VFB
0 )]/ V1 + s0 , where 0 is the body factor at the source, 2 2
V1 = 1 V, and s0 is the surface potential at the source. To
account for mobility reduction due to the vertical electrical dr

valid for VGC < VFB , respectively. Here, dr = 2qSi ND /
field, the effective electron mobility is taken as [1] Cox is the body factor of the drift region, and VFB dr
is the flat-
band voltage of the drift region. Integration of (6) from x = Lch
ch to x = Lch + Ldr yields
ch
e = 0   (3)
1 + 1 Vinv0 + 2 s0 s0 |VSB =0 VD
W dr  
Idr = e
Qdr
n dVC (10)
Ldr 1 + 3dr VDDi
where 1 and 2 are model parameters. VDi
Velocity saturation in the channel region occurs if
where 3dr = dr dr
e /(Ldr vsat ). In the model, 3 is taken as
 parameter, thus independent of the bias condition. In this way,
Ich  a sufficiently large value for 3dr ensures the occurrence of
= 0. (4)
VDiS VDiS =Vsat,ch velocity saturation in the drift region. Substitution of (7)(9)
into (10) yields, under the assumption that tSieff is independent
of VC
By use of (2) and (3), elabobration of (4) yields for the satura-
  
tion potential of the channel region dr 
dr
W e Cox V n VC =VDi 1 dr
2 V D  Di VD Di
Idr = (11)
2Vinv0 Ldr 1 + 3dr VD Di

Vsat,ch =  . (5) in which a Taylor expansion has been made around VC = VDi .
23 Vinv0
1+ 1+ Here, Vndr = Qdr
n /Cox , so that

qND tSieff Qacc |VC =VDi , V
dr
Subsequently, we incorporate saturation in the channel-region  dr
GDi > VFB
current Ich by taking an effective potential drop VDiS,e accord- Vndr VC =VDi = qN t CQoxdr .
ing to [13], which takes the minimum of VDiS and Vsat,ch in a D Sieff dep |VC =VDi , V

< V dr
Cox GDi FB
smooth manner. (12)
900 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 53, NO. 4, APRIL 2006

Fig. 5. Measured (symbols) and modeled (solid lines) drain-to-source current


IDS in the linear operating regime, for VDS = 0.25 V and VSB = 0, 0.5,
Fig. 4. Measured (symbols) and modeled (solid lines) drain-to-source current
1, 1.5, and 2 V, for Wmask = 20 m, LPSOD = 2.6 m, and LLOCOS =
IDS in the subthreshold regime, for VSB = 0, 1, and 2 V, for Wmask =
3.5 m.
20 m, LPSOD = 2.6 m, and LLOCOS = 3.5 m.

while dr = (Vndr /VC )|VC =VDi . For simplicity, dr is taken


equal to one, which is the value in accumulation. Finally, to
account for mobility reduction due to the vertical electrical field
in accumulation, the effective electron mobility is taken as [1]

dr
dr
e = 1 0
 (13)
1 + 1acc 2 (V GS + VGD ) VFB
dr

where dr
0 is the zero-field electron mobility in the drift region.
Velocity saturation in the drift region occurs if

Idr 
= 0. (14)
VD Di VD Di =Vsat,dr

By use of (11) and (13), elaboration of (13) yields for the


saturation potential of the drift region

2Vndr VC =VDi
Vsat,dr =  . (15)
1 + 1 + 23dr Vndr |VC =VDi

Notice that, in contrast to the channel region, the saturation po-


tential in the drift region depends on the internal-drain potential
VDi . Subsequently, we incorporate saturation in the drift region Fig. 6. Measured (symbols) and modeled (solid lines) drain-to-source
by taking an effective potential drop VD Di,e according to [13], current IDS and output conductance |gDS | = |IDS /VDS |, for VGS =
1.4, 2.4, 3.4, and 4.4 V, and VSB = 0 V, for Wmask = 20 m, LPSOD =
which takes the minimum of VD Di and Vsat,dr in a smooth 2.6 m, and LLOCOS = 3.5 m.
manner.

in the subthreshold regime is the formulation of the final drain-


IV. RESULTS
to-source current IDS in surface potentials. Furthermore, the
We have characterized a 60-V LDMOS device, with a inclusion of drain-induced barrier lowering yields in this regime
thin-gate-oxide thickness tox = 38 nm, and a thick-field-oxide an accurate description of the increase in current for higher
thickness of 0.7 m. The device is processed in silicon-on- drain voltages.
insulator technology [16], and it has different mask widths In Fig. 5, we observe that also in the linear regime the model
Wmask , and lengths LPSOD , and LLOCOS . For the reference is accurate, even at the high-gate voltages where the effect of
device of Wmask = 20 m, LPSOD = 2.6 m, and LLOCOS = the gate extending over the drift region is significant. Thus, by
3.5 m, the resistance Rdrift is equal to 330 . In the model, inclusion of the potential drop across the accumulation layer
velocity saturation in the drift region is obtained by taking in the thin-gate-oxide drift region, an accurate description is
3dr = 0.9 V1 . obtained.
In Fig. 4, we observe that the model describes the subthresh- In Fig. 6, the drain-to-source current and the output con-
old current accurately, also at the transition from the weak to ductance are plotted versus drain voltage, for relatively low-
strong inversion regime. The reason for the accurate description gate voltages. In this operating regime, the current is controlled
AARTS AND KLOOSTERMAN: COMPACT MODELING OF LDMOS DEVICES INCLUDING QUASI-SATURATION 901

Fig. 9. Internal potentials of MM20 including quasi-saturation, for VGS =


Fig. 7. Measured (symbols) drain-to-source current IDS in comparison 3.4 V, for Wmask = 20 m, LPSOD = 2.6 m, and LLOCOS = 3.5 m
to MM20 including quasi-saturation (solid lines), at VGS = 2.4, 3.4, 4.4, (see also Fig. 7).
6, 8, 10, and 12 V and VSB = 0 V, for Wmask = 20 m, LPSOD = 2.6 m,
and LLOCOS = 3.5 m; cf. Fig. 3. By inclusion of quasi-saturation into
MM20, an accurate description is obtained, also for the high gate-voltages.

Fig. 10. Internal potentials of MM20 including quasi-saturation, for VGS =


12 V, for Wmask = 20 m, LPSOD = 2.6 m, and LLOCOS = 3.5 m
(see also Fig. 7).

ishes, indicating again the onset of quasi-saturation. Thus, by


Fig. 8. Measured (symbols) drain-to-source current IDS in comparison to inclusion of velocity saturation in the drift region of MM20,
MM20 including quasi-saturation (solid lines), at VDS = 3, 6, and 12 V,
and VSB = 0 V, for Wmask = 20 m, LPSOD = 2.6 m, and LLOCOS = an accurate description is obtained for the whole range of bias
3.5 m. conditions.
To demonstrate the effect of velocity saturation in the drift
by the channel region, and saturation of the current occurs region, in Figs. 9 and 10, the internal potentials of MM20
because the electrons in the channel region reach their saturated including quasi-saturation are plotted versus drain voltage. In
drift velocity (see Fig. 9). Notice that in Fig. 6, a negative Fig. 9, the internal potentials are given for the relatively low-
output conductance is obtained, which clearly demonstrates the gate voltage VGS = 3.4 V. In this figure, we observe that
effect of self-heating. In the model, the effect of self-heating is when the current saturates, the potential drop VDi VS over
incorporated by the temperature dependent model parameters. the channel region exceeds its saturation potential Vsat,ch . At
By subsequent use of a thermal network [7], which calculates the onset of saturation the potential drop VD VDi over the
the temperature rise due to self-heating, the current through the thin-gate-oxide drift region, on the other hand, is still below
device is affected accordingly. its saturation potential Vsat,dr ; only for higher drain voltages
In Fig. 7, the measured drain-to-source current is plotted also the potential drop over the thin-gate-oxide drift region
versus drain voltage, over the whole gate-bias range; see also exceeds its saturation potential. Thus, for VGS = 3.4 V, first,
Fig. 3. For the high gate-voltages, the current is controlled by the potential drop of the channel region exceeds its satura-
the drift region, and saturation of the current occurs because the tion potential, and the saturation current is controlled by the
electrons in the drift region reach their saturated drift velocity channel region.
(see Fig. 10). As we have seen in Fig. 3, MM20 without quasi- In Fig. 10, the internal potentials of MM20 are given for
saturation is not capable of describing the current correctly at the high gate-voltage VGS = 12 V. In contrast to Fig. 9, we
these high gate-voltages. By inclusion of quasi-saturation in observe in Fig. 10 that when the current saturates, the potential
MM20, however, we observe in Fig. 7 that an accurate current drop VD VDi over the thin-gate-oxide drift region exceeds its
description is obtained, also for the high gate-voltages. saturation potential Vsat,dr . The potential drop VDi VS over
In Fig. 8, the drain-to-source current versus gate voltage is the channel region, on the other hand, is significantly decreased
plotted. In this figure, we clearly see that for high gate-voltages for VGS = 12 V compared to the one for the low-gate voltage
the increase of a current with an increasing gate voltage dimin- VGS = 3.4 V, and it remains below its saturation potential
902 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 53, NO. 4, APRIL 2006

Vsat,ch . Thus, for VGS = 12 V, the saturation current is dictated [8] N. V. T. DHalleweyn, J. Benson, W. Redman-White, K. Mistry, and
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100 V. Successful use of the model in circuit simulations has
proven that the iteration procedure inside the model, used for
the calculation of the internal-drain potential, is robust and Annemarie C. T. Aarts received the M.Sc. degree in
technical mathematics in 1992, and the Ph.D. degree
sufficiently fast. Finally, it is mentioned that the source code for her research in instabilities in the extrusion of
and documentation of the model will become available in the polymers, in 1997, both from the Eindhoven Univer-
public domain [17]. sity of Technology, Eindhoven, The Netherlands.
In 1997, she joined Shell International Exploration
and Production, Rijswijk, The Netherlands. In 1999,
R EFERENCES she became a Senior Research Scientist with Philips
Research Laboratories, Eindhoven, The Netherlands,
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voltage lateral DMOS transistors suited for CACD, IEEE Trans. Electron Willy J. Kloosterman was born in Olst, The Nether-
Devices, vol. ED-33, no. 12, pp. 19641970, Dec. 1976. lands, in July 1951. He received the B.S. degree in
[4] C. M. Liu, F. C. Shone, and J. B. Kuo, A closed-form physical back-gate- mechanical engineering from the Technical College
bias dependent quasi-saturation model for SOI lateral DMOS devices with in Zwolle, Zwolle, The Netherlands, in 1974.
self-heating for circuit simulation, in Proc. Power Semicond. Devices ICs In 1974, he joined Philips Research Laborato-
(ISPSD), Yokohama, Japan, 1995, pp. 321324. ries, Eindhoven, The Netherlands. He worked on the
[5] J. Victory, C. C. Mc Andrew, R. Thoma, K. Joardar, M. Kniffin, dynamical behavior of CRTs, powder compaction
S. Merchant, and D. Moncoqut, A physically-based compact model models, and since 1980, on bipolar and MOS com-
for LDMOS transistors, in Proc. Simulation of Semicond. Processes pact transistor modeling. A major achievement is
Devices (SISPAD), Leuven, Belgium, 1998, pp. 271274. the development of the Mextram Bipolar transistor
[6] J. Jang, T. Arnborg, Z. Yu, and R. W. Dutton, Circuit model for model. He joined Philips Semiconductors in Ni-
power LDMOS including quasi-saturation, in Proc. Simulation Semi- jmegen, in 2001, and is now involved in the design, modeling, and characteriza-
cond. Processes Devices (SISPAD), Kyoto, Japan, 1999, pp. 1518. tion of advanced bipolar, CMOS, DMOS, JFET, high-voltage (10600 V) and
[7] A. C. T. Aarts, M. J. Swanenberg, and W. J. Kloosterman, Mod- passive devices.
elling of high-voltage SOILDMOS transistors including self-heating, in Mr. Kloosterman was a member of the modeling and characterization pro-
Proc. Simulation Semicond. Processes Devices (SISPAD), Athens, Greece, gram committee of the BiPolar /BiCMOS Circuit Technology Meeting in 1998
2001, pp. 246249. and 1999.