AN-501

APPLICATION NOTE
One Technology Way P.O. Box 9106 Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 www.analog.com

Aperture Uncertainty and ADC System Performance

by Brad Brannon and Allen Barlow

APERTURE UNCERTAINTY Figure 1 illustrates how an error in the sampling instant results
Aperture uncertainty is a key ADC concern when performing in an error in the sampled voltage. Mathematically, the
IF sampling. The terms aperture jitter and aperture uncertainty magnitude of the sampled voltage error is defined by the time
are synonymous and are frequently interchanged in the derivative of the signal function. Consider a sine wave input
literature. Aperture uncertainty is the sample-to-sample signal
variation in the encoding process. It has three distinct effects on v(t ) = A sin (2 ft ) (1)
system performance. First, it can increase system noise. Second,
it can contribute to the uncertainty in the actual phase of the The derivative is
sampled signal itself giving rise to increases in error vector dv (t )
magnitude. Third, it can heighten intersymbol interference = A 2f cos (2ft ) (2)
dt
(ISI). However, in typical communications applications, an
aperture uncertainty that is sufficiently small to meet system The maximum error occurs when the cosine function equals 1,
noise constraints results in negligible impact on phase that is, at t = 0.
uncertainty and ISI. For example, consider the case of sampling dv(0 ) (3)
an IF of 250 MHz. At that speed, even 1 ps of aperture jitter can = A2f
dt max
limit any ADCs SNR to only 56 dB, while for the same
conditions, the phase uncertainty error is only 0.09 degrees rms We see from Figure 1 that dv is the error in the sampled voltage
based on a 4 ns period. This is quite acceptable even for a corresponding to the jitter dt. For conceptual clarity, if we
demanding specification such as GSM. The focus of this relabel dv as Verr and dt as ta (aperture error) and rearrange the
analysis is, therefore, on overall noise contribution due to factors, we get
aperture uncertainty.
Verr = A2ft a (4)

If ta is given as an rms value, the derived Verr is also rms.

Although this is the error at maximum input slew and
represents an upper bound rather than a nominal, this simple
model proves surprisingly accurate and useful for estimating
the degradation in SNR as a function of sample clock jitter.
dv
JITTER AND SNR
As Equation 4 indicates, the error in the sampled voltage
increases linearly with input frequency, so at high frequencies,
ERROR VOLTAGE
for example, in IF sampled receiver applications, clock purity
becomes extremely important. Sampling is a mixing operation:
the input signal is multiplied by a local oscillator or in this case,
a sampling clock. Because multiplication in time is convolution
ENCODE in the frequency domain, the spectrum of the sample clock is
01399-001

convolved with the spectrum of the input signal. Considering

dt
that aperture uncertainty is wideband noise on the clock, it
Figure 1. RMS Jitter vs. RMS Noise
shows up as wideband noise in the sampled spectrum, periodic
and repeated around the sample rate.

Rev. A | Page 1 of 4
AN-501
Because ADC encode inputs have very high bandwidth, the Next, an FFT is done at high (IF) frequency. The high frequency
effects of clock input noise can extend out many times the chosen should be as high as possible. Again, the SNR value
sample rate itself and alias back into the baseband of the without harmonics is measured. This time jitter is a contributor
converter. Therefore, this wideband noise degrades the noise to noise and solving Equation 6 for ta yields
floor performance of the ADC. Consider a sinusoidal input 2
signal of amplitude A. Utilizing Equation 4, the SNR for an SNR
1 + 2
10 20 N
2
ADC limited by aperture uncertainty is (8)
ta =
2f
= 20 log(2ft a )
A
SNR = 20 log (5)
Verr where:
Equation 5 illustrates why systems that require high dynamic SNR = the high frequency SNR just measured
range and high analog input frequencies also require a low jitter = the value determined in the low frequency measurement.
encode source. For an analog input of 200 MHz and only EXAMPLE: JITTER AND THE AD9246
300 femtoseconds rms clock jitter, SNR is limited to only
68.5 dB, well below the level commonly achieved at lower The example shown here utilizes the AD9246 evaluation board,
speeds by 12-bit converters. Note in Equation 5 that the jitter a 14-bit, 125 MSPS ADC. An external clock oscillator such as a
limit of SNR is independent of the converter resolution. (For Wenzel Sprinter or Ultra-Low Noise provides a suitable encode
the case just mentioned, a 14-bit converter would do no better.) source. A mainstream RF synthesizer from Rohde & Schwarz or
Agilent can be used for the analog source. Typically, these
Aperture jitter is not always the performance limiter. Equation 6 generators have insufficient phase noise performance for use as
shows its effect in superposition with other noise sources. The the encode source. For more information about configuring
first term in the brackets is the jitter from Equation 5. To that, Analog Devices evaluation boards, please consult the individual
we must add terms for quantization noise, DNL, and thermal product data sheet.
noise. For other analytic purposes, each of these could be WALL OUTLET
100V TO 240V AC
47Hz TO 63Hz
broken out separately, but for simplicity in isolating the effect of 3.3V
+
jitter, we combine them here in a single additional term. 6V DC
2A MAX
SWITCHING
POWER
1/ 2

GND

VCC
1+
2 SUPPLY

SNR = 20 log(2 f t a ) + N
CHB
2 (6) PARALLEL
CMOS

2 OUTPUTS
HSC-ADC-EVALB-DC PC
EVALUATION FIFO DATA RUNNING
ROHDE & SCHWARZ, BOARD CAPTURE ADC
SMHU, BOARD ANALYZER
where: 2V p-p SIGNAL BAND-PASS
FILTER
XFMR
INPUT CHA
SYNTHESIZER
PARALLEL USB
f = analog input frequency. ROHDE & SCHWARZ,
SMHU, CLK
CMOS
OUTPUTS
CONNECTION

01399-002
2V p-p SIGNAL
ta = aperture uncertainty (jitter). SYNTHESIZER
SPI SPI SPI

= composite rms DNL in LSBs, including thermal noise. Figure 2. Aperture Uncertainty Measurement Setup with AD9246 Customer
N = number of bits. Evaluation Board

This simple equation provides considerable insight into the Figure 3 is a 5 average, 64 K FFT of the AD9246 sampling a 2.3
noise performance of a data converter. MHz sine wave at 125 MSPS. Analog Devices ADC AnalyzerTM
Software (www.analog.com/fifo) collects and processes the data
MEASURING SUBPICOSECOND JITTER to report SNR without harmonics. From the plots, the SNR is
Aperture uncertainty is readily determined by examining SNR 72.05 dBFS.
without harmonics as a function of analog input frequency. Two
measurements are required for the calculation. The first
measurement is done at a sufficiently low analog input
frequency that the effects of aperture uncertainty are negligible.
Since jitter is negligible, Equation 6 can be simplified and
rearranged to solve for , the composite DNL.
SNR
= 2N 10 20 1 (7)
Here, SNR is the low frequency value just measured.

Rev. A | Page 2 of 4
 AN-501
Device: AD9246
Device No.: 1
0 Figure 5 overlays plots of Equation 5 for various jitter values
10
Avcc: 1.8 Volts (the sloped lines) with ideal, quantization noise limited
Dvcc: 1.8 Volts 20
Encode: 125. MSPS performance at various resolutions (the horizontal lines), and is
30
Analog: 2.3 MHz
SNR: 71.06 dB 40
a useful guide for quickly determining jitter limits based on
SNRFS: 72.05 dBFS
50
analog input frequency and SNR requirements.
UDSNR: 96.62 dB
NF: 30.69 dB 60 100
SINAD: 70.87 dB
70 16 BITS
Fund: 0.999 dBfs
2nd: 90.62 dBc 80
3rd: 86.59 dBc 2 3 + 90
90
4th: 104.15 dBc 6
5th: 108.51 dBc 100 14 BITS
4
6th: 94.04 dBc 5
110
WoSpur: 90.53 dBc + 0.5 0.2 0.1
80 2p 1p 5 25

SNR (dB)
THD: 84.55 dBc 120 s s ps ps ps
SFDR: 86.59 dBc
130 12 BITS
Noise Floor: 117.21 dBFS

01399-003
0 5 10 15 20 25 30 35 40 45 50 55 60
Samples: 65536 70
FREQUENCY (MHz)
Windowing: None

Figure 3. 2.3 MHz FFT 10 BITS

60
Using this value for SNR in Equation 7 gives a composite DNL
() for this converter of 3.09 LSB.

01399-005
50
10 100 1000
Next, the degradation in SNR as a function of analog input INPUT (MHz)
frequency is found. Figure 4 shows data from the same setup and Figure 5. Signal-to-Noise Ratio Due to Aperture Jitter
clock, but using an analog input frequency of 201 MHz. Here, the CLOCK DISTRIBUTION
noise floor has risen and the resulting SNR is 69.05 dBFS.
System clocks commonly must be distributed to multiple
Device: AD9246
Device No.: 1
0 converters, and additionally to the FPGAs, ASICs, and DSPs
10
Avcc: 1.8 Volts included in the signal chain. There are several ways to distribute
Dvcc: 1.8 Volts 20
Encode: 125. MSPS clocks with the low jitter demanded by the converters.
Analog: 49.004 MHz
30
SNR: 67.98 dB 40
SNRFS: 69.05 dBFS
If the sample clock is generated as a sinewave, it can be
50
UDSNR: 93.4 dB distributed using power dividers and delivered to the ADC with
NF: 33.69 dB 60
SINAD: 66.75 dB a transformer as shown in Figure 6. This solution is simple and
70
Fund: 1.069 dBfs 3
2nd: 78.21 dBc 80
2 works well for many applications, especially in situations
3rd: 74.41 dBc
90
+
6
involving single-ended to differential conversion.
4th: 103.12 dBc
5th: 104.29 dBc 100
5 4
6th: 93.26 dBc
110
However, more often than not the clock is a logic signal sourced
WoSpur: 90.65 dBc +
THD: 72.85 dBc 120 directly from a PLL, VCO, or VCXO. In these cases, it is
SFDR: 74.41 dBc
Noise Floor: 114.2 dBFS
130 advantageous to use logic gates to fan out the signal and to drive the
01399-004

0 5 10 15 20 25 30 35 40 45 50 55 60
Samples: 65536
FREQUENCY (MHz)
data converters. Table 1 summarizes the typical jitter that can be
Windowing: None
achieved with a variety of logic families. It should be noted that
Figure 4. 201 MHz FFT many of the older families, and even current FPGAs, cannot deliver
Using this SNR and the previous solution for , Equation 8 gives acceptable performance. Some newer, high-speed devices do
provide acceptable jitter and have the ability to translate single-
2
69.05
1 + 3.092 2 ended signals into differential signals as shown in Figure 7.
10
214
20
Table 1.
(9)
ta = = 197 fs rms Gate Type Jitter
2 201 10 6
FPGA 1 33 to 50 ps
This value, 197 fs, is the combined aperture uncertainty for the 74LS00 4.94 ps
AD9246 plus the clock oscillator. Since total noise squared is the 74HCT00 2.20 ps
sum of the squares of individual contributors, the jitter of the 74ACT00 0.99 ps
ADC itself is readily determined if the jitter of the source clock MC100EL16 (PECL) 0.70 ps
is known. Here a Wenzel ULN clock oscillator with about 50 fs AD9510 Clock Synthesis and Distribution 0.22 ps
jitter is used, giving a jitter for the ADC of about 190 fs. These NBSG16 (Reduced Swing ECL) 0.20 ps
simple measurements confirm that it is possible to measure very 1
Does not include the jitter introduced by input structure or internal routing
small aperture uncertainty numbers using readily available gates, or the jitter associated with the use of internal DLL/PLL structures.
hardware and simple numeric calculations. Based on product data sheet peak-to-peak values ranging from 100 ps to
300 ps peak.

Rev. A | Page 3 of 4
AN-501
CLOCK ADT11WT
CLK+ In addition, the AD9510 includes many other features not
SOURCE
0.1F available in discrete logic such as selectable output types (LVDS,
AD9444
CLK PECL, and CMOS) and programmable fine delays. Figure 10

01399-006
HSMS2812
DIODES
shows how the AD9510 can be used in a typical low jitter
solution.
Figure 6. Distribution and Differential Encode Options
VS GND RSET CPRSET VCP
VT
DISTRIBUTION PLL
0.1F REF
AD9510 REF
ENCODE REFIN
ECL/ R DIVIDER PHASE
REFINB CHARGE
PECL 0.1F AD9444 FREQUENCY
DETECTOR PUMP CP
N DIVIDER
ENCODE SYNCB,
FUNCTION RESETB
01399-007
PDB PLL STATUS
SETTINGS
VT
CLK1 CLK2
Figure 7. Active Differential Drive Circuit CLK1B CLK2B
PROGRAMMABLE
DIVIDERS AND
PHASE ADJUST LVPECL
Clock trees employing cascaded gates are commonly used in /1, /2, /3... /31, /32
OUT0
OUT0B
digital circuits (see Figure 8), but jitter accumulates as the clock LVPECL
progresses down the tree. /1, /2, /3... /31, /32
OUT1
OUT1B
LVPECL
ADC ENCODE INPUT OUT2
/1, /2, /3... /31, /32
OUT2B
ADC DATA LATCH SCLK LVPECL
SYSTEM CLOCK SDIO SERIAL OUT3
CONTROL /1, /2, /3... /31, /32
SDO PORT OUT3B
CSB LVDS/CMOS
OUT4
DAC CLOCK INPUT /1, /2, /3... /31, /32
OUT4B
LVDS/CMOS
DAC DATA LATCH OUT5
/1, /2, /3... /31, /32 T
OUT5B
(A) LVDS/CMOS
OUT6
/1, /2, /3... /31, /32 T
SYSTEM CLOCK OUT6B
LVDS/CMOS
ADC ENCODE INPUT OUT7
01399-008

/1, /2, /3... /31, /32

01399-009
OUT7B
(B)

Figure 8. Clock Distribution Chains Figure 9. AD9510 Clock Synthesis and Distribution

In a cascade of just three NBSG16 gates (one of the better 16

performers), the cumulative rms jitter increases to 350 fs, which AD6633 AD9786 TX

is a significant impact on system performance of an IF sampling IF = ~190MHz MAIN TX

92.16MHz 491.52MHz
system. It is better to avoid conventional clock trees altogether,
and instead, approach clock generation and distribution as a LOOP FILTER

system level function. 32.768MHz

DSP AD9510
REFERENCE

Devices such as the AD9510 have optimized the clock paths to VCXO

minimize total rms noise. By comparing Figure 8 and Figure 9,

92.16MHz 92.16MHz
it is clear that the AD9510 offers the same function for clock
14
distribution as that in Figure 8, but with an additive jitter of AD6636 AD9246 RX
only 220 fs. In addition, this part includes an ultra low noise IF = ~190MHz MAIN RX
PLL similar to the ADF4106 that allows complete clock cleanup,
92.16MHz 92.16MHz
synthesis, and distribution in a single package.
14
AD6636 AD9246 RX
01399-010

IF = ~190MHz
DIVERSITY
RX
Figure 10. Typical Clock Distribution Application

2006 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
AN01399-0-3/06(A)

Rev. A | Page 4 of 4