A B C D E

Compal Confidential
MODEL NAME : ZIVY1
PCB NO : LA-B131P
1 1

BOM P/N : SKU1_4519RY38L05 (I5-4200U 1.6GHZ - Hynix 2G)

SKU2_4519RY38L05 (I5-4200U 1.6GHZ - Micro 2G)
SKU3_4519RY38L08 (I7-4500U 1.8GHZ - Hynix 4G) FAI
SKU3_4519RY38L08 (I7-4510U 1.8GHZ - Hynix 4G) main SMT
SKU4_4519RY38L07 (I2-4200U 1.6GHZ - Micro 4G)
SKU5_4519RY38L05 (I5-4200U 1.6GHZ - Samsung 2G)
SKU6_4519RY38L07 (I5-4200U 1.6GHZ - Samsung 4G)

Compal Confidential
2 2

Lamborghini Y40 M/B Schematics Document

Intel Haswell / Broadwell ULT Processor + AMD Venus XTX
3 3

2014-03-03
REV:1.0

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/03/03 Deciphered Date 2015/03/03 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Sheet
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-B131P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 04, 2014 Sheet 1 of 52
A B C D E
 A B C D E

Compal confidential
File Name :ZIVY1

AMD Venus XTX (M2) 204pin DDR3L-SO-DIMM X2

Memory BUS page 15~16
VRAM 256X16, 128X16 PCIE x4
1 DDR3 x 8 1.35V DDR3L 1600 1

page 17~24

eDP x1
SATA 3.0
2 Lane
SATA3.0 HDD (SSD)
page 29
EDP Conn.
page 25

Intel Haswell / Broadwell USB Charger

TPS2544
HDMI Conn. HDMI x 4 lanes DDI x1 ULT Processor page 32

page 28
2 1168pin BGA 2

port 3 USB 3.0 USB 2.0 CMOS

LAN( 10/100/1GbE) PCIe 2.0 5GT/s PCIE x1 page 04~14 USB 3.0
RJ45 Conn Realtek RTL8111GUL-CG conn x2 conn x1 Camera
page 26 page 26
port 1, 2 (Left) port 3 (Right)
page 32 page 25

Int. Speaker Conn. USB 2.0x8

page 27
AUDIO CODEC HD Audio Audio/B
Realtek ALC283 WLAN+BT Touch Panel
Combo jack & S/PDIF PCIE x1
page 27 (NGFF E type)
Audio/B page 29 Card Reader
RTS5249-GR page 25
PCIE x1
3
SYS BIOS ROM 8M SPI 3
WINBOND W25Q64FVSSIQ
page 7
Card Reader
Conn.

LPC BUS Card Reader/B

CLK=24MHz

KBC
Sub-board NUVOTON
NPCE288N page 30
Power Board
PS/2

LED Board Lid SW Touch Pad Int.KBD Thermal Sensor

4
EMC1403-2-AIZL-TR 4
TCS20DLR
Audio/B page 31 page 31 page 31
AUDIO Board

Card Reader Board Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/03/03 Deciphered Date 2015/03/03 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagram
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-B131P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 04, 2014 Sheet 2 of 52
A B C D E
 1 2 3 4 5

Voltage Rails
SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

+5VS Full ON HIGH HIGH HIGH HIGH ON ON ON ON

power +3VS PCB part
plane S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
+1.5VS
ZZZ @ ZZZ
+1.05VS S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
+5VALW
+CPU_CORE
B+ +1.35V S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
+0.675VS
A
+3VALW A
+VGA_CORE S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF DA8000ZQ010 DAZ14P00100
PCB 14P LA-B131P REV1 M/B 4 PCB ZIVY1 LA-B131P LS-B131P/B132/B133 02
+MEM_GFX
State SVT
+3VGA
+1.8VGA
BOM Structure Table
+VGA_PCIE
BTO Item BOM Structure
Unpop @ CPU part (R1)
@CONN@ / @DIS@
S0 U9 CPU3@ U9 CPU1@ U9 CPU2@ U9 CPU4@
O O O O @EMI@ / @ESD@
CPU OPTION CPU1@ ~ CPU4@ HSW R3 R1 R3 R1
S3
O O O X AMD Venus XTX DIS@ I5-4200U_1.6G I5-4210U_1.7GHZ I7-4500U_1.8G I7-4510U_2GHZ
SA00006SMC0 SA00007LO10 SA00006SLA0 SA00007M700
S5 S4/AC
VRAM Option V2G@ / V4G@
O O X X HYN2@ / HYN4@ SVT
SAM2@ / SAM4@
S5 S4/ Battery only
X X X X MIC2@ / MIC4@
Platform BDW@ / HSW@ BDW
S5 S4/AC & Battery DS3 DS3@
don't exist X X X X
NODS3 NODS3@
LAN RTL8111GUS SWR@ / LDO@
EMI PART EMI@
ESD PART ESD@
Crystal NOGCLK@ VRAM * 8 (R1)
B B
Green CLK GCLK@ ZZZ V2G@ ZZZ V4G@
SATA Repeater TI@ / Parade@ 2G 4G
EC 9022@ / 9012@
Connector CONN@
X7654038L01 X7654038L04
H5TC2G63FFR-11C H5TC4G63AFR-11C

U21 HYN2@ U16 HYN2@ U15 HYN2@ U20 HYN2@ RV6 HYN2@ U14 HYN4@ U16 HYN4@ U18 HYN4@ U20 HYN4@ RV6 HYN4@

EC SM Bus1 address EC SM Bus2 address H5TC2G63FFR-11C H5TC2G63FFR-11C 10K_0402_5% H5TC4G63AFR-11C H5TC4G63AFR-11C 10K_0402_5%
H5TC2G63FFR-11C H5TC2G63FFR-11C H5TC4G63AFR-11C H5TC4G63AFR-11C
RV8 HYN2@ RV7 HYN4@
Device Address Device Address
U19 HYN2@ U17 HYN2@ U14 HYN2@ U18 HYN2@ U15 HYN4@ U17 HYN4@ U19 HYN4@ U21 HYN4@
Smart Battery 0001 0010 Thermal Sensor 1001 101xb

10K_0402_5% 10K_0402_5%
PCH SM Bus address H5TC2G63FFR-11C H5TC2G63FFR-11C RV10 HYN2@ H5TC4G63AFR-11C H5TC4G63AFR-11C RV9 HYN4@
H5TC2G63FFR-11C H5TC2G63FFR-11C H5TC4G63AFR-11C H5TC4G63AFR-11C
SA00006H410 SA00006E830
Device Address
DDR_JDIMM1 1010 000x A0h
DDR_JDIMM2
Hynix_X7654038L01 10K_0402_5% Hynix_X7654038L04 10K_0402_5%
1010 010x A4h
TP module

U21 MIC2@ U18 MIC2@ U14 MIC2@ U19 MIC2@ RV6 MIC2@

C U20 MIC4@ U14 MIC4@ U17 MIC4@ U18 MIC4@ RV5 MIC4@ C

SMBUS Control Table

MT41J128M16JT-093G:K MT41J128M16JT-093G:K 10K_0402_5%
MT41J128M16JT-093G:K MT41J128M16JT-093G:K
RV8 MIC2@ MT41J256M16HA-093G MT41J256M16HA-093G 10K_0402_5%
SOURCE BATT VGA SODIMM EC-KB9022 TP Smart Charge Thermal Sensor MT41J256M16HA-093G MT41J256M16HA-093G
U20 MIC2@ U16 MIC2@ U15 MIC2@ U17 MIC2@ RV8 MIC4@

U21 MIC4@ U15 MIC4@ U16 MIC4@ U19 MIC4@

SMB_EC_CK1
SMB_EC_DA1
EC
V X X X X V X 10K_0402_5%
MT41J128M16JT-093G:K MT41J128M16JT-093G:K RV9 MIC2@ 10K_0402_5%
MT41J128M16JT-093G:K MT41J128M16JT-093G:K
SMBCLK
SMBDATA
PCH X X V X V X X SA000067510 MT41J256M16HA-093G MT41J256M16HA-093G
MT41J256M16HA-093G MT41J256M16HA-093G
RV10 MIC4@

SA000077K10
SML0CLK
SML0DATA
PCH X X X X X X X Micron_X7654038L02
10K_0402_5%
Micron_X7654038L05 10K_0402_5%
SML1CLK
SML1DATA
PCH X V X V X X V
U15 SAM2@ U21 SAM2@ U17 SAM2@ U14 SAM2@ RV6 SAM2@ U21 SAM4@ U14 SAM4@ U16 SAM4@ U19 SAM4@ RV5 SAM4@

USB2.0
K4W2G1646Q-BC1A K4W2G1646Q-BC1A 10K_0402_5% K4W4G1646D-BC1A K4W4G1646D-BC1A 10K_0402_5%
Port 0 1 2 3 4 5 6 7 K4W2G1646Q-BC1A K4W2G1646Q-BC1A K4W4G1646D-BC1A K4W4G1646D-BC1A
RV7 SAM2@ RV8 SAM4@

Left USB3.0 Left USB3.0 Right USB2.0 Touch Panel Camera BT (NGFF) U20 SAM2@ U19 SAM2@ U16 SAM2@ U18 SAM2@ U20 SAM4@ U17 SAM4@ U15 SAM4@ U18 SAM4@

D 10K_0402_5% 10K_0402_5% D

K4W2G1646Q-BC1A K4W2G1646Q-BC1A RV10 SAM2@ K4W4G1646D-BC1A K4W4G1646D-BC1A RV9 SAM4@

K4W2G1646Q-BC1A K4W2G1646Q-BC1A K4W4G1646D-BC1A K4W4G1646D-BC1A
SA000068U50 SA000076P10
Flexible I/O Capable Ports
HSIO Port 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Samsung_X7654038L03 10K_0402_5% Samsung_X7654038L06 10K_0402_5%
1 2
USB 3.0 USB3.0_1 USB3.0_2
1 2
CardReader
3
LAN
4
WLAN
5-L0
GPU_Venus
5-L1
GPU_Venus
5-L2 5-L3
GPU_Venus GPU_Venus
6-L0 6-L1 6-L2 6-L3 Security Classification Compal Secret Data Compal Electronics, Inc.
PCIe Issued Date 2014/03/03 Deciphered Date 2015/03/03 Title

3 2 1 0 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
SATA HDD(SSD) AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-B131P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 04, 2014 Sheet 3 of 52
1 2 3 4 5
 5 4 3 2 1

D D

U9A HASWELL_MCP_E

C54 C45 EDP_TXN0 25

DDI1_TXN0 EDP_TXN0
C55 B46 EDP_TXP0 25
DDI1_TXP0 EDP_TXP0
B58 A47 EDP_TXN1 25
DDI1_TXN1 EDP_TXN1
C58 DDI1_TXP1 EDP_TXP1 B47 EDP_TXP1 25
B55 DDI1_TXN2
A55 DDI1_TXP2 EDP_TXN2 C47 eDP
A57 DDI1_TXN3 EDP_TXP2 C46
B57 DDI1_TXP3 EDP_TXN3 A49
DDI EDP B49
C1 0.1U_0402_16V7K CPU_DP2_N0 EDP_TXP3
28 HDMI_TX2-_CK 1 2 C51
C2 0.1U_0402_16V7K CPU_DP2_P0 DDI2_TXN0
28 HDMI_TX2+_CK 1 2 C50 DDI2_TXP0 EDP_AUXN A45 EDP_AUXN 25
C3 1 2 0.1U_0402_16V7K CPU_DP2_N1 C53 B45 EDP_AUXP 25
28 HDMI_TX1-_CK DDI2_TXN1 EDP_AUXP
C4 1 2 0.1U_0402_16V7K CPU_DP2_P1 B54
28 HDMI_TX1+_CK CPU_DP2_N2 DDI2_TXP1 EDP_COMP R1 1
HDMI C5 1 2 0.1U_0402_16V7K C49 D20 2 24.9_0402_1% +VCCIOA_OUT
28 HDMI_TX0-_CK CPU_DP2_P2 DDI2_TXN2 EDP_RCOMP CPU_INV_PWM
C6 1 2 0.1U_0402_16V7K B50 A43 @
28 HDMI_TX0+_CK CPU_DP2_N3 DDI2_TXP2 EDP_DISP_UTIL
C7 1 2 0.1U_0402_16V7K A53 T20
28 HDMI_CLK-_CK CPU_DP2_P3 DDI2_TXN3
C8 1 2 0.1U_0402_16V7K B53
28 HDMI_CLK+_CK DDI2_TXP3

EDP_COMP:
Trace width=20 mils,Spacing=25mil,Max length=100mils
1 OF 19 Rev1p2

C C

U9B HASWELL_MCP_E

T1 @ D61
T2 @ PROC_DETECT MISC
K61 CATERR
30 H_PECI N62 J62
PECI PRDY
PREQ K62
1 2 R3 R4 JTAG E60 XDP_TCK @ T3
+1.05VS PROC_TCK
62_0402_5% 56_0402_5% E61 XDP_TMS @ T4
PROC_TMS
30 H_PROCHOT# 1 2 H_PROCHOT#_R K63 E59 XDP_TRST# @ T5
PROCHOT THERMAL
PROC_TRST XDP_TDI @ T6
F63
PROC_TDI XDP_TDO @ T7
F62
PROC_TDO
R5 1 2 10K_0402_5% H_CPUPWRGD C61 PROCPWRGD PWR
J60
BPM#0
DDR3 Compensation Signals BPM#1
H60
H61
BPM#2
H62
B BPM#3 B
R6 1 2 200_0402_1% SM_RCOMP0 AU60
SM_RCOMP0 BPM#4
K59
DDR3
R7 1 2 120_0402_1% SM_RCOMP1 AV60
SM_RCOMP1 BPM#5
H63
R8 1 2 100_0402_1% SM_RCOMP2 AU61
SM_RCOMP2 BPM#6
K60
DDR3 Compensation Signals: DIMM_DRAMRST#AV15 J61
DDR_PG_CTRL AV61 SM_DRAMRST BPM#7
20mils to comp signals 15 DDR_PG_CTRL SM_PG_CNTL1

25mils to non-comp signals 2 OF 19 Rev1p2

500mil for Max trace length

+1.35V
1

R9
470_0402_5%
2

H_CPUPWRGD
DIMM_DRAMRST#
DIMM_DRAMRST# 15,16
1
C338 ESD@ 1
100P_0402_50V8J
2 ESD@ C9
A A
100P_0402_50V8J
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/03/03 Deciphered Date 2015/03/03 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BDW ULT(1/11) DDI,MSIC,XDP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B131P
Date: Tuesday, March 04, 2014 Sheet 4 of 52
5 4 3 2 1
 5 4 3 2 1

D D

U9D HASWELL_MCP_E

U9C HASWELL_MCP_E

DDR_B_D0 AY31 AM38

DDR_A_D0 DDR_B_D1 SB_DQ0 SB_CK#0 SA_CLK_DDR#2 16
AH63 AU37 SA_CLK_DDR#0 15 AW31 AN38 SA_CLK_DDR2 16
DDR_A_D1 SA_DQ0 SA_CLK#0 DDR_B_D2 SB_DQ1 SB_CK0
AH62 AV37 SA_CLK_DDR0 15 AY29 AK38 SA_CLK_DDR#3 16
DDR_A_D2 SA_DQ1 SA_CLK0 DDR_B_D3 SB_DQ2 SB_CK#1
AK63 AW36 SA_CLK_DDR#1 15 AW29 AL38 SA_CLK_DDR3 16
DDR_A_D3 SA_DQ2 SA_CLK#1 DDR_B_D4 SB_DQ3 SB_CK1
AK62 SA_DQ3 SA_CLK1 AY36 SA_CLK_DDR1 15 AV31 SB_DQ4
DDR_A_D4 AH61 DDR_B_D5 AU31 AY49
SA_DQ4 SB_DQ5 SB_CKE0 DDRB_CKE2_DIMM 16
DDR_A_D5 AH60 AU43 DDR_B_D6 AV29 AU50
DDR_A_D6 SA_DQ5 SA_CKE0 DDRA_CKE0_DIMM 15 DDR_B_D7 SB_DQ6 SB_CKE1 DDRB_CKE3_DIMM 16
AK61 SA_DQ6 SA_CKE1 AW43 DDRA_CKE1_DIMM 15 AU29 SB_DQ7 SB_CKE2 AW49
DDR_A_D7 AK60 AY42 DDR_B_D8 AY27 AV50
DDR_A_D8 SA_DQ7 SA_CKE2 DDR_B_D9 SB_DQ8 SB_CKE3
AM63 SA_DQ8 SA_CKE3 AY43 AW27 SB_DQ9
DDR_A_D9 AM62 DDR_B_D10 AY25 AM32
DDR_A_D10 SA_DQ9 DDR_B_D11 SB_DQ10 SB_CS#0 DDRB_CS2_DIMM# 16
AP63 SA_DQ10 SA_CS#0 AP33 DDRA_CS0_DIMM# 15 AW25 SB_DQ11 SB_CS#1 AK32 DDRB_CS3_DIMM# 16
DDR_A_D11 AP62 AR32 DDR_B_D12 AV27
SA_DQ11 SA_CS#1 DDRA_CS1_DIMM# 15 SB_DQ12
DDR_A_D12 AM61 DDR_B_D13 AU27 AL32 DDRB_ODT0 @ T8
DDR_A_D13 SA_DQ12 SB_DQ13 SB_ODT0
AM60 SA_DQ13 SA_ODT0 AP32 DDRA_ODT0 @ T9 DDR_B_D14 AV25 SB_DQ14
DDR_A_D14 AP61 DDR_B_D15 AU25 AM35
DDR_A_D15 SA_DQ14 DDR_B_D16 SB_DQ15 SB_RAS DDR_B_RAS# 16
AP60 SA_DQ15 SA_RAS
AY34 DDR_A_RAS# 15 AM29 SB_DQ16 SB_WE
AK35 DDR_B_WE# 16
DDR_A_D16 AP58 AW34 DDR_B_D17 AK29 AM33
DDR_A_D17 SA_DQ16 SA_WE DDR_A_WE# 15 DDR_B_D18 SB_DQ17 SB_CAS DDR_B_CAS# 16
AR58 SA_DQ17 SA_CAS AU34 DDR_A_CAS# 15 AL28 SB_DQ18
DDR_A_D18 AM57 DDR_B_D19 AK28 AL35
DDR_A_D19 SA_DQ18 DDR_B_D20 SB_DQ19 SB_BA0 DDR_B_BS0 16
AK57 SA_DQ19 SA_BA0 AU35 DDR_A_BS0 15 AR29 SB_DQ20 SB_BA1 AM36 DDR_B_BS1 16
DDR_A_D20 AL58 AV35 DDR_B_D21 AN29 AU49
SA_DQ20 SA_BA1 DDR_A_BS1 15 SB_DQ21 4 OF 19 SB_BA2 DDR_B_BS2 16
DDR_A_D21 AK58 AY41 DDR_B_D22 AR28
DDR_A_D22 SA_DQ21 SA_BA2 DDR_A_BS2 15 DDR_B_D23 SB_DQ22 DDR_B_MA0
AR57 SA_DQ22 AP28 SB_DQ23 SB_MA0 AP40
DDR_A_D23 AN57 3 OF 19 AU36 DDR_A_MA0 DDR_B_D24 AN26 AR40 DDR_B_MA1
C DDR_A_D24 SA_DQ23 SA_MA0 SB_DQ24 SB_MA1 C
AP55 SA_DQ24 SA_MA1 AY37 DDR_A_MA1 DDR_B_D25 AR26 SB_DQ25 SB_MA2 AP42 DDR_B_MA2
DDR_A_D25 AR55 AR38 DDR_A_MA2 DDR_B_D26 AR25 AR42 DDR_B_MA3
DDR_A_D26 SA_DQ25 SA_MA2 SB_DQ26 SB_MA3
AM54 SA_DQ26 SA_MA3 AP36 DDR_A_MA3 DDR_B_D27 AP25 SB_DQ27 SB_MA4 AR45 DDR_B_MA4
DDR_A_D27 AK54 AU39 DDR_A_MA4 DDR_B_D28 AK26 AP45 DDR_B_MA5
DDR_A_D28 SA_DQ27 SA_MA4 SB_DQ28 SB_MA5
AL55 SA_DQ28 SA_MA5 AR36 DDR_A_MA5 DDR_B_D29 AM26 SB_DQ29 SB_MA6 AW46 DDR_B_MA6
DDR_A_D29 AK55 AV40 DDR_A_MA6 DDR_B_D30 AK25 AY46 DDR_B_MA7
DDR_A_D30 SA_DQ29 SA_MA6 SB_DQ30 SB_MA7
AR54 SA_DQ30 SA_MA7 AW39DDR_A_MA7 DDR_B_D31 AL25 SB_DQ31 SB_MA8 AY47 DDR_B_MA8
DDR_A_D31 AN54 AY39 DDR_A_MA8 DDR_B_D32 AY23 AU46 DDR_B_MA9
DDR_A_D32 SA_DQ31 SA_MA8 SB_DQ32 SB_MA9
AY58 AU40 DDR_A_MA9 DDR_B_D33 AW23 AK36 DDR_B_MA10
DDR_A_D33 SA_DQ32 SA_MA9 SB_DQ33 DDR CHANNEL B SB_MA10
AW58 AP35 DDR_A_MA10 DDR_B_D34 AY21 AV47 DDR_B_MA11
DDR_A_D34 SA_DQ33 SA_MA10 SB_DQ34 SB_MA11
AY56 AW41DDR_A_MA11 DDR_B_D35 AW21 AU47 DDR_B_MA12
DDR_A_D35 SA_DQ34 DDR CHANNEL A SA_MA11 SB_DQ35 SB_MA12
AW56 AU41 DDR_A_MA12 DDR_B_D36 AV23 AK33 DDR_B_MA13
DDR_A_D36 SA_DQ35 SA_MA12 SB_DQ36 SB_MA13
AV58 AR35 DDR_A_MA13 DDR_B_D37 AU23 AR46 DDR_B_MA14
DDR_A_D37 SA_DQ36 SA_MA13 SB_DQ37 SB_MA14
AU58 AV42 DDR_A_MA14 DDR_B_D38 AV21 AP46 DDR_B_MA15
DDR_A_D38 SA_DQ37 SA_MA14 SB_DQ38 SB_MA15
AV56 AU42 DDR_A_MA15 DDR_B_D39 AU21
DDR_A_D39 SA_DQ38 SA_MA15 DDR_B_D40 SB_DQ39 DDR_B_DQS#0
AU56 AY19 AW30
DDR_A_D40 SA_DQ39 SB_DQ40 SB_DQSN0
AY54 AJ61 DDR_A_DQS#0 DDR_B_D41 AW19 AV26 DDR_B_DQS#1
DDR_A_D41 SA_DQ40 SA_DQSN0 SB_DQ41 SB_DQSN1
AW54 AN62 DDR_A_DQS#1 DDR_B_D42 AY17 AN28 DDR_B_DQS#2
DDR_A_D42 SA_DQ41 SA_DQSN1 SB_DQ42 SB_DQSN2
AY52 AM58 DDR_A_DQS#2 DDR_B_D43 AW17 AN25 DDR_B_DQS#3
DDR_A_D43 SA_DQ42 SA_DQSN2 SB_DQ43 SB_DQSN3
AW52 AM55 DDR_A_DQS#3 DDR_B_D44 AV19 AW22 DDR_B_DQS#4
DDR_A_D44 SA_DQ43 SA_DQSN3 SB_DQ44 SB_DQSN4
AV54 AV57 DDR_A_DQS#4 DDR_B_D45 AU19 AV18 DDR_B_DQS#5
DDR_A_D45 SA_DQ44 SA_DQSN4 SB_DQ45 SB_DQSN5
AU54 AV53 DDR_A_DQS#5 DDR_B_D46 AV17 AN21 DDR_B_DQS#6
DDR_A_D46 SA_DQ45 SA_DQSN5 SB_DQ46 SB_DQSN6
AV52 AL43 DDR_A_DQS#6 DDR_B_D47 AU17 AN18 DDR_B_DQS#7
DDR_A_D47 SA_DQ46 SA_DQSN6 SB_DQ47 SB_DQSN7
AU52 AL48 DDR_A_DQS#7 DDR_B_D48 AR21
DDR_A_D48 SA_DQ47 SA_DQSN7 DDR_B_D49 SB_DQ48 DDR_B_DQS0
AK40 AR22 AV30
DDR_A_D49 SA_DQ48 SB_DQ49 SB_DQSP0
AK42 AJ62 DDR_A_DQS0 DDR_B_D50 AL21 AW26 DDR_B_DQS1
DDR_A_D50 SA_DQ49 SA_DQSP0 SB_DQ50 SB_DQSP1
AM43 AN61 DDR_A_DQS1 DDR_B_D51 AM22 AM28 DDR_B_DQS2
DDR_A_D51 SA_DQ50 SA_DQSP1 SB_DQ51 SB_DQSP2
AM45 AN58 DDR_A_DQS2 DDR_B_D52 AN22 AM25 DDR_B_DQS3
DDR_A_D52 SA_DQ51 SA_DQSP2 SB_DQ52 SB_DQSP3
AK45 AN55 DDR_A_DQS3 DDR_B_D53 AP21 AV22 DDR_B_DQS4
DDR_A_D53 SA_DQ52 SA_DQSP3 SB_DQ53 SB_DQSP4
AK43 AW57DDR_A_DQS4 DDR_B_D54 AK21 AW18 DDR_B_DQS5
DDR_A_D54 SA_DQ53 SA_DQSP4 SB_DQ54 SB_DQSP5
AM40 AW53DDR_A_DQS5 DDR_B_D55 AK22 AM21 DDR_B_DQS6
DDR_A_D55 SA_DQ54 SA_DQSP5 SB_DQ55 SB_DQSP6
AM42 AL42 DDR_A_DQS6 DDR_B_D56 AN20 AM18 DDR_B_DQS7
B DDR_A_D56 SA_DQ55 SA_DQSP6 SB_DQ56 SB_DQSP7 B
AM46 AL49 DDR_A_DQS7 DDR_B_D57 AR20
DDR_A_D57 SA_DQ56 SA_DQSP7 DDR_B_D58 SB_DQ57
AK46 AK18
DDR_A_D58 SA_DQ57 DDR_B_D59 SB_DQ58
AM49 AP49 SM_DIMM_VREFCA 15 AL18
DDR_A_D59 SA_DQ58 SM_VREF_CA DDR_B_D60 SB_DQ59
AK49 AR51 SA_DIMM_A_VREFDQ 15 AK20
DDR_A_D60 SA_DQ59 SM_VREF_DQ0 DDR_B_D61 SB_DQ60
AM48 AP51 SA_DIMM_B_VREFDQ 16 AM20
DDR_A_D61 SA_DQ60 SM_VREF_DQ1 DDR_B_D62 SB_DQ61
AK48 AR18
DDR_A_D62 SA_DQ61 DDR_B_D63 SB_DQ62
AM51 AP18
DDR_A_D63 SA_DQ62 SB_DQ63
AK51
SA_DQ63

Rev1p2

Rev1p2

16 DDR_B_D[0..63]

16 DDR_B_MA[0..15]
15 DDR_A_D[0..63]
16 DDR_B_DQS#[0..7]
15 DDR_A_MA[0..15]
16 DDR_B_DQS[0..7]
15 DDR_A_DQS#[0..7]

15 DDR_A_DQS[0..7]
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/03/03 Deciphered Date 2015/03/03 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BDW ULT(2/11) DDRIII
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B131P
Date: Tuesday, March 04, 2014 Sheet 5 of 52
5 4 3 2 1
 5 4 3 2 1

GCLK (RG3 close to Y1.1)

RG3 1 2 0_0402_5% PCH_RTCX1

34 CPU_RTCX1_GCLK
SVT

PCH_RTCX1

1NOGCLK@2 PCH_RTCX2
R10 10M_0402_5%
+RTCVCC
U9E HASWELL_MCP_E
Y1
1 2 1 Clear ME (TOP)

2
D 32.768KHZ 12.5PF 9H03200031 +RTCVCC C11 JME2 PCH_RTCX1 AW5 D
NOGCLK@ 1U_0603_10V6K PCH_RTCX2 RTCX1
SHORT PADS AY5

1
2 RTCX2
@ R13 1 2 1M_0402_5% SM_INTRUDER# AU6 J5 SATA_PRX_DTX_N0 29
R11 20K_0402_1% SVT PCH_INTVRMEN INTRUDER RTC SATA_RN0/PERN6_L3
1 1 AV7 H5 SATA_PRX_DTX_P0 29
C12 C13 PCH_SRTCRST# INTVRMEN SATA_RP0/PERP6_L3
1 2
PCH_RTCRST#
AV6
SRTCRST SATA_TN0/PETN6_L3
B15 SATA_PTX_DRX_N0 29 HDD(SSD)
NOGCLK@ NOGCLK@ 1 2 AU7 A15
RTCRST SATA_TP0/PETP6_L3 SATA_PTX_DRX_P0 29
15P_0402_50V8J 15P_0402_50V8J R12 20K_0402_1%
2 2
1 Clear CMOS (BOT) SATA_RN1/PERN6_L2
J8

2
H8
C10 JME1 SATA_RP1/PERP6_L2
A17
1U_0603_10V6K SATA_TN1/PETN6_L2
SHORT PADS B17

1
2 CMOS SATA_TP1/PETP6_L2
@
HDA_BIT_CLK AW8 J6
HDA_SYNC HDA_BCLK/I2S0_SCLK SATA_RN2/PERN6_L1
AV11 HDA_SYNC/I2S0_SFRM SATA_RP2/PERP6_L1 H6
+RTCVCC HDA_RST# AU8 B14
HDA_SDIN0 HDA_RST/I2S_MCLK SATA_TN2/PETN6_L1
27 HDA_SDIN0 AY10 HDA_SDI0/I2S0_RXD SATA_TP2/PETP6_L1 C15
AU12 AUDIO SATA
PCH_INTVRMEN R14 HDA_SDOUT HDA_SDI1/I2S1_RXD
1 2 330K_0402_5% AU11 F5
R15 @ HDA_SDO/I2S0_TXD SATA_RN3/PERN6_L0
1 2 330K_0402_5% AW10 HDA_DOCK_EN/I2S1_TXD SATA_RP3/PERP6_L0 E5
AV10 C17
INTVRMEN (+1.05VA) HDA_DOCK_RST/I2S1_SFRM SATA_TN3/PETN6_L0
AY8 I2S1_SCLK SATA_TP3/PETP6_L0 D17
* HIntegrated VRM enable
LIntegrated VRM disable
5 OF 19 PCH_GPIO34
SATA0GP/GPIO34 V1
U1 PCH_GPIO35 PCH_GPIO35 9
SATA1GP/GPIO35 PCH_GPIO36 +1.05VS_ASATA3PLL
SATA2GP/GPIO36 V6 PCH_GPIO36 9
AC1 PCH_GPIO37
SATA3GP/GPIO37 PCH_GPIO37 9
@ T10 PCH_JTAG_RST# AU62
PCH_JTAG_TCK PCH_TRST
AE62 PCH_TCK SATA_IREF A12
@ T11 PCH_JTAG_TDI AD61 L11
@ T12 PCH_JTAG_TDO PCH_TDI RSVD
AE61 PCH_TDO RSVD K10 within 500 mils
@ T13 PCH_JTAG_TMS AD62 JTAG C12 SATA_RCOMP R16 1 2 3.01K_0402_1%
C PCH_TMS SATA_RCOMP PCH_SATALED# C
RTC CONN place to PWR side AL11 RSVD SATALED U3 PCH_SATALED# 9,33
AC4 RSVD
@ T14 PCH_TCK_JTAGX AE63
@ T91 PCH_RSVD JTAGX
AV2
RTC Battery RSVD

W=20mils W=20mils
Rev1p2
+RTCVCC +RTCBATT

R17 1 2 0_0402_5%

1 SIV
C14
1U_0402_6.3V6K
2

+3V_PCH

B B
1 2 HDA_SDOUT
R18 @ 1K_0402_5% +3VS

HDA_SDOUT RP1 EMI@

1 8 HDA_SDOUT
27 HDA_SDOUT_AUDIO
ME debug mode,this signal has a weak internal PD 2 7 HDA_SYNC R19 1 2 10K_0402_5% PCH_GPIO34
27 HDA_SYNC_AUDIO
Low = Disabled (Default) HDA_RST#
* High = Enabled [Flash Descriptor Security Overide]
27 HDA_RST_AUDIO#
27 HDA_BITCLK_AUDIO
3
4
6
5 HDA_BIT_CLK

1 33_0804_8P4R_5%

C15 @EMI@
68P_0402_50V8J
2

1 2 PCH_JTAG_TCK R21 1 2 0_0402_5%

30 ME_EN
R20 @ 51_0402_5%
SIV

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/03/03 Deciphered Date 2015/03/03 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BDW ULT(3/11)RTC,SATA,JTAG
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B131P
Date: Tuesday, March 04, 2014 Sheet 6 of 52
5 4 3 2 1
 5 4 3 2 1

GCLK (RG9 close to Y2.1)

RG9 1 2 0_0402_5% XTAL24_IN XTAL24_IN
U9F HASWELL_MCP_E 34 CPU_XTAL24_IN_GCLK
SVT
2 1 NOGCLK@ XTAL24_OUT
1M_0402_5% R22
Y2 24MHZ_12PF_7V24000020
C43 A25 XTAL24_IN
CLKOUT_PCIE_N0 XTAL24_IN XTAL24_OUT
C42 CLKOUT_PCIE_P0 XTAL24_OUT B25 1 1 3 3
U2 +1.05VS_AXCK_LCPLL
9 PCH_GPIO18 PCIECLKRQ0/GPIO18 GND GND
RSVD K21 1 1
B41 M21 C16 NOGCLK@ C17
33 CLK_PCIE_CR# CLKOUT_PCIE_N1 RSVD 2 4
33 CLK_PCIE_CR A41 C26 XCLK_BIASREF R23 1 2 3.01K_0402_1% 15P_0402_50V8J 15P_0402_50V8J
CLKOUT_PCIE_P1 DIFFCLK_BIASREF
D
Card Reader 9,33 CRCLK_REQ# Y5 PCIECLKRQ1/GPIO19
NOGCLK@
2 2
NOGCLK@
D
C35 RP31 3 8 10K_8P4R_5%
CLOCK TESTLOW_C35
26 CLK_PCIE_LAN# C41 C34 4 7
CLKOUT_PCIE_N2 TESTLOW_C34
26 CLK_PCIE_LAN B42 AK8 1 6
CLKOUT_PCIE_P2 SIGNALS TESTLOW_AK8
LAN 9,26 LANCLK_REQ# AD1
PCIECLKRQ2/GPIO20 TESTLOW_AL8
AL8 2 5
SIV
29 CLK_PCIE_WLAN# B38 AN15 CLKOUT_LPC0 R28 2 EMI@ 1 22_0402_5% CK_LPC_KBC 30
CLKOUT_PCIE_N3 CLKOUT_LPC_0
29 CLK_PCIE_WLAN C37 AP15
CLKOUT_PCIE_P3 CLKOUT_LPC_1
WLAN(NGFF) 9,29 WLANCLK_REQ# N1 PCIECLKRQ3/GPIO21
B35 CLK_BCLK_ITP# @ T15
CLKOUT_ITPXDP_N CLK_BCLK_ITP @ T16
17 CLK_PCIE_VGA# A39 A35 1
CLKOUT_PCIE_N4 CLKOUT_ITPXDP_P
17 CLK_PCIE_VGA B39
CLKOUT_PCIE_P4
dGPU 18 GPUCLK_REQ# U5 PCIECLKRQ4/GPIO22
C18 @EMI@
68P_0402_50V8J
B37 2
CLKOUT_PCIE_N5 6 OF 19
A37 CLKOUT_PCIE_P5
9 PCH_GPIO23 PCH_GPIO23 T2
PCIECLKRQ5/GPIO23
+3VS
Rev1p2 SMBus :DIMMA,DIMMB,TP
FootPrint :DMN66D0LDW-7_SOT363-6
1

R154 +3VS
10K_0402_5%
2

2
@
GPUCLK_REQ#
SMBDATA 6 1 PCH_SMB_DATA 15,16,31
2

R1443 ME2N7002D1KW-G 2N SOT363-6

10K_0402_5% Q1A
@

5
C U9G HASWELL_MCP_E C
@
1

LPC_AD0 AU14 AN2 SMBCLK 3 4

30 LPC_AD0 LPC_AD1 LAD0 SMBALERT/GPIO11 SMBCLK PCH_GPIO11 9 PCH_SMB_CLK 15,16,31
30 LPC_AD1 AW12 LAD1 SMBCLK AP2
LPC_AD2 AY12 LPC AH1 SMBDATA Q1B ME2N7002D1KW-G 2N SOT363-6
30 LPC_AD2 LPC_AD3 LAD2 SMBDATA PCH_GPIO60
30 LPC_AD3 AW11 LAD3 SML0ALERT/GPIO60 AL2 PCH_GPIO60 9
LPC_FRAME# SMBUS SML0CLK
30 LPC_FRAME# AV12 LFRAME SML0CLK AN1
AK1 SML0DATA SMBDATA 1 2 PCH_SMB_DATA
SML0DATA PCH_GPIO73 R34 0_0402_5%
SML1ALERT/PCHHOT/GPIO73 AU4 PCH_GPIO73 9
AU3 SML1CLK SMBCLK 1 2 PCH_SMB_CLK
SML1CLK/GPIO75 SML1DATA R35 0_0402_5% SIT
AH3
PCH_SPI_CLK SML1DATA/GPIO74
AA3
PCH_SPI_CS0# SPI_CLK @ T17
Y7 SPI_CS0 CL_CLK
AF2
1

@EMI@ Y4 AD2 @ T18

C325
22P_0402_50V8J PCH_SPI_SI
AC2
AA2
SPI_CS1
SPI_CS2
SPI C-LINK CL_DATA
CL_RST AF4 @ T19 SML1 Bus :EC,Thermal Sensor
FootPrint :DMN66D0LDW-7_SOT363-6
2

PCH_SPI_SO SPI_MOSI
AA4
+3V_PCH PCH_SPI_WP# SPI_MISO +3VS
Y6
PCH_SPI_HOLD# SPI_IO2
AF1
SPI_IO3

2
@

Rev1p2 SML1CLK 6 1 EC_SMB_CK2 30,31

R36 7 OF 19
1 2 1K_0402_1% ME2N7002D1KW-G 2N SOT363-6
R37 1 2 1K_0402_1% Q2A

5
@

SML1DATA 3 4 EC_SMB_DA2 30,31

PCH_SPI_WP#_R R42 1 2 33_0402_5% PCH_SPI_WP#
B Q2B ME2N7002D1KW-G 2N SOT363-6 B
RP30
PCH_SPI_HOLD#_R 1 8 PCH_SPI_HOLD#
PCH_SPI_CLK_R 2 7 PCH_SPI_CLK SML1CLK 1 2 EC_SMB_CK2
To SPI 8MByte ROM PCH_SPI_SI_R 3 6 PCH_SPI_SI From PCH R39 0_0402_5%
PCH_SPI_SO_R 4 5 PCH_SPI_SO SML1DATA 1 2 EC_SMB_DA2
R40 0_0402_5% SIT
33_0804_8P4R_5%
EMI@
PCH_SPI_CS0#_R R38 1 2 0_0402_5% PCH_SPI_CS0#
SVT

+3VS
RP32
PCH_SMB_DATA 1 8
PCH_SMB_CLK 2 7
EC_SMB_DA2 3 6
RP12 EC_SMB_CK2 4 5
1 8 PCH_SPI_CS0#_R
30 EC_SPI_CS0# PCH_SPI_CLK_R
2 7 2.2K_0804_8P4R_5%
30 EC_SPI_CLK
From EC 3 6 PCH_SPI_SI_R To SPI 8MByte ROM SIV
30 EC_SPI_MOSI
4 5 PCH_SPI_SO_R
(For share ROM) 30 EC_SPI_MISO
1

@EMI@ 33_0804_8P4R_5%
C19 EMI@ RP4 @
22P_0402_50V8J
SDV for HSW SDV for BDW SML1CLK 1 8 +3V_PCH
2

SML1DATA 2 7
SMBCLK 3 6
U10 HSW@ SMBDATA 4 5

2.2K_0804_8P4R_5%

SPI ROM ( 8MByte )

SML0CLK R41 1 2 2.2K_0402_5%
A +3V_PCH SML0DATA R43 1 2 2.2K_0402_5% A

W25Q64FVSSIQ_SO8
@
U10 @
PCH_SPI_CS0#_R 1 8 +3V_ROM C20 1 2 0.1U_0402_16V7K
PCH_SPI_SO_R /CS VCC PCH_SPI_HOLD#_R
2 DO(IO1) /HOLD(IO3) 7
PCH_SPI_WP#_R 3 6 PCH_SPI_CLK_R
4
/WP(IO2) CLK
5 PCH_SPI_SI_R SIV
Security Classification Compal Secret Data Compal Electronics, Inc.
GND DI(IO0)
Issued Date 2014/03/03 Deciphered Date 2015/03/03 Title
W25Q64FVSSIQ_SO8
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BDW ULT(4/11)CLK,SPI,SMBUS
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B131P
Date: Tuesday, March 04, 2014 Sheet 7 of 52
5 4 3 2 1
 5 4 3 2 1

Note: SUSACK# and SUSWARN# can be tied together if

EC does not want to involve in the handshake mechanism
for the Deep Sleep state entry and exit DPWROK: Tired toghter with RSMRST# DSWODVREN - On Die DSW VR Enable
that do not support Deep Sx Enable(DEFAULT)
(*) H +RTCVCC
CAN be NC ,if not support Deep Sx Disable
( ) L
SUSWARN#_R R210 1 @ 2 0_0402_5%
U9H HASWELL_MCP_E
R44 1 2 330K_0402_5%
R45 1 @ 2 330K_0402_5%
DS3
SYSTEM POWER MANAGEMENT
DS3
D R47 SUSACK#_R DSWODVREN D
30 SUSACK# 1 DS3@ 2 0_0402_5% AK2 AW7 R212 1 DS3@ 2 0_0402_5% DPWROK_EC 30
SYS_RESET# SUSACK DSWVRMEN DPWROK R48 1NODS3@ 2 0_0402_5% EC_RSMRST#
9 SYS_RESET# AC3 SYS_RESET DPWROK
AV5
SYS_PWROK AG2 AJ5 R49 1 2 10K_0402_5%
30 SYS_PWROK SYS_PWROK WAKE
PCH_PWROK AY7
30 PCH_PWROK PCH_PWROK
R46 1 2 0_0402_5% APWROK_R AB5 PCH_PCIE_WAKE#
SIT APWROK PCH_PCIE_WAKE# 9,29
AG7 V5 PCH_GPIO32
PLTRST CLKRUN/GPIO32 PCH_GPIO32 9
C21 2 1 100P_0402_50V8J CPU_PLT_RST# AG4
ESD ESD@ SUS_STAT/GPIO61
SUSCLK/GPIO62
AE6 SUSCLK
PM_SLP_S5# SUSCLK 29
DS3 SLP_S5/GPIO63 AP5 PM_SLP_S5# 30
30 EC_RSMRST# EC_RSMRST# AW6 T21
+3VALW R209 1 DS3@2 0_0402_5% SUSWARN#_R RSMRST @ T22 T23
30 SUSWARN# AV4 SUSWARN/SUSPWRDNACK/GPIO30
PBTN_OUT# AL7 AJ6 PM_SLP_S4# @ @
30 PBTN_OUT# PWRBTN SLP_S4 PM_SLP_S4# 30
AC_PRESENT AJ8 AT4 PM_SLP_S3#
ACPRESENT/GPIO31 SLP_S3 PM_SLP_S3# 30

1
9 PCH_GPIO72 PCH_GPIO72 AN4 AL5 PM_SLP_A# @ T24
R50 T25 @ BATLOW/GPIO72 SLP_A
AF3 SLP_S0 SLP_SUS AP4 SLP_SUS# 30
200K_0402_5% 9 PCH_GPIO29 PCH_GPIO29 AM5 AJ7 @ T27
SLP_WLAN/GPIO29 SLP_LAN
DS3

30 AC_PRESENT 2 AC_PRESENT

Rev1p2

8 OF 19

SYS_PWROK EC_RSMRST#

U9I HASWELL_MCP_E +3VS

1 1
C C339 ESD@ C340 ESD@ C
SIT
100P_0402_50V8J 100P_0402_50V8J DDI1_CTRL_CK R58 1 @ 2 2.2K_0402_5%
2 2 0_0402_5%
R51 1 2 EDP_BKCTL B8 B9 DDI1_CTRL_CK
25 INVPWM EDP_BKLCTL DDPB_CTRLCLK DDI1_CTRL_DATA DDI1_CTRL_DATA
A9 C9 R52 1 @ 2 2.2K_0402_5%
25,30 ENBKL EDP_BKLEN eDP SIDEBAND DDPB_CTRLDATA DDI2_CTRL_CK
25 PCH_ENVDD C6 EDP_VDDEN DDPC_CTRLCLK D9 DDI2_CTRL_CK 28
DDPC_CTRLDATA D11 DDI2_CTRL_DATA DDI2_CTRL_DATA 28 DDPB_CTRLDATA: Port B Detected
DDPC_CTRLDATA: Port C Detected
9,45 DGPU_PWROK U6
PIRQA/GPIO77
9,19,30,41,42 DGPU_PWR_EN P4 PIRQB/GPIO78 DISPLAY DDPB_AUXN
C5 * 1: Port B or C is detected
N4 B6 0: Port B or C is not detected
17 DGPU_HOLD_RST# PIRQC/GPIO79 DDPC_AUXN (Have internal PD)
9,29 WLBT_OFF# N2 PIRQD/GPIO80 DDPB_AUXP
B5
T28 @ AD4 A6
PME GPIO DDPC_AUXP
+3V_PCH PCH_GPIO55 U7
9 PCH_GPIO55 GPIO55
9 PCH_GPIO52 PCH_GPIO52 L1
R211 1 SUSWARN#_R PCH_GPIO54 GPIO52
2 10K_0402_5% 9 PCH_GPIO54 L3
GPIO54 DDPB_HPD
C8 @ T99
9 PCH_GPIO51 R5 A8 DDI2_HDMI_HPD 9,28
PCH_GPIO53 GPIO51 DDPC_HPD
9 PCH_GPIO53 L4 D6 EDP_HPD 25
GPIO53 EDP_HPD

9 OF 19 Rev1p2

B B

SIT
0_0402_5%
R53 1 2

+3VS
V0.2
SVT

5
U11 @
CPU_PLT_RST# 2 B

P
4 PLT_RST# 17,26,29,30,33
Y
1
A

1
R54
MC74VHC1G08DFT2G_SC70-5 3 100K_0402_5%

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/03/03 Deciphered Date 2015/03/03 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BDW ULT(5/11) PM,GPIO,DDI
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B131P
Date: Tuesday, March 04, 2014 Sheet 8 of 52
5 4 3 2 1
 5 4 3 2 1

+3VS

+1.05VS
1 8 PCH_GPIO18 7
2 7 PCH_GPIO50

1
U9J HASWELL_MCP_E
3 6 SERIRQ SIV
4 5 PCH_GPIO17 R56
1K_0402_1%
RP5 10K_8P4R_5%

2
1 8 PCH_GPIO83 P1 D60 H_THERMTRIP#
D 8,28 DDI2_HDMI_HPD BMBUSY/GPIO76 THERMTRIP D
2 7 PCH_GPIO2 PCH_GPIO8 AU2 V4
PCH_GPIO12 GPIO8 RCIN/GPIO82 KB_RST# 30
3 6 PCH_GPIO51 8 SIV AM7
LAN_PHY_PWR_CTRL/GPIO12 SERIRQ
T4 SERIRQ 30
PCH_GPIO15 CPU/ PCH_OPIRCOMP
4 5 WLBT_OFF# 8,29 AD6 AW15 1 2
PCH_GPIO16 GPIO15 MISC PCH_OPI_RCOMP R57
Y1 AF20
RP6 10K_8P4R_5% PCH_GPIO17 GPIO16 RSVD 49.9_0402_1%
T3 AB21
PCH_GPIO24 GPIO17 RSVD
AD5
PCH_GPIO27 GPIO24
AN5
PCH_GPIO65 PCH_GPIO28 GPIO27
1 8 AD7
GPIO28
2 7 PCH_GPIO64 PCH_GPIO26 AN3
PCH_GPIO1 GPIO26 PCH_GPIO83
3 6 R6
PCH_GPIO3 PCH_GPIO56 GSPI0_CS/GPIO83 PCH_GPIO84
4 5 AG6
GPIO56 GSPI0_CLK/GPIO84
L6
PCH_GPIO57 AP1 N6 PCH_GPIO85 SIT
RP7 10K_8P4R_5% PCH_GPIO58 GPIO57 GSPI0_MISO/GPIO85 PCH_GPIO86
AL4 GPIO58 GSPI0_MOSI/GPIO86 L8
PCH_GPIO59 AT5 R7
PCH_GPIO44 GPIO59 GSPI1_CS/GPIO87 PCH_GPIO88 PCH_GPIO87 25
AK4 GPIO44 GSPI1_CLK/GPIO88 L5
PCH_GPIO47 GPIO PCH_GPIO89 SDV
1 8 PCH_GPIO36 6 AB6 N7
PCH_GPIO48 GPIO47 GSPI1_MISO/GPIO89 PCH_GPIO90
2 7 CRCLK_REQ# 7,33 U4 GPIO48 GSPI_MOSI/GPIO90 K2
3 6 KB_RST# PCH_GPIO49 Y3 J1 PCH_GPIO91 GPIO87 : Touch / Non-Touch
PCH_GPIO50 GPIO49 UART0_RXD/GPIO91 PCH_GPIO92
4 5 LANCLK_REQ# 7,26 P3 GPIO50 UART0_TXD/GPIO92 K3
PCH_GPIO71 Y2 J2 PCH_GPIO93
RP8 10K_8P4R_5% PCH_GPIO13 HSIOPC/GPIO71 10 OF 19 LPIO UART0_RTS/GPIO93 PCH_GPIO94
AT3 G1 1: Non-Touch
1
2
8
7
PCH_GPIO53 8
PCH_GPIO14
PCH_GPIO25
PCH_GPIO45
AH4
AM4
AG5
GPIO13
GPIO14
GPIO25
UART0_CTS/GPIO94
UART1_RXD/GPIO0
UART1_TXD/GPIO1
K4
G2
J3
PCH_GPIO0
PCH_GPIO1
PCH_GPIO2
* 0: Touch
PCH_GPIO52 8 GPIO45 UART1_RST/GPIO2
3 6 WLANCLK_REQ# 7,29 PCH_GPIO46 AG3 J4 PCH_GPIO3
PCH_GPIO33 GPIO46 UART1_CTS/GPIO3 PCH_GPIO4
4 5 I2C0_SDA/GPIO4 F2
AM3 F3 PCH_GPIO5
RP9 10K_8P4R_5% PCH_GPIO10 GPIO9 I2C0_SCL/GPIO5 PCH_GPIO6
AM2 GPIO10 I2C1_SDA/GPIO6 G4
PCH_GPIO33 P2 F1 PCH_GPIO7
DEVSLP0/GPIO33 I2C1_SCL/GPIO7 PCH_GPIO64
C4 SDIO_POWER_EN/GPIO70 SDIO_CLK/GPIO64 E3
PCH_GPIO38 L2 F4 PCH_GPIO65
EC_SCI# DEVSLP1/GPIO38 SDIO_CMD/GPIO65 PCH_GPIO66
30 EC_SCI# N5 DEVSLP2/GPIO39 SDIO_D0/GPIO66 D3
C HDA_SPKR PCH_GPIO67 C
1 2 DGPU_PWR_EN 8,19,30,41,42 27 HDA_SPKR V2 SPKR/GPIO81 SDIO_D1/GPIO67 E4
R276 10K_0402_5% C3 PCH_GPIO68
SDIO_D2/GPIO68 PCH_GPIO69
SDIO_D3/GPIO69 E2
SIT
Rev1p2

1 8 +3V_PCH
PCH_SATALED# 6,33
2 7 PCH_GPIO35 6
3 6 PCH_GPIO48 ESD@
4 5 PCH_GPIO71 H_THERMTRIP# C22 1 2 100P_0402_50V8J
1 8 PCH_GPIO60 7
RP2 10K_8P4R_5% 2 7 PCH_GPIO58
3 6 PCH_GPIO10
4 5 PCH_GPIO11 7
1 8 DGPU_PWROK 8,45 RP14 10K_8P4R_5%
2 7 PCH_GPIO87
3 6 PCH_GPIO94 1 8 PCH_GPIO13
4 5 PCH_GPIO69 2 7 USB_OC1# 10,32
3 6 PCH_GPIO8 +3VS
RP23 10K_8P4R_5% 4 5 PCH_GPIO12

RP16 10K_8P4R_5% +3VALW

1 8 PCH_GPIO55 8 PCH_GPIO86 R60 1 @ 2 1K_0402_1%
2 7 1 8 PCH_GPIO26 R61 1 2 1K_0402_1%
PCH_GPIO32 8
3 6 2 7 1 8 PCH_GPIO25
PCH_GPIO54 8 PCH_GPIO72 8
4 5 PCH_GPIO38 3 6 2 7 PCH_GPIO27
PCH_GPIO43 10
4 5 PCH_GPIO57 3 6 PCH_GPIO29 8
RP26 10K_8P4R_5% SIT 4 5 PCH_PCIE_WAKE# 8,29 GSPI0_MOSI / GPIO86 : Boot BIOS Strap
RP18 10K_8P4R_5%
RP27 10K_8P4R_5%
1 8 PCH_GPIO0 1 8 PCH_GPIO24 1: LPC BUS
B EC_SCI# PCH_GPIO46 B
2 7 2 7
3 6 PCH_GPIO68 3 6 0: SPI BUS (Have internal PD)
4 5 PCH_GPIO67 4 5 PCH_GPIO14
PCH_GPIO42 10
*
RP24 10K_8P4R_5% RP11 10K_8P4R_5%

1 8 PCH_GPIO59 +3VS
2 7 PCH_GPIO44
1 8 PCH_GPIO4 3 6 USB_OC0# 10,32
PCH_GPIO66 R205 1 2 150K_0402_1%
2 7 PCH_GPIO5 4 5 PCH_GPIO73 7
3 6 PCH_GPIO6 SDIO_D0 / GPIO66 : Top-Block Swap Override
4 5 PCH_GPIO7 RP15 10K_8P4R_5% SIT

RP25 2.2K_0804_8P4R_5% 1 8 PCH_GPIO47 1: DISABLED

2
3
7
6
PCH_GPIO28
PCH_GPIO45 * 0: ENABLED (Have internal PD)
1 8 PCH_GPIO49 4 5 PCH_GPIO56
2 7 PCH_GPIO16
3 6 SYS_RESET# 8 RP17 10K_8P4R_5%
4 5 PCH_GPIO37 6 +3V_PCH

RP13 10K_8P4R_5% Platform R69 1 @ 2 PCH_GPIO15

+3VS BDW => R200 stuff (BDW@) 1K_0402_1%
HSW => R202 stuff (HSW@)
1 8 PCH_GPIO89 GPIO15 : TLS Confidentiality
2 7 PCH_GPIO85 SIT
3 6 PCH_GPIO92 1 BDW@ 2 PCH_GPIO88
4 5 PCH_GPIO23 7 R200 10K_0402_5% 1: Intel ME TLS with confidentiality
RP28 10K_8P4R_5% SIV 0: Intel ME TLS with no confidentiality
A
R202
1 HSW@ 2
10K_0402_5% * (Have internal PD) A
1 8 PCH_GPIO84
2 7 PCH_GPIO90
3 6 PCH_GPIO93
4 5 PCH_GPIO91

RP29 10K_8P4R_5%

1 @ 2 HDA_SPKR Security Classification Compal Secret Data Compal Electronics, Inc.

R170 1K_0402_5% Issued Date 2014/03/03 2015/03/03 Title
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BDW ULT(6/11) GPIO,LPIO
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B131P
Date: Tuesday, March 04, 2014 Sheet 9 of 52
5 4 3 2 1
 5 4 3 2 1

D U9K HASWELL_MCP_E D

17 PCIE_CRX_GTX_N0 F10 AN8 USB20_N0 32

PERN5_L0 USB2N0
17 PCIE_CRX_GTX_P0 E10
PERP5_L0 USB2P0
AM8 USB20_P0 32 Left USB2/3 IO (MB)
17 PCIE_CTX_GRX_N0
C23 1 2 0.22U_0402_10V6KPCIE_PTX_DRX_N5_L0 C23 AR7 USB20_N1 32
PETN5_L0 USB2N1
17 PCIE_CTX_GRX_P0 C24 1 2 0.22U_0402_10V6KPCIE_PTX_DRX_P5_L0 C22 PETP5_L0 USB2P1
AT7 USB20_P1 32 Left USB2/3 IO (MB)
17 PCIE_CRX_GTX_N1 F8 AR8 USB20_N2 32
PERN5_L1 USB2N2
17 PCIE_CRX_GTX_P1 E8
PERP5_L1 USB2P2
AP8 USB20_P2 32 Right USB2.0 (IO/B)
C25 1 2 0.22U_0402_10V6KPCIE_PTX_DRX_N5_L1 B23 PETN5_L1 USB2N3 AR10
17 PCIE_CTX_GRX_N1
dGPU C26 1 2 0.22U_0402_10V6KPCIE_PTX_DRX_P5_L1 A23 PETP5_L1 USB2P3 AT10
17 PCIE_CTX_GRX_P1

17 PCIE_CRX_GTX_N2 H10 PERN5_L2 USB2N4 AM15 USB20_N4 25

17 PCIE_CRX_GTX_P2
G10 PERP5_L2 USB2P4 AL15 USB20_P4 25 Touch Panel
17 PCIE_CTX_GRX_N2
C27 1 2 0.22U_0402_10V6KPCIE_PTX_DRX_N5_L2 B21 PETN5_L2 USB2N5 AM13 USB20_N5 25
C28 1 2 0.22U_0402_10V6KPCIE_PTX_DRX_P5_L2 C21 AN13 USB20_P5 25 Camera
17 PCIE_CTX_GRX_P2 PETP5_L2 USB2P5
E6 PERN5_L3 USB2N6 AP11 USB20_N6 29
17 PCIE_CRX_GTX_N3
17 PCIE_CRX_GTX_P3
F6 PERP5_L3 USB2P6 AN11 USB20_P6 29 BT (NGFF)
17 PCIE_CTX_GRX_N3
C29 1 2 0.22U_0402_10V6KPCIE_PTX_DRX_N5_L3 B22 AR13
PETN5_L3 USB2N7
17 PCIE_CTX_GRX_P3
C30 1 2 0.22U_0402_10V6KPCIE_PTX_DRX_P5_L3 A21 PETP5_L3 USB2P7 AP13
11 OF 19

26 PCIE_PRX_DTX_N3 G11 PERN3

26 PCIE_PRX_DTX_P3 F11 PERP3 USB3RN1 G20 USB3_RX1_N 32
LAN USB3RP1 H20 USB3_RX1_P 32
26 PCIE_PTX_C_DRX_N3
C31 1 2 0.1U_0402_16V7K PCIE_PTX_DRX_N3 C29 PETN3 USB2/3 IO (MB)
C32 1 2 0.1U_0402_16V7K PCIE_PTX_DRX_P3 B30 PCIe USB C33
C 26 PCIE_PTX_C_DRX_P3 PETP3 USB3TN1 USB3_TX1_N 32 C
USB3TP1 B34 USB3_TX1_P 32
29 PCIE_PRX_DTX_N4 F13 PERN4
29 PCIE_PRX_DTX_P4 G13 PERP4 USB3RN2 E18 USB3_RX2_N 32
WLAN(NGFF) USB3RP2 F18 USB3_RX2_P 32
29 PCIE_PTX_C_DRX_N4 C33 1 2 0.1U_0402_16V7K PCIE_PTX_DRX_N4 B29 PETN4 USB2/3 IO (MB)
29 PCIE_PTX_C_DRX_P4 C34 1 2 0.1U_0402_16V7K PCIE_PTX_DRX_P4 A29 PETP4 USB3TN2 B33 USB3_TX2_N 32
USB3TP2 A33 USB3_TX2_P 32
G17
PERN1/USB3RN3
F17
PERP1/USB3RP3
C30
PETN1/USB3TN3 USBRBIAS R71
C31 AJ10 1 2 22.6_0402_1% CAD note:
PETP1/USB3TP3 USBRBIAS
AJ11 Route single-end 50-ohms and max 450-mils length.
USBRBIAS @ T92
F15 AN10
33 PCIE_PRX_DTX_N2 PERN2/USB3RN4 RSVD @ T93 Avoid routing next to clock pins or under stitching capacitors.
G15 AM10
33 PCIE_PRX_DTX_P2 PERP2/USB3RP4 RSVD
Card Reader Recommended minimum spacing to other signal traces is 15 mils
C35 1 2 0.1U_0402_16V7K PCIE_PTX_DRX_N2 B31
33 PCIE_PTX_C_DRX_N2 PETN2/USB3TN4
C36 1 2 0.1U_0402_16V7K PCIE_PTX_DRX_P2 A31
PETP2/USB3TP4
33 PCIE_PTX_C_DRX_P2 AL3
OC0/GPIO40 USB_OC0# 9,32
OC1/GPIO41 AT1 USB_OC1# 9,32
+1.05VS_AUSB3PLL AH2
OC2/GPIO42 PCH_GPIO42 9
E15 AV3 PCH_GPIO43 9
RSVD OC3/GPIO43
E13
R72 PCIE_RCOMP RSVD
1 2 3.01K_0402_1% A27
PCIE_RCOMP
B27
PCIE_IREF

Rev1p2

B B

USB2.0
Port 0 1 2 3 4 5 6 7

Left USB3.0 Left USB3.0 Right USB2.0 Touch Panel Camera BT (NGFF)

Flexible I/O Capable Ports

HSIO Port 1 2 3 4 5 6 7 8 9 10 11 12 13 14
1 2
USB 3.0 USB3.0_1 USB3.0_2
1 2 3 4 5-L0 5-L1 5-L2 5-L3 6-L0 6-L1 6-L2 6-L3
PCIe CardReader LAN WLAN GPU_Venus GPU_Venus GPU_Venus GPU_Venus
3 2 1 0
SATA HDD(SSD)
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/03/03 Deciphered Date 2015/03/03 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BDW ULT(7/11) PCIE,USB
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B131P
Date: Tuesday, March 04, 2014 Sheet 10 of 52
5 4 3 2 1
 5 4 3 2 1

+CPU_CORE
U9L HASWELL_MCP_E

L59 RSVD VCC C36

+1.35V J58 C40
RSVD VCC
VCC C44
AH26 VDDQ VCC C48
AJ31 VDDQ VCC C52
AJ33 VDDQ VCC C56
AJ37 VDDQ VCC E23
AN33 VDDQ VCC E25
AP43 E27
VDDQ VCC
AR48 E29
VDDQ VCC
AY35 E31
D +1.05VS VDDQ VCC D
AY40 E33
VDDQ VCC
AY44 E35
+CPU_CORE VDDQ VCC
AY50 E37
VDDQ VCC

1
E39
R73 VCC
F59 E41
T29 VCC VCC
10K_0402_5% N58 E43
@ RSVD VCC
AC58 E45
RSVD VCC
E47

2
VCCSENSE VCC
E63 E49
VCCST_PWRGD T30 @ VCC_SENSE VCC
30 VCCST_PWRGD AB23 E51
+VCCIO_OUT_R RSVD VCC
A59 E53
VCCIO_OUT VCC
+VCCIOA_OUT E20 VCCIOA_OUT VCC E55
connect to PWR AD23 RSVD VCC E57
12 OF 19
AA23 RSVD VCC F24
AE59 RSVD VCC F28
VCC F32
H_CPU_SVIDALRT# L62 F36
VR_SVID_CLK VIDALERT VCC
46 VR_SVID_CLK N63 VIDSCLK VCC F40
H_CPU_SVIDDATA L63 F44
VCCST_PWRGD VIDSOUT HSW ULT POWER VCC
B59 VCCST_PWRGD VCC F48
46 VR_ON F60 VR_EN VCC F52
R151 1 2 10K_0402_5% C59 F56
VR_READY VCC
46 VGATE VCC G23
D63 VSS VCC G25
CPU_PWR_DEBUG H59 G27
PWR_DEBUG VCC
P62 VSS VCC G29
T31 @ P60 G31
T32 @ RSVD_TP VCC
P61 G33
RF T33
T34
@
@
N59
N61
RSVD_TP
RSVD_TP
VCC
VCC G35
G37
VR_SVID_CLK T35 @ RSVD_TP VCC
T59 RSVD VCC G39
T36 @ AD60 G41
C T37 @ RSVD VCC C
1 AD59 RSVD VCC G43
T38 @ AA59 G45
C38 @ T39 @ RSVD VCC
AE60 RSVD VCC G47
68P_0402_50V8J T40 @ AC59 G49
2 T41 @ RSVD VCC
SVID ALERT +1.05VS T42 @
AG58
U59
RSVD
RSVD
VCC
VCC
G51
G53
T43 @ V59 G55
RSVD VCC
G57
+1.05VS VCC
AC22 H23
VCCST VCC
Place the PU +CPU_CORE AE22
VCCST VCC
J23
AE23 K23
resistors close to CPU VCCST VCC
1

K57
R74 VCC
AB57 L22
75_0402_5% VCC VCC
AD57 M23
VCC VCC
AG57 M57
R75 VCC VCC
C24 P57
2

43_0402_1% +1.05VS VCC VCC

C28 U57
H_CPU_SVIDALRT# VCC VCC
46 VR_SVID_ALRT# 2 1 R76: CPU_PWR_DEBUG C32
VCC VCC
W57
CRB mount Rev1p2
2

Check list ,XDP use only

R76
@
SVID DATA 150_0402_1%

+1.35V
1

+1.05VS
Place the PU CPU_PWR_DEBUG VDDQ DECOUPLING
resistors close to CPU
1

R77 R78

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M
110_0402_5% @ 10K_0402_5% @

C41

C42

C43

C49

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
B @ B
1 1 1 1 1 1 1 1 1 1
SIT
2

C50

C44

C51

C45

C46

C52
R79
1 2 H_CPU_SVIDDATA
46 VR_SVID_DAT 2 2 2 2 2 2 2 2 2 2
0_0402_5%

R77:
CRB r0.7 changed from 130 Ohms to
110 Ohms SIV CRB: SIV
+1.35V : 470UF/2V/7343 *2 (Un-mount)
10UF/6.3V/0603 * 6
2.2UF/6.3V/0402 * 4
+CPU_CORE
1

R80
100_0402_1%
2

VCCSENSE
CAD Note: PU resistor should be close to CPU
46 VCCSENSE

VSSSENSE CAD Note: PD resistor should be close to CPU

A 13,46 VSSSENSE A
1

R81
100_0402_1%
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/03/03 Deciphered Date 2015/03/03 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BDW ULT(8/11) Power
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B131P
Date: Tuesday, March 04, 2014 Sheet 11 of 52
5 4 3 2 1
 5 4 3 2 1

D D

Check Power Source

+1.05VS +1.05VS_AUSB3PLL

L11 2 C58 1 2 1U_0402_6.3V6K 18mA

C59 1 2 22U_0805_6.3V6M
2.2UH_LQM2MPN2R2NG0L_30% @ C37 1 2 47U_0805_6.3V6M SIT
U9M HASWELL_MCP_E

+1.05VS_ASATA3PLL K9
+1.05VS VCCHSIO +RTCVCC
L10 VCCHSIO +3V_PCH
M9 VCCHSIO
L21 C60 1 mPHY
2 2 1U_0402_6.3V6K +1.05VS N8 AH11 C61 1 2 1U_0402_6.3V6K
@ C62 1 VCC1_05 RTC VCCSUS3_3
2 47U_0805_6.3V6M P9 AG10 +RTCVCC
VCC1_05 VCCRTC +3V_PCH

1U_0402_6.3V6K
2.2UH_LQM2MPN2R2NG0L_30% C138 1 2 22U_0805_6.3V6M SIT B18 AE7
+1.05VS_AUSB3PLL VCCUSB3PLL DCPRTC
B11 +VCCRTCEXT C63 1 2 0.1U_0402_16V7K Share ROM 1
+1.05VS_ASATA3PLL VCCSATA3PLL
+1.05VS_APLLOPI

C79
SPI C64 1
Y20 RSVD VCCSPI Y8 2 0.1U_0402_16V7K
OPI @ +1.05VS 2
+1.05VS_APLLOPI AA21 VCCAPLL
W21 VCCAPLL
C L31 C65 1 C
2 2 1U_0402_6.3V6K VCCASW AG14
2.2UH_LQM2MPN2R2NG0L_30% @ C66 1 2 22U_0805_6.3V6M SIT AG13
@ C333 1 SIV VCCASW
2 47U_0805_6.3V6M +1.05VS
T44 @ USB3
J13 DCPSUS3
+1.05VS_AXCK_DCB VCC1_05 J11 C67 1 2 10U_0603_6.3V6M 658mA
H11 C69 1 2 1U_0402_6.3V6K
AXALIA/HDA VCC1_05 C71
+3VALW AH14 VCCHDA VCC1_05 H15 1 2 1U_0402_6.3V6K
AE8 C72
VCC1_05 1U_0402_6.3V6K +1.05VS
AF22
L4 1 C68 1 VRM/USB2/AZALIA VCC1_05 +PCH_VCCDSW
2 2 1U_0402_6.3V6K T45 @ AH13 AG19 1 2
2.2UH_LQM2MPN2R2NG0L_30% @ C70 1 DCPSUS2 CORE DCPSUSBYP
2 47U_0805_6.3V6M DCPSUSBYP
AG20
C334 1 2 22U_0805_6.3V6M SIT AE9
+3VALW 13 OF 19 VCCASW C74
VCCASW
AF9 1@ 2 22U_0603_6.3V6M
+3V_PCH AC9 AG8 C76 1 2 1U_0402_6.3V6K
VCCSUS3_3 VCCASW
AA9 AD10
+1.05VS_AXCK_LCPLL VCCSUS3_3 DCPSUS1 T46 @
AH10 AD8
VCCDSW3_3 GPIO/LCC DCPSUS1 T47 @
+3VS V8
VCC3_3
W9
L5 1 C73 1 VCC3_3
2 2 1U_0402_6.3V6K J15 +1.5VS
2.2UH_LQM2MPN2R2NG0L_30% C75 1 THERMAL SENSOR VCCTS1_5
2 22U_0805_6.3V6M VCC3_3
K14 +3VS
@ C335 1 2 47U_0805_6.3V6M SIT K16 C77 1 2 0.1U_0402_16V7K
VCC3_3

+1.05VS_AXCK_DCB J18
VCCCLK SDIO/PLSS
K19 U8 +3VS
VCCCLK VCCSDIO C78 1 1U_0402_6.3V6K
+1.05VS_AXCK_LCPLL A20 T9 2
VCCACLKPLL VCCSDIO
+1.05VS J17
VCCCLK
+1.05VS R21
VCCCLK LPT LP POWER
T21
VCCCLK SUS OSCILLATOR
K18 AB8
RSVD DCPSUS4
M20
RSVD T48 @
V21
B RSVD B
+3V_PCH AE20 AC20
VCCSUS3_3 RSVD
AE21 AG16 +1.05VS
VCCSUS3_3 USB2 VCC1_05
Close to N8 VCC1_05
AG17
C81 1 2 1U_0402_6.3V6K
+1.05VS C57 @1 2 1U_0402_6.3V6K
Rev1p2
Close to K9,M9
C80 1 2 1U_0402_6.3V6K
+1.05VS C82 1 2 1U_0402_6.3V6K

Close to AC9/AA9/AE20/AE21
+3V_PCH C84 1 2 22U_0603_6.3V6M

Close to V8
+3VS C85 1 2 22U_0603_6.3V6M

Close to J17
+1.05VS C86 1 2 1U_0402_6.3V6K

Close to R21
+1.05VS C87 1 2 1U_0402_6.3V6K
A A
Close to AH14
+3VALW C88 2 1 1U_0402_6.3V6K

V1.0

C83 1 2 0.47U_0402_16V4Z +PCH_VCCDSW

+3V_PCH
@ Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/03/03 Deciphered Date 2015/03/03 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BDW ULT(9/11) Power
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B131P
Date: Tuesday, March 04, 2014 Sheet 12 of 52
5 4 3 2 1
 5 4 3 2 1

D D

U9N HASWELL_MCP_E U9O HASWELL_MCP_E U9P HASWELL_MCP_E

VSS H17
A11 VSS VSS AJ35 AP22 VSS VSS AV59 D33 VSS VSS H57
A14 VSS VSS AJ39 AP23 VSS VSS AV8 D34 VSS VSS J10
A18 VSS VSS AJ41 AP26 VSS VSS AW16 D35 VSS VSS J22
A24 VSS VSS AJ43 AP29 VSS VSS AW24 D37 VSS VSS J59
A28 VSS VSS AJ45 AP3 VSS VSS AW33 D38 VSS VSS J63
A32 VSS VSS AJ47 AP31 VSS VSS AW35 D39 VSS VSS K1
A36 VSS VSS AJ50 AP38 VSS VSS AW37 D41 VSS VSS K12
A40 VSS VSS AJ52 AP39 VSS VSS AW4 D42 VSS VSS L13
A44 VSS VSS AJ54 AP48 VSS VSS AW40 D43 VSS VSS L15
A48 VSS VSS AJ56 AP52 VSS VSS AW42 D45 VSS VSS L17
A52 VSS VSS AJ58 AP54 VSS VSS AW44 D46 VSS VSS L18
A56 VSS VSS AJ60 AP57 VSS VSS AW47 D47 VSS VSS L20
AA1 VSS VSS AJ63 AR11 VSS VSS AW50 D49 VSS VSS L58
AA58 VSS VSS AK23 AR15 VSS VSS AW51 D5 VSS VSS L61
AB10 VSS VSS AK3 AR17 VSS VSS AW59 D50 VSS VSS L7
AB20 VSS VSS AK52 AR23 VSS VSS AW60 D51 VSS VSS M22
AB22 VSS VSS AL10 AR31 VSS VSS AY11 D53 VSS VSS N10
AB7 VSS VSS AL13 AR33 VSS VSS AY16 D54 VSS VSS N3
C C
AC61 VSS VSS AL17 AR39 VSS VSS AY18 D55 VSS VSS P59
AD21 VSS VSS AL20 AR43 VSS VSS AY22 D57 VSS VSS P63
AD3 VSS VSS AL22 AR49 VSS VSS AY24 D59 VSS VSS R10
AD63 VSS VSS AL23 AR5 VSS VSS AY26 D62 VSS VSS R22
AE10 VSS VSS AL26 AR52 VSS VSS AY30 D8 VSS VSS R8
16 OF 19
AE5 VSS VSS AL29 AT13 VSS VSS AY33 E11 VSS VSS T1
14 OF 19 15 OF 19
AE58 VSS VSS AL31 AT35 VSS VSS AY4 E17 VSS VSS T58
AF11 AL33 AT37 AY51 F20 U20
VSS VSS VSS VSS VSS VSS
AF12 AL36 AT40 AY53 F26 U22
VSS VSS VSS VSS VSS VSS
AF14 AL39 AT42 AY57 F30 U61
VSS VSS VSS VSS VSS VSS
AF15 AL40 AT43 AY59 F34 U9
VSS VSS VSS VSS VSS VSS
AF17 AL45 AT46 AY6 F38 V10
VSS VSS VSS VSS VSS VSS
AF18 AL46 AT49 B20 F42 V3
VSS VSS VSS VSS VSS VSS
AG1 AL51 AT61 B24 F46 V7
VSS VSS VSS VSS VSS VSS
AG11 AL52 AT62 B26 F50 W20
VSS VSS VSS VSS VSS VSS
AG21 AL54 AT63 B28 F54 W22
VSS VSS VSS VSS VSS VSS
AG23 AL57 AU1 B32 F58 Y10
VSS VSS VSS VSS VSS VSS
AG60 AL60 AU16 B36 F61 Y59
VSS VSS VSS VSS VSS VSS
AG61 AL61 AU18 B4 G18 Y63
VSS VSS VSS VSS VSS VSS
AG62 AM1 AU20 B40 G22
VSS VSS VSS VSS VSS
AG63 AM17 AU22 B44 G3
VSS VSS VSS VSS VSS
AH17 AM23 AU24 B48 G5 V58
VSS VSS VSS VSS VSS VSS
AH19 AM31 AU26 B52 G6 AH46
VSS VSS VSS VSS VSS VSS
AH20 AM52 AU28 B56 G8 V23
VSS VSS VSS VSS VSS VSS
AH22 AN17 AU30 B60 H13 E62 VSSSENSE 11,46
VSS VSS VSS VSS VSS VSS_SENSE
AH24 AN23 AU33 C11 AH16
VSS VSS VSS VSS Rev1p2 VSS
AH28 AN31 AU51 C14
VSS VSS VSS VSS
AH30 AN32 AU53 C18
VSS VSS VSS VSS
AH32 AN35 AU55 C20
VSS VSS VSS VSS
AH34 AN36 AU57 C25
VSS VSS VSS VSS
AH36 AN39 AU59 C27
VSS VSS VSS VSS
AH38 AN40 AV14 C38
B VSS VSS VSS VSS B
AH40 AN42 AV16 C39
VSS VSS VSS VSS
AH42 AN43 AV20 C57
VSS VSS VSS VSS
AH44 AN45 AV24 D12
VSS VSS VSS VSS
AH49 AN46 AV28 D14
VSS VSS VSS VSS
AH51 AN48 AV33 D18
VSS VSS VSS VSS
AH53 AN49 AV34 D2
VSS VSS VSS VSS
AH55 AN51 AV36 D21
VSS VSS VSS VSS
AH57 AN52 AV39 D23
VSS VSS VSS VSS
AJ13 AN60 AV41 D25
VSS VSS VSS VSS
AJ14 AN63 AV43 D26
VSS VSS VSS VSS
AJ23 AN7 AV46 D27
VSS VSS VSS VSS
AJ25 AP10 AV49 D29
VSS VSS VSS VSS
AJ27 AP17 AV51 D30
VSS VSS VSS VSS
AJ29 AP20 AV55 D31
VSS VSS VSS Rev1p2 VSS

Rev1p2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/03/03 Deciphered Date 2015/03/03 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BDW ULT(10/11) GND
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B131P
Date: Tuesday, March 04, 2014 Sheet 13 of 52
5 4 3 2 1
 1

U9Q HASWELL_MCP_E U9R HASWELL_MCP_E

DC_TEST_AY2_AW2 AY2 A3 DC_TEST_A3_B3 N23

DC_TEST_AY3_AW3 DAISY_CHAIN_NCTF_AY2 DAISY_CHAIN_NCTF_A3 @ T50 RSVD
AY3 DAISY_CHAIN_NCTF_AY3 DAISY_CHAIN_NCTF_A4 A4 RSVD R23
T49 @ AY60 T23
DC_TEST_AY61_AW61 AY61 DAISY_CHAIN_NCTF_AY60 V1.0 AT2 RSVD
A60 RSVD U10
DC_TEST_AY62_AW62 AY62 DAISY_CHAIN_NCTF_AY61 DAISY_CHAIN_NCTF_A60 DC_TEST_A61_B61 AU44 RSVD
A61 RSVD
T51 @ DAISY_CHAIN_NCTF_AY62 DAISY_CHAIN_NCTF_A61 AV44
B2 A62 RSVD
DC_TEST_A3_B3 DAISY_CHAIN_NCTF_B2 DAISY_CHAIN_NCTF_A62 @ T52 D15
B3 AV1 RSVD AL1
DC_TEST_A61_B61 DAISY_CHAIN_NCTF_B3 DAISY_CHAIN_NCTF_AV1 @ T53 RSVD
B61 DAISY_CHAIN_NCTF_B61 DAISY_CHAIN_NCTF_AW1 AW1 RSVD AM11
DC_TEST_B62_B63 B62 AW2 DC_TEST_AY2_AW2 AP7
DAISY_CHAIN_NCTF_B62 DAISY_CHAIN_NCTF_AW2 DC_TEST_AY3_AW3 F22 RSVD
B63 AW3 RSVD AU10
DC_TEST_C1_C2 DAISY_CHAIN_NCTF_B63 DAISY_CHAIN_NCTF_AW3 DC_TEST_AY61_AW61 H22 RSVD
C1 AW61 RSVD AU15
DAISY_CHAIN_NCTF_C1 DAISY_CHAIN_NCTF_AW61 DC_TEST_AY62_AW62 J21 RSVD
C2 AW62 RSVD AW14
DAISY_CHAIN_NCTF_C2 DAISY_CHAIN_NCTF_AW62 @ T54 RSVD
DAISY_CHAIN_NCTF_AW63 AW63 RSVD AY14
Rev1p2
17 OF 19 18 OF 19
Rev1p2

U9S HASWELL_MCP_E

T55 @ CFG0 AC60 AV63

T56 @ CFG1 CFG0 RSVD_TP
T57 @ CFG2
AC62
AC63
CFG1
CFG2
RSVD_TP
AU63
CFG Straps for Processor
T58 @ CFG3 AA63
T59 @ CFG4 CFG3
AA60 C63
T60 @ CFG5 CFG4 RSVD_TP
Y62 C62
T61 @ CFG6 CFG5 RSVD_TP
Y61 B43
T62 @ CFG7 CFG6 RSVD CFG3
Y60
T63 @ CFG8 CFG7
V62 A51
CFG8 RSVD_TP

1
T64 @ CFG9 V61 B51
T65 @ CFG10 CFG9 RSVD_TP R82
A T66 @ CFG11
V60
U60
CFG10
CFG11 RESERVED RSVD_TP
L60 1K_0402_1% A
T67 @ CFG12 T63 @
T68 @ CFG13 CFG12
T62 N60

2
T69 @ CFG14 CFG13 RSVD
T61
T70 @ CFG15 CFG14
T60 W23
CFG15 RSVD
Y22
T71 @ CFG16 RSVD OPI_COMP
AA62 AY15
T72 @ CFG18 CFG16 PROC_OPI_RCOMP
U63
T73 @ CFG17 CFG18
AA61 AV62
T74 @ CFG19 CFG17 19 OF 19 RSVD
U62
CFG19 RSVD
D58 Physical Debug Enable (DFX Privacy)
CFG_RCOMP V63 P22
CFG_RCOMP VSS
VSS
N21 1: DISABLED
A5
RSVD CFG3
RSVD
P20 0: ENABLED; SET DFX ENABLED BIT
E1 R20 IN DEBUG INTERFACE MSR
RSVD RSVD
D1
RSVD
J20
RSVD
H18
TD_IREF RSVD CFG4
B12
TD_IREF

1
Rev1p2
R83
1K_0402_1%

2
2 1 CFG_RCOMP
R84 49.9_0402_1%
2 1 OPI_COMP
R85 49.9_0402_1%
2 1 TD_IREF Display Port Presence Strap
R86 8.2K_0402_5%

1 : Disabled; No Physical Display Port

CFG4 attached to Embedded Display Port

0 : Enabled; An external Display Port device is

connected to the Embedded Display Port

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/03/03 Deciphered Date 2015/03/03 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BDW ULT(11/11) RSVD
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-B131P
Date: Tuesday, March 04, 2014 Sheet 14 of 52
 A B C D E

+1.35V
+1.35V +1.35V
JDIMM1

1
+V_DDR_REFA 1 2 All VR\EF traces should
VREF_DQ VSS DDR_A_D9
3 4
R87 DDR_A_D13 VSS DQ4 DDR_A_D12 have 10 mil trace width
5 6
1.8K_0402_1% DDR_A_D8 DQ0 DQ5
7 8
R88 DQ1 VSS DDR_A_DQS#1
9 10

2
VSS DQS0# DDR_A_DQS1
5 SA_DIMM_A_VREFDQ 1 2 11 12
DM0 DQS0
13 14

1
VSS VSS

0.022U_0402_16V7K
C89

C90
2.2U_0402_6.3V6M

0.1U_0402_16V7K
C91
0_0402_5% 1 1 DDR_A_D14 15 16 DDR_A_D15
@ DDR_A_D10 DQ2 DQ6 DDR_A_D11
17 18

1
@ DQ3 DQ7
19 20

1 2
DDR_A_D29 VSS VSS DDR_A_D25
21 22
R89 2 2 DDR_A_D28 DQ8 DQ12 DDR_A_D24
23 24
R90 1.8K_0402_1% DQ9 DQ13
1 25 26 1
@ DDR_A_DQS#3 VSS VSS
24.9_0402_1% 27 28

2
DDR_A_DQS3 DQS1# DM1 DIMM_DRAMRST#
29 30 DIMM_DRAMRST# 4,16
DQS1 RESET#
31 32
2
SIT DDR_A_D30 VSS VSS DDR_A_D27 C92 0.1U_0402_16V7K
33 34
DDR_A_D31 DQ10 DQ14 DDR_A_D26
35 36 1 2
DQ11 DQ15
37 38
DDR_A_D44 VSS VSS DDR_A_D45 @
CRB1.0 0.1uF *1 /2.2uF *1 39 40
DDR_A_D41 DQ16 DQ20 DDR_A_D40
41 42
2.2uF (reserved\) DQ17 DQ21
43 44
DDR_A_DQS#5 VSS VSS
45 46 DDR_A_D[0..63] 5
DDR_A_DQS5 DQS2# DM2
47 48
+1.35V DQS2 VSS DDR_A_D42
49 50 DDR_A_MA[0..15] 5
DDR_A_D43 VSS DQ22 DDR_A_D46
51 52
DDR_A_D47 DQ18 DQ23
53 54 DDR_A_DQS#[0..7] 5
DQ19 VSS DDR_A_D52
55 56
VSS DQ28 +1.35V
1U_0402_6.3V6K
C93

1U_0402_6.3V6K
C94

1U_0402_6.3V6K
C96

1U_0402_6.3V6K
C95

DDR_A_D51 57 58 DDR_A_D53
DQ24 DQ29 DDR_A_DQS[0..7] 5
1 1 1 1 DDR_A_D50 59 60 SIV
@ @ @ DQ25 VSS DDR_A_DQS#6
61 62
VSS DQS3# +5VALW +5VS

0.1U_0402_16V7K
63 64 DDR_A_DQS6
DM3 DQS3
65 66 1
2 2 2 2 DDR_A_D49 VSS VSS DDR_A_D54
67 68
DQ26 DQ30

C97

R91

R92
DDR_A_D48 69 70 DDR_A_D55 @
SIV DQ27 DQ31
71 72
VSS VSS 2

1
V0.2
+1.35V

220K_0402_5%

220K_0402_5%
5 DDRA_CKE0_DIMM DDRA_CKE0_DIMM 73 74 DDRA_CKE1_DIMM DDRA_CKE1_DIMM 5 U13 @
+1.35V CKE0 CKE1
75 76 1 5
VDD VDD DDR_A_MA15 NC VCC Q3
77 78

1
DDR_A_BS2 NC A15 DDR_A_MA14 D
5 DDR_A_BS2 79 80 4 DDR_PG_CTRL 2
BA2 A14 A LBSS138LT1G_SOT-23-3
81 82 4 2
VDD VDD Y
1U_0402_6.3V6K
C98

1U_0402_6.3V6K
C99

1U_0402_6.3V6K
C100

1U_0402_6.3V6K
C101

DDR_A_MA12 83 84 DDR_A_MA11 3 G 1 2 SA_ODT0

DDR_A_MA9 A12/BC# A11 DDR_A_MA7 GND R93 66.5_0402_1%
1 1 1 1 85 86 S

3
2 @ @ @ A9 A7 M_A_B_DIMM_ODT SA_ODT1 2
87 88 1 2
DDR_A_MA8 VDD VDD DDR_A_MA6 R94 66.5_0402_1%
89 90 74AUP1G07GW_TSSOP5
DDR_A_MA5 A8 A6 DDR_A_MA4 SA_ODT2
91 92 1 2
2 2 2 2 A5 A4 R95 66.5_0402_1%
93 94 DDR_VTT_PG_CTRL 40
DDR_A_MA3 VDD VDD DDR_A_MA2 SA_ODT3
SIV 95 96 1 2
DDR_A_MA1 A3 A2 DDR_A_MA0 R96 66.5_0402_1%
97 98
A1 A0
99 100
SA_CLK_DDR0 VDD VDD SA_CLK_DDR1
5 SA_CLK_DDR0 101 102 SA_CLK_DDR1 5
SA_CLK_DDR#0 CK0 CK1 SA_CLK_DDR#1 SA_ODT2
5 SA_CLK_DDR#0 103 104 SA_CLK_DDR#1 5 16 SA_ODT2
CK0# CK1# SA_ODT3
105 106 16 SA_ODT3
+1.35V DDR_A_MA10 VDD VDD DDR_A_BS1 +1.35V
107 108 DDR_A_BS1 5
DDR_A_BS0 A10/AP BA1 DDR_A_RAS#
5 DDR_A_BS0 109 110 DDR_A_RAS# 5
BA0 RAS#
111 112

1
DDR_A_WE# VDD VDD DDRA_CS0_DIMM#
5 DDR_A_WE# 113 114 DDRA_CS0_DIMM# 5
WE# S0#
10U_0603_6.3V6M
C102

10U_0603_6.3V6M
C103

10U_0603_6.3V6M
C104

10U_0603_6.3V6M
C105

5 DDR_A_CAS# DDR_A_CAS# 115 116 SA_ODT0

CAS# ODT0 R97
1 1 1 1 117 118
DDR_A_MA13 VDD VDD SA_ODT1 +VREF_CA 1.8K_0402_1%
119 120
DDRA_CS1_DIMM# A13 ODT1
5 DDRA_CS1_DIMM# 121 122

2
S1# NC R98
123 124
2 2 2 2 VDD VDD
125 126 1 2 SM_DIMM_VREFCA 5
TEST VREF_CA
127 128
DDR_A_D0 VSS VSS DDR_A_D5 0_0402_5%
129 130
DQ32 DQ36

1
2.2U_0402_6.3V6M

0.1U_0402_16V7K
C108

0.022U_0402_16V7K
C107
DDR_A_D1 131 132 DDR_A_D4
DQ33 DQ37

C106
133 134 1 1 @
DDR_A_DQS#0 VSS VSS @ R99
135 136

1 2
DDR_A_DQS0 DQS4# DM4 1.8K_0402_1%
137 138
DQS4 VSS DDR_A_D3
139 140

2
+1.35V DDR_A_D2 VSS DQ38 DDR_A_D7 2 2 @ R100
141 142
DDR_A_D6 DQ34 DQ39
143 144 24.9_0402_1%
DQ35 VSS DDR_A_D18
145 146
DDR_A_D21 VSS DQ44 DDR_A_D19 SIT
147 148

2
DQ40 DQ45
10U_0603_6.3V6M
C109

10U_0603_6.3V6M
C110

10U_0603_6.3V6M
C111

C112
100U_B2_6.3VM_R45M

1 DDR_A_D20 149 150

DQ41 VSS DDR_A_DQS#2
1 1 1 151 152
3 + VSS DQS5# DDR_A_DQS2 3
153 154
DM5 DQS5
155 156 CRB1.0 0.1uF *1 /2.2uF *1
@ @ DDR_A_D17 VSS VSS DDR_A_D22
157 158
2 2 2 2 DDR_A_D16 DQ42 DQ46 DDR_A_D23 2.2uF (reserved\)
159 160
DQ43 DQ47
161 162
DDR_A_D36 VSS VSS DDR_A_D37
163 164
DDR_A_D33 DQ48 DQ52 DDR_A_D32
165 166
DQ49 DQ53
167 168
DDR_A_DQS#4 VSS VSS
169 170
DDR_A_DQS4 DQS6# DM6
171 172
DQS6 VSS DDR_A_D35
173 174
DDR_A_D34 VSS DQ54 DDR_A_D39
Layout Note: 175
DQ50 DQ55
176 Address : 00
DDR_A_D38 177 178
Place near JDIMMA DQ51 VSS DDR_A_D63
179 180
VSS DQ60 R101 1
Everage by each side DDR_A_D62 181 182 DDR_A_D59 2 0_0402_5% DDR_A_SA0
DDR_A_D58 DQ56 DQ61
183 184
DQ57 VSS DDR_A_DQS#7
185 186
VSS DQS7# R102 1
187 188 DDR_A_DQS7 2 0_0402_5% DDR_A_SA1
DM7 DQS7
CRB1.0 10uF *8 /1uF *8 189 190 SIV
DDR_A_D60 VSS VSS DDR_A_D56
191 192
DDR_A_D61 DQ58 DQ62 DDR_A_D57
193 194
DQ59 DQ63
195 196
DDR_A_SA0 VSS VSS
197 198
SA0 EVENT# PCH_SMB_DATA
+3VS 199 200 PCH_SMB_DATA 7,16,31
+0.675VS DDR_A_SA1 VDDSPD SDA PCH_SMB_CLK
201 202 PCH_SMB_CLK 7,16,31
SA1 SCL
+0.675VS 203 204 +0.675VS
VTT VTT
205 206
GND1 GND2
10U_0603_6.3V6M
C113

1U_0402_6.3V6K
C115

1U_0402_6.3V6K
C116

1U_0402_6.3V6K
C114

1U_0402_6.3V6K
C117

C118
0.1U_0402_16V7K

2.2U_0402_6.3V6M
C119

1 1 207 208
BOSS1 BOSS2
1 1 1 1 1
LCN_DAN06-K4406-0103
@ @ @ @
2 2
4
2 2 2 2 2 4
CHANN\EL A /TYP\E :Reverse / H:4mm
SIV
SIV PN:SP07000LT00
CRB1.0 0.1uF *1 /2.2uF *1
Layout Note:
Place near JDIMM1.203,204 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/03/03 Deciphered Date 2015/03/03 Title

CRB1.0 10uF *1 /1uF *4 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDR3L_DIMMA
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B131P
Date: Tuesday, March 04, 2014 Sheet 15 of 52
A B C D E
 A B C D E

+1.35V
+1.35V +1.35V
JDIMM2

1
+V_DDR_REFB 1 2 All VR\EF traces should
VREF_DQ VSS DDR_B_D12
3 4
R103 DDR_B_D8 VSS DQ4 DDR_B_D9 have 10 mil trace width
5 6
1.8K_0402_1% DDR_B_D14 DQ0 DQ5
7 8
R104 DQ1 VSS DDR_B_DQS#1
9 10

2
VSS DQS0# DDR_B_DQS1
5 SA_DIMM_B_VREFDQ 1 2 11 12
DM0 DQS0
13 14

1
VSS VSS

0.022U_0402_16V7K
C120

C121
2.2U_0402_6.3V6M

0.1U_0402_16V7K
C122
0_0402_5% 1 1 DDR_B_D10 15 16 DDR_B_D13
@ DDR_B_D11 DQ2 DQ6 DDR_B_D15
17 18

1
@ DQ3 DQ7
19 20

1 2
DDR_B_D28 VSS VSS DDR_B_D25
21 22
R105 2 2 DDR_B_D29 DQ8 DQ12 DDR_B_D24
23 24
R106 1.8K_0402_1% DQ9 DQ13
1 25 26 1
@ DDR_B_DQS#3 VSS VSS
24.9_0402_1% 27 28

2
DDR_B_DQS3 DQS1# DM1 DIMM_DRAMRST#
29 30 DIMM_DRAMRST# 4,15
DQS1 RESET#
31 32
2
SIT DDR_B_D26 VSS VSS DDR_B_D30 C123 0.1U_0402_16V7K
33 34
DDR_B_D27 DQ10 DQ14 DDR_B_D31
35 36 1 2
DQ11 DQ15
37 38
DDR_B_D40 VSS VSS DDR_B_D45 @
CRB1.0 0.1uF *1 /2.2uF *1 39 40
DDR_B_D41 DQ16 DQ20 DDR_B_D44
41 42
2.2uF (reserved\) DQ17 DQ21
43 44
DDR_B_DQS#5 VSS VSS
45 46 DDR_B_D[0..63] 5
DDR_B_DQS5 DQS2# DM2
47 48
+1.35V DQS2 VSS DDR_B_D47
49 50 DDR_B_MA[0..15] 5
DDR_B_D46 VSS DQ22 DDR_B_D43
51 52
DDR_B_D42 DQ18 DQ23
53 54 DDR_B_DQS#[0..7] 5
DQ19 VSS DDR_B_D61
55 56
VSS DQ28
1U_0402_6.3V6K
C124

1U_0402_6.3V6K
C127

1U_0402_6.3V6K
C126

1U_0402_6.3V6K
C125

DDR_B_D56 57 58 DDR_B_D60
DQ24 DQ29 DDR_B_DQS[0..7] 5
1 1 1 1 DDR_B_D57 59 60
DQ25 VSS DDR_B_DQS#7
61 62
@ @ @ VSS DQS3# DDR_B_DQS7
63 64
DM3 DQS3
65 66
2 2 2 2 DDR_B_D59 VSS VSS DDR_B_D63
67 68
DDR_B_D58 DQ26 DQ30 DDR_B_D62
SIV 69 70
DQ27 DQ31
71 72
VSS VSS

5 DDRB_CKE2_DIMM DDRB_CKE2_DIMM 73 74 DDRB_CKE3_DIMM DDRB_CKE3_DIMM 5

+1.35V CKE0 CKE1
75 76
VDD VDD DDR_B_MA15
77 78
DDR_B_BS2 NC A15 DDR_B_MA14
5 DDR_B_BS2 79 80
BA2 A14
81 82
VDD VDD
1U_0402_6.3V6K
C128

1U_0402_6.3V6K
C129

1U_0402_6.3V6K
C131

1U_0402_6.3V6K
C130

DDR_B_MA12 83 84 DDR_B_MA11
DDR_B_MA9 A12/BC# A11 DDR_B_MA7
1 1 1 1 85 86
2 A9 A7 2
87 88
@ @ @ DDR_B_MA8 VDD VDD DDR_B_MA6
89 90
DDR_B_MA5 A8 A6 DDR_B_MA4
91 92
2 2 2 2 A5 A4
93 94
DDR_B_MA3 VDD VDD DDR_B_MA2
SIV 95 96
DDR_B_MA1 A3 A2 DDR_B_MA0
97 98
A1 A0
99 100
SA_CLK_DDR2 VDD VDD SA_CLK_DDR3
5 SA_CLK_DDR2 101 102 SA_CLK_DDR3 5
SA_CLK_DDR#2 CK0 CK1 SA_CLK_DDR#3
5 SA_CLK_DDR#2 103 104 SA_CLK_DDR#3 5
CK0# CK1#
105 106
+1.35V DDR_B_MA10 VDD VDD DDR_B_BS1
107 108 DDR_B_BS1 5
DDR_B_BS0 A10/AP BA1 DDR_B_RAS#
5 DDR_B_BS0 109 110 DDR_B_RAS# 5
BA0 RAS#
111 112
DDR_B_WE# VDD VDD DDRB_CS2_DIMM#
5 DDR_B_WE# 113 114 DDRB_CS2_DIMM# 5
WE# S0#
10U_0603_6.3V6M
C132

10U_0603_6.3V6M
C133

10U_0603_6.3V6M
C134

10U_0603_6.3V6M
C135

5 DDR_B_CAS# DDR_B_CAS# 115 116 SA_ODT2 SA_ODT2 15

CAS# ODT0
1 1 1 1 117 118
DDR_B_MA13 VDD VDD SA_ODT3 +VREF_CA
119 120 SA_ODT3 15
DDRB_CS3_DIMM# A13 ODT1
5 DDRB_CS3_DIMM# 121 122
S1# NC
123 124
2 2 2 2 VDD VDD
125 126
TEST VREF_CA
127 128
DDR_B_D4 VSS VSS DDR_B_D5
129 130
DQ32 DQ36

2.2U_0402_6.3V6M

0.1U_0402_16V7K
C137
DDR_B_D1 131 132 DDR_B_D0
DQ33 DQ37

C136
133 134 1 1
DDR_B_DQS#0 VSS VSS @
135 136
DDR_B_DQS0 DQS4# DM4
137 138
DQS4 VSS DDR_B_D2
139 140
+1.35V DDR_B_D3 VSS DQ38 DDR_B_D6 2 2
141 142
DDR_B_D7 DQ34 DQ39
143 144
DQ35 VSS DDR_B_D16
145 146
DDR_B_D21 VSS DQ44 DDR_B_D17
147 148
DQ40 DQ45
10U_0603_6.3V6M
C139

10U_0603_6.3V6M
C140

10U_0603_6.3V6M
C141

C142
100U_B2_6.3VM_R45M

1 DDR_B_D20 149 150

DQ41 VSS DDR_B_DQS#2
1 1 1 151 152
3 + VSS DQS5# DDR_B_DQS2 3
153 154
DM5 DQS5
155 156 CRB1.0 0.1uF *1 /2.2uF *1
@ @ DDR_B_D22 VSS VSS DDR_B_D19
157 158
2 2 2 2 DDR_B_D23 DQ42 DQ46 DDR_B_D18 2.2uF (reserved\)
159 160
DQ43 DQ47
161 162
DDR_B_D36 VSS VSS DDR_B_D37
163 164
DDR_B_D33 DQ48 DQ52 DDR_B_D32
165 166
DQ49 DQ53
167 168
DDR_B_DQS#4 VSS VSS
169 170
DDR_B_DQS4 DQS6# DM6
171 172
DQS6 VSS DDR_B_D34
173
VSS DQ54
174 Address : 01
Layout Note: DDR_B_D35 175 176 DDR_B_D38
DDR_B_D39 DQ50 DQ55
177 178
Place near JDIMMB DQ51 VSS DDR_B_D51 R111 1
179 180 2 0_0402_5% DDR_B_SA0
DDR_B_D52 VSS DQ60 DDR_B_D55
Everage by each side 181 182
DDR_B_D49 DQ56 DQ61
183 184
DQ57 VSS R112 1
185 186 DDR_B_DQS#6 +3VS 2 0_0402_5% DDR_B_SA1
VSS DQS7# DDR_B_DQS6
187 188 SIV
DM7 DQS7
CRB1.0 10uF *8 /1uF *8 189 190
DDR_B_D48 VSS VSS DDR_B_D54
191 192
DDR_B_D53 DQ58 DQ62 DDR_B_D50
193 194
DQ59 DQ63
195 196
DDR_B_SA0 VSS VSS
197 198
SA0 EVENT# PCH_SMB_DATA
+3VS 199 200 PCH_SMB_DATA 7,15,31
+0.675VS DDR_B_SA1 VDDSPD SDA PCH_SMB_CLK
201 202 PCH_SMB_CLK 7,15,31
SA1 SCL
+0.675VS 203 204 +0.675VS
VTT VTT
205 206
GND1 GND2
10U_0603_6.3V6M
C143

1U_0402_6.3V6K
C144

1U_0402_6.3V6K
C147

1U_0402_6.3V6K
C146

1U_0402_6.3V6K
C145

C148
0.1U_0402_16V7K

2.2U_0402_6.3V6M
C149

1 1 207 208
BOSS1 BOSS2
1 1 1 1 1
LCN_DAN06-K4406-0103
@ @ @ @
2 2
4
2 2 2 2 2 4
CHANN\EL B /TYP\E :Reverse / H:4mm
SIV PN:SP07000LT00
CRB1.0 0.1uF *1 /2.2uF *1
Layout Note:
Place near JDIMMB.203,204 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/03/03 Deciphered Date 2015/03/03 Title

CRB1.0 10uF *1 /1uF *4 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDR3L_DIMMB
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B131P
Date: Tuesday, March 04, 2014 Sheet 16 of 52
A B C D E
 5 4 3 2 1

GFX PCIE LANE REVERSAL

D
UV1A D

PCIE_CTX_GRX_P0 AA38 Y33 PCIE_CRX_C_GTX_P0 0.22U_0402_10V6K 2 1 CV1 DIS@ PCIE_CRX_GTX_P0

LVDS Interface
10 PCIE_CTX_GRX_P0 PCIE_RX0P PCIE_TX0P PCIE_CRX_GTX_P0 10
10 PCIE_CTX_GRX_N0 PCIE_CTX_GRX_N0 Y37 Y32 PCIE_CRX_C_GTX_N0 0.22U_0402_10V6K 2 1 CV2 DIS@ PCIE_CRX_GTX_N0 PCIE_CRX_GTX_N0 10
PCIE_RX0N PCIE_TX0N

10 PCIE_CTX_GRX_P1 PCIE_CTX_GRX_P1 Y35 W33 PCIE_CRX_C_GTX_P1 0.22U_0402_10V6K 2 1 CV3 DIS@ PCIE_CRX_GTX_P1 PCIE_CRX_GTX_P1 10
PCIE_CTX_GRX_N1 PCIE_RX1P PCIE_TX1P
10 PCIE_CTX_GRX_N1 W36 PCIE_RX1N PCIE_TX1N W32 PCIE_CRX_C_GTX_N1 0.22U_0402_10V6K 2 1 CV4 DIS@ PCIE_CRX_GTX_N1 PCIE_CRX_GTX_N1 10

10 PCIE_CTX_GRX_P2 PCIE_CTX_GRX_P2 W38 U33 PCIE_CRX_C_GTX_P2 0.22U_0402_10V6K 2 1 CV8 DIS@ PCIE_CRX_GTX_P2 PCIE_CRX_GTX_P2 10 UV1G
PCIE_CTX_GRX_N2 PCIE_RX2P PCIE_TX2P
10 PCIE_CTX_GRX_N2 V37 PCIE_RX2N PCIE_TX2N U32 PCIE_CRX_C_GTX_N2 0.22U_0402_10V6K 2 1 CV5 DIS@ PCIE_CRX_GTX_N2 PCIE_CRX_GTX_N2 10

10 PCIE_CTX_GRX_P3 PCIE_CTX_GRX_P3 V35 U30 PCIE_CRX_C_GTX_P3 0.22U_0402_10V6K 2 1 CV6 DIS@ PCIE_CRX_GTX_P3 PCIE_CRX_GTX_P3 10
LVDS CONTROL AK27
PCIE_CTX_GRX_N3 PCIE_RX3P PCIE_TX3P VARY_BL
10 PCIE_CTX_GRX_N3 U36 PCIE_RX3N PCIE_TX3N U29 PCIE_CRX_C_GTX_N3 0.22U_0402_10V6K 2 1 CV7 DIS@ PCIE_CRX_GTX_N3 PCIE_CRX_GTX_N3 10 DIGON AJ27

U38 PCIE_RX4P PCIE_TX4P T33

T37 PCIE_RX4N PCIE_TX4N T32

PCI EXPRESS INTERFACE

TXCLK_UP_DPF3P AK35
TXCLK_UN_DPF3N AL36
T35 PCIE_RX5P PCIE_TX5P T30
R36 PCIE_RX5N PCIE_TX5N T29 TXOUT_U0P_DPF2P AJ38
TXOUT_U0N_DPF2N AK37

R38 PCIE_RX6P PCIE_TX6P P33 TXOUT_U1P_DPF1P AH35

C C
P37 PCIE_RX6N PCIE_TX6N P32 TXOUT_U1N_DPF1N AJ36

TXOUT_U2P_DPF0P AG38
P35 PCIE_RX7P PCIE_TX7P P30 TXOUT_U2N_DPF0N AH37
N36 PCIE_RX7N PCIE_TX7N P29
TXOUT_U3P AF35
TXOUT_U3N AG36
N38 PCIE_RX8P PCIE_TX8P N33
M37 PCIE_RX8N PCIE_TX8N N32
LVTMDP

M35 PCIE_RX9P PCIE_TX9P N30 TXCLK_LP_DPE3P AP34

L36 PCIE_RX9N PCIE_TX9N N29 TXCLK_LN_DPE3N AR34

TXOUT_L0P_DPE2P AW37
L38 PCIE_RX10P PCIE_TX10P L33 TXOUT_L0N_DPE2N AU35
K37 PCIE_RX10N PCIE_TX10N L32
TXOUT_L1P_DPE1P AR37
TXOUT_L1N_DPE1N AU39
K35 PCIE_RX11P PCIE_TX11P L30
J36 PCIE_RX11N PCIE_TX11N L29 TXOUT_L2P_DPE0P AP35
TXOUT_L2N_DPE0N AR35

J38 PCIE_RX12P PCIE_TX12P K33 TXOUT_L3P AN36

H37 PCIE_RX12N PCIE_TX12N K32 TXOUT_L3N AP37

H35 PCIE_RX13P PCIE_TX13P J33

G36 PCIE_RX13N PCIE_TX13N J32
216-0833000-A11-THAMES-XT-M2_FCBGA962~D
DIS@
B G38 K30 B
PCIE_RX14P PCIE_TX14P
F37 PCIE_RX14N PCIE_TX14N K29

F35 PCIE_RX15P PCIE_TX15P H33

E37 PCIE_RX15N PCIE_TX15N H32

CLOCK
CLK_PCIE_VGA AB35 +3VGS
7 CLK_PCIE_VGA PCIE_REFCLKP
CLK_PCIE_VGA# AA36
7 CLK_PCIE_VGA# PCIE_REFCLKN DIS@ Place CV326 Close to UV13
RV1
CALIBRATION 1.69K_0402_1%
PCIE_CALRP Y30 1 2 +VGA_PCIE 2 @DIS@
DIS@ CV9
1 2 AH16 Y29 1 2 0.1U_0402_25V6K SIV
PWRGOOD PCIE_CALRN +VGA_PCIE
RV2 1K_0402_5%

5
DIS@ 1
GPU_RST# AA30 RV3

VCC
PERSTB 1K_0402_1% 8 DGPU_HOLD_RST# 1 IN1
1

4 GPU_RST#
DIS@ 216-0833000-A11-THAMES-XT-M2_FCBGA962~D OUT
Thames 2

GND
8,26,29,30,33 PLT_RST# IN2
RV4 THAMES XT M2 RV198, 1.27K_0402_1% pull-down
100K_0402_5% UV2
DIS@ RV203, 2K_0402_1% pull-up MC74VHC1G08DFT2G_SC70-5
2

3
PWR need to Modify +VGA_PCIE DIS@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/03/03 Deciphered Date 2015/03/03 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Venus XTX(1/8) PCIE/PWRseq
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-B131P
Date: Tuesday, March 04, 2014 Sheet 17 of 52
5 4 3 2 1
 5 4 3 2 1

CONFIGURATION STRAPS RECOMMENDED SETTINGS

ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE 0= DO NOT INSTALL RESISTOR
+1.8VGS 1 = INSTALL 10K RESISTOR
GPIOS ARE USED, THEY MUST NOT CONFLICT DURING RESET X = DESIGN DEPENDANT
RV5 1 2 @ 10K_0402_5% VRAM_ID0 NA = NOT APPLICABLE
RV6 1 2 @ 10K_0402_5% UV1B
RV7 1 2 @ 10K_0402_5% VRAM_ID1
RV8 1 2 @ 10K_0402_5% RECOMMENDED
RV9 1 2 @ 10K_0402_5% VRAM_ID2 STRAPS PIN DESCRIPTION OF DEFAULT SETTINGS SETTINGS
RV10 1 2 @ 10K_0402_5% AU24
TXCAP_DPA3P 0: 50% swing
AV23
TXCAM_DPA3N TX_PW RS_ENB GPIO0 PCIE FULL TX OUTPUT SW ING 1: Full swing X
AT25
MUTI GFX TX0P_DPA2P 0: disable
AR24
DPA TX0M_DPA2N TX_DEEMPH_EN GPIO1 PCIE TRANSMITTER DE-EMPHASIS 1: enable X
Vendor VRAM_ID0 VRAM_ID1 VRAM_ID2 TX1P_DPA1P
AU26
AV25 Advertises PCIE speed 0: 2.5GT/s
TX1M_DPA1N RSVD GPIO2 1: 5GT/s 0
when compliance test
D H5TC2G63FFR-11C AR8 AT27 D
DVPCNTL_MVP_0 TX2P_DPA0P
AU8 AR26
DVPCNTL_MVP_1 TX2M_DPA0N
128MX16bits Hy b RV6 RV8 RV10 AP8
AW8
DVPCNTL_0
AR30
RSVD GPIO8 RESERVED 0
DDR3
SA00006H410 0 0 0 AR3
DVPCNTL_1
DVPCNTL_2
TXCBP_DPB3P
TXCBM_DPB3N
AT29 +3VGS
AR1 +3VGS BIF_VGA DIS GPIO9 VGA ENABLED 0
MT41J128M16JT-093G:K VRAM_ID0 DVPCLK
AU1
DVPDATA_0 TX3P_DPB2P
AV31 RV85 PU

1
VRAM_ID1 AU3 AU30 chg to @

1
DVPDATA_1 TX3M_DPB2N
128MX16bits Micron 2Gb RV6 RV8 RV9 VRAM_ID2 AW3
DVPDATA_2
DPB
RV34
RV11
@DIS@
RSVD GPIO21 RESERVED 0
DDR3 AP6 AR32
SA000067510 0 0 1 AW5
DVPDATA_3
DVPDATA_4
TX4P_DPB1P
TX4M_DPB1N
AT31 @DIS@ 10K_0402_5% 0: disable
AU5 4.7K_0402_5% BIOS_ROM_EN GPIO_22_ROMCSB ENABLE EXTERNAL BIOS ROM 1: enable X

2
K4W2G1646Q-BC1A DVPDATA_5 AC_BATT
AR6 AT33

2
DVPDATA_6 TX5P_DPB0P QV1A
AW6 AU32
DVPDATA_7 TX5M_DPB0N
128MX16bits Samsung 2Gb RV6 RV7 RV10 AU6
DVPDATA_8
DMN66D0LDW-7_SOT363-6
@DIS@
ROMIDCFG(2:0) GPIO[13:11] SERIAL ROM TYPE OR MEMORY APERTURE SIZE SELECT XXX
DDR3 AT7 AU14
SA000068U50

3
0 1 0 DVPDATA_9 TXCCP_DPC3P
AV7 AV13
DVPDATA_10 TXCCM_DPC3N PACIN#
D
VIP_DEVICE_STRAP_ENA V2SYNC IGNORE VIP DEVICE STRAPS 0
AN7 5 G
DVPDATA_11
AV9 AT15 S

H5TC4G63AFR-11C DVPDATA_12 TX0P_DPC2P @DIS@

AT9 AR14

4
DVPDATA_13 TX0M_DPC2N QV1B RSVD H2SYNC 0
AR10

6
DVPDATA_14
256MX16bits Hy b RV6 RV7 RV9 AW10
AU10
DVPDATA_15
DPC
TX1P_DPC1P
AU16
AV15
DMN66D0LDW -7_SOT363-6 D
DDR3 30,38 VCIN1_AC_IN 1 2 2 G

SA00006y 0 0 1 1 AP10
DVPDATA_16
DVPDATA_17
TX1M_DPC1N S RSVD GENERICC 0
AV11 AT17 RV12

1
MT41J256M16HA-093G DVPDATA_18 TX2P_DPC0P 0_0402_5% AUD[1] AUD[0]
AT11 AR16
DVPDATA_19 TX2M_DPC0N @DIS@ AUD[1] HSYNC 11
AR12 0 0 No audio function
DVPDATA_20
256MX16bits Micron 4Gb RV5 RV8 RV10 AW12
DVPDATA_21 TXCDP_DPD3P
AU20
AUD[0] VSYNC
0 1 Audio for DisplayPort and HDMI if dongle is detected
DDR3 AU12 AT19 1 0 Audio for DisplayPort only
SA000077K10 1 0 0 AP12
DVPDATA_22
DVPDATA_23
TXCDM_DPD3N
1 1 Audio for both DisplayPort and HDMI
AT21
K4W4G1646D-BC1A TX3P_DPD2P
AJ21 AR20
AK21
SWAPLOCKA
SWAPLOCKB
TX3M_DPD2N AMD RESERVED CONFIGURATION STRAPS
256MX16bits Samsung 4Gb RV5 RV8 RV9 DPD
TX4P_DPD1P
AU22
AV21
ALLOW FOR PULLUP PADS FOR THESE STRAPS BUT DO NOT INSTALL
DDR3
SA000076P10 1 0 1 TX4M_DPD1N RESISTOR. IF THESE GPIOS ARE USED, THEY MUST KEEP "LOW" AND
I2C AT23
TX5P_DPD0P NOT CONFLICT DURING RESET
T96 AK26
TX5M_DPD0N
AR22
y Debug
SCL
T97 AJ26
SDA (y ) GPIO21 H2SYNC GENERICC GPIO2 GPIO8

AD39 T75
GENERAL PURPOSE I/O R
AD37
GPU_GPIO0 RB
AH20
GPU_GPIO1 GPIO_0 T76
AH18 AE36
GPIO_1 G
+3VGS STRAPS T95
AN16
AH23
GPU_GPIO2
GPIO_2 GB
AD35
TX_PWRS_ENB
Transmitter Power Saving Enable
GPIO0 0: 50% Tx output swing for mobile mode
T94 GPIO_3_SMBDATA T77
AJ23
GPIO_4_SMBCLK B
AF37 1: full Tx output swing (Default setting for Desktop)
AC_BATT AH17 AE38
30,37 AC_BATT GPIO_5_AC_BATT DAC1 BB
4.7K_0402_5% 1 DIS@ 2 RV13 THM_ALERT# AJ17 PCI Express Transmitter De-emphasis Enable
C GPIO_6 T78 C
SIV AK17
GPIO_7_BLON HSYNC
AC36 TX_DEEMPH_EN GPIO1 0: Tx de-emphasis diabled for mobile mode
GPU_GPIO8 AJ13 AC38 T79 1: Tx de-emphasis enabled (Defailt setting for desktop)
10K_0402_5% 1 @DIS@ 2 RV16 GPU_GPIO0 GPU_GPIO9 GPIO_8_ROMSO VSYNC
AH15
GPU_VID5 GPIO_9_ROMSI DIS@
45 GPU_VID5 AJ16
@DIS@ GPU_GPIO11 GPIO_10_ROMSCK RV15 1 +1.8VGS
AK16 AB34 2 499_0402_1% 65mA
GPIO_11 RSET
1
2
8
7
GPU_GPIO2
GPU_GPIO1 SIV 45 GPU_VID4
GPU_VID4
GPU_GPIO13
AL16
AM16
GPIO_12 10mil
AD34 +AVDD 1 2
GPU_GPIO8 GPU_GPIO14 GPIO_13 AVDD
3 6 AM14
GPIO_14_HPD2 AVSSQ
AE34 (1.8V@65mA AVDD) DIS@
GPU_GPIO9 GPU_VID3
10mil

CV11

CV12

CV10
4 5 AM13 100mA LV1

1U_0402_6.3V6K

10U_0603_6.3V6M
0.1U_0402_16V7K
45 GPU_VID3 GPIO_15_PWRCNTL_0 +1.8VGS +1.8VGS +1.8VGS
GPU_VID2 AK14 AC33 +VDD1DI(1.8V@100mA VDD1DI) 1 2 +1.8VGS 1 1 1 BLM15BD121SN1D_0402
45 GPU_VID2 GPIO_16 VDD1DI
RP19 THM_ALERT# AG30 AC34 DIS@
31 THM_ALERT# GPIO_17_THERMAL_INT VSS1DI
10K_8P4R_5%

CV13

CV14

CV15
AN14 LV2

1U_0402_6.3V6K

10U_0603_6.3V6M
0.1U_0402_16V7K
RV18 1 @DIS@ GPIO_18_HPD3
2 10K_0402_5% BLM15BD121SN1D_0402

DIS@

DIS@

DIS@
AM17 1 1 1

1
GPIO_19_CTF 2 2 2
10K_0402_5% 1 2 RV19 GPU_GPIO11
@DIS@
45 GPU_VID1
GPU_VID1 AL13 AC30
10K_0402_5% 1 @DIS@ GPIO_20_PWRCNTL_1 R2/NC
2 RV22 GPU_GPIO14 AJ14 AC31 RV23 RV20 RV21
10K_0402_5% 1 @DIS@ GPIO_21_BB_EN R2B/NC
2 RV24 GPU_GPIO13 T80 8.45K_0402_1% 10K_0402_1% 8.45K_0402_1%

DIS@

DIS@

DIS@
AK13
GPIO_22_ROMCSB 2 2 2
1K_0402_5% 1 2 RV25 AC_BATT
@DIS@ T98 GPUCLK_REQ#_R AN13 AD30 DIS@ @DIS@ @DIS@
SVT
GPIO24_TRSTBAM23 GPIO_23_CLKREQB G2/NC PS_1
connect to PWR AD31

2
@DIS@ GPIO25_TDI JTAG_TRSTB G2B/NC PS_1 PS_2 PS_3
AN23
GPIO24_TRSTB GPIO26_TCK AK23 JTAG_TDI
1 8 AF30
JTAG_TCK B2/NC

1
2 7 GPIO25_TDI GPIO27_TMS AL24 AF31
GPIO27_TMS T81 JTAG_TMS B2B/NC RV26 RV28 RV29 RV30
3 6 AM24 1 1 1

0.68U_0402_10V

0.68U_0402_10V

0.68U_0402_10V
GPIO26_TCK JTAG_TDO
4 5 AJ19 1 2 +DPLL_PVDD 2K_0402_1% 4.75K_0402_1% 4.75K_0402_1%
GENERICA @DIS@0_0402_5% CV16 DIS@ CV17 DIS@ CV18 DIS@
AK19 AC32
RP20 GENERICB C/NC RV27
AJ20 AD32

2
10K_8P4R_5% GENERICC Y/NC 2 2 2
AK20 AF32 1 2 DPLL_PVSS @DIS@ @DIS@ @DIS@
GENERICD COMP/NC @DIS@0_0402_5%
AJ24
GENERICE_HPD4 DAC2
AH26
GENERICF_HPD5 T82
AH24 AD29
GENERICG_HPD6 H2SYNC/GENLK_CLK T83
AC29
V2SYNC/GENLK_VSYNC
AK24
HPD1 PS_2
AG31
+1.8VGS VDD2DI/NC
AG32
VSS2DI/NC
(75mA) 0.60 V level, Please
LV3 DIS@
+DPLL_PVDD
VREFG Divider ans
2 1
cap close to ASIC A2VDD/NC
AG33 VENUS MLPs
BLM15BD121SN1D_0402 +1.8VGS
PS_3 PS_3 used default
20mil
CV20

CV21

CV22

DIS@ AD33 SIT

10U_0603_6.3V6M

1U_0402_6.3V6K

0.1U_0402_16V7K

A2VDDQ/NC
1 1 1 2 RV31 1 499_0402_1% +VREFG_GPUAH13
DIS@ VREFG
AF33 1 2
A2VSSQ/TSVSSQ
2 RV33 1 249_0402_1%
DIS@ RV32 0_0402_5%
2 2 2
20mil
DIS@

DIS@

DIS@

2 1 AA29
R2SET/NC
CV19 0.1U_0402_16V7K
1 2
+DPLL_PVDDAM32
DPLL_PVSS AN32
DPLL_PVDD NC_TSVSSQ should be tied to GND
DPLL_PVSS
RV44 0_0402_5%
+VGA_PCIE (125mA) +3VGS 20mil
+DPLL_VDDCAN31 PLL/CLOCK
DDC/AUX
DDC1CLK
AM26
AN26 PS0_[1] = 1
SIT DPLL_VDDC DDC1DATA
LV4 DIS@ 0.95V@Venus
PS0_[2] = 0 For a 256-MB aperture size, PS_0[3:1] is set to 001
1

B 2 1 +DPLL_VDDC AM27 B
BLM15BD121SN1D_0402 RV35 XTALIN AUX1P
XTALIN AV33 AL27
XTALOUT AU34 XTALIN AUX1N
PS0_[3] = 0
CV23

CV24

CV25

10K_0402_5% Voltage Swing: 1.8 V

10U_0603_6.3V6M

1U_0402_6.3V6K

0.1U_0402_16V7K

XTALOUT
1 1 1 @DIS@ AM19
DDC2CLK
AL19 PS0_[4] = 1 Must be 1 at reset.
2

TS_FDO DDC2DATA
AW34
XO_IN
AUX2P
AN20 PS0_[5] = 1 Audio-capable display outputs. 111 = No usable endpoints.
1

2 2 2
DIS@

DIS@

DIS@

AW35 AM20
RV36 XO_IN2 AUX2N
10K_0402_5% AL30
DDCCLK_AUX3P
DIS@ DDCDATA_AUX3N
AM30
PS1_[1] = 1 PCIe GEN3 is supported = 1
2

AL29
Add 12/6 for MLPS 31 REMOTE2+ AF29
DPLUS THERMAL
DDCCLK_AUX4P
DDCDATA_AUX4N
AM29 PS1_[2] = 0 Must be 0 at reset.
AG29
GCLK (RV187 cl\ose t\o \YV1.1)
31 REMOTE2- DMINUS
DDCCLK_AUX5P
AN21 PS1_[3] = 0 Must be 0 at reset.
TS_FDO AK32
DDCDATA_AUX5N
AM21
y Debug PS1_[4] = 1 Full Tx output swing = 1
TS_FDO

34 GPU_XTALIN_GCLK
GPU_XTALIN_GCLK 1 2 XTALIN (5mA) AL31
DDC6CLK
AJ30
AJ31 (y ) PS1_[5] = 1 Tx deemphasis enabled = 1
RV187 0_0402_5% DIS@ TS_A/NC DDC6DATA
SVT (1.8V@20mA TSVDD)
RESERVE FOR GREEN CLOCK LV5 AK30 T84
DDCCLK_AUX7P
+1.8VGS 1 2
BLM15BD121SN1D_0402
+TSVDD 10mil
AJ32
TSVDD DDCDATA_AUX7N
AK29 T85
AJ33
PS2_[1] = 0 Reserved
10U_0603_6.3V6M

1U_0402_6.3V6K

0.1U_0402_16V7K

TSVSS
DIS@ CV26

DIS@ CV28

DIS@ CV29

1 1 1
216-0833000-A11-THAMES-XT-M2_FCBGA962~D
DIS@
PS2_[2] = 0 Reserved
RV37 NOGCLK@
1M_0402_5%
2 2 2
PS2_[3] = 0 Disable the external BIOS ROM device = 1
XTALOUT XTALIN PS2_[4] = 1 The device will not be recognized as the systems VGA controller = 1
YV1 NOGCLK@
27MHZ_10PF_7V27000050
PS2_[5] = 1 Reserved
3 1
3 1
PS3_[1] = 0 Reserved
1

CV30 GND GND CV31

10P_0402_50V8J 10P_0402_50V8J
4 2 PS3_[2] = 0 Reserved
2

NOGCLK@ NOGCLK@
PS3_[3] = 0 Reserved
PS3_[4] = 1 Audio-capable display outputs. 111 = No usable endpoints.
+3VGS
PS3_[5] = 1 Audio-capable display outputs. 111 = No usable endpoints.
1

+3VGS
A @DIS@ A
RV40
2

2.2K_0402_5%
G

1 3 GPUCLK_REQ#_R
7 GPUCLK_REQ#
D

SUN internal VGA Thermal Sensor QV2 @DIS@

2N7002K_SOT23-3

Address 0x714

Security Classification
2014/03/03
Compal Secret Data
2015/03/03 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Venus XTX(2/8) Main Gen
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
D 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-B131P
Date: Tuesday, March 04, 2014 Sheet 18 of 52
5 4 3 2 1
 5 4 3 2 1

PX_MODE=1 for Normal Operation

PX_MODE=0 for BACO mode to shut down power rails expcept VDDR3,PCIE_VDDC and 1.8V rail

Note:
PX4.0 +VGA_CORE,VDDCI,+1.5VGS ON Switch circuits in BACO desingns for Thames/Seymour only
PX4.0 +3VGS, +1.0VGS,+1.8VGS OFF
PX5.0 +3VGS,+VGA_CORE,VDDCI,+1.5VGV,+1.0VGS,+1.8VGS OFF 55mA@1.0V, in BACO mode
D D

+3VS TO +3VGS
+3VS +3VGS

JP2 @DIS@
2 1

2MM 1 DIS@ 1 DIS@

+VGA_PCIE 60mil +BIF_VDDC

1
CV34 CV35
10U_0603_6.3V6M 1U_0603_10V6K R829 RV45
10_0805_1% 0_0805_5%
2 2

D
3 1 @DIS@ 1 2
SVT SIT

2
C QV5 DIS@ C
ME2301DC-G_SOT23-3

G
2
+5VALW DIS@ DIS@

1
RV47 RV48 SIV D
1
1 2 2 Q7 CV33
G 2N7002K_SOT23-3
20K_0402_5% 1K_0402_5% S @DIS@ DIS@ 22U_0805_6.3V6M

3
2
1
6

DIS@
DIS@ CV36 SIT
Q17A 0.1U_0603_25V7K
2
8,9,30,41,42 DGPU_PW R_EN 2
ME2N7002D1KW -G 2N SOT363-6
1

SVT

+1.5VS to +MEM_GFX
+1.5VS +MEM_GFX

B B
+MEM_GFX
Power seguence of Venus XTX SVT
Q139 DIS@

2
8 D S 1
7 2 R825
D S 470_0805_5% DIS@
6 D S 3 1
5 4 R826 DIS@ DIS@
D G 200K_0402_5% + C342

1
AO4354_SO8 VRAM_1.5VS_GATE 150U_B2_6.3VM_R35M
+3VGS 1
1 2 B+

3
DIS@ 2

0.01U_0402_25V7K
SVT
R830 C900 R827 Q15A
@DIS@ 820K_0402_5% Q15B
+VGA_PCIE (0.95V) 33_0603_5%
DIS@
2
2 1.5V_PW R_EN# 5 ME2N7002D1KW -G 2N SOT363-6
ME2N7002D1KW -G 2N SOT363-6 DIS@

2
DIS@

4
SIT +5VALW
+1.8VGS
1 2
100K_0402_5% R828
DIS@
+MEM_GFX (1.5V)

3
<20ms DIS@
Q17B
+VGA_CORE >100ms
30,45 GPU_PW R_EN 5
ME2N7002D1KW -G 2N SOT363-6

4
SVT
GPU_RST#
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/03/03 Deciphered Date 2015/03/03 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Venus XTX(3/8) DC/DC POWER
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-B131P
Date: Tuesday, March 04, 2014 Sheet 19 of 52
5 4 3 2 1
 5 4 3 2 1

UV1F

AB39 PCIE_VSS#1 GND#1 A3

E39 PCIE_VSS#2 GND#2 A37
F34 PCIE_VSS#3 GND#3 AA16
F39 PCIE_VSS#4 GND#4 AA18
G33 PCIE_VSS#5 GND#5 AA2
G34 PCIE_VSS#6 GND#6 AA21
H31 PCIE_VSS#7 GND#7 AA23
H34 PCIE_VSS#8 GND#8 AA26
H39 PCIE_VSS#9 GND#9 AA28
J31 PCIE_VSS#10 GND#10 AA6
D J34 PCIE_VSS#11 GND#11 AB12 D
K31 PCIE_VSS#12 GND#12 AB15
K34 PCIE_VSS#13 GND#13 AB17
(30mA) K39
L31
PCIE_VSS#14 GND#14 AB20
AB22
+DPAB_VDD18 +1.8VGS PCIE_VSS#15 GND#15
L34 PCIE_VSS#16 GND#16 AB24
1.8V@300mA DPAB_VDD18) M34 PCIE_VSS#17 GND#17 AB27
+DPAB_VDD18 1 2 M39 AC11
PCIE_VSS#18 GND#18
1 1 1 N31 PCIE_VSS#19 GND#19 AC13
RV57 0_0402_5%

DIS@ CV37

DIS@ CV38

DIS@ CV39
10U_0603_6.3V6M
0.1U_0402_16V7K

1U_0402_6.3V6K
N34 PCIE_VSS#20 GND#20 AC16
UV1H
(30mA) 20mil SIT
P31
P34
PCIE_VSS#21 GND#21 AC18
AC2
+1.8VGS +DPCD_VDD18 DP C/D POWER 2 2 2 PCIE_VSS#22 GND#22
1.8V@300mA DPCD_VDD18) DP A/B POWER 20mil P39 PCIE_VSS#23 GND#23 AC21
130mA R34
PCIE_VSS#24 GND#24
AC23
1 2 +DPCD_VDD18 AP20 AN24 T31 AC26
DPCD/DPC_VDD18#1 DPAB/DPA_VDD18#1 PCIE_VSS#25 GND#25
RV46 0_0402_5%
AP21
DPCD/DPC_VDD18#2 DPAB/DPA_VDD18#2
AP24 (330mA) T34
PCIE_VSS#26 GND#26
AC28

CV40

CV41

CV42
10U_0603_6.3V6M

1U_0402_6.3V6K

0.1U_0402_16V7K
T39 AC6
+DPCD_VDD10 +DPAB_VDD10 +VGA_PCIE PCIE_VSS#27 GND#27
SIT 1 1 1 20mil (1.0V@220mA DPAB_VDD10) U31
PCIE_VSS#28 GND#28
AD15
20mil 110mA 0.95V@Venus U34
PCIE_VSS#29 GND#29
AD17
@DIS@ @DIS@ @DIS@ AP13 AP31 +DPAB_VDD10 1 2 V34 AD20
DPCD/DPC_VDD10#1 DPAB/DPA_VDD10#1 PCIE_VSS#30 GND#30

10U_0603_6.3V6M
0.1U_0402_16V7K

1U_0402_6.3V6K
AT13 AP32 V39 AD22
2 2 2 DPCD/DPC_VDD10#2 DPAB/DPA_VDD10#2 RV51 0_0402_5% PCIE_VSS#31 GND#31

DIS@ CV43

DIS@ CV44

DIS@ CV45
W31 AD24
PCIE_VSS#32 GND#32
1 1 1 W34 AD27
SIT PCIE_VSS#33 GND#33
AN17 AN27 Y34 AD9
DP/DPC_VSSR#1 DP/DPA_VSSR#1 PCIE_VSS#34 GND#34
AP16 AP27 Y39 AE2
DP/DPC_VSSR#2 DP/DPA_VSSR#2 PCIE_VSS#35 GND#35
AP17 AP28 AE6
DP/DPC_VSSR#3 DP/DPA_VSSR#3 2 2 2 GND#36
(220mA) +DPCD_VDD10
AW14
AW16
DP/DPC_VSSR#4 DP/DPA_VSSR#4
AW24
AW26
GND#37
AF10
AF16
+VGA_PCIE DP/DPC_VSSR#5 DP/DPA_VSSR#5 GND#38
1.0V@220mA DPCD_VDD10) GND#39
AF18
0.95V@Venus +DPCD_VDD18 +DPAB_VDD18 AF21
1 2
0_0402_5%
+DPCD_VDD10 20mil
AP22
DPCD/DPD_VDD18#1 DPAB/DPB_VDD18#1
20mil
AP25 130mA F15
GND#100
GND GND#40
GND#41
GND#42
AG17
AG2
RV50
@DIS@ CV46

@DIS@ CV47

@DIS@ CV48
10U_0603_6.3V6M

1U_0402_6.3V6K

0.1U_0402_16V7K

AP23 AP26 F17 AG20

DPCD/DPD_VDD18#2 DPAB/DPB_VDD18#2 GND#101 GND#43
SIT 1 1 1 F19 AG22
+DPCD_VDD10 +DPAB_VDD10 GND#102 GND#44
F21 AG6
GND#103 GND#45
20mil 20mil F23
GND#104 GND#46
AG9
AP14 AN33 110mA F25 AH21
2 2 2 DPCD/DPD_VDD10#1 DPAB/DPB_VDD10#1 GND#105 GND#47
C AP15 AP33 F27 AJ10 C
DPCD/DPD_VDD10#2 DPAB/DPB_VDD10#2 GND#106 GND#48
F29 AJ11
GND#107 GND#49
F31 AJ2
GND#108 GND#50
F33 AJ28
GND#109 GND#51
AN19 AN29 F7 AJ6
DP/DPD_VSSR#1 DP/DPB_VSSR#1 GND#110 GND#52
AP18 AP29 F9 AK11
DP/DPD_VSSR#2 DP/DPB_VSSR#2 GND#111 GND#53
AP19 AP30 G2 AK31
DP/DPD_VSSR#3 DP/DPB_VSSR#3 GND#112 GND#54
AW20 AW30 G6 AK7
DP/DPD_VSSR#4 DP/DPB_VSSR#4 GND#113 GND#55
AW22 AW32 H9 AL11
DP/DPD_VSSR#5 DP/DPB_VSSR#5 DIS@ GND#114 GND#56
J2 AL14
RV54 GND#115 GND#57
J27 AL17
150_0402_1% GND#116 GND#58
J6 AL2
150_0402_1% 2 DIS@ GND#117 GND#59
1 RV53 AW18 DPCD_CALR DPAB_CALR
AW28 1 2 J8
GND#118 GND#60
AL20
+1.8VGS (330mA) +DPEF_VDD18 +DPAB_VDD18
K14
K7
GND#119 GND/PX_EN#61
AL21
AL23
GND#120 GND#62
1.8V@300mA DPEF_VDD18) 20mil DP E/F POWER DP PLL POWER 20mA 10mil L11
GND#121 GND#63
AL26
1 2 +DPEF_VDD18 AH34
DPAB_VDD18/DPA_PVDD AU28
L17 AL32
DPEF/DPE_VDD18#1 GND#122 GND#64

1
AJ34
DP_VSSR/DPA_PVSS AV27
L2 AL6
RV52 0_0402_5% DPEF/DPE_VDD18#2 GND#123 GND#65
DIS@ CV49

DIS@ CV50

DIS@ CV51

@DIS@
10U_0603_6.3V6M

1U_0402_6.3V6K

0.1U_0402_16V7K

L22 AL8
+DPEF_VDD10 +DPAB_VDD18 GND#124 GND#66 RV56
SIT 1 1 1 L24 AM11
GND#125 GND#67 4.7K_0402_5%
20mil 20mA 10mil L6
GND#126 GND#68
AM31
AL33 AV29 M17 AM9

2
DPEF/DPE_VDD10#1 DPAB_VDD18/DPB_PVDD GND#127 GND#69
AM33 AR28 M22 AN11
2 2 2 DPEF/DPE_VDD10#2 DP_VSSR/DPB_PVSS GND#128 GND#70
M24 AN2
+DPCD_VDD18 GND#129 GND#71
N16 AN30
GND#130 GND#72
20mA 10mil N18
GND#131 GND#73
AN6
AN34 AU18 N2 AN8
DP/DPE_VSSR#1 DPCD_VDD18/DPC_PVDD GND#132 GND#74
AP39 AV17 N21 AP11
+DPEF_VDD10 DP/DPE_VSSR#2 DP_VSSR/DPC_PVSS GND#133 GND#75
(220mA) AR39
AU37
DP/DPE_VSSR#3 +DPCD_VDD18
N23
N26
GND#134 GND#76
AP7
AP9
+VGA_PCIE DP/DPE_VSSR#4 GND#135 GND#77
1.0V@240mA DPEF_VDD10) 20mA 10mil N6
GND#136 GND#78
AR5
0.95V@Venus DPCD_VDD18/DPD_PVDD
AV19 R15
GND#137 GND#79
B11
1 2 +DPEF_VDD10 +DPEF_VDD18 AR18 R17 B13
DP_VSSR/DPD_PVSS GND#138 GND#80
RV55 0_0402_5% 20mil R2
GND#139 GND#81
B15
@DIS@ CV52

@DIS@ CV53

@DIS@ CV54

+DPEF_VDD18
10U_0603_6.3V6M

1U_0402_6.3V6K

0.1U_0402_16V7K

AF34 R20 B17

DPEF/DPF_VDD18#1 GND#140 GND#82
SIT 1 1 1 AG34
DPEF/DPF_VDD18#2
20mA 10mil R22
GND#141 GND#83
B19
AM37 R24 B21
+DPEF_VDD10 DPEF_VDD18/DPE_PVDD GND#142 GND#84
B AN38 R27 B23 B
DP_VSSR/DPE_PVSS GND#143 GND#85
2 2 2
20mil R6
GND#144 GND#86
B25
AK33 +DPEF_VDD18 T11 B27
DPEF/DPF_VDD10#1 GND#145 GND#87
AK34
DPEF/DPF_VDD10#2
20mA 10mil T13
GND#146 GND#88
B29
AL38 T16 B31
DPEF_VDD18/DPF_PVDD GND#147 GND#89
AM35 T18 B33
DP_VSSR/DPF_PVSS GND#148 GND#90
T21 B7
GND#149 GND#91
AF39 T23 B9
DP/DPF_VSSR#1 GND#150 GND#92
AH39 T26 C1
DP/DPF_VSSR#2 GND#151 GND#93
AK39 U15 C39
DP/DPF_VSSR#3 GND#153 GND#94
AL34 U17 E35
PS_0 DP/DPF_VSSR#4 GND#154 GND#95
AM34 U2 E5
DP/DPF_VSSR#5 GND#155 GND#96
U20 F11
GND#156 GND#97
U22 F13
+1.8VGS GND#157 GND#98
U24
GND#158
AM39 U27
DPEF_CALR GND#159
U6
GND#160
V11
GND#161
1

DIS@ 216-0833000-A11-THAMES-XT-M2_FCBGA962~D V16

GND#163
1

RV59 DIS@ V18

DIS@ 150_0402_1% GND#164
V21
RV58 GND#165
V23
8.45K_0402_1% GND#166
V26
2

GND#167
W2
2

GND#168
W6
PS_0 GND#169
Y15
GND#170
Y17
GND#171
Y20
GND#172
1

1 Y22 A39
DIS@ @DIS@ GND#173 VSS_MECH#1 T86 PAD
Y24 AW1
RV60 CV55 GND#174 VSS_MECH#2 T87 PAD
Y27 AW39
2K_0402_1% 0.68U_0402_10V GND#175 VSS_MECH#3 T88 PAD
U13
2 GND#152
V13
2

GND#162
Thames/Seymour Only 216-0833000-A11-THAMES-XT-M2_FCBGA962~D
DIS@
Do not install for Heathrow/Mars Pro
A A
PS_0 Should be tied to GND on Thames/Seymour

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/03/03 Deciphered Date 2015/03/03 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Venus XTX(4/8)DPX Power/GND
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B131P
Date: Tuesday, March 04, 2014 Sheet 20 of 52
5 4 3 2 1
 5 4 3 2 1

(440mA) +1.8VGS
(1.8V@504mA PCIE_VDDR) @DIS@ LV6
+PCIE_VDDR 1 2
BLM15PD121SN1D_0402

CV56

CV57

CV58

CV59

CV66

CV60
10U_0603_6.3V6M
0.1U_0402_16V7K

0.1U_0402_16V7K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1 1 1 1 1 1
SIV

2 2 2 2 2 2

@DIS@

@DIS@

@DIS@

@DIS@

@DIS@

@DIS@
UV1E +1.8VGS
For GDDR3 MVDDQ = 1.5V 40mA DIS@ LV7
+MEM_GFX MEM I/O
D (1.7)A 40mil 1 2 D

CV67

CV68

CV69
PCIE

10U_0603_6.3V6M
0.1U_0402_16V7K

1U_0402_6.3V6K
BLM15PD121SN1D_0402
AC7
AD11
VDDR1#1 PCIE_VDDR#1 AA31
AA32
1 1 1 (SUN)(VENUS)
VDDR1#2 PCIE_VDDR#2

220U_B2_2.5VM_R35

CV61

CV71

CV72

CV73

CV74

CV75

CV62

CV76

CV63

CV77
@DIS@1 2 +PCIE_VDDR SIV (PCIe 2.0 => 1.8V@50mA PCIE_PVDD)

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1 AF7 VDDR1#3 PCIE_VDDR#3 AA33

CV70 @DIS@
1 1 1 1 1 1 1 1 1 1 AG10 AA34 RV61 0_0402_5%
+ VDDR1#4 PCIE_VDDR#4 2 2 2

DIS@

DIS@

DIS@
AJ7 VDDR1#5 PCIE_VDDR#5 V28 (PCIe 3.0 => 1.8V@80mA PCIE_PVDD)
AK8 W29 @DIS@1 2 +BIF_VDDC
VDDR1#6 PCIE_VDDR#6 RV62 0_0402_5%
AL9 VDDR1#7 PCIE_VDDR#7 W30
2 2 2 2 2 2 2 2 2 2 2

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@
G11 VDDR1#8 PCIE_VDDR#8 Y31
G14 AB37 +PCIE_PVDD +VGA_PCIE
VDDR1#9 PCIE_VDDR/PCIE_PVDD
G17 VDDR1#10
G20 VDDR1#11 PCIE_VDDC#1 G30
G23 G31
VDDR1#12 PCIE_VDDC#2

CV78

CV79

CV80

CV81

CV82

CV64
(SUN) (VENUS)

10U_0603_6.3V6M
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
G26 H29
VDDR1#13 PCIE_VDDC#3
G29 H30 1 1 1 1 1 1
VDDR1#14 PCIE_VDDC#4
H10
VDDR1#15 PCIE_VDDC#5
J29 (PCIe 2.0 => +0.95V@1920mA PCIE_VDDC)
+MEM_GFX J7 J30
VDDR1#16 PCIE_VDDC#6
J9
VDDR1#17 PCIE_VDDC#7
L28
2 2 2 2 2 2
(PCIe 3.0 => +0.95V@2.5A PCIE_VDDC)

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@
K11 M28
VDDR1#18 PCIE_VDDC#8
K13 N28
VDDR1#19 PCIE_VDDC#9

CV83

CV84

CV65

CV85

CV86
0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K
K8 R28
VDDR1#20 PCIE_VDDC#10
1 1 1 1 1 L12 T28
VDDR1#21 PCIE_VDDC#11
L16 U28
VDDR1#22 PCIE_VDDC#12 +VGA_CORE
L21
VDDR1#23
L23
2 2 2 2 2 VDDR1#24

DIS@

DIS@

DIS@

DIS@

DIS@
L26
L7
VDDR1#25 CORE VDDC#1
AA15
AA17
(20.5A)
VDDR1#26 VDDC#2
M11 AA20
VDDR1#27 VDDC#3
N11 AA22
VDDR1#28 VDDC#4
P7 AA24 1
VDDR1#29 VDDC#5
R11 AA27
VDDR1#30 VDDC#6 CV87
U11 AB16
+1.8VGS +VDDC_CT VDDR1#31 VDDC#7 330U_D2_2.5V_R6M
(50mA) U7
Y11
VDDR1#32 VDDC#8
AB18
AB21 2 ESD@
DIS@ LV8 VDDR1#33 VDDC#9
(1.8V@110mA VDD_CT) Y7
VDDR1#34 VDDC#10
AB23
1 2 AB26
BLM15BD121SN1D_0402 VDDC#11
C VDDC#12
AB28 ESD solution C
CV88

CV89

CV90

CV91

CV92
10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

0.1U_0402_16V7K
AC17
VDDC#13
1 1 1 1 1 AC20
LEVEL VDDC#14
+3VGS 20mil TRANSLATION VDDC#15
AC22
AC24
VDDC#16

POWER
(60mA) 2 2 2 2 2
AF26
VDD_CT#1 VDDC#17
AC27
DIS@

DIS@

DIS@

DIS@

DIS@
AF27 AD18
VDD_CT#2 VDDC#18
AG26 AD21
VDD_CT#3 VDDC#19
CV93

CV94

CV95

CV96
10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

AG27 AD23
VDD_CT#4 VDDC#20
1 1 1 1 AD26
VDDC#21
10mil I/O VDDC#22
AF17
AF20
VDDC#23
AF23 AF22
2 2 2 2 VDDR3#1 VDDC#24
DIS@

DIS@

DIS@

DIS@

AF24 AG16
VDDR3#2 VDDC#25
AG23 AG18
VDDR3#3 VDDC#26
AG24 AG21
+1.8VGS DIS@ VDDR3#4 VDDC#27
LV9
20mil VDDC#28
AH22
AH27
+VDDR4 AF13 VDDC#29
1 2 AH28
BLM15BD121SN1D_0402 VDDR4#4 VDDC#30
AF15 M26
VDDR4#5 VDDC#31
CV97

CV98
1U_0402_6.3V6K

0.1U_0402_16V7K

AG13 N24
VDDR4#7 VDDC#32
1 1 AG15 N27
VDDR4#8 VDDC/BIF_VDDC#33
R18
VDDC#34
R21
VDDC#35
AD12 R23
2 2 VDDR4#1 VDDC#36
DIS@

DIS@

AF11
AF12
VDDR4#2 VDDC#37
R26
T17
55mA
VDDR4#3 VDDC#38
AG11 T20
VDDR4#6 VDDC#39 +BIF_VDDC
(150mA) VDDC#40
T22
T24
+1.8VGS (M97, VDDC#41
Broadway and Madison: 1.8V@150mA MPV18) VDDC/BIF_VDDC#42
T27
U16
VDDC#43

CV99

CV100
LV10 DIS@ SVT

1U_0402_6.3V6K

1U_0402_6.3V6K
M20 U18
NC_VDDRHA VDDC#44
1 2 M21
NC_VSSRHA VDDC#45
U21 1 1 For non-BACO designs, connect BIF_VDDC to VDDC.
CHILISIN PBY100505T-300Y-N 0402
+1.8VGS (50mA) VDDC#46
U23
U26 For BACO designs - see BACO reference schematics
VDDC#47
CV101

CV102

CV103

DIS@ LV11 (1.8V@75mA SPV18)

10U_0603_6.3V6M

1U_0402_6.3V6K

0.1U_0402_16V7K

V12 V17
NC_VDDRHB VDDC#48 2 2

DIS@

DIS@
B 1 2 1 1 1 U12
NC_VSSRHB VDDC#49
V20 B
BLM15BD121SN1D_0402 V22
VDDC#50
CV104

CV105

CV106
10U_0603_6.3V6M

1U_0402_6.3V6K

0.1U_0402_16V7K

V24
VDDC#51
1 1 1 V27
2 2 2 VDDC#52
DIS@

DIS@

DIS@

Y16
PLL VDDC#53
Y18
VDDC#54
2 2 2 20mil VDDC#55
Y21
DIS@

DIS@

DIS@

Y23
+MPV18 VDDC#56
H7 Y26
MPV18#1 VDDC#57
H8 Y28
MPV18#2 VDDC#58
(100mA) (GDDR3/DDR3 1.12V@4A VDDCI)
+VGA_CORE
+VGA_PCIE 10mil +SPV18 AM10
0.95V@Venus
LV13 DIS@ SPV18 (GDDR5 1.12V@16A VDDCI) 4A
1 2
(120mA SPV10) 20mil +SPV10 AN9
VDDCI#1
AA13
AB13
SPV10 VDDCI#2
CV110

CV111

CV112

CV113

CV114

CV115

CV116

CV117

CV118

CV119

CV120

CV121
CHILISIN PBY100505T-300Y-N 0402

10U_0603_6.3V6M

10U_0603_6.3V6M
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
AC12
+VGA_CORE VDDCI#3
CV107

CV108

CV109
10U_0603_6.3V6M

1U_0402_6.3V6K

0.1U_0402_16V7K

AN10 AC15 1 1 1 1 1 1 1 1 1 1 1 1
SVT SPVSS VDDCI#4
1 1 1 AD13
VDDCI#5
AD16
VDDCI#6
1

M15
VDDCI#7 2 2 2 2 2 2 2 2 2 2 2 2
DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@
RV64 M16
2 2 2 VDDCI#8
DIS@

DIS@

DIS@

10_0402_1% VOLTAGE M18

DIS@ SENESE VDDCI#9
M23
VDDCI#10
10mil N13
2

VDDC_SEN VDDCI#11
45 VDDC_SEN AF28 N15
FB_VDDC VDDCI#12
N17
VDDCI#13
10mil VDDCI#14
N20
AG28 N22
FB_VDDCI ISOLATED VDDCI#15 R12
CORE I/O VDDCI#16 R13
VDDC_RTN VDDCI#17
45 VDDC_RTN AH29 R16
FB_GND VDDCI#18
T12
VDDCI#19
1

T15
RV65 VDDCI#20
V15
DIS@ 10_0402_1% VDDCI#21
Y13
VDDCI#22
connect to PWR
VDDCI and VDDC should have seperate regulators with a merge option on PCB
2

A 216-0833000-A11-THAMES-XT-M2_FCBGA962~D A
DIS@
For Madison, Park, Capilano, Robson, Seymour and Whistler, VDDCI and VDDC can share one common regulator

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/03/03 Deciphered Date 2015/03/03 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Venus XTX(5/8) Power
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B131P
Date: Tuesday, March 04, 2014 Sheet 21 of 52
5 4 3 2 1
 5 4 3 2 1

M_DA[63..0]
23 M_DA[63..0] M_DB[63..0]
UV1C UV1D
M_MAA[14..0] DDR2 DDR2 24 M_DB[63..0] DDR2 DDR2
23 M_MAA[14..0] GDDR3/GDDR5 GDDR5/GDDR3 M_MAB[14..0] GDDR3/GDDR5 GDDR5/GDDR3
M_DQMA[7..0] DDR3 DDR3 24 M_MAB[14..0] DDR3 DDR3
23 M_DQMA[7..0] M_DQMB[7..0]
M_DA0 C37 G24 M_MAA0 M_DB0 C5 P8 M_MAB0
M_DQSA[7..0] DQA0_0/DQA_0 MAA0_0/MAA_0 24 M_DQMB[7..0] DQB0_0/DQB_0 MAB0_0/MAB_0
M_DA1 C35 J23 M_MAA1 M_DB1 C3 T9 M_MAB1
23 M_DQSA[7..0] DQA0_1/DQA_1 MAA0_1/MAA_1 M_DQSB[7..0] DQB0_1/DQB_1 MAB0_1/MAB_1
M_DA2 A35 H24 M_MAA2 M_DB2 E3 P9 M_MAB2
M_DQSA#[7..0] DQA0_2/DQA_2 MAA0_2/MAA_2 24 M_DQSB[7..0] DQB0_2/DQB_2 MAB0_2/MAB_2
M_DA3 E34 J24 M_MAA3 M_DB3 E1 N7 M_MAB3
23 M_DQSA#[7..0] DQA0_3/DQA_3 MAA0_3/MAA_3 M_DQSB#[7..0] DQB0_3/DQB_3 MAB0_3/MAB_3
M_DA4 G32 H26 M_MAA4 M_DB4 F1 N8 M_MAB4

MEMORY INTERFACE A
DQA0_4/DQA_4 MAA0_4/MAA_4 24 M_DQSB#[7..0] DQB0_4/DQB_4 MAB0_4/MAB_4
M_DA5 D33 J26 M_MAA5 M_DB5 F3 N9 M_MAB5

MEMORY INTERFACE B
M_DA6 DQA0_5/DQA_5 MAA0_5/MAA_5 M_MAA6 M_DB6 DQB0_5/DQB_5 MAB0_5/MAB_5 M_MAB6
F32 DQA0_6/DQA_6 MAA0_6/MAA_6 H21 F5 DQB0_6/DQB_6 MAB0_6/MAB_6 U9
M_DA7 E32 G21 M_MAA7 M_DB7 G4 U8 M_MAB7
M_DA8 DQA0_7/DQA_7 MAA0_7/MAA_7 M_MAA8 M_DB8 DQB0_7/DQB_7 MAB0_7/MAB_7 M_MAB8
D31 DQA0_8/DQA_8 MAA1_0/MAA_8 H19 H5 DQB0_8/DQB_8 MAB1_0/MAB_8 Y9
D M_DA9 F30 H20 M_MAA9 M_DB9 H6 W9 M_MAB9 D
M_DA10 DQA0_9/DQA_9 MAA1_1/MAA_9 M_MAA10 M_DB10 DQB0_9/DQB_9 MAB1_1/MAB_9 M_MAB10
C30 DQA0_10/DQA_10 MAA1_2/MAA_10 L13 J4 DQB0_10/DQB_10 MAB1_2/MAB_10 AC8
M_DA11 A30 G16 M_MAA11 M_DB11 K6 AC9 M_MAB11
M_DA12 DQA0_11/DQA_11 MAA1_3/MAA_11 M_MAA12 M_DB12 DQB0_11/DQB_11 MAB1_3/MAB_11 M_MAB12
F28 DQA0_12/DQA_12 MAA1_4/MAA_12 J16 K5 DQB0_12/DQB_12 MAB1_4/MAB_12 AA7
M_DA13 C28 H16 M_A_BA2 M_DB13 L4 AA8 M_B_BA2
DQA0_13/DQA_13 MAA1_5/MAA_13_BA2 M_A_BA2 23 DQB0_13/DQB_13 MAB1_5/BA2 M_B_BA2 24
M_DA14 A28 J17 M_A_BA0 M_DB14 M6 Y8 M_B_BA0
DQA0_14/DQA_14 MAA1_6/MAA_14_BA0 M_A_BA0 23 DQB0_14/DQB_14 MAB1_6/BA0 M_B_BA0 24
M_DA15 E28 H17 M_A_BA1 M_DB15 M1 AA9 M_B_BA1
DQA0_15/DQA_15 MAA1_7/MAA_A15_BA1 M_A_BA1 23 DQB0_15/DQB_15 MAB1_7/BA1 M_B_BA1 24
M_DA16 D27 M_DB16 M3
M_DA17 DQA0_16/DQA_16 M_DQMA0 M_DB17 DQB0_16/DQB_16 M_DQMB0
F26 DQA0_17/DQA_17 WCKA0_0/DQMA_0 A32 M5 DQB0_17/DQB_17 WCKB0_0/DQMB_0 H3
M_DA18 C26 C32 M_DQMA1 M_DB18 N4 H1 M_DQMB1
M_DA19 DQA0_18/DQA_18 WCKA0B_0/DQMA_1 M_DQMA2 M_DB19 DQB0_18/DQB_18 WCKB0B_0/DQMB_1 M_DQMB2
A26 DQA0_19/DQA_19 WCKA0_1/DQMA_2 D23 P6 DQB0_19/DQB_19 WCKB0_1/DQMB_2 T3
M_DA20 F24 E22 M_DQMA3 M_DB20 P5 T5 M_DQMB3
M_DA21 DQA0_20/DQA_20 WCKA0B_1/DQMA_3 M_DQMA4 M_DB21 DQB0_20/DQB_20 WCKB0B_1/DQMB_3 M_DQMB4
C24 DQA0_21/DQA_21 WCKA1_0/DQMA_4 C14 R4 DQB0_21/DQB_21 WCKB1_0/DQMB_4 AE4
M_DA22 A24 A14 M_DQMA5 M_DB22 T6 AF5 M_DQMB5
M_DA23 DQA0_22/DQA_22 WCKA1B_0/DQMA_5 M_DQMA6 M_DB23 DQB0_22/DQB_22 WCKB1B_0/DQMB_5 M_DQMB6
E24 E10 T1 AK6
M_DA24 DQA0_23/DQA_23 WCKA1_1/DQMA_6 M_DQMA7 M_DB24 DQB0_23/DQB_23 WCKB1_1/DQMB_6 M_DQMB7
C22 D9 U4 AK5
M_DA25 DQA0_24/DQA_24 WCKA1B_1/DQMA_7 M_DB25 DQB0_24/DQB_24 WCKB1B_1/DQMB_7
A22 V6
M_DA26 DQA0_25/DQA_25 GDDR5/DDR2/GDDR3 M_DQSA0 M_DB26 DQB0_25/DQB_25 GDDR5/DDR2/GDDR3 M_DQSB0
F22 C34 V1 F6
M_DA27 DQA0_26/DQA_26 EDCA0_0/QSA_0/RDQSA_0 M_DQSA1 M_DB27 DQB0_26/DQB_26 EDCB0_0/QSB_0/RDQSB_0 M_DQSB1
D21 D29 V3 K3
M_DA28 DQA0_27/DQA_27 EDCA0_1/QSA_1/RDQSA_1 M_DQSA2 M_DB28 DQB0_27/DQB_27 EDCB0_1/QSB_1/RDQSB_1 M_DQSB2
A20 D25 Y6 P3
M_DA29 DQA0_28/DQA_28 EDCA0_2/QSA_2/RDQSA_2 M_DQSA3 M_DB29 DQB0_28/DQB_28 EDCB0_2/QSB_2/RDQSB_2 M_DQSB3
F20 E20 Y1 V5
M_DA30 DQA0_29/DQA_29 EDCA0_3/QSA_3/RDQSA_3 M_DQSA4 M_DB30 DQB0_29/DQB_29 EDCB0_3/QSB_3/RDQSB_3 M_DQSB4
D19 E16 Y3 AB5
M_DA31 DQA0_30/DQA_30 EDCA1_0/QSA_4/RDQSA_4 M_DQSA5 M_DB31 DQB0_30/DQB_30 EDCB1_0/QSB_4/RDQSB_4 M_DQSB5
E18 E12 Y5 AH1
M_DA32 DQA0_31/DQA_31 EDCA1_1/QSA_5/RDQSA_5 M_DQSA6 M_DB32 DQB0_31/DQB_31 EDCB1_1/QSB_5/RDQSB_5 M_DQSB6
C18 J10 AA4 AJ9
M_DA33 DQA1_0/DQA_32 EDCA1_2/QSA_6/RDQSA_6 M_DQSA7 M_DB33 DQB1_0/DQB_32 EDCB1_2/QSB_6/RDQSB_6 M_DQSB7
A18 D7 AB6 AM5
M_DA34 DQA1_1/DQA_33 EDCA1_3/QSA_7/RDQSA_7 M_DB34 DQB1_1/DQB_33 EDCB1_3/QSB_7/RDQSB_7
F18 AB1
M_DA35 DQA1_2/DQA_34 M_DQSA#0 M_DB35 DQB1_2/DQB_34 M_DQSB#0
D17 A34 AB3 G7
M_DA36 DQA1_3/DQA_35 DDBIA0_0/QSA_0B/WDQSA_0 M_DQSA#1 M_DB36 DQB1_3/DQB_35 DDBIB0_0/QSB_0B/WDQSB_0 M_DQSB#1
A16 E30 AD6 K1
M_DA37 DQA1_4/DQA_36 DDBIA0_1/QSA_1B/WDQSA_1 M_DQSA#2 M_DB37 DQB1_4/DQB_36 DDBIB0_1/QSB_1B/WDQSB_1 M_DQSB#2
F16 E26 AD1 P1
M_DA38 DQA1_5/DQA_37 DDBIA0_2/QSA_2B/WDQSA_2 M_DQSA#3 M_DB38 DQB1_5/DQB_37 DDBIB0_2/QSB_2B/WDQSB_2 M_DQSB#3
D15 C20 AD3 W4
M_DA39 DQA1_6/DQA_38 DDBIA0_3/QSA_3B/WDQSA_3 M_DQSA#4 M_DB39 DQB1_6/DQB_38 DDBIB0_3/QSB_3B/WDQSB_3 M_DQSB#4
E14 C16 AD5 AC4
M_DA40 DQA1_7/DQA_39 DDBIA1_0/QSA_4B/WDQSA_4 M_DQSA#5 M_DB40 DQB1_7/DQB_39 DDBIB1_0/QSB_4B/WDQSB_4 M_DQSB#5
F14 C12 AF1 AH3
M_DA41 DQA1_8/DQA_40 DDBIA1_1/QSA_5B/WDQSA_5 M_DQSA#6 M_DB41 DQB1_8/DQB_40 DDBIB1_1/QSB_5B/WDQSB_5 M_DQSB#6
D13 J11 AF3 AJ8
M_DA42 DQA1_9/DQA_41 DDBIA1_2/QSA_6B/WDQSA_6 M_DQSA#7 M_DB42 DQB1_9/DQB_41 DDBIB1_2/QSB_6B/WDQSB_6 M_DQSB#7
F12 F8 AF6 AM3
M_DA43 DQA1_10/DQA_42 DDBIA1_3/QSA_7B/WDQSA_7 M_DB43 DQB1_10/DQB_42 DDBIB1_3/QSB_7B/WDQSB_7
A12 AG4
M_DA44 DQA1_11/DQA_43 M_DB44 DQB1_11/DQB_43
D11 J21 VRAM_ODTA0 23 AH5 T7 VRAM_ODTB0 24
M_DA45 DQA1_12/DQA_44 ADBIA0/ODTA0 M_DB45 DQB1_12/DQB_44 ADBIB0/ODTB0
F10 G19 VRAM_ODTA1 23 AH6 W7 VRAM_ODTB1 24
M_DA46 DQA1_13/DQA_45 ADBIA1/ODTA1 M_DB46 DQB1_13/DQB_45 ADBIB1/ODTB1
C A10 AJ4 C
M_DA47 DQA1_14/DQA_46 M_DB47 DQB1_14/DQB_46
C10 H27 M_CLKA0 23 AK3 L9 M_CLKB0 24
M_DA48 DQA1_15/DQA_47 CLKA0 M_DB48 DQB1_15/DQB_47 CLKB0
G13 G27 M_CLKA#0 23 AF8 L8 M_CLKB#0 24
M_DA49 DQA1_16/DQA_48 CLKA0B M_DB49 DQB1_16/DQB_48 CLKB0B
H13 AF9
M_DA50 DQA1_17/DQA_49 M_DB50 DQB1_17/DQB_49
J13 J14 M_CLKA1 23 AG8 AD8 M_CLKB1 24
M_DA51 DQA1_18/DQA_50 CLKA1 M_DB51 DQB1_18/DQB_50 CLKB1
H11 H14 M_CLKA#1 23 AG7 AD7 M_CLKB#1 24
M_DA52 DQA1_19/DQA_51 CLKA1B M_DB52 DQB1_19/DQB_51 CLKB1B
G10 AK9
M_DA53 DQA1_20/DQA_52 M_DB53 DQB1_20/DQB_52
G8 K23 M_RASA#0 23 AL7 T10 M_RASB#0 24
M_DA54 DQA1_21/DQA_53 RASA0B M_DB54 DQB1_21/DQB_53 RASB0B
K9 K19 M_RASA#1 23 AM8 Y10 M_RASB#1 24
M_DA55 DQA1_22/DQA_54 RASA1B M_DB55 DQB1_22/DQB_54 RASB1B
K10 AM7
M_DA56 DQA1_23/DQA_55 M_DB56 DQB1_23/DQB_55
G9 K20 M_CASA#0 23 AK1 W10 M_CASB#0 24
M_DA57 DQA1_24/DQA_56 CASA0B M_DB57 DQB1_24/DQB_56 CASB0B
A8 K17 M_CASA#1 23 AL4 AA10 M_CASB#1 24
M_DA58 DQA1_25/DQA_57 CASA1B M_DB58 DQB1_25/DQB_57 CASB1B
C8 AM6
M_DA59 DQA1_26/DQA_58 M_DB59 DQB1_26/DQB_58
E8 K24 M_CSA0#_0 23 AM1 P10 M_CSB0#_0 24
M_DA60 DQA1_27/DQA_59 CSA0B_0 M_DB60 DQB1_27/DQB_59 CSB0B_0
A6 K27 AN4 L10
M_DA61 DQA1_28/DQA_60 CSA0B_1 M_DB61 DQB1_28/DQB_60 CSB0B_1
C6 AP3
M_DA62 DQA1_29/DQA_61 M_DB62 DQB1_29/DQB_61
E6 M13 M_CSA1#_0 23 AP1 AD10 M_CSB1#_0 24
M_DA63 DQA1_30/DQA_62 CSA1B_0 M_DB63 DQB1_30/DQB_62 CSB1B_0
A5 K16 AP5 AC10
DQA1_31/DQA_63 CSA1B_1 DQB1_31/DQB_63 CSB1B_1
+VDD_MEM15_REFDA L18 K21 U10
MVREFDA CKEA0 M_CKEA0 23 CKEB0 M_CKEB0 24
+VDD_MEM15_REFSA L20 J20 +VDD_MEM15_REFDB Y12 AA11
MVREFSA CKEA1 M_CKEA1 23 MVREFDB CKEB1 M_CKEB1 24
+VDD_MEM15_REFSB AA12
MVREFSB
L27 K26 M_WEA#0 23 N10 M_WEB#0 24
MEM_CALRN0 WEA0B WEB0B
N12 L15 M_WEA#1 23 AB11 M_WEB#1 24
MEM_CALRN1 WEA1B WEB1B
AG12
MEM_CALRN2 DIS@
M12 H23 M_MAA13 RV66 1 2 TESTEN AD28 T8 M_MAB13
RV67 MEM_CALRP1 MAA0_8 M_MAA14 TESTEN MAB0_8 M_MAB14
1 DIS@ 2 120_0402_1% M27 J19 1K_0402_5% W8
MEM_CALRP0 MAA1_8 MAB1_8
AH12 AK10

GDDR5
MEM_CALRP2 CLKTESTA DRAM_RST#_R
GDDR5

AL10 AH11
CLKTESTB DRAM_RST

216-0833000-A11-THAMES-XT-M2_FCBGA962~D
216-0833000-A11-THAMES-XT-M2_FCBGA962~D DIS@
B DIS@ B

1
This basic topology should be used for DRAM_RST for DDR3/GDDR5.These @DIS@ @DIS@
CV126 CV127
Capacitors and Resistor values are an example only. The Series R and 0.1U_0402_16V7K 0.1U_0402_16V7K

2
|| Cap values will depend on the DRAM load and will have to be route 50ohms single-ended/100ohms diff
calculated for different Memory ,DRAM Load and board to pass Reset and keep short

1
Signal Spec. Debug only, for clock observation, if not needed, DNI
@DIS@ @DIS@
Place all these components very close to GPU (Within RV68 RV69 5mil 5mil
25mm) and keep all component close to each Other (within 51.1_0402_1% 51.1_0402_1%
5mm) except Rser2

2
+MEM_GFX
1

RV70
4.7K_0402_5% +MEM_GFX +MEM_GFX
@DIS@
2

1
RV71 RV72
40.2_0402_1% 40.2_0402_1%
+MEM_GFX +MEM_GFX 1 RV73 2 1 RV74 2 DRAM_RST#_R DIS@ DIS@
23,24 DRAM_RST#
51.1_0402_1% 10_0402_1%

2
DIS@ DIS@
1

+VDD_MEM15_REFDB +VDD_MEM15_REFSB
2

RV75 RV76
1

40.2_0402_1% 40.2_0402_1% DIS@ DIS@ 1 1

1
DIS@ DIS@ CV128 RV77 CV129 CV130
120P_0402_50V9 4.99K_0402_1% RV78 1U_0402_6.3V6K RV79 1U_0402_6.3V6K
2

A 100_0402_1% DIS@ 100_0402_1% DIS@ A

1

+VDD_MEM15_REFDA +VDD_MEM15_REFSA 2 DIS@ 2

DIS@

2
1 1
1

CV131 CV132
RV80 1U_0402_6.3V6K RV81 1U_0402_6.3V6K
100_0402_1% DIS@ 100_0402_1% DIS@
DIS@ 2 DIS@ 2
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/03/03 Deciphered Date 2015/03/03 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Venus XTX(6/8)MEM Interface
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B131P
Date: Tuesday, March 04, 2014 Sheet 22 of 52
5 4 3 2 1
 5 4 3 2 1

M_DA[63..0]
22 M_DA[63..0]
U14 U15 U16 U17
M_MAA[14..0]
22 M_MAA[14..0] VREFC_A56 M8 M_DA20 VREFD_Q56 M_DA27 VREFC_A78 M_DA37 VREFD_Q78 M_DA55
VREFCA DQL0 E3 M8 VREFCA DQL0 E3 M8 VREFCA DQL0 E3 M8 VREFCA DQL0 E3
M_DQMA[7..0] VREFD_Q56 H1 F7 M_DA21 VREFC_A56 H1 F7 M_DA24 VREFD_Q78 H1 F7 M_DA38 VREFC_A78 H1 F7 M_DA52
22 M_DQMA[7..0] VREFDQ DQL1 M_DA19 VREFDQ DQL1 M_DA31 VREFDQ DQL1 M_DA34 VREFDQ DQL1 M_DA50
DQL2 F2 DQL2 F2 DQL2 F2 DQL2 F2
M_DQSA[7..0] M_MAA0 N3 F8 M_DA18 M_MAA0 N3 F8 M_DA25 M_MAA0 N3 F8 M_DA35 M_MAA0 N3 F8 M_DA54
22 M_DQSA[7..0] A0 DQL3 A0 DQL3 A0 DQL3 A0 DQL3
M_MAA1 P7 H3 M_DA22 M_MAA1 P7 H3 M_DA26 M_MAA1 P7 H3 M_DA33 M_MAA1 P7 H3 M_DA48
M_DQSA#[7..0] M_MAA2 A1 DQL4 M_DA17 M_MAA2 A1 DQL4 M_DA28 M_MAA2 A1 DQL4 M_DA32 M_MAA2 A1 DQL4 M_DA53
22 M_DQSA#[7..0] P3 A2 DQL5 H8 P3 A2 DQL5 H8 P3 A2 DQL5 H8 P3 A2 DQL5 H8
M_MAA3 N2 G2 M_DA23 M_MAA3 N2 G2 M_DA29 M_MAA3 N2 G2 M_DA39 M_MAA3 N2 G2 M_DA49
M_MAA4 A3 DQL6 M_DA16 M_MAA4 A3 DQL6 M_DA30 M_MAA4 A3 DQL6 M_DA36 M_MAA4 A3 DQL6 M_DA51
P8 H7 P8 H7 P8 H7 P8 H7
M_MAA5 A4 DQL7 M_MAA5 A4 DQL7 M_MAA5 A4 DQL7 M_MAA5 A4 DQL7
P2 P2 P2 P2
M_MAA6 A5 M_MAA6 A5 M_MAA6 A5 M_MAA6 A5
R8 R8 R8 R8
D M_MAA7 A6 M_DA1 M_MAA7 A6 M_DA15 M_MAA7 A6 M_DA40 M_MAA7 A6 M_DA61 D
R2 D7 R2 D7 R2 D7 R2 D7
M_MAA8 A7 DQU0 M_DA7 M_MAA8 A7 DQU0 M_DA10 M_MAA8 A7 DQU0 M_DA47 M_MAA8 A7 DQU0 M_DA59
T8 C3 T8 C3 T8 C3 T8 C3
M_MAA9 A8 DQU1 M_DA0 M_MAA9 A8 DQU1 M_DA12 M_MAA9 A8 DQU1 M_DA43 M_MAA9 A8 DQU1 M_DA63
R3 C8 R3 C8 R3 C8 R3 C8
M_MAA10 A9 DQU2 M_DA6 M_MAA10 A9 DQU2 M_DA11 M_MAA10 A9 DQU2 M_DA41 M_MAA10 A9 DQU2 M_DA56
L7 C2 L7 C2 L7 C2 L7 C2
M_MAA11 A10/AP DQU3 M_DA3 M_MAA11 A10/AP DQU3 M_DA14 M_MAA11 A10/AP DQU3 M_DA46 M_MAA11 A10/AP DQU3 M_DA60
R7 A7 R7 A7 R7 A7 R7 A7
M_MAA12 A11 DQU4 M_DA4 M_MAA12 A11 DQU4 M_DA9 M_MAA12 A11 DQU4 M_DA45 M_MAA12 A11 DQU4 M_DA57
N7 A2 N7 A2 N7 A2 N7 A2
M_MAA13 A12 DQU5 M_DA2 M_MAA13 A12 DQU5 M_DA13 M_MAA13 A12 DQU5 M_DA44 M_MAA13 A12 DQU5 M_DA62
T3 B8 T3 B8 T3 B8 T3 B8
M_MAA14 A13 DQU6 M_DA5 M_MAA14 A13 DQU6 M_DA8 M_MAA14 A13 DQU6 M_DA42 M_MAA14 A13 DQU6 M_DA58
T7 A3 T7 A3 T7 A3 T7 A3
A14 DQU7 A14 DQU7 A14 DQU7 A14 DQU7
M7 M7 M7 M7
A15/BA3 +MEM_GFX A15/BA3 +MEM_GFX A15/BA3 +MEM_GFX A15/BA3 +MEM_GFX

M_A_BA0 M2 B2 M_A_BA0 M2 B2 M_A_BA0 M2 B2 M_A_BA0 M2 B2

22 M_A_BA0 M_A_BA1 N8 BA0 VDD M_A_BA1 N8 BA0 VDD M_A_BA1 N8 BA0 VDD M_A_BA1 N8 BA0 VDD
22 M_A_BA1 BA1 VDD D9 BA1 VDD D9 BA1 VDD D9 BA1 VDD D9
M_A_BA2 M3 G7 M_A_BA2 M3 G7 M_A_BA2 M3 G7 M_A_BA2 M3 G7
22 M_A_BA2 BA2 VDD BA2 VDD BA2 VDD BA2 VDD
VDD K2 VDD K2 VDD K2 VDD K2
VDD K8 VDD K8 VDD K8 VDD K8
VDD N1 VDD N1 VDD N1 VDD N1
M_CLKA0 J7 N9 M_CLKA0 J7 N9 M_CLKA1 J7 N9 M_CLKA1 J7 N9
22 M_CLKA0 M_CLKA#0 K7 CK VDD M_CLKA#0 K7 CK VDD 22 M_CLKA1 M_CLKA#1 K7 CK VDD M_CLKA#1 K7 CK VDD
22 M_CLKA#0 CK VDD R1 CK VDD R1 22 M_CLKA#1 CK VDD R1 CK VDD R1
M_CKEA0 K9 R9 M_CKEA0 K9 R9 M_CKEA1 K9 R9 M_CKEA1 K9 R9
22 M_CKEA0 CKE/CKE0 VDD CKE/CKE0 VDD 22 M_CKEA1 CKE/CKE0 VDD CKE/CKE0 VDD
+MEM_GFX +MEM_GFX +MEM_GFX +MEM_GFX

VRAM_ODTA0
K1 A1 VRAM_ODTA0
K1 A1 VRAM_ODTA1K1 A1 VRAM_ODTA1K1 A1
22 VRAM_ODTA0 M_CSA0#_0L2 ODT/ODT0 VDDQ M_CSA0#_0L2 ODT/ODT0 VDDQ 22 VRAM_ODTA1 M_CSA1#_0 L2 ODT/ODT0 VDDQ M_CSA1#_0 L2 ODT/ODT0 VDDQ
22 M_CSA0#_0 CS/CS0 VDDQ A8 CS/CS0 VDDQ A8 22 M_CSA1#_0 CS/CS0 VDDQ A8 CS/CS0 VDDQ A8
M_RASA#0 J3 C1 M_RASA#0 J3 C1 M_RASA#1 J3 C1 M_RASA#1 J3 C1
22 M_RASA#0 M_CASA#0 K3 RAS VDDQ M_CASA#0 K3 RAS VDDQ 22 M_RASA#1 M_CASA#1 K3 RAS VDDQ M_CASA#1 K3 RAS VDDQ
22 M_CASA#0 CAS VDDQ C9 CAS VDDQ C9 22 M_CASA#1 CAS VDDQ C9 CAS VDDQ C9
M_WEA#0 L3 D2 M_WEA#0 L3 D2 M_WEA#1 L3 D2 M_WEA#1 L3 D2
22 M_WEA#0 WE VDDQ WE VDDQ 22 M_WEA#1 WE VDDQ WE VDDQ
VDDQ E9 VDDQ E9 VDDQ E9 VDDQ E9
VDDQ F1 VDDQ F1 VDDQ F1 VDDQ F1
M_DQSA2 F3 H2 M_DQSA3 F3 H2 M_DQSA4 F3 H2 M_DQSA6 F3 H2
M_DQSA0 DQSL VDDQ M_DQSA1 DQSL VDDQ M_DQSA5 DQSL VDDQ M_DQSA7 DQSL VDDQ
C7 DQSU VDDQ H9 C7 DQSU VDDQ H9 C7 DQSU VDDQ H9 C7 DQSU VDDQ H9
C C
M_DQMA2 E7 A9 M_DQMA3 E7 A9 M_DQMA4 E7 A9 M_DQMA6 E7 A9
M_DQMA0 DML VSS M_DQMA1 DML VSS M_DQMA5 DML VSS M_DQMA7 DML VSS
D3 DMU VSS B3 D3 DMU VSS B3 D3 DMU VSS B3 D3 DMU VSS B3
VSS E1 VSS E1 VSS E1 VSS E1
VSS G8 VSS G8 VSS G8 VSS G8
M_DQSA#2 G3 J2 M_DQSA#3 G3 J2 M_DQSA#4 G3 J2 M_DQSA#6 G3 J2
M_DQSA#0 DQSL VSS M_DQSA#1 DQSL VSS M_DQSA#5 DQSL VSS M_DQSA#7 DQSL VSS
B7 DQSU VSS J8 B7 DQSU VSS J8 B7 DQSU VSS J8 B7 DQSU VSS J8
M1 M1 M1 M1
VSS VSS VSS VSS
M9 M9 M9 M9
VSS VSS VSS VSS
P1 P1 P1 P1
DRAM_RST# T2 VSS DRAM_RST# T2 VSS DRAM_RST# T2 VSS DRAM_RST# T2 VSS
22,24 DRAM_RST# P9 P9 P9 P9
RESET VSS RESET VSS RESET VSS RESET VSS
T1 T1 T1 T1
VSS VSS VSS VSS
L8 T9 L8 T9 L8 T9 L8 T9
ZQ/ZQ0 VSS ZQ/ZQ0 VSS ZQ/ZQ0 VSS ZQ/ZQ0 VSS
1

1
J1 B1 J1 B1 J1 B1 J1 B1
R113 NC/ODT1 VSSQ R114 NC/ODT1 VSSQ R115 NC/ODT1 VSSQ R116 NC/ODT1 VSSQ
L1 B9 L1 B9 L1 B9 L1 B9
243_0402_1% NC/CS1 VSSQ 243_0402_1% NC/CS1 VSSQ 243_0402_1% NC/CS1 VSSQ 243_0402_1% NC/CS1 VSSQ
J9 D1 J9 D1 J9 D1 J9 D1
DIS@ NC/CE1 VSSQ DIS@ NC/CE1 VSSQ DIS@ NC/CE1 VSSQ DIS@ NC/CE1 VSSQ
L9 D8 L9 D8 L9 D8 L9 D8
NCZQ1 VSSQ NCZQ1 VSSQ NCZQ1 VSSQ NCZQ1 VSSQ
E2 E2 E2 E2
2

2
VSSQ VSSQ VSSQ VSSQ
E8 E8 E8 E8
VSSQ VSSQ VSSQ VSSQ
F9 F9 F9 F9
VSSQ VSSQ VSSQ VSSQ
G1 G1 G1 G1
VSSQ VSSQ VSSQ VSSQ
G9 G9 G9 G9
VSSQ VSSQ VSSQ VSSQ
96-BALL 96-BALL 96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
K4W2G1646E-BC1A K4W2G1646E-BC1A K4W2G1646E-BC1A K4W2G1646E-BC1A
@ @ @ @

B DIS@ B
M_CLKA0 1 2
R117 40.2_0402_1%
+MEM_GFX +MEM_GFX +MEM_GFX +MEM_GFX
DIS@
M_CLKA#0 1 2
1

1
R118 40.2_0402_1%
1 R119 R120 DIS@ R121 R122
C150 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% DIS@
0.01U_0402_16V7K DIS@ DIS@ 4.99K_0402_1%
DIS@
2

2
2
VREFD_Q56 VREFC_A56 VREFC_A78 VREFD_Q78
1

0.1U_0402_16V7K
DIS@ C154

DIS@ C151

DIS@ C152

DIS@ C153
1 1 1 1
0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K
R123 R127 R124 R125
DIS@ 4.99K_0402_1% 4.99K_0402_1% DIS@ DIS@
M_CLKA1 1 2 DIS@ DIS@ 4.99K_0402_1% 4.99K_0402_1%
R126 40.2_0402_1% 2 2 2 2
2

2
DIS@
M_CLKA#1 1 2
R128 40.2_0402_1%1
C155 +MEM_GFX
0.01U_0402_16V7K +MEM_GFX
DIS@ 1U_0402_6.3V6K 1U_0402_6.3V6K
2 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K

DIS@
DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@
10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K

DIS@
+MEM_GFX
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

DIS@

DIS@
DIS@

DIS@

DIS@
DIS@

DIS@

DIS@

DIS@

C172

C173

C174

C175

C176

C177

C178

C179

C180

C181
DIS@
1 1 1 1 1 1 1 1 1 1

C162

C163

C164

C165

C166

C167

C168

C169

C170

C171
ref Mars_M2 recommand C156
DIS@
C157
DIS@
C158
DIS@
C159
DIS@
C160
DIS@
C161
DIS@
A 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 A
10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M 2 2 2 2 2 2 2 2 2 2 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K
VRAM P/N : 1U_0402_6.3V6K 1U_0402_6.3V6K

Hynix : SA00003YO40 (S IC D3 128M16 H5TQ2G63BFR-11C 96P C38A! )

Samsung : SA000047Q30 (S IC D3 128M16 K4W2G1646C-HC11 96P C38A!) Security Classification Compal Secret Data Compal Electronics, Inc.
update VRAM PN Issued Date 2014/03/03 Deciphered Date 2015/03/03 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Venus XTX(7/8) DDR3 VRAM_A
Size Document Number Rev
Place across each VDDIO-GND plane seam AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B131P
Date: Tuesday, March 04, 2014 Sheet 23 of 52
5 4 3 2 1
 5 4 3 2 1

M_DB[63..0]
22 M_DB[63..0]
U18 U19 U20 U21
M_MAB[14..0]
22 M_MAB[14..0] VREFC_A12 M8 M_DB18 VREFD_Q12 M_DB25 VREFC_A34 M_DB37 VREFD_Q34 M_DB53
VREFCA DQL0 E3 M8 VREFCA DQL0 E3 M8 VREFCA DQL0 E3 M8 VREFCA DQL0 E3
M_DQMB[7..0] VREFD_Q12 H1 F7 M_DB19 VREFC_A12 H1 F7 M_DB27 VREFD_Q34 H1 F7 M_DB39 VREFC_A34 H1 F7 M_DB51
22 M_DQMB[7..0] VREFDQ DQL1 M_DB20 VREFDQ DQL1 M_DB28 VREFDQ DQL1 M_DB34 VREFDQ DQL1 M_DB54
DQL2 F2 DQL2 F2 DQL2 F2 DQL2 F2
M_DQSB[7..0] M_MAB0 N3 F8 M_DB16 M_MAB0 N3 F8 M_DB26 M_MAB0 N3 F8 M_DB33 M_MAB0 N3 F8 M_DB50
22 M_DQSB[7..0] M_MAB1 A0 DQL3 M_DB21 M_MAB1 A0 DQL3 M_DB30 M_MAB1 A0 DQL3 M_DB32 M_MAB1 A0 DQL3 M_DB52
P7 A1 DQL4 H3 P7 A1 DQL4 H3 P7 A1 DQL4 H3 P7 A1 DQL4 H3
M_DQSB#[7..0] M_MAB2 P3 H8 M_DB17 M_MAB2 P3 H8 M_DB29 M_MAB2 P3 H8 M_DB36 M_MAB2 P3 H8 M_DB49
22 M_DQSB#[7..0] M_MAB3 A2 DQL5 M_DB22 M_MAB3 A2 DQL5 M_DB31 M_MAB3 A2 DQL5 M_DB35 M_MAB3 A2 DQL5 M_DB55
N2 A3 DQL6 G2 N2 A3 DQL6 G2 N2 A3 DQL6 G2 N2 A3 DQL6 G2
M_MAB4 P8 H7 M_DB23 M_MAB4 P8 H7 M_DB24 M_MAB4 P8 H7 M_DB38 M_MAB4 P8 H7 M_DB48
M_MAB5 A4 DQL7 M_MAB5 A4 DQL7 M_MAB5 A4 DQL7 M_MAB5 A4 DQL7
P2 P2 P2 P2
M_MAB6 A5 M_MAB6 A5 M_MAB6 A5 M_MAB6 A5
R8 R8 R8 R8
M_MAB7 A6 M_DB2 M_MAB7 A6 M_DB15 M_MAB7 A6 M_DB45 M_MAB7 A6 M_DB57
R2 D7 R2 D7 R2 D7 R2 D7
D M_MAB8 A7 DQU0 M_DB7 M_MAB8 A7 DQU0 M_DB8 M_MAB8 A7 DQU0 M_DB40 M_MAB8 A7 DQU0 M_DB62 D
T8 C3 T8 C3 T8 C3 T8 C3
M_MAB9 A8 DQU1 M_DB1 M_MAB9 A8 DQU1 M_DB14 M_MAB9 A8 DQU1 M_DB47 M_MAB9 A8 DQU1 M_DB56
R3 C8 R3 C8 R3 C8 R3 C8
M_MAB10 A9 DQU2 M_DB6 M_MAB10 A9 DQU2 M_DB10 M_MAB10 A9 DQU2 M_DB42 M_MAB10 A9 DQU2 M_DB61
L7 C2 L7 C2 L7 C2 L7 C2
M_MAB11 A10/AP DQU3 M_DB3 M_MAB11 A10/AP DQU3 M_DB12 M_MAB11 A10/AP DQU3 M_DB44 M_MAB11 A10/AP DQU3 M_DB59
R7 A7 R7 A7 R7 A7 R7 A7
M_MAB12 A11 DQU4 M_DB5 M_MAB12 A11 DQU4 M_DB9 M_MAB12 A11 DQU4 M_DB41 M_MAB12 A11 DQU4 M_DB63
N7 A2 N7 A2 N7 A2 N7 A2
M_MAB13 A12 DQU5 M_DB0 M_MAB13 A12 DQU5 M_DB13 M_MAB13 A12 DQU5 M_DB46 M_MAB13 A12 DQU5 M_DB58
T3 B8 T3 B8 T3 B8 T3 B8
M_MAB14 A13 DQU6 M_DB4 M_MAB14 A13 DQU6 M_DB11 M_MAB14 A13 DQU6 M_DB43 M_MAB14 A13 DQU6 M_DB60
T7 A3 T7 A3 T7 A3 T7 A3
A14 DQU7 A14 DQU7 A14 DQU7 A14 DQU7
M7 M7 M7 M7
A15/BA3 +MEM_GFX A15/BA3 +MEM_GFX A15/BA3 +MEM_GFX A15/BA3 +MEM_GFX

M_B_BA0 M2 B2 M_B_BA0 M2 B2 M_B_BA0 M2 B2 M_B_BA0 M2 B2

22 M_B_BA0 M_B_BA1 N8 BA0 VDD M_B_BA1 N8 BA0 VDD M_B_BA1 N8 BA0 VDD M_B_BA1 N8 BA0 VDD
22 M_B_BA1 BA1 VDD D9 BA1 VDD D9 BA1 VDD D9 BA1 VDD D9
M_B_BA2 M3 G7 M_B_BA2 M3 G7 M_B_BA2 M3 G7 M_B_BA2 M3 G7
22 M_B_BA2 BA2 VDD BA2 VDD BA2 VDD BA2 VDD
VDD K2 VDD K2 VDD K2 VDD K2
VDD K8 VDD K8 VDD K8 VDD K8
VDD N1 VDD N1 VDD N1 VDD N1
M_CLKB0 J7 N9 M_CLKB0 J7 N9 M_CLKB1 J7 N9 M_CLKB1 J7 N9
22 M_CLKB0 M_CLKB#0 K7 CK VDD M_CLKB#0 CK VDD 22 M_CLKB1 M_CLKB#1 K7 CK VDD M_CLKB#1 CK VDD
22 M_CLKB#0 CK VDD R1 K7
CK VDD R1 22 M_CLKB#1 CK VDD R1 K7
CK VDD R1
M_CKEB0 K9 R9 M_CKEB0 K9 R9 M_CKEB1 K9 R9 M_CKEB1 K9 R9
22 M_CKEB0 CKE/CKE0 VDD CKE/CKE0 VDD 22 M_CKEB1 CKE/CKE0 VDD CKE/CKE0 VDD
+MEM_GFX +MEM_GFX +MEM_GFX +MEM_GFX

VRAM_ODTB0
K1 A1 VRAM_ODTB0K1 A1 VRAM_ODTB1K1 A1 VRAM_ODTB1K1 A1
22 VRAM_ODTB0 M_CSB0#_0L2 ODT/ODT0 VDDQ M_CSB0#_0L2 ODT/ODT0 VDDQ 22 VRAM_ODTB1 M_CSB1#_0 L2 ODT/ODT0 VDDQ M_CSB1#_0 L2 ODT/ODT0 VDDQ
22 M_CSB0#_0 CS/CS0 VDDQ A8 CS/CS0 VDDQ A8 22 M_CSB1#_0 CS/CS0 VDDQ A8 CS/CS0 VDDQ A8
M_RASB#0 J3 C1 M_RASB#0 J3 C1 M_RASB#1 J3 C1 M_RASB#1 J3 C1
22 M_RASB#0 M_CASB#0 K3 RAS VDDQ M_CASB#0 K3 RAS VDDQ 22 M_RASB#1 M_CASB#1 K3 RAS VDDQ M_CASB#1 K3 RAS VDDQ
22 M_CASB#0 CAS VDDQ C9 CAS VDDQ C9 22 M_CASB#1 CAS VDDQ C9 CAS VDDQ C9
M_WEB#0 L3 D2 M_WEB#0 L3 D2 M_WEB#1 L3 D2 M_WEB#1 L3 D2
22 M_WEB#0 WE VDDQ WE VDDQ 22 M_WEB#1 WE VDDQ WE VDDQ
VDDQ E9 VDDQ E9 VDDQ E9 VDDQ E9
VDDQ F1 VDDQ F1 VDDQ F1 VDDQ F1
M_DQSB2 F3 H2 M_DQSB3 F3 H2 M_DQSB4 F3 H2 M_DQSB6 F3 H2
M_DQSB0 DQSL VDDQ M_DQSB1 DQSL VDDQ M_DQSB5 DQSL VDDQ M_DQSB7 DQSL VDDQ
C7 DQSU VDDQ H9 C7 DQSU VDDQ H9 C7 DQSU VDDQ H9 C7 DQSU VDDQ H9

C M_DQMB2 M_DQMB3 M_DQMB4 M_DQMB6 C

E7 DML VSS A9 E7 DML VSS A9 E7 DML VSS A9 E7 DML VSS A9
M_DQMB0 D3 B3 M_DQMB1 D3 B3 M_DQMB5 D3 B3 M_DQMB7 D3 B3
DMU VSS DMU VSS DMU VSS DMU VSS
VSS E1 VSS E1 VSS E1 VSS E1
VSS G8 VSS G8 VSS G8 VSS G8
M_DQSB#2 G3 J2 M_DQSB#3 G3 J2 M_DQSB#4 G3 J2 M_DQSB#6 G3 J2
M_DQSB#0 DQSL VSS M_DQSB#1 DQSL VSS M_DQSB#5 DQSL VSS M_DQSB#7 DQSL VSS
B7 DQSU VSS J8 B7 DQSU VSS J8 B7 DQSU VSS J8 B7 DQSU VSS J8
VSS M1 VSS M1 VSS M1 VSS M1
M9 M9 M9 M9
VSS VSS VSS VSS
P1 P1 P1 P1
DRAM_RST# T2 VSS DRAM_RST# T2 VSS DRAM_RST# T2 VSS DRAM_RST# T2 VSS
22,23 DRAM_RST# P9 P9 P9 P9
RESET VSS RESET VSS RESET VSS RESET VSS
T1 T1 T1 T1
VSS VSS VSS VSS
L8 T9 L8 T9 L8 T9 L8 T9
ZQ/ZQ0 VSS ZQ/ZQ0 VSS ZQ/ZQ0 VSS ZQ/ZQ0 VSS
1

1
J1 B1 J1 B1 J1 B1 J1 B1
R129 NC/ODT1 VSSQ R130 NC/ODT1 VSSQ R131 NC/ODT1 VSSQ R132 NC/ODT1 VSSQ
L1 B9 L1 B9 L1 B9 L1 B9
243_0402_1% NC/CS1 VSSQ 243_0402_1% NC/CS1 VSSQ 243_0402_1% NC/CS1 VSSQ 243_0402_1% NC/CS1 VSSQ
J9 D1 J9 D1 J9 D1 J9 D1
DIS@ NC/CE1 VSSQ DIS@ NC/CE1 VSSQ DIS@ NC/CE1 VSSQ DIS@ NC/CE1 VSSQ
L9 D8 L9 D8 L9 D8 L9 D8
NCZQ1 VSSQ NCZQ1 VSSQ NCZQ1 VSSQ NCZQ1 VSSQ
E2 E2 E2 E2
2

2
VSSQ VSSQ VSSQ VSSQ
E8 E8 E8 E8
VSSQ VSSQ VSSQ VSSQ
F9 F9 F9 F9
VSSQ VSSQ VSSQ VSSQ
G1 G1 G1 G1
VSSQ VSSQ VSSQ VSSQ
G9 G9 G9 G9
VSSQ VSSQ VSSQ VSSQ
96-BALL 96-BALL 96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
K4W2G1646E-BC1A K4W2G1646E-BC1A K4W2G1646E-BC1A K4W2G1646E-BC1A
@ @ @ @

DIS@ +MEM_GFX +MEM_GFX

B M_CLKB0 +MEM_GFX +MEM_GFX B
1 2
R133 40.2_0402_1%

1
1

DIS@ DIS@ R135 R136

M_CLKB#0 1 2 R134 R138 4.99K_0402_1% DIS@
R137 40.2_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
1 DIS@ DIS@

2
C182
2

0.01U_0402_16V7K VREFC_A34 VREFD_Q34

DIS@ VREFD_Q12 VREFC_A12

1
2

0.1U_0402_16V7K
DIS@ C185

DIS@ C186
1 1
1

0.1U_0402_16V7K
DIS@ C183

DIS@ C184

1 1 R141 R142
0.1U_0402_16V7K

0.1U_0402_16V7K

R139 R140 DIS@ DIS@

4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
DIS@ DIS@ 2 2

2
DIS@ 2 2
2

M_CLKB1 1 2
R143 40.2_0402_1%

DIS@
M_CLKB#1 1 2
R144 40.2_0402_1%1
C187 +MEM_GFX
0.01U_0402_16V7K +MEM_GFX
ref 139-02 recommand 2
DIS@ 1U_0402_6.3V6K 1U_0402_6.3V6K
add off page 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K

DIS@
DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@
10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K

DIS@
+MEM_GFX
Park SCL recommand 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

DIS@

DIS@
DIS@

DIS@

DIS@
DIS@

DIS@

DIS@

DIS@

C204

C205

C206

C207

C208

C209

C210

C211

C212

C213
DIS@
1 1 1 1 1 1 1 1 1 1
pu 60.4 ohm to 1.5VGS

C194

C195

C196

C197

C198

C199

C200

C201

C202

C203
C188 C189 C190 C191 C192 C193
DIS@
0619 update 2
DIS@
2
DIS@
2
DIS@
2
DIS@
2
DIS@
2 2 2 2 2 2 2 2 2 2 2
A 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M 2 2 2 2 2 2 2 2 2 2 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K A
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K
VRAM P/N : 1U_0402_6.3V6K 1U_0402_6.3V6K

Hynix : SA00003YO40 (S IC D3 128M16 H5TQ2G63BFR-11C 96P C38A! )

Samsung : SA000047Q30 (S IC D3 128M16 K4W2G1646C-HC11 96P C38A!)
update VRAM PN
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/03/03 Deciphered Date 2015/03/03 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Venus XTX(8/8) DDR3 VRAM_B
Size Document Number Rev
Place across each VDDIO-GND plane seam AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B131P
Date: Tuesday, March 04, 2014 Sheet 24 of 52
5 4 3 2 1
 5 4 3 2 1

LCD POWER CIRCUIT

+LCDVDD
+3VS U22
W=80mils
W=80mils 2A +LCDVDD
0_0402_5%
2A OUT 1
5 IN
1 1 1
D @ R145 2 D
@ C214 +3VS_SS GND C215 C216
1 2 4 SS
0.1U_0402_16V7K 4.7U_0603_6.3V6K 0.1U_0402_16V7K
2 2 2
1 EN 3
SIV
C217 APL3512ABI-TRG_SOT23-5
1500P_0402_50V7K
2
8 PCH_ENVDD

C217 Resevre for APL3512A

R145 Resevre for G5243AT11U

@EMI@
R258 2 1 0_0402_5%

L24 @EMI@
10 USB20_N4 2 1 USB20_N4_L
2 1

10 USB20_P4 3 4 USB20_P4_L
3 4
DLW21HN900HQ2L_4P SIT eDP(FHD) + TOUCH + Camera
R255 2 1 0_0402_5%
@EMI@

JEDP1
C C
+3VS 1 1
30 TS_DISABLE# 2 2
T\ouch Screen 3 3
USB20_N4_L 4
USB20_P4_L 4
5 5
@EMI@ SDV 6
R254 6
2 1 0_0402_5% 9 PCH_GPIO87 7 7
+3VS_CMOS 8 8
L23 EMI@ USB20_N5_L 9
USB20_N5_L USB20_P5_L 9
10 USB20_N5 2 2 1 1 Camera 10 10
11 11
DMIC 12 12
10 USB20_P5 3 4 USB20_P5_L 13
3 4 27 DMIC_CLK 13
27 DMIC_DATA 14 14
DLW21HN900HQ2L_4P +3VS 15
DMIC_DATA 15
+LCDVDD 16 16
R244 2 1 0_0402_5% 17
@EMI@ 17
18

220P_0402_50V7K
18
19 19

1
@EMI@ CA12
20 20
21 21
C223 1 2 0.1U_0402_16V7K EDP_CONN_AUXP 22
4 EDP_AUXP

2
C224 22
4 EDP_AUXN 1 2 0.1U_0402_16V7K EDP_CONN_AUXN 23 23
24 24
C218 1 2 0.1U_0402_16V7K EDP_CONN_TXN0 25
4 EDP_TXN0 25
C219 1 2 0.1U_0402_16V7K EDP_CONN_TXP0 26
4 EDP_TXP0 26
SVT CA12 close to JEDP1 27 27
eDP(FHD) C221 1 2 0.1U_0402_16V7K EDP_CONN_TXN1 28
SIV 4 EDP_TXN1 28
C222 1 2 0.1U_0402_16V7K EDP_CONN_TXP1 29
CMOS Camera @
4 EDP_TXP1
30
31
29
30
8 EDP_HPD 31
R148 1 2 0_0603_5% DISPOFF# 32 32
8 INVPWM 33 33
+3VS_CMOS 34
+3VS Q70 34
B 35 35
B
ME2301DC-G_SOT23-3 R2 INVPWR_B+
W=20mils W=20mils JP5 @
36 36 G1 41
W=80mils 37 37 G2 42
S

3 1 R1456 1 2 0_0603_5% B+ 1 2 1 2 38 43
1 2 38 G3
1 1 1090mA 39 39 G4 44
SVT JUMP_43X39 SVT 0_0805_5% 40 45
C1152 C1153 @ 40 G5
G

2 2
2

0.1U_0402_16V7K 10U_0603_6.3V6M ENBKL @ @ ACES_50398-04041-001

C225

C226
1 8
2 2 DISPOFF# 0.1U_0402_25V6K 0.1U_0402_25V6K CONN@
2 7
3 6 PCH_ENVDD
EDP_HPD SIT 1 1
4 5
R1458 150K_0402_5%
RP10 100K_8P4R_5%
30 CMOS_ON# SIT
1
C1155
0.1U_0402_16V7K
2

+3VS

@ SVT

5
U33
Fr\om PCH 2

P
8,30 ENBKL B
4 DISPOFF#
Y
Fr\om EC 30 BKOFF# 1 A

G
MC74VHC1G08DFT2G_SC70-5

3
DMIC_CLK

USB20_P4 USB20_P5_L
2
L30ESDL5V0C3-2 C/A SOT-23

USB20_N4 USB20_N5_L
R146
A A
33_0402_5% @EMI@ 1 2
R213 0_0402_5%
1
3

SIT
D3 D4
1
C220 @EMI@
@ESD@ @ESD@ 22P_0402_50V8J
Security Classification Compal Secret Data Compal Electronics, Inc.
1

2
L30ESDL5V0C3-2 C/A SOT-23 2014/03/03 2015/03/03 Title
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
eDP LCD / Camera / Touch
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B131P
Date: Tuesday, March 04, 2014 Sheet 25 of 52
5 4 3 2 1
 1 2 3 4 5

C230 C298 C230 C298

RTL8111GS L7 C232 C237 R147 C229 RTL8111G L7 C232 C237 R147 C229
+3_LAN Rising time (10%~90%) >1mS and <100mS
SWR mode O O O X X LDO mode X X X O O
+3VALW +3V_LAN
W=60mils J2 @ 370mA
1 1 2 2
Layout Notice : Place as close
JUMP_43X39
chip as possible.
A A

LDO@ +3V_LAN
R147 1 2 0_0603_5%
+3V_LAN +LAN_VDD10
L7 SWR@ W=60mils
+LAN_REGOUT 1 2 @ @

4.7U_0603_6.3V6K
C322

4.7U_0603_6.3V6K
C227

0.1U_0402_16V7K
C228

C238
GCLK (RG6 cl\ose t\o \Y3.1) W=60mils 2.2UH +-5% NLC252018T-2R2J-N

C231

1U_0402_6.3V6K

C233

0.1U_0402_16V7K

C234

0.1U_0402_16V7K

C235

0.1U_0402_16V7K

C236

0.1U_0402_16V7K

0.1U_0402_16V7K
2 1 1 1 1 1 1 1

1
1 2 XTLI
34 LAN_XTLI_GCLK
RG6 0_0402_5% SVT C298 SWR@ C237 SWR@ LDO@ SWR@ SWR@ @ @
4.7U_0603_6.3V6K 0.1U_0402_16V7K C229 C230 C232

2
1 0.1U_0402_16V7K 2 4.7U_0603_6.3V6K 2 2 2 2 2 2

0.1U_0402_16V7K
close to pin 22
These caps cl\ose t\o U23 : Pin 23
C239
( Sh\ould be place within 200 mils ) These c\omp\onents cl\ose t\o U23 : Pin 3,8,22,30 These caps cl\ose t\o U23 : Pin 11,32
15P_0402_50V8J
These c\omp\onents cl\ose t\o U23 : Pin 24 1uF reserved \on Pin 22 DVDD33
1 2 XTLI
1 LDO mode SWR mode
NOGCLK@
Y3
1
25MHZ_12PF_7V25000012
2 GND NOGCLK@

4 U23 +3VS
GND

2
B B
C242
15P_0402_50V8J 3

R149
XTLO
These caps cl\ose t\o U11
1 2
MDI0+ 1 17 PCIE_PRX_C_DTX_P3 C240 1 2 0.1U_0402_16V7K PCIE_PRX_DTX_P3 1K_0402_5%
MDIP0 HSOP PCIE_PRX_DTX_P3 10
NOGCLK@ MDI0- 2 18 PCIE_PRX_C_DTX_N3 C241 1 2 0.1U_0402_16V7K PCIE_PRX_DTX_N3
PCIE_PRX_DTX_N3 10

1
+LAN_VDD10 MDIN0 HSON
3 AVDD10 PERSTB 19 PLT_RST# 8,17,29,30,33
MDI1+ 4 20 ISOLATEB ISOLATEB
MDI1- MDIP1 ISOLATEB
5 MDIN1 LANWAKEB 21 PCIE_LAN_WAKE# 29,30

1
MDI2+ 6 22 +LAN_VDD10
MDI2- MDIP2 DVDD10 +3V_LAN R153
7 MDIN2 VDDREG 23
+LAN_VDD10 8 24 +LAN_REGOUT +3V_LAN 15K_0402_5%
MDI3+ AVDD10 REGOUT
9 MDIP3 LED2 25 1 T89
MDI3- 10 26 LED1_GPIO 1 @ 2

2
+3V_LAN MDIN3 LED1/GPIO RL17 10K_0402_5%
11 AVDD33 LED0 27 1 T90
12 28 XTLO
7,9 LANCLK_REQ# CLKREQB CKXTAL1
13 29 XTLI
10 PCIE_PTX_C_DRX_P3
14
HSIP CKXTAL2
30 +LAN_VDD10 R152 reserved GPIO pin
10 PCIE_PTX_C_DRX_N3 HSIN AVDD10
15 31 LAN_RSET 1 2
7 CLK_PCIE_LAN REFCLK_P RSET
16 32 +3V_LAN 2.49K_0402_1%
7 CLK_PCIE_LAN# REFCLK_N AVDD33
GND 33

RTL8111GUL-CG QFN 32P

SA00006ML10
JRJ1 CONN@

GND 12

D5 EMI@ 11
MDI1- GND
1 1 10 10
C 2 9 MDI3+ 10 C
TS1 MDI1+ 2 9 MDO0+ GND
3 3 8 8 1 PR1+
TCT 1 24 MCT 4 7 MDI3- 9

GND
TCT1 MCT1 4 7 MDO0- GND
5 5 6 6 2 PR1-
MDI0+ 2 23 MDO0+
TD1+ MX1+ RCLAMP3304N.TCT_SLP2626P10-10 MDO1+ 3

11
MDI0- MDO0- PR2+
3 TD1- MX1- 22 Place Close to TS1
R168 EMI@ MDO2+ 4 CHASSIS1_GND
PR3+
4 TCT2 MCT2 21 1 2 1 2
75_0805_5% CHASSIS1_GND MDO2- 5
C292 MDI1+ MDO1+ C290 PR3-
5 TD2 MX2+ 20
1 2 10P_0603_50V8-J MDO1- 6
MDI1- MDO1- PR2-
6 TD2- MX2- 19
0.01U_0402_16V7K MDO3+ 7 PR4+
7 TCT3 MCT3 18 2 1
D6 EMI@ MDO3- 8
MDI2+ MDO2+ DL2 MDI0- PR4-
8 TD3+ MX3+ 17 1 1 10 10
BS4200N-C-LV_SMB-F2 2 9 MDI2+
MDI2- MDO2- EMI@ SCV00001D00 MDI0+ 2 9
9 TD3- MX3- 16 3 3 8 8
4 7 MDI2- SANTA_130460-3

GND
4 7 DC231112261
10 TCT4 MCT4 15 5 5 6 6

MDI3+ 11 14 MDO3+ RCLAMP3304N.TCT_SLP2626P10-10

11
TD4+ MX4+
Place Close to TS1
MDI3- 12 13 MDO3-
TD4- MX4-

NS892407 1G
SP050006800
SIV (EMI suggestion)
SIV

D D

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/03/03 Deciphered Date 2015/03/03 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN_RTL8111G-CG
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B131P
Date: Tuesday, March 04, 2014 Sheet 26 of 52
1 2 3 4 5
 5 4 3 2 1

R159
1
0_0402_5%
2 +1.5VS_AVDD2 +3VS +3VDD_CODEC +IOVDD_CODEC +3VDD_CODEC
JACK_PLUG Delay circutis
+1.5VS
U1 @ +3VS +3VS
+3VS 1 5 R155 0_0603_5% R156 0_0603_5%
VIN VOUT

1U_0402_6.3V6K

1U_0603_10V6K
1 1 2 1 2

1
C344

33_0603_5%

33_0603_5%
3 1 SVT

1U_0402_6.3V6K
0.1U_0402_16V7K

0.1U_0402_16V7K
SHDN SIV

1
R249

R250

C253
1 1 @ @ JACK_SENSE#

1
0.01U_0402_16V7K
RA11 RA9

C245

C246

C247
4 2
2 @ BP GND
1 100K_0402_5% 100K_0402_5%
APE8800A-15Y5P_SOT23-5 2 @

2
2 2

C343

3
D
2 @ D
@ D
Place near Pin1 Place near Pin9 5 G QA5A
SVT @ S DMN66D0LDW-7_SOT363-6
QA5B

4
6
DMN66D0LDW-7_SOT363-6 D
600ohms @100MHz 2A 33 PLUG_IN# PLUG_IN# 1 2 2 G

@ S
P/N: SM01000EE00 RA8

1
Place near Pin25 10K_0402_5% 1 1
R157
+5VS 1 2 +5VS_PVDD @ @
CA11 CA10

0.1U_0402_16V7K

0.1U_0402_16V7K
4.7U_0603_6.3V6K
0_0805_5% 10U_0603_6.3V6M 2 2 10U_0603_6.3V6M
2 1 1 +5VS
+5VDDA_CODEC

C249

C250
C248
SVT
1 2 2
Place near Pin26
R158 0_0603_5%
1 2
+IOVDD_CODEC SIT

0.1U_0402_16V7K

4.7U_0603_6.3V6K
+3VDD_CODEC +1.5VS_AVDD2
1 1
SVT PLUG_IN# RA10 1 2 0_0402_5% JACK_SENSE#

C251

C252
2 2
Reserve for cancel Delay circutis
SVT

41

46

26

40
1

9
UA1

DVDD

DVDD-IO

PVDD1

PVDD2

AVDD1

AVDD2
Place near Pin40

22 +3VLP
LINE1-L(PORT-C-L) SPK_L- V0.2
C
21 LINE1-R(PORT-C-R) SPK-OUT-L- 43 C
42 SPK_L+
SPK-OUT-L+ +3VS
24
wide 40MIL 23
LINE2-L(PORT-E-L)
LINE2-R(PORT-E-R) SPK-OUT-R+ 45 SPK_R+

1 100K_0402_5%
44 SPK_R- EXT_MIC_SLEEVE
SPK-OUT-R-

R160
33 EXT_MIC_RING2 EXT_MIC_RING2 17 MIC2-L(PORT-F-L) /RING2

6
33 EXT_MIC_SLEEVE EXT_MIC_SLEEVE 18 MIC2-R(PORT-F-R) /SLEEVE

ME2N7002D1KW-G 2N SOT363-6
32 HP_OUTL HP_OUTL 33
HPOUT-L(PORT-I-L) HP_OUTR R161 @

Q4A
31 33 HP_OUTR 33

2
SIV (EMI suggestion) LINE1-VREFO-L HPOUT-R(PORT-I-R) 100K_0402_5%
30 LINE1-VREFO-R 2
EMI@ 10 HDA_SYNC_AUDIO HDA_SYNC_AUDIO 6

2
SYNC

3
RA13 1 2 0_0402_5% DMIC_DATA_R 2 6 HDA_BITCLK_AUDIO HDA_BITCLK_AUDIO 6
25 DMIC_DATA

1
DMIC_CLK_R GPIO0/DMIC-DATA BCLK
25 DMIC_CLK 1 2 3 GPIO1/DMIC-CLK

ME2N7002D1KW-G 2N SOT363-6
Q4B
L8 EMI@ SBY100505T-301Y-N
SIT HDA_SDOUT_AUDIO 6 HDA_RST_AUDIO# 1 2 5
RA2 2 0_0402_5% PDB HDA_SDOUT_AUDIO R162
30 EC_MUTE# 1 47 PDB ALC283-CG SDATA-OUT 5
1

HDA_RST_AUDIO# HDA_SDIN0_R RA3 2 33_0402_5% 10K_0402_5%

EMI@ C254

@EMI@ CA13

6 HDA_RST_AUDIO# 11 8 1 HDA_SDIN0 6 1
220P_0402_50V7K

220P_0402_50V7K

4
RESETB SDATA-IN

1U_0402_6.3V6K
C255
48 EMI@ RA12 1 2 @
SPDIF_OUT 33
2

PC_BEEP SPDIF-OUT/GPIO2 CHILISIN SBY100505T-301Y-N 0402 GNDA

12 PCBEEP 2
MONO-OUT 16 SIT (EMI suggestion)
JACK_SENSE# RA4 39.2K_0402_1% 13 SENSE A
14
RA4 close to chip SENSE B
29
MIC2-VREFO MIC2-VREFO 33
37 CBP
CA2 1 2 2.2U_0402_6.3V6M 35 7 LDO3 CA3 2 1 4.7U_0603_6.3V6K
SIV (EMI suggestion) CBN LDO3-CAP
39 LDO2 CA4 2 1 4.7U_0603_6.3V6K
LDO2-CAP
RA13, CA13 close to UA1 LDO1-CAP 27
+3VS 36 LDO1 CA5 2 1 4.7U_0603_6.3V6K
CA6 CPVDD
2 1 4.7U_0603_6.3V6K 1 RA5 2
28 100K_0402_5%
R163 1 VREF
+3VLP 2100K_0402_5% 20 CPVREF
CA7 1 2 1U_0402_6.3V6K
@ 15 JDREF
CA8 JDREF
2 1 4.7U_0603_6.3V6K 19 MIC-CAP CPVEE 34 CPVEE 1 2 20K_0402_1%
RA6
B SVT
RA7 1 2 0_0402_5% 4 DVSS
close to chip wide 40MIL JSPK1
B

RA7 pop on ALC283, NC on ALC233 49 Thermal PAD AVSS1 25 1 SPK_R+ R164 1 2 0_0603_5% SPK_R+_CONN 1 1
38 SPK_R- R165 1 2 0_0603_5% SPK_R-_CONN 2
AVSS2 CA9 SPK_L+ R166 0_0603_5% SPK_L+_CONN 2
1 2 3 3
2.2U_0402_6.3V6M SPK_L- R167 1 2 0_0603_5% SPK_L-_CONN 4
ALC283-CG_MQFN48_6X6 2 4

1000P_0402_50V7K

1000P_0402_50V7K

1000P_0402_50V7K

1000P_0402_50V7K
SIT (EMI suggestion) 1 1 1 1

C256

C257

C258

C259
5 G1
6 G2
2 2 2 2 ACES_50281-0040N-001
EMI@ EMI@ EMI@ EMI@ CONN@

SIT (EMI suggestion)

R196 1 2 0_0402_5% PC Beep
SPK_R+_CONN SPK_L-_CONN
R197 1 2 0_0402_5%
SPK_R-_CONN SPK_L+_CONN

R198 1 2 0_0402_5%
EMI EC Beep 30 BEEP# 1
C260
2
0.1U_0402_16V7K

2
@EMI@
C261
1 2 HDA_BITCLK_AUDIO R172
R173 1 2 0_0402_5% PCH Beep 9 HDA_SPKR 1 2 PC_BEEP1 1 2 1 2 PC_BEEP @EMI@ @EMI@
R171 27_0402_5% C262 0.1U_0402_16V7K 1K_0402_5%
1 D8 D7
0.1U_0402_16V7K
1

PACDN042Y3R_SOT23-3 PACDN042Y3R_SOT23-3

1
@EMI@ @
C263 R174
2 33P_0402_50V8J 10K_0402_5%
GND GNDA
2

A Reserve for ESD request. A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/03/03 Deciphered Date 2015/03/03 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ALC283 CODEC
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B131P
Date: Tuesday, March 04, 2014 Sheet 27 of 52
5 4 3 2 1
 5 4 3 2 1

+5VS +5VS_HDMI

UH1

OUT 3

1 1
+3VS IN C264
2
D GND 0.1U_0402_16V7K D
2
1

2
EMI@ AP2330W-7_SC59-3
R175 C265
1M_0402_5% 1000P_0402_50V7K
2

2
Q5A

1
JHDMI1
1 6 HDMI_DET 19
8,9 DDI2_HDMI_HPD HP_DET
+5VS_HDMI 18
ME2N7002D1KW-G 2N SOT363-6 +5V
17
HDMIDAT_R DDC/CEC_GND
16 SDA

1
SVT HDMICLK_R 15 SCL
14 Reserved
R176 13
100K_0402_5% HDMI_CLK-_CK R177 1 @ HDMI_CLK-_CONN CEC
4 HDMI_CLK-_CK 2 0_0402_5% 12 20
CK- GND
11 21

2
HDMI_CLK+_CKR178 1 @ HDMI_CLK+_CONN CK_shield GND
4 HDMI_CLK+_CK 2 0_0402_5% 10 22
HDMI_TX0-_CK R179 1 @ HDMI_TX0-_CONN CK+ GND
4 HDMI_TX0-_CK 2 0_0402_5% 9 D0- GND 23
8 D0_shield
4 HDMI_TX0+_CK HDMI_TX0+_CKR180 1 @ 2 0_0402_5% HDMI_TX0+_CONN 7
+3VS +5VS_HDMI HDMI_TX1-_CK R181 1 @ HDMI_TX1-_CONN D0+
4 HDMI_TX1-_CK 2 0_0402_5% 6 D1-
5 D1_shield
RHP1 HDMI_TX1+_CKR182 1 @ 2 0_0402_5% HDMI_TX1+_CONN 4
4 HDMI_TX1+_CK D1+
2.2K_0804_8P4R_5% 4 HDMI_TX2-_CK HDMI_TX2-_CK R183 1 @ 2 0_0402_5% HDMI_TX2-_CONN 3
HDMICLK_R D2-
1 8 2 D2_shield
2 7 HDMIDAT_R HDMI_TX2+_CK R184 1 @ 2 0_0402_5% HDMI_TX2+_CONN 1
4 HDMI_TX2+_CK D2+
3 6 DDI2_CTRL_CK
4 5 DDI2_CTRL_DATA SINGA_2HE1638-012212F_19P-T
CONN@
SIV

C C
Q6A
2

ME2N7002D1KW-G 2N SOT363-6
Close to HDMI connector
8 DDI2_CTRL_CK 1 6 HDMICLK_R ESD
5

D9 @ESD@ SD309470080
HDMI_TX2+_CONN 1 9 HDMI_TX2+_CONN
4 3 HDMIDAT_R S ROW RES 1/16W 470 +-5% 8P4R 0804
8 DDI2_CTRL_DATA
HDMI_TX2-_CONN 2 8 HDMI_TX2-_CONN
Q6B
HDMI_TX0+_CONN 4 7 HDMI_TX0+_CONN 470 +-5% 8P4R
ME2N7002D1KW-G 2N SOT363-6 HDMI_CLK-_CONN 5 4
HDMI_TX0-_CONN 5 6 HDMI_TX0-_CONN HDMI_CLK+_CONN 6 3
HDMI_TX1-_CONN 7 2
HDMI_TX1+_CONN 8 1

3 RP21

TVWDF1004AD0_DFN9 Main: SC300002800 470 +-5% 8P4R

L9 EMI@ 2nd: SC300001Y00 HDMI_TX0-_CONN 5 4
HDMI_CLK+_CK 3 4 HDMI_CLK+_CONN HDMI_TX0+_CONN 6 3
3 4 HDMI_TX2-_CONN 7 2
HDMI_TX2+_CONN 8 1
HDMI_CLK-_CK 2 1 HDMI_CLK-_CONN D10 @ESD@
2 1 HDMI_TX1+_CONN HDMI_TX1+_CONN RP22
1 1 1 9

3
+3VS
C323 @EMI@

2.2PU_50V C NPO 0402

C326 @EMI@

2.2PU_50V C NPO 0402

DLW21HN900HQ2L_4P
HDMI_TX1-_CONN 2 8 HDMI_TX1-_CONN SVT

2 2 C323,C326 close to L9 HDMI_CLK+_CONN 4 7 HDMI_CLK+_CONN Q5B 5

B HDMI_CLK-_CONN HDMI_CLK-_CONN ME2N7002D1KW-G 2N SOT363-6 B
5 6

4
SVT
L10 EMI@
HDMI_TX0+_CK 3 4 HDMI_TX0+_CONN 3
3 4
TVWDF1004AD0_DFN9
HDMI_TX0-_CK 2 1 HDMI_TX0-_CONN
2 1
1 1
C327 @EMI@

2.2PU_50V C NPO 0402

C328 @EMI@

2.2PU_50V C NPO 0402

DLW21HN900HQ2L_4P

2 2 C327,C328 close to L10

D11 @ESD@
+5VS_HDMI 6 3 HDMICLK_R
L11 EMI@ I/O4 I/O2
HDMI_TX1+_CK 3 4 HDMI_TX1+_CONN
3 4

+5VALW 5 2
HDMI_TX1-_CK HDMI_TX1-_CONN VDD GND
2 1
2 1
1 1
C329 @EMI@

2.2PU_50V C NPO 0402

C330 @EMI@

2.2PU_50V C NPO 0402

DLW21HN900HQ2L_4P
HDMI_DET 4 1 HDMIDAT_R
I/O3 I/O1
2 2 YSUSB2.0-5_SOT23-6
C329,C330 close to L11

Main: SC300001400
2nd: SC300001G00
L12 EMI@
A HDMI_TX2+_CK HDMI_TX2+_CONN A
3 3 4 4

HDMI_TX2-_CK 2 1 HDMI_TX2-_CONN
2 1
1 1
C331 @EMI@

2.2PU_50V C NPO 0402

C332 @EMI@

2.2PU_50V C NPO 0402

DLW21HN900HQ2L_4P

C331,C332 close to L12

2 2 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/03/03 Deciphered Date 2015/03/03 Title

SVT (EMI suggestion) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDMI_CONN
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B131P
Date: Tuesday, March 04, 2014 Sheet 28 of 52
5 4 3 2 1
 A B C D E F G H

SATA HDD (SSD) CONN.

+3VS

U25 @
+3VS 7 EN VDD 10
20 JHDD1
SATA_PTX_DRX_P0 0.01U_0402_16V7K SATA_PTX_DRX_P0_R VDD SATA_PTX_C_DRX_P0_R SATA_PTX_C_DRX_P0_C
6 SATA_PTX_DRX_P0 1 2 C267 1 A_INp
C268 1 2 0.01U_0402_16V7K 1 1
6 SATA_PTX_DRX_N0 SATA_PTX_DRX_N0 0.01U_0402_16V7K 1 2 C266 SATA_PTX_DRX_N0_R 2 6 DEW2_TI SATA_PTX_C_DRX_N0_R C269 1 2 0.01U_0402_16V7K SATA_PTX_C_DRX_N0_C 2
A_INn NC DEW1_TI SIT 2
NC 16 3 3
SATA_PRX_DTX_P0 0.01U_0402_16V7K 1 2 C270 SATA_PRX_DTX_P0_R 5 SATA_PRX_C_DTX_N0_R C271 1 2 0.01U_0402_16V7K SATA_PRX_C_DTX_N0_C 4
6 SATA_PRX_DTX_P0 SATA_PRX_DTX_N0 0.01U_0402_16V7K B_OUTp 4
6 SATA_PRX_DTX_N0 1 2 C272 SATA_PRX_DTX_N0_R 4 B_OUTn A_PRE0 9 SATA1_A_PRE0 SATA_PRX_C_DTX_P0_R C273 1 2 0.01U_0402_16V7K SATA_PRX_C_DTX_P0_C 5 5
1 8 SATA1_B_PRE0 6 1
SATA1_A_PRE1 B_PRE0 6
19 A_PRE1 7 7
SATA1_B_PRE1 17 15 SATA_PTX_C_DRX_P0_R 8
B_PRE1 A_OUTp SATA_PTX_C_DRX_N0_R 8
A_OUTn 14 9 9
SATA1_TEST 18 R185 1 2 0_0805_5% +5VS_HDD 10
TEST +5VS 10
3 11 SATA_PRX_C_DTX_P0_R SVT
GND B_INp SATA_PRX_C_DTX_N0_R
13 GND B_INn 12
21 EPAD
PS8520CTQFN20GTR2-A_TQFN20_4X4
Add EQ pin
11 GND
12 GND
U25 TI@ U25 Parade@
ACES_50208-01001-001
CONN@

+3VS
Place caps.
SN75LVCP601RTJR_TQFN20_4X4 PS8520CTQFN20GTR2-A_TQFN20_4X4 near U25

+3VS

1U_0402_6.3V6K
C275

0.1U_0402_16V7K
C276

0.01U_0402_16V7K
C277
1 1

1
SIT SATA1_TEST TI@ 1 R186 2 0_0402_5% SATA1_TEST @1 R187 2 0_0402_5%

2
SATA1_B_PRE1 @1 R189 2 2
2 0_0402_5% SATA1_B_PRE1 @1 R188 2 4.7K_0402_5%

SATA1_A_PRE1 @1 R190 2 0_0402_5% SATA1_A_PRE1 @1 R191 2 4.7K_0402_5% +5VS_HDD

SATA1_A_PRE0 @1 R192 2 0_0402_5% SATA1_A_PRE0 TI@ 1 R193 2 4.7K_0402_5% SIT

1 1 1

1
SATA1_B_PRE0 @1 R194 2 0_0402_5% SATA1_B_PRE0 @1 R195 2 4.7K_0402_5% EMI@ @
C278 C279 C280 C281
2 2
DEW1_TI @1 R201 2 0_0402_5% DEW1_TI @1 R214 2 4.7K_0402_5% 1000P_0402_50V7K 0.1U_0402_16V7K 1U_0402_6.3V6K 10U_0603_6.3V6M

2
2 2 2
DEW2_TI @1 R204 2 0_0402_5% DEW2_TI @1 R272 2 4.7K_0402_5% SIT

NGFF for WLAN+BT

+3VS +3VS_WLAN

JP3 @
1 1 2 2

JUMP_43X39 1 1
C282 C283
For Power consumption 4.7U_0603_6.3V6K 0.1U_0402_16V7K
2 2
Measurement

+3VS_WLAN
3 3
JWLAN1
1 GND 3.3VAUX 2
10 USB20_P6 3 USB_D+ 3.3VAUX 4
BT 10 USB20_N6 5 USB_D- LED1# 6
7 GND PCM_CLK 8
9 SIDO_CLK PCM_SYNC 10
11 SDIO_CMD PCM_IN 12
13 SDO_DAT0 PCM_OUT 14
15 SDO_DAT1 LED2# 16
17 SDO_DAT2 GND 18
19 SDO_DAT3 UART_WAKE# 20
21 SDIO_WAKE# UART_RX 22
23 SDIO_RESET#

UART_TX 24
25 26 SIV
GND UART_CTS
10 PCIE_PTX_C_DRX_P4 27 PETP0 UART_RTS 28
29 30 R218 1 2 0_0402_5%
10 PCIE_PTX_C_DRX_N4 PETN0 RESERVED EC_TX 30
31 32 R257 1 2 0_0402_5%
GND RESERVED EC_RX 30
10 PCIE_PRX_DTX_P4 33 PERP0 RESERVED 34
WLAN 10 PCIE_PRX_DTX_N4 35 PERN0 COEX3 36 1 R169 2
37 38 100K_0402_5%
GND COEX2
7 CLK_PCIE_WLAN 39 REFCLKP0 COEX1 40
41 42 SUSCLK_R R222 1 2 0_0402_5%
7 CLK_PCIE_WLAN# REFCLKN0 SUSCLK SUSCLK 8
SIV 43 GND PERST0# 44 PLT_RST# 8,17,26,30,33
7,9 WLANCLK_REQ# R217 1 2 0_0402_5% WLANCLK_REQ#_R 45 46 BT_DISABLE_R R199 1 2 0_0402_5%
CLKEQ0# W_DISABLE2# WLBT_OFF# 8,9
8,9 PCH_PCIE_WAKE# R216 1 @ 2 0_0402_5% WAKE#_R 47 48 R226 1 2 0_0402_5%
PEWAKE0# W_DISABLE1# EC_WL_OFF# 30
49 GND I2C_DATA 50
26,30 PCIE_LAN_WAKE# R275 1 @ 2 0_0402_5% 51 52
RSRVD/PETP1 I2C_CLK
53 RSRVD/PETN1 ALERT 54 N\ote: The real behavi\or \of BT_DISABLE are
SIT
55 GND RESERVED 56
4
57 RSRVD/PERP1 RESERVED 58 BT_DISABLE=LOW, BT=OFF 4
59 RSRVD/PERN1 RESERVED 60 BT_DISABLE=HIGH, BT=ON
61 GND RESERVED 62
63 RESERVED 3.3VAUX 64
65 RESERVED 3.3VAUX 66
67 GND

69 MTG77 MTG76 68

LCN_DAN05-67306-0102
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/03/03 Deciphered Date 2015/03/03 Title
CONN@
SP070013F00
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDD/NGFF(WLAN+BT)
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B131P
Date: Tuesday, March 04, 2014 Sheet 29 of 52
A B C D E F G H
 +3VALW
+3VLP SIT
R224 1 @ 2 0_0603_5% +3VALW_EC
1
R225 0_0603_5% C291 EMI@
SIV 1 2 100P_0402_50V8J
SVT SIT
L13 2
BLM15BD601SN1D_2P_0402 SIT 1 1 1 1
+EC_VCCA

0.1U_0402_16V7K
C284

0.1U_0402_16V7K
C285

1000P_0402_50V7K
C286 EMI@

1000P_0402_50V7K
C287 EMI@
1 2 +EC_VCCA
+3VALW_EC 1 1
C288 C289 EMI@
0.1U_0402_16V7K 2 2 2 2

111
125
1000P_0402_50V7K U26

22
33
96

67
9
1 2 2 ECAGND 2
ECAGND 37
BLM15BD601SN1D_2P_0402

EC_VDD0
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC

EC_VDD/VCC

EC_VDD/AVCC
L14
ECAGND
32 USB_CHG_CTL3 1 21 VCCST_PWRGD 11
GATEA20/GPIO00 GPIO0F
9 KB_RST# 2 23 BEEP# 27
KBRST#/GPIO01 BEEP#/GPIO10
9 SERIRQ 3 26 EC_FAN_PWM1 33
SERIRQ GPIO12
7 LPC_FRAME# 4 27 AC_OFF 38
LPC_AD3 LPC_FRAME# ACOFF/GPIO13
5
EMI
@EMI@ @EMI@
7
7
7
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD2
LPC_AD1
LPC_AD0
7
8
LPC_AD3
LPC_AD2
LPC_AD1
PWM Output
BATT_TEMP/GPIO38
63 VCIN1_BATT_TEMP 37
LPC_AD0LPC & MISC
7 LPC_AD0 10 64 VCIN1_BATT_DROP 37
R29 2 GPIO39
2 1 1 10_0402_1% 65 ADP_I 37,38
C243 22P_0402_50V8J ADP_I/GPIO3A
7 CK_LPC_KBC 12
CLK_PCI_EC AD Input GPIO3B
66
8,17,26,29,33 PLT_RST# 13 75 ADP_ID 36
EC_RST# PCIRST#/GPIO05 GPIO42
+3VALW_EC 1 2 37 76 ENBKL 8,25
R269 47K_0402_5% EC_SCI# EC_RST# IMON/GPIO43
9 EC_SCI# 20 DS3
EC_SCII#/GPIO0E
2 36 ADP_ID_CLOSE 38
GPIO1D
68 SUSACK# 8
C337 DAC_BRIG/GPIO3C
70 GPU_PWR_EN 19,45
0.1U_0402_16V7K EN_DFAN1/GPIO3D
DA Output IREF/GPIO3E
71 DGPU_PWR_EN 8,9,19,41,42 +3VALW
1

1 ESD@ KSI0 55 72
KSI0/GPIO30 CHGVADJ/GPIO3F EC_WL_OFF# 29
C295 KSI1 56
22P_0402_50V8J KSI2 KSI1/GPIO31 EC_MUTE# R271 1 @
57 2 10K_0402_5%
2

KSO[0..15] KSI3 KSI2/GPIO32 +5VS +3VS +5VS +3VS

58 83 EC_MUTE# 27
31 KSO[0..15] KSI4 KSI3/GPIO33 EC_MUTE#/GPIO4A
59 84 USB1_EN# 32
KSI[0..7] KSI5 KSI4/GPIO34 USB_EN#/GPIO4B VR_TT#_R
60 85 1 2 VR_TT# 45
31 KSI[0..7] KSI6 KSI5/GPIO35 CAP_INT#/GPIO4C 0_0402_5%
61
KSI6/GPIO36 PS2 Interface EAPD/GPIO4D
86 CMOS_ON# 25 R274
KSI7 62 87 TP_CLK R1567 1 @ 2 4.7K_0402_5%

+3VALW_EC ESD KSO0

KSO1
KSO2
39
40
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
TP_CLK/GPIO4E
TP_DATA/GPIO4F
88 TP_DATA
TP_CLK 31
TP_DATA 31
SIV
TP_CLK R1568 1 2 4.7K_0402_5%
41
KSO3 KSO2/GPIO22 R1569
42 97 TS_DISABLE# 25 1 @ 2 4.7K_0402_5%
KSO3/GPIO23 CPU1.5V_S3_GATE/GPXIOA00
1 R263 2 EC_SMB_CK1 KSO4 43 98 AC_BATT_R 1 2 AC_BATT 18,37
2.2K_0402_5% KSO5 KSO4/GPIO24 WOL_EN/GPXIOA01 0_0402_5% TP_DATA R1570 2 4.7K_0402_5%
KSO5/GPIO25 Int. K/B
44 99 ME_EN 6 R273 1
KSO6 HDA_SDO/GPXIOA02
45 109
EC_SMB_DA1 KSO7 KSO6/GPIO26 Matrix VCIN0_PH/GPXIOD00 VCIN0_PH1 37 SIV
1 R264 2 46 SPI Device Interface
2.2K_0402_5% KSO8 KSO7/GPIO27
47
KSO9 KSO8/GPIO28 VCIN1_BATT_TEMP
48 119 EC_SPI_MISO 7 1 2
KSO10 KSO9/GPIO29 SPIDI/GPIO5B C341 100P_0402_50V8J
49 120 EC_SPI_MOSI 7
KSO11 KSO10/GPIO2A SPIDO/GPIO5C VCIN1_AC_IN
50
KSO11/GPIO2B SPI Flash ROM SPICLK/GPIO58
126 EC_SPI_CLK 7 1 2
KSO12 51 128 C336 100P_0402_50V8J
KSO12/GPIO2C SPICS#/GPIO5A EC_SPI_CS0# 7
KSO13 52 1 2
KSO14 KSO13/GPIO2D R203 @ 4.7K_0402_5%
53
KSO15 KSO14/GPIO2E
54 73 USB_CHG_CTL2 32
KSO15/GPIO2F ENBKL/GPIO40
81 74 SYS_PWROK 8
KSO16/GPIO48 PECI_KB930/GPIO41
82 89 USB2_EN# 32
KSO17/GPIO49 FSTCHG/GPIO50
90 BATT_CHG_LED# 33
BATT_CHG_LED#/GPIO52
91 CAPS_LED# 31
EC_SMB_CK1 CAPS_LED#/GPIO53
37,38 EC_SMB_CK1 77
EC_SMB_CK1/GPIO44 GPIO PWR_LED#/GPIO54
92 PWR_LED# 33
EC_SMB_DA1 78 93
37,38 EC_SMB_DA1 EC_SMB_DA1/GPIO45 BATT_LOW_LED#/GPIO55 BATT_LOW_LED# 33 SIT
EC_SMB_CK2 79 SM Bus 95
7,31 EC_SMB_CK2 EC_SMB_CK2/GPIO46 SYSON/GPIO56 SYSON 35,40 DS3
EC_SMB_DA2 80 121 PM_SLP_S4#_R VCOUT1_PROCHOT# R260 1 2 0_0402_5%
7,31 EC_SMB_DA2 EC_SMB_DA2/GPIO47 VR_ON/GPIO57
127 DPWROK_EC 8
PM_SLP_S4#/GPIO59
R223 1 2 0_0402_5% H_PROCHOT# 4
46 VR_HOT#
8 PM_SLP_S3# 6 100 EC_RSMRST# 8
PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03
DS3 32 USB_CHG_CTL1 14 101 USB_CHG_STATUS# 32
PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXIOA04

1
D
39 3V/5VALW_PG 15 102 VCIN1_ADP_PROCHOT 37
EC_SMI#/GPIO08 PROCHOT_IN/GPXIOA05 VCOUT1_PROCHOT#
8 SUSWARN# 16 103 VCOUT1_PROCHOT# 37 2 1
GPIO0A H_PROCHOT#_EC/GPXIOA06 G @
8 SLP_SUS# 17 104 VCOUT0_MAIN_PWR_ON 39
GPIO0B VCOUT0_PH/GPXIOA07 Q13 C297
32 USB_CHG_EN 18 GPO 105 BKOFF# 25 S

3
19
GPIO0C
GPIO
BKOFF#/GPXIOA08
106 SVT DS3 2N7002K_SOT23-3 47P_0402_50V8J
8 AC_PRESENT GPIO0D PBTN_OUT#/GPXIOA09 2
25 107 9012@
33 EC_FAN_PWM2 EC_INVT_PWM/GPIO11 PCH_APWROK/GPXIOA10 PCH_PWR_EN 35
33 FAN_SPEED1 28 108 +1.05VS_PGOOD 43
FAN_SPEED1/GPIO14 SA_PGOOD/GPXIOA11
33 FAN_SPEED2 29
EC_PME#/GPIO15 +3VALW
29 EC_TX 30
EC_TX/GPIO16
29 EC_RX 31 110 VCIN1_AC_IN 18,38
EC_RX/GPIO17 AC_IN/GPXIOD01
8 PCH_PWROK 32 112 EC_ON 39
PCH_PWROK/GPIO18 EC_ON/GPXIOD02 @
33 NOVO# 34 114 ON/OFF# 33
SUSP_LED#/GPIO19 ON/OFF/GPXIOD03 LID_SW#
33 TP_LOCK_LED# 36 GPI 115 LID_SW# 33 1 R267 2
R207 2 NUM_LED#/GPIO1A LID_SW#/GPXIOD04 100K_0402_5%
1 116 SUSP# 35,40,43,44
10K_0402_5% SUSP#/GPXIOD05 NUVOTON_VTT
117
GPXIOD06 PECI SIT
118 1 2 H_PECI 4
PECI_KB9012/GPXIOD07
AGND/AGND

122 R208 43_0402_1%

8 PBTN_OUT# XCLKI/GPIO5D +V18R R265 1 2 0_0402_5%
GND/GND
GND/GND
GND/GND
GND/GND

Share ROM 26,29 PCIE_LAN_WAKE# 123

XCLKO/GPIO5E V18R
124 +3VALW_EC
9012@ +1.05VS
C294
1
4.7U_0603_6.3V6K
GND0

9022@

SA000079Y00 2 NUVOTON_VTT 1 2
11
24
35
94
113

69

NPCE288NA0DX LQFP 128P KBC R268 0_0402_5%

+3VALW KB9012/Nuvoton : +V18R
SIV
ECAGND

KB9022 : +3VALW_EC

PCIE_LAN_WAKE# +3VS
ESD
1 2
R261 10K_0402_5% SYSON
+5VALW 1 8 FAN_SPEED1
FAN_SPEED2

C296
2 7

0.1U_0402_16V7K
3 6 USB1_EN# @ESD@
4 5 USB_CHG_EN 1
RP33 10K_8P4R_5%
R270 1 2 0_0402_5% SIV 2

SIT 1 2 USB2_EN#
R277 10K_0402_5%
+3VS SIT

@
5

U27
2
P

8 PM_SLP_S4# B
4 PM_SLP_S4#_R
Y
8 PM_SLP_S5# 1
A
G
3

MC74VHC1G08DFT2G_SC70-5 SVT

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/03/03 Deciphered Date 2015/03/03 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BIOS & EC I/O Port
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B131P
Date: Tuesday, March 04, 2014 Sheet 30 of 52
 5 4 3 2 1

Thermal Sensor

REMOTE1+
Close U28 SMSC thermal sensor +3VS 33 REMOTE1+ To PWR/B
REMOTE1+
1 Close to thermal pipe

1
C299 +3VS R227
2200P_0402_50V7K 10K_0402_5% REMOTE1-
2 33 REMOTE1-
REMOTE1- @
U28

2
D D

1 10 EC_SMB_CK2
VDD SMCLK EC_SMB_CK2 7,30
REMOTE2+
REMOTE1+ 2 9 EC_SMB_DA2
Close to GPU
1 DP1 SMDATA EC_SMB_DA2 7,30 18 REMOTE2+
2 1

1
C301 @ @ REMOTE1- 3 8 THM_ALERT#_R 1 2 C
DN1 ALERT# THM_ALERT# 18
2200P_0402_50V7K C300 R243 0_0402_5% @ C302 2 Q9 @
2 REMOTE2- 0.1U_0402_16V7K REMOTE2+ SIV 100P_0402_50V8J B MMST3904-7-F_SOT323-3
4 DP2 THERM# 7
1 2 E

3
REMOTE2- 5 6
DN2 GND 18 REMOTE2-
SIT

EMC1403-2-AIZL-TR_MSOP10
P/N:SA000029210
REMOTE1,2+/-:
Trace width/space:10/10 mil
Address 1001_101xb F75303M P/N:SA000046C00 Trace length:<8"

KB CONN. JKB1
TP CONN.
KSI1 1
C
KSI7 1 C
2 2
KSI6 3
KSO9 3
4 4
KSI4 5 +3VS
KSI5 5
6 6
KSO0 7
KSI2 7
8 8
KSI[0..7] KSI3 9
KSI[0..7] 30 9
KSO5 10 C303
KSO[0..15] KSO1 10 @
KSO[0..15] 30 11 11
KSI0 12 0.1U_0402_16V7K SIT
KSO2 12 JTP1
13 13
KSO4 14 6 8
KSO7 14 TP_CLK 6 G2
15 15 30 TP_CLK 5 5 G1 7
KSO8 16 TP_DATA 4
16 30 TP_DATA 4
KSO6 17 1 1 3
KSO3 17 R228 1 3
18 18 7,15,16 PCH_SMB_CLK 2 0_0402_5% PCH_SMBCLK_TP 2 2
KSO12 19 @EMI@ C304 C305 @EMI@ R229 1 2 0_0402_5% PCH_SMBDATA_TP 1
19 7,15,16 PCH_SMB_DATA 1
KSO13 20 100P_0402_50V8J 100P_0402_50V8J
20 2 2 SIT
KSO14 21 ACES_51524-0060N-001
21

2
KSO11 SP010014M10

C306

C307
22

100P_0402_50V8J

100P_0402_50V8J
SIT KSO10 22 CONN@
23 23 1 1
KSO15 24 D12
R230 1 24
+5VS 2 649_0402_1% +5VS_CAPLED 25 25
@ESD@ @EMI@ @EMI@
CAPS_LED# 26 PJSOT24C 3P C/A SOT-23
30 CAPS_LED# 26 2 2

1
27 GND
28 GND SIT
3

ACES_50504-0260N-001
D13 CONN@
@ESD@
MESC5V02BD03 3P C/A SOT23

B B
1

Screw
H13 H15 H20 H19 H16 H18 H6
H7 H12 H14 H2 H3 HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
HOLEA HOLEA HOLEA HOLEA HOLEA
Board side
CPU
1

1
1

CHASSIS1_GND H_2P5 H_2P5 H_2P5 H_4P1X3P1N H_2P5 H_3P0 H_2P5

H_3P7 H_3P7 H_3P7 H_3P3
H_3P3

H9 H10 H11
HOLEA HOLEA HOLEA LAN H17
H5 H8 HOLEA
GPU HOLEA HOLEA
NGFF
1

1
1

H_3P7 H_3P7 H_3P7 H_1P5N H_1P5N

A H_3P3 A

FD1 FD2 FD3 FD4 H4 H21

HOLEA HOLEA
Fan
Zero point
Security Classification Compal Secret Data Compal Electronics, Inc.
1

Issued Date 2014/03/03 Deciphered Date 2015/03/03 Title

H_3P1N
H_1P3X1P8N
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
KB/TP/Thermal Sensor
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B131P
Date: Tuesday, March 04, 2014 Sheet 31 of 52
5 4 3 2 1
 A B C D E

USB3.0 <Port1>
+USB3_VCCA
USB3.0 <Port2>
+USB3_VCCA
+5VALW 2A

220U 6.3V M B2 H1.9

470P_0402_50V7K
1
U29 D21 @EMI@

1
C1312

C309
W=80mils + CON-USBP1+ 1 10
1 10 CON-USBP0- +USB3_VCCB
1 8 2 9
GND OUT CON-USBP1- 2 9
2 7 3 8

2
IN OUT 2 3 8 CON-USBP0+
3 6 4 7

GND
1 2 IN OUT 4 7
C310 @ C311 USB_OC0# +USB3_VCCB
4
EN# OC#
5 USB_OC0# 9,10 5
5 6
6
+5VALW
2A

220U 6.3V M B2 H1.9

470P_0402_50V7K
2.2U_0603_10V6K 1
0.1U_0402_16V7K RCLAMP3304N.TCT_SLP2626P10-10 U30

11

1
2 1

C1311

C313
AP2301MPG-13 MSOP 8P W=80mils +
1 8
GND OUT
2 7

2
1 IN OUT 2 1
1 2 3 6
C314 @ C315 IN OUT USB_OC0#
SIV (EMI suggestion) 4
EN# OC#
5
30 USB1_EN# 2.2U_0603_10V6K
0.1U_0402_16V7K
2 1 AP2301MPG-13 MSOP 8P
SIT

30 USB2_EN#

SIT

R231 2 @EMI@ 1 0_0402_5%

L15 EMI@
10 USB20_P0 USB20_P0 2 1 CON-USBP0+
2 1

USB20_N0 CON-USBP0-
10 USB20_N0 3
3 4
4 Pseudo Cap(C345, C346) to protect L16
DLW 21HN900HQ2L_4P

2 1 R232 2 @EMI@ 1 0_0402_5%

R233 @EMI@ 0_0402_5%
L16 EMI@
10 USB20_P1 USB20_P1 2 1 CON-USBP1+
2 1
+USB3_VCCA
10 USB20_N1 USB20_N1 3 4 CON-USBP1-
3 4
JUSB1 DLW21HN900HQ2L_4P
R235 2 @EMI@ 1 0_0402_5% 1
CON-USBP0- VBUS +USB3_VCCB
2 2 1
L17 EMI@ CON-USBP0+ D- R234 @EMI@ 0_0402_5%
3
U3RXDN1 D+
10 USB3_RX1_N 3 4 4
3 4 U3RXDN1 GND JUSB2
5
U3RXDP1 STDA_SSRX-
6 1
U3RXDP1 STDA_SSRX+ CON-USBP1- VBUS
10 USB3_RX1_P 2 1 7 2
2 1 U3TXDN1 GND CON-USBP1+ D-
8 2 @EMI@ 1 0_0402_5% 3
DLW 21HN900HQ2L_4P D16 U3TXDP1 STDA_SSTX- D+
9 4
U3TXDP1 STDA_SSTX+ GND
R237 2 1 0_0402_5% 1 9U3TXDP1 C345 C346 L18 EMI@ U3RXDN2 5
@EMI@ U3RXDN2 R236 U3RXDP2 STDA_SSRX-
10 2 1 2 1 10 USB3_RX2_N 3 4 6
2 U3TXDN1 GND 3 4 STDA_SSRX+ 2
2 8U3TXDN1 11 7
GND 0.1U_0402_16V7K 0.1U_0402_16V7K U3TXDN2 GND
12 8
U3RXDP1 GND SVT STDA_SSTX-
4 7U3RXDP1 13 10 USB3_RX2_P 2 1 U3RXDP2 U3TXDP2 9
GND 2 1 D17 STDA_SSTX+
U3RXDN1 5 6U3RXDN1 SINGA_2UB4039-200011F U3RXDN2 1 9U3RXDN2 10
CONN@ GND
2 1 0_0402_5% 11
U3RXDP2 GND
R239 2 @EMI@ 1 0_0402_5% @EMI@ 2 8U3RXDP2 12
DLW21HN900HQ2L_4P GND
13
U3TXDN2 GND
L19 EMI@ 3 R238 4 7U3TXDN2
10 USB3_TX1_N 2 1 U3TXDN1_R 3 4 U3TXDN1 SINGA_2UB4039-200011F
C316 0.1U_0402_16V7K 3 4 TVW DF1004AD0_DFN9 U3TXDP2 5 6U3TXDP2 CONN@
@ESD@ 2 @EMI@ 1 0_0402_5%
10 USB3_TX1_P 2 1 U3TXDP1_R 2 1 U3TXDP1 SIV (EMI suggestion)
C318 0.1U_0402_16V7K 2 1 L20 EMI@
DLW 21HN900HQ2L_4P 10 USB3_TX2_N 2 1 U3TXDN2_R 3 4 U3TXDN2 R240 3
C317 0.1U_0402_16V7K 3 4
R241 2 1 0_0402_5% TVWDF1004AD0_DFN9
@EMI@ 10 USB3_TX2_P 2 1 U3TXDP2_R 2 1 U3TXDP2 @ESD@
C319 0.1U_0402_16V7K 2 1
SIV (EMI suggestion)

2 1 0_0402_5%
@EMI@ DLW21HN900HQ2L_4P

R242

USB2.0 + Charger
+USB2_VCCA
47U_0805_6.3V6M

470P_0402_50V7K

1
1
C467
C468

2
3 @ 3

+5VALW

C320 0.1U_0402_16V7K
2 1

2 1 +USB2_VCCA

C321 4.7U_0402_6.3V6M
@

U32 R245 2 @EMI@ 1 0_0402_5%

1 12
IN OUT CON_USB20_P2_L L21 EMI@
30 USB_CHG_STATUS# 9 10
R259 2 @ 1 0_0402_5% STATUS# DP_IN CON_USB20_N2_L CON_USB20_P2_L CON_USB20_P2
9,10 USB_OC1# 13 11 2 1 CON_USB20_P2 33
FAULT# DM_IN USB20_N2 2 1
4 2
ILIM_SEL DM_OUT USB20_P2 USB20_N2 10
30 USB_CHG_EN 5 3
EN DP_OUT @ R246 2 USB20_P2 10 CON_USB20_N2_L CON_USB20_N2
30 USB_CHG_CTL1 6 15 1 2.2M_0402_1% 3 4 CON_USB20_N2 33
CTL1 ILIM_LO R247 2 3 4
30 USB_CHG_CTL2 7 16 1 20K_0402_1%
CTL2 ILIM_HI DLW 21HN900HQ2L_4P
30 USB_CHG_CTL3 8 14
CTL3 GND
17
T-PAD
2 1
TPS2544RTER_QFN16_3X3 R248 @EMI@ 0_0402_5%

4 4

Security Classification
2014/03/03
Compal Secret Data
2015/03/03 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB2.0/3.0
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
D 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-B131P
Date: Tuesday, March 04, 2014 Sheet 32 of 52
A B C D E
Power Board CONN.

+3VLP

2
R251
100K_0402_5%
I/O Board CONN.

1
ON/OFFBTN#
J3
R253
1 2 1 2 ON/OFF#
ON/OFF# 30
SHORT PADS 0_0402_5% JIO1
SIV 31 32
+USB2_VCCA 31 32
J4
1 2
J3: TOP 29
27
29 30
30
28
27 28 CON_USB20_P2 32
J4: BOT 25
25 26
26 CON_USB20_N2 32
SHORT PADS 8,17,26,29,30 PLT_RST# 23 24
23 24
7,9 CRCLK_REQ# 21 22
21 22
10 PCIE_PTX_C_DRX_P2 19 20 CLK_PCIE_CR 7
19 20
10 PCIE_PTX_C_DRX_N2 17 18 CLK_PCIE_CR# 7
17 18
10 PCIE_PRX_DTX_P2 15 16
15 16
10 PCIE_PRX_DTX_N2 13 14
+3VLP 13 14
27 HP_OUTL 11 12 +3VS
11 12
27 HP_OUTR 9 10
9 10
27 EXT_MIC_SLEEVE 7 8 +5VS
+5VALW 7 8
27 EXT_MIC_RING2 5 6 PLUG_IN# 27
5 6
2

+3VALW 40 mils 3 4
40 mils 3 4 SPDIF_OUT 27
30 LID_SW# 1 2 +3VALW
R266 @ JPWR1 1 2
100K_0402_5% 8 27 MIC2-VREFO R321 1 2 2.2K_0402_5% ACES_50255-03001-001
8 CONN@
7 10
1

SIT ON/OFFBTN# 7 G2 R322 1

6 9 2 2.2K_0402_5%
6 G1
30 NOVO# 5
PWR_LED# 5
30 PWR_LED# 4
4
31 REMOTE1+ 3
3
31 REMOTE1- 2
2
1
1 EMC
ACES_51522-00801-001 SPDIF_OUT
CONN@
1
CS1
0.1U_0402_16V7K C244
1 2 22P_0402_50V8J
EXT_MIC_SLEEVE EXT_MIC_RING2 2
@EMI@
NOVO# @EMI@

1
ON/OFFBTN#
3

R30
33_0402_5%
3

@EMI@

2
@ESD@
D20 ESD@
PJSOT24C 3P C/A SOT-23
SCA00001A00
D19
1

AZ5125-02_SOT23-3

SIV (EMI suggestion)

LED Board CONN.

FAN1 Conn

+3VS +3VLP

JLED1
8
8
7 10
PWR_LED# 7 G2 +5VS
6
6 G1
9 SVT
BATT_LOW_LED# 5
30 BATT_LOW_LED# 5
BATT_CHG_LED# 4 JFAN1
30 BATT_CHG_LED# 4
PCH_SATALED# 3 R256 1 2 0_0603_5% +5VS_FAN 1
6,9 PCH_SATALED# 3 1
TP_LOCK_LED# 2 2
30 TP_LOCK_LED# 2 2
1 30 FAN_SPEED1 3
1 3
30 EC_FAN_PWM1 4
ACES_51522-00801-001 4
2 30 FAN_SPEED2 5
5
CONN@ 30 EC_FAN_PWM2 6
C324 6
7
7
10U_0603_6.3V6M 8
1 8
9
GND
10
GND
ACES_50278-00801-001 FAN1 FAN2
CONN@

FAN_SPEED1 FAN_SPEED2
EC_FAN_PWM1 EC_FAN_PWM2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/03/03 Deciphered Date 2015/03/03 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FAN/PWR/LED/IO Board
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-B131P
Date: Tuesday, March 04, 2014 Sheet 33 of 52
 5 4 3 2 1

D D

+CHGRTC_R

1
RG1
330_0402_5%
GCLK@

2
C 1 1 C
CG5 CG11
22U_0805_6.3V6M 2.2U_0402_6.3V6M
GCLK@ GCLK@
2 UG1 2

GCLK_VRTC 10 14 RTC_VOUT
VRTC VOUT

+3VLP 15
V3.3A
1 +3VALW 2
CG4 VDD CPU_RTCX1_GCLK_R RG4
9 1 GCLK@ 2 0_0402_5% CPU_RTCX1_GCLK 6 CPU_32.768KHz
0.1U_0402_16V7K 32.768kHz
1
GCLK@ CG10 SVT
2 0.1U_0402_16V7K 11 12 GPU_XTALIN_GCLK_R RG5 1 GCLK@ 2 0_0402_5%
+1.8VGS VIOE_27M 27M GPU_XTALIN_GCLK 18 GPU_27MHz for GPU
GCLK@
2 8 6 LAN_XTLI_GCLK_R RG7 1 GCLK@ 2 33_0402_5%
1 +3V_LAN VIO_25M 25M LAN_XTLI_GCLK 26 LAN_25MHz
CG1
0.1U_0402_16V7K 1 +1.05VS 3 5 CPU_XTAL24_IN_GCLK_R RG8 1 GCLK@ 2 0_0402_5%
GCLK@ CG3 VIOE_24M 24M CPU_XTAL24_IN_GCLK 7 CPU_24MHz
2 0.1U_0402_16V7K CLK_X2 16
1 X2 1
GCLK@ CG2 CLK_X1 1 CG9
2 X1

GND1
GND2
GND3

GND4
0.1U_0402_16V7K 15P_0402_50V8J
GCLK@ @EMI@

1
2 2
SLG3NB3374VTR_TQFN16_2X3 RG2

4
7
13

17
GCLK@ 510_0402_5% 1
SA00006RD00 GCLK@ CG8
15P_0402_50V8J

2
SVT @EMI@
2

CLK_X1 1
CG7
YG1 CLK_X2 15P_0402_50V8J
4 3 @EMI@
NC OSC 2
1 2 SIV
B OSC NC B

1 25MHZ_10PF_7V25000014 1
CL28 GCLK@ CL29
15P_0402_50V8J 12P_0402_50V8J
GCLK@ GCLK@
2 2
SIV

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/03/03 Deciphered Date 2015/03/03 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
GCLK
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-B131P
Date: Tuesday, March 04, 2014 Sheet 34 of 52
5 4 3 2 1
 A B C D E

+5VALW TO +5VS
+3VALW TO +3VS +3VALW t\o +3V_PCH
DS3 +3VALW +3V_PCH

NODS3@
2 R219 1
0_0603_5%

1 1
3 1
+5VALW +5VS @
1 1 1

1
1U_0603_10V6K
C274
C293 DS3@ DS3@ DS3@

4.7U_0603_6.3V6K
C308
4.7U_0603_6.3V6K Q16 @
U2301 J510 ME2301DC-G_SOT23-3 R220

2
1 14 5VS 2 1 2 2 2 470_0603_5%
VIN1 VOUT1 2 1
2 13

2
VIN1 VOUT1

C2307

10U_0805_10V4Z

C2308

0.1U_0402_16V7K
C2322 @ JUMP_43X79
R630 0_0402_5% EN_3VS_5VS 220P_0402_50V7K
30,40,43,44 SUSP# 1 2 3 12 1 2 1 1
ON1 CT1

1
V0.2 +5VALW D
10mil SIV +5VL 4 11 DS3@ 2 PCH_PWR_EN#
VBIAS GND C2309 @ G
5 10 1 2 470P_0402_50V7K 2 2 1 R221 2 PCH_PWR_EN# S @

3
ON2 CT2 Q18
6 9 3VS 47K_0402_5% 2N7002K_SOT23-3
+3VALW VIN2 VOUT2
7 8 1 DS3@
VIN2 VOUT2

1
D DS3@
+3VS Q19 C312
15 30 PCH_PWR_EN 2 0.1U_0402_16V7K
GPAD G 2N7002K_SOT23-3
APE8990GN3B_DFN_14P J511 2
S

3
2 1
2 1
SVT

C2324

10U_0603_6.3V6M

C2323

0.1U_0402_16V7K
@ JUMP_43X79
1 1
+3VALW +5VALW

Need to check power sequence @

2 2
C2318

10U_0603_6.3V6M

C2305

10U_0603_6.3V6M
0.1U_0402_16V7K

0.1U_0402_16V7K

1 1 1 1
C2316

C2306

2 2
@ @

2 2 2 2

+0.675VS +1.05VS
+5VALW
1

1
R627 R628
@ @
1

470_0402_5% 470_0402_5%
2

@ R620 2
100K_0402_5%
2

SUSP
1

3 D 3
SUSP# 2 Q45
G SSM3K7002BFU_SC70-3
1

Q47 D Q48 D
S
3
1

@ SUSP 2 @ SUSP 2 @
R622 G G
10K_0402_5% S S
3

SSM3K7002BFU_SC70-3 SSM3K7002BFU_SC70-3
@
2

+5VALW
+1.35V
1
1

R629
@
@ R619 470_0402_5%
100K_0402_5%
2
2

SYSON#
6

Q44B
Q44A @
@ ME2N7002D1KW-G 2N SOT363-6
2 SYSON# 5
30,40 SYSON
ME2N7002D1KW-G 2N SOT363-6 SVT
1

4
1

4 4
R621
10K_0402_5% @
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/03/03 Deciphered Date 2015/03/03 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC/DC Interface
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B131P
Date: Tuesday, March 04, 2014 Sheet 35 of 52
A B C D E
 5 4 3 2 1

EMI@
PL101

JDCIN1 PF101
FBMA-L11-201209-121LMA50T_0805
1 2
VIN
1 APDIN FUSE 0501010.WR 10A 32V 5A*2 EMI@
1
2 2 1 2 APDIN1 PL102
3 FBMA-L11-201209-121LMA50T_0805
3 SP040005R00
4 4 1 2

1000P_0402_50V7K

1000P_0402_50V7K
100P_0402_50V8J

100P_0402_50V8J
5 5 SM01000BY00

ACES_50299-00501-003_5P

1
EMI@ PC101

EMI@ PC102

EMI@ PC103

EMI@ PC104
@CONN@
SP02000YD00

2
D
90W adaptor D

@ PR101
0_0402_5%
1 2
PQ101A
2N7002KDW-2N_SOT363-6

680P_0603_50V7K
+3VALW 1 2 6 1
ADP_ID 30

0.1U_0402_16V7K
PR102
750_0402_1% A/D

1
PC105

PC106
2
PR103

2
2N7002KDW-2N_SOT363-6
100K_0402_5%
VIN 1 2

3
1

PQ101B
PR104
ADP_ID_CLOSE 30
5
100K_0402_5%

4
+CHGRTC
PR105
1K_0603_5%
1 2 +3VLP
PD101
S SCH DIO BAS40CW SOT-323
2 +CHGRTC_R
+RTCBATT 1
C PR106 C
3
1K_0603_5% JBATT1 @CONN@
1 2 1 1
2 2
3 GND
4 GND

ACES_50271-0020N-001
SP02000RO00

GC02001DR00
RTC Battery BATT CR2032 3V 210MAH MB 5 W/C
30MM

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/03/03 Deciphered Date 2015/03/03 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR DCIN / RTC Battery
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom BE_BDW 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 04, 2014 Sheet 36 of 52
5 4 3 2 1
 5 4 3 2 1

EMI@ PL202
FBMA-L11-201209-121LMA50T_0805
1 2
VMB2 VMB
@CONN@ EMI@ PL201
JBATT2 PF201 FBMA-L11-201209-121LMA50T_0805
1 1
1 2 1 2 BATT+
2 2 EC_SMCA
3 3
FUSE 0501015.WR 15A 32V 5A*2 SM01000BY00
EC_SMDA SP040006F00
4 4
5 5
6 6

1
7 7

1
100_0402_1%

100_0402_1%
GND 8 PC201 EMI@ PC202 EMI@
D GND 9 1000P_0402_50V7K 0.01U_0402_25V7K D

2
PR201

PR211
SUYIN_125017GA007G101ZL

2
LTCX005GY00

2S2P / 48W

EC_SMB_CK1 30,38

EC_SMB_DA1 30,38
1 2 +3VLP
PR212
6.49K_0402_1%

1
PR214
2 VCIN1_BATT_TEMP 30 A/D
10K_0402_5%
PH201 under CPU botten side :
CPU thermal protection at 93 +-3 degree C
Recovery at 56 +-3 degree C
30 VCOUT1_PROCHOT#
18,30 AC_BATT
+EC_VCCA
30,38 ADP_I

16.5K_0402_1%
1
VCOUT1_PROCHOT#

10K_0402_1%

PR215
C C

2
5.1K_0402_1%
PR228 PR230
+5VS +5VS

PR216
0_0402_5% 0_0402_5%

PR217

2
1

1
@ 30 VCIN0_PH1

1
2

PR219

1
PC204 30 VCIN1_ADP_PROCHOT
1

3
10K_0402_1% PQ202A PQ202B PH201
1

2
0.01U_0402_25V7K 2N7002KDW-2N_SOT363-6 2N7002KDW-2N_SOT363-6 100K_0402_1%_TSM0B104F4251RZ
1

PR220
2

47K_0402_1% 2 5 PR221 SL200002H00

2
100K_0402_1%
6
2

1
8

VCIN1_BATT_DROP 3 PQ201A
P

+ ECAGND 30
1 2 2N7002KDW-2N_SOT363-6 PC203
O 0.022U_0402_16V7K +5VS
2
2

-
G

+2.48V PU202A
1

AS393MTR-E1 SO 8P OP +2.48V
4

47K_0402_1%
+5VS PR226
1

1
PQ201B 665K_0402_1%
1

PR222
1N4148WS-7-F_SOD323-2

PR232 2N7002KDW-2N_SOT363-6 1 2
2

1.5M_0402_5%

14.7K_0402_1% PR227
1

5 PR218 15K_0402_1%

3
PR202

PD204

10K_0402_1%
2

2
8
4

P
1

+
2

7 5 PQ215B
2

O
2

PR231 VCIN1_BATT_DROP 6 2N7002KDW-2N_SOT363-6

-

G
10K_0402_1% PR229

4
B 10K_0402_1% B

4
1

D PU202B
1

PQ205 2 AS393MTR-E1 SO 8P OP
1

2N7002KW_SOT323-3 G
S
3

6
2N7002KDW-2N_SOT363-6 B+
PQ215A
2

1
+5VS +2.48V PR14

PR223 PR224 56.2K_0402_1%

PR225 10K_0402_1% 10K_0402_1%

2
1 2 1 2 1 2
200_0603_5%
VCIN1_BATT_DROP 30
2

1
PC209 2 @ PC9
470P_0402_50V7K PR15
0.1U_0402_25V6
REF
1

1
10K_0402_1%

2
3 PU201
Cathode
APL431LBAC-TRL_SOT23-3
SA00001MU00
Anode
A A
1

Security Classification Compal Secret Data

Issued Date 2014/03/03 Deciphered Date 2015/03/03 Title Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-BATTERY CONN/OTP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: BE_BDW
Tuesday, March 04, 2014 Sheet 37 of 52

5 4 3 2 1
 5 4 3 2 1
AO4435L Vds=-30V
AO4435L Vds=-30V Rds_on=7.4~9.5mohm@Vgs=-6V P3
B+
Power Rating = 1W Need EC write ChargeOption() bit[8]=0
Rds_on=27~36mohm@Vgs=-5V P2 ID = 14A (Ta=70C)
ID = 8A (Ta=70C) VACP~VACN spec < 80.64mV to disable iFault_Hi function.
PQ301 SB00000DJ10 PQ302 SB000012B00
AO4435L 1P SO8 AO4455 1P SO8 SD00000K820
PR302
VIN 8
7
1
2
1
2
8
7 0.01_1206_1% EMI@ PL301 CHG_B+
6 3 3 6 1UH +-20% PH041H-1R0MS 3.8A
5 5 1 4 1 2 PQ303 SB000012B00
AO4455 1P SO8
2 3 SH00000YG00 1 8

2200P_0402_50V7K
10U_0805_25V6K

10U_0805_25V6K

0.1U_0402_25V6
2 7
3 6

PC304

PC305

EMI@ PC306

EMI@ PC307
D
PQ304 3.8x3.8xH1.8 5 D
47K_0402_5%

1 2 @EMI@ PC303
DCR: 20~25mohm
1

1
10U_0805_25V6K

200K_0402_1%
0.1U_0603_25V7K

4
1
Idc / Isat: 3.8A
PR301

DTA144EUA_SC70-3 PC302 DISCHG_G

PC301

PR303
5600P_0402_25V7K

2
PR304
200K_0402_1%
2

2
2 1 2

2
ACN VIN

2ACOFF-1
1
1

ACP PR305

1DISCHG_G-1
47K_0402_1%

1SS355_UMD2-2
1

1
V1

PD302
P2-1 PR306

2
2 charge current: 6.6A 200K_0402_1%
PQ305 PC308 PC309 PQ306
0.1U_0402_25V6 0.1U_0402_25V6
discharge current: 8A DTC115EUA_SC70-3

2
DTC115EUA_SC70-3 1 2 1 2 Hybrid: BATT limit 6.5A
PD303
3

1SS355_UMD2-2
2 1 2
6

PQ309
150K_0402_1%
PR308

PQ307A 2N7002KW _SOT323-3

0.1U_0603_25V7K

1
2 2N7002KDW -2N_SOT363-6 ACPRN# P2 D

1
PC311
PC310 2PACIN_2
1 2 G
1

VIN PACIN

2
S

3
0.1U_0402_25V6
124K_0402_1%

249K_0402_1%
1

1
P2-2

PACIN_2 SB00000H800

5
C C
PR309

PR328

10_1206_5%

AON7408L 1N DFN
5

PR310
PQ307B

7x7xH3
3

DCR: 18~22mohm

ACOK

CMPIN

CMPOUT

ACP

ACN
PR311 PR312 30,37 ADP_I PR313
2

2
Idc: 6.5A

PQ310
47K_0402_1% 20K_0402_1% 21 0_0402_5%

2
PACIN TP
1 2 5 1 2 6 1 2 4 Isat: 9.5A
2N7002KDW-2N_SOT363-6

ACDET PC314
PC313 20 BQ24737VCC 1 2
4

PC312 VCC SD00000K820

1 2 7 IOUT
1 2 SH00000Q900 PR314

3
2
1
1U_0603_25V6K
1

PQ311 0.01u_0402_25V7K 100P_0603_50V8 19 PL302 0.01_1206_1%

PHASE
DTC115EUA_SC70-3
30,37 EC_SMB_DA1
8 SDA
PU301 4.7UH +-20% PCMB104T-4R7MS 8.5A BATT+
BQ24737RGRR_VQFN20_3P5X3P5 LX_CHG 1 2 1 4
18 DH_CHG SB000010U00
HIDRV

EMI@ PR319
1 PR315 ACOFF-1 2
2 9 SA00004RZ00 2 3

AON7752 1N DFN
AC_OFF SCL

1
30,37 EC_SMB_CK1 PR317 PR318

4.7_1206_5%
10K_0402_1% 121K_0402_1% 2.2_0603_5% PC315

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K
1 2 10 17 BST_CHG 1 2 1 2 SRP SRN
ILIM BTST
1

16251_SN
+3VLP 100K_0402_1%
PD301
3

1
PQ312
PR320

PC317

PC318

PC324
0.047U_0603_16V7K

LODRV
4
0.01U_0402_25V7K
PC316

2
1

16 2 1

GND
SRN

SRP
REGN

BM

2
@

680P_0603_50V7K
2

RB751V-40_SOD323-2

EMI@ PC320
11

1 12

13

14

15

3
2
1
1

1
10_0603_5%
6.8_0603_5%

2
PR321
PC319

PR322
1U_0603_16V7 BQ24737VDD

2
2
2
1

DL_CHG
PC321
B @ PR323 B
10K_0402_5% 1 2
2

0.1U_0402_25V6
1

1
PC323
0.1U_0402_25V6 @ PC322
2

+3VALW 2 0.1U_0402_25V6

BQ24737VDD

PR326
10K_0402_1%

1
1 2 VCIN1_AC_IN 18,30
MOSFET: 3x3 DFN PR325
PR324 10K_0402_1%
H/S Rds(on): 22mohm(Typ), 34mohm(Max) 47K_0402_1%
Idsm: 7.5A@Ta=25C, 5.5A@Ta=70C PACIN

1 2

1
L/S Rds(on): 9.8mohm(Typ), 15.8mohm(Max)
Idsm: 12A@Ta=25C, 10.5A@Ta=70C PR327
ACPRN# 2
12K_0402_1%

2
PQ314

DTC115EUA_SC70-3

3
A A
For disable pre-charge circuit

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/03/03 Deciphered Date 2015/03/03 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Charger_BQ24737
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
BE_BDW
Date: Tuesday, March 04, 2014 Sheet 38 of 52

5 4 3 2 1
 A B C D E

1 1

PR401
499K_0402_1%
ENLDO_3V5V 1 2 B+

1
150K_0402_1%
PU401 PC403 PR403
B+

PR404
EMI@ PL401 7 1 3V5V_EN 0.01U_0402_25V7K 1K_0402_5%
HCB2012KF-121T50_0805 IN EN1
1 2 1 2

2200P_0402_50V7K
1 2 3V_VIN 8 3 3V_FB
IN EN2 PR405 PC404

2
10U_0805_25V6K

10U_0805_25V6K
@EMI@ PC405
0.1U_0402_25V6
5A SM01000C000 6 BST_3V
1 2 1 2
BS
1

1
0_0603_5%
@EMI@ PC401

PC406

PC407
0.1U_0603_25V7K
PL402
2

2
10 LX_3V 1 2
@ LX +3VALWP

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
1.5UH_PCMB053T-1R5MS_6A_20%
9 GND OUT 4 TDC=4A

@EMI@ PR406
SH00000SC00

1
PC408

PC409

PC410

PC411
680P_0603_50V7K 4.7_1206_5%
2 PG LDO 5 +3VLP 5x5xH3
Iocp : 6A

1
100K_0402_1%
SY8208BQNC_QFN10_3X3
30 3V/5VALW_PG DCR: 20~25mohm FSW : 750KHz

2
PR415
SA000061M00 PC412
Idc: 6A

1 3V_SN
4.7U_0603_6.3V6M

2
Isat: 10A

@EMI@ PC413
+3VLP 3.3V LDO 150mA~300mA

2
2 PR407 2
2.2K_0402_5%
30 EC_ON 1 2

@ PR408
30 VCOUT0_MAIN_PWR_ON 1 2
@ PJ401
0_0402_5%
+3VALWP 1
1 2
2 +3VALW
JUMP_43X118
3V5V_EN
1M_0402_1%

4.7U_0402_6.3V6M
1

1
PR410

PC414
2

@
2

B+ EMI@ PL403
HCB2012KF-121T50_0805
1 2 5V_VIN

5A SM01000C000

EN1 and EN2 dont't floating

2200P_0402_50V7K
10U_0805_25V6K

10U_0805_25V6K

0.1U_0402_25V6

PU402 PC415 PR412

8 1 3V5V_EN 6800P_0402_25V7K 1K_0402_5%
IN EN1
1 2 1 2
1

1
PC416

PC418

@EMI@ PC419

@EMI@ PC420

3 5V_FB PR413 PC417

3 EN2 0_0603_5% 0.1U_0603_25V7K 3
6 BST_5V 1 2 1 2
2

BS

PL404
9 10 LX_5V 1 2 +5VALWP
GND LX

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
5V_VCC 1.5UH_PCMB053T-1R5MS_6A_20%
5
VCC OUT
4 TDC=6A
1
@EMI@ PR414

680P_0603_50V7K 4.7_1206_5%

SH00000SC00

1
PC422

PC423

PC424

PC425

PC428

PC429
2
PG LDO
7
+5VL 5x5xH3 Iocp : 9A
1

PC421
4.7U_0603_6.3V6M

SY8208CQNC_QFN10_3X3
DCR: 20~25mohm
FSW : 750KHz

2
Idc: 6A
1 5V_SN

SA000061N00
2

2
1

PC426
4.7U_0603_6.3V6M

Isat: 10A
2

@EMI@ PC427

@ PJ402
+5VALWP 1 2 +5VALW
2

1 2
JUMP_43X118

5V LDO 150mA~300mA

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/03/03 Deciphered Date 2015/03/03 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+3VALW/+5VALW
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom BE_BDW 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 04, 2014 Sheet 39 of 52
A B C D E
 5 4 3 2 1

D D

EMI@ PL501
HCB2012KF-121T50_0805
B+ 1 2 1.35V_B+ PR501
2.2_0603_5%
BST_1.35V 1 2 BOOT_1.35V

2200P_0402_50V7K

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6
+1.35VP
1

1
@EMI@ PC501

@EMI@ PC502

PC503

PC504
DH_1.35V +0.675VSP
2

2
SW _1.35V

10U_0805_6.3V6K

10U_0805_6.3V6K
1

1
PC505

PC506

PC507
5
0.1U_0603_25V7K

16

17

18

19

20
2
PQ501
C PU501 C

2
VLDOIN
PHASE

UGATE

BOOT

VTT
7x7xH3 PAD 21

SB00000H800
DCR: 6.7~7.4mohm 4 DL_1.35V 15 1

AON7408L-3x3
LGATE VTTGND
Idc: 12A
Isat: 15A
14 PGND VTTSNS 2
PL502 PR502

1
2
3
1UH +-20% PCMB063T-1R0MS 12A 12.4K_0402_1%
1 2 1 2 CS_1.35V 13 3
+1.35VP CS GND
1

SH00000YE00 PC508 RT8207MZQW _W QFN20_3X3

1U_0603_10V6K
TDC : 7A @EMI@ PR503 5 1 2 12 VDDP
SA00004OV00
VTTREF 4 +VTTREFP
330U 2V D2 LESR9M EEFSX H1.9

PQ502

4.7_1206_5% PR504
PC510

ESR: 9mohm
+5VALW
AON7752 1N DFN3X3EP

5.1_0603_5%
Iocp : 10.7A 1
2

1 2 VDD_1.35V 11 5
VDD VDDQ
+1.35VP

1
+

PGOOD
FSW : 300KHz
1

PC512 PC509
SGA20331E10

4 1 2
SB000010U00

TON
@EMI@ PC513 1U_0603_10V6K PR513 0.033U_0402_16V7K

FB
+5VALW

S5

S3
2

2
2 680P_0402_50V7K 5.1_0603_5%
2

10

6
+3VALW
1
2
3

1 2

FB_1.35V
TON_1.35V

EN_0.675VSP
EN_1.35V
PR505 100K_0402_5% PR506
8.2K_0402_1%
PR507 1 2 +1.35VP
B
MOSFET: 3x3 DFN 887K_0402_1%
B
1.35V_B+ 1 2
H/S Rds(on): 22mohm(Typ), 34mohm(Max)
Vout=0.75V* (1+Rup/Rdown)

1
Idsm: 7.5A@Ta=25C, 5.5A@Ta=70C
PR508
L/S Rds(on): 8.2mohm(Typ), 14.5mohm(Max) @ PR509 10K_0402_1%
Idsm: 12A@Ta=25C, 15A@Ta=70C 30,35 SYSON 1 2

2
Mode Level +0.675VSP VTTREF_1.35V 0_0402_5%
S5 L off off

1
@ PC514
S3 L off on 0.1U_0402_10V7K
S0 H on on

2
Note: S3 - sleep ; S5 - power off
PR511
1_0402_1% @ PJ501
1 2 +1.35VP 1 2 +1.35V
15 DDR_VTT_PG_CTRL 1 2
JUMP_43X118
@ PR510
0_0402_5%
1 2
30,35,43,44 SUSP# @
PC515

1
PJ503 @

0.1U_0402_10V7K
1 2
+0.675VSP 1 2 +0.675VS

2
A
JUMP_43X39 A

Security Classification Compal Secret Data

Title
Compal Electronics, Inc.
Issued Date 2014/03/03 Deciphered Date 2015/03/03
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RT8207M
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
BE_BDW
Date: Tuesday, March 04, 2014 Sheet 40 of 52
5 4 3 2 1
 A B C D

PR601
+1.8VGSP_ON 1 2 DGPU_PWR_EN 8,9,19,30,42
180K_0402_1%

0.1U_0402_16V7K

1
PC601
1
PR603
1
1M_0402_5% 1

2
PU601
PGND 9 3.8x3.8xH1.8
1 FB SGND 8 DCR: 20~25mohm
PJ601 @ 2 7 PL601 Idc / Isat: 3.8A
PG EN 1UH_PH041H-1R0MS_3.8A_20%
+3VALW 1 2 3 6 LX_1.8VGSP 1 2
1 2 IN LX +1.8VGSP

@EMI@ PR604
SH00000YG00

68P_0402_50V8J
JUMP_43X79 PC602 4 PGND NC 5

22U_0603_6.3V6M

22U_0603_6.3V6M
4.7_0603_5%
TDC : 1.6A

1
PC603
22U_0805_6.3VAM

1
PC604

PC605
SY8003ADFC DFN 8P PR605
SA00007QP00 20K_0402_1%
Rup Iocp : 3A

2
FSW : 1MHz

2
FB_1.8VSP

1
@EMI@ PC606
1
FB=0.6V

680P_0402_50V7K
PR606
10K_0402_1%
Rdown

2
@
PJ602

2
1 2
+1.8VGSP 1 2 +1.8VGS
JUMP_43X79

2
Vout=0.6V* (1+Rup/Rdown) 2

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/03/03 Deciphered Date 2015/03/03 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1.8VGS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
BE_BDW
Date: Tuesday, March 04, 2014 Sheet 41 of 52
A B C D
 5 4 3 2 1

D D

PR608
1 2 DGPU_PWR_EN 8,9,19,30,41
150K_0402_1%

0.1U_0402_16V7K
1

1
PC607
1M_0402_1%

2
PR609
PJ603 +VGA_PCIE

2
+0.95VSP 1 2
1 2
JUMP_43X118 @
C @EMI@ PR610 @EMI@ PC608 C
4.7_1206_5% 680P_0603_50V7K
EMI@ PL602 1 2SNB_0.95VS1 2
HCB2012KF-121T50_0805 PU602
B+_0.95VS
B+ 1 2 8
IN EN
1 PR611
0_0603_5%
PC612
0.1U_0603_25V7K
10U_0805_25V6K

10U_0805_25V6K

6 BST_0.95VS
1 2 1 2
0.1U_0402_25V6
2200P_0402_50V7K

BS
1

PL603
@EMI@ PC609

PC613

PC610

3VLDO_0.95VS LX_0.95VS
+0.95VSP
@EMI@ PC611

9 10 1 2
GND LX
2

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
@ 1UH +-20% PCMB053T-1R0MS 7A PR613
1

1
SH00000Z200 TDC 5A

330P_0402_50V7K
1

1
PC615

PC616

PC617

PC618
4

78.7K_0402_1%
@ PR612 FB

PC614
0_0402_5% ILMT_0.95VS
3 7
Rup Iocp 8A
+3VALW

2
ILMT BYP
FSW 800KHz
2

2
4.7U_0603_6.3V6K
ILMT_0.95VS 2 5 3VLDO_0.95VS
PG LDO

PC620
4.7U_0603_6.3V6K
1

1
@ SY8208DQNC_QFN10_3X3

PC619
SA000061Q00 FB = 0.6V

1
PR615
0_0402_5% 2 PR616
Rdown
2

133K_0402_1%

2
The current limit is set to 8A, 12A or 16A when this pin
is pull low, floating or pull high
VFB=0.6V
Vout=0.6V* (1+Rup/Rdown)

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

2014/03/03 2015/03/03 Title
Issued Date Deciphered Date 0.95VS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
BE_BDW
Date: Tuesday, March 04, 2014 Sheet 42 of 52
5 4 3 2 1
 5 4 3 2 1

D D

PR702
0_0402_5%
1 2 SUSP# 30,35,40,44
C C

1
@ PC702
1M_0402_1%
0.22U_0402_10V6K

2
PR703 PJ701

2
+1.05VSP 1 2 +1.05VS
1 2
JUMP_43X118 @
@EMI@ PR704 @EMI@ PC703
4.7_1206_5% 680P_0603_50V7K
EMI@ PL701 1 2SNB_1.05VS1 2
HCB2012KF-121T50_0805 PU701
B+_1.05VS
B+ 1 2 8
IN EN
1 PR705
0_0603_5%
PC704
0.1U_0603_25V7K
10U_0805_25V6K

10U_0805_25V6K

6 BST_1.05VS
1 2 1 2
0.1U_0402_25V6
2200P_0402_50V7K

BS
1

PL702
@EMI@ PC705

PC706

PC707

3VLDO_1.05VS LX_1.05VS
+1.05VSP
@EMI@ PC701

9 10 1 2
GND LX
2

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
@ 1UH +-20% PCMB053T-1R0MS 7A TDC=4.5A
1

1
SH00000Z200

100K_0402_5%

330P_0402_50V7K
1

1
PC709

PC710

PC711

PC712
PR707
@ PR706 FB
4 Iocp 8A

PC708
ILMT_1.05VS
0_0402_5% 3 7
+3VALW FSW 800KHz

2
ILMT BYP
Rup
2

2
4.7U_0603_6.3V6K
ILMT_1.05VS +1.05VS_PGOOD 2 3VLDO_1.05VS
+3VS 1 2
PG LDO
5

1
PR701

PC714
4.7U_0603_6.3V6K
1

@ 10K_0402_5% SY8208DQNC_QFN10_3X3
PC713

SA000061Q00 FB = 0.6V
2

1
PR708
2

0_0402_5% PR709
30 +1.05VS_PGOOD
Rdown
2

133K_0402_1%

2
B
The current limit is set to 8A, 12A or 16A when this pin B
is pull low, floating or pull high
VFB=0.6V
Vout=0.6V* (1+Rup/Rdown)

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/03/03 Deciphered Date 2015/03/03 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1.05VS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
BE_BDW
Date: Tuesday, March 04, 2014 Sheet 43 of 52
5 4 3 2 1
 5 4 3 2 1

D D

PR815
200K_0402_1%
2 1 SUSP# 30,35,40,43

1
PR810 PC832
1M_0402_1% 0.01UF_0402_25V7K

2
1
@ PR817 @ PC824
4.7_1206_5% 680P_0603_50V7K
PL801 1 2SNB_1.5VS 1 2 +1.5VSP PJ801
HCB2012KF-121T50_0805 PU801 2 1 +1.5VS
B+_1.5VS 2 1
B+ 1 2 8
IN EN
1 PR818
0_0603_5%
PC827
0.1U_0603_25V7K @ JUMP_43X118
0.1U_0402_25V6
10U_0805_25V6K

10U_0805_25V6K
6BST_1.5VS 1 2 1 2
2200P_0402_50V7K

BS
1

1 PL802
@EMI@ PC831

PC830

PC828

LX_1.5VS
+1.5VSP
@EMI@ PC829

9 10 1 2
GND LX
2

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
@ 1UH +-20% PCMB053T-1R0MS 7A @

1
SH00000Z200 PR816 TDC 5.5A

330P_0402_50V7K
1

1
PC833

PC822

PC821

PC820
FB
4 Rup

PC826
Iocp 8A

30.1K_0402_1%
3VLDO_1.5VS ILMT_1.5VS 3 7
+3VALW

2
ILMT BYP
FSW 800KHz

4.7U_0603_6.3V6K

2
C 2 53VLDO_1.5VS C

4.7U_0603_6.3V6K
PG LDO
1

PC823
1
SY8208DQNC_QFN10_3X3 FB = 0.6V

PC825
@ PR711 SA000061Q00

1
0_0402_5%

2
PR812
Rdown
2

ILMT_1.5VS
20K_0402_1%
1

2
PR712
0_0402_5%
VFB=0.6V
Vout=0.6V* (1+Rup/Rdown)
2

The current limit is set to 8A, 12A or 16A when this pin
is pull low, floating or pull high

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/03/03 Deciphered Date 2015/03/03 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1.5VSP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-A321PR01
Date: Tuesday, March 04, 2014 Sheet 44 of 52
5 4 3 2 1
 A B C D E

MOSFET: dual N / 5x6 DFN

H/S Rds(on): 5mohm(Typ), 8.5mohm(Max)
1
Idsm: 22A@Ta=25C, 17A@Ta=70C 1

+VGA_B+
L/S Rds(on): 2.4mohm(Typ), 3.2mohm(Max)

10U_0805_25V6K

10U_0805_25V6K
Idsm: 36A@Ta=25C, 29A@Ta=70C

1
PC936

PC927
2

2
+3VGS Vboot regulation
HG3
7x7xH3

10K_0402_1%

10K_0402_1%

10K_0402_1%

10K_0402_1%

10K_0402_1%

10K_0402_1%

10K_0402_1%

10K_0402_1%

10K_0402_1%

10K_0402_1%
+5VS
PU902 DCR: 0.98mohm

1
PR955 6 1 PR954 PC908 Idc / Isat: 28A
0_0402_5% VCC UGATE 2.2_0603_5% 0.22U_0603_25V7K
1 2 7 2 1 2 1 2 PL904 SH00000OY00 +VGA_CORE
FCCM BOOT 0.22UH 20% PCME064T-R22MS0R985 28A

1U_0603_10V6K
1
PR903

PR904

@ PR905

PR906

@ PR907

@ PR909

@ PR910

PR911

@ PR912

PR913

PC937
3 8 1 2

GPU_VID5 2

GPU_VID4 2

GPU_VID3 2

GPU_VID2 2

GPU_VID1 2

GPU_VID5 2

GPU_VID4 2

GPU_VID3 2

GPU_VID2 2

GPU_VID1 2
PWM PHASE
4 5

1
GND LGATE

4.7_1206_5%
9

SNUB1_VGA
TP

330U 2V D2 LESR9M EEFSX H1.9

RF@ PR953

PC926
1
SA000050900
ISL6208BCRZ-T_QFN8_2X2 +

2
D1

G1

S1/D2

2 PR950 1
2

10K_0402_1%

10K_0402_1%

10K_0402_1%

1_0402_1%

SGA20331E10
3.65K_0402_1%
RF@ PC935

PR952
680P_0603_50V7K
1

PR951

PR958
1 2 AON6932A 2N DFN5X6-8

PR949
SB00000XJ10 PQ903

G2
S2

S2

S2
19,30 GPU_PWR_EN @ PR902 0_0402_5%
0.1U_0402_16V7K

2
1

6
PC902

VSUM+_VGA ISEN3_VGA ISEN2_VGA ISEN1_VGA VSUM-_VGA

@
LG3 EMI@ PL901
FBMA-L11-201209-121LMA50T_0805
PR915 1 2
1 2DPRSLPVR_VGA-1 +VGA_B+ EMI@ PL905
FBMA-L11-201209-121LMA50T_0805

18

18

18

18

18
GPU_VID5

GPU_VID4

GPU_VID3

GPU_VID2

GPU_VID1
10K_0402_1%

2200P_0402_50V7K

10U_0805_25V6K

10U_0805_25V6K
1 2

0.1U_0402_25V6
2
B+ 2

@EMI@ PC903

@EMI@ PC904
FBMA-L11-201209-121LMA50T_0805

1
PC905

PC901
+3VGS 1 2 1 2
@ PR916 EMI@ PL906 Venus / XTX (45W)
1.91K_0402_1%

2
Maximum Current: 52A
PR901
Peck Current: 78A
8,9 DGPU_PWROK OCP setting: 93.6A
0_0603_5%
UGATE2_VGA 1 2 HG2 Frquency: 450KHz
PR917 PC906 Load line: 1.5mV/A
+3VGS 1 2 2.2_0603_5% 0.22U_0603_25V7K
VRON_VGA

PR918 BOOT2_VGA 1 2BOOT2_2_VGA 1 2 PL903 SH00000OY00

GPU_VID6

+VGA_CORE
10K_0402_5% 0.22UH 20% PCME064T-R22MS0R985 28A
PHASE2_VGA 1 2
Rbias PR920
47K_0402_1%
PSI#_VGA

1 2

1
RF@ PR919
4.7_1206_5%
Rsum
RBIAS_VGA

Ro

330U 2V D2 LESR9M EEFSX H1.9

PC925
3.65K_0402_1%
1

1
LGATE2_VGA

1_0402_1%
PR925

10K_0402_1%

10K_0402_1%

10K_0402_1%
40
39
38
37
36
35
34
33
32
31

D1

G1

S1/D2

SNUB2_VGA
2
+

PR921

PR924
100K_0402_5% PU901

PR922

PR923

PR957
1 2
CLK_EN#

VID6
VID5
VID4
VID3
VID2
VID1
VID0
DPRSLPVR
VR_ON

+3VGS
AON6932A 2N DFN5X6-8
SB00000XJ10 PQ902 2

SGA20331E10
G2
30

S2

S2

S2
30 VR_TT#

2
BOOT2

680P_0603_50V7K
Rth UGATE2
29

RF@ PC910
1 28

6
PGOOD PHASE2
2 27
PSI# VSSP2

1
6.98K_0402_1% 470K_0402_5%_TSM0B474J4702RE 3 26
RBIAS LGATE2 VSUM+_VGA ISEN2_VGA ISEN1_VGA ISEN3_VGA VSUM-_VGA
1 2 1 2 4 25 +5VS
VR_TT# VCCP
5 24

2
PR926 PH902 VW_VGA NTC PWM3

1U_0603_10V6K
6 23
VW LGATE1

PC913
SL200002E00 COMP_VGA 7 22
FB_VGA COMP VSSP1
8 21
FB PHASE1
Rfset ISEN3_VGA 9

2
UGATE1

ISEN3
1000P_0402_50V7K

10
BOOT1
ISUM+

ISEN2
1

ISEN1

ISUM-
VSEN

IMON

PC938
5.9K_0402_1%

VDD
RTN

VIN
PR927

VSUM-_VGA 2 1 41
AGND
1
PC914

SA00003WG00
0.22U_0402_16V7K ISL62883CHRTZ-T_TQFN40_5X5
11
12
13
14
15
16
17
18
19
20

3 3
PR928 PC915
2

499_0402_1% 390P_0402_50V7K
1 2FB1_VGA
1 2
ISUM-_VGA

VDD_VGA
RTN_VGA

PR929
BOOT1_VGA

2.32K_0402_1% 1 2 +5VS
PC916 1 2 VSEN_VGA @ PR930
S CER CAP 150P 50V J NPO 0402 @ PR931 0_0402_5% 10K_0402_1%
1 2 Rdroop VIN_VGA 1 2
ISEN2_VGA +VGA_B+
PC919 PR933 PR934 +VGA_B+
150P_0402_50V8J 147K_0402_1% 1_0402_5%

10U_0805_25V6K

10U_0805_25V6K
ISEN1_VGA
1 2FB2_VGA1 2 1 2
0.22U_0402_16V7K

0.22U_0402_16V7K

0.22U_0603_25V7K

+5VS
1

1
PC921

PC922

PC924
51.1K_0402_1%
1

1
PC923

PC917

PC918
1U_0603_10V6K
PR936

PR932
2

2
0_0603_5%
2

for positive offset UGATE1_VGA 1 2 HG1

@
2

1 2 BOOT1_1_VGA 1 2
PR935
VSUM-_VGA 2.2_0603_5% PC920
0.22U_0603_25V7K PL902 SH00000OY00 +VGA_CORE
0.22UH 20% PCME064T-R22MS0R985 28A
VSUM+_VGA PHASE1_VGA 1 2

330U 2V D2 LESR9M EEFSX H1.9

PC907
4.7_1206_5%
1

SNUB1_VGA
RF@ PR938
Cn
2

+
2.61K_0402_1%
1

1 2
D1

G1

S1/D2
1

21 VDDC_SEN
PR944

LGATE1_VGA

1
@ PR943 0_0402_5% 2

SGA20331E10
PC928

3.65K_0402_1%
Rp Rntcs
0.033U_0402_16V7K

2 PR942 1
PR939
1000P_0402_50V7K

10K_0402_1%

10K_0402_1%

10K_0402_1%

1_0402_1%
0.22U_0402_16V7K
2

RF@ PC929

PQ901 SB00000XJ10
330P_0402_50V7K

680P_0603_50V7K
G2
S2

S2

S2
1NTC_VGA 2
1

1
PC930 @

PR941

PR956
AON6932A 2N DFN5X6-8
11K_0402_1%
1

1
PC931

PC932

PR945

PR940
3

2
2

2
2

4 4
2
1

PC933 PH901 VSUM+_VGA ISEN1_VGA ISEN2_VGA ISEN3_VGA VSUM-_VGA

1 2 1000P_0402_50V7K 10K_0402_1%_TSM0A103F34D1RZ
21 VDDC_RTN
2

@ PR946 0_0402_5%
Rntc
2

PR948 SL200002F00
887_0402_1%
1 2 VSUM-_VGA

Ri
1

PC934
.1U_0402_16V7K Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/03/03 Deciphered Date 2015/03/03 Title
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ISL62883C
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 04, 2014 Sheet 45 of 52
A B C D E
 5 4 3 2 1

D D

+1.05VS Follow intel guideline

PR1102
1 2

130_0402_1%

PC1102
1U_0402_6.3V6K PR1103
1 2 1 2

54.9_0402_1%

EMI@
11 VR_SVID_DAT PL1103
FBMA-L11-201209-121LMA50T_0805
Note: 1 2
VR_SVID_ALRT# Pull high on HW side EMI@
11 VR_SVID_ALRT# PL1101
FBMA-L11-201209-121LMA50T_0805
1 2
B+ 1
CPU_B+

33U_25V_M
PC1107
PR1104 CPU_B+ +
11 VR_SVID_CLK Note:
90.9K_0402_1%
1 2 PR1104=169K
C
=>Icc(max)=32A 2 C

VR_SVID_ALRT#
CPU_B+
fsw=700KHz

VR_SVID_DAT
VR_SVID_CLK

2200P_0402_50V7K
0.01U_0402_50V7K
11 VR_ON SF000005200

10U_0805_25V6K

10U_0805_25V6K

@EMI@ PC1105

@EMI@ PC1106
PRGM1

1
PC1104
@ PR1101
+1.05VS

1
PC1103
1.91K_0402_1%
1 2

2
PR1105 7x7xH3

2
0_0603_5%
21

20

19

18

17
PU1101 1 2
DCR: 0.66mohm
11 VGATE
@ PR1122 Idc: 36A

SCLK

SDA
PAD

ALERT#

PRGM1
1.5K_0402_1% Isat: 45A
1 2
PC1101 VR_ON 1 16 LAGTE
1000P_0402_50V7K VR_ON LGATE PL1102 SH00000OY00
1 2 0.22UH 20% PCME064T-R15MS0R667 36A
2 15 PHASE 1 2
PR1106 PGOOD PHASE +CPU_CORE

4.7_1206_5%
RF@PR1107
Note: 97.6K_0402_1% PQ1101

1
1 2 IMON 3 14 UAGTE
VR_HOT# Pull high on HW side IMON UGATE

7
SB00000XJ10
PR1108 PC1108

AON6932A 2N DFN5X6-8
ISL95813HRZ-T_QFN20_3X4 2.2_0603_5% 0.22U_0603_16V7K

D1

G1

S1/D2

1
30 VR_HOT# VR_HOT_1# 4 13 BOOT 1 2 1 2
PH1101 VR_HOT# SA000073100 BOOT PR1109

2
47P_0402_50V8J

470K_0402_5%_ TSM0B474J4702RE PR1110 3.65K_0603_1%

NTC

G2
1 2 1 2 5 12

S2

S2

S2
NTC VCC +5VS
1

680P_0603_50V7K
PC1109

RF@PC1110
SL200002E00 intel Shark Bay ULT 15W

2
1
3.83K_0402_1%
TDC 10A

6
PR1111 COMP 6 11 PRGM2
2

COMP PRGM2

1
27.4K_0402_1% TDC 14A at PL2 for 40S
ISUMN

ISUMP

2
Over temperature protection: 1 2 PC1111
Peak Current: 32A
RTN

124K_0402_1% 0.1U_0402_25V6
FB

OTP Setting: 100C active

2
1 OCP current: 38.5A
PR1112

B Pin5 (NTC) voltage <0.88V, Protect Frequency: 750KHz B

7

10

Pin5 (NTC) voltage >0.92v, recovery Load line -2.0mV/A

5.9K_0402_1%
1

FB
ISUMN

ISUMP

Note:
PR1113

33P_0402_50V8J PR1112=124K
1
6800P_0402_25V7K

2K_0402_1%

10_0402_1%

PC1112 =>Slew rate=53mV/us

2

@PR1115

Vboot = 1.7V
2

PR1114
1

1.27K_0402_1%
PC1113

@
1
PR1116
2

1
390P_0402_50V7K

4.99M_0402_1%
1

1
330P_0402_50V7K

PR1118
2
1

@PC1115

PR1117

4.42K_0402_1%
@ RC Match
2
PC1114

Droop
2

2
2

1
PC1116 PC1117 PR1119
0.022U_0402_25V7K 0.1U_0402_16V4Z 11K_0402_1%
2

1
11 VCCSENSE
PH1102
10KB_0402_5%_ERTJ0ER103J

@ PC1118 SL200002F00

2
0.082U_0402_16V7K

1 2 OCP Setting
@PC1119

330P_0402_50V7K
1

PR1120
A
1 2 A
2

PC1120 422_0402_1%
1 2
0.01U_0402_50V7K
@ PC1121 @ PR1121

11,13 VSSSENSE 1 2 1 2
123
4700P_0402_25V7K 1.5K_0402_1% Title

Local sense put on HW site ISL95813 for BDW-Y&U(15W/28W) CPU

Size Document Number Rev
1.0
BE_BDW
Date: Tuesday, March 04, 2014 Sheet 46 of 52

5 4 3 2 1
 A
B
C
D

5
5

+CPU_CORE

2 1 2 1 2 1
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

@
PC1323 PC1311 PC1301

2 1 2 1 2 1
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

@
PC1327 PC1312 PC1302

2 1 2 1
22U_0603_6.3V6M 22U_0603_6.3V6M
PC1313 PC1303

2 1 2 1
22U_0603_6.3V6M 22U_0603_6.3V6M
PC1314 PC1304
22u 0603 *22/ @*2

2 1 2 1
22U_0603_6.3V6M 22U_0603_6.3V6M
PC1315 PC1305

2 1 2 1
22U_0603_6.3V6M 22U_0603_6.3V6M
PC1316 PC1306

4
4

2 1 2 1
22U_0603_6.3V6M 22U_0603_6.3V6M
PC1317 PC1307

2 1 2 1
22U_0603_6.3V6M 22U_0603_6.3V6M
PC1318 PC1308

2 1 2 1
22U_0603_6.3V6M 22U_0603_6.3V6M
PC1319 PC1309

2 1 2 1
22U_0603_6.3V6M 22U_0603_6.3V6M
PC1320 PC1310

Issued Date
Security Classification

3
3

2014/03/03
+VGA_CORE

10U_0603_6.3V6M 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K

PC993 PC983 PC974 PC966
2
1
2
1
2
1
2
1

Compal Secret Data

Deciphered Date
10U_0603_6.3V6M 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K
PC994 PC984 PC975 PC967
2
1
2
1
2
1
2
1

10U_0603_6.3V6M 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K

PC995 PC985 PC976 PC968
2
1
2
1
2
1
2
1

10U_0603_6.3V6M 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K

PC961 PC986 PC977 PC969
2
1
2
1
2
1
2
1

2
2

10U_0603_6.3V6M 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K

PC1000 PC987 PC978 PC970
2
1
2
1
2
1
2
1

10U_0603_6.3V6M 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K

PC1001 PC988 PC998 PC971
2015/03/03

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2
1
2
1
2
1
2
1

10U_0603_6.3V6M 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K

PC999 PC989 PC979 PC972
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
2
1
2
1
2
1
2
1

10U_0603_6.3V6M 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

PC962 PC990 PC980 PC973

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
2
1
2
1
2
1
2
1

10U_0603_6.3V6M 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K

PC963 PC991 PC981 PC996
Size
Title

Date:
2
1
2
1
2
1
2
1

Custom

1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K

PC992 PC982 PC997
2
1
2
1
2
1

Document Number

Tuesday, March 04, 2014

BE_BDW
1
1

Sheet
Compal Electronics, Inc.

47
of
52
PWR-PROCESSOR_DECOUPLING
Rev
1.0
A
B
C
D
 5 4 3 2 1

Version change list (P.I.R. List) Page 1 of 1

for PWR
Item Reason for change PG# Modify List Date Phase
45 change net name +3VS_VGA or +3VGS 11/15 SIV
1 link with HW side

D D

2 1. Change the PR1120 from 280 Ohm to 287 Ohm.

modify VCORE setting 46 2. Change the PR1117 from @ to 4.99MOhm. 11/15 SIV
3. Change the PR1118 from 2.61kOhm to 4.42kOhm.
4. Change the PC1101 from @ to 1000pF.
5. Change the PR1106 from @ to 97.5kOhm.
6. Change the PR1114 from 2kOhm to @.
7. Change the PC1114 from 330pF to @.

3 for RF request
45 PR953, PC935, PR919, PC910, PR938, PC929 change to mount 11/19 SIV

4 for RF request 46 PR1107, PC1110 change to mount 11/19 SIV

5 SIV MEMO 46 PR1101 change to NA 12/24 SIT

12/24
6 Valure modify 45 PC916 change to 150p SIT

C C
PR309 is changed from 392K_0402_1% to 124K_0402_1% (SD034124380) 12/24 SIT
AC detect valure setting 38 PR312 is changed from 59K_0402_1% to 20K_0402_1% (SD034200280)
7 Add a resistor 249K_0402_1% (SD034249380) between pin 6 of PU301 and PACIN.
PC312 is changed from 2200pF_0402_25V_X7R to 0.01uF_0402_25V_X7R (SE075103K80)
Add 2caps to GND, Add 1 SNUB
8 for EMI request 38 (PC320=0603 680pF, PR319=1206 4.7ohm, PC306=0.1uF, PC307=2200pF) 12/24 SIT

9 battery can't be remove del PC206, PD201, PC205, PR307, PQ306, PQ313
37 12/24 SIT

10 modify VCORE setting Change PR1120 to 422ohm.

46 Change PR1104 to 90.9Kohm. 02/20 SVT

B B

02/20 SVT
11 modify VCORE setting 47 Add PC1320 22uF.

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/03/03 Deciphered Date 2015/03/03 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PIR (PWR)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B131P
Date: Tuesday, March 04, 2014 Sheet 48 of 52
5 4 3 2 1
 5 4 3 2 1

Version change list (P.I.R. List) Page 1 of 4

for HW
Item Reason for change PG# Modify List Date Phase

1 HW design 09 Change U9J.P1 from PCH_GPIO76 to DDI2_HDMI_HPD 10/02 SIV

2 26 Change D5, D6 from SC300001G00 to SC300001J00

D EMI recommend 10/29 SIV D
Change D5, D6 from @EMI@ to EMI@

Change RA12 from SD028000080 to SM01000DF00

3 EMI recommend 27 Change C254 from SE071220J80 to SE074221K80 10/29 SIV
Change C254 from @EMI@ to EMI@
4 EMI recommend 32 Change D21 from SC300001G00 to SC300001J00 10/29 SIV

07 Change C20 to @
5 HW design 11/06 SIV
Remove R201
6 HW design 11 Change C41, C45 to @ 11/06 SIV

7 Change C97,C119,C113,C115,C116 to @
HW design 11/06 SIV
15 Change C93,C94,C96,C98,C99,C100 to @
Change C124,C126,C127,C128,C129,C131 to @
8 HW design 16 11/06 SIV
Change C149,C143,C144,C147 to @

C
9 HW design 17 Change CV9 to @DIS@ 11/06 SIV C

10 25 Change C214 to @
HW design 11/06 SIV
Remove R722,R721
11 Vendor recommend 34 Change CL29 form 15p to 12p 11/06 SIV
12 HW design 06 Change R17,R21 to short pad 11/07 SIV

13 HW design Change R24,R25,R26,R27 to RP31

07 11/07 SIV
Change R31,R33,R32,R55 to RP32
14 HW design 15 Change R101,R102 to short pad 11/07 SIV

15 HW design 16 Change R111,R112 to short pad 11/07 SIV

Remove RV17
16 HW design 18 11/07 SIV
Move GPU_GPIO1 to RP19.7

B 17 HW design 25 Add PCH_GPIO87 to JEDP1.7 11/07 SIV B

18 HW design 27 Change R156 to short pad 11/07 SIV

19 EMI recommend 27 Add RA13 for EMI@

11/07 SIV
Add CA12 for @EMI@
20 HW design 29 Change R217,R218,R257,R222,R199,R226 to short pad 11/07 SIV

Change R273,R274,R268 to short pad

HW design 30
21 Remove R266,R276,R214,R272 11/07 SIV
Move USB_CHG_EN#, USB_EN#, FAN_SPEED2, FAN_SPEED1 to RP33

22 HW design 31 Change R243 to short pad 11/07 SIV

23 HW design 33 Change R253 to short pad 11/07 SIV

24 HW design 35 Change R630 to short pad 11/07 SIV

25 EMI recommend 28 Add C323,C326,C327,C328,C329,C330,C331,C332 for @EMI@ 11/07 SIV

A A

26 HW design 32 Add R249,R250 11/10 SIV

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/03/03 Deciphered Date 2015/03/03 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HW-PIR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
BE_BDW
Date: Tuesday, March 04, 2014 Sheet 49 of 52
5 4 3 2 1
 5 4 3 2 1

Version change list (P.I.R. List) Page 2 of 4

for HW
Item Reason for change PG# Modify List Date Phase
27 HW design 09 Change PCH_GPIO85 to PCH_USB_EN# 11/10 SIV
28 HW design 18 Add RV13 for THM_ALERT# 11/10 SIV
D D

29 ME recommend 28 Change JHDMI1 footprint to SINGA_2HE1638-012212F_19P-T 11/10 SIV

30 Change C59,C62,C66,C70,C75 from SE00000O000 to SE00000PL00

HW design 12 11/10 SIV
Add C37,C138,C333@,C334,C335 SE00000PL00

31 HW design 07 RP31.1 & RP31.3 swap RP31.2 & RP31.4 swap => modify RP31 symbol 11/10 SIV
RP32.1 & RP32.2 swap RP32.3 & RP32.4 swap
32 EMI recommend 27 Add CA13 close to UA1 11/11 SIV
30
33 HW design 32 Change USB_CHG_EN# to USB_CHG_EN 11/11 SIV

Remove DGPU_PWR_EN, DGPU_HOLD_RST#

34 Change PCH_GPIO18 from RP10.5 to RP5.8
HW design 09 11/12 SIV
Change PCH_GPIO23 from RP10.6 to RP28.5
Remove RP10

35 HW design 25 Remove JP5 11/15 SIV

C C

36 Busyer suggestion 19 Change QV5 from SB000007H10 to SB00000QP00 11/15 SIV

37 Busyer suggestion 21 Change LV6, LV7 from SM01000BZ00 to SM01000FF00 11/15 SIV

38 Busyer suggestion 30 Change L13,L14 from SM010016810 to SM01000LP00 11/15 SIV

39 HW design 32 swap D21 (Pin1=>Pin9, Pin3=>Pin1, Pin7=>Pin3, Pin9=>Pin7) 11/18 SIV

40 EMI recommend 26 Change TS1 from SP050006F00 to SP050006800 11/20 SIV
41 EMI recommend 25 Change CA12 from 2.2u to 220P 12/02 SIV
27 Change RA3 from 45.1 to 10.6
EMI recommend 12/02 SIV
42 Change CA13 from 2.2u to 220P

43 EMI recommend 28 Change C323,C326,C327,C328,C329,C330,C331,C332 from 0.1u to 2.2P 12/02 SIV

B
44 EMI recommend 32 Change D16, D17 from ESD@ to @ESD@ 12/02 SIV B

33 Change D19 from ESD@ to @ESD@

EMI recommend 12/02 SIV
45 Change D20 from @ESD@ to ESD@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/03/03 Deciphered Date 2015/03/03 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HW-PIR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B131P
Date: Tuesday, March 04, 2014 Sheet 50 of 52
5 4 3 2 1
 5 4 3 2 1

Version change list (P.I.R. List) Page 3 of 4

for HW
Item Reason for change PG# Modify List Date Phase
1 HW design 33 Add R266(@) 100K pull-high to +3VLP for NOVO# 12/05 SIT
2 HW design 29 Add NET: DEW1_TI / DEW2_TI 12/09 SIT
D D

3 HW design 09 Add R276 10K pull-high to +3VS for DGPU_PWR_EN 12/19 SIT

4 Vendor recommend 29 Change R186, R193 from @ to TI@ 12/20 SIT

Change +12VS_Panel to B+
Add JP5
5 HW design 25 Delete R215, R504, R148 for RP10 12/20 SIT
Add RP10
Change R213 to short pad
Change R267 to @
Change net name from USB_EN# to USB1_EN#
6 HW design 30 Add USB2_EN# to U26.89 12/20 SIT
Add R277 (10K) pull-high +5VALW
Change R270 to short pad
Change net name from USB_EN# to USB1_EN# by U29.4
7 HW design Change net name from USB_EN# to USB2_EN# by U30.4 12/20 SIT
32
C Delete R249, R250 C

Change PCH_USB_EN# to PCH_GPIO85

8 HW design 09 Delete R252,R262 12/20 SIT
Delete R206 for RP10
9 HW design 08 12/20 SIT
Change R46,R51,R53 to short pad

10 HW design 07 Change R34, R35, R39, R40 to short pad 12/20 SIT

37 HW design 11 Change R79 to short pad 12/20 SIT

38 HW design 15 Change R88, R98 to short pad 12/20 SIT

39 HW design 16 Change R104 to short pad 12/20 SIT

40 HW design 18 Change RV44,RV32 to short pad 12/20 SIT
41 HW design 19 Change RV45 to short pad 12/20 SIT
B 42 HW design 20 Change RV46, RV50, RV52, RV55, RV57, RV51 to short pad 12/20 SIT B

HW design 28 Delete Q5, Q7

43 Add Q5A, Q5B 12/20 SIT
44 EMI recommend 32 Change C306, C307 from 0.1u to100P 12/20 SIT
45 HW design 33 Change R230 from 300 ohm to 649 ohm 12/23 SIT
46 Busyer suggestion 21 (X1 code) Change LV10, LV13 from SM01000BL00 to SM01000GG00 12/23 SIT
47 Busyer suggestion 08 (X1 code) Change U11 from SA00006QR00 to SA741080400 12/23 SIT
48 Busyer suggestion 25 (X1 code) Change U33 from SA00006QR00 to SA741080400 12/23 SIT
49 Busyer suggestion 30 (X1 code) Change U27 from SA00006QR00 to SA741080400 12/24 SIT
50 EMI recommend 27 Change RA12 from 120 ohm(SM01000DF00) to 300 ohm (SM01000I000) 12/24 SIT
51 HW design 27 Change RA2, RA10 to short pad 12/24 SIT
52 EMI recommend 30 Change C286, C287, C289, C291 from @ to EMI@ 12/24 SIT
53 HW design 30 Change R260, R223 to short pad 12/24 SIT
54 HW design 31 Change R228, R229 to short pad 12/24 SIT
A A

55 HW design 19 Change R260, R223 to short pad 12/25 SIT

56 HW design 25 Change L24 from EMI@ to @EMI@ 12/25 SIT
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/03/03 Deciphered Date 2015/03/03 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HW-PIR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B131P
Date: Tuesday, March 04, 2014 Sheet 51 of 52
5 4 3 2 1
 5 4 3 2 1

Version change list (P.I.R. List) Page 4 of 4

for HW
Item Reason for change PG# Modify List Date Phase
57 HW design 29 Change R275 to @ 12/27 SIT
58 HW design 28 Change C323, C326, C327, C328, C329, C330, C331, C332 from @EMI@ to EMI@ 12/27 SIT
D D

59 HW design 31 Change R230 from 649 ohm 5% to 649 ohm 1%. 12/31 SIT
60 Vendor recommend 21 Change LV10, LV13 from SM01000GG00 to SM01000I300. 01/03 SIT
61 HW design 12 Change C59, C138, C66, C334, C75 from 47uF to 22uF 01/07 SIT
62 HW design 15 Change C89, R90, C107, R100 to @ 01/07 SIT
63 HW design 16 Change C120, R106 to @ 01/07 SIT
Change R1456 to short pad
64
HW design 25 Change C225, C226 to @ 01/07 SIT
65
66 Change L6 from SM010014520 to SD002000080 (0 ohm) and change location to R2
HW design 31 Change C300, C303 to @ 01/07 SIT
67
68 HW design 33 Change R256 to short pad 01/07 SIT
69 HW design 12 Change C37, C62, C70, C335 to @ 01/03 SIT

1 HW design 25 Change location L6 to R2 01/12 SVT

2 HW design 19 Change location C989 to R830 01/12 SVT

C
3 EMI recommend 28 Change C327, C328, C329, C330, C331, C332, C323, C326 from EMI@ to @EMI@ 01/14 SVT C

4 HW design 27 Add U1(LDO), C344, C343 01/20 SVT

5 DFx recommend 32 Add C345, C346 01/22 SVT

6 Busyer suggestion 21 Change LV10, LV13 from SM01000I300 to SM01000F100 01/22 SVT
Add R249, R250
7 HW design 27 01/22 SVT
Change C253 from 1uF_0402 tp 1uF_0603

8 HW design 06 Change RG3 to short pad 01/22 SVT

9 HW design 07 Change RG9, R38 to short pad 01/22 SVT
10 HW design 25 Change R2 to short pad 01/22 SVT
11 HW design 18 Change RV187 to short pad 01/22 SVT
12 HW design 29 Change R185 to short pad 01/22 SVT
B 13 HW design 27 Change R155, R157, R158 to short pad 01/22 SVT B

14 HW design 26 Change RG6 to short pad 01/22 SVT

15 HW design 30 Change R225 to short pad 01/22 SVT
16 HW design 18 Change RV25 from 100K to 1K 02/10 SVT
17 HW design 28 Change RP21, PR22 from 680 ohm to 470 ohm 02/12 SVT
18 HW design 25 Add R148 02/19 SVT
19 HW design 30 Delete net: BATT_LEN# 02/20 SVT
20 HW design 19 Change R829 from 470 ohm to 10 ohm 02/21 SVT
21 HW design 18 Change RV187 from short pad to 0 ohm 02/21 SVT
Change R164, R165, R166, R167 from 0 ohm to short pad
22 EMI recommend 27 Change R196, R197, R198, R173 from 0 ohm to short pad 02/21 SVT
23 Busyer suggestion 19 Change Q139 from SB000003W00 to SB00000ZN00 02/21 SVT
34 Add RG2
A
24 Vendor recommend Change RG5 from 10 ohm to 0 ohm 02/24 SVT
A

25 DFx recommend 32 Change C346@ to C346 02/26 SVT

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/03/03 Deciphered Date 2015/03/03 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HW-PIR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B131P
Date: Tuesday, March 04, 2014 Sheet 52 of 52
5 4 3 2 1
www.s-manuals.com