Hybrid Switching Amplifier Using a Novel Two-

Quadrant Wideband Buffer for Dynamic Power

Supply Applications
Tae-Woo Kwak, Min-Chul Lee, Young-Sub Yuk, Kang-Ho Lee, Hyun-Hee Park, Chul Kim,
and Gyu-Hyeong Cho
Division of Electrical Engineering, School of Electrical Engineering and Computer Science
Korea Advanced Institute of Science and Technology (KAIST)
335 Gwahangno, Yuseong-gu, Daejeon, 305-701, Republic of Korea

Abstract A hybrid switching amplifier for dynamic power
supply applications is presented. To achieve both high speed
and high efficiency, a wideband buffered linear amplifier is
combined with a hysteretic controlled switching amplifier.
To obtain high linearity and reduce switching loss at low
power levels where the switching amplifier is not needed, the
linear amplifier supplies all load current with the switching
one disabled. The novel two-quadrant linear amplifier as a
voltage source for regulating the output voltage has very low
output impedance of about 200m around the switching
frequency, a high current-driving capability of maximum
220mA and a bandwidth wider than 7MHz. The hybrid
amplifier can drive a circuit with an equivalent impedance
of 7 and supply a maximum output power of 1.1W with a
maximum efficiency of about 91%. Its output voltage ranges
from 0.3V to 2.9V for a 3.3V supply. The chip is fabricated
using only thick-oxide devices in a 0.13um CMOS process
and occupies an area of 3.9mm2.
I. INTRODUCTION
Spectral efficiency and power efficiency are the most
significant issues in recent wireless communication
systems. Accordingly, modern or next generation systems
(2.5G and 3G) like EDGE, WCDMA, CDMA2000, and
WLAN utilize complex modulation techniques to make
Amplitude Modulator
optimum use of the available spectral bandwidth.
Unfortunately, however, the higher spectral efficiency of
complex modulation requires envelope variation of the
phase modulated RF carrier, which leads to an inherent
tradeoff between linearity and power efficiency in
traditional transmitter architectures.
This problem has been thoroughly investigated over
many years to improve the efficiency with high linearity
and many techniques including gate dynamic biasing [1,
2], envelope tracking [3, 4], envelope elimination and
restoration (EER) [5, 6] and polar modulation [7- 9] have
been explored. In particular, EER or polar modulation
schemes shown in Fig. 1 have significant potential for
power savings in wireless transmitters in that such a
tradeoff does not exist because nonlinear power amplifiers
are allowed to improve the power efficiency while
maintaining the linearity. However, they place very
stringent demands on the supply regulation systems
because their amplitude and phase components have much
wider bandwidths than the original I/Q components. This
is why wideband low-dropout linear amplifiers have been
still used in the amplitude path in spite of their low
efficiencies.
Recently, these linear amplifiers have been replaced by

R (t ) = I 2 + Q 2 + v(t)
-
R (t ) F t
D/A
I, Q

to
Phase Modulator
Polar
D/A Limiter v(t)
(t )
fc RF PA t
(t ) = tan 1 (Q / I ) v(t)

t
v(t)

Fig. 1. Block diagram of a polar transmitter

978-1-4244-1668-4/08/$25.00 2008 IEEE 546


switching ones for higher efficiency. To increase the
bandwidth of switching amplifier, several control methods
like interleaving delta modulation (IDM) [9] or hybrid
switching technique [10, 11] have been introduced and
expensive high-speed processes such as GaAs or SiGe
have often been used [3, 4, 6]. CMOS switching amplifier
based on IDM concept dissipates considerable power and
requires many external components like binary-weighted
inductors. Although it is demonstrated in [11] that
switching amplifiers using hybrid switching technique
which has been suggested for audio applications [12-14]
are suitable for high-speed and high-efficiency dynamic
power supplies with fewer external components, it is still
difficult to design the linear amplifier with wide
bandwidth, low output impedance and high current-
driving capability [11]. In particular, at low power levels,
unnecessary switching results in switching loss,
nonlinearity and electromagnetic interference (EMI). In
this paper, therefore, a novel hybrid switching technique
turning off the switching amplifier at low power levels is
introduced and a new buffer amplifier simpler than that in
[11] is proposed for two-quadrant operation.
II. HYBRID SWITCHING TECHNIQUE TO IMPROVE THE
EFFICIENCY AT LIGHT LOADS
A. Concept of theHybrid Switching Technique
Fig. 2(a) shows the conceptual diagram of the hybrid
switching structure where the linear stage regulates the
output voltage as a voltage source and the switching one
supplies most of the output current as a dependent current
source controlled by the output current of the former (ia)
[11-14]. In other words, the current loop defined as ( id
/ ia) drives the switching amplifier so that the output
current of the linear amplifier is as small as possible.
Driving the linear amplifiers output current as small as
possible can be viewed as raising the load impedance seen
by the linear amplifier. Because the current loop gain is ,
the equivalent load impedance of the linear amplifier is
increased by the factor of (1+).
The block diagram of a conventional hybrid switching
amplifier based on the hysteretic control is shown in Fig.
2(b). If the magnitude of hysteresis window is W as
shown in the figure, the output current of the linear
amplifier, that is, the inverse of the ripple current is
limited to the hysteresis level. Assuming that the input
voltage varies slowly compared to the switching period
and the output voltage (Vo) can be treated as constant
within the switching interval (T), the switching frequency
(fs) can be found as follows:
(1)
f s = 4 D (1 D) f s ,max
Vdd V A
f s ,max = = dd S (2)
4 L ir 4 LW
where D is the duty ratio, fs,max is the maximum switching
frequency, As is the current sense gain and ir is the peak-
to-peak ripple current. Note that the switching frequency
will not be fixed because of its dependence on the output
voltage.
Because the hybrid switching technique ensures that the
linear amplifier usually operates at a much smaller power
level than the switching amplifier, it is not difficult to
547
ia io = (1 + )ia
Vo id = ia ZL
Linear Amp Switching Amp
(a)
Vdd
VL
VH
Vx
id
W = VH - V L
AS
L
+
Vo
Vin -
ia
io ZL
F
(b)
Fig. 2. (a) Conceptual diagram and (b) conventional
structure of hybrid switching amplifier
improve the overall linearity of the hybrid switching
amplifier through the linear amplifier with higher
performance. However, unnecessary switching operation
at low power levels where the linear amplifier can drive
the output current deteriorates the performance of the
overall system including the efficiency, linearity, noise
and so on. Reference [14], therefore, proposed a novel
control approach of a dead-band at low power levels
where the switching amplifier does not assist, allowing the
linear amplifier to supply the load without interference,
ensuring high fidelity for audio applications.
B. Proposed Hybrid Switching Amplifier
The switching stage of the hybrid switching audio
amplifier proposed in [14] consists of two separate buck
converters to avoid shoot-through currents and poor
reverse recovery characteristics. In addition, it suffers
from unwanted oscillations due to the ringing between the
inductor and parasitic capacitances at the turn-off of the
switching stage.
The hybrid switching amplifier free from these
problems is shown in Fig. 3(a) for dynamic power supply
applications. Its switching stage is a single half-bridge
converter consisting of two MOSFETs and one inductor.
It also includes a freewheeling circuit to prevent unwanted
oscillations. As shown in Fig. 3(b), if the sensed value
(VSEN) exceeds the upper limit (VTH) of the hysteresis
band, the switching stage begins to supply the output
current and then the output current of the linear amplifier
(ia) decreases towards the lower limit (VTL). In the instant
of touching the lower limit, the inductor current (id)
freewheels through the power NMOS to decrease and ia
increases again. The switching operation goes on
repeatedly within the hysteresis band so long as the output
current does not go under the predefined value. Once the
output current decreases less than the predefined value,
the direction of id changes after a while and then the
enable signal (EN) becomes low to turn NMOS switch off.
Meanwhile, the output of SR latch (Q) keeps low and the
 VDD

Vg
Vx

R QB
Q
Freewheeling circuit

S
Hysteresis IT
Comparator EN

+
-
- + - +
VF
NMOS SW - VC Q
VTH VTL Control

+
SW1
id
VSEN CT

AS
ia
VIN + VOUT

RF PA
R2
R1

Load
Linear Amplifier
(a)

VTH

VTL

VSEN

Vg

EN

VF

tF
(b)
Fig. 3. (a) Simplified structure and (b) control signals of the proposed hybrid switching amplifier

capacitor CT in the freewheeling circuit charges towards
VC. After the predefined time of tF, the switch SW1 turns
on and the residual current of the inductor freewheels
through SW1 to disappear. Because the switching node
(VX) is floating, only the linear amplifier supplies all the
output current. Therefore, switching loss, noise and EMI
caused by the needless switching operation do not exist at
low power levels.
Component values in the freewheeling circuit are
chosen carefully lest the maximum turn-on time of the
NMOS switch during the maximum switching period
should exceed the value of (CTVC) / IT. Otherwise, SW1
turns on during the switching operation. The maximum
switching period can be found from the inverse of
equation (1).
III. NOVEL TWO-QUADRANT WIDEBAND BUFFER
AMPLIFIER
To control the output voltage, the linear amplifier
supplies some amount of signal current within the
predefined value and absorbs the switching ripple current
from the switching stage. Because the output ripple

548
 +Vdd +Vdd Rail-to-Rail Control

I2
+Vdd
I2
MPCS
Vbias
I2
Vi MP1 I1
Io
MNSF MPCS
Vo
SW1
I3
Vbias
Vi MPSF MN1
Vbias1
MNSF MP1
Vo

I1 Io
I1 MPCS

-Vdd -Vdd
Source
Vi Follower Vo
Biasing
Io Io
Io

Vo Vo
0 0
clipped clipped MPSF MN1
I3
by MPSF Vdd-Vd,sat by MNSF Vbias2

(a) (b) SW2

Fig. 4. Composite output stages advantageous to sourcing
the output current. I1
I2

voltage is generated by the multiplication of the ripple -Vdd

current and the output impedance of the linear amplifier,
low output impedance at the switching frequency is
requisite for low output ripple voltage [11]. In addition, Io
the linear amplifier should be able to source or sink the
ripple current while signal current is provided. It means
so-called two-quadrant operation because the current Vo
direction of the linear amplifier is always positive. 0

The composite output stages shown in Fig. 4 can make -Vdd+Vd,sat Vdd-Vd,sat
the output impedance very low with relatively low power
dissipation because of reducing the output impedance of Fig. 5. Composite output stage for two-quadrant operation.
the SF by a factor of the loop gain of the local feedback
loop [15]. Therefore, by widening the local loop, it is
possible to implement the output stage with a wide [11]. Class-AB bias circuit is also unnecessary since the
bandwidth, a high current-driving capability, and a very output stage does not require a push-pull structure.
low output impedance even at a high frequency. However, Biasing of push-pull source followers, MPSF and MNSF,
the composite output stage shown in Fig. 4(a) cannot is easily achieved by two diode-connected transistors, MPD
obtain large negative output swing because of the source and MND. In spite of the diode-connected transistors, the
follower MPSF. As a result, there is a region unable to output voltage swing of two-stage OTA is guaranteed by
operate in the second quadrant. In contrast, the output connecting the gates of MNA and MNB each other [16].
stage in Fig. 4(b) has this type of region in the first
quadrant because of the source follower MNSF. IV. EXPERIMENTAL RESULTS
Fig. 5 shows a composite output stage combining the Fig. 7 shows a micrograph of the prototype fabricated
two structures shown in Fig. 4(a) and (b) for complete using thick-oxide devices in 0.13um CMOS process with
two-quadrant operation. Two local loops (MNSF-MP1-MPCS, an area of 3.9mm2. The closed-loop gain of the hybrid
MPSF-MN1-MPCS) can be found in the middle range of the switching amplifier is 2 and the hysteresis band
output voltage. In addition, the rail-to-rail control circuit approximately ranges from 0.6V to 1.4V. Waveforms for
having the switches SW1 and SW2 is included to prevent a 50kHz sinusoidal and square-wave signal with a 7 load
the output voltage from being clipped by the SF transistor, are given in Fig. 8 and Fig. 9. Vreset is the reset signal of
namely MNSF or MPSF, near the positive or negative supply SR latch, that is, Vg and the dotted circle shows the turn-
rail, respectively. In the concrete, during positive output off of the switching stage at low power levels. Fig. 10
swings, MNSF is turned off by SW1, and the loop (MPSF- shows that the small-signal closed-loop bandwidth is
MN1-MPCS) sources or sinks the ripple current to eliminate about 7MHz. The simulation result shown in Fig. 11
the output ripple voltage. During negative output swings, demonstrates that the output impedance of the linear
MPSF is turned off by SW2, and the loop (MNSF-MP1-MPCS) amplifier is less than 200m at the switching frequency.
performs the same function. Fig. 12 shows the efficiency in relation to the output
The complete two-quadrant linear amplifier with wide voltage and the load condition. The amplifier can provide
bandwidth, low output impedance and high current- a maximum power of 1.1W to a 7 load and it has a
driving capability is shown in Fig. 6. This is much simpler maximum efficiency of 91% at a 10 load. Table I
structure than the four-quadrant amplifier suggested in summarizes the measured performance with a 4uH
inductor. The ripple current more than about 100mApp can

549
 Two-Stage OTA
- +
CC1 RC1
MNA
Fig. 6. Novel two-quadrant wideband amplifier with very low output impedance buffer
be reduced to 40mApp by a 3rd-order filter and current
feedback [11]. Although the linear amplifier was designed
to drive 220mA, unfortunately, its current-driving
capability was reduced to 40mA at the maximum output
voltage due to the channel-length modulation of the output
PMOS transistor. This is why the ripple voltage is visible
at the output as shown in Fig. 8 and Fig. 9.
V. CONCLUSION
A CMOS hybrid switching amplitude modulator based
on a hysteretic control is proposed to achieve both high
efficiency and high speed for dynamic power supply
applications. Because the linear amplifier supplies all load
current with the switching amplifier disabled at low power
levels, the performance of the overall system including the
efficiency, linearity, noise and so on is improved. We also
propose a novel buffer amplifier with a wide bandwidth,
low output impedance, two-quadrant operation, and high
current-driving capability.
ACKNOWLEDGMENT
This work was supported by the ERC program of the
Korea Science and Engineering Foundation (KOSEF)
grant funded by the Korea Ministry of Education, Science
and Technology (MEST) (No. R11-2007-045-01004-0).
REFERENCES
[1] A. A. M. Saleh and D. C. Cox, Improving the power added
efficiency of FET amplifiers operating with varying-envelope
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56, Jan. 1983.
Low Output Impedance Buffer
VDD
I2 I1
SW1
Vbias1 MP1
MPCS
MNSF
MND
CC2 RC2
VOUT
MPD
MPSF
I3
Vbias2 MN1
SW2
MNB
I2 I1
VSS
[2] K. Yang, G. I. Haddad, and J. R. East, High-efficiency class-A
power amplifiers with dual bias-control scheme, IEEE Trans.
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[3] N. Schlumpf, et al., A Fast Modulator for Dynamic Supply
Linear RF Power Amplifier, IEEE J. Solid-State Circuits, vol. 39,
pp. 1015 1025, July. 2004.
[4] F. Wang, et al., Envelope Tracking Power Amplifier with Pre-
Distortion Linearization for WLAN 802.11g, IEEE MTT-S
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[5] L. R. Kahn, Single sideband transmission by envelope
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806, July 1952.
[6] F. Wang, et al., An Improved Power-Added Efficiency 19-dBm
Hybrid Envelope Elimination and Restoration Power Amplifier for
802.11g WLAN Applications, IEEE Trans. Microwave Theory
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[7] M. R. Elliott, et al., A Polar Modulator Transmitter for
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2199, Dec. 2004.
[8] P. Reynaert and M. Steyaert, A 1.75-GHz Polar Modulated
CMOS RF Power Amplifier for GSM-EDGE, IEEE Journal of
Solid-State Circuits, vol. 40, pp. 2598-2608, Dec. 2005.
[9] P. J. Nagle, et al., A Wideband Linear Amplitude Modulator for
Polar Transmitters Based on the Concept of Interleaving Delta
Modulation, IEEE ISSCC Dig. Tech. Papers, pp. 234-488, Feb.
2002.
[10] F. Wang, et al., Wideband envelope elimination and restoration
power amplifier with high efficiency wideband envelope amplifier
for WLAN 802.11g applications, IEEE MTT-S International
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[12] N. S. Jung, J. H. Jeong, and G. H. Cho, High Efficiency and High
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[13] N. I. Kim, S. H. Jung, J. Y. Ryoo, and G. H. Cho, Ripple
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Vin

Vout

Vreset

Fig. 7. Chip micrograph. Fig. 8. 50kHz sinusoidal response at 7 load.

10

Vin

Vout Gain [dB]

1

Vreset
0.1
2.0e+6 4.0e+6 6.0e+6 8.0e+6 1.0e+7 1.2e+7

Frequency [Hz]

Fig. 9. 50kHz square-wave response at 7 load.

Fig. 10. Magnitude response of hybrid switching amplifier.

40
Zout @ Vout = Center
Zout @ Vout = Max
20
Output Impedance [dB]

-20

-40
Table I. Measured performance parameters.
-60
Supply voltage 3.3 V (only 3.3V devices)
-80
Output voltage range 0.3 V ~ 2.9 V
-100 Maximum output power (Class-E2) 1.1 W @ 7
1e+2 1e+3 1e+4 1e+5 1e+6 1e+7 1e+8

Frequency [Hz] Switching frequency ~ 2 MHz

Closed-loop BW (small-signal) ~ 7 MHz
Fig. 11. Simulated output impedance of the linear amplifier.
Output ripple voltage (with 3rd-order filter) < 20 mVpp

100 Zout of linear amp (by simulation) < 200 m @ 2MHz

Current driving capability of linear amp 40 mA ~ 220 mA (w.r.t Vout)

80

Maximum efficiency ~ 91 % @ 10
Efficiency (%)

60

40

7 ohm
20 10 ohm
22 ohm
47 ohm
Commercial LDO @ 4ohm
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

Output Voltage (V)

Fig. 12. Measured efficiency at various loads.

551