Here we generated the netlist file and constraint file (SDC) from RTL compiler in cadence and

the generated netlist and SDC files have been used in synopsys IC compiler to generate GDSII file.

STEPS

1. Create Milky way database

Create library

Set TLU+

2. IMPORT

Read Verilog

Read SDC

3. FLOOR PLAN

Aspect ratio

4. PRE ROUTE

Drive PG

Create rings

Pre route standard cells

Pre route instances

Create_fp_place_ment

Legalize_fp_placement

5. PLACE

Place_opt

6. CLOCK

Remove_clock_uncertainty [all_clocks]

Set_fix_hold [all_clocks]

Clock_opt

7. ROUTE

Route_opt
 8. EXPORT

Write stream GDSII

SCRIPT FILE FOR LIBRARY

lappend search_path ./lib/
set target_library "tsl18fs120_scl_ss.db tsl18cio250_max.db"
set link_library "tsl18fs120_scl_ss.db tsl18cio250_max.db"

STEP 1 CREATE MILKYWAY DATABASE

The milkyway libraries are given by SCL for std lib, io lib and memory which are used by us to create the
milkyway database. The following warnings were faced which snapshot is attached in the following text.

Command
create_mw_lib my_design_lib -technology
/home/subash/Desktop/synopsys_designs/counter_design/lib/icc.tf -mw_reference_library
"/home/subash/Desktop/scl_pdk/stdlib/fs120/mw/fs120_scl
/home/subash/Desktop/scl_pdk/iolib/cio250/mw/cio250_scl" -open

While adding the milkyway library of memory, it shows the following warnings
Set TLU+
The required files are max.tlup, min.tlup and .map, but SCL gave the following files only.

RCE_TS18SL_STAR_RCXT_4M1L.map
RCE_TS18SL_SCL_STAR_RCXT_4M1L_TYP.tlup

Whether the min and max files are required or not which has to be confiremed by SCL?

STEP 2 IMPORT
Read Verilog

Read SDC
When read the SDC file, the following warnings and error is shown as below and
"set_wire_load_mode" command is unsupported by icc_shell.
STEP 3 Floor Plan
 STEP 4 PRE ROUTE
Derive PG Connection

Create Rings
Pre route standard cells
Preroute instances
Create_fp_placement

legalize_fp_placement

STEP 5 PLACE

Place_opt
 STEP 6 CLOCK

clock_opt
 STEP 7 ROUTE
route_opt
The following warnings and errors are showns as below
 MEMORY
SCL has given the 256x8 memory model. We made 1024x16 memory model by 256x8. This memory
model was used to do the PnR. While reading the verilog file the following errors and warnings are
shows as below

SCRIPT FILE FOR LIBRARY

lappend search_path ./lib/

set target_library "tsl18fs120_scl_ss.db tsl18cio250_max.db dpram_256x8_max.db"

set link_library "tsl18fs120_scl_ss.db tsl18cio250_max.db dpram_256x8_max.db"

Read verilog