16MVD0099

Vinod patil

vit university

vellore tamilnadu

Assignment-3

Question: Design a XOR-XNOR circuit in the following logic and compare the
following parameters.

Logic implementation in,

1) CMOS logic

2) Ratioed Logic

3) Dynamic logic

4) DCVSL Logic

5) Pass transistor Logic

Parameters to be calculated are Area (No of transistors), Power, Timing, and

PDP

Solution:

The XOR and XNOR gate functions are shown in table,

Logic expressions for XOR and XNOR are,

A XOR B = A'B+AB'

A XNOR B = A'B'+AB

A B
0 0
0 1
1 0
1 1
XOR XNOR
0 1
1 0
1 0
0 1
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CMOS logic:

Waveforms:
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Calculations:

Power 2.08 uW
Delay 49.98 ns
PDP(power delay product) 1.039*10-13
Area 14 transistors

Ratioed logic:
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Waveforms:

Calculations:

Power 137.40 uW
Delay 25.22 ns
PDP(power delay product) 3.45*10-12
Area 11 transistors

Dynamic logic:
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Waveforms:

Calculations:

Power 4.30 uW
Delay 63.68 ps
PDP(power delay product) 2.73*10-16
Area 12 transistors

DCVSL logic:
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Waveforms:

Calculations:

Power 2.61 uW
Delay 39.53 ps
PDP(power delay product) 1.03*10-16
Area 12 transistors

Pass transistor logic:

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Waveforms:

Calculations:

Power 1.87 uW
Delay 1.658 ps
PDP(power delay product) 3.10*10-18
Area 8 transistors
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Conclusion: from this assignment we implement XOR-XNOR function using

various logic. And from this we analyze pass transistor logic implementation is
efficient in terms of area, power, and delay.