Beruflich Dokumente
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MT7620
DATASHEET
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
DSMT7620_V.1.3_091212 Page 1 of 54
Overview
The MT7620 router-on-a-chip includes an 802.11n MAC and baseband, a 2.4 GHz Applications:
radio and FEM, a 580 MHz MIPS 24K CPU core, a 5-port 10/100 switch and two Routers
RGMII. The MT7620 includes everything needed to build an AP router from a NAS devices
single chip. The embedded high performance CPU can process advanced iNICs
applications effortlessly, such as routing, security and VoIP. The MT7620 also Dual band
includes a selection of interfaces to support a variety of applications, such as a concurrent routers
USB port for accessing external storage.
Features
Embedded MIPS24KEc (580 MHz) with 64 KB I- An optimized PMU
Cache and 32 KB D-Cache Green AP
2T2R 2.4 GHz with 300 Mbps PHY data rate Intelligent Clock Scaling (exclusive)
Legacy 802.11b/g and HT 802.11n modes DDRII: ODT off, Self-refresh mode
20/40 MHz channel bandwidth SDRAM: Pre-charge power down
Legacy 802.11b/g and HT 802.11n modes I2C, I2S, SPI, PCM, UART, JTAG, MDC, MDIO, GPIO
Reverse Data Grant (RDG) Hardware NAT with IPv6 and 2 Gbps wired speed
Maximal Ratio Combining (MRC) 16 Multiple BSSID
Space Time Block Coding (STBC) WEP64/128, TKIP, AES, WPA, WPA2, WAPI
16-bit SDRAM up to 64 Mbytes QoS: WMM, WMM-PS
16-bit DDR1/2 up to 128/256 Mbytes (MT7620A) WPS: PBC, PIN
SPI, NAND Flash/SD-XC Voice Enterprise: 802.11k+r
1x USB 2.0, 1x PCIe host/device AP Firmware: Linux 2.6 SDK, eCOS with IPv6
5-port 10/100 SW and two RGMII RGMII iNIC Driver: Linux 2.4/2.6
Ordering Information
Ralink Technology Corp. (USA) Ralink Technology Corp. (Taiwan) Part Package
st
Suite 200 5F, 5 Taiyuan 1 St Number (Green/RoHS Compliant)
20833 Stevens Creek Blvd. Jhubei City, Hsinchu MT7620A TFBGA 265 ball
Cupertino CA95014, U.S.A Taiwan, R.O.C (11 mm x 11 mm)
Tel: 408-725-8070 Tel: 886-3-560-0868 MT7620N DR-QFN 148 pin
Fax: 408-725-8069 Fax: 886-3-560 (12 mm x 12 mm)
www.ralinktech.com
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Table of Contents
1. MAIN FEATURES 6
2. PINS 7
2.1 TFBGA (11 MM X 11 MM) 265 BALL PACKAGE DIAGRAM 7
2.1.1 DDR2 BALL MAP 7
2.2 DR-QFN (12 MM X 12 MM) 148-PIN PACKAGE DIAGRAM 8
2.2.1 LEFT SIDE VIEW 8
2.2.2 RIGHT SIDE VIEW 9
2.3 PIN DESCRIPTIONS (TFBGA) 11
2.4 PIN DESCRIPTIONS (DRQFN) 17
2.5 PIN SHARING SCHEMES 22
2.5.1 GPIO PIN SHARE SCHEME 22
2.5.2 UARTF PIN SHARE SCHEME 24
2.5.3 RGMII PIN SHARE SCHEMES 25
2.5.4 WDT_RST_MODE PIN SHARE SCHEME 25
2.5.5 PERST_N PIN SHARE SCHEME 25
2.5.6 MDC/MDIO PIN SHARE SCHEME: 25
2.5.7 EPHY_LED PIN SHARE SCHEME 26
2.5.8 SPI PIN SHARE SCHEME 26
2.5.9 ND/SD PIN SHARE SCHEME 27
2.5.10 XMII PHY/MAC PIN MAPPING 29
2.6 BOOTSTRAPPING PINS DESCRIPTION 30
3. MAXIMUM RATINGS AND OPERATING CONDITIONS 31
3.3 ABSOLUTE MAXIMUM RATINGS 31
3.4 MAXIMUM TEMPERATURES 31
3.5 OPERATING CONDITIONS 31
3.6 THERMAL CHARACTERISTICS 31
3.7 STORAGE CONDITIONS 32
3.8 EXTERNAL XTAL SPECFICATION 32
3.9 DC ELECTRICAL CHARACTERISTICS 32
3.10 AC ELECTRICAL CHARACTERISTICS 33
3.10.1 SDRAM INTERFACE 33
3.10.2 DDR2 SDRAM INTERFACE 34
3.10.3 RGMII INTERFACE 36
3.10.4 MII INTERFACE (25 MHZ) 37
3.10.5 RVMII INTERFACE (PHY MODE MII TIMING) (25 MHZ) 38
3.10.6 SPI INTERFACE 39
2
3.10.7 I S INTERFACE 40
3.10.8 PCM INTERFACE 41
3.10.9 POWER ON SEQUENCE 42
3.11 PACKAGE PHYSICAL DIMENSIONS 43
3.11.1 TFBGA (11 MM X 11 MM) 265 BALLS 43
3.11.2 DR-QFN (12 MM X 12 MM) 148LD 45
3.11.3 MT7620 N/A MARKING 48
3.11.4 REFLOW PROFILE GUIDELINE 49
4. ABBREVIATIONS 50
5. REVISION HISTORY 53
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Table of Figures
FIGURE 2-1 DR-QFN PIN DIAGRAM (LEFT VIEW) .............................................................................................................. 9
FIGURE 2-2 DR-QFN PIN DIAGRAM (RIGHT SIDE VIEW) ................................................................................................... 10
FIGURE 2-3 MII MII PHY ..................................................................................................................................... 29
FIGURE 2-4 RVMII MII MAC ................................................................................................................................ 29
FIGURE 2-5 RGMII RGMII PHY ............................................................................................................................. 29
FIGURE 2-6 RGMII RGMII MAC ........................................................................................................................... 29
FIGURE 3-1 SDRAM INTERFACE .................................................................................................................................. 33
FIGURE 3-2 DDR2 SDRAM COMMAND ....................................................................................................................... 34
FIGURE 3-3 DDR2 SDRAM WRITE DATA ...................................................................................................................... 34
FIGURE 3-4 DDR2 SDRAM READ DATA ....................................................................................................................... 34
FIGURE 3-5 RGMII INTERFACE .................................................................................................................................... 36
FIGURE 3-6 MII INTERFACE ......................................................................................................................................... 37
FIGURE 3-7 RVMII INTERFACE ..................................................................................................................................... 38
FIGURE 3-8 SPI INTERFACE ......................................................................................................................................... 39
FIGURE 3-9 I2S INTERFACE ......................................................................................................................................... 40
FIGURE 3-10 PCM INTERFACE ..................................................................................................................................... 41
FIGURE 3-11 POWER ON SEQUENCE ............................................................................................................................ 42
FIGURE 3-12 TFBGA TOP VIEW .................................................................................................................................. 43
FIGURE 3-13 TFBGA SIDE VIEW.................................................................................................................................. 43
FIGURE 3-14 TFBGA A EXPANDED ........................................................................................................................... 43
FIGURE 3-15 TFBGA BOTTOM VIEW............................................................................................................................ 44
FIGURE 3-16 TFBGA B EXPANDED ........................................................................................................................... 44
FIGURE 3-17 DR-QFN TOP VIEW ................................................................................................................................ 45
FIGURE 3-18 DR-QFN SIDE VIEW ............................................................................................................................... 45
FIGURE 3-19 DR-QFN B EXPANDED ......................................................................................................................... 45
FIGURE 3-20 DR-QFN BOTTOM VIEW ......................................................................................................................... 46
FIGURE 3-21 DR-QFN A EXPANDED ......................................................................................................................... 46
FIGURE 3-22 MT7620N TOP MARKING ........................................................................................................................ 48
FIGURE 3-23 MT7620A TOP MARKING ........................................................................................................................ 48
FIGURE 3-24 REFLOW PROFILE FOR MT7620 ................................................................................................................ 49
List of Tables
TABLE 1-1 MAIN FEATURES........................................................................................................................................... 6
TABLE 2-1 DDR2 BALL MAP ......................................................................................................................................... 8
TABLE 3-1 ABSOLUTE MAXIMUM RATINGS .................................................................................................................... 31
TABLE 3-2 MAXIMUM TEMPERATURES .......................................................................................................................... 31
TABLE 3-3 OPERATING CONDITIONS ............................................................................................................................. 31
TABLE 3-4 THERMAL CHARACTERISTICS ......................................................................................................................... 31
TABLE 3-5 EXTERNAL XTAL SPECIFICATIONS .................................................................................................................... 32
TABLE 3-6 DC ELECTRICAL CHARACTERISTICS .................................................................................................................. 32
TABLE 3-7 VDD 2.5V ELECTRICAL CHARACTERISTICS ........................................................................................................ 32
TABLE 3-8 SDRAM INTERFACE DIAGRAM KEY ................................................................................................................ 33
TABLE 3-9 DDR2 SDRAM INTERFACE DIAGRAM KEY ...................................................................................................... 35
TABLE 3-10 RGMII INTERFACE DIAGRAM KEY ................................................................................................................ 36
TABLE 3-11 MII INTERFACE DIAGRAM KEY .................................................................................................................... 37
TABLE 3-12 RVMII INTERFACE DIAGRAM KEY ................................................................................................................ 38
TABLE 3-13 SPI INTERFACE DIAGRAM KEY ..................................................................................................................... 39
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1. Main Features
The following table covers the main features offered by the MT7620N and MT7620A. Overall, the MT7620N
supports the requirements of an entry-level AP/router, while the more advanced MT7620A supports a number
of interfaces together with a large maximum RAM capacity.
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2. Pins
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26
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
5
DDR_I SOC_C SOC
DDR EPHY MDI MDI MDI_ MDI
MDQ MDQ O O _IO EPHY
N MA4 _IOC MA13 GND _V33 _TN_ _TP_P RP _RN_ N
S1 M1 _V18 _V12D _V33D _V33A
_V12D A P3 3 _P4 P4
D _2 _2
ND_CL
DDR E/ SD ND_W MDI_ MDI MDI_ MDI
MCK_ MCK_ ND_CS_
P MA6 MA8 MA12 MA7 _IO _CARD P/ SD DSR _N RXD TXD2 TP _TN_ RP _RN_ P
P N N
_V18D _DETE _WP _P2 P2 _P2 P2
CT
ND_AL
ND_RB_ ND EPHY MDI_ MDI
ND_RE E/
R MD5 MD2 MA11 MA9 MA5 MA3 MBA2 N/ _WE TXD RTS_N RXD2 _RES RP _RN_ R
_N SD_CM
SD_CLK _N _VBG _P1 P1
D
ND_D4
ND_D6/ ND_D2 ND MDI MDI_ MDI
MWE / DCD I2C_S
T MD0 MD6 MD4 MDQS0 MA1 MBA1 BT / _D0/ RIN _RN_ TP _TN_ T
_N BT_ST _N D
_WACT SD_D2 SD _D0 P0 _P1 P1
AT
ND_D5
ND_D3 ND MDI_ MDI MDI
MDQM ND_D7/ / DTR I2C
U MD7 MD1 MD3 MA10 MBA0 MCKE / _D1/ CTS_N RP _TP_P _TN_ U
0 BT_ANT BT_AU _N _SCLK
SD_D3 SD _D1 _P0 0 P0
X
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
SOC_CO_V12D_0
ADC_VX _LDO
RF0_VX _LDO
PLL_VX_LDO
WDT_RST_N
BBPLL_V12A
PLL_VC_CAP
XTAL_V12A
ANT_TRNB
PA_PE_G1
PA_PE_G0
ANT_TRN
BG_V33A
PORST_N
BG_EXTR
XTAL_XO
XTAL_XI
GPIO0
NC
NC NC 74 73 72 71 70 69 68 67 66
NC 148 147 146 145 144 143 142 141 140 139
NC PLL S oC
RF0_OUTP 75
RF0_PA2_V33N 1
RF0_OUTN 76
RF0_PA1_V33A 2
GND 77 RF
RF1_VX_LDO 3
NC 78
RF1_OUTP 4
RF1_PA2_V33N 79
RF1_OUTN 5
RF1_PA1_V33A 80
SOC_IO_V33D_1 6
WLED_N 81
EPHY_LED3_N_JTCLK 7
EPHY_LED0_N_JTDO 82
EPHY_LED1_N_JTDI 8
LED
EPHY_LED2_N_JTMS 83
EPHY_LED4_N_JTRST_N 9
SOC_CO_V12D_1 84
VDD18 VDD25 10
DDR_DQ14 DDR_DQ15 85
DDR_DQ9 DDR_DQ14 11
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DDR_DQ12 DDR_DQ13 86
DDR_DQ11 DDR_DQ12 12
DDR_DQ10 DDR_DQ11 87
DDR_DQ13 DDR_DQ10 13
DRAM
DDR_DQ8 DDR_DQ9 88
DDR_DQ15 DDR_DQ8 14
DDR_DQS1 DDR_DQS1 89
DDR_DQM1 DDR_DQM1 15
MCK_P MCK_N 90
MCK_N MCK_P 16
DDR_VREF DDR_VREF 91
DDR_ODT DDR_MA4 17
DDR_RAS_N DDR_MA5 92
DDR_IOC_V12D DDR_IOC_V12D 18
VDD18 VDD25 93
NC DRAM
NC 94 95 96 97 98 99 100 101 102
NC NC DDR _MA6 19 20 21 22 23 24 25 26 27
DDR _MA7
DDR _MA8
DDR _MA9
DDR _MA11
DDR _MA12
DDR_CKE
DDR_DQ0
DDR_DQ1
DDR_DQ2
DDR_DQ3
DDR_DQ4
DDR_DQ5
DDR_DQ6
DDR_DQ7
DDR_ODT
VDD25
DDR_IOC_V12D
DDR_ CAS_N
DDR_DQ5
DDR_DQ2
DDR_DQ0
DDR_DQ7
DDR_DQ6
DDR_DQ1
DDR_DQ4
DDR_DQ3
DDR_CS_N
DDR_MA0
DDR_MA2
DDR_MA4
DDR_MA6
DDR_MA8
DDR_MA11
VDD18
DDR_IOC_V12D
Figure 2-1 DR-QFN Pin Diagram (left view)
EXT_LDO_DDR
DCDC_V33D
DCDC_V33A
APCK_V12A
APCK_V33A
SPI_HOLD
SPI_MOSI
SPI_MISO
VFB_DDR
SPI_CS0
SPI_CS1
SPI_CLK
SPI_WP
UGATE
LGATE
COMP
FB
65 64 63 62 61 60 59 58 57 56 NC NC
138 137 136 135 134 133 132 131 NC
SoC PCIE PMU 55 VFB_DIG
54 EXT_LDO_DIG
130 UPHY0_VRES
53 UPHY0_PADM
USB
129 UPHY0_V33A
52 UPHY0_PADP
128 UPHY0_V12D
51 SOC_CO_V12D_3
127 MDI_TN_P4
50 MDI_TP_P4
126 MDI_RN_P4
49 MDI_RP_P4
125 MDI_RN_P3
48 MDI_RP_P3
124 MDI_TN_P3
47 MDI_TP_P3
123 EPHY_V12A
46 MDI_TN_P2
122 EPHY_V33A
45 MDI_TP_P2
EPHY
121 MDI_RN_P2
44 MDI_RP_P2
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120 EPHY_PLL_V12A
43 EPHY_RES_VBG
119 EPHY_V33A
42 MDI_RN_P1
118 MDI_RP_P1
41 MDI_TN_P1
117 EPHY_V33A
40 MDI_TP_P1
116 MDI_TN_P0
39 MDI_TP_P0
115 MDI_RN_P0
38 MDI_RP_P0
114 EPHY_V12A
37 RXD2
113 TXD2
DRAM NC
103 104 105 106 107 108 109 110 111 112 NC
28 29 30 31 32 33 34 35 36 NC NC
SOC_IO_V33D_
DDR_MA3
DDR_MA2
DDR_MA1
DDR_MA0
DDR_MA10
DDR_BA1
DDR_BA0
DDR_DQS0
DDR_DQM0
VDD25
DDR_RAS_N
DDR_VREF
I2C_SCLK
I2C_SD
DDR_CS_N
DDR_CAS_N
DDR_WE_N
SOC_CO_V12D
1
DDR_MA9
DDR_MA5
DDR_MA3
DDR_MA1
DDR_BA0
DDR_DQS0
DDR_DQM0
VDD18
DDR_MA12
DDR_MA7
DDR_MA10
DDR_BA1
DDR_VREF
DDR_WE_N
DDR_CKE
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NOTE:
1. Pin types marked with an * indicate that they are available only in the TFBGA package.
2. Ball mapping for these pins is shown in the DDR2 Ball Map table in section 2.3.1. For information on DDR1
ball mapping, see section 2.3.2.
3. Ball mapping for these pins is shown in the DDR2 Ball Map table in section 2.3.1. For information on DDR1
ball mapping, see section 2.3.2.
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NOTE:
IPD : Internal pull-down
IPU : Internal pull-up
I : Input
O : Output
IO : Bi-directional
P : Power
G : Ground
NC : Not connected
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MII RvMII
GE0_RXCLK RXCLK GE0_RXCLK RXCLK
Figure 2-3 MII MII PHY Figure 2-4 RvMII MII MAC
RGMII RGMII
GE0_RXCLK RXCLK GE0_RXCLK TXCLK
GE0_RXCTL RXCTL/RXDV GE0_RXCTL TXCTL/TXEN
GE0_RXD[3:0] RXD[3:0] GE0_RXD[3:0] TXD[3:0]
MDC MDC MDC MDC
MDIO MDIO MDIO MDIO
Figure 2-5 RGMII RGMII PHY Figure 2-6 RGMII RGMII MAC
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MT7620N:
Thermal Resistance JA (C /W) for JEDEC 2L system PCB 20.14 C/W
Thermal Resistance JA (C /W) for JEDEC 4L system PCB 17.19 C/W
Thermal Resistance JC (C /W) for JEDEC 2L system PCB 7.29 C/W
Thermal Resistance JC (C /W) for JEDEC 4L system PCB 6.14 C/W
Thermal Resistance Jt (C /W) for JEDEC 2L system PCB 2.02C/W
Thermal Resistance Jt (C /W) for JEDEC 4L system PCB 1.84C/W
MT7620A:
Thermal Resistance JA (C /W) for JEDEC 2L system PCB 26.67 C/W
Thermal Resistance JA (C /W) for JEDEC 4L system PCB 24.9 C/W
Thermal Resistance JC (C /W) for JEDEC 2L system PCB 9.89 C/W
Thermal Resistance JC (C /W) for JEDEC 4L system PCB 9.75 C/W
Thermal Resistance Jt (C /W) for JEDEC 2L system PCB 4.31C/W
Thermal Resistance Jt (C /W) for JEDEC 4L system PCB 4.19C/W
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SDRAM CLK
t_IN_SU t_IN_HD
SDRAM_INPUT
SDRAM_OUTPUT
t_OUT_VLD
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MDQS
tDS tDH
MD D1 D2 D3 D4
tDS tDH
MDQM
tRPRE tRPST
MDQS
MD D1 D2 D3
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NOTE: Depends on slew rate of DQS and DQ/DQM for single ended DQS.
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GE0_TXCLK
t_TX_HD
GE0_TXD/TXCTL
t_TX_SU
GE0_RXCLK
t_RX_HD
GE0_RXD/RXCTL
t_RX_SU
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t_RXCK
Receive:
MII RXCLK
t_RX_SU t_RX_HD
RXDV,RXD
t_TXCK
Transmit:
MII TXCLK
TXEN,TXD
t_TX_delay
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t_TXCK
Receive:
MII TXCLK
t_TX_SU t_TX_HD
TXEN,TXD
t_RXCK
Transmit:
MII RXCLK
RXDV,RXD
t_RX_delay
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SPI_CLK
SPI_CS
SPI_MOSI
Read operation (Driven by clock rising edge (slave-device) and latched by clock rising edge)
SPI_CLK
SPI_CS
SPI_MISO
t_SPI_IS t_SPI_IH
NOTE: 1) SPI_CLK is a gated clock.
2) SPI_CS is controlled by software
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2
3.10.7 I S Interface
Transmitter
SCK
WS & SD
Receiver
SCK
WS & SD
t_I2S_IS t_I2S_IH
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PCMCLK
DTX
t_PCM_OVLD
PCMCLK
DRX &
FSYNC
t_PCM_IS t_PCM_IH
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3.3 V
2.6 V
VDD33
1.5 V
SW_REG
1.27 V
LDO_DIG
1.8 V
LDO_DDR
T3 T4
T1 T2
3.3 V
PORST_N
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MEDIATEK
MT7620N
YYWW-XXXX
LLLLLLLLL
MEDIATEK
MT7620A
YYWW-XXXX
LLLLLLLLL
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Notes;
1. Reflow profile guideline is designed for SnAgCulead-free solder paste.
2. Reflow temperature is defined at the solder ball of package/or the lead of package.
3. MTK would recommend customer following the solder paste vendors guideline to design a profile
appropriate your line and products.
4. Appropriate N2 atmosphere is recommended since it would widen the process window and mitigate the risk
for having solder open issues.
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4. Abbreviations
Abbrev. Description Abbrev. Description
AC Access Category CLK Clock
ACK Acknowledge/ Acknowledgement CPU Central Processing Unit
ACPR Adjacent Channel Power Ratio CRC Cyclic Redundancy Check
AD/DA Analog to Digital/Digital to Analog CSR Control Status Register
converter CTS Clear to Send
ADC Analog-to-Digital Converter CW Contention Window
AES Advanced Encryption Standard CWmax Maximum Contention Window
AGC Auto Gain Control CWmin Minimum Contention Window
AIFS Arbitration Inter-Frame Space DAC Digital-To-Analog Converter
AIFSN Arbitration Inter-Frame Spacing DCF Distributed Coordination Function
Number
DDONE DMA Done
ALC Asynchronous Layered Coding
DDR Double Data Rate
A-MPDU Aggregate MAC Protocol Data Unit
DFT Discrete Fourier Transform
A-MSDU Aggregation of MAC Service Data
DIFS DCF Inter-Frame Space
Units
DMA Direct Memory Access
AP Access Point
DSP Digital Signal Processor
ASIC Application-Specific Integrated Circuit
DW DWORD
ASME American Society of Mechanical
Engineers EAP Expert Antenna Processor
ASYNC Asynchronous EDCA Enhanced Distributed Channel Access
BA Block Acknowledgement EECS EEPROM chip select
BAC Block Acknowledgement Control EEDI EEPROM data input
BAR Base Address Register EEDO EEPROM data output
BBP Baseband Processor EEPROM Electrically Erasable Programmable
Read-Only Memory
BGSEL Band Gap Select
eFUSE electrical Fuse
BIST Built-In Self-Test
EESK EEPROM source clock
BSC Basic Spacing between Centers
EIFS Extended Inter-Frame Space
BJT
EIV Extend Initialization Vector
BSSID Basic Service Set Identifier
EVM Error Vector Magnitude
BW Bandwidth
FDS Frequency Domain Spreading
CCA Clear Channel Assessment
FEM Front-End Module
CCK Complementary Code Keying
FEQ Frequency Equalization
CCMP Counter Mode with Cipher Block
Chaining Message Authentication FIFO First In First Out
Code Protocol FSM Finite-State Machine
CCX Cisco Compatible Extensions GF Green Field
CF-END Control Frame End GND Ground
CF-ACK Control Frame Acknowledgement GP General Purpose
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5. Revision History
This product is not designed for use in medical and/or life support applications. Do not use this product in these
types of equipment or applications. This document is subject to change without notice and Ralink assumes no
responsibility for any inaccuracies that may be contained in this document. Ralink reserves the right to make
DSMT7620_V.1.3_091212 Page 53 of 54
changes in its products to improve function, performance, reliability, and to attempt to supply the best product
possible.
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