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What is the impact Interview with Dr. William Chen of ASE
of Xilinxs 3D Yole Dveloppement recently had an opportunity to interview William (Bill) Chen
silicon interposer about his long career in microelectronics packaging and his current activities as
announcement? a part of ASE.
Yole Dveloppement: Dr Chen before we start new. I learned how to do engineering from concept
Xilinx made a big announcement last
our questions on ASE, can you share a little on nucleation, feasibility demonstration, and product
month when announcing their intention
to commercialize 3D silicon interposers your past history. Its our understanding that development to manufacturing. I spent over 33 years
based on TSV interconnects for their next- you had a full career at IBM before coming to at IBM in various technical and R&D management
generation 28nm FPGAs in their Virtex 7 ASE and that you just finished two terms as positions. After retirement, I joined the Institute of
future product line. President of the IEEE Component, Packaging Materials Research and Engineering (IMRE) in
and Manufacturing Technology Society (CPMT). Singapore. My initial role at IMRE was to establish a
Lets look at why this announcement is so Can you fill us in on this part of your past? research program in Electronic Packaging within this
important: To begin with, Xilinx is the first
large semiconductor company to jump into young Research Institute. As it turned out I became
Bill Chen: After I completed my PhD studies the Director of IMRE, nurturing the young Institute to
the free space of 3D integration in the logic
area. Its quite impressive that a fabless at Cornell University, I started working at the become the premier materials research institute in
company is taking the first big step in this IBM Development Laboratory in Endicott New the region. I retired from IMRE to join ASE in 2000.
new direction for manufacturing. Indeed, York. It was still at an early point in the history of I was President of IEEE CPMT Society from 2006 to
Xilinx is kind of cleaning the pipeline so that electronics and certainly an exciting time at IBM. 2009. I am currently co-chair of the ITRS Assembly
other players can quickly follow in the FPGA I soon gravitated to work in electronic packaging.
10
and Packaging ITWG. I have been
and high-performance ASIC spaces. The science was intriguing and technology was elected a Fellow of ASME and IEEE.
To be continued on page 2
M
any companies are publicly discussing their Why I/O
3D IC integration roadmaps and the role interfaces?
wide input/output (I/O) interfaces will play.
For starters, South Korean-based electronics giant When asked whats
Samsung hails the wide I/O and through-silicon via fueling the drive to use
(TSV) combination as the best of both worlds in wide I/O interfaces
terms of achieving performance and thin multiple- for 3D ICs, answers
die stacks. vary slightly from
company to company
Memory maker Elpida, based in Tokyo, Japan, is but a theme is clearly
actively developing next-gen mobile wide I/O DRAM, emerging.
which expands the I/O interface bus width, and Wide I/O interface with TSV for Mobile processors
mounting technologies that use TSVs. In fact, Elpida As handheld devices become increasingly more (Courtesy of Texas Instruments)
has installed a production line at its Hiroshima Plant sophisticated, applications are emerging that
to develop TSV and mass production technologies require much higher memory bandwidth, says
for multiple connections using TSVs. Jeff Brighton, director of CMOS 3DIC technology
development at Texas Instruments (TI; Dallas,
C O N TE N TS
And Nokia, an Espoo, Finland-based leader in Texas). However, fundamental power and thermal
the transformation and growth of the converging limitations remain the same as in todays handsets.
The initial version of a wide I/O memory interface EVE N TS 2
Internet and communications industries, describes
the evolution of 3D IC integration as moving from will deliver 12.8GB/s of memory bandwidthwhile
keeping the processor plus memory system-on- A N AL Y SIS 2
2.5 to true 3D, relying on various applications of
TSVs in silicon interposers, memories, and ICs. chip (SoC) power consumption under control, he
adds. ... COMPA NY v i s i o nS 6
2
The company plans to integrate wide I/O interface
structures using TSVs for mobile phones in volume
by 2013. A N AL Y ST C OR N ER 2 2
platinum partners:
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NOVEMBER 2010 i s s u e n 1 7
Newsletter on 3D IC, T S V, WLP & Embedded Te c h n o l o g i e s
E D I T O R I A L a n a l y sis
events
3-D Architectures for Semiconductor
Integration and Packaging
December 8 to 10, 2010 - Burlingame, CA
EPTC
December 8 to 10, 2010 - Shangri-La Hotel,
Singapore
IC Packaging Technology Expo
January 19 to 21, 2011 - Tokyo, Japan Nokias Wide I/O interface between logic and DRAM memories with need TSV interconnects to meet the next
generation performance requirements (Courtesy of Nokia)
gold partners:
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Newsletter on 3 D I C , TSV , WLP & E m b e d d e d T e c h n o l o g i e s
And Kauppi Kujala, senior technology manager at Networking is the application thats driving Avagos interest
Nokia R&D, sums it all up: Wide I/O performance in wide I/O. 3D integration makes a wide memory
target assumptions include 12.8GB/s, peak interface spatially possible, while drastically reducing I/O power,
bandwidth, 4-channel SDRAM x128 200MHz-
type interface, 1.2V LVCMOS look-alike, power explains Pete ONeill, Avago Technologies
approximately 500mW (which offers a large power
savings compared to LPDDR2), with a maximum Such a high number of interconnections cant Dorsey and Rahman say that Xilinxs
DRAM memory die count of 4. be done through a traditional package, such as customers, encompassing aerospace and defense,
package-on-package (PoP), where the ball pitch communications, medical, test and measurement,
Whats driving wide I/O?
is in the range of 0.5 or 0.4mm. Dies need to be high-performance computing, and ASIC prototyping
The key driver behind wide I/O right now is that the
mobile phone industry is embracing it as a solution
to combine processors with memories, especially
for high-end smartphones and connected devices.
Smartphone marketshare has soared from less
than 5% a few years ago to nearly 30% today.
And devices such as tablets, e-readers, or
netbooks are also appearing and bringing along
demanding needs for high bandwidth data without
major power penalties. The web experience is
being redefined with the mobile phone, and HD is
moving from our home environment and becoming
mobile. As a consequence, the computing power
of new application processor engines (APE) and
multicore CPUs is growing and the latest solutions
are being defined to run well above 1GHz, Guillou
says. Similarly, the multimedia performance of
these APE will need to deliver features such as
HD 1080p encode/decode with 60fps or even
higher, dual density, 3D graphics, etc. To deliver
this performance, the wide I/O interface is one
technology of interest. Nokias next generation mobile phones and tablet systems will need wide I/O interface based 3DICs with
TSV interconnects for high bandwidth, low power consumption (Courtesy of Nokia)
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Newsletter on 3 D I C , TSV , WLP & E m b e d d e d T e c h n o l o g i e s
Standardization?
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Standards body JEDEC is among those leading companies, especially since using a temporary assembly process. If this isnt achieved, cost may
important standardization activities for wide I/O, carrier to ensure rigidity of the thin wafer stacks be a potential showstopper, he cautions.
and companies such as OEMS, memory providers, would be necessary. If carriers are used, some
chipset suppliers, and test, packaging, and IP houses agreements should be redefined between foundries
are also deeply involved in the process, notes Guillou. and packaging housesespecially regarding the While there will be supply chain challenges,
Nokia is among those participating in JEDECs wide bonding/debonding process. This is a key step in the well be working on them, says Kujala. Mobile
I/O standardization work, and Kujala says that their process that also needs standardization. products are extremely performance hungry and
preference is to follow JEDECs lead. Based on the performance is the driver behind wide I/O. There
standard, there will be an offering by IC suppliers, From Brightons perspective, chip suppliers and is already consensus in the industry that wide I/O
he explains. For the whole 3DIC technology OSATs must collaborate more closely to meet is needed. To fulfill that needed performance, the
development, having a standard is a positive step, customers requirements. As an industry, we have industry will make it happen.
and Nokia sees this activity as one of the first challenges about the compatibility of processes and
common targets for the entire industry. materials used by different foundries and OSATs, he
says.
Xilinx is also working with industry groups including
Imec, Sematech, and SEMI to help promote and Another challenge Cheung sees is timing. How
support standardization in this area, according to quickly and effectively the industry can come up
Dorsey and Rahman. with cost-effective assembly equipment and an Sally Cole Johnson for Yole Dveloppement
Nearly everyone involved in 3D integration cites the Yann Guillou leads 3D and Arif Rahman is a principal
advanced packaging in the CTO engineer and technology architect
supply chain as their major practical concern, points
and Strategic Planning Office at ST- at Xilinx Inc., where he has
out ONeill. Its not at all clear how the established incubated R&D programs, leading
Ericsson. Guillou began his career
players will divide the new functions and whether at CEA-LETI and then worked at to successful technology transfer
new players will fill in the gaps, he says. The supply STMicroelectronics and ST-NXP. for commercialization. With more
chain is particularly difficult for fabless companies He holds a MSc. in materials and than 10 years experience in digital,
that need suppliers for new operations such as TSV nanotechnology from the National Institute of mixed-signal, and sensor design, development, and
Applied Sciences, and a Masters in Management of supply chain evaluation, he has worked in all aspects
formation and die-to-wafer bonding that neither the of 3D ICs. He holds a Ph.D. in electrical engineering
Technology and Innovation from Grenoble Business
foundries nor OSATS currently provide. from Massachusetts Institute of Technology and an
School, France.
MBA from Santa Clara University.
A good example in terms of whos responsible Kauppi Kujala is the senior
for what: Guillou expects via middle TSV is the technology manager at Nokia Jeff Brighton is a TI Fellow and manages the
technology option the industry is most likely to select, R&D. Kujala has worked at Nokia CMOS 3DIC technology development program
since 1999. Prior to that, he was a for Texas Instruments. During more than 25 years
with the TSV process run in foundries between at TI, Brighton has been a key technical leader in
FEOL and BEOL. TSV will be embedded within a project engineer at VTI Technology.
He holds a M.Sc. in materials process development and volume ramp for more
regular thickness CMOS wafer, he explains. To science from Helsinki University of than 10 generations of CMOS technology. He
make the TSV emerge and connect the logic die with Technology. helped pioneer TIs flexible, internal and external
the memory, the logic wafer will need to be thinned manufacturing model for advanced CMOS
technology and also directed TIs 45nm and 28nm
to a few 10s of microns. Depending on what point
low power CMOS development programs prior to his
in the chain the foundry stops and the assembly role with TIs 3DIC program. He graduated from the
begins, very thin wafers or stacks will be manipulated University of Illinois at Urbana Champaign with a MS
and exchanged between foundries and assembly degree in electrical engineering.
houses. These aspects are an area of concern for
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c o mp a ny v i s i o n
W
hile process experts are confident to 3D-ready with the TSVs and their drivers and If implemented in separate ICs, every one of these
continue on the shrink-path for a few receivers included in the layout, instead of the functions can benefit from cost-effective, dedicated
more generations, the challenging design much larger I/O buffers and bonding pads. process technologies. This benefit also applies
requirements and costly manufacturing equipment to all four More than Moore alternatives and is
triggered the search for alternatives to shrinking of Facing these 3D challenges, creative engineers essential to produce highly integrated solutions
2-dimensional SoCs. developed a less demanding interposer-based cost-effectively.
alternative and called it 2D, indicating its
The first viable 3-dimensional alternatives started place between 2D SoCs and 3D stacked dice. A Applying this fifth technical criteria to one large
to gain market share about five years ago. PoP key advantage of the 2D technology is that it can SoC, the most common alternative today, shows
(Package-on-Package) and SiP (System-in- utilize flip-chip dice, mounted side by side on an that significant technical challenges arise. Despite
Package) demonstrated space and/or power interposer or face-to-face with an interposer in very flexible and capable process technologies
savings, compared to implementing the same between. and design tools, the implementation of logic and
functions in multiple 2-dimensional SoCs. memory and/or analog, is not as easy as dedicated
To give an overview of all these technologies, their processes can enable and often forces relaxing of
To gain more from utilizing the 3rd dimension, benefits and trade-off, Table 1 below shows in six specifications.
leading edge companies focused on thinning columns major implementation alternatives IC-
wafers to less than 50 microns and started to or system designers can choose from and applies First business criteria (Time to Profit): It gets
interconnect bare dice with TSVs (Through Silicon five technical criteria and two business criteria increasingly difficult and time consuming to
Vias). This 3D/TSV stacks were even faster, smaller to compare these technologies. integrate all functions needed into one large SoC
and consumed less power than SiP solutions. and manufacture the design cost-effectively in a
The two More Moore alternatives universal process technology. Design iterations
As leading edge wafer foundries and OSATs on the left and yield enhancement efforts can further delay
(OutSourced Assembly and Test houses) engaged the product introduction, increase time to profit and
in the development of the necessary manufacturing The first four technical criteria (speed, power, reduce profit margins.
flows and encouraged their equipment vendors form factors) are self-explanatory.
to meet the demanding new requirements, it Distributing the functions into multiple ICs allows
became clear that 3D/TSV technology offered The fifth criteria Heterogeneous Technology more reuse, reduces the application-specific
many compelling benefits but still required Mix refers to designs comprised of significant development efforts and helps to get to market
development efforts to become cost-effective in amounts of logic, large memories and/or analog / and profit faster.
volume production. Also, to fully utilize the 3D/TSV RF components, MEMS, sensors, etc.
benefits, the individual dice need to be designed However, many applications need higher
performance or dont allow the power budget or
space required for multiple SoCs.
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www.eda2asic.info
MOLECULES TO BUILD ON
Also, please join Claudio Truzzi, Alchimers Chief Technology Officer, for his presentation,
An Integrated Wet-Process Solution to Isolate and Fill Through Silicon Vias:
Wednesday, Dec. 1, at 3:10 p.m. in Room 201, 2F,
Intl Conference Hall, Makuhari Messe.
alchimer.com
c o mp a ny v i s i o n
I
n the February 2010 Yole 3D Packaging
newsletter we discussed the advantages of
Xintec WL-CSP used by OmniVision/TSMCs
first back illuminated (BSI) image sensor. We were
excited by the iPhone 4 announcement in June
which included mention of a 5 Mp, 1.75 m pixel
pitch BSI camera module. Early speculation of
an OmniVision design win proved to be true and
one surprising find from the reverse engineering
analysis is yet another approach to BSI CIS
package integration.
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Newsletter on 3 D I C , TSV , WLP & E m b e d d e d T e c h n o l o g i e s
Apple iPhone 4 Rear Camera Die Bond Pad Region (Courtesy of Chipworks)
bond directly to the pads as we saw in the new 4th
generation iPod Touch 0.7 Mp BSI camera module.
In summary, with a little ingenuity CIS foundries and Jrme Baron leads Yoles Ray Fontaine has been
IDMs need not take on the cost and complexities of MEMS and Advanced a process analyst at
a TSV process for all applications. Contrasting the Packaging market research. Chipworks since 2001,
investment required for TSV integration in a 300 mm He has been involved in the specializing in image
wafer process, these devices show what is possible technology analysis of the 3D sensors. He has authored
packaging market evolution and technically reviewed
using 200 mm wafer fabs and a depreciated wire
at device, equipment, and numerous image sensor
bonding toolset. Given the low number of I/Os and material supplier levels. process review (IPR)
large pad pitch, BSI CIS represents a sweet spot for Baron earned a MSc. Degree reports.
gold stud bumping. in Micro and Nanotechnologies from the National
www.chipworks.com Institute of Applied Sciences in Lyon, France.
www.yole.fr
Disruptive technologies pave the way to the future of digital imaging industry!
MaRKEt tREnDs
the reason why we are now releasing the first report on cMos
image sensor industry is that we feel that we are at an historic
turning point of this young, but still maturing industry. says
Jrme Baron, technology & Market analyst, MEMs & advanced
Packaging.
Key technical insight about future technology trends & challenges: WLP (Wafer Level packaging)
3D TSV interconnects
WLO (Wafer Level Optics)
Image stabilization (MEMS Inertial)
YOLE DVELOPPEMENT
Wafer Level Camera & Molding Auto-focus (Piezo, liquid lense, MEMS)
contact us
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c o mp a ny v i s i o n
BC: You have hit the nail right on the head: technical
challenges and customer acceptance. Changing
from Au wire to Cu wire involves a whole set of
changes in materials, equipment, and manufacturing
processes. It took a lot of hard work and
(Courtesy of Ase Group) commitment from the top management to process
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Newsletter on 3 D I C , TSV , WLP & E m b e d d e d T e c h n o l o g i e s
engineers, and manufacturing operators to make that makes the ASE approach BC: We have test vehicles designed
the Cu wirebond qualification and implementation different or more reliable than your with our partners that have been
seamless for customers. ASE actively worked on competitors? generated for process evaluations in
fine pitch Cu wire bond technology for a number our R&D environment. Technology
BC: We are working with multiple
of years before starting high volume production in feasibility demonstrations and stress
partners on various Middle process
September of 2008. With gold price escalating, tests are on schedule for middle end
approaches for the assembly of die with
there is real cost benefit for the customers across and back end assembly processes.
TSVs into their final package assemblies.
a broad spectrum of products. Many technical and ASE will expand our capabilities for
ASE has developed a TSV formation
manufacturing challenges were addressed one by wafer level processing and assembly
process, middle end, and final package Dr Bill Chen,
one. This is indeed is a major step forward for the within 2011, aligning our schedule
assembly capability for 200mm wafers. Fellow and Senior
industry. We are proud that we have won over many to meet our customer development
300mm wafer capability is on schedule Technical Advisor, ASE
customers by providing them with solid reliability timeline requirements. At this time we
for next year. ASE has developed both
data and manufacturing track record. ASE will exit do not have products qualified.
copper solid fill and copper lining plating with polymer
2010 having shipped approximately 2 billion units,
isolation for the TSV processing for both via middle YD: When it comes to D2W bonding what is
with approximately 30% of our wirebond output
and via last. The polymer isolation provides better the thinnest chip you can currently handle?
allocated to copper. We expect the conversion rate
electrical performance and lower stress distribution What can you tell us about handling these
to exceed 70% within the next 2-3 years, and expect
than some alternative barrier and isolation techniques. thin die?
Au to be only a niche (<10%) after 2015.
Underfill materials and underfill application process
YD: Certainly many of our readers are following BC: We have good success with D2W bonding with
are also crucial parts of assembly for microbump
the emergence of 3D / TSV technology very 50m thick die using thermocompression bonding
interconnection of silicon dies with TSV.
closely. How would you describe overall 3D and NCF underfill. Engineering development has
status at ASE? What issues have been resolved YD: Many are assuming that the OSATS will demonstrated success with alternative approaches
and what issues are still to be solved? be responsible for bond, test and package. of die to substrate and die to memory stack
However, another option would be for the assembly for 3D stacked packages. For handling
BC: 3DIC / TSV offers significant advantages for OSATS to receive the wafers with TSV directly chips at this thickness, sawing tape, ejection
many customer applications in the market place, from the foundries and then be responsible for system & bonding tool design in TC bond, and die
from wireless to PC and server applications. ASE is everything else including thinning, backside flatness are keys for successful yields
collaborating closely with key customers and foundry processing, bond, test and package. Has this
partners to enable the full middle and backend process YD: Without telling us who, can you share
division of labor been determined between ASE
elements of 3D / TSV technologies. While basic anything about customer pull for 3D with
and the foundries. If you had to guess how you
process technology feasibility has been demonstrated, interposers and full 3D stacks?
expect this to play out?
there is still much work to do. Areas include material BC: We have talked to many customers. The
handling of thin wafers that require dual side BC: We have many customers working with different
strongest interests are in mobile processor and PC
patterning, warpage control, testing including ultra- foundries. We expect both business models to
applications. And the motivations are market driven
fine pitch probe, and overall cost of manufacturing. be in play. The issues of test, product liability
as you may expect.
Standards are needed for physical connection of the boundaries, as well as competitive supply chain
various IC elements in 3D structures. Co-design tools concerns will have an effect on each companys YD: What unresolved issues does ASE see in
must be ready. For TSV enabled integrated packages, decision regarding which model to employ. the infrastructure?
test will be a major challenge for the industry. YD: Are any of the required 3D unit operations BC: Works on various standards is slowly taking
YD: ASE has been a strong proponent of qualified yet at ASE? Can you share with us shape. Particularly important for us are those at the
interposers for the initial stages of full 3D IC which ones? When do you expect your full 300 interface connections.
stacking. Can you tell us something about mm line to be in place?
your interposer program and when we can
expect to see something in production? We
are hearing that single chip interposers for the
32 and 22 node will be an important interposer
application space is this correct? When can
we expect interposers applied to 3D stacks?
BC: Silicon interposer is a viable, if not critical,
enabler for addressing the CPI issue with CTE
mismatch between ELK silicon die and organic
substrate. We agree with you that 32 and 22 nm
node will be an important application space. It
will also be an important package solution for 3D
heterogeneous integration. We are working with
our foundry partners and our key customers on
a number of interposer package development
programs. For example, the interposer could
include a 3D memory stack in the architecture
design. In our view, production ramp will be
sometime in late 2012 or early 2013.
YD: What can you say about your standard 3D
process? Cu metal?, oxide liner?, Cu/Sn bonding?
underfill?, expected initial pitch ? Anything
(Courtesy of Ase Group)
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We will discuss the MotionIC platform, now available to help developers meet market demands
without having to deal with the complexities of sensor combination and motion processing.
Register Today
To learn more and to register, please go to
to Explore the MotionIC platform
www.i-micronews.com/webcast or click here.
When: Wednesday, December 15
8:00 AM PST
Sponsored by Hosted by
Speakers:
Bruno Flament, CTO, Movea
Tim Kelliher, Customer Solutions Architect, Movea
Jean-Christophe Eloy, CEO, Yole Dveloppement
c o mp a ny
CMA3000v(Courtesy
i s i ofoVTI)
n
T
he company is a leading supplier of Yole Dveloppement: VTI is one of the very few utilizing dry etching of silicon instead of mechanical
acceleration, inclination and angular motion MEMS companies using a Through-Glass Vias machining. The process is scalable for larger wafer
sensor solutions for transportation, medical, technology for its 3-axis accelerometer. Why sizes. It is used for all VTI MEMS designs.
instrument and consumer electronics applications. using glass wafers instead of Si?
VTI develops and produces silicon-based capacitive Anssi Korhonen : We are actually using a silicon YD: VTI has recently achieved the smallest
sensors using its proprietary 3D MEMS (Micro wafer and molten glass material for isolation of accelerometer on the market (2x2 mm). Do you
Electro-Mechanical System) technology. TSVs. Benefits of the VTI cap wafer technology plan to go even smaller?
include good insulation and very low parasitic (stray) AK: Smallest size components can be achieved
In 2009 VTI was the first MEMS company to adopt capacitance. Glass, on the other hand, provides with the Wafer Level Packaging (WLP) technology,
Wafer Level Packaging in the worlds smallest and planar surface and reliable bonding interface to which is close to WLCSP technology that has
least power consuming three-axis acceleration the structural wafer. Also, glass is very inexpensive received wide acceptance in the market. VTI WLP
sensor, the CMA3000, and the company has starting material, Mr. Korhonen explains. goes one step further by flip chip attaching ASIC on
already announced that it will launch new MEMS the MEMS sensing element.
solutions at Electronica 2010. YD: There are different ways to do TGV. What
Further size reduction is possible and restricted to
makes the VTI technology specific?
specific MEMS or ASIC design requirements, not so
Mr Anssi Korhonen, VTI Chief Technology Officer, AK: The process is VTI proprietary technology. We
much on packaging technology, Mr. Antti Korhonen
was interviewed for the MEMS Trend Magazine. avoid using plating processes in forming the vias. It is
concludes.
compatible for wafer level processing although needs
some specific equipment. Currently we are satisfied www.vti.fi
with the via resistance in the tens of ohms range.
Mr. Anssi Korhonen, M.Sc. in
YD: Is VTI Technologies planning to use its TGV electrical engineering, has worked
AK: The technology in its initial form (planar as Chief Technology Officer for
isolation and one via) has been in use since 1984. VTI Technologies since 2008.
In the late 90s due to requirements by multi-axis He has worked for electronics
accelerometers and gyros we added the capability manufacturing services industry
for a multitude of vias. More recently this technology since 15 years.
CMA3000 (Courtesy of VTI)
has been developing for finer pad pitch and size by
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SET collaborates with CEA-LETI, STMicroelectronics, SET has entered the JEMSiP-3D project to develop prevents oxygen intrusion while preserving the
ALES and the CEMES-CNRS on advanced chip- a high accuracy, high speed die bonder for the alignment of the device with respect to its substrate.
to-wafer technologies (direct metallic bonding) production of devices using 3D technology with high Consequently, it ensures an excellent wetting and
for 3D integration: history & content . density TSV. The goal is to introduce a die-to-wafer a higher quality of solder joints at reduced bonding
bonder with submicron placement accuracy with forces and temperatures as well as higher yield as
Direct copper-to-copper bonding requires a good stacking capability compatible with face-to-face or no cleaning step is required.
planarity and excellent surface quality especially in face-to-back alignment. A 2-Step approach with
terms of both particulate and metallic contamination. individual placement followed by a global bonding With the confinement chamber, the process gas is
The low roughness of the copper pillars and pad as sequence is favoured. injected through horizontal nozzles aimed at the
well as the topology between the copper and oxide device being bonded. An exhaust ring removes the
areas are critical to obtain good bond at low force process gas from the micro-chamber and sends it
and room temperature. The process is developed into the gas exhaust line, keeping the gas out of the
by CEA-LETI. ALES is supporting some specific machine and the clean room. A nitrogen curtain is
developments for the surface preparation. The formed around the exhaust, ensuring that ambient
CEMES-CNRS characterises the bond quality air is not entrained into the micro-chamber by the
especially concerning the copper structure evolution Venturi effect, while a deflector attached to the bond
upon annealing. STMicroelectronics is driving the head creates the confined micro-chamber. The
application of this technology for the high density 3D wafer acts as the deflector for D2W configuration
integration. when the chamber is attached to the bond head.
SET has developed a clean FC300 enabling Die-
Yole Dveloppement understands that SET
to-Wafer direct bonding at high yield. The machine
mainly works on accurate placement. What
operates at room temperature. Special care has
is SETs market positioning with respect to
been taken for cabling in order to reduce drastically Semi-open confinement substrate for the FC150 placement accuracy? What are the trades-offs
the particle generation. The clean environment
being made to achieve such levels of accuracy?
inside the machine housing protects the wafer
Semi-open confinement chamber for oxide
surface while it is fully populated with dice. For over 30 years, SET has been involved in high
removal: principle & advantages.
What are the advantages of this technology accuracy applications such as the hybridization
compares to conventional thermo-compression Cu-based systems have become a major focus of infrared focal plane arrays and the assembly
bonding? as an interconnect material for 3D integration. Cu of optoelectronics components required for high
surfaces are bonded together using either die-to- bandwidth telecommunication. Both applications
SET is very much interested by this direct metal-to- die (D2D), die-to-wafer (D2W), or wafer-to-wafer require placement within a micron or better.
metal bonding which enables fast placement for 3D- (W2W) bonding. The oxides present at the Cu Optoelectronics typically involves components
IC. It is performed at low force and room temperature surfaces compromise results of thermocompression ranging from a few hundred microns in size to a few
which is advantageous for high density interconnect bonding. To achieve high-quality and reliable millimetres, whereas the infrared focal plane arrays
applications requiring high accuracy placement as bonding, a controlled environment preventing oxide can be as large as 100 millimetres. 3D integration
we do avoid temperature expansion problem. To formation during the bonding sequence is required; with high-density TSVs requires submicron [or
ensure void-free bonding, the die placement must be it is also necessary to remove the oxide that might
carried out in a particle-free environment. be present before bonding. Mechanical scrubbing
cannot be used when submicron accuracy is
JEMSIP-3D: project based on the development needed; therefore SET has developed the semi-
of a High speed bonder required for the high open confinement chamber to enable chemical
volume production of 3D devices using the TSV oxide removal without jeopardizing the final
technology. placement accuracy. The chamber can be used with
forming gas, but efficiency of the oxide reduction is
significantly increased by using formic acid vapour.
The semi-open confinement chamber includes a
substrate chuck and a bond head with a non-contact
localized confinement which operates safely with
reducing gases such as forming gas or formic acid
vapour. To preserve the standard capabilities of
SETs bonding tools and especially the low contact
force measurement applied to the components,
the Semi-Open Confinement Chamber has no
hardware sealing. A non-contact virtual seal of the
micro-chamber enables gas confinement for chip-
Inside view of the FC300 with direct metallic
to-chip or chip-to-wafer bonding under controlled
bonding configuration
atmosphere. This ensures gas collection and FC300 submicron high force die bonder
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many bonding schemes are being investigated this article, a 2-step approach with individual die
around the world for 3D devices, a clear winner placement followed by global bonding captures the
has not yet emerged and so process flexibility is best features of D2W and W2W bonding schemes;
still a critical feature. Commercialization of 3D this method is being characterized to identify best
integration is expected to begin perhaps as early practices for pre-attachment. While submicron
as 2012, with higher volume applications ramping alignment and positioning of stages and bonding
up after that. arms will continue to occupy a significant portion
of the machine overhead, bonding materials and
Several tool designs to meet these market needs are processes which reduce the temperature and force
on the drawing boards at SET, always with an eye to requirements will likely play a key role in increasing
Cross section of three chips stack meeting the process and throughput requirements the throughput for 3D applications. For this
of emerging market segments. As noted earlier in reason, molecular bonding, performed at modest
highly accurate] bonding, consistent with the temperatures and forces, is of great interest.
accuracy historically required by the IR FPA devices. Similarly, polymer bonding is under investigation
The primary difference between these two markets at IMEC, where SET is partnering with the institute
is the need for much higher throughput; production to develop 3D processes using accurate die
of IR FPAs may be limited to a few tens of devices/ placement followed by collective bonding in a wafer
day due to extremely long bonding times, while bonder.
consumer applications of 3D IC may require several
thousand bonds/hour. These high throughputs are
available on some production bonders, but not at
the accuracy or process conditions required by
most 3D bonding schemes. SET offers a tool for
submicron bonding on 300mm wafers, but with a
throughput of only a few hundred units/hour. SET
will continue to deliver a high accuracy tool for
3D development and lower volume applications,
concurrent to developing a tool with throughputs
Populated wafer Courtesy of IMEC
to meet high volume consumer applications. While www.set-sas.fr
MARKET TRENDS
These players, in search of growth opportunities, have positioned
as service providers for the back-end operations for the making of
through silicon vias (TSVs) and other related wafer-level assembly
operations, explains Jean-Marc Yannou, Project Manager at Yole
Dveloppement.Thanks to 3D glass / silicon interposers, they can
go one step further, and actually propose products combined with
their service offer.
KEY FEatuREs
Detailed account of all the application fields of 3D interposers
Drivers and expected benefits by application
Comparison with technology alternatives and likeliness
of 3D interposer penetration by application YOLE DVELOPPEMENT
contact us
For more information, feel free to contact David Jourdan: Y O L E D V E L O P P E M E N T
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c o mp a ny v i s i o n
T
he eWLB (enhanced Wafer Level BGA) is the Chip placement (pick and place equipment)
first Fan-Out BGA package available on the Wafer molding (epoxy)
market. De-bonding of carrier wafer
Packaging process
The technology is based on a carrier on which the Cost analysis
dies are individually placed to form a reconstituted
wafer. The wafer is then molded and the carrier The cost analysis performed on this package
removed. One or 2 distribution layers are deposited showed that in 2010 the manufacturing cost is
before bumping and singulation. slightly higher than equivalent flip-chip BGA.
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MEMS
developed but the future yield of this approach is still difficult to
estimate.
PROCESSES
serious alternative, with applications extending outside mobile phones
to many consumer products.
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c o mp a ny v i s i o n
Redistribution Layers 1 to 4 1 to 4 2 to 4 2 to 6 2 to 4 2 to 4 2 to 6 2 to 6 2 to 4
YD: What are the key motivations and Volumetric space sensitive X X X
applications driving the commercialization of
Fan-out Wafer-level-packages? Requirements and features by industry and application for Redistributed Chip Packaging technology (RCP)
(Courtesy of Freescale)
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support a single die Fan-out package however this but mostly in developing the infrastructure to support in reliability and appear on larger packages with
is only the beginning. To enable a game changing this capability. Effort and activities are underway in increased layers of redistribution. Fortunately, we
solution for customers, we need to be able to provide developing these solutions. were able to resolve these by passing reliability with
very flexible building blocks off the same fan- good margin and capability.
out platform. The question will be how robust the Infrastructure development challenges:
platform is to support these needs. - Supply chain and die management www.freescale.com
- System architecture
YD: What are the challenges to face for next - 2D and 3D IC system design and electrical
generation FO WLP based on multi-die, double- modeling
side RDL, 3D vias and, eventually, based on - 2D and 3D package design and modeling Navjot Chhabra is currently
Panels? - Inline and end of line component and system heading Research and
testing Development as well as the
NC: Freescale has made good progress in developing - Thermal management operations for Redistributed
and qualifying various RCP building blocks and - Yield management Chip Packaging technology
platforms to allow a diverse range of configurations - Failure analysis within Packaging Solutions
and applications to be realized. Overcoming the Development at Freescale
challenges of processing on 300mm with multiple For 3D systems the biggest challenges will be
Semiconductor. Navjot has held several
layers of routing has put us in a good position to positions within Freescale /Motorola
reliability, system design and addressing yield and
develop a diverse range of integration schemes. We including Strategy, Director of Interconnect at
testability challenges. With respect to the process International SEMATECH and key positions
are continuing to work with multiple customers to find technology, it does require a different level of in Manufacturing. Prior to Motorola, Navjot
new ways to exploit this technology. sophistication to build these reliable structures but spent several years with Micron Technology
not insurmountable. working in process development, process and
Listed below are some of the challenges we have device integration as well as manufacturing.
to solve. From a RCP technology perspective, we Lastly, Freescale made the decision early to migrate Navjot has been involved in the introduction
have qualified to commercial and industrial levels. development and pilot production to a 300mm of several generations of Memory devices as
Getting to multi-die systems (2D) require anywhere format to resolve any issues we may see moving well as the initial migrating to Cu interconnects
from two to six RDL layers, which can also be done from our 200mm platform. As expected, we did see
and adoption of ultra low k dielectrics. Navjot
in RCP without assembly, die drift, yield and warping holds several patents in the area of process
significant challenges that we had not experienced
issues. Multi-die packages have new requirements development and design.
at 200mm. A large number of those showed up
KEY FEATURES
CONSULTING
19
The Market Leader
in eWLB Technology
First in high volume eWLB is a fan-out wafer
eWLB manufacturing with level packaging technology
that offers a small, thin,
best-in-class yields high performance
semiconductor solution
First to offer 300mm for mobile phones and
eWLB reconstituted wafer consumer devices.
c o mp a ny v i s i o n
For starters, interconnect density is increasing. This Historically, multi-die packages have used die from
means a smaller bond pad pitch, stacked die that the same sources such as memory stacks. As 3D
require more interconnects in the same package packaging expands, we can expect die from multiple
footprint, and the adoption of mixed interconnect sources to be packaged together. Well see various
types, wirebond and flip chip, in the same package. Copper pillar bumps (Courtesy of Amkor)
die designed for optimum connection within a single
package. This will be even more critical for TSV and pillar flip chip technology platform (Figure 2), which
Reducing package thickness is another big trend designs where two die are connected by flip chip. will enable fine-pitch 3D interconnects well into the
right now. This is being done with thinner wafers future.
and die, heightening the importance of thinning YD: How is demand for 3D packages compared
methods for creating space for wirebonds such as to more traditional packages? Amkor has relationships with leading foundries,
spacer films, as well as thin core substrates. which enables us to collaborate on reliability
TD: Handheld applications like smartphones and studies with advanced silicon nodes to ensure
Another trend is shrinking footprint size while tablets are driving higher levels of integration. silicon/packaging interactions are addressed for
maintaining or increasing I/O count. Were seeing applications like 3D packaging, where fragile, low-k
finer external ball pitch, with 0.4mm gaining wider YD: Any comments on the A4 processor in dielectrics create challenges due to the thin, high-
adoption and 0.3mm in development. Theres also some handheld tablets? density structures and interconnect technologies.
a push to increase the number of I/O rows.
TD: The A4 processor is the bottom package in a YD: What role will industry collaboration play in
Were also seeing custom external ball patterns package-on-package (PoP) configuration, with the the future of 3D packaging?
being used to optimize escape routing on top package housing two memory die. The benefits
applications boards. include reduced footprint, improved communication TD: Collaboration is a key element in both translating
between application processor and memory, and requirements and reducing time to market. For
YD: Is an example of these custom external ball the ability to package and test the application example, we worked with Nokia and ST to qualify
patterns the A4 used in Apples iPad? processor separately from the memory to reduce our TMV PoP package. All parties benefited from
yield stack-up. this collaboration, which resulted in reduced time
TD: Yes, a good example is the A4 processor used to market and increased sales, thanks to a short
in the iPad. Again, using handheld tablets as an example, the qualification time.
flash memory is in 64GB LGA packages, where
YD: What are the biggest challenges that remain four die are stacked in each package. Memory-type We also recently collaborated with TI on our fine-
for 3D packaging? Any not-so-obvious ones? devices have been the early adopters of 3D-type pitch copper pillar flip chipshrinking bump pitch
packaging. up to 300% compared to current solder bump flip
TD: Package warpage is still a key concern, with
chip technology.
the drive to a thinner package height. This requires YD: How is Amkor differentiating itself with 3D?
thinned wafer/die, a thin mold cap, and a thin YD: Whats next for 3D packaging? Any trends
substrate core. TD: Amkor recognized the drive toward 3D-type we should watch for during the next 5 years?
packaging early on, and our TMV (through-mold
The electrical and thermal performance of the via) PoP, Stacked CSP, and FlipStack CSP (Figure TD: Amkor expects to see increased stacked
system are more heavily influenced by package 1) are clearly aimed at 3D packaging requirements. die counts for memory applications. In wafer-
performance as more functionality is transferred to We also recently announced our fine pitch copper level packages, we also expect to see various
fewer packages by making use of 3D-type package configurations of stacked die and stacked package
with TMV as an enabling technology. Were also
expecting more hybrid packages, in the form
of wafer-level packages stacked with laminate
packages. And as far as TSVs, its still a question of
whether itll be via first, middle, or last.
www.amkor.com
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A N AL Y ST C OR N ER
DBC package structure for power semiconductors (Yole Dveloppement - Nov. 2010)
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way to manage the temperature issue of power The limited number of substrate suppliers for power
semiconductors can often be found in packaging
materials. semiconductors and lack of a supply chain, however, are
When you look at most ICs for consumer
challenges that need to be overcome,
applications, theyre being overloaded with explains Jean-Marc Yannou, Yole Developpement
epoxy resins. These epoxy resins are limited to
operating temperatures of 200C. For higher-power
Since they needed even higher thermal conductivity, the semiconductor device to bring the signal to the
applications, overmoldings are no longer used.
the industry continued to load more metal particles top. The downside is used for grounding and heat
Then you need a specific substrate as well, because
into the latest glues to the point where the latest extraction.
the standard organic substrates have the same
ones are 80% silver; they barely contain glue
issue: theyre epoxy-based.
anymore.
The most common one is the direct-bond copper
The latest step in the evolution of die attach
(DBC) substrate. It uses a ceramic-based substrate
materials is using pure silver. One issue is that it
either made of aluminum nitride or silicon nitride,
has a high melting point. Thats why recent R&D
with copper foils on both sides. This ceramic
involves silver powder with some chemical agents
substrate is a good thermal conductor, which helps
to help it be sintered at low temperatures using low
with heat extraction. Copper is also a good heat Power module with parallel wide bond
temperature sintering technology.
extractor. interconnections
The next step will likely be nanoparticles, which are
The transistors, silicon MOSFETs, IGBTs, GaN, or
still in the R&D stage.
SiC, are attached on the overlying copper foil. The
A driver for using copper pillars is that wire bonds or
whole device is encapsulated and then signals exit Interconnects ribbon bonds create some intermetallic compounds
the upper face of the device. For consumer electronics the most common (IMCs), but these are interface alloys between
interconnections are wire bonds, although bumping the interconnection itself and the pads on the
Substrates
interconnects are becoming common for flip chip semiconductor device. There are conductivity and
Its not at all easy to find companies who provide
devices. Both are used in power applications. reliability issues with wire bonds, including cracking.
substrates for power semiconductors. The
substrates are quite difficult to produce and there The two issues of high current and high temperature
is a lot of secrecy surrounding which companies are a problem because interconnects must be Future of packaging power
produce them and for whom. Its rumored that there able to drive enough current density, and the high semiconductors
will only be three providers of the nitride-based temperatures are an issue of interconnect reliability.
substrates worldwide, because it requires knowing The future of packaging power semiconductors
how to place copper on the nitride substrates. To drive more current density than in the past, looks very bright. A lot of industry momentum
instead of using one wire bond per pad, multiple is starting to ratchet up the pace of evolution of
Thermal dissipation
wires are being used, as well as a larger-diameter power semiconductor technologies and, as a
The goal is to dissipate/extract heat off the
wire bond. For consumer electronics, the most consequence, packaging for these devices.
semiconductor junction, through the semiconductor
common wire bonds are made of gold. But there are
material to extract it from the package. Silicon isnt
serious cost issues involved and its difficult to make The limited number of substrate suppliers for
as good a thermal dissipater as ceramic, and not
large-diameter gold wire bonds. Now, aluminum, power semiconductors and lack of a supply chain,
even close to copper. So when using silicon wafers,
which can be grown in large diameters, is usually however, are challenges that need to be overcome.
they need to be thinned down to below 100m.
substituted for gold.
Actually, all of the high-powered transistors need
However, standardized technical solutions are
to be thinner than 100mand only to combat
After the arrays for wire bonding, the industry emerging which will allow at their turn an outsourcing
thermal dissipation issues.
began using ribbon bonding. It uses the exact same of assembly and packaging services of power
Die attach materials principle as wire bonding and the same equipment. semiconductors as they keep on growing.
ICs need to be attached to the substrates using die But instead of putting a round-shaped wire they use
attach materials. The material of choice in most a rectangular-shaped wire, referred to as a ribbon,
semiconductor packaging is usually glue, so for power which is much larger and capable of driving much
semiconductor devices in the past thermal conductive higher current density.
glues with a high metal content were used.
There are other interconnects being used, such as
Sintering for die attach, in production at Semikron
clip bonding, which is when a MOSFET transistor
(Yole Dveloppement - Nov. 2010)
is sandwiched between its copper foil and another
copper foil, with attachment material on both sides
of the device.
Jean-Marc Yannou joined Yole Developpement
And the reason for so many different technologies as technology and market expert in the fields of
for interconnects is that we need to drive high advanced packaging and system integration. He
current, but also reduce the excess resistance to has 15-years of experience in the semiconductor
the transistors. industry. He worked for Texas Instruments and
Philips (then NXP semiconductors) where he
Copper pillars served as Innovation Manager for System-in-
Package technologies. He is also the President
Copper pillars are an attractive option for power
of IMAPS (International Microelectronics And
semiconductors, but contrary to how theyre used
Ribbon bonding interconnections Packaging Society) in France.
(Courtesy of ST Microelectronics)
in flip chips, they would be placed on the topside of
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Embedded Wafer-Level-Packages
Fan-out WLP / Chip Embedding in Substrate
Be ready for the next generation of IC packaging & substrate assembly waves!
MARKET TRENDS
Embedded wafer-level-packaging technology is not new at all. Key
benefits of the technology include miniaturization, improvement of 3DIC
3-D WLP
with
electrical and thermal performance, cost reduction and simplification tSV Flip-Chip
of logistic for OEMs MEMS
Things are moving really fast at the moment as this year, we see both
Fan-Out wafer level packaging and chip embeddeding into PCB
Fan-out
laminate package infrastructures emerging at the same time, ramping WLP
Package
to high volume production IPDs
PCB
KEY FEatuRES
Both Fan-Out WLP and Chip embedded package technologies
analyzed
Key market drivers, benefits and challenges application by
application
Market trends & figures with detailed breakdown by application
Description of the complete manufacturing tool-box for embedded YOLE DVELOPPEMENT
Supply chain perspectives, key players and emerging infrastructure (Courtesy of NANIUM / Infineon).
ContaCt uS
For more information, feel free to contact David Jourdan: Y O L E D V E L O P P E M E N T
SERVICES PUBLICATIONS
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Critical news, Bi-weekly: Micronews, the magazine
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Services : Jean-Christophe Eloy (eloy@yole.fr)
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Editorial Staff
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Editors: Jrme Baron, Jean-Marc Yannou, Sally Cole Johnson, Dr. Phil Garrou
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24