Beruflich Dokumente
Kultur Dokumente
Features
TAB
TAB
Order code VDSS RDS(on) max. ID
STB55NF06
50 A 3
STP55NF06 60 V < 0.018 2
3 1
1
STP55NF06FP 50 A (1) TO-220 D2PAK
1. Refer to soa for the max allowable current value on
FP-type due to Rth value
!-V
Contents
1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Electrical characteristics (curves) ............................. 6
6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1 Electrical ratings
2 Electrical characteristics
Drain-source
V(BR)DSS ID = 250 A, VGS =0 60 V
breakdown voltage
Zero gate voltage VDS = 60 V 1 A
IDSS
drain current (VGS = 0) VDS = 60 V,@ TJ= 125 C 10 A
Gate-body leakage
IGSS VGS = 20 V 100 nA
current (VDS = 0)
VGS(th) Gate threshold voltage VDS = VGS, ID = 250 A 2 3 4 V
Static drain-source
RDS(on) VGS = 10 V, ID = 27.5 A 0.015 0.018
on-resistance
Table 5. Dynamic
Symbol Parameter Test conditions Min. Typ. Max. Unit
Input capacitance
Ciss 1300 pF
Output capacitance VDS = 25 V, f = 1MHz,
Coss - 300 pF
Reverse transfer VGS = 0
Crss 105 pF
capacitance
td(on) Turn-on delay time 20 ns
VDD = 30 V, ID = 27.5 A
tr Rise time 50 ns
RG = 4.7 VGS = 10 V -
td(off) Turn-off delay time 36 ns
(see Figure 15)
tf Fall time 15 ns
Qg Total gate charge VDD = 48 V, ID = 55 A, 44.5 60 nC
Qgs Gate-source charge VGS = 10 V - 10.5 nC
Qgd Gate-drain charge (see Figure 16) 17.5 nC
Source-drain current
ISD 50 A
Source-drain current -
ISDM (1) 200 A
(pulsed)
VSD (2) Forward on voltage ISD = 50 A, VGS = 0 - 1.5 V
ISD = 50 A,
trr Reverse recovery time 75 ns
di/dt = 100 A/s,
Qrr Reverse recovery charge - 170 nC
VDD = 30 V, Tj = 150 C
IRRM Reverse recovery current 4.5 A
(see Figure 17)
1. Pulse width limited by safe operating area.
2. Pulsed: Pulse duration = 300 s, duty cycle 1.5%
Figure 4. Safe operating area for TO-220FP Figure 5. Thermal impedance TO-220FP
Figure 10. Gate charge vs gate-source voltage Figure 11. Capacitance variations
Figure 12. Normalized gate threshold voltage Figure 13. Normalized on-resistance vs
vs temperature temperature
3 Test circuit
Figure 15. Switching times test circuit for Figure 16. Gate charge test circuit
resistive load
VDD
12V 47k
1k
100nF
RL 2200 3.3
F F
VDD IG=CONST
VD Vi=20V=VGMAX 100 D.U.T.
VGS 2200
RG D.U.T. F 2.7k VG
PW
47k
PW 1k
AM01468v1 AM01469v1
Figure 17. Test circuit for inductive load Figure 18. Unclamped inductive load test
switching and diode recovery times circuit
L
A A A
D
FAST L=100H VD
G D.U.T. DIODE 2200 3.3
F F VDD
S B 3.3 1000
B B F F
25 VDD ID
D
RG S
Vi D.U.T.
Pw
AM01470v1 AM01471v1
Figure 19. Unclamped inductive waveform Figure 20. Switching time waveform
90% 90%
IDM
10%
ID 10% VDS
0
A 4.40 4.60
A1 0.03 0.23
b 0.70 0.93
b2 1.14 1.70
c 0.45 0.60
c2 1.23 1.36
D 8.95 9.35
D1 7.50
E 10 10.40
E1 8.50
e 2.54
e1 4.88 5.28
H 15 15.85
J1 2.49 2.69
L 2.29 2.79
L1 1.27 1.40
L2 1.30 1.75
R 0.4
V2 0 8
0079457_T
12.20 5.08
1.60
3.50
9.75
Footprint
A 4.40 4.60
b 0.61 0.88
b1 1.14 1.70
c 0.48 0.70
D 15.25 15.75
D1 1.27
E 10 10.40
e 2.40 2.70
e1 4.95 5.15
F 1.23 1.32
H1 6.20 6.60
J1 2.40 2.72
L 13 14
L1 3.50 3.93
L20 16.40
L30 28.90
P 3.75 3.85
Q 2.65 2.95
0015988_typeA_Rev_S
A 4.4 4.6
B 2.5 2.7
D 2.5 2.75
E 0.45 0.7
F 0.75 1
F1 1.15 1.70
F2 1.15 1.70
G 4.95 5.2
G1 2.4 2.7
H 10 10.4
L2 16
L3 28.6 30.6
L4 9.8 10.6
L5 2.9 3.6
L6 15.9 16.4
L7 9 9.3
Dia 3 3.2
7012510_Rev_K_B
mm mm
Dim. Dim.
Min. Max. Min. Max.
10 pitches cumulative
tolerance on tape +/- 0.2 mm
Top cover P0 D P2
T tape
E
F
K0 W
B0
A0 P1 D1
Bending radius
User direction of feed
AM08852v2
40mm min.
Access hole
At sl ot location
A N
AM08851v2
6 Revision history
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