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Device Architectures
Overview out the base products. These GAL devices meet and, in
most cases, beat bipolar PAL performance specifica-
In 1985, Lattice Semiconductor introduced a new type of tions while consuming significantly lower power and
programmable logic device (PLD) that transformed the offering higher quality and reliability via Lattices electri-
PLD market: the Generic Array Logic (GAL) device. The cally reprogrammable E2CMOS technology. High-speed
E2CMOS technology of the GAL devices gave them erase times (<100ms) allow the devices to be repro-
significant advantages over their bipolar PAL counter- grammed quickly and efficiently.
parts; not only could GAL devices be programmed quickly
and efficiently, but they could also be erased and repro- Extension Products These products build upon the
grammed. Today, Lattice is the leading supplier, Base GAL product features to provide enhanced func-
worldwide, of low-density PLDs. Industry leading perfor- tionality including innovative architectures (GAL18V10,
mance, low power E2CMOS technology, 100% testability GAL26CV12, GAL6001/6002), 64mA high output drive
and 100% programming yields make the GAL family the (GAL16VP8 & GAL20VP8), Zero power operation
preferred choice among system designers. (GAL16V8Z/ZD & GAL20V8Z/ZD) and In-System Pro-
grammability (ispGAL22V10).
The GAL family includes fourteen distinct product archi-
tectures, with a variety of performance levels specified Low Voltage GAL Products As more system design-
across commercial, industrial, and military (MIL-STD- ers move to 3.3V, Lattice provides high-performance
883) operating ranges, to meet the demands of any 3.3V versions of the popular GAL devices. The standard
system logic design. (GAL16LV8, GAL20LV8 and GAL26CLV12), zero-power
(GAL16LV8ZD, GAL20LV8ZD and GAL22LV10Z/ZD)
These GAL products can be segmented into three broad and in-system programmable (ispGAL22LV10) device
categories: architectures are all available.
Base Products - Aimed at providing superior design A Product for any System Design Need
alternatives to bipolar PLDs, these five architectures
Lattice GAL products have the performance, architec-
replace over 98% of all bipolar PAL devices. The GAL16V8
tural features, low power, and high quality to meet the
and GAL20V8 replace forty-two different PAL devices.
needs of the most demanding system designs.
The GAL22V10, GAL20RA10, and GAL20XV10 round
I/CLK
I GAL20V8 Only
I IMUX
E CMOS Programmable
I CLK
I
AND Array
8
I/O/Q
OLMC I/O/Q
I I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I I/O/Q
I
2
I I
IMUX
I/OE
I GAL20V8 Only
GAL20V8 Only
2
Introduction to GAL Device Architectures
enable control for combinational outputs in the registered ibility in matching signal requirements, thus providing
mode or combinational outputs in the complex mode. more functionality than possible with standard PAL de-
vices.
There is no output enable control in the simple mode. The
OLMC provides the designer with maximum output flex-
Vcc
D Q
Q
XOR XOR
OE
Combinatorial Configuration for Registered Mode Combinatorial Output Configuration for Simple
Mode
Vcc
XOR
XOR
Combinatorial Output Configuration for Complex Dedicated Input Configuration for Simple Mode
Mode
XOR
3
Introduction to GAL Device Architectures
ASYNC.
RESET
SYNC.
I/CLK PRESET
I
GAL18V10
I
GAL22V10
GAL26CV12
I
OLMC
PROGRAMMABLE
I/O/Q
I/O/Q
AND-ARRAY
I
1 I/O/Q
GAL18V10 and
I
2 I/O/Q
GAL26CV12
GAL22V10
I 3 I/O/Q
I 4 I/O/Q
5 I/O/Q
I
6 I/O/Q
I 7 I/O/Q
I 8 I/O/Q
9 I/O/Q
I
10 I/O/Q
I 11
12
4
Introduction to GAL Device Architectures
The output polarity of each OLMC can be individually GAL22V10 family devices have a product term for Asyn-
programmed to be true or inverting, in either combina- chronous Reset (AR) and a product term for Synchronous
tional or registered mode. This allows the user to reduce Preset (SP). These two product terms are common to all
the overall number of product terms required in a design registered OLMCs.
and/or to invert the output signal.
A R
D
4 TO 1
Q
MUX
CLK Q
SP
2 TO 1
MUX
AR AR
D Q D Q
CLK Q CLK Q
SP SP
5
Introduction to GAL Device Architectures
The GAL20RA10
The GAL20RA10 (24-pin) supports high performance, the state of the programmable polarity bit. The ability to
asynchronous logic. It is a direct parametric compatible program the active polarity of the D-inputs can be used to
CMOS replacement for the PAL20RA10 device. How- reduce the total number of product terms used, by allow-
ever, Lattices E2CMOS circuitry achieves power levels ing the DeMorganization of the logic functions. This logic
as low as 75mA typical Icc, which represents a substan- reduction is accomplished by the logic compiler, and
tial savings in power when compared to bipolar does not require the designer to define the polarity.
counterparts like the PAL20RA10.
The GAL20RA10 contains ten dedicated input pins and GAL20RA10 Block Diagram
ten I/O pins. As with other GAL devices, it has user-
PL
configurable OLMCs.
PROGRAMMABLE
8
control of each output. Each OLMC has a flip-flop by- I OLMC I/O/Q
pass, allowing any combination of registered or
AND-ARRAY
combinational outputs. 8
(80X40)
I OLMC I/O/Q
An independent clock control product term is provided for
each GAL20RA10 macrocell. Data is clocked into the 8
I OLMC I/O/Q
flip-flop on the active edge of the clock product term. The
use of individual clock control product terms allows up to 8
ten separate clocks. These clocks can be derived from I OLMC I/O/Q
6
Introduction to GAL Device Architectures
AR
PL PD
D Q 0
AP 1
X O R (n )
PL
OE
AR
PL PD
D
Q
AP
X O R (n )
OE
XOR (n)
7
Introduction to GAL Device Architectures
The GAL20XV10
The GAL20XV10 (24-pin) provides the highest speed, When the macrocell is set to the Exclusive-OR Regis-
low-density Exclusive-OR PLD available in the market, tered configuration, the four product terms are segmented
making it perfect for the fast counters, decoders, or into two OR-sums of two product terms each, which are
comparators common in video, multimedia, and graphics then combined by an Exclusive-OR gate and fed into a D-
applications. At 75mA typical Icc, the E 2 CMOS type register that is clocked by the low-to-high transition
GAL20XV10 reduces power by over 50% from bipolar of the I/CLK pin.
XOR architectures.
When the macrocell is set to Registered configuration,
The GAL20XV10 is a 24-pin device which contains ten three of the four product terms are used as sum-of-
dedicated input pins and ten I/O pins. Its generic architec- product terms for the D input of the register. The inverting
ture provides maximum design flexibility by allowing the output buffer is enabled by the fourth product term. The
Output Logic Macrocell (OLMC) to be configured by the output is enabled while this product term is true. The XOR
user. An important subset of the many architecture con- bit controls the polarity of the output.
figurations possible with the GAL20XV10 are the standard
PAL architectures. Providing ten OLMCs with four prod- When the macrocell is set to the Exclusive-OR combina-
uct terms each, the GAL20XV10 is capable of emulating torial configuration, the four product terms are segmented
the PAL12L10, PAL20L10, PAL20X10, PAL20X8, and into two OR-sums of two product terms each, which are
PAL20X4 devices. then combined by an Exclusive-OR gate and fed to an
output buffer.
Output Logic Macrocell
Each OLMC has an Exclusive-OR gate capability with GAL20XV10 Block Diagram
programmable polarity. This minimizes product term I/CLK
usage.
4
The GAL20XV10 has two global OLMC architecture OLMC I/O/Q
configurations that allow it to emulate PAL architectures. I
Input mode emulates combinatorial PAL devices, whereas 4
Feedback mode emulates registered PAL devices. OLMC I/O/Q
I
macrocell. 4
I OLMC I/O/Q
AND-ARRAY
(40 X 40)
4
I OLMC I/O/Q
4
I OLMC I/O/Q
4
I
OLMC I/O/Q
I 4
OLMC I/O/Q
I 4
OLMC I/O/Q
I
4
OLMC I/O/Q
I/OE
8
Introduction to GAL Device Architectures
GAL20XV10 OLMC Configurations
D Q D Q
Q XOR Q
CLK CLK
OE
XOR
9
Introduction to GAL Device Architectures
I
8 OLMC I/O/Q
PROGRAMMABLE
3
AND-ARRAY
I 8 OLMC I/O/Q
3
AND-ARRAY
(64 X 32)
I
OLMC I/O/Q
(64 X 40)
8
4
I 8 OLMC I/O/Q
4
I
8 OLMC I/O/Q
5
I 8 OLMC I/O/Q
5
I
8 OLMC I/O/Q
6
I 8 OLMC I/O/Q
6
I
8 OLMC I/O/Q
7
I 8 OLMC I/O/Q
7
I
8 OLMC I/O/Q
8
I OE 8 OLMC I/O/Q
I/OE I 8
OE
I I
IMUX
I/OE
10
Introduction to GAL Device Architectures
I/CLK I/CLK
CLK
I
IMUX
I CLK
8 OLMC I/O/Q
1
I 8 OLMC I/O/Q
1
I
8 OLMC I/O/Q
2
8 OLMC I/O/Q
I
2
I/DPP
OLMC I/O/Q
PROGRAMMABLE
PROGRAMMABLE
3
I/DPP 8 OLMC I/O/Q
AND-ARRAY
AND-ARRAY
I
(64 X 32)
OLMC I/O/Q
(64 X 40)
8
4
I 8 OLMC I/O/Q
4
I
8 OLMC I/O/Q
5
I 8 OLMC I/O/Q
5
I
8 OLMC I/O/Q
6
I 8 OLMC I/O/Q
6
I
8 OLMC I/O/Q
7
8 OLMC I/O/Q
I 7
I
OLMC I/O/Q
8 8
8 OLMC I/O/Q
I I 8
OE
I/OE OE
I I
IMUX
I/OE
11
Introduction to GAL Device Architectures
ICLK
INPUT
CLOCK
2 14
11
23
INPUTS
2-11
{ ILMC
IOLMC
RESET
OUTPUT
AND ENABLE
14
D 23
OLMC
E
0
OR
7 D
BLMC
E
{ OUTPUTS
14 - 23
OCLK OUTPUT
CLOCK
12
Introduction to GAL Device Architectures
Output Logic Macrocell (OLMC) and Buried with directional control provided by the ten output enable
Logic Macrocell (BLMC) (OE) product terms. Additionally, the polarity of each
OLMC output is selected through the D XOR. Polarity
The outputs of the OR array feed two groups of macrocells. selection is available for BLMCs, since both the true and
One group of eight macrocells is buried; its outputs feed complemented forms of their outputs are available in the
back directly into the AND array rather than to device AND array. Polarity of all E sum terms is selected
pins. These cells are called the Buried Logic Macrocells through the E XOR.
(BLMCs), and are useful for building state machines. The
second group of macrocells consists of ten cells whose Registers in both the OLMCs and BLMCs feature a
outputs, in addition to feeding back into the AND array, common RESET product term. This active high product
are available at the device pins. Cells in this group are term allows the registers to be asynchronously reset.
known as Output Logic Macrocells (OLMCs). Registers are reset to a logic zero. If connected to an
output pin, a logic one will occur because of the inverting
The Output and Buried Logic Macrocells are configurable output buffer.
on a macrocell by macrocell basis. They may be set to
one of three configurations: combinatorial, D-type regis-
ter with sum term (asynchronous) clock, or D/E-type
register. Output macrocells always have I/O capability,
13
Introduction to GAL Device Architectures
The ispGAL22V10
The ispGAL22V10 (28-pin) provides the industrys first ispGAL22V10 Block Diagram
in-system programmable 22V10 device. It is fully func-
tion/fuse map/parametric compatible with standard bipolar
RESET
and CMOS 22V10 devices (refer to the GAL22V10, I/CLK
GAL18V10, and GAL26CV12 section in this article). The 8
standard 28-pin PLCC package provides the same func- OLMC I/O/Q
I
tional pinout at the standard 22V10 PLCC package with
the four No-Connect pins being used for ISP interface 10
PROGRAMMABLE
systems with capabilities previously unattainable. ISP 14
I OLMC I/O/Q
provides the ability to program and reprogram logic
AND-ARRAY
devices while attached to the printed circuit board (PCB).
(132X44)
No other logic technology is better for reducing time to I
16
OLMC I/O/Q
market, while assuring the highest system quality and
lowest overall cost. With ISP technology, hardware as
16
flexible and easy to modify as software becomes a reality: I OLMC I/O/Q
hardware functions can be programmed and modified in
real time to expand product features, shorten system 14
I
design and debug time, enhance product OLMC I/O/Q
manufacturability and simplify field upgrades.
I 12
OLMC I/O/Q
ispGAL22V10 28-Pin PLCC Pinout Diagram
I 10
SCLK
I/CLK
I/O/Q
I/O/Q
OLMC I/O/Q
Vcc
I
I
8
4 2 28 26 OLMC I/O/Q
I 5 25 I/O/Q
I
I I/O/Q PRESET SDO
Programming SDI
Logic MODE
I 7 23 I/O/Q SCLK
MODE SDO
I 9 21 I/O/Q
I I/O/Q ispGAL22V10 28-Pin SSOP Pinout Diagram
I 11 19 I/O/Q
12 14 16 18 SCLK 1 28 Vcc
I/CLK I/O/Q
I
I
GND
SDI
I
I/O/Q
I/O/Q
I I/O/Q
I I/O/Q
I I/O/Q
I I/O/Q
I 7 22 SDO
MODE I/O/Q
I I/O/Q
I I/O/Q
I I/O/Q
I I/O/Q
I I
GND 14 15 SDI
14
Introduction to GAL Device Architectures
12
The GAL16LV8, GAL20LV8 and GAL26CLV12 are 3.3V OLMC
I I/O/Q
versions of the GAL16V8, GAL20V8 and GAL26CV12
architectures. The device fuse maps are the same be-
PROGRAMMABLE
14
tween the 3.3V and 5V devices. Refer to the previous I OLMC I/O/Q
architecture discussions for the 5V standard devices.
AND-ARRAY
(132X44)
16
The GAL16LV8ZD, GAL20LV8ZD and GAL22LV10Z/ZD I OLMC I/O/Q
devices are 3.3V versions of the GAL16V8ZD,
GAL20V8ZD and GAL22V10Z/ZD architectures. Again, 16
the device fuse maps are the same. Refer to the previous I OLMC I/O/Q
architecture discussions for the 5V zero-power devices.
14
I
The ispGAL22LV10 is a 3.3V version of the 22V10 OLMC I/O/Q
architecture, allowing in-system programming with 3.3V
TTL signals. Refer to the GAL22V10, GAL18V10 and I 12
GAL26CV12 section of this document for an architecture OLMC I/O/Q
description. The ispGAL22LV10 differs from the
ispGAL22V10 in that it uses the boundary scan (IEEE I 10
I/O/Q
I/O/Q
4 2 28 6
2
I 5 25 I/O/Q TCK 1 28 Vcc
I/CLK I/O/Q
I I/O/Q I I/O/Q
I I/O/Q
I 7 23 I/O/Q I I/O/Q
I I/O/Q
TMS TDO
I 7 22 TDO
I 9 21 I/O/Q TMS I/O/Q
I I/O/Q
I I/O/Q I I/O/Q
I I/O/Q
I 11 19 I/O/Q I I/O/Q
12 14 16 18 I I
GND 14 15 TDI
I
I
GND
I
I/O/Q
I/O/Q
TDI
15