a Dual PLL Frequency Synthesizer

Preliminary Technical Data ADF4216/ADF4217/ADF4218

FEATURES GENERAL DESCRIPTION
ADF4216: 550MHz/1.2GHz The ADF4216/ADF4217/ADF4218 is a dual frequency
ADF4217: 550MHz/2.0GHz synthesizer which can be used to implement local oscil-
ADF4218: 550MHz/2.5GHz lators in the up-conversion and down-conversion sec-
+2.7 V to +5.5 V Power Supply tions of wireless receivers and transmitters. They can
Selectable Charge Pump Currents provide the LO for both the RF and IF sections. They
Selectable Dual Modulus Prescaler consist of a low-noise digital PFD (Phase Frequency
3-Wire Serial Interface Detector), a precision charge pump, a programmable
Power Down Mode reference divider, programmable A and B counters and a

APPLICATIONS
RY dual-modulus prescaler (P/P+1). The A (6-bit) and B
(11-bit) counters, in conjunction with the dual modulus
prescaler (P/P+1), implement an N divider (N= BP+A).
Portable Wireless Communications (PCS/PCN, Cordless)
Cordless and Cellular Telephone Systems

N A In addition, the 14-bit reference counter (R Counter),

I
allows selectable REFIN frequencies at the PFD input.
Wireless Local Area Networks (WLANs)
Cable TV Tuners (CATV)
Pagers
M
I IC A L A complete PLL (Phase-Locked Loop) can be imple-
mented if the synthesizers are used with an external loop
filter and VCO's (Voltage Controlled Oscillators)

L
E HN
Control of all the on-chip registers is via a simple 3-wire
interface.

R
P EC TA
The devices operate with a 3V ( 10%) or 5V( 10%)
power supply and can be powered down when not in
use.

T DA FUNCTIONAL BLOCK DIAGRAM

VCC1 V C C2 VP1 VP 2

A DF421 6/A DF42 17 /A DF421 8

SW A LL O W
C O N TR OL

IF IN A 17 -B IT I F
+
IF N -C O U N TER
P R E SC ALE R
IF IN B -
C H A RG E
PU MP
C P IF

PH A S E
C O M P A R A TO R
14 -B IT IF
R-C O UN T ER

IF
LO C K
D ETE C T

R EF I N O SC ILL A TO R

O UT P U T
M U XO U T
M UX

C LO C K
22-B IT
D ATA D AT A
RE G IS T E R
LE SD O U T

RF
LO C K
D ETE C T

17 -B IT R F
R F IN A +
RF N-C O UN TE R
P RE S C ALE R

R F INB -
C H A RG E
PU MP
C PR F
14 -B IT RF
R-C O UN TER PH A S E
C O M P A R A TO R

SW A LL O W
C O N TR OL

D G ND R F A G ND R F D G ND IF D G ND IF A G ND IF
REV.PrD 7/99

Information furnished by Analog Devices is believed to be accurate and reliable. Analog Devices, Inc., 1999
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties which may result from its use.
No license is granted by implication or otherwise under any patent or patent rights of One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Analog Devices. Tel: 781-329-4700 Fax: 781-326-8703
ADF4216/17/18 SPECIFICATIONS1 GND
(V = +3 V 10%, +5 V 10%; V = V , +5 V 10%;
CC
= 0 V; T = T to T unless otherwise noted)
A MIN MAX
P CC

Parameter B Version BChips Units Test Conditions/Comments

RF/IF CHARACTERISTICS
RF Input Frequency (RFIN)
ADF4216 0.1/1.2 0.1/1.2 GHz min/max
ADF4217 0.1/2.0 0.1/2.0 GHz min/max
ADF4218 0.1/2.5 0.1/2.5 GHz min/max
IF Input Frequency (IFIN) 45/550 45/550 MHz min/max
Reference Input Frequency 5/40 5/40 MHz min/max
Phase Detector Frequency 10 10 MHz max
RF Input Sensitivity -15/0 -15/0 dBm min/max 3V Power Supply
-10/0 -10/0 dBm min/max 5V Power Supply
IF Input Sensitivity -15/0 -15/0 dBm min/max 3V Power Supply
-10/0 -10/0 dBm min/max 5V Power Supply
Reference Input Sensitivity -5 -5 dBm min
CHARGE PUMP
ICP sink/source
High Value 4
RY
4 mA typ
Low Value
ICP Three State Current
1
1
A
N L
1
1
mA typ
nA max
Sink and Source Current Matching
ICP vs. VCP
2
2

M I A
2
2
% typ
% typ
0.5V < VCP < VP - 0.5
0.5V < V CP < VP - 0.5
ICP vs. Temperature
LOGIC INPUTS
2
I
L NI C
2 % typ VCP = VP/2

VINH, Input High Voltage

E0.8*VCC 0.8*VCC V min

PR ECH TA
VINL, Input Low Voltage 0.2*VCC 0.2*VCC V max
IINH/IINL, Input Current 1 1 A max
CIN, Input Capacitance 10 10 pF max
Oscillator Input Current 100 100 A max
LOGIC OUTPUTS
VOH, Output High Voltage
VOL, Output Low Voltage
T DA
VCC - 0.4
0.4
VCC - 0.4
0.4
V min
V max
IOH = 1mA
IOL = 1mA
POWER SUPPLIES
VCC1 2.7/5.5 2.7/5.5 V min/V max
VCC2 VCC1 V CC1
VP VCC1/5.5 VCC1/5.5 V min/V max
ICC
ADF4216 4.0 4.0 mA max
ADF4217 4.5 4.5 mA max
ADF4218 5.0 5.0 mA max
Low Power Sleep Mode 1 1 A typ

2 REV.PrD 7/99
ADF4216/17/18 SPECIFICATIONS1 (VGND == +30 V;VR 10%, +5 V 10%; V = V , +5 V 10%;
= 4.7k; T = T to T unless otherwise
CC
SET A MIN
P CC
MAX
noted)
Parameter B Version BChips Units Test Conditions/Comments
NOISE CHARACTERISTICS
Phase Noise Floor -173 -173 dBc/Hz typ @ 25kHz PFD Frequency
-165 -165 dBc/Hz typ @ 200kHz PFD Frequency
Phase Noise Performance2 @ VCO Output
ADF4216, ADF4217, ADF4218 (IF)3 -97 -97 dBc/Hz typ
ADF4216 (RF)4 -91 -91 dBc/Hz typ
ADF4216 (RF)5 -82 -82 dBc/Hz typ
ADF4217 (RF)6 -85 -85 dBc/Hz typ
ADF4217 (RF)7 -65 -65 dBc/Hz typ
ADF4218 (RF)8 -85 -85 dBc/Hz typ
Spurious Signals Measured at offset of fPFD/2fPFD
ADF4216, ADF4217, ADF4218 (IF)3 tbd/tbd tbd/tbd dB typ
ADF4216 (RF)4 tbd/tbd tbd/tbd dB typ
ADF4216 (RF)5 tbd/tbd tbd/tbd dB typ
ADF4217 (RF)6
ADF4217 (RF)7
ADF4218 (RF)8
RY tbd/tbd
tbd/tbd
tbd/tbd
tbd/tbd
tbd/tbd
tbd/tbd
dB
dB
dB
typ
typ
typ
NOTES
A
N L
I
1 Operating temperature range is as follows: B Version: 40C to +85C.
2 The phase noise is measured with the EVAL-ADF421XEB Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REFIN for the

M A
synthesizer. (f REFOUT = 10MHz @ 0dBm)

I
3. f REFIN = 10 MHz; fPFD = 200 kHz; Offset frequency = 1 kHz; fIF = 460MHz; N = 2300; Loop B/W = 20kHz;

L NI C
4. f REFIN = 10 MHz; fPFD = 200 kHz; Offset frequency = 1 kHz; fRF = 900MHz; N = 4500; Loop B/W = 12kHz
5. f REFIN = 10 MHz; fPFD = 30kHz; Offset frequency = 1 kHz; fRF = 836MHz; N = 27867; Loop B/W = 3kHz

E
6. f REFIN = 10 MHz; fPFD = 200kHz; Offset frequency = 1 kHz; fRF = 1880MHz; N = 9400; Loop B/W = 20kHz

PR ECH TA
7. f REFIN = 10 MHz; fPFD = 10kHz; Offset frequency = 250Hz; fRF = 1880MHz; N = 188000; Loop B/W = 1kHz
8. f REFIN = 10 MHz; fPFD = 200kHz; Offset frequency = 1 kHz; fRF = 1960MHz; N = 9800; Loop B/W = 20kHz

T DA
CHIP LAYOUT

3 REV.PrD 7/99
Preliminary Technical Data ADF4216/ADF4217/ADF4218
TIMING CHARACTERISTICS (VCC = +5 V 10%, +3 V 10%; GND = 0 V, unless otherwise noted)
Limit at
TMIN to TMAX
Parameter (B Version) Units Test Conditions/Comments
t1 50 ns min DATA to CLOCK Set Up Time
t2 10 ns min DATA to CLOCK Hold Time
t3 50 ns min CLOCK High Duration
t4 50 ns min CLOCK Low Duration
t5 50 ns min CLOCK to LE Set Up Time
t6 50 ns min LE Pulse Width
NOTE
Guaranteed by Design but not Production Tested.
t3 t4

Y
C LO CK

R
t1 t2

DA TA
DB 21
(M SB )

N A D B 20 D B2 DB1
(C O NT R O L BIT C 2)
D B 0(L S B )
(C O NT R O L BI T C 1)

I L
t6

LE

L M
I IC A t5

E HN
LE

R
P EC TA
Figure 1. Timing Diagram

T DA
ABSOLUTE MAXIMUM RATINGS1, 2
(TA = +25C unless otherwise noted)
VCC to GND . . . . . . . . . . . . . . . . . . . . . . . . . .0.3 V to +7 V
VP to GND . . . . . . . . . . . . . . . . . . . . . . . . . . .0.3 V to +7 V
VP to VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.3 V to +3.5 V
Digital I/O Voltage to GND . . . . . . . . 0.3 V to VDD + 0.3 V
Analog I/O Voltage to GND . . . . . . . . 0.3 V to VP + 0.3 V
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . 40C to +85C
Storage Temperature Range . . . . . . . . . . . 65C to +150C
Maximum Junction Temperature . . . . . . . . . . . . . . . +150C
TSSOP JA Thermal Impedance . . . . . . . . . . . . . TBDC/W
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although this device features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220C
1. Stresses above those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2. This device is a high-performance RF integrated circuit with an ESD rating of
< 2kV and it is ESD sensitive. Proper precautions should be taken for handling
and assembly.
WARNING!
ESD SENSITIVE DEVICE

ORDERING GUIDE

Model Temperature Range Package Option*

ADF4216BRU 40C to +85C RU-20
ADF4216BCHIPS 40C to +85C
ADF4217BRU 40C to +85C RU-20
ADF4217BCHIPS 40C to +85C
ADF4218BRU 40C to +85C RU-20
ADF4218BCHIPS 40C to +85C

*RU = Thin Shrink Small Outline Package (TSSOP).

4 REV.PrD 7/99
 Preliminary Technical Data ADF4216/ADF4217/ADF4218
PIN DESCRIPTION

Mnemonic Function
VCC1 Positive power supply for the RF section. A 0.1F capacitor should be connected between this pin and the RF
ground pin, DGNDRF. VCC1 should have a value of +5V 10% or +3V 10%. VCC1 must have the same
potential as VCC2.
VP 1 Power supply for the RF charge pump. This should be greater than or equal to VDD.
CPRF Output from the RF charge pump. This is normally connected to a loop filter which drives the input to an
external VCO.
DGNDRF Ground pin for the RF digital circuitry.
RFINA Input to the RF Prescaler. This low-level input signal is normally taken from the RF VCO.
RFINB Complementary Input to the RF Prescaler. This point should be decoupled to the ground plane with a small
bypass capacitor. If this is not done then there will be some degradation in RF sensitivity.
AGNDRF Ground pin for the RF analog circuitry.
REFIN

DGNDIF Y
Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and an equivalent input resistance
of 100k. This input can be driven from a TTL or CMOS crystal oscillator.

R
Ground pin for the IF digital, interface and control circuitry.
MUXOUT
A
This multiplexer output allows either the IF/RF Lock Detect, the scaled RF or the scaled Reference Frequency

N
CLK
I
to be accessed externally.

L
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into

M A
DATA
L I IC
the 22-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is

LE
E HN
a high impedance CMOS input.

R
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the
four latches, the latch being selected using the control bits.
AGNDIF
IFINB P EC TA
Ground pin for the IF analog circuitry.
Complementary Input to the IF Prescaler. This point should be decoupled to the ground plane with a small

IFINA
DGNDIF
T DA
bypass capacitor. If this is not done then there will be some degradation in IF sensitivity.
Input to the IF Prescaler. This low-level input signal is normally taken from the IF VCO.
Ground pin for the IF digital, interface and control circuitry.
CPIF Output from the IF charge pump. This is normally connected to a loop filter which drives the input to an
external VCO.
VP 2 Power supply for the IF charge pump. This should be greater than or equal to VCC.
VCC2 Positive power supply for the IF, interface and oscillator sections. A 0.1F capacitor should be connected
between this pin and the IF ground pin, DGNDIF. VCC2 should have a value of +5V 10% or +3V 10%.
VCC2 must have the same potential as VCC1.

V C C1 1 20 VC C2
VP1 VP2
CP RF CP IF
DG ND RF ADF4216 DG ND I F
RF I N A ADF4217 IF I N A
RF I N B ADF4218
IF I N B
AG ND RF AG ND I F
REF IN LE
DG ND I F DATA
M UXO U T 10 11 CLK

5 REV.PrD 7/99
Preliminary Technical Data ADF4216/ADF4217/ADF4218
CIRCUIT DESCRIPTION
INPUT SHIFT REGISTER Table 1. C2, C1 Truth Table
The functional block diagram for the ADF4216 family is
Control Bits
shown below. The main blocks include a 22-bit input shift
C2 C1 Data Latch
register, a 14-bit R counter and an 17-bit N counter, com-
prising a 6-bit A counter and a 11-bit B counter. Data is 0 0 IF R Counter
clocked into the 22-bit shift register on each rising edge of 0 1 IF N Counter (A and B)
CLK. The data is clocked in MSB first. Data is transferred 1 0 RF R Counter
from the shift register to one of four latches on the rising edge 1 1 RF N Counter (A and B)
of LE. The destination latch is determined by the state of the
two control bits (C2, C1) in the shift register. These are the
two lsb's DB1, DB0 as shown in the timing diagram of Figure
1. The truth table for these bits is shown in Table 1.

RY
FUNCTIONAL BLOCK DIAGRAM

N A V CC 1 V CC 2 VP1 VP2 R S ET

M I A L
I IC
A D F4 2 16 /A D F4 2 1 7/A D F 42 1 8
SW A LLO W

L
CO NT RO L

IF IN A +

R E HN
IF
17 -B IT I F
N -C O U N T E R

P EC TA
TE S T
P R E SC ALE R
IF IN B - M UX
1 CH AR G E
PU M P
C P IF

T DA
P H AS E
C O M P A R A TO R
14-B IT IF
R -C O U N TE R

IF
LO C K
D E TE C T

RE FIN O S C ILL A TO R

O UT PU T
MU XOUT
MUX

C L OC K FA S T
22 -B IT CH AR G E
D A TA DAT A PU M P

RE GI ST ER
LE SD O U T

RF
LO C K
D E TE C T

TES T
17 -B IT R F
RF IN A +
RF M UX
2
N -C O U N TE R
P RE SC ALE R

RF IN B -
CH AR G E
PU M P
C P RF
14-B IT R F
R -C O U N T E R P H AS E
C O M P A R A TO R

SW A LL O W
CO NT RO L

D G ND RF A G N D RF D G N D IF A G N D IF

6 REV.PrD 7/99
 Preliminary Technical Data ADF4216/ADF4217/ADF4218
IF REFERENCE (IF R) COUNTER
If control bits C2, C1 are 0,0 then the data is transferred
from the input shift register to the IF R counter as shown in
Table 2. Table 3 shows the divide ratios possible.
Table 2. Programming the Reference (R) Counter
DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

P4 P3 P2 P5 P1 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 C 2 (0 ) C 1 (0 )

A D F4 21 6 Fam ily
IF CP Gain

P o larity
IF L o ck

3- S tat e

IF P D
D et ect

A D F4 20 6 Fam ily
C P IF

IF F O 14-B it R eferen ce C ou n ter C o ntr o l

B its

1. Data is shifted in MSB (DB23) first.

Table 3. R Counter Divide Ratios

Divide Ratio R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1

1
2
*
0
0
*

RY
0
0
*
0
0
*
0
0
*
0
0
*
0
0
*
0
0
*
0
0
*
0
0
*
0
0
*
0
0
*
0
0
*
0
1
*
1
0
*

A
* * * * * * * * * * * * * * *
16382 1 1 1 1 1 1 1 1 1 1 1 1 1 0
16383 1

I N 1

L
1 1 1 1 1 1 1 1 1 1 1 1

M A
NOTES
1. Divide ratio: 1 to 16383

TABLE 4. Truth Table for Program Modes on ADF4216

L I IC The IF and RF Counter Reset mode does both of the above.

P12 P11 P4 P3
RFR20RFR19IFR20 IFR19
R E HN
Program Mode
Upon removal of the reset bits, the N counter resumes counting in close
alignment with the R counter (maximum error is one prescaler output
cycle).
0 0 0 0
P EC TA
Drive MUXOUT (FOLD on
LMX233X) to low logic state
4.The Fastlock mode uses MUXOUT to switch a second loop filter damping
resistor to ground during Fastlock operation. Activation of Fastlock occurs
whenever RF CP Gain in the RF Reference counter is set to one.In the

T DA
0 0 0 1 IF Analog Lock Detect on MUXOUT ADF4210, the Fastlock switch is brought out on a separate pin (FLO).
0 X 1 0 IF Reference Divider Output on However, its operation is the same as the other devices. Note, however,
that the RF CP Gain bit which initiates Fastlock is contained in the RF N
MUXOUT
counter latch. This means that only one write is needed to both program a
0 X 1 1 IF N Divider Output on MUXOUT new output frequency and also initiate Fastlock.
0 1 0 0 RF Analog Lock Detect on MUXOUT
R COUNTER FOR THE IF
0 1 0 1 RF/IF Analog Lock Detect on
R1 to R14 set the counter divide ratio. The divide range is 1
MUXOUT
(00.....001) to 16383(111......111).
1 X 0 0 RF Reference Divider on MUXOUT
1 X 0 1 RF N Divider MUXOUT IF PROGRAMMABLE MODES
1 0 1 0 Fast Lock Output Switch On and PD POLARITY.
connected to MUXOUT When the IF VCO characteristics are positive then this bit
1 0 1 1 IF Counter Reset should be set to 1. When VCO characteristics are negative
1 1 1 0 RF Counter Reset then this bit should be set to 0.
1 1 1 1 IF and RF Counter Reset
CHARGE PUMP 3-STATE
To put IF charge pump into 3-State, this bit (P2 for
Notes for Table 3
1. IF and RF Analog Lock Detect indicate when the PLL is in lock. When the loop ADF4210, ADF4216, ADF4206 families) should be set to
is locked and either IF or RF Analog Lock Detect is selected, then the MUXOUT 1. For normal operation this bit should be set to zero.
pin will show a logic high with narrow low-going pulses. When the IF/RF Analog
Lock Detect is chosen then the locked condition is indicated only when both IF IF LOCK DETECT / IF FO
and RF loops are locked.
P3 and P4 on the ADF4216 family are used in conjunction
2. The digital lock detect modes also indicate when the loop is in lock. When the
loop is locked and either IF or RF Digital Lock Detect is selected, then the with bits P11 and P12 of the RF R Latch to determine a
MUXOUT pin will show a logic high. Internally, the device looks for 5 programmable mode. Most but not all of these modes refer to
successive low-going pulses of less than 15ns at the output of the PFD and when the state of MUXOUT. Table 4 shows the full truth table for
it finds these it sets the Digital Lock Detect. When the IF/RF Analog Lock Detect the ADF4216 Family Program Modes.
is chosen then the locked condition is indicated only when both IF and RF loops
are locked.
3. The IF Counter Reset mode resets the R and N counters in the IF section and also IF CHARGE PUMP CURRENT
puts the IF charge pump into 3-state. The RF Counter Reset mode resets the R On these devices, DB18 determines the level of IF Charge
and N counters in the RF section and also puts the RF charge pump into 3-state. Pump Current. If DB18 is 1 then ICP is High (4mA). If
DB18 is 0, then ICP is Low, (ICP High)/4, or 1mA.

7 REV.PrD 7/99
Preliminary Technical Data ADF4216/ADF4217/ADF4218
IF N COUNTER
If control bits C2, C1 are 0, 1 then the data in the input reg-
ister is used to program the IF N (A + B) counter. The N
counter consists of a 6-bit swallow counter (A counter) and
11-bit programmable counter (B counter). Table 5 shows
the input register data format for programming these.

Table 5. Programming the IF A, B Counters

DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

P7 P6 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 0 A6 A5 A4 A3 A2 A1 C 2 (0 ) C 1 (1 )
A DF4216 Fam ily
P re s c a le r
Power
Down

A DF4206 Fam ily

IF

1 1 -B it B C o u nt er C o n tro l
IF

6 -B it A C o u nter
B its

Pulse Swallow Function

RY POWERDOWN FOR THE IF

A
The A and B counters, in conjunction with the dual modulus In all the device families, the IF Power Down works as
prescaler make it possible to generate output frequencies follows:
which are spaced only by the Reference Frequency divided by
R . The equation for the VCO frequency is as follows:
I N L Synchronous Power Down.

M A
Programming a 1 to P7 of the ADF4216 family will

fVCO:
fVCO = [(P x B) + A] x fREFIN/R
Ouput Frequency of external voltage controlled oscil-
L I IC initiate a power down. If P2 of the ADF4216 family has
been set to 0 (normal operation), then a synchronous

P:
lator (VCO).
Preset modulus of dual modulus prescaler.
R E HN power down is conducted. The device will automatically
put the charge pump into 3-state and then complete the
power down.
B: Preset Divide Ratio of binary 13-bit counter (3 to
8191). P EC TA Asynchronous Power Down
If P2 of the ADF4216 families has been set to 1 (3-
A: Preset Divide Ratio of binary 6-bit swallow
counter.
fREFIN: Ouput frequency of the external reference
T DA state the charge pump), then an asynchronous power
down is conducted. The device will go into power down
on the rising edge of LE which latches the 1 to the IF
Power Down bit.
frequency oscillator.
Activation of either synchronous or asynchronous power
R: Preset divide ratio of binary 14-bit down forces the IF loops R and N dividers to their load
programmable reference counter (3 to 16383). state conditions and the IFIN section is debiased to a high
A Counter Latch For The IF impedance state.
In the ADF4216 family, A6 - A1 program the A counter. The REFIN oscillator circuit is only disabled if both the
The divide range is 0 (000000) to 15 (001111). IF and RF Power Downs are set.
The input register and latches remain active and are
B Counter Latch For the IF capable of loading and latching data during all the power
In the ADF4216 family, B1 - B11 program the 11-bit B down modes.
counter. The valid divide range is 3 (00....011) to 2047 The IF section of the devices will return to normal pow-
(11...111). ered-up operation immediately upon LE latching a 0 to
Overall Divide Range the IF Power Down bit.
The upper limit of the divide range is defined by ((PxB) +
A), where P is the prescaler value. To ensure a fully contigu-
ous range, there is a lower limit of (P 2 -P).
IF Prescaler
In the ADF4216 family, DB20 determines the prescaler
value. If DB20 is "0", then the prescaler value is 8/9. If it is
"1", then the prescaler value is 16/17.

8 REV.PrD 7/99
 Preliminary Technical Data ADF4216/ADF4217/ADF4218
Table 6. Programming the RF Reference Counter

D B 21 D B 20 D B 19 D B 18 D B 17 D B 16 D B 15 D B 14 D B 13 D B 12 D B 11 D B 10 DB 9 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 DB 0

P12 P11 P10 P13 P9 R 15 R 14 R 13 R 12 R 11 R 10 R9 R8 R7 R6 R5 R4 R3 R2 R1 C 2(1) C 1(0)

A D F 4216 Fam ily
R F L o ck

P o la r it y
D e tec t

3-S tate
RF FO

RF PD
R F IC P
C P RF
1 4 - B it R e f e re n c e C o u n t e r C o n tr o l A D F 4206 Fam ily
B i ts

THE RF R COUNTER LATCH

With (C2, C1) = (1,0), the R Counter for RF is pro-
grammed.
R Counter For The RF
On the ADF4216 family, R1 to R14 set the counter divide
ratio. The divide range is 1 (00.....001) to
16383(111......111).

RY
A
RF PROGRAMMABLE MODES

N
RF PD Polarity.
When the RF VCO characteristics are positive then this bit
(P9) should be set to 1. When VCO characteristics are

M I A L
negative then this bit should be set to 0.
Charge Pump 3-State
L I IC
To put RF charge pump into 3-State, this bit (P10) should
be set to 1. For normal operation this bit should be set to

R E HN
P EC TA
zero.
RF Lock Detect /RF FO
P11 and P12 on the ADF4216 family are used in conjunc-
tion with bits P3 and P4 of the IF R Latch to determine a
programmable mode. Most but not all of these modes refer to
the state of MUXOUT. Table 4 shows the truth table for the
ADF4216 family.
T DA
RF Charge Pump Current
DB18 determines the level of RF Charge Pump Current. If
DB18 is 1 then ICP is High (4.0mA). If DB18 is 0, then
ICP is Low, (ICP High)/4, or 1.0mA.

9 REV.PrD 7/99
Preliminary Technical Data ADF4216/ADF4217/ADF4218
THE RF A,B COUNTER LATCH
With (C2, C1) = (1,1), the A, B Counters for the IF are
programmed.

Table 7. Programming the RF N (A B) Counter

DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

P16 P14 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 0 A6 A5 A4 A3 A2 A1 C 2 (1 ) C 1 (1 )

A D F4 216 Fam ily
P r es cale r
Power
Down

A D F4 206 Fam ily

RF

C on tro l
RF

11-B it B Co un ter 6-Bit A C ou nter

B its

A Counter Latch For The RF

In the ADF4216 family, A6 - A1 program the 6-bit A
counter. The divide range is 0 (000000) to 63 (111111).
B Counter Latch For The RF
B1 - B11 program the 11-bit B counter. The valid divide
RY
range is 3 (00....011) to 2047 (11...111).

N A
I
Overall Divide Range
The upper limit of the divide range is defined by ((PxB) +
A), where P is the prescaler value. To ensure a fully contigu-
ous range, there is a lower limit of (P 2 -P). M
I IC A L
RF Prescaler
DB20 (P14) determines RF prescaler value. L
E HN
For the ADF4216 and ADF4216, if P14 is "0", then the
prescaler value is 64/65. If P14 is "1", then the prescaler
value is 32/33.
R
P EC TA
For the ADF4218, if P14 is "0', then the prescaler value is 32/
33. If P14 is "1", then the prescaler value is 64/65.
T DA

10 REV.PrD 7/99