Embedded Split-Gate Flash Memory with Silicon Nanocrystals for 90nm and Beyond

Gowrishankar Chindalore, Jane Yater, Horacio Gasquet, Mohammed Suhail, Sung-Taeg Kang, Cheong Min Hong, Nicole Ellis,
Glenn Rinkenberger, James Shen, Matthew Herrick, Wendy Malloch, Ronald Syzdek, Kelly Baker, Ko-Min Chang

Technology Solutions Organization, Freescale Semiconductor, Inc.

6501 William Cannon Drive, Austin, Texas, USA
Tel: (512) 895-8381; Fax: (512) 895-8605; g.chindalore@freescale.com

Abstract portion of the channel is counter-doped in order to eliminate

We present a split-gate based NOR flash memory array
with silicon nanocrystals as the storage medium. 128KB
memory arrays have been evaluated with this technology and
the results presented here show a nanocrystal memory that has
been demonstrated to achieve a minimum 1.5V operating
window that is maintained through 10K program/erase cycles;
well controlled array threshold distributions; fast source-side
injection programming (10-20us); fast tunnel erase into the
gate; and robust high temperature data retention for both
uncycled and cycled arrays. Results presented here with
focus on the array operation demonstrate the maturity of this
technology for implementation into consumer, industrial, and
automotive microcontrollers. (Keywords: Microcontrollers,
Nanocrystals, Flash Memories, Memory Array, Source-side
Injection, Tunnel Erase, Endurance, Data Retention)
Introduction
The increasing intelligence in the products that affect our
lives such as consumer (appliances, electronics, etc);
industrial (robotics, power tools, etc); and automotive (engine
control, safety features, etc) products require microcontrollers
with high density of flash memory that are not only reliable
but also cost-effective to integrate. The traditional floating
gate based embedded flash memories are either implemented
as one transistor cells (1-T) mostly in high density
applications, or as split-gate cells (1.5T) in medium-low
density applications [1]. However, combining nanocrystal
storage and split-gate architectures, the scaling limitations
imposed by floating gate memories are overcome while
availing the benefit of smaller module size achievable with
split-gate architecture. In this paper, we report the progress
made in developing such a broadly applicable nanocrystal
memory supported with an extensive set of data from memory
arrays.
Description
A. Memory Array Design and Implementation
The nanocrystal memory has been integrated into the 90nm
technology node along with high voltage (HV) devices
necessary for the array operation. The HV devices are used to
drive the control gate (CG) and source, while core logic
transistors (low voltage and I/O devices) control the select
gate (SG) and the bit lines. The array test vehicle is a 16Mb
part partitioned into sixteen 1Mb modules (Fig. 1). Each of
the 1Mb modules is soft sectored into 2KB sectors, creating a
selectable array from 2KB-2MB.
The memory stack consists of thermally grown bottom
oxide, a layer of deposited nanocrystals and high quality
deposited top oxide. The dielectric layers are thinner than
those used in the floating gate memories. The control gate
the read disturb that is inherent to memories with thin
dielectrics [2,3]. The array threshold (Vth) distributions in the
natural state (fully discharged nanocrystals) have a width of
1.3-1.5V (Fig. 2), close to the expectation based on channel
dopant fluctuations. The natural Vth distributions have been
found to be repeatable in over 10,000 1Mb modules covering
multiple silicon lots.
B. Program and Erase Operations
The source-side injection programming is fast (<20us) and
requires low power (2-15uA/bit). The program efficiency is a
strong function of the select gate bias (Fig. 3) due to its effect
on the field at the gap. The tunnel erase operation into control
gate using positive bias is also very fast at the beginning of
life (Fig. 4), but slows with cycling due to oxide trap up [4].
Neither operation requires negative bias, thus increasing array
efficiency.
C. Endurance and Reliability
Over one thousand 1Mb modules have been cycled with a
minimum operating window of at least 1.5V. The window is
maintained after 10K write/erase cycles (Fig. 5) and is large
enough to generate the read currents necessary for high
performance products (read speeds < 20ns), while also
providing sufficient margin for high temperature data
retention (DR) from the program state. The memory stack is
inherently vulnerable to trap-up during programming due to
the discontinuous nature of nanocrystals [3]. However, we
have minimized trap-up with process optimization so that
sufficient operating window can be maintained throughout the
life of the product.
Figure 6 shows long-term DR for both uncycled and 10K
cycled parts as a function of temperature. The data shows
well controlled Vth distributions with an intrinsic shift that is
consistent with expectation based on single bitcell evaluations
[4], and in addition, no extrinsic bits have been observed in
the arrays as seen from the Vth distributions collected during
DR bake (Fig. 6) despite the use of thinner dielectrics.
Summary
Nanocrystal memory technology combined with split-gate
architecture allows for efficient design solutions that span a
wide range of applications from low to high density due to
minimal analog circuit requirements and relatively high array
efficiency. Array results from split-gate nanocrystal flash
memories show controllable Vth distributions, fast program
(<20us) and erase operations (<250us at the beginning of life),
at least 1.5V operating window that is maintained through
10K cycles, and robust high temperature DR without extrinsic
bits.

978-1-4244-1805-3/08/$25.00 2008 IEEE 2008 Symposium on VLSI Technology Digest of Technical Papers 136
9VS=5V
D

References [3] J.A. Yater, 2007 22nd NVSMW, pp.77-78.

[1] S. Saha, IEEE TED, vol.54, pp. 3049-3055, 2007 [4] C.M. Hong, 2007 22nd NVSMW, pp.75-76.
[2] C.T. Swift, 2006 21st IEEE NVSMW, pp. 56-57.
6
10
V = 13V
CG

# of bits above Erase Verify

5
10 U ncycle d

4
10
13V
0V
0V 0V
10
3 S 0V D

2
10

10
Under 200s

1
-5 -4
10 10
Figure 1: 2MB split-gate nanocrystal Era se Tim e (s)
Control Gate
memory test vehicle partitioned into
Select Gate
sixteen 1Mb modules, with sector size Figure 4: Erase rate distribution with 13V control gate. The erase
as small as 2KB creating selectable speed is fast with all bits are erased under 200s with 13V. Both
arrays from 2KB-2MB. TEM program and erase operations are positive bias operations, thus
cross-section of a typical array bitcell is Nanocrystal storage layer eliminating the need for negative charge pump entirely.
shown on the right.

6
10 106
Erase Program
5 1K 1K
10 5
128KB 10
100 10K 100 10K
4
10 4
10
# of Bits

# of Bits

3
10
103
2KB
2
10
102

10
10
V
read
1
-2 -1.5 -1 -0.5 0 0.5 1 1.5 2
1
-3 -2 -1 0 1 2
V -V V -V
th th,median th read
Figure 2: Natural Vth distributions (fully discharged nanocrystals) for Figure 5: Program and erase Vth distributions as a function of cycling for
2KB and 128KB memory sizes. The widths are consistent with 1Mb module. The minimum window is about 1.5V which is sufficient to
expectation based on channel dopant fluctuations under the control gate. balance the read performance and the data retention requirements.

7 0 0
10
85C 85C
V = 9V; V = 5V
# of bits below Program Verify

CG S 150C 150C
6 200C
10 Uncycled 200C
0.5 250C
0.5
5
10
VTH Shift

250C
VTH Shift

4 9V
10 1 1
5V IPGM
3 S D
10
0V

2 1.5 1.5
10 10K Cycled
1.2V Uncycled
Median bit - 1Mb array Median bit - 1Mb array
10 Dashed line - worst-case bit at 150C Dashed line - worst-case bit at 150C
V = 0.8V 0.9V 1.0V 2
SG 2
0.1 1 10 0.1 1 10
1
Time (Days) Time (Days)
0 15 30
Program Time ( s)
Figure 6: Threshold shift for program state as a function of temperature for uncycled and
Figure 3: Program rate distribution as a function of select gate bias. 10K-cycled 1Mb arrays. The Vth shift is higher after cycling due to oxide detrapping. The Vth
With increasing SG bias, the inversion field at the gap region increases distributions are also well controlled without evidence of extrinsic bits as seen by the Vth
resulting in less efficient heating of the carriers. distributions shown in the inset (only 150C distributions shown here for clarity).

978-1-4244-1805-3/08/$25.00 2008 IEEE 2008 Symposium on VLSI Technology Digest of Technical Papers 137