Z09 SYSTEM BLOCK DIAGRAM

5 4 3 2 1
VER : 3A
BOM P/N Description Z09 SYSTEM BLOCK
DIAGRAM
D D
Dual Channel DDR III
Memory Down 1333/1600 MHZ
DDRIII-SODIMM1 IMC NVIDIA GPU
P13 PCI-E
PCIE
Ivy Bridge X16 N13P-GV
1GB (128Mb x 32 IO x 4 pcs)
256MB*16 2.5GT/s
BGA 1023
P27,28,29,30,31,32
17W
P2,3,4,5,6 X'TAL
27.0MHz
Max. 2G P14
eDP eDP Conn.
mSATA - HDD FDI DMI P15
P20
DMI(x4)
SATA - HDD FDI DMI

SATA
P20
C C
SATA - ODD SATA
P21 Display
HDMI
HDMI Conn.
USB3.0(USB2.0) P16
USB3.0 *2
USB2.0 *2
USB Port
P23
USB3.0(USB2.0) PCIE-8
USB3.0
USB Port Panther Point PCI-E x1 MINI CARD
P23 WLAN+BT
USB-10 P19
PCI-E x1 PCH
BGA 989 PCI-E x1
BCM57780
USB Port P7, 8, 9, 10, 11, 12 PCIE-3 RJ45 Conn.
(Charger)P23 GIGA LAN P18
P17
X'TAL
USB2.0 32.768KHz X'TAL
25MHz
B B
USB2.0
CCD Conn. USB2.0
X'TAL
P15 25MHz
PCIE-2 RTS5209-GR Cardreader
Cardreader Conn.(2in1)
P8 BATTERY RTC
controller P19
SPI
SPI ROM
Azalia IHDA P8
Daugther board
LPC
2M+4M
LPC
Batery Charger P31 +1.05V P34 +VGFX_AXG P33
ALC271-VB6 WPCE885
DMIC
AUDIO CODEC EC
Daugther board P19 P24 3V/5V P32 +1.8V/+1V P37 CPU core P33
Discharger
+VGPU_CORE P38 +VGPU_IO P38 P37
BOM Option Table
A A
MIC/HP JACK K/B Con. Touch Pad
Reference Description Con.
P22 P19 Thermal Protection
EV@ Optimize SKU
P37
SNB@ For Sandy bridge.
IVB@ For Ivy bridge.
IV@ For UMA. W25X16VSS1G EM-6781-T3 Fan Driver Quanta Computer Inc.
Speaker HALL SENSOR
* do not stuff SPI FLASH P8 P15 P19 PROJECT : Z09
Size Document Number Rev
3A
Block Diagram
Date: Monday, April 09, 2012 Sheet 1 of 40
5 4 3 2 1
5 4 3 2 1
Ivy Bridge Processor (DMI,PEG,FDI)

PEG_ICOMPI and RCOMPO signals
should be shorted and routed with
- max length = 500 mils
U9A - typical impedance = 43 mohms
G3 PEG_COMP PEG_ICOMPO 12mil PEG_ICOMPO signals should be routed with
PEG_ICOMPI G1
M2 PEG_ICOMPO G4 PEG_ICOMPI, PEG_RCOMPO 4mil, - max length = 500 mils
<7> DMI_TXN0 DMI_RX#[0] PEG_RCOMPO - typical impedance = 14.5 mohms
P6
<7> DMI_TXN1 DMI_RX#[1]
<7> DMI_TXN2 P1 GRN[0..15] <25>
P10 DMI_RX#[2] H22 GRN15
D <7> DMI_TXN3 DMI_RX#[3] PEG_RX#[0] D
J21 GRN14
N3 PEG_RX#[1] B22 GRN13
<7> DMI_TXP0 DMI_RX[0] PEG_RX#[2]
P7 D21 GRN12
<7> DMI_TXP1 DMI_RX[1] PEG_RX#[3]
DMI
<7> DMI_TXP2 P3 A19 GRN11
P11 DMI_RX[2] PEG_RX#[4] D17 GRN10
<7> DMI_TXP3 DMI_RX[3] PEG_RX#[5] B14 GRN9
K1 PEG_RX#[6] D13 GRN8
<7> DMI_RXN0 DMI_TX#[0] PEG_RX#[7]
M8 A11 GRN7
<7> DMI_RXN1 DMI_TX#[1] PEG_RX#[8]
<7> DMI_RXN2 N4 B10 GRN6
R2 DMI_TX#[2] PEG_RX#[9] G8 GRN5
<7> DMI_RXN3 DMI_TX#[3] PEG_RX#[10] A8 GRN4
K3 PEG_RX#[11] B6 GRN3
<7> DMI_RXP0 DMI_TX[0] PEG_RX#[12]
M7 H8 GRN2
<7> DMI_RXP2 P4 E5 GRN1
T3 DMI_TX[2] PEG_RX#[14] K7 GRN0
GRP[0..15] <25>
K22 GRP15
PEG_RX[0] K19 GRP14
PEG_RX[1] C21 GRP13
U7 PEG_RX[2] D19 GRP12
<7> FDI_TXN0 FDI0_TX#[0] PEG_RX[3]
W11 C19 GRP11
<7> FDI_TXN2 W1 D16 GRP10
PCI EXPRESS -- GRAPHICS

AA6 FDI0_TX#[2] PEG_RX[5] C13 GRP9
<7> FDI_TXN4 W6 D12 GRP8
V4 FDI1_TX#[0] PEG_RX[7] C11 GRP7
Y2 C9 GRP6
Intel(R) FDI
<7> FDI_TXN7 AC9 F8 GRP5
FDI1_TX#[3] PEG_RX[10] C8 GRP4
PEG_RX[11] C5 GRP3
C U6 PEG_RX[12] H6 GRP2 C
<7> FDI_TXP0 FDI0_TX[0] PEG_RX[13]
W10 F6 GRP1
<7> FDI_TXP1 FDI0_TX[1] PEG_RX[14]
<7> FDI_TXP2 W3 K6 GRP0
AA7 FDI0_TX[2] PEG_RX[15]
<7> FDI_TXP3 FDI0_TX[3] GTN[0..15] <25>
<7> FDI_TXP4 W7 G22 GTN15C C154 EV@0.22u/10V_4 GTN15
T4 FDI1_TX[0] PEG_TX#[0] C23 GTN14C C152 EV@0.22u/10V_4 GTN14
<7> FDI_TXP5 FDI1_TX[1] PEG_TX#[1]
AA3 D23 GTN13C C149 EV@0.22u/10V_4 GTN13
<7> FDI_TXP6 FDI1_TX[2] PEG_TX#[2]
<7> FDI_TXP7 AC8 F21 GTN12C C148 EV@0.22u/10V_4 GTN12
FDI1_TX[3] PEG_TX#[3] H19 GTN11C C146 EV@0.22u/10V_4 GTN11
AA11 PEG_TX#[4] C17 GTN10C C143 EV@0.22u/10V_4 GTN10
<7> FDI_FSYNC0 FDI0_FSYNC PEG_TX#[5]
AC12 K15 GTN9C C142 EV@0.22u/10V_4 GTN9
<7> FDI_FSYNC1 FDI1_FSYNC PEG_TX#[6] F17 GTN8C C140 EV@0.22u/10V_4 GTN8
U11 PEG_TX#[7] F14 GTN7C C137 EV@0.22u/10V_4 GTN7
<7> FDI_INT FDI_INT PEG_TX#[8] A15 GTN6C C136 EV@0.22u/10V_4 GTN6
AA10 PEG_TX#[9] J14 GTN5C C156 EV@0.22u/10V_4 GTN5
<7> FDI_LSYNC0 FDI0_LSYNC PEG_TX#[10]
AG8 H13 GTN4C C134 EV@0.22u/10V_4 GTN4
<7> FDI_LSYNC1 FDI1_LSYNC PEG_TX#[11] M10 GTN3C C162 EV@0.22u/10V_4 GTN3
PEG_TX#[12] F10 GTN2C C132 EV@0.22u/10V_4 GTN2
PEG_TX#[13] D9 GTN1C C130 EV@0.22u/10V_4 GTN1
PEG_TX#[14] J4 GTN0C C128 EV@0.22u/10V_4 GTN0
AF3 PEG_TX#[15]
eDP_ICOMPO 12mil EDP_COMP AD2 eDP_COMPIO F22 GTP15C C153 EV@0.22u/10V_4 GTP15
GTP[0..15] <25>
eDP_COMPIO 4mil INT_EDP_HPD# AG11 eDP_ICOMPO PEG_TX[0] A23 GTP14C C151 EV@0.22u/10V_4 GTP14
eDP_HPD PEG_TX[1] D24 GTP13C C150 EV@0.22u/10V_4 GTP13
PEG_TX[2] E21 GTP12C C147 EV@0.22u/10V_4 GTP12
EDP_AUX# AG4 PEG_TX[3] G19 GTP11C C145 EV@0.22u/10V_4 GTP11
<15> EDP_AUX# AF4 eDP_AUX# PEG_TX[4] B18
EDP_AUX GTP10C C144 EV@0.22u/10V_4 GTP10
<15> EDP_AUX eDP_AUX PEG_TX[5] K17 GTP9C C141 EV@0.22u/10V_4 GTP9
PEG_TX[6]
DP
G17 GTP8C C139 EV@0.22u/10V_4 GTP8

EDP_TX0# AC3 PEG_TX[7] E14 GTP7C C138 EV@0.22u/10V_4 GTP7
B <15> EDP_TX0# eDP_TX#[0] PEG_TX[8] B
AC4 C15 GTP6C C135 EV@0.22u/10V_4 GTP6
AE11 eDP_TX#[1] PEG_TX[9] K13 GTP5C C155 EV@0.22u/10V_4 GTP5
AE7 eDP_TX#[2] PEG_TX[10] G13 GTP4C C133 EV@0.22u/10V_4 GTP4
eDP_TX#[3] PEG_TX[11] K10 GTP3C C161 EV@0.22u/10V_4 GTP3
EDP_TX0 AC1 PEG_TX[12] G10 GTP2C C131 EV@0.22u/10V_4 GTP2
<15> EDP_TX0 eDP_TX[0] PEG_TX[13]
AA4 D8 GTP1C C129 EV@0.22u/10V_4 GTP1
AE10 eDP_TX[1] PEG_TX[14] K4 GTP0C C127 EV@0.22u/10V_4 GTP0
AE6 eDP_TX[2] PEG_TX[15]
eDP_TX[3]
SNB_2CBGA_1P0 0.22uF AC coupling Caps for PCIE GEN1/2/3
DG 1.0 :
The recommended AC cap value is changed to 220nF for compatibility with
DP_COMPIO and ICOMPO signals PCIe Gen3 on future platforms.
should be shorted near balls and routed with For Gen2 only designs, it is acceptable to continue to use the 100nF capacitor.
- typical impedance < 25 mohms
+1.05V_VTT
DP & PEG Compensation eDP Hot-plug (Disable)
20111104 change from 10k to 1k.
R192
+1.05V_VTT 1K_4
A INT_EDP_HPD# A
EDP_COMP R564 24.9/F_4
3
+1.05V_VTT 2 EDP_HPD
EDP_HPD <15>
Q2
Quanta Computer Inc.
PEG_COMP
CAD Note: Place PU resistor
R193 24.9/F_4 2N7002E R191
within 2 inches of CPU PROJECT : Z09
1
100K_4 Size Document Number Rev

3A
HPD PU/PD resistor values based Ivy Bridge 1/5
on CRB and different to DG Date: Monday, April 09, 2012 Sheet 2 of 40
5 4 3 2 1
5 4 3 2 1
Boot S3 S3 RSM
+1.5V_CPU
DRAM_PWRGD
Ivy Bridge Processor (CLK,MISC,JTAG) 100 ns after +1.5V_CPU
SYS_PWROK reaches 80%
U9B
D SM_DRAMPWROK D
J3 CLK_CPU_BCLKP <9>
BCLK H2 CLK_CPU_BCLKN <9>
CLOCKS
BCLK#
MISC
If motherboard only supports external graphics or if it supports
F49 TP95
20111121 Remove R5306/R5311/R5474/R5476. Processor Graphics but without eDP:
<8> H_SNB_IVB# PROC_SELECT# Connect DPLL_REF_SSCLK on Processor to GND through 1K +/-
AG3 CLK_DPLL_SSCLKP <9>
DPLL_REF_CLK AG1 5% resistor.
DPLL_REF_CLK# CLK_DPLL_SSCLKN <9> Connect DPLL_REF_SSCLK# on Processor to VCCP through 1K +/
TP85 C57 TP53 - 5% resistor
PROC_DETECT#
N59 CLK_PCIE_XDPP_R R230 *0_4 CLK_PCIE_XDPP <9>
BCLK_ITP N58 CLK_PCIE_XDPN_R R229 *0_4
BCLK_ITP# CLK_PCIE_XDPN <9>
TP78 TP_CATERR# C49

CATERR#
THERMAL
Isolate Space:20mils
A48 AT30
<10,24> EC_PECI PECI SM_DRAMRST# CPU_DRAMRST# <4,24>
BF44 SM_RCOMP_0 R209 140/F_4 CAD NOTE: All DDR_COMP signals

R207 56_4 H_PROCHOT#_R C45 SM_RCOMP[0] BE43 SM_RCOMP_1 R206 25.5/F_4 should be routed such that :-
<24,33> H_PROCHOT#
DDR3
MISC
C253 PROCHOT# SM_RCOMP[1] BG43 SM_RCOMP_2 R204 200/F_4 - max length = 500 mils
2 1 *43P/50V_4N SM_RCOMP[2] - trace width = 15mils and
- MB trace impedance < 68 mohms
(worst case resistance)
D45 Impedance 85ohm
<10> PM_THRMTRIP# THERMTRIP#
N53 TP79
PRDY# N55 XDP_PREQ#
PREQ# TP83
C C
L56 XDP_TCLK_VT <8,22> Place near to XDP connector
TCK L55
Over 130 degree C will TMS XDP_TMS_VT <8,22>
PWR MANAGEMENT
J58 XDP_TRST# TP103
drive low
JTAG & BPM

TRST# 51_4 R232 PCH_XDP_TDO_VT
+1.05V_VTT
<7> PM_SYNC R214 *SHORT_4 PM_SYNC_R C48 M60 XDP_TDI_VT <22>
PM_SYNC TDI L59
TDO PCH_XDP_TDO_VT <8>
C718 0.1U/10V_4
20111021 Add 10k to +3V,CRB 1k
R596 *SHORT_4 H_PWRGOOD_R B46 20111103 del R601
<10> H_PWRGOOD UNCOREPWRGOOD K58 XDP_DBRST#_R R233 0_4 XDP_DBRST# <7>
R595 10K_4 DBR#
PM_DRAM_PWRGD_R BE45 G58 Option for Prochot# function +1.05V_VTT

Isolate Space:20mils SM_DRAMPWROK BPM#[0] E55
TP97
BPM#[1] TP82 68 ohm for unused, 62 ohm for used
E59
BPM#[2] TP81
R194 75/F_4 G55 H_PROCHOT# R219 62_4
+1.05V_VTT TP67 BPM#[3] TP80
G59
BPM#[4] TP98
CPU_PLTRST# R190 43_4 CPU_PLTRST#_R D44 H60 TP100
RESET# BPM#[5] J59 XDP_TMS_VT R606 51_4
BPM#[6] TP99
J61 XDP_TDI_VT R231 51_4
BPM#[7] TP101
R196 XDP_PREQ# R612 *51_4
*750/F_4 XDP_TCLK_VT R611 51_4

XDP_TRST# R228 51_4
SNB_2CBGA_1P0 When MP, JTAG PU/PD resistor can be

B
removed? (Yes Intel, TDI, TDO, TMS, TRST#, B
TCK,PREQ#, PRDY#)
+3V
If PM_DRAM_PWEGD connector,the R5180 must stuff. C190

Thermal Trip <CPU> s3 leakage circuit U8 0.1U/10V_4X
20111128 change net to PCI_PLTRST# 1 5
+3V_S5 +3V_S5 NC VCC
20111121 add Q31 becaue Vh=2.1/Vl=0.9. 2
+1.05V_VTT <9,24> PCI_PLTRST# IN
3 4 CPU_PLTRST#
+1.5V_CPU GNDOUT
R604 R603 C727 74LVC1G07GW_NC
3
*1K_4 *10K_4 0.1u/10V_4
R186 *1.5K/F_4 CPU_PLTRST#_R

2 Q6 +1.5V_CPU R605
<7,33> IMVP_PWRGD
5
U33 200/F_4
2N7002_200MA 2
<7> SYS_PWROK
4 PM_DRAM_PWRGD_Q R598 130/F_4 PM_DRAM_PWRGD_R
IN OUT
1 L L
1
A A
5
74AHC1G09 H High-Z
3
R610 *39_4 3 1
R195
1K_4
*2N7002DW Q44 *2N7002K
2
Q42
4
1
2
Q5
<5,37> MAINON_G PROJECT : Z09
PM_THRMTRIP# 1 3 MMBT3904-7-F_200MA R602 0_4 Size Document Number Rev
SYS_SHDN# <32,37> <7> PM_DRAM_PWRGD
3A
20111030 add resistor. R608 *0_4
Ivy Bridge 2/5
5 4 3 2 1
5 4 3 2 1
Sandy Bridge Processor (DDR3)

U9C U9D
<14> M_B_DQ[63:0]
<13> M_A_DQ[63:0] AG6 AL4
M_A_DQ0 M_B_DQ0
M_A_DQ1 AJ6 SA_DQ[0] AU36 M_B_DQ1 AL1 SB_DQ[0] BA34
M_A_DQ2 AP11 SA_DQ[1] SA_CLK[0] AV36 M_A_CLK0 <13> M_B_DQ2 AN3 SB_DQ[1] SB_CLK[0] AY34 M_B_CLK0 <14>
AL6 SA_DQ[2] SA_CLK#[0] AY26 M_A_CLK0# <13> AR4 SB_DQ[2] SB_CLK#[0] AR22 M_B_CLK0# <14>
M_A_DQ3 M_B_DQ3
AJ10 SA_DQ[3] SA_CKE[0] M_A_CKE0 <13> AK4 SB_DQ[3] SB_CKE[0] M_B_CKE0 <14>
M_A_DQ4 M_B_DQ4
M_A_DQ5 AJ8 SA_DQ[4] M_B_DQ5 AK3 SB_DQ[4]
D M_A_DQ6 AL8 SA_DQ[5] M_B_DQ6 AN4 SB_DQ[5] D
M_A_DQ7 AL7 SA_DQ[6] M_B_DQ7 AR1 SB_DQ[6]
M_A_DQ8 AR11 SA_DQ[7] M_B_DQ8 AU4 SB_DQ[7]
M_A_DQ9 AP6 SA_DQ[8] AT40 M_A_CLK1 M_B_DQ9 AT2 SB_DQ[8] BA36 M_B_CLK1
AU6 SA_DQ[9] SA_CLK[1] AU40 M_A_CLK1 <13> AV4 SB_DQ[9] SB_CLK[1] BB36
M_A_DQ10 M_A_CLK1# M_B_DQ10 M_B_CLK1#
AV9 SA_DQ[10] SA_CLK#[1] BB26 M_A_CLK1# <13> BA4 SB_DQ[10] SB_CLK#[1] BF27
M_A_DQ11 M_A_CKE1 M_B_DQ11 M_B_CKE1 TP31
M_A_DQ12 AR6 SA_DQ[11] SA_CKE[1] M_A_CKE1 <13> M_B_DQ12 AU3 SB_DQ[11] SB_CKE[1]
M_A_DQ13 AP8 SA_DQ[12] M_B_DQ13 AR3 SB_DQ[12]
M_A_DQ14 AT13 SA_DQ[13] M_B_DQ14 AY2 SB_DQ[13]
M_A_DQ15 AU13 SA_DQ[14] M_B_DQ15 BA3 SB_DQ[14]
M_A_DQ16 BC7 SA_DQ[15] M_B_DQ16 BE9 SB_DQ[15]
M_A_DQ17 BB7 SA_DQ[16] BB40 M_B_DQ17 BD9 SB_DQ[16] BE41
SA_DQ[17] SA_CS#[0] M_A_CS#0 <13> SB_DQ[17] SB_CS#[0] M_B_CS#0 <14>
M_A_DQ18 BA13 BC41 M_A_CS#1 M_B_DQ18 BD13 BE47 M_B_CS#1
SA_DQ[18] SA_CS#[1] M_A_CS#1 <13> SB_DQ[18] SB_CS#[1] TP32
M_A_DQ19 BB11 M_B_DQ19 BF12
M_A_DQ20 BA7 SA_DQ[19] M_B_DQ20 BF8 SB_DQ[19]
M_A_DQ21 BA9 SA_DQ[20] M_B_DQ21 BD10 SB_DQ[20]
M_A_DQ22 BB9 SA_DQ[21] M_B_DQ22 BD14 SB_DQ[21]
M_A_DQ23 AY13 SA_DQ[22] M_B_DQ23 BE13 SB_DQ[22]
M_A_DQ24 AV14 SA_DQ[23] AY40 M_B_DQ24 BF16 SB_DQ[23] AT43
SA_DQ[24] SA_ODT[0] M_A_ODT0 <13> SB_DQ[24] SB_ODT[0] M_B_ODT0 <14>
M_A_DQ25 AR14 BA41 M_A_ODT1 M_B_DQ25 BE17 BG47 M_B_ODT1
SA_DQ[25] SA_ODT[1] M_A_ODT1 <13> SB_DQ[25] SB_ODT[1] TP33
M_A_DQ26 AY17 M_B_DQ26 BE18
M_A_DQ27 AR19 SA_DQ[26] M_B_DQ27 BE21 SB_DQ[26]
M_A_DQ28 BA14 SA_DQ[27] M_B_DQ28 BE14 SB_DQ[27]
M_A_DQ29 AU14 SA_DQ[28] M_B_DQ29 BG14 SB_DQ[28]
M_A_DQ30 BB14 SA_DQ[29] M_B_DQ30 BG18 SB_DQ[29]
SA_DQ[30] M_A_DQSN[7:0] <13> SB_DQ[30] M_B_DQSN[7:0] <14>
M_A_DQ31 BB17 AL11 M_A_DQSN0 M_B_DQ31 BF19 AL3 M_B_DQSN0
M_A_DQ32 BA45 SA_DQ[31] SA_DQS#[0] AR8 M_A_DQSN1 M_B_DQ32 BD50 SB_DQ[31] SB_DQS#[0] AV3 M_B_DQSN1
M_A_DQ33 AR43 SA_DQ[32] SA_DQS#[1] AV11 M_A_DQSN2 M_B_DQ33 BF48 SB_DQ[32] SB_DQS#[1] BG11 M_B_DQSN2
M_A_DQ34 AW48 SA_DQ[33] SA_DQS#[2] AT17 M_A_DQSN3 M_B_DQ34 BD53 SB_DQ[33] SB_DQS#[2] BD17 M_B_DQSN3
M_A_DQ35 BC48 SA_DQ[34] SA_DQS#[3] AV45 M_A_DQSN4 M_B_DQ35 BF52 SB_DQ[34] SB_DQS#[3] BG51 M_B_DQSN4
DDR SYSTEM MEMORY A
SA_DQ[35] SA_DQS#[4] SB_DQ[35] SB_DQS#[4]
DDR SYSTEM MEMORY B

M_A_DQ36 BC45 AY51 M_A_DQSN5 M_B_DQ36 BD49 BA59 M_B_DQSN5
M_A_DQ37 AR45 SA_DQ[36] SA_DQS#[5] AT55 M_A_DQSN6 M_B_DQ37 BE49 SB_DQ[36] SB_DQS#[5] AT60 M_B_DQSN6
M_A_DQ38 AT48 SA_DQ[37] SA_DQS#[6] AK55 M_A_DQSN7 M_B_DQ38 BD54 SB_DQ[37] SB_DQS#[6] AK59 M_B_DQSN7
M_A_DQ39 AY48 SA_DQ[38] SA_DQS#[7] M_B_DQ39 BE53 SB_DQ[38] SB_DQS#[7]
C SA_DQ[39] SB_DQ[39] C
M_A_DQ40 BA49 M_B_DQ40 BF56
M_A_DQ41 AV49 SA_DQ[40] M_B_DQ41 BE57 SB_DQ[40]
M_A_DQ42 BB51 SA_DQ[41] M_B_DQ42 BC59 SB_DQ[41]
M_A_DQ43 AY53 SA_DQ[42] M_B_DQ43 AY60 SB_DQ[42]
M_A_DQ44 BB49 SA_DQ[43] M_B_DQ44 BE54 SB_DQ[43]
SA_DQ[44] M_A_DQSP[7:0] <13> SB_DQ[44]
M_A_DQ45 AU49 AJ11 M_A_DQSP0 M_B_DQ45 BG54
SA_DQ[45] SA_DQS[0] SB_DQ[45] M_B_DQSP[7:0] <14>
M_A_DQ46 BA53 AR10 M_A_DQSP1 M_B_DQ46 BA58 AM2 M_B_DQSP0
M_A_DQ47 BB55 SA_DQ[46] SA_DQS[1] AY11 M_A_DQSP2 M_B_DQ47 AW59 SB_DQ[46] SB_DQS[0] AV1 M_B_DQSP1
M_A_DQ48 BA55 SA_DQ[47] SA_DQS[2] AU17 M_A_DQSP3 M_B_DQ48 AW58 SB_DQ[47] SB_DQS[1] BE11 M_B_DQSP2
M_A_DQ49 AV56 SA_DQ[48] SA_DQS[3] AW45 M_A_DQSP4 M_B_DQ49 AU58 SB_DQ[48] SB_DQS[2] BD18 M_B_DQSP3
M_A_DQ50 AP50 SA_DQ[49] SA_DQS[4] AV51 M_A_DQSP5 M_B_DQ50 AN61 SB_DQ[49] SB_DQS[3] BE51 M_B_DQSP4
M_A_DQ51 AP53 SA_DQ[50] SA_DQS[5] AT56 M_A_DQSP6 M_B_DQ51 AN59 SB_DQ[50] SB_DQS[4] BA61 M_B_DQSP5
M_A_DQ52 AV54 SA_DQ[51] SA_DQS[6] AK54 M_A_DQSP7 M_B_DQ52 AU59 SB_DQ[51] SB_DQS[5] AR59 M_B_DQSP6
M_A_DQ53 AT54 SA_DQ[52] SA_DQS[7] M_B_DQ53 AU61 SB_DQ[52] SB_DQS[6] AK61 M_B_DQSP7
M_A_DQ54 AP56 SA_DQ[53] M_B_DQ54 AN58 SB_DQ[53] SB_DQS[7]
M_A_DQ55 AP52 SA_DQ[54] M_B_DQ55 AR58 SB_DQ[54]
M_A_DQ56 AN57 SA_DQ[55] M_B_DQ56 AK58 SB_DQ[55]
M_A_DQ57 AN53 SA_DQ[56] M_B_DQ57 AL58 SB_DQ[56]
M_A_DQ58 AG56 SA_DQ[57] M_B_DQ58 AG58 SB_DQ[57]
M_A_DQ59 AG53 SA_DQ[58] M_B_DQ59 AG59 SB_DQ[58]
M_A_DQ60 AN55 SA_DQ[59] M_B_DQ60 AM60 SB_DQ[59]
SA_DQ[60] M_A_A[15:0] <13> SB_DQ[60] M_B_A[15:0] <14>
M_A_DQ61 AN52 BG35 M_A_A0 M_B_DQ61 AL59 BF32 M_B_A0
M_A_DQ62 AG55 SA_DQ[61] SA_MA[0] BB34 M_A_A1 M_B_DQ62 AF61 SB_DQ[61] SB_MA[0] BE33 M_B_A1
M_A_DQ63 AK56 SA_DQ[62] SA_MA[1] BE35 M_A_A2 M_B_DQ63 AH60 SB_DQ[62] SB_MA[1] BD33 M_B_A2
SA_DQ[63] SA_MA[2] BD35 M_A_A3 SB_DQ[63] SB_MA[2] AU30 M_B_A3
SA_MA[3] AT34 M_A_A4 SB_MA[3] BD30 M_B_A4
SA_MA[4] AU34 M_A_A5 SB_MA[4] AV30 M_B_A5
SA_MA[5] BB32 M_A_A6 SB_MA[5] BG30 M_B_A6
BD37 SA_MA[6] AT32 M_A_A7 BG39 SB_MA[6] BD29 M_B_A7
<13> M_A_BS#0 BF36 SA_BS[0] SA_MA[7] AY32 <14> M_B_BS#0 BD42 SB_BS[0] SB_MA[7] BE30
M_A_A8 M_B_A8
<13> M_A_BS#1 BA28 SA_BS[1] SA_MA[8] AV32 <14> M_B_BS#1 AT22 SB_BS[1] SB_MA[8] BE28
M_A_A9 M_B_A9
<13> M_A_BS#2 SA_BS[2] SA_MA[9] BE37 <14> M_B_BS#2 SB_BS[2] SB_MA[9] BD43
M_A_A10 M_B_A10
SA_MA[10] BA30 M_A_A11 SB_MA[10] AT28 M_B_A11
SA_MA[11] BC30 M_A_A12 SB_MA[11] AV28 M_B_A12
B B
BE39 SA_MA[12] AW41 M_A_A13 AV43 SB_MA[12] BD46 M_B_A13
<13> M_A_CAS# BD39 SA_CAS# SA_MA[13] AY28 <14> M_B_CAS# BF40 SB_CAS# SB_MA[13] AT26
M_A_A14 M_B_A14
<13> M_A_RAS# AT41 SA_RAS# SA_MA[14] AU26 <14> M_B_RAS# BD45 SB_RAS# SB_MA[14] AU22
M_A_A15 M_B_A15
<13> M_A_WE# SA_WE# SA_MA[15] <14> M_B_WE# SB_WE# SB_MA[15]
SNB_2CBGA_1P0 SNB_2CBGA_1P0 M_B_CLK1
R588
75/F_4
+0.75V_DDR_VTT
M_B_CLK1#
C758 C757 C756 C755 C753 C754 C759

1u/6.3V_41u/6.3V_4 1u/6.3V_41u/6.3V_41u/6.3V_4 1u/6.3V_4 10u/6.3V_8
20120112 for memory down PU CAP.
+3V_S5
+1.5VSUS 201201119 move R358 to near Q38 and del net DRAMRST_CNTRL_PCH,
s3 leakage circuit and EC_DRAMRST_CNTRL and R616. +0.75V_DDR_VTT
S3 circuit:- DRAM_RST# to memory should be high during S3
A R579 *0_4 M_B_A0 R550 36_4 A
R580 R358 M_B_A1 R555 36_4
1K/F_4 1K_4 M_B_A2 R554 36_4
M_B_A3 R531 36_4
Q38 2N7002K M_B_A4 R562 36_4
R577 1K/F_4 3 1 M_B_A5 R565 36_4 +0.75V_DDR_VTT
<13,14> DDR3_DRAMRST# CPU_DRAMRST# <3,24>
M_B_A6 R570 36_4
M_B_A7 R569 36_4 M_B_WE# R535 36_4
M_B_A8 R571 36_4 M_B_CAS# R539 36_4
2
<9> DRAMRST_CNTRL_PCH R573 *0_4 M_B_A9 R557 36_4 M_B_RAS# R542 36_4
M_B_A10 R537 36_4 M_B_BS#0 R534 36_4
R582 M_B_A11 R563 36_4 M_B_BS#2 R533 36_4
<24> EC_DRAMRST_CNTRL R574 0_4 C610 4.99K/F_4 M_B_A12 R549 36_4 M_B_CKE0 R540 36_4
PROJECT : Z09
0.047u/10V_4 M_B_A13 R567 36_4 M_B_ODT0 R541 36_4 Size Document Number Rev
M_B_A14 R568 36_4 M_B_CS#0 R538 36_4
<13,14> DEEPS3_EC M_B_A15 R536 36_4 M_B_BS#1 R532 36_4
Ivy Bridge 3/5 3A
20120204 Change to EC for new BIOS 0.6 Date: Monday, April 09, 2012 Sheet 4 of 40
5 4 3 2 1
5 4 3 2 1
CPU VCCIO
Sandy Bridge Processor (POWER) IVY 17W:8.5A
CPU VCCAXG
Cose down IVY 17W:TDC 18A CPU VDDQ
U9F SNB : Spec Sandy Bridge Processor (GRAPHIC POWER) IVY 45W: 5A
330uF/6mohm x 2 330uF/6mohm x 1
Spec Cose down
+1.05V_VTT U9G
3.9m/LoadlineDesign 3.9m/LoadlineDesign Spec
10uF x 10 10uF x 10 total : 1uF x 11 total : 1uF x 11 +VCC_GFX
total : 10uF x 6 total : 10uF x 12 330uF/6mohm x 1
AF46 1uF x 26 1uF x 26
+VCC_CORE VCCIO[1]
VCCIO[3]
AG48 total : 22uF x 6 tatal : 470u x 1(power side*2) CAD Note: +VDDR_REF_CPU should 10uF x 8
AG50 AA46
20120120 remove C621 for debug IC. A26 VCCIO[4] AG51 tatal : 470u x 1(power side*2) AB47 VAXG[1] have 10 mil trace width
VCC[1] VCCIO[5] VAXG[2] 1uF x 10
A29 AJ17 C730 AB50
A31 VCC[2] VCCIO[6] AJ21 + AB51 VAXG[3] AY43
VCC[3] VCCIO[7] VAXG[4] SM_VREF +VDDR_REF_CPU
C235 C237 C238 A34 AJ25 + C603 + C215 AB52
A35 VCC[4] VCCIO[8] AJ43 *330u/2V_7343 330u/2V_7343 470u/2V_7343 AB53 VAXG[5]
D D
10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 A38 VCC[5] VCCIO[9] AJ47 AB55 VAXG[6] +1.5V_CPU
A39 VCC[6] VCCIO[10] AK50 AB56 VAXG[7]
A42 VCC[7] VCCIO[11] AK51 AB58 VAXG[8]
C26 VCC[8] VCCIO[12] AL14 AB59 VAXG[9] AJ28
C27 VCC[9] VCCIO[13] AL15 AC61 VAXG[10] VDDQ[1] AJ33
C32 VCC[10] VCCIO[14] AL16 C729 C283 C282 C726 C281 C728 AD47 VAXG[11] VDDQ[2] AJ36
C697 C692 C693 C704 C34 VCC[11] VCCIO[15] AL20 AD48 VAXG[12] VDDQ[3] AJ40 C667 C662 C682 C681 C668
C37 VCC[12] VCCIO[16] AL22 C181 C639 C184 C652 C182 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 AD50 VAXG[13] VDDQ[4] AL30 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6
10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 C39 VCC[13] VCCIO[17] AL26 AD51 VAXG[14] VDDQ[5] AL34
- 1.5V RAILS
C42 VCC[14] VCCIO[18] AL45 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 AD52 VAXG[15] VDDQ[6] AL38
D27 VCC[15] VCCIO[19] AL48 AD53 VAXG[16] VDDQ[7] AL42
D32 VCC[16] VCCIO[20] AM16 AD55 VAXG[17] VDDQ[8] AM33
20120120 remove C622 for debug IC. D34 VCC[17] VCCIO[21] AM17 AD56 VAXG[18] VDDQ[9] AM36
D37 VCC[18] VCCIO[22] AM21 C278 C725 C285 C724 C284 C292 AD58 VAXG[19] VDDQ[10] AM40
C696 C236 C703 D39 VCC[19] VCCIO[23] AM43 AD59 VAXG[20] VDDQ[11] AN30 C242
D42 VCC[20] VCCIO[24] AM47 C656 C180 C604 C710 C183 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 AE46 VAXG[21] VDDQ[12] AN34 C666 C691 C680 +
10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 E26 VCC[21] VCCIO[25] AN20 N45 VAXG[22] VDDQ[13] AN38 10u/6.3V_6 *10u/6.3V_6 *10u/6.3V_6
POWER
E28 VCC[22] VCCIO[26] AN42 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 P47 VAXG[23] VDDQ[14] AR26 330u/2V_7343
E32 VCC[23] VCCIO[27] AN45 P48 VAXG[24] VDDQ[15] AR28
E34 VCC[24] VCCIO[28] AN48 P50 VAXG[25] VDDQ[16] AR30
E37 VCC[25] VCCIO[29] P51 VAXG[26] VDDQ[17] AR32
E38 VCC[26] C712 C708 C713 C701 C707 P52 VAXG[27] VDDQ[18] AR34
DDR3
VCC[27] VAXG[28] VDDQ[19]
CORE SUPPLY
F25 P53 AR36 C655 C665 C677 C664 C654
F26 VCC[28] 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 P55 VAXG[29] VDDQ[20] AR40
PEG AND DDR

F28 VCC[29] C630 C620 C635 C624 C642 C611 C702 C626 C186 C709 C715 C716 C185 P56 VAXG[30] VDDQ[21] AV41 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4
F32 VCC[30] P61 VAXG[31] VDDQ[22] AW26
F34 VCC[31] 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 T48 VAXG[32] VDDQ[23] BA40
VCC[32] VAXG[33] VDDQ[24]
GRAPHICS
F37 AA14 T58 BB28
F38 VCC[33] VCCIO[30] AA15 T59 VAXG[34] VDDQ[25] BG33
F42 VCC[34] VCCIO[31] AB17 C711 C706 C714 C698 C700 C699 T61 VAXG[35] VDDQ[26]
G42 VCC[35] VCCIO[32] AB20 U46 VAXG[36] C676 C690 C689 C663 C675
H25 VCC[36] VCCIO[33] AC13 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 V47 VAXG[37]
H26 VCC[37] VCCIO[34] AD16 C619 C615 C633 C641 C623 C694 C616 C705 C605 C634 C612 C613 C614 V48 VAXG[38] 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4
C231 C240 C244 C629 C246 C653 C241 H28 VCC[38] VCCIO[35] AD18 V50 VAXG[39]
H29 VCC[39] VCCIO[36] AD21 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 V51 VAXG[40]
2.2u/10V_4 2.2u/10V_4 2.2u/10V_4 2.2u/10V_4 2.2u/10V_4 2.2u/10V_4 2.2u/10V_4 H32 VCC[40] VCCIO[37] AE14 V52 VAXG[41]
H34 VCC[41] VCCIO[38] AE15 V53 VAXG[42]
C C
H35 VCC[42] VCCIO[39] AF16 V55 VAXG[43]
H40 VCC[45] VCCIO[42] AG15 V59 VAXG[46]
VCC[46] VCCIO[43] IVY SPEC VAXG[47]
C669 C683 C658 C684 C670 C657 C645 J25 AG16 22uF_8 x7 Socket TOP cavity W50
J26 VCC[47] VCCIO[44] AG17 W51 VAXG[48]
J28 VCC[48] VCCIO[45] AG20
22uF_8 x5 Socket BOT cavity W52 VAXG[49]
2.2u/10V_4 2.2u/10V_4 2.2u/10V_4 2.2u/10V_4 2.2u/10V_4 2.2u/10V_4 2.2u/10V_4
J29 VCC[49] VCCIO[46] AG21 22uF_8 x2 Socket TOP cavity (no stuff) W53 VAXG[50]
J32 VCC[50] VCCIO[47] AJ14 22uF_8 x5 Socket BOT cavity (no stuff) W55 VAXG[51]
VCC[51] VCCIO[48] 330uF_7343 x2 VAXG[52]
POWER
J34 AJ15 W56
J35 VCC[52] VCCIO[49] W61 VAXG[53]
J37 VCC[53] Y48 VAXG[54]
C251 C646 C628 C232 C678 C250 C239 J38 VCC[54] Y61 VAXG[55]
VCC[55] VCCAXG_SENSE/VSSAXG_SENSE R=100, VAXG[56]
J40
2.2u/10V_4 2.2u/10V_4 2.2u/10V_4 2.2u/10V_4 2.2u/10V_4 2.2u/10V_4 2.2u/10V_4 J42 VCC[56] Trace impedance 15.5~34.5, <25mils.
K26 VCC[57] W16 R187 *SHORT_6
VCC[58] VCCIO50 +1.05V_VTT
K27 W17
VCC[59] VCCIO51 TP69
K29
QUIET RAILS
K32 VCC[60] R593 100_4 AM28
VCC[61] Voltage selection for VCCIO: +VCC_GFX VCCDQ[1] +1.5V_CPU
LINES
SENSE
K34 F45 AN26
C671 C685 C687 C695 C686 C659 C647 K35 VCC[62] this pin must be pulled high CPU VCCPL <33> VCC_AXG_SENSE
G45 VAXG_SENSE VCCDQ[2] C650 1U/6.3V_4X
VCC[63] <33> VSS_AXG_SENSE VSSAXG_SENSE
K37 IVY 17W:1.5A R594 100_4
2.2u/10V_4 2.2u/10V_4 2.2u/10V_4 2.2u/10V_4 2.2u/10V_4 2.2u/10V_4 2.2u/10V_4 K39 VCC[64] on the motherboard
VCC[66] TP70
K42 BC22 VCCIO_SEL
L25 VCC[67] VCCIO_SEL TP64
On CRB Spec Real
VCC[68]
1.8V RAIL
L28 H_SNB_IVB#_PWRCTRL = low, 1.0V 330uF/7mohm x 1 10uF x 1 R566 *SHORT_8
VCC[69] +1.8V
L33 H_SNB_IVB#_PWRCTRL = high/NC, 1.05V
L36 VCC[70] R560 *SHORT_8 CPU_VCCPLL BB3
VCC[71] 1uF x 2 1uF x 2 VCCPLL[1]
C673 C672 C245 C648 C649 C660 C661 L40 BC1
QUIET RAILS
N26 VCC[72] +1.05V_VTT C200 C192 + C177 BC4 VCCPLL[2]

2.2u/10V_4 2.2u/10V_4 2.2u/10V_4 2.2u/10V_4 2.2u/10V_4 2.2u/10V_4 2.2u/10V_4 N30 VCC[73] AM25 R581 *SHORT_4 1u/6.3V_4 1u/6.3V_4 VCCPLL[3]
N34 VCC[74] VCCPQE[1] AN22 *330u/2V_7343
VCC[75] VCCPQE[2] IVY SPEC
N38 C632 1U/6.3V_4X 330uF x1, 10uF_8 x1, 1uF_4 x2
VCC[76] BC43 R590 *51_4
CPU Core Power Socket BOT edge. +VCCSA VDDQ_SENSE BA43 R592 *51_4
+1.5V_CPU
SENSE LINES
VSS_SENSE_VDDQ
IVY 17W:TDC 33A L17
B B
L21 VCCSA[1]
IVY SPEC VCCSA[2]
N16
1.9m/LoadlineDesign A44 H_CPU_SVIDALRT# N20 VCCSA[3]
total : 2.2uF x 35 VIDALERT# VCCSA[4]
SA RAIL
C674 C247 B43 H_CPU_SVIDCLK C627 C618 N22
SVID
VIDSCLK C44 P17 VCCSA[5]

total : 22uF x 12 + +
VIDSOUT
H_CPU_SVIDDAT IVY SPEC C609 C636 C651 + C178
VCCSA[6]
R575 *100/F_4 +VCCSA
330uF x1, 10uF_8 x1 Socket BOT edge, 10u/6.3V_6 10u/6.3V_610u/6.3V_6 10u/6.3V_6 10u/6.3V_6 330u/2V_7343 P20 U10
tatal : 470u x3(Power side*1) 470u/2V_7343 470u/2V_7343 R16 VCCSA[7] VCCSA_SENSE VCCSA_SENSE <36>
10uF_8 x2 Socket BOT cavity. VCCSA[8] SNB_IVB# N.A at SNB EDS #27637 0.7v1
R18
R21 VCCSA[9] R217 *10K_4
Cose down CPU VCCSA U15 VCCSA[10] 201201117 C767 for Intel fw issue, if solve need un-stuff.
V16 VCCSA[11] C767 *33n/10V_4
IVY SPEC IVY 17W: 6A VCCSA[12]
V17 D48 R220 IVB@0_4
1.9m/LoadlineDesign Spec V18 VCCSA[13] VCCSA_VID[0] D49
VCCSA_VID0 <36>
VCCSA[14] VCCSA_VID[1] VCCSA_VID1 <36>
total : 2.2uF x 35 R591 100_4 330uF/7mohm x 1 V21
total : 10uF x 12 F43
+VCC_CORE
VCC_SENSE <33> 10uF x 5
Real C608 C617 C631 C637 C625 W20 VCCSA[15] R597 *10K_4
SENSE LINES
VCC_SENSE G43 VCCSA[16] A 1-K pull-down resistor should be placed on the

tatal : 470u x1(Power side*1) VSS_SENSE VSS_SENSE <33> 1uF x 5 10uF x 3 VCCSA VID lines. This will ensure the VID
R589 100_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4
is 00 prior to VCCIO stability..
R94 for SN Bridge
R576 10_4 +1.05V_VTT
AN16 SNB_2CBGA_1P0
VCCIO_SENSE VCCP_SENSE <34>
AN17 For SN Bridge
VSS_SENSE_VCCIO VSSP_SENSE <34>
R578 10_4
S3 STUFF NO_STUFF 20111107 stuff Q5010 and un-staff R5347/R362. VID[1] +VCCSA
4.5A
+1.5VSUS R210 *0_1206 +1.5V_CPU 0 0.9V
enable - R5347/R6362
SNB_2CBGA_1P0 1 0.8V
disable - R211 *0_1206
R5347/R6362
Q41 AO4496 For IV Bridge
8 1
+SMDDR_VREF +VDDR_REF_CPU +1.5V_CPU 7 2 VID[0] VID[1] +VCCSA
6 3
20111024 from +1.5VSUS change to +1.5V_CPU 5 0 0 0.9V
A R234 *0_8 R221 0 1 0.8V A
4
*1K/F_4
Layout note: need routing 1 0 0.725V
MAIND
together and ALERT need Place PU resistor close to CPU 3 1 R583 1 1 0.675V
Place PU resistor close to CPU C688 220_8
between CLK and DATA +1.05V_VTT +1.05V_VTT Q7 470P/50V_4
2N7002K
3
MAIND R218
SVID DATA <32,35,37> MAIND
100K_4 R215
SVID ALERT
SVID CLK R202 R213
*1K/F_4
MAINON_G 2 Quanta Computer Inc.
<3,37> MAINON_G
130/F_4 75/F_4 S3 circuit: 1.5V input to IVB is gated &
H_CPU_SVIDCLK R203 *SHORT_4 Q39
VR_SVID_CLK <33>
H_CPU_SVIDDAT R205 *SHORT_4 VR_SVID_DATA <33> H_CPU_SVIDALRT# R208 43_4 VR_SVID_ALERT#_R R212 *SHORT_4 VR_SVID_ALERT# <33>
IVB Read Vref 0.75V is gated change to 1K/F_4 DMN601K-7 PROJECT : Z09
1
3A
Ivy Bridge 4/5
5 4 3 2 1
5 4 3 2 1
Sandy Bridge Processor (GND) Sandy Bridge Processor (RESERVED, CFG)

U9H U9I BE7 SA_DIMM_VREFDQ
U9E BG7 SB_DIMM_VREFDQ
R572 *1K_4
BG17 M4
A13 AM38 BG21 VSS[181] VSS[251] M58 B50 BE7
VSS[1] VSS[91] VSS[182] VSS[252] TP76 CFG[0] RSVD28 SMDDR_VREF_DQ0_M3 <13>
D A17 AM4 BG24 M6 CFG1 C51 BG7 D
VSS[2] VSS[92] VSS[183] VSS[253] TP96 CFG[1] RSVD29 SMDDR_VREF_DQ1_M3 <14>
A21 AM42 BG28 N1 CFG2 B54
A25 VSS[3] VSS[93] AM45 BG37 VSS[184] VSS[254] N17 CFG3 D53 CFG[2] R197 *1K_4
A28 VSS[4] VSS[94] AM48 BG41 VSS[185] VSS[255] N21 CFG4 A51 CFG[3] N42
A33 VSS[5] VSS[95] AM58 BG45 VSS[186] VSS[256] N25 CFG5 C53 CFG[4] RSVD30 L42 processor signal balls BF3 and BG4 for
A37 VSS[6] VSS[96] AN1 BG49 VSS[187] VSS[257] N28 CFG6 C55 CFG[5] RSVD31 L45 Ivy Bridge 4-core and balls BE7
A40 VSS[7] VSS[97] AN21 BG53 VSS[188] VSS[258] N33 CFG7 H49 CFG[6] RSVD32 L47 and BG7 for Ivy Bridge 2-core
A45 VSS[8] VSS[98] AN25 BG9 VSS[189] VSS[259] N36 A55 CFG[7] RSVD33
A49 VSS[9] VSS[99] AN28 C29 VSS[190] VSS[260] N40 H51 CFG[8]
A53 VSS[10] VSS[100] AN33 C35 VSS[191] VSS[261] N43 K49 CFG[9] M13
A9 VSS[11] VSS[101] AN36 C40 VSS[192] VSS[262] N47 K53 CFG[10] RSVD34 M14
AA1 VSS[12] VSS[102] AN40 D10 VSS[193] VSS[263] N48 F53 CFG[11] RSVD35 U14
AA13 VSS[13] VSS[103] AN43 D14 VSS[194] VSS[264] N51 G53 CFG[12] RSVD36 W14
VSS[14] VSS[104] VSS[195] VSS[265] CFG[13] RSVD37 for M3 solution
AA50 AN47 D18 N52 L51 P13
AA51 VSS[15] VSS[105] AN50 D22 VSS[196] VSS[266] N56 F51 CFG[14] RSVD38 need R5265/R5266,
AA52 VSS[16] VSS[106] AN54 D26 VSS[197] VSS[267] N61 D52 CFG[15] W/O M3 then NC
AA53 VSS[17] VSS[107] AP10 D29 VSS[198] VSS[268] P14 L53 CFG[16] AT49
AA55 VSS[18] VSS[108] AP51 D35 VSS[199] VSS[269] P16 CFG[17] RSVD39 K24
AA56 VSS[19] VSS[109] AP55 D4 VSS[200] VSS[270] P18 RSVD40
RESERVED
AA8 VSS[20] VSS[110] AP7 D40 VSS[201] VSS[271] P21 H43
VSS[21] VSS[111] VSS[202] VSS[272] TP65 VCC_VAL_SENSE
AB16 AR13 D43 P58 K43 AH2
AB18
AB21
VSS[22]
VSS[23]
VSS[24]
VSS[112]
VSS[113]
VSS[114]
AR17
AR21
D46
D50
VSS[203]
VSS[204]
VSS[205]
VSS VSS[273]
VSS[274]
VSS[275]
P59
P9
TP68 VSS_VAL_SENSE RSVD41
RSVD42
RSVD43
AG13
AM14
AB48 AR41 D54 R17 TP66
H45 AM15
AB61 VSS[25] VSS[115] AR48 D58 VSS[206] VSS[276] R20 K45 VAXG_VAL_SENSE RSVD44
VSS[26] VSS[116] VSS[207] VSS[277] TP72 VSSAXG_VAL_SENSE
AC10 AR61 D6 R4
AC14 VSS[27] VSS[117] AR7 E25 VSS[208] VSS[278] R46 N50
AC46 VSS[28] VSS[118] AT14 E29 VSS[209] VSS[279] T1 F48 RSVD45
VSS[29] VSS[119] VSS[210] VSS[280] TP74 VCC_DIE_SENSE
AC6 AT19 E3 T47
C AD17 VSS[30] VSS[120] AT36 E35 VSS[211] VSS[281] T50 C
AD20 VSS[31] VSS[121] AT4 E40 VSS[212] VSS[282] T51 H48
VSS[32] VSS[122] VSS[213] VSS[283] TP71 RSVD6
AD4 AT45 F13 T52 K48
AD61
AE13
VSS[33]
VSS[34]
VSS[35]
VSS VSS[123]
VSS[124]
VSS[125]
AT52
AT58
F15
F19
VSS[214]
VSS[215]
VSS[216]
VSS[284]
VSS[285]
VSS[286]
T53
T55
TP73 RSVD7
DC_TEST_A4
DC_TEST_C4
A4
C4
AE8 AU1 F29 T56 BA19 D3
AF1 VSS[36] VSS[126] AU11 F35 VSS[217] VSS[287] U13 AV19 RSVD8 DC_TEST_D3 D1
AF17 VSS[37] VSS[127] AU28 F40 VSS[218] VSS[288] U8 AT21 RSVD9 DC_TEST_D1 A58
AF21 VSS[38] VSS[128] AU32 F55 VSS[219] VSS[289] V20 BB21 RSVD10 DC_TEST_A58 A59
AF47 VSS[39] VSS[129] AU51 G48 VSS[220] VSS[290] V61 BB19 RSVD11 DC_TEST_A59 C59
AF48 VSS[40] VSS[130] AU7 G51 VSS[221] VSS[291] W13 AY21 RSVD12 DC_TEST_C59 A61
AF50 VSS[41] VSS[131] AV17 R599 G6 VSS[222] VSS[292] W15 BA22 RSVD13 DC_TEST_A61 C61
AF51 VSS[42] VSS[132] AV21 *SNB@0_4 G61 VSS[223] VSS[293] W18 AY22 RSVD14 DC_TEST_C61 D61
AF52 VSS[43] VSS[133] AV22 H10 VSS[224] VSS[294] W21 AU19 RSVD15 DC_TEST_D61 BD61
AF53 VSS[44] VSS[134] AV34 H14 VSS[225] VSS[295] W46 AU21 RSVD16 DC_TEST_BD61 BE61
AF55 VSS[45] VSS[135] AV40 H17 VSS[226] VSS[296] W8 BD21 RSVD17 DC_TEST_BE61 BE59
AF56 VSS[46] VSS[136] AV48 H21 VSS[227] VSS[297] Y4 BD22 RSVD18 DC_TEST_BE59 BG61
AF58 VSS[47] VSS[137] AV55 H4 VSS[228] VSS[298] Y47 BD25 RSVD19 DC_TEST_BG61 BG59
AF59 VSS[48] VSS[138] AW13 H53 VSS[229] VSS[299] Y58 BD26 RSVD20 DC_TEST_BG59 BG58
AG10 VSS[49] VSS[139] AW43 H58 VSS[230] VSS[300] Y59 BG22 RSVD21 DC_TEST_BG58 BG4
AG14 VSS[50] VSS[140] AW61 J1 VSS[231] VSS[301] BE22 RSVD22 DC_TEST_BG4 BG3
AG18 VSS[51] VSS[141] AW7 J49 VSS[232] BG26 RSVD23 DC_TEST_BG3 BE3
AG47 VSS[52] VSS[142] AY14 J55 VSS[233] BE26 RSVD24 DC_TEST_BE3 BG1
AG52 VSS[53] VSS[143] AY19 K11 VSS[234] BF23 RSVD25 DC_TEST_BG1 BE1
AG61 VSS[54] VSS[144] AY30 K21 VSS[235] BE24 RSVD26 DC_TEST_BE1 BD1
AG7 VSS[55] VSS[145] AY36 K51 VSS[236] A5 RSVD27 DC_TEST_BD1
AH4 VSS[56] VSS[146] AY4 K8 VSS[237] VSS_NCTF_1 A57
AH58 VSS[57] VSS[147] AY41 L16 VSS[238] VSS_NCTF_2 BC61
AJ13 VSS[58] VSS[148] AY45 L20 VSS[239] VSS_NCTF_3 BD3
B AJ16 VSS[59] VSS[149] AY49 L22 VSS[240] VSS_NCTF_4 BD59 SNB_2CBGA_1P0 B
VSS[60] VSS[150] VSS[241] VSS_NCTF_5
NCTF
AJ20 AY55 L26 BE4

AJ22 VSS[61] VSS[151] AY58 L30 VSS[242] VSS_NCTF_6 BE58
AJ26 VSS[62] VSS[152] AY9 L34 VSS[243] VSS_NCTF_7 BG5
AJ30 VSS[63] VSS[153] BA1 L38 VSS[244] VSS_NCTF_8 BG57 CFG5 R225 *1K/F_4
AJ34 VSS[64] VSS[154] BA11 L43 VSS[245] VSS_NCTF_9 C3 CFG6 R227 *1K/F_4
AJ38 VSS[65] VSS[155] BA17 L48 VSS[246] VSS_NCTF_10 C58
AJ42 VSS[66] VSS[156] BA21 L61 VSS[247] VSS_NCTF_11 D59
AJ45 VSS[67] VSS[157] BA26 M11 VSS[248] VSS_NCTF_12 E1
AJ48 VSS[68] VSS[158] BA32 M15 VSS[249] VSS_NCTF_13 E61
CFG[6:5] (PCIE Port Bifurcation Straps)
AJ7 VSS[69] VSS[159] BA48 VSS[250] VSS_NCTF_14
VSS[70] VSS[160]
11: (Default) x16 - Device 1 functions 1 and 2 disabled
AK1 BA51 10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled
AK52 VSS[71] VSS[161] BB53
AL10 VSS[72] VSS[162] BC13
01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)
AL13 VSS[73] VSS[163] BC5 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
AL17 VSS[74] VSS[164] BC57 SNB_2CBGA_1P0
AL21 VSS[75] VSS[165] BD12
AL25 VSS[76] VSS[166] BD16
AL28 VSS[77] VSS[167] BD19
AL33 VSS[78] VSS[168] BD23
AL36 VSS[79]
VSS[80]
VSS[169]
VSS[170]
BD27 Processor Strapping The CFG signals have a default value of '1' if not terminated on the board. CFG2 R226 1K/F_4
AL40 BD32
AL43 VSS[81] VSS[171] BD36 20111102 stuff for revers
AL47 VSS[82] VSS[172] BD40
AL61 VSS[83] VSS[173] BD44
1 0
AM13 VSS[84] VSS[174] BD48 CFG3 R224 *1K/F_4
AM20 VSS[85] VSS[175] BD52
CFG2
AM22 VSS[86] VSS[176] BD56 (PCI-E Static x16 Lane Reversal) Normal Operation Lane Reversed CFG4 R223 1K/F_4
AM26 VSS[87] VSS[177] BD8
A VSS[88] VSS[178] A
AM30 BE5 CFG3 CFG7 R222 *1K/F_4
AM34 VSS[89] VSS[179] BG13
VSS[90] VSS[180] (PCI-E Static x4 Lane Reversal) Normal Operation Lane Reversed
CFG4
Disable; No physical DP attached to eDP Enable; An ext DP device is connected to eDP
SNB_2CBGA_1P0
(DP Presence Strap) Quanta Computer Inc.
CFG7
PROJECT : Z09
PEG train immediately following PEG wait for BIOS training Size Document Number Rev
(PEG Defer Training)
xxRESETB de assertion Ivy Bridge 5/5 3A

5 4 3 2 1
5 4 3 2 1
CPT/PPT (LVDS,DDI)
U26D
07
CPT/PPT (DMI,FDI,PM) <15> INT_LVDS_BLON
J47
M45 L_BKLTEN SDVO_TVCLKINN
AP43
AP45
<15> INT_LVDS_DIGON L_VDD_EN SDVO_TVCLKINP
U26C Need notice BIOS if DMI or FDI reverse. P45 AM42
<15> INT_LVDS_BRIGHT L_BKLTCTL SDVO_STALLN AM40
D BC24 BJ14 T40 SDVO_STALLP D
<2> DMI_RXN0 DMI0RXN FDI_RXN0 FDI_TXN0 <2> L_DDC_CLK
BE20 AY14 K47 AP39
<2> DMI_RXN1 DMI1RXN FDI_RXN1 FDI_TXN1 <2> L_DDC_DATA SDVO_INTN
BG18 BE14 AP40
<2> DMI_RXN2 DMI2RXN FDI_RXN2 FDI_TXN2 <2> SDVO_INTP
BG20 BH13 T45
<2> DMI_RXN3 DMI3RXN FDI_RXN3 FDI_TXN3 <2> L_CTRL_CLK
BC12 P39
BE24 FDI_RXN4 BJ12 FDI_TXN4 <2> L_CTRL_DATA
<2> DMI_RXP0 DMI0RXP FDI_RXN5 FDI_TXN5 <2>
BC20 BG10 AF37 P38
<2> DMI_RXP1 DMI1RXP FDI_RXN6 FDI_TXN6 <2> LVD_IBG SDVO_CTRLCLK HDMI_DDCCLK_SW <16>
BJ18 BG9 AF36 M39
<2> DMI_RXP2 DMI2RXP FDI_RXN7 FDI_TXN7 <2> LVD_VBG SDVO_CTRLDATA HDMI_DDCDATA_SW <16>
BJ20
<2> DMI_RXP3 DMI3RXP BG14 AE48
FDI_RXP0 FDI_TXP0 <2> LVD_VREFH
INT. HDMI
AW24 BB14 AE47 AT49
<2> DMI_TXN0 DMI0TXN FDI_RXP1 FDI_TXP1 <2> LVD_VREFL DDPB_AUXN
AW20 BF14 AT47
<2> DMI_TXN1 DMI1TXN FDI_RXP2 FDI_TXP2 <2> DDPB_AUXP
BB18 BG13 AT40
<2> DMI_TXN2 DMI2TXN FDI_RXP3 FDI_TXP3 <2> DDPB_HPD HDMI_HP <16>
AV18 BE12 AK39
DMI
FDI
<2> DMI_TXN3
LVDS
DMI3TXN FDI_RXP4 BG12 FDI_TXP4 <2> AK40 LVDSA_CLK# AV42 INT_HDMITX2N_C
AY24 FDI_RXP5 BJ10 FDI_TXP5 <2> LVDSA_CLK DDPB_0N AV40 INT_HDMITX2N_C <16>
<2> DMI_TXP0 INT_HDMITX2P_C
AY20 DMI0TXP FDI_RXP6 BH9 FDI_TXP6 <2> AN48 DDPB_0P AV45 INT_HDMITX2P_C <16>
<2> DMI_TXP1 INT_HDMITX1N_C
AY18 DMI1TXP FDI_RXP7 FDI_TXP7 <2> AM47 LVDSA_DATA#0 DDPB_1N AV46 INT_HDMITX1N_C <16>
INT_HDMITX1P_C
Digital Display Interface

<2> DMI_TXP2 DMI2TXP LVDSA_DATA#1 DDPB_1P INT_HDMITX1P_C <16>
AU18 20111102 FDI reverse AK47 AU48 INT_HDMITX0N_C
<2> DMI_TXP3 DMI3TXP LVDSA_DATA#2 DDPB_2N INT_HDMITX0N_C <16>
AW16 20111111 FDI change to normal AJ48 AU47 INT_HDMITX0P_C
FDI_INT FDI_INT <2> LVDSA_DATA#3 DDPB_2P AV47 INT_HDMITX0P_C <16>
20111102 DMI reverse INT_HDMICLK-_C
BJ24 AV12 AN47 DDPB_3N AV49 INT_HDMICLK-_C <16>
20111111 DMI change to normal INT_HDMICLK+_C
DMI_ZCOMP FDI_FSYNC0 FDI_FSYNC0 <2> AM49 LVDSA_DATA0 DDPB_3P INT_HDMICLK+_C <16>
R505 49.9/F_4 DMI_COMP BG25 BC10 AK49 LVDSA_DATA1
+1.05V_VTT DMI_IRCOMP FDI_FSYNC1 FDI_FSYNC1 <2> LVDSA_DATA2
AJ47 P46
R502 750/F_4 BH21 AV14 LVDSA_DATA3 DDPC_CTRLCLK P42
DMI2RBIAS FDI_LSYNC0 FDI_LSYNC0 <2> DDPC_CTRLDATA
DisplayPort C
BB10 AF40
FDI_LSYNC1 FDI_LSYNC1 <2> AF39 LVDSB_CLK# AP47
C
LVDSB_CLK DDPC_AUXN AP49 C
20110214 add SUSWAEN to SUSACK connector. DPWROK need to be AH45 DDPC_AUXP AT38
A18 shorted to RSMRST# when Deep S4/S5 state is not support AH47 LVDSB_DATA#0 DDPC_HPD
DSWVRMEN DSWVREN <8> LVDSB_DATA#1
SUSWARN#_R R642 0_4 AF49 AY47
LVDSB_DATA#2 DDPC_0N
System Power Management

AF45 AY49
R91 *0_4 SUSACK#_R C12 E22 DPWROK_R R94 0_4 20120104 change DPWROK from PCH_Rsmrst# to EC control. LVDSB_DATA#3 DDPC_0P AY43
<24> SUSACK# SUSACK# DPWROK DPWROK <24> DDPC_1N
AH43 AY45
XDP_DBRST# AH49 LVDSB_DATA0 DDPC_1P BA47
<3> XDP_DBRST# LVDSB_DATA1 DDPC_2N
K3 B9 PCIE_WAKE#_LAN R397 0_4 AF47 BA48
SYS_RESET# WAKE# PCIE_LAN_WAKE# <17> LVDSB_DATA2 DDPC_2P
C431 *1U/10V_4 AF43 BB47
20111206 add R5193 un-stuff for normal s3 PCIE LAN wake up. LVDSB_DATA3 DDPC_3N BB49
SYS_PWROK R405 *SHORT_4 SYS_PWROK_R P12 N3 CLKRUN# DDPC_3P
SYS_PWROK +3V CLKRUN# / GPIO32 CLKRUN# <19,24>
N48 M43
R382 *0_4 EC_PWROK_R L22 G8 P49 CRT_BLUE DDPD_CTRLCLK M36
PWROK +3V_S5 SUS_STAT# / GPIO61 LPCPD# <19> CRT_GREEN DDPD_CTRLDATA
DisplayPort D
R403 *SHORT_4 T49
CRT_RED
PWROK_EC R414 *SHORT_4 APWROK_R L10 +3V_S5 N14 PCH_SUSCLK 20111123 add for TPM LPCPD# pin. AT45
CRT
APWROK SUSCLK / GPIO62 TP36 DDPD_AUXN
R404 *SHORT_4 T39 AT43
M40 CRT_DDC_CLK DDPD_AUXP BH41
PM_DRAM_PWRGD B13 D10 CRT_DDC_DATA DDPD_HPD
<3> PM_DRAM_PWRGD DRAMPWROK +3V_S5 SLP_S5# / GPIO63 TP35
BB43
M47 DDPD_0N BB45
PCH_RSMRST# C21 H4 M49 CRT_HSYNC DDPD_0P BF44
<24> PCH_RSMRST# RSMRST# SLP_S4# SUSC# <24> CRT_VSYNC DDPD_1N BE44
DDPD_1P BF42
R635 *0_4 SUSWARN#_R K16 F4 DAC_IREF T43 DDPD_2N BE42
<20,24> IOAC_PCIERST# SUSWARN#/SUSPWRDNACK/GPIO30 +3V_S5
SLP_S3# SUSB# <24> DAC_IREF DDPD_2P
T42 BJ42
CRT_IRTN DDPD_3N BG42
R69 *SHORT_4 E20 G10 SLP_A# R120 DDPD_3P
B <24> DNBSWON# PWRBTN# SLP_A# TP37 B
PM_PWRBTN# 1K/F_4 Panther Point_R1P0
TP40
ACPRESENT H20 DSW G16 SLP_SUS#
<31> ACPRESENT ACPRESENT / GPIO31 SLP_SUS# SLP_SUS# <11,24>
1% or 5%
PM_BATLOW# E10 AP14

BATLOW# / GPIO72 +3V_S5 PMSYNCH PM_SYNC <3>
PM_RI# A10 +3V_S5 K14 SLP_LAN#

RI# SLP_LAN# / GPIO29
Panther Point_R1P0
PCH Pull-high/low(CLG) System PWR_OK(CLG) IMVP_PWRGD PU +3V

+3V_S5
CRB 1.0 change R5196 to 1K PWROK_EC PD
+3V_S5
CRB 1.0 uses 1k +3V_S5
so AND gate output dont need PD again
+3V
CLKRUN# R429 8.2K_4 PM_RI# R359 10K_4 C434

C426 *0.1U/10V_4
XDP_DBRST# R433 4.99K/F_4 PM_BATLOW# R363 8.2K_4 0.1u/10V_4
5
R432 *1K_4 PCIE_WAKE#_LAN R398 10K_4 U25
5
to PCH Pin12, XDP and EE debug U24 2

2 4 IMVP_PWRGD <3,33>
PCH_RSMRST# R76 10K_4 SLP_LAN# R84 *10K_4 IMVP_PWRGD_R
A SYS_PWROK 4 1 A
<3> SYS_PWROK GFX_PWRGD <24,33>
SUSWARN#_R R62 10K_4 1 PWROK_EC
PWROK_EC <24>
*TC7SH08
3
SYS_PWROK R352 *10K_4 ACPRESENT R346 *10K_4 TC7SH08FU
3
201201119 stuff R346. R411

100K_4
PM_DRAM_PWRGD R396 200/F_4 Quanta Computer Inc.

wo S3 leakage, un-stuff R5180 R409 0_4
20111107 R5180 un-stuff. PROJECT : Z09
20111128 add 0ohm to passed IMVP_PERGD Size Document Number Rev
R406 *0_4 3A
include GFX_PWRGD to SYS_PWROK for PCH check
Panther Point 1/6
5 4 3 2 1
5 4 3 2 1
RTC Circuitry(RTC) +3V_RTC PCH2(CLG)

20mils
R35 20K_4 RTC_RST#
CPT/PPT (HDA,JTAG,SATA) 08
1
J2
C31
D14 1u/6.3V_4 C424 18p/50V_4
1
R545 *SHORT_6 30mils *SHORT_ PAD1
+3VPCU
2
VCCRTC_1 U26A
R48 20K_4 SRTC_RST# Y4 R408
20MIL BAT54C 32.768KHZ 10M_4 RTC_X1 A20 C38
RTCX1 FWH0 / LAD0 LPC_LAD0 <19,20,24>
1
J1 A38
LPC
FWH1 / LAD1 LPC_LAD1 <19,20,24>
R530 C38 C36 C425 18p/50V_4 RTC_X2 C20 B37
LPC_LAD2 <19,20,24>
2
1K_4 1u/6.3V_4 1u/6.3V_4 RTCX2 FWH2 / LAD2 C37
FWH3 / LAD3 LPC_LAD3 <19,20,24>
*SHORT_ PAD1 RTC_RST# D20
2
RTCRST# D36
D FWH4 / LFRAME# LPC_LFRAME# <19,20,24> D
SRTC_RST# G22 CRB 1.0 uses 10kohm
+5V_S5 SRTCRST# E36 PCH_DRQ#0
20MIL 20MIL TP5
RTC
R68 1M_4 SM_INTRUDER# K22 LDRQ0# K36 PCH_DRQ#1
20110530-modify +3V_RTC INTRUDER# +3V LDRQ1# / GPIO23 TP11
VCCRTC_2 1 3VCCRTC_3 R519 4.7K_4 VCCRTC_4 R518 4.7K_4
PCH_INVRMEN C17 V5
Q33 R517 Add MOSFET to separate CODEC SYNC signal INTVRMEN SERIRQ R135 8.2K_4
SERIRQ <19,24>
+3V
MMBT3904 20120109 change footprint. R349 *SHORT_4
+5V
2
1
68.1K/F_4 ZRH use 2N7002D AM3 SATA_RXN0 <21>

SATA0RXN
2
ACZ_BITCLK_R N34 AM1 SATA_RXP0 <21>
HDA_BCLK SATA0RXP
SATA 6G
AP7 SATA HDD
SATA0TXN SATA_TXN0 <21>
BT1 ACZ_SYNC_CODEC 1 3 ACZ_SYNC_R L34 AP5 SATA_TXP0 <21>
RTC SOCKET HDA_SYNC SATA0TXP 20110908 acer request HDD,MSATA need SATA3.
R529 Q21 SPKR T10 AM10 SATA_RXN1 <20>
<19> SPKR SPKR SATA1RXN
20MIL CRB 1.0 2N7002K AM8
SATA_RXP1 <20>
2
150K/F_4 R348 ACZ_RST#_R K34 SATA1RXP AP11

HDA_RST# SATA1TXN SATA_TXN1 <20> mSATA
20111117 change back RTC connect 1M_4 AP10 SATA_TXP1 <20>
20111118 change RTC connect to 2P. SATA1TXP
20111121 change back RTC connector to socket. E34 AD7
<19> PCH_AZ_CODEC_SDIN0 HDA_SDIN0 SATA2RXN
20111116 For EMI solution. AD5
HDA Bus(CLG) C430 22p/50V_4
TP9
G34
HDA_SDIN1
SATA2RXP
SATA2TXN
AH5
AH4
DG recommended that AC coupling capacitors should be
SATA2TXP TP15 close to the connector (<100 mils) for optimal signal quality.
R390 33_4 ACZ_BITCLK_R C34
<19> PCH_AZ_CODEC_BITCLK
IHDA
HDA_SDIN2 AB8
R347 33_4 ACZ_SYNC_CODEC A34 SATA3RXN AB10
<19> PCH_AZ_CODEC_SYNC HDA_SDIN3 SATA3RXP
UM77 SATA port 1,3 disable.
AF3
R51 33_4 ACZ_RST#_R SATA3TXN AF1
<19> PCH_AZ_CODEC_RST# SATA3TXP TP26
ACZ_SDOUT_R A36
SATA
R376 33_4 ACZ_SDOUT_R HDA_SDO Y7
<19> PCH_AZ_CODEC_SDOUT SATA4RXN Y5
PCH_GPIO33 C36 SATA4RXP AD3
TP2 HDA_DOCK_EN# / GPIO33 +3V SATA4TXN AD1
PCH JTAG Debug (CLG) TP13
PCH_GPIO13 N32
HDA_DOCK_RST# / GPIO13 +3V_S5 SATA4TXP
Y3
+3V_S5 SATA5RXN SATA_RXN5_C <21>
20111128 Remove net TP_INT#, becaue change to pin E12. Y1 SATA_RXP5_C <21> SATA ODD
SATA5RXP AB3
C SATA5TXN SATA_TXN5 <21> C
<3,22> XDP_TCLK_VT XDP_TCLK_VT J3 AB1 SATA_TXP5 <21>
JTAG_TCK SATA5TXP
XDP_TMS_VT H7 Y11
JTAG
<3,22> XDP_TMS_VT JTAG_TMS SATAICOMPO
R423 R421 R97 <3> PCH_XDP_TDO_VT PCH_XDP_TDO_VT K5 Y10 SATA_COMP R128 37.4/F_4 +1.05V_VTT
210/F_4 210/F_4 210/F_4 JTAG_TDI SATAICOMPI
PCH_XDP_TDO H1
TP14 JTAG_TDO
XDP_TMS_VT AB12
PCH_XDP_TDO_VT SATA3RCOMPO
PCH_XDP_TDO AB13 SATA3_COMP R131 49.9/F_4
XDP_TCLK_VT SATA3COMPI
PCH_SPI_CLK T3 AH1 SATA3_RBIAS R464 750/F_4

SPI_CLK SATA3RBIAS
R428 R422 R419 R96 PCH_SPI_CS0# Y14
51_4 100/F_4 100/F_4 100/F_4 20111110 change power plant to +3V_PCH_ME SPI_CS0# 20111108 PU 10k to +3V, becaue no sata LED.
R524 *47K_4 PCH_SPI_CS1# T1
SPI
+3V_PCH_ME SPI_CS1# P3 SATA_ACT# R443 10K_4 +3V SATA0GP/GPIO21
SATALED#
SATA4GP/GPIO16
PCH_SPI_SI V4 +3V V14 PCH_ODD_EN SATA5GP/GPIO49
SPI_MOSI SATA0GP / GPIO21 PCH_ODD_EN <21>
If these pins are unused use 8.2k
PCH_SPI_SO U3 +3V P1 BBS_BIT0 R459 10K_4
SPI_MISO SATA1GP / GPIO19 +3V to 10k pull-up to +Vcc3_3 or 8.2k
20111127 add R444 PU 10K to +3V for PCH_ODD_EN not use. to 10k pull-down to ground
PCH Dual SPI (Default for WIN8) PCH Strap Table Panther Point_R1P0
(CLG) W25Q32BVSSIG / AKE391P0N00----->4MB

Pin Name Strap description Sampled Configuration
W25Q16BVSSIG / AKE38FP0N01----->2MB
0 = Default (weak pull-down 20K) R460 *1K_4 SPKR
R492 *SHORT_6
SPKR No reboot mode setting PWROK +3V
+3V_S5 +3V_PCH_ME 1 = Setting to No-Reboot mode
+3V_PCH_ME 0 = "top-block swap" mode R418 *1K_4
10/11 add GNT3# / GPIO55 Top-Block Swap Override PWROK PCI_GNT3# <9> Used as GPIO only. at chklist 1.2
B U27 1 = Default (weak pull-up 20K) B
PCH_SPI_CS0# 1 8
PCH_SPI_CLK R490 33_4 6 CE# VDD
PCH_SPI_SI R489 33_4 5 SCK R391 330K_4 PCH_INVRMEN
PCH_SPI_SO R522 33_4 2 SI 7 R491 3.3K_4
INTVRMEN Integrated 1.05V VRM enable ALWAYS Should be always pull-up +3V_RTC
SO HOLD#
3 4
C520 WP# VSS C114 GNT1# / GPIO51 Boot BIOS Selection 1 [bit-1] PWROK
*22p/50V_4 ROM-2M_ME 0.1u/10V_4 GNT1# GNT0# Boot Location
R412 *1K_4
Default weak pull-up on GNT0/1#
1 1 SPI * BBS_BIT1 <9> [Need external pull-down for LPC BIOS]
+3V_PCH_ME R520 3.3K_4 GPIO19 Boot BIOS Selection 0 [bit-0] PWROK 0 0 LPC R448 *1K_4 BBS_BIT0
10/11 add +3V_PCH_ME

U28 0 = effect (default)(weak pull-down 20K)
PCH_SPI_CS1# 1 8 HDA_SDO Flash Descriptor Security RSMRST R377 *SHORT_4 ACZ_SDOUT_R
PCH_SPI_CLK R486 33_4 6 CE# VDD <24> ME_WR# ME_WR default EC setting folating
PCH_SPI_SI R494 33_4 5 SCK 1 = overridden
PCH_SPI_SO R525 33_4 2 SI 7 R488 3.3K_4 R482 2.2K_4
SO HOLD# 0 = Set to Vss (weak pull-down 20K) +1.8V for future CPU, Sandy Bridge NC
DF_TVS DMI/FDI Termination voltage PWROK R483 1K_4 DF_TVS needs to be pulled up to VccDFTERM power rail
DF_TVS <10>
C508 *22p/50V_4 3 4 1 = Set to Vcc through 2.2 kOhm 5% - R8361 change to 0 or not??
WP# VSS H_SNB_IVB# <3>
C580
20111129 contact to EC thougth series resistor. ROM-4M_EC 0.1u/10V_4 0 = Disable R439 *1K_4
<24> PCH_SPI_CLK_EC GPIO28 On-die PLL Voltage Regulator RSMRST# PLL_ODVR_EN <10>
<24> PCH_SPI_SI_EC 1 = Enable (weak pull-up 20K)
<24> PCH_SPI_SO_EC
R523 3.3K_4
0 = Support by 1.8V (weak pull-down) R350 1K_4 ACZ_SYNC_R
+3V_PCH_ME HDA_SYNC On-Die PLL VR Voltage Select RSMRST +3V_S5 Needs to be pulled High for Huron River platform.
R521 *0_4 PCH_SPI_CS0#
1 = Support by 1.5V chklist 1.2
Intel ME Crypto Transport Layer 0 = Disable (Default)

GPIO15 Security (TLS) cipher suite RSMRST R413 1K_4
1 = Enable +3V_S5 PCH_GPIO15 <10>
internal PD
A <24> SPI_CS0#_UR_ME R526 0_4 PCH_SPI_CS1# A
DEEP S4/S5 well High = Enable (Default) +3V_RTC R60 330K_4 R59 *330K_4
DSWVREN On Die DSW VR Enable DSW
Low = Disable DSWVREN <7>
+3V_PCH_ME R479 *1K_4

NV_ALE Intel Anti-Theft HDD protection PWROK 0 = Disable (Internal pull-down 20kohm) +1.8V NV_ALE <9>
20111103 add pull up 10k to PSI CS#.
Only for Interposer
SPI_CS0#_UR_ME R620 47K_4

PROJECT :Z09
3A
Panther Point 2/6
5 4 3 2 1
5 4 3 2 1
CPT/PPT (PCI,USB,NVRAM)
CPT/PPT (PCI-E,SMBUS,CLK)
PCIE port 1 for commeral model S3 can't weak up.
U26B
20111122 add for Touch pad interrupt pin from GPIO13 to GPIO11.
09
BG34
U26E BJ34 PERN1 E12 SMBALERT#
PERP1 +3V_S5 SMBALERT# / GPIO11 SMBALERT# <19>
AY7 AV32
RSVD1 AV7 AU32 PETN1 H14 SMB_PCH_CLK
RSVD2 PETP1 SMBCLK SMB_PCH_CLK <20>
BG26 AU3
BJ26 TP1 RSVD3 BG4 BE34 C9 SMB_PCH_DAT
TP2 RSVD4 <19> PCIE_RX2- PERN2 SMBDATA SMB_PCH_DAT <20>
BH25 <19> PCIE_RX2+ BF34
BJ16 TP3 AT10 C108 0.1U/10V_4 PCIE_TX2-_C BB32 PERP2
TP4 RSVD5 Cardreader <19> PCIE_TX2- PETN2
BG16 BC8 <19> PCIE_TX2+ C105 0.1U/10V_4 PCIE_TX2+_C AY32
SMBUS
AH38 TP5 RSVD6 PETP2 A12 DRAMRST_CNTRL_PCH
TP6 +3V_S5 SML0ALERT# / GPIO60 DRAMRST_CNTRL_PCH <4>
AH37 AU2 <17> PCIE_RX3- BG36
D
AK43 TP7 RSVD7 AT4 BJ36 PERN3 C8 SMB_ME0_CLK
D
TP8 RSVD8 <17> PCIE_RX3+ PERP3 SML0CLK
AK45 AT3 C103 0.1u/10V_4 PCIE_TXN3_C AV34
C18 TP9 RSVD9 AT1
LAN <17> PCIE_TX3-
C100 0.1u/10V_4 PCIE_TXP3_C AU34 PETN3 G12 SMB_ME0_DAT For LAN
TP10 RSVD10 <17> PCIE_TX3+ PETP3 SML0DATA
N30 AY3
H3 TP11 RSVD11 AT5 BF36
AH12 TP12 RSVD12 AV3 BE36 PERN4 20110907 del net SML1ALERT#
AM4 TP13 RSVD13 AV1 AY34 PERP4 C13 SML1ALERT#_R
TP14 RSVD14 PETN4 +3V_S5 SML1ALERT# / PCHHOT# / GPIO74 TP24
AM5 BB1 BB34
Y13 TP15 RSVD15 BA3 PETP4 E14 SMB_ME1_CLK
+3V_S5
PCI-E*
K24 TP16 RSVD16 BB5 BG37 SML1CLK / GPIO58
L24 TP17 RSVD17 BB3 BH37 PERN5
+3V_S5 M16 SMB_ME1_DAT For EC
AB46 TP18 RSVD18 BB7 AY36 PERP5 SML1DATA / GPIO75
AB45 TP19 RSVD19 BE8 BB36 PETN5
RSVD
TP20 RSVD20 BD4 PETP5
RSVD21 BF6 BJ38
UM77 4~7 PCIE port disable
RSVD22 BG38 PERN6
Controller
B21 AV5 AU36 PERP6 M7 CL_CLK1
TP21 RSVD23 NV_ALE <8> PETN6 CL_CLK1 CL_CLK1 <20>
M20 AV10 AV36
AY16 TP22 RSVD24 PETP6
Link
BG46 TP23 AT8 BG40 T11 CL_DATA1
TP24 RSVD25 PERN7 CL_DATA1 CL_DATA1 <20>
TX AC cap place at connector side, AC cap to BJ40
AY5 AY40 PERP7
connector < 400mils RSVD26 PETN7
BA2 BB40 P10 CL_RST1#
BE28 USB3.0
USB30_RX1N
RSVD27 PETP7 CL_RST1# CL_RST1# <20>
<23> USB30_RX1- TP25
BC30 USB30_RX2N AT12 BE38
<23> USB30_RX2- BE32 TP26 RSVD28 BF3 <20> PCIE_RX8- BC38 PERN8
TP17 USB30_RX3N
TP27 RSVD29 <20> PCIE_RX8+ PERP8
TP30 BJ32 C106 0.1u/10V_4 PCIE_TXN8_C AW38
BC28 TP28 USB30_RX4N
port9 can be used on debug mode
Wireless <20> PCIE_TX8-
C109 0.1u/10V_4 PCIE_TXP8_C AY38 PETN8
<23> USB30_RX1+ TP29 USB30_RX1P <20> PCIE_TX8+ PETP8
BE30 USB30_RX2P
<23> USB30_RX2+ TP30
TP20 BF32 M10 PCIE_CLKREQ_PEG#_R R103 EV@0_4
TP31 USB30_RX3P PEG_A_CLKRQ# / GPIO47 PEG_CLKREQ# <25>
TP29 BG32 C24 <19> CLK_PCIE_MMC# Y40
TP32 USB30_RX4P USBP0N USBP0- <23> CLKOUT_PCIE0N
AV26 USB30_TX1N A24 MB USB left side Cardreader <19> CLK_PCIE_MMC Y39 +3V_S5
<23> USB30_TX1- BB26 TP33 USBP0P C25 USBP0+ <23> CLKOUT_PCIE0P AB37
<23> USB30_TX2- TP34 USB30_TX2N USBP1N USBP1- <23> +3V_S5 CLKOUT_PEG_A_N CLK_PCIE_VGAN <25>
CLOCKS
TP18 AU28 B25 MB usb left side XHCI for USBP0-3 PCIE_CLKREQ0# J2 AB38
TP35 USB30_TX3N USBP1P USBP1+ <23> <19> PCIE_CLKREQ0# PCIECLKRQ0# / GPIO73 CLKOUT_PEG_A_P CLK_PCIE_VGAP <25>
TP21 AY30 C26
TP36 USB30_TX4N USBP2N TP7
AU26 A26
<23> USB30_TX1+ TP37 USB30_TX1P USBP2P TP1
AY26 K28 AB49 AV22
<23> USB30_TX2+ TP38 USB30_TX2P USBP3N CLKOUT_PCIE1N CLKOUT_DMI_N CLK_CPU_BCLKN <3>
TP16 AV28 H28 AB47 AU22
TP39 USB30_TX3P USBP3P TP61 CLKOUT_PCIE1P CLKOUT_DMI_P CLK_CPU_BCLKP <3>
TP19 AW30 E28 EHCI1 +3V
TP40 USB30_TX4P USBP4N
C D28 PCIE_CLKREQ1# M1 C
USBP4P C28 PCIECLKRQ1# / GPIO18 AM12
USBP5N CLKOUT_DP_N CLK_DPLL_SSCLKN <3>
A28 AM13
USBP5P CLKOUT_DP_P CLK_DPLL_SSCLKP <3>
C29 AA48
USBP6N B29 USB port6/7 may not be available on all PCH sku AA47 CLKOUT_PCIE2N
PCI_PIRQA# K40 USBP6P N28 (HM55 support 12port only) CLKOUT_PCIE2P BF18 CLK_BUF_PCIE_3GPLLN
PIRQA# USBP7N +3V CLKIN_DMI_N
PCI_PIRQB# K38 M28 PCIE_CLKREQ2# V10 BE18 CLK_BUF_PCIE_3GPLLP
PCI
PCI_PIRQC# H38 PIRQB# USBP7P L30 PCIECLKRQ2# / GPIO20 CLKIN_DMI_P

G38 PIRQC# USBP8N K30 USBP8- <15>
PCI_PIRQD# Camera
PIRQD# USBP8P USBP8+ <15>
G30 Y37 BJ30 CLK_BUF_BCLKN
USBP9N USBP9- <23> CLKOUT_PCIE3N CLKIN_GND1_N
DGPU_EDIDSEL# C46 +3V E30 MB USB right side Y36 BG30 CLK_BUF_BCLKP
USB
C44 REQ1# / GPIO50 USBP9P C30 USBP9+ <23> CLKOUT_PCIE3P CLKIN_GND1_P

DGPU_SELECT# +3V +3V_S5
REQ2# / GPIO52 USBP10N USBP10- <20>
REQ#3 E40 +3V A30 BT+WL PCIE_CLKREQ3# A8
REQ3# / GPIO54 USBP10P L32 USBP10+ <20> PCIECLKRQ3# / GPIO25 G24 CLK_BUF_DREFCLKN
EHCI2 XTAL25_IN
USBP11N TP4 CLKIN_DOT_96N
<8> BBS_BIT1 D47 +3V K32 TP6 E24 CLK_BUF_DREFCLKP
3
4
BOARD_ID2 E42 GNT1# / GPIO51 USBP11P G32 Y43 CLKIN_DOT_96P
<10> BOARD_ID2 GNT2# / GPIO53 +3V USBP12N CLKOUT_PCIE4N
F46 +3V E32 UM77 USB port 6,7,12,13 disable. Y45 Y2
<8> PCI_GNT3# GNT3# / GPIO55 USBP12P CLKOUT_PCIE4P
C32 +3V_S5 AK7 CLK_BUF_DREFSSCLKN 25MHz_XTAL
USBP13N A32 PCIE_CLKREQ4# L12 CLKIN_SATA_N AK5 CLK_BUF_DREFSSCLKP
MPC_PWR_CTRL# G42 USBP13P PCIECLKRQ4# / GPIO26 CLKIN_SATA_P
+3V
1
2
DGPU_PWR_EN G40 PIRQE# / GPIO2 20110908 WLAN support S3 wake up function. XTAL25_OUT
<39> DGPU_PWR_EN
C42 PIRQF# / GPIO3 +3V C33 V45 K45
<25> DGPU_HOLD_RST# DGPU_HOLD_RST# +3V USB_BIAS R86 22.6/F_4 CLK_PCH_14M
PIRQG# / GPIO4 USBRBIAS# <20> CLK_PCIE_WLAN# CLKOUT_PCIE5N REFCLK14IN
EXTTS_SNI_DRV1_PCH D44 +3V Wireless V46
PIRQH# / GPIO5 <20> CLK_PCIE_WLAN CLKOUT_PCIE5P
+3V_S5
B33 <20> PCIE_CLKREQ5# PCIE_CLKREQ5# L14 H45 CLK_PCI_FB C87 10p/50V_4
TP12 PCI_PME# K10 USBRBIAS PCIECLKRQ5# / GPIO44 CLKIN_PCILOOPBACK
PME# R133
PCI_PLTRST# C6 +3V_S5 A14 USB_OC0# AB42 V47 XTAL25_IN
<3,24> PCI_PLTRST# PLTRST# OC0# / GPIO59 USB_OC0# <23> <17> CLK_PCIE_LOM# CLKOUT_PEG_B_N XTAL25_IN
+3V_S5 K20 USB_OC1# AB40 V49 XTAL25_OUT
20111108 Add PCLK_TPM for TPM. +3V_S5
OC1# / GPIO40 B17 USB_OC2#
LAN <17> CLK_PCIE_LOM CLKOUT_PEG_B_P
+3V_S5
XTAL25_OUT
H49 OC2# / GPIO41 C16 RAM_ID0 CLK_PCIE_LAN_REQ# E6 1M_4
H43 CLKOUT_PCI0 +3V_S5 OC3# / GPIO42 L16
<17> CLK_PCIE_LAN_REQ# PEG_B_CLKRQ# / GPIO56
<19> PCLK_TPM R104 22_4 PCLK_TPM_R +3V_S5 USB_OC4# C74 10p/50V_4
CLK_PCI_FB R431 22_4 CLK_PCI_FB_C J48 CLKOUT_PCI1 OC4# / GPIO43 A16 RAM_ID1 Y47 XCLK_RCOMP R132 90.9/F_4
CLKOUT_PCI2 +3V_S5 OC5# / GPIO9 XCLK_RCOMP +1.05V_VTT
R115 22_4 CLK_LPC_DEBUG_C K42 +3V_S5 D14 RAM_ID2 V40
<20> CLK_LPC_DEBUG CLKOUT_PCI3 OC6# / GPIO10 CLKOUT_PCIE6N
R99 22_4 CLK_PCI_775_C H40 +3V_S5 C14 RAM_ID3 TP34 V42
<24> CLK_PCI_EC CLKOUT_PCI4 OC7# / GPIO14 CLKOUT_PCIE6P
+3V_S5 20120201 Change CAP from 27P to 10P.
CLK_PCIE_REQ6# T13
Panther Point_R1P0 PCIECLKRQ6# / GPIO45
V38 +3V K43 CLK_FLEX0 R85 *SHORT_4 SKU_ID1
FLEX CLOCKS
TP42 V37 CLKOUT_PCIE7N CLKOUTFLEX0 / GPIO64
B CLKOUT_PCIE7P B
+3V_S5 +3V F47 CLK_FLEX1
CLKOUTFLEX1 / GPIO65 TP59
CLK_PCIE_REQ7# K12
PCIECLKRQ7# / GPIO46 H47
+3V CLKOUTFLEX2 / GPIO66 BOARD_ID4 <10,19>
AK14
<3> CLK_PCIE_XDPN CLKOUT_ITPXDP_N
<3> CLK_PCIE_XDPP AK13 +3V K49 R457 *SHORT_4 ODD_PRSNT# <21>
CLKOUT_ITPXDP_P CLKOUTFLEX3 / GPIO67
Panther Point_R1P0
PLTRST#(CLG) +3V 20111128 change power plant to +3V. PCI/USBOC# Pull-up(CLG)

+3V_S5 +3V CLK_REQ/Strap Pin(CLG) SMBus(EC) +3V_S5 SMBus(PCH)
+3V
PCI_PIRQA# R74 8.2K_4
USB_OC0# R55 10K_4 PCI_PIRQB# R75 8.2K_4 +3V_S5
C417 USB_OC1# R82 10K_4 PCI_PIRQC# R373 8.2K_4
0.1u/10V_4 USB_OC2# R392 10K_4 PCI_PIRQD# R40 8.2K_4 R79 10K_4 PCIE_CLKREQ4# R338 R339 R316 R317
USB_OC4# R88 10K_4 R364 10K_4 PCIE_CLKREQ5# 2.2K_4 2.2K_4 4.7K_4 4.7K_4
5
R430 10K_4 PCIE_CLKREQ0#

PCI_PLTRST# 2
4 +3V
R399 10K_4 PCIE_CLKREQ3#
5
Q19
S5 5
Q20
S0
PLTRST# R402 10K_4 CLK_PCIE_LAN_REQ#
PLTRST# <17,19,20,24,25>
1 R44 R365 10K_4 CLK_PCIE_REQ6#
10 1 DGPU_HOLD_RST# R83 10K_4 CLK_PCIE_REQ7# 3 4 SMB_ME1_CLK SMB_PCH_DAT 3 4
<24> 2ND_MBCLK
U23 MPC Switch Control MPC_PWR_CTRL# 9 2 DGPU_EDIDSEL# CLK_SDATA <13,14,19>
3
TC7SH08FU R351 EXTTS_SNI_DRV1_PCH 8 3 dGPU_SELECT# +3V

100K_4 Low = MPC ON REQ#3 7 4 2 2
MPC_PWR_CTRL# High = MPC OFF (Default) 6 5 R424 10K_4 PCIE_CLKREQ1#
R124 10K_4 PCIE_CLKREQ2# <24> 2ND_MBDATA 6 1 SMB_ME1_DAT SMB_PCH_CLK 6 1
10KX8 CLK_SCLK <13,14,19>
MPC_PWR_CTRL# R49 *1K_4
R366 *0_4 +3V_S5
2N7002DW 2N7002DW
R102 10K_4 PCIE_CLKREQ_PEG#_R
dGPU_PW_CTRL# SKU_ID1 SKU_ID0 VGA H/W Setup 20111021 remove pull/down resistor
DDRIII Memory down strap Optimize SKU (GPIO68) (GPIO64) (GPIO16) Signal Menu 20111117 change footprint to dual type.
RAM RAM_IDn CTL : dGPU_VRON
A +3V_S5 A
+3V UMA Only 1 0 0 UMA Hidden UMA boot CLK_BUF_BCLKN R504 10K_4
R394 *RAMID@5K/F_4 RAM_ID0 R379 RAMID@10K_4 CLK_BUF_BCLKP R503 10K_4
R393 RAMID@15K/F_4 RAM_ID1 R378 *RAMID@10K_4 Hynix 0x000 R93 EV@10K_4 SKU_ID1
R70 RAMID@15K/F_4 RAM_ID2 R71 *RAMID@10K_4 R100 IV@10K_4 dGPU Only 0 or 1 0 1 GPU Hidden GPU boot
R395 RAMID@15K/F_4 RAM_ID3 R380 *RAMID@10K_4 CLK_BUF_PCIE_3GPLLN R164 10K_4 +3V_S5
Elpida 0x001 Switchable CLK_BUF_PCIE_3GPLLP R163 10K_4
(Mux) 0 1 0 UMA+GPU dGPU/SG UMA boot CLK_BUF_DREFCLKN R89 10K_4 if net DRAMRST_CNTRL_PCH change to PCH control need stuff R358.
+3V CLK_BUF_DREFCLKP R90 10K_4
Optimize CLK_BUF_DREFSSCLKN R480 10K_4
R108 EV@10K_4 (Muxless) 0 1 1 UMA UMA/SG UMA boot CLK_BUF_DREFSSCLKP R478 10K_4
SKU_ID0 <10>
R114 IV@10K_4 CLK_PCH_14M R111 10K_4
+3V dGPU_PW_CTRL#
R72 10K_4 SMBALERT# Quanta Computer Inc.
CLOCK TERMINATION for FCIM R343 2.2K_4 SMB_PCH_CLK
0 = GPU power is control by PCH GPIO (Discrete, SG or Optimize) R340 2.2K_4 SMB_PCH_DAT
1 = GPU power is control by H/W (pure Discrete SKU) R361 2.2K_4 SMB_ME0_CLK
PROJECT : Z09
R386 *100K_4 DGPU_PWR_EN R370 10K_4 R360 2.2K_4 SMB_ME0_DAT Size Document Number Rev
R357 10K_4 SML1ALERT#_R 3A
Panther Point 3/6
5 4 3 2 1
5 4 3 2 1
S_GPIO R112 100_4

CPT/PPT (GPIO,VSS_NCTF,RSVD)
T7
U26F
BMBUSY# / GPIO0 +3V +3V TACH4 / GPIO68

C40 DGPU_PW_CTRL#
GPIO Pull-up/Pull-down(CLG)
10
SIO_EXT_SMI# A42 +3V +3V B41 LCD_SELECT
<24> SIO_EXT_SMI# TACH1 / GPIO1 TACH5 / GPIO69
BOARD_ID1 H36 +3V +3V C41 BOARD_ID3 +3V_S5
TACH2 / GPIO6 TACH6 / GPIO70
D SIO_EXT_SCI# E38 A40 R407 1.5K/F_4 PCH_GPIO24 R73 *10K_4 D
<24> SIO_EXT_SCI# TACH3 / GPIO7 +3V +3V TACH7 / GPIO71 +3V
ICC_EN# C10 +3V_S5 PLL_ODVR_EN R440 10K_4
TP25 GPIO8
SMIB C4 +3V
LAN_PHY_PWR_CTRL / GPIO12 +3V_S5
G2 P4 SIO_A20GATE SIO_EXT_SMI# R39 10K_4
<8> PCH_GPIO15 GPIO15 +3V_S5 A20GATE SIO_A20GATE <24>
SIO_EXT_SCI# R50 10K_4
AU16 EC_PECI_R R162 *0_4
PECI EC_PECI <3,24>
U2 STP_PCI# R420 *10K_4
<9> SKU_ID0 SATA4GP / GPIO16 +3V P5 SIO_RCIN# SIO_A20GATE R105 10K_4
RCIN# SIO_RCIN# <24>
SIO_RCIN# R98 10K_4
GPIO
TP75
DGPU_PWROK D40 AY11 CRIT_TEMP_REP# R458 10K_4
TACH0 / GPIO17 +3V
CPU/MISC
<25> DGPU_PWROK PROCPWRGD H_PWRGOOD <3>
G_SENSOR_ID T5 AY10 PCH_THRMTRIP# R156 390_4 +3VPCU
SCLOCK / GPIO22 +3V THRMTRIP# PM_THRMTRIP# <3>
20120201 reserve GPIO27 PU +3VPCU
PCH_GPIO24 E8 T14 R616 10K_4
GPIO24 / MEM_LED+3V_S5 INIT3_3V# WK_GPIO27 R101 *10K_4
WK_GPIO27 E16 DSW AY1
<24> WK_GPIO27 GPIO27 DF_TVS DF_TVS <8>
20111017 un-stuff R5126 for DSW
PLL_ODVR_EN P8 +3V_S5 DGPU_PWROK R87 *10K_4
<8> PLL_ODVR_EN GPIO28 AH8
STP_PCI# K1 TS_VSS1
STP_PCI# / GPIO34 +3V
AK11 GPIO27 : If not used then use 8.2-k to 10-k pull-down to GND.
DGPU_VRON K4 TS_VSS2
<38,39> DGPU_VRON GPIO35 +3V AH10
C TS_VSS3 C
DMI_OVRVLTG V8
SATA2GP / GPIO36 +3V AK10
TS_VSS4
Low = Tx, Rx terminated to
FDI_OVRVLTG M5 DMI TERMINATION
SATA3GP / GPIO37 +3V same voltage (DC Coupling Mode)
VOLTAGE OVERRIDE (DEFAULT)
MFG_MODE N2 P37 USB3.0 IC CTL
SLOAD / GPIO38 +3V NC_1
BOARD_ID0 M3 +3V
SDATAOUT0 / GPIO39 +3V
LOW = USB3.0 IC
20110907 del R5217 and net SML1ALERT# TEST_SET_UP V13 +3V BG2
SDATAOUT1 / GPIO48 VSS_NCTF_15
CRIT_TEMP_REP# V3 +3V BG48
SATA5GP / GPIO49 VSS_NCTF_16 R148 *10K_4 DMI_OVRVLTG R146 *200K/F_4
SV_DET D6 BH3
TP23 GPIO57 +3V_S5 VSS_NCTF_17 +3V_S5
BH47
VSS_NCTF_18 SMIB R401 10K_4
A4 BJ4
VSS_NCTF_1 VSS_NCTF_19
A44 BJ44 high VDDR=+1.35V_SUS for DDR3L
VSS_NCTF_2 VSS_NCTF_20 +3V_S5 Low VDDR =+1.5V_SUS(default)
A45 BJ45
VSS_NCTF_3 VSS_NCTF_21 R362 *10K_4 SV_DET R400 100K_4
NCTF
A46 BJ46
VSS_NCTF_4 VSS_NCTF_22 assign to VID for VDDR control
A5 BJ5
B SV_SET_UP B
A6 BJ6 +3V
B3 C2 High = Strong (Default) R106 10K_4 BOARD_ID0 R107 *10K_4
VSS_NCTF_7 VSS_NCTF_25 R389 10K_4 BOARD_ID1 R374 *10K_4
B47 C48 R385 10K_4 BOARD_ID2 R369 *10K_4
VSS_NCTF_8 VSS_NCTF_26 +3V R384 *10K_4 BOARD_ID3 R368 10K_4
BD1 D1 R425 *10K_4 BOARD_ID4 R427 10K_4
VSS_NCTF_9 VSS_NCTF_27 TEST_SET_UP R147 10K_4 <9> BOARD_ID2
BD49 D49 R149 *1K_4
VSS_NCTF_10 VSS_NCTF_28 <9,19> BOARD_ID4
BE1 E1
Board_ID4 Hight=Symatic, LOW=ELAN.
BE49 E49
BF1 F1
SGPIO
BF49 F49
VSS_NCTF_14 VSS_NCTF_32 GPU power is control by
SATA2GP : strap for reserved at chklist 1.2 +3V high H/W (pure Discrete SKU)
Panther Point_R1P0
SATA3GP : strap for reserved at chklist 1.2 S_GPIO R113 1K_4 GPU power is control by PCH
NOTE: The internal pull-down is disabled after PLTRST# deasserts. R116 *1K_4 +3V low GPIO (Discrete, SG or Optimize)
NOTE: This signal should not be pulled high when strap is sampled.
R372 IV@1K_4 DGPU_PW_CTRL# R388 EV@100K_4
A A
2011/09/01 add select resistor +3V +3V +3V
LCD_SELECT R371 *LVDS@1.5K/F_4 R436 100K_4 FDI_OVRVLTG R437 *1K_4 G_SENSOR_ID R117 10K_4
R119 *1K_4
R387 EDP@1K_4
MFG-TEST Quanta Computer Inc.
+3V
LVDS = Pull HIGH FDI TERMINATION LOW - Tx, Rx terminated High = Disable (Default) MFG_MODE R445 10K_4
PROJECT : Z09
VOLTAGE OVERRIDE to same voltage G_SENSOR_ID R444 *1K_4 Size Document Number Rev
eDP = Pull LOW Low = Enable Panther Point 4/6 3A

5 4 3 2 1
5 4 3 2 1
PCH5(CLG)
20111021 remove vcc core power sense net

CPT/PPT (POWER)
+VCCA_DAC_1_2 +3V
11
VccADAC =1mA(8mils)
U26G POWER L2 180ohm/5A CPT/PPT (POWER)
+1.05V_VTT R136 *0_8
+1.05V_VTT +1.05V_VTT
VccCORE =1.3 A(60mils) C61 C55 C43
20111117 remove 0ohm resistor.

AA23
AC23 VCCCORE[1] VCCADAC
U48 C47
10u/6.3V_6
0.01u/25V_4 0.1u/10V_4 10u/6.3V_6
20120104 change power plant from +3V_S5 to +3VPCU.
U26J POWER
VCCCORE[2]
CRT
AD21 +VCCACLK AD49 N26 20111117 remove 0ohm resistor.
C82 C81 C92 C88 AD23 VCCCORE[3] U47 R449 *SHORT_4 VCCACLK VCCIO[29] C59
VCCCORE[4] VSSADAC +3VPCU
VCC CORE
1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 4.7u/6.3V_6 AF21 VCCDSW3_3= 3mA P26 1u/6.3V_4 VCCSUS3_3 = 119mA(15mils)
AF23 VCCCORE[5] +VCCPDSW T16 VCCIO[30]
AG21 VCCCORE[6] VCCDSW3_3 P28 +3VCC_S5
D
R5285 near PCH ball for VCCP GND sense AG23 VCCCORE[7] VCCIO[31] D
AG24 VCCCORE[8] AK36 C52 PCH_VCCDSW V12 T27 R56 *SHORT_6 20111018 change for DSW
AG26 VCCCORE[9] VCCALVDS 0.1u/10V_4 DCPSUSBYP VCCIO[32]
+1.05V_VTT AG27 VCCCORE[10] AK37 T29
AG29 VCCCORE[11] VSSALVDS C65 +3V_SUS_CLKF33 T38 VCCIO[33] C62
VCCCORE[12] When Dis sku and eDP , LVDS power can short to GND +1.05V_VTT +VCCAPLL_CPY_PCH VCC3_3[5]
AJ23 *0.1u/10V_4 0.1u/10V_4
LVDS
20111117 remove 0ohm resistor. AJ26 VCCCORE[13] AM37 T23 +3V_VCCPUSB
+1.05V_VTT +1.05V_VCCAPLL_EXP AJ27 VCCCORE[14] VCCTX_LVDS[1] 20111101 remove vccalcd and vcctx_lds power, when LVDS disable. L7 *10uH/100mA_8 BH23 VCCSUS3_3[7]
AJ29 VCCCORE[15] AM38 VCCAPLLDMI2 T24
L6 *1uH/25mA_6 AJ31 VCCCORE[16] VCCTX_LVDS[2] R141 *SHORT_6 +VCCDPLL_CPY AL29 VCCSUS3_3[8] R57 *SHORT_6
VCCCORE[17] +1.05V_VTT VCCIO[14]
AP36 C118 V23
USB
VCCTX_LVDS[3] *10u/6.3V_6 VCCSUS3_3[9]
C119 AP37 +VCCSUS1 AL24 V24 C50
*10u/6.3V_6 AN19 VCCTX_LVDS[4] DCPSUS[3] VCCSUS3_3[10] 0.1u/10V_4
VCCIO[28] P24 +3V_VCCAUBG
C97 VCCSUS3_3[6]
VCCME(+1.05V) = ??A(??mils)
BJ22 +3V_VCC_GIO +3V *1u/6.3V_4 AA19
+1.05V_VTT VCCAPLLEXP VCCASW[1] T26 +VCCAUPLL R123 *SHORT_6
+1.05V_VTT VCCIO[34] +1.05V_VTT
VccIO =2.925 A(140mils) V33 AA21 VCC5REFSUS=1mA
HVCMOS
AN16 VCC3_3[6] R125 *SHORT_6 VCCASW[2]
VCCIO[15] +1.05V_VTT
VccASW =1.01 A(60mils)
AA24 M26 +5V_PCH_VCC5REFSUS R110 10/F_4
VCCASW[3] V5REF_SUS +5VCC_S5
20111117 remove 0ohm resistor. AN17 C66 VCCDMI = 42mA(10mils)
C99 C98 C91 VCCIO[16] V34 0.1u/10V_4 +1.1V_VCC_DMI AA26 D11 RB500V-40
Clock and Miscellaneous

VCC3_3[7] VCCASW[4] +3VCC_S5
1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 C84 C79 C80 AN23 +VCCA_USBSUS C44
AN21 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 AA27 DCPSUS[4] 0.1u/10V_4 20111018 change for DSW
VCCIO[17] R169 *SHORT_4 VCCASW[5] AN24 +3V_VCCPSUS
AN26 AA29 VCCSUS3_3[1] C96
VCCIO[18] C104 VCCASW[6] *1u/6.3V_4
AN27 AT16 +VCCAFDI_VRM +VCCAFDI_VRM 1u/6.3V_4 20120216 remove R168 for power plant chnge to +1.05V_VTT. AA31 V5REF= 1mA
VCCIO[19] VCCVRM[3] VCCASW[7]
+1.1V VCC_DMI witdth >= 20mils.
C94 C101 AP21 AC26 P34 +5V_PCH_VCC5REF R353 10/F_4
VCCIO[20] VCCASW[8] V5REF +5V
1u/6.3V_4 10u/6.3V_6 C69 C70
AP23 AT20 VCCCLKDMI = 20mA(8mils) 10u/6.3V_6 10u/6.3V_6 AC27 D10 RB500V-40 +3V
VCCIO[21] VCCDMI[1] VCCASW[9] N20 C49
DMI
PCI/GPIO/LPC
AP24 +1.1V_VCC_DMI_CCI +VCC_DMI_CCI +1.05V_VTT AC29 VCCSUS3_3[2] 1u/6.3V_4
VCCIO
VCCIO[22] VCCASW[10] N22 20111018 change for DSW
AP26 AB36 L4 *10uH/100mA_8 AC31 VCCSUS3_3[3]
VCCIO[23] VCCCLKDMI R144 *1/F_4 VCCASW[11] P20 +3V_VCCPSUS R58 *SHORT_6
VCCSUS3_3[4] +3VCC_S5
AT24 AD29
+3V +3V_VCC_EXP VCCIO[24] C78 C77 R139 *SHORT_4 VCCASW[12] P22
C
VCCSUS3_3[5]
VCCSUS3_3 = 119mA(15mils) C
1u/6.3V_4 *10u/6.3V_6 AD31 C48
R167 *SHORT_8 AN33 VCCASW[13] 1u/10V_4
VCCIO[25] W21 AA16
AN34 AG16 VCCASW[14] VCC3_3[1]
C121 VCCIO[26] VCCDFTERM[1] +VCCP_NAND +1.8V W23 W16 +3V_VCCPCORE R130 *SHORT_6
VCCPNAND = 190 mA(15mils) VCCASW[15] VCC3_3[8] +3V
0.1u/10V_4
BH29 AG17 W24 T34 VCCPCORE = 28mA(10mils)
+3V
DFT / SPI
VCC3_3[3] VCCDFTERM[2] R159 *SHORT_8 VCCASW[16] VCC3_3[4] C71
W26 0.1u/10V_4
AJ16 C93 VCCASW[17] C56
VCCDFTERM[3] 0.1u/10V_4 W29 0.1u/10V_4
+VCCAFDI_VRM AP16 VCCASW[18]
+VCCAFDI_VRM VCCVRM[2] +1.05V_VTT
AJ17 W31 AJ2 +3V
VCCDFTERM[4] VCCASW[19] VCC3_3[2]
+1.05V_VTT R506 *0_8 +1.05V_VCCAPLL_FDI BG6 R134 *SHORT_6 W33
VccAFDIPLL VCCASW[20] AF13 C95
+3V_VCCME_SPI VCCIO[5] 0.1u/10V_4
VCCSPI = 20mA(8mils)
+1.05V_VCCDPLL_FDI AP17 C86 C51 0.1u/10V_4 +VCCRTCEXT N16
VCCIO[27] DCPRTC
FDI
R158 *SHORT_8 V1 1u/6.3V_4 AH13 +1.05V_VTT

VCCSPI VCCIO[12]
AU20 +VCCAFDI_VRM Y49 AH14 20111117 remove 0ohm resistor.
+1.1V_VCC_DMI VCCDMI[2] +VCCAFDI_VRM VCCVRM[4] VCCIO[13]
C67 R138 *SHORT_6 C89
+1.1V VCC_DMI witdth >= 20mils. 1u/6.3V_4 1u/10V_4
Panther Point_R1P0 AF14
C85 +1.05V_VCCA_A_DPL BD47 VCCIO[6]
65mA(10mils) ??mA(??mils)
SATA
1u/6.3V_4 VCCADPLLA AK1 +V1.1LAN_VCCAPLL L24 *10uH/100mA_8
VCCAPLLSATA +1.05V_VTT
8mA(8mils) +1.05V_VCCA_B_DPL BF47 VCCVRM= 114mA(15mils)
VCCADPLLB C476
R143 *SHORT_6 AF11 +VCCAFDI_VRM *10u/6.3V_6
+VCCDIFFCLK AF17 VCCVRM[1]
VccDMI needs to be powered by the same 1.05 V voltage source as +VCCDIFFCLKN AF33 VCCIO[7]
the CPU VCCIO, and the trace needs to be at least 20 mils width with full VSS/ C90 AF34 VCCDIFFCLKN[1] AC16
VCC reference plane. VCCDIFFCLKN[2] VCCIO[2] +1.05V_VTT
20120105 change power plant to +3V for power saving. 1u/6.3V_4 VCCDIFFCLKN= 55mA(10mils) AG34
+1.05V_VTT VCCDIFFCLKN[3] AC17 20111117 remove 0ohm resistor.
+3V VCCIO[3] C76
VCCSSC= 95mA(10mils)
+3V_VCCME_SPI R127 *0_6 +V1.05V_SSCVCC AG33 AD17 1u/6.3V_4
+VCCAFDI_VRM R634 *0_6 +3V_S5 VCCSSC VCCIO[4]
R121 0_6 C63 C58 0.1u/10V_4 +VCCSST V16 +1.05V_VTT VCCME = 1.01A(60mils)
B
*1u/6.3V_4 DCPSST B
VCCVRM: 1.8V (Destop) 02/20 del for Pre-ES1
+1.5V R170 *SHORT_6 1.5V (Mobile)
Reserve +3V_S5 to VCCSPI for EC 795 co-layout +1.05V_VTT T17 T21
R171 *0_6 +V1.05M_VCCSUS V19 DCPSUS[1] VCCASW[22]
+1.05V_VTT
MISC
DCPSUS[2]
R173 *SHORT_41mA(8mils) +VTT_VCCPCPU V21
VCCASW[23]
CPU
BJ8
20120216 remove R172 for power plant chnge to +1.05V_VTT. C111 C120 C116 V_PROC_IO T19
4.7u/6.3V_6 0.1u/10V_4 0.1u/10V_4 VCCASW[21]
VCCRTC<1mA(8mils) +3V_RTC 20111107 remove R5144 PU 1.5VSUS.
RTC
A22 P32 +V3.3A_1.5A_HDA_IO R375 *SHORT_4 VCCSUSHDA= 10mA(8mils)
HDA
VCCRTC VCCSUSHDA +3V_S5
C40 C37 C39 Panther Point_R1P0 C53 C429

1u/6.3V_4 0.1u/10V_4 0.1u/10V_4 *1u/6.3V_4 0.1u/10V_4
+5VCC_S5 +3V_S5 +3VCC_S5
+5V_S5 1 3 1 3
+3V C411 R354 AO3413 Q23 C412 R355 AO3413 Q22

+1.05V_VTT L5 10uH/100mA_8 +1.05V_VCCA_A_DPL *0.33u/10V_6 100K_4 *0.33u/10V_6 100K_4
2
R118 *0_6
R126 1/F_4 L3 10uH/100mA_8 +3V_SUS_CLKF33 + C529 C115

220u/2.5V_3528 1u/6.3V_4 R344
*SHORT_6 R345
C68 C57 *SHORT_6
4.7u/6.3V_6 1u/10V_4
L26 10uH/100mA_8 +1.05V_VCCA_B_DPL
<7,24> SLP_SUS#
6
A + C512 C112 A
220u/2.5V_3528 1u/6.3V_4 Q24
2N7002DW
20111117 change mose footprint to dual type.
1
20111018 ADD DSW Cricuit Quanta Computer Inc.
20111030 modify cuirucit.
PROJECT : Z09
3A
Panther Point 5/6
5 4 3 2 1
5 4 3 2 1
PCH6(CLG)
12
U26I
AY4 H46
IBEX PEAK-M (GND) AY42
AY46
VSS[159]
VSS[160]
VSS[259]
VSS[260]
K18
K26
AY8 VSS[161] VSS[261] K39
D VSS[162] VSS[262] D
B11 K46
B15 VSS[163] VSS[263] K7
B19 VSS[164] VSS[264] L18
B23 VSS[165] VSS[265] L2
B27 VSS[166] VSS[266] L20
B31 VSS[167] VSS[267] L26
B35 VSS[168] VSS[268] L28
B39 VSS[169] VSS[269] L36
B7 VSS[170] VSS[270] L48
U26H F45 VSS[171] VSS[271] M12
H5 BB12 VSS[172] VSS[272] P16
VSS[0] BB16 VSS[173] VSS[273] M18
AA17 AK38 BB20 VSS[174] VSS[274] M22
AA2 VSS[1] VSS[80] AK4 BB22 VSS[175] VSS[275] M24
AB11 VSS[5] VSS[84] AL16 BB38 VSS[179] VSS[279] M38
AB4 VSS[8] VSS[87] AL2 BC14 VSS[182] VSS[282] M46
AB43 VSS[9] VSS[88] AL21 BC18 VSS[183] VSS[283] M8
AB5 VSS[10] VSS[89] AL23 BC2 VSS[184] VSS[284] N18
AB7 VSS[11] VSS[90] AL26 BC22 VSS[185] VSS[285] P30
AC19 VSS[12] VSS[91] AL27 BC26 VSS[186] VSS[286] N47
AC2 VSS[13] VSS[92] AL31 BC32 VSS[187] VSS[287] P11
AC24 VSS[15] VSS[94] AL34 BC36 VSS[189] VSS[289] T33
AC34 VSS[17] VSS[96] AM11 BC42 VSS[191] VSS[291] P43
AC48 VSS[18] VSS[97] AM14 BC48 VSS[192] VSS[292] P47
C AD10 VSS[19] VSS[98] AM36 BD46 VSS[193] VSS[293] P7 C
AD11 VSS[20] VSS[99] AM39 BD5 VSS[194] VSS[294] R2
AD12 VSS[21] VSS[100] AM43 BE22 VSS[195] VSS[295] R48
AD13 VSS[22] VSS[101] AM45 BE26 VSS[196] VSS[296] T12
AD19 VSS[23] VSS[102] AM46 BE40 VSS[197] VSS[297] T31
AD24 VSS[24] VSS[103] AM7 BF10 VSS[198] VSS[298] T37
AD26 VSS[25] VSS[104] AN2 BF12 VSS[199] VSS[299] T4
AD27 VSS[26] VSS[105] AN29 BF16 VSS[200] VSS[300] W34
AD36 VSS[29] VSS[108] AP12 BF24 VSS[203] VSS[303] T8
AD37 VSS[30] VSS[109] AP19 BF26 VSS[204] VSS[304] V11
AD39 VSS[32] VSS[111] AP30 BD3 VSS[206] VSS[306] V26
AD45 VSS[37] VSS[116] AP46 BG17 VSS[211] VSS[311] V39
AD46 VSS[38] VSS[117] AP8 BG21 VSS[212] VSS[312] V43
AD8 VSS[39] VSS[118] AR2 BG33 VSS[213] VSS[313] V7
AE2 VSS[40] VSS[119] AR48 BG44 VSS[214] VSS[314] W17
AE3 VSS[41] VSS[120] AT11 BG8 VSS[215] VSS[315] W19
AF10 VSS[42] VSS[121] AT13 BH11 VSS[216] VSS[316] W2
AF12 VSS[43] VSS[122] AT18 BH15 VSS[217] VSS[317] W27
AD14 VSS[44] VSS[123] AT22 BH17 VSS[218] VSS[318] W48
AD16 VSS[45] VSS[124] AT26 BH19 VSS[219] VSS[319] Y12
AF16 VSS[46] VSS[125] AT28 H10 VSS[220] VSS[320] Y38
AF19 VSS[47] VSS[126] AT30 BH27 VSS[221] VSS[321] Y4
B AF27 VSS[50] VSS[129] AT39 BH35 VSS[224] VSS[324] Y8 B
AF29 VSS[51] VSS[130] AT42 BH39 VSS[225] VSS[325] BG29
AF31 VSS[52] VSS[131] AT46 BH43 VSS[226] VSS[328] N24
AF38 VSS[53] VSS[132] AT7 BH7 VSS[227] VSS[329] AJ3
AF4 VSS[54] VSS[133] AU24 D3 VSS[228] VSS[330] AD47
AF42 VSS[55] VSS[134] AU30 D12 VSS[229] VSS[331] B43
AF46 VSS[56] VSS[135] AV16 D16 VSS[230] VSS[333] BE10
AF5 VSS[57] VSS[136] AV20 D18 VSS[231] VSS[334] BG41
AF7 VSS[58] VSS[137] AV24 D22 VSS[232] VSS[335] G14
AF8 VSS[59] VSS[138] AV30 D24 VSS[233] VSS[337] H16
AG19 VSS[60] VSS[139] AV38 D26 VSS[234] VSS[338] T36
AG2 VSS[61] VSS[140] AV4 D30 VSS[235] VSS[340] BG22
AG31 VSS[62] VSS[141] AV43 D32 VSS[236] VSS[342] BG24
AG48 VSS[63] VSS[142] AV8 D34 VSS[237] VSS[343] C22
AH11 VSS[64] VSS[143] AW14 D38 VSS[238] VSS[344] AP13
AH3 VSS[65] VSS[144] AW18 D42 VSS[239] VSS[345] M14
AH36 VSS[66] VSS[145] AW2 D8 VSS[240] VSS[346] AP3
AH39 VSS[67] VSS[146] AW22 E18 VSS[241] VSS[347] AP1
AH40 VSS[68] VSS[147] AW26 E26 VSS[242] VSS[348] BE16
AH42 VSS[69] VSS[148] AW28 G18 VSS[243] VSS[349] BC16
AH46 VSS[70] VSS[149] AW32 G20 VSS[244] VSS[350] BG28
AH7 VSS[71] VSS[150] AW34 G26 VSS[245] VSS[351] BJ28
AJ19 VSS[72] VSS[151] AW36 G28 VSS[246] VSS[352]
AJ21 VSS[73] VSS[152] AW40 G36 VSS[247]
AJ24 VSS[74] VSS[153] AW48 G48 VSS[248]
AJ33 VSS[75] VSS[154] AV11 H12 VSS[249]
AJ34 VSS[76] VSS[155] AY12 H18 VSS[250]
AK12 VSS[77] VSS[156] AY22 H22 VSS[251]
AK3 VSS[78] VSS[157] AY28 H24 VSS[252]
VSS[79] VSS[158] H26 VSS[253]
Panther Point_R1P0 H30 VSS[254]
H32 VSS[255]
A A
H34 VSS[256]
F3 VSS[257]
VSS[258]
Panther Point_R1P0

PROJECT : Z09
3A
Panther Point 6/6
5 4 3 2 1
5 4 3 2 1
DDR3 DIMM-A
JDIM1A M_A_DQ[63:0] <4>

+1.5VSUS
75
76
81
82
87
JDIM1B
VDD1
VDD2
VDD3
VDD4
VSS16
VSS17
VSS18
VSS19
44
48
49
54
55
13
<4> M_A_A[15:0] 98 5 88 VDD5 VSS20 60
M_A_A0 M_A_DQ5
M_A_A1 97 A0 DQ0 7 M_A_DQ1 93 VDD6 VSS21 61
M_A_A3 95 A2 DQ2 17 M_A_DQ7
2.48A 99 VDD8 VSS23 66
D A4 DQ4 VDD10 VSS25 D
M_A_A5 91 6 M_A_DQ0 105 72
PC2100 DDR3 SDRAM SO-DIMM

M_A_A11 84 A10/AP DQ10 35 M_A_DQ15 123 VDD16 VSS31 139
M_A_A13 119 A12/BC# DQ12 24 M_A_DQ9 VDD18 VSS33 145
M_A_A14 80 A13 DQ13 34 M_A_DQ11 199 VSS34 150
78 A14 DQ14 36 +3V VDDSPD VSS35 151
M_A_A15 M_A_DQ10
A15 DQ15 39 M_A_DQ20 77 VSS36 155
PC2100 DDR3 SDRAM SO-DIMM

109 DQ16 41 M_A_DQ21 122 NC1 VSS37 156
<4> M_A_BS#0 108 BA0 DQ17 51 125 NC2 VSS38 161
M_A_DQ22
<4> M_A_BS#1 79 BA1 DQ18 53 NCTEST VSS39 162
M_A_DQ19
<4> M_A_BS#2 114 BA2 DQ19 40 198 VSS40 167
M_A_DQ16 TP22
<4> M_A_CS#0 121 S0# DQ20 42 30 EVENT# VSS41 168
M_A_DQ17
<4> M_A_CS#1 101 S1# DQ21 50 <4,14> DDR3_DRAMRST# RESET# VSS42 172
M_A_DQ23
<4> M_A_CLK0 103 CK0 DQ22 52 VSS43 173
M_A_DQ18
<4> M_A_CLK0# 102 CK0# DQ23 57 1 VSS44 178
M_A_DQ29 R559 *M3@0_6 +SMDDR_VREF_DQ0
<4> M_A_CLK1 104 CK1 DQ24 59 <6> SMDDR_VREF_DQ0_M3 126 VREF_DQ VSS45 179
M_A_DQ28 +SMDDR_VREF_DIMM_A
<4> M_A_CLK1# 73 CK1# DQ25 67 VREF_CA VSS46 184
M_A_DQ30
<4> M_A_CKE0 74 CKE0 DQ26 69 VSS47 185
M_A_DQ25
<4> M_A_CKE1 115 CKE1 DQ27 56 2 VSS48 189
M_A_DQ27
<4> M_A_CAS# 110 CAS# DQ28 58 3 VSS1 VSS49 190
M_A_DQ24
<4> M_A_RAS# 113 RAS# DQ29 68 8 VSS2 VSS50 195
M_A_DQ26
(204P)
<4> M_A_WE# 197 WE# DQ30 70 9 VSS3 VSS51 196
C R238 10K_4 DIMM1_SA0 M_A_DQ31 C
R239 10K_4 DIMM1_SA1 201 SA0 DQ31 129 M_A_DQ33 13 VSS4 VSS52
CLK_SCLK 202 SA1 DQ32 131 M_A_DQ32 14 VSS5
<9,14,19> CLK_SCLK CLK_SDATA 200 SCL DQ33 141 M_A_DQ39 19 VSS6 +0.75V_DDR_VTT
<9,14,19> CLK_SDATA SDA DQ34 143 M_A_DQ38 20 VSS7
116 DQ35 130 M_A_DQ36 25 VSS8
<4> M_A_ODT0 120 ODT0 DQ36 132 26 VSS9 203
M_A_DQ37
<4> M_A_ODT1 ODT1 DQ37 140 31 VSS10 VTT1 204
M_A_DQ35
11 DQ38 142 M_A_DQ34 32 VSS11 VTT2
28 DM0 DQ39 147 M_A_DQ41 37 VSS12 205
46 DM1 DQ40 149 M_A_DQ45 38 VSS13 GND 206
(204P)
63 DM2 DQ41 157 M_A_DQ46 43 VSS14 GND

136 DM3 DQ42 159 M_A_DQ47 VSS15
153 DM4 DQ43 146 M_A_DQ40
170 DM5 DQ44 148 M_A_DQ44
DM6 DQ45 DDR3-DIMM1_H=5.2_Reverse
187 158 M_A_DQ42
DM7 DQ46 160 M_A_DQ43
<4> M_A_DQSP[7:0] 12 DQ47 163
M_A_DQSP0 M_A_DQ48
M_A_DQSP1 29 DQS0 DQ48 165 M_A_DQ52
DQS1 DQ49 +SMDDR_VREF
M_A_DQSP2 47 175 M_A_DQ50
M_A_DQSP4 137 DQS3 DQ51 164 M_A_DQ53 +1.5VSUS +1.5VSUS
<4> M_A_DQSN[7:0] 10 DQS7 DQ55 181
M_A_DQSN0 M_A_DQ57 R556 20110817 change to 1K/F_4 R601 20110817 change to 1K/F_4
M_A_DQSN1 27 DQS#0 DQ56 183 M_A_DQ60
DQS#1 DQ57 1K/F_4 1K/F_4
B M_A_DQSN2 45 191 M_A_DQ63 B
DQS#2 DQ58
M_A_DQSN3
M_A_DQSN4
62
135 DQS#3 DQ59
193
180
M_A_DQ58
M_A_DQ56
M1 solution R558 *0_6 +SMDDR_VREF_DQ0 R607 *0_6 +SMDDR_VREF_DIMM_A
M_A_DQSN7 186 DQS#6 DQ62 194 M_A_DQ59 R600 C723
DQS#7 DQ63
1K/F_4 470p/X7R_4
SMDDR_VREF_DQ0_M3 1 3
DDR3-DIMM1_H=5.2_Reverse
Q36 R546 C601
2
CRV add *AP2302GN
Place these Caps near So-Dimm0. 1K/F_4 470p/X7R_4
<4,14> DEEPS3_EC
+1.5VSUS
+SMDDR_VREF_DQ0 +SMDDR_VREF_DIMM_A
C267
C638 C717 C720 C719 C248 C243 C640 C643
+
10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 .1u/16V_4 .1u/16V_4 .1u/16V_4 .1u/16V_4 .1u/16V_4 *150u/6.3V_3528 C600 C602 C721 C722
SA1 SA0
.1u/16V_4 2.2u/6.3V_6 .1u/16V_4 2.2u/6.3V_6
CHA0 0 0
A A
CHA1 0 1
+3V +0.75V_DDR_VTT
CHB0 1 0
C731 C736 C323 C324 C312 C317 C318
CHB1 1 1
2.2u/6.3V_6 .1u/16V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 *10u/6.3V_6 PROJECT : Z09
3A
DDRIII SO-DIMM-0
5 4 3 2 1
1 2 3 4 5 6 7 8
<DDR> BYTE0_0-7 BYTE4_32-39 BYTE6_48-55

14
<4> M_B_DQSP[7:0]
<4> M_B_DQSN[7:0]
<4> M_B_DQ[63:0]
BYTE2_16-23
BYTE1_8-15 BYTE5_40-47 BYTE7_56-63
U30 U31 BYTE3_24-31 U32 U35
+SMDDR_VREF_DIMM M8 E3 M_B_DQ3 +SMDDR_VREF_DIMM M8 E3 M_B_DQ23 +SMDDR_VREF_DIMM M8 E3 M_B_DQ38 +SMDDR_VREF_DIMM M8 E3 M_B_DQ54

R587 *M3@0_6 SMDDR_VREF_DQ1 H1 VREFCA DQL0 F7 M_B_DQ2 SMDDR_VREF_DQ1 H1 VREFCA DQL0 F7 M_B_DQ18 SMDDR_VREF_DQ1 H1 VREFCA DQL0 F7 M_B_DQ35 SMDDR_VREF_DQ1 H1 VREFCA DQL0 F7 M_B_DQ50
<6> SMDDR_VREF_DQ1_M3 VREFDQ DQL1 VREFDQ DQL1 VREFDQ DQL1 VREFDQ DQL1
F2 M_B_DQ7 F2 M_B_DQ19 F2 M_B_DQ34 F2 M_B_DQ55
<4> M_B_A[15:0] DQL2 DQL2 DQL2 DQL2
M_B_A0 N3 F8 M_B_DQ6 M_B_A0 N3 F8 M_B_DQ22 M_B_A0 N3 F8 M_B_DQ39 M_B_A0 N3 F8 M_B_DQ51
M_B_A1 P7 A0 DQL3 H3 M_B_DQ5 M_B_A1 P7 A0 DQL3 H3 M_B_DQ21 M_B_A1 P7 A0 DQL3 H3 M_B_DQ33 M_B_A1 P7 A0 DQL3 H3 M_B_DQ49
M_B_A3 N2 A2 DQL5 G2 M_B_DQ1 M_B_A3 N2 A2 DQL5 G2 M_B_DQ20 M_B_A3 N2 A2 DQL5 G2 M_B_DQ32 M_B_A3 N2 A2 DQL5 G2 M_B_DQ53
M_B_A5 P2 A4 DQL7 M_B_A5 P2 A4 DQL7 M_B_A5 P2 A4 DQL7 M_B_A5 P2 A4 DQL7
A M_B_A6 R8 A5 M_B_A6 R8 A5 M_B_A6 R8 A5 M_B_A6 R8 A5 A
M_B_A7 R2 A6 D7 M_B_DQ12 M_B_A7 R2 A6 D7 M_B_DQ31 M_B_A7 R2 A6 D7 M_B_DQ42 M_B_A7 R2 A6 D7 M_B_DQ59
SO-DIMMB SPD Address is 0XA4
M_B_A8 T8 A7 DQU0 C3 M_B_DQ15 M_B_A8 T8 A7 DQU0 C3 M_B_DQ28 M_B_A8 T8 A7 DQU0 C3 M_B_DQ44 M_B_A8 T8 A7 DQU0 C3 M_B_DQ61
SO-DIMMB TS Address is 0X34 A8 DQU1 A8 DQU1 A8 DQU1 A8 DQU1
M_B_A9 R3 C8 M_B_DQ13 M_B_A9 R3 C8 M_B_DQ30 M_B_A9 R3 C8 M_B_DQ47 M_B_A9 R3 C8 M_B_DQ62
M_B_A10 L7 A9 DQU2 C2 M_B_DQ14 M_B_A10 L7 A9 DQU2 C2 M_B_DQ25 M_B_A10 L7 A9 DQU2 C2 M_B_DQ45 M_B_A10 L7 A9 DQU2 C2 M_B_DQ57
M_B_A11 R7 A10/AP DQU3 A7 M_B_DQ10 M_B_A11 R7 A10/AP DQU3 A7 M_B_DQ27 M_B_A11 R7 A10/AP DQU3 A7 M_B_DQ46 M_B_A11 R7 A10/AP DQU3 A7 M_B_DQ58
M_B_A12 N7 A11 DQU4 A2 M_B_DQ9 M_B_A12 N7 A11 DQU4 A2 M_B_DQ29 M_B_A12 N7 A11 DQU4 A2 M_B_DQ41 M_B_A12 N7 A11 DQU4 A2 M_B_DQ56
M_B_A13 T3 A12/BC DQU5 B8 M_B_DQ11 M_B_A13 T3 A12/BC DQU5 B8 M_B_DQ26 M_B_A13 T3 A12/BC DQU5 B8 M_B_DQ43 M_B_A13 T3 A12/BC DQU5 B8 M_B_DQ63
M_B_A14 T7 A13 DQU6 A3 M_B_DQ8 M_B_A14 T7 A13 DQU6 A3 M_B_DQ24 M_B_A14 T7 A13 DQU6 A3 M_B_DQ40 M_B_A14 T7 A13 DQU6 A3 M_B_DQ60
M_B_A15 M7 A14 DQU7 M_B_A15 M7 A14 DQU7 M_B_A15 M7 A14 DQU7 M_B_A15 M7 A14 DQU7
A15 +1.5VSUS A15 +1.5VSUS A15 +1.5VSUS A15 +1.5VSUS
M2 B2 M_B_BS#0 M2 B2 M_B_BS#0 M2 B2 M_B_BS#0 M2 B2

<4> M_B_BS#0 BA0 VDD#B2 BA0 VDD#B2 BA0 VDD#B2 BA0 VDD#B2
N8 D9 M_B_BS#1 N8 D9 M_B_BS#1 N8 D9 M_B_BS#1 N8 D9
<4> M_B_BS#1 BA1 VDD#D9 BA1 VDD#D9 BA1 VDD#D9 BA1 VDD#D9
M3 G7 M_B_BS#2 M3 G7 M_B_BS#2 M3 G7 M_B_BS#2 M3 G7
<4> M_B_BS#2 BA2 VDD#G7 BA2 VDD#G7 BA2 VDD#G7 BA2 VDD#G7
K2 K2 K2 K2
VDD#K2 K8 VDD#K2 K8 VDD#K2 K8 VDD#K2 K8
VDD#K8 N1 VDD#K8 N1 VDD#K8 N1 VDD#K8 N1
J7 VDD#N1 N9 M_B_CLK0 J7 VDD#N1 N9 M_B_CLK0 J7 VDD#N1 N9 M_B_CLK0 J7 VDD#N1 N9
<4> M_B_CLK0 CK VDD#N9 CK VDD#N9 CK VDD#N9 CK VDD#N9
K7 R1 M_B_CLK0# K7 R1 M_B_CLK0# K7 R1 M_B_CLK0# K7 R1
<4> M_B_CLK0# CK VDD#R1 CK VDD#R1 CK VDD#R1 CK VDD#R1
K9 R9 M_B_CKE0 K9 R9 M_B_CKE0 K9 R9 M_B_CKE0 K9 R9
<4> M_B_CKE0 CKE VDD#R9 +1.5VSUS CKE VDD#R9 +1.5VSUS CKE VDD#R9 +1.5VSUS CKE VDD#R9 +1.5VSUS
K1 A1 M_B_ODT0 K1 A1 M_B_ODT0 K1 A1 M_B_ODT0 K1 A1

<4> M_B_ODT0 ODT VDDQ#A1 ODT VDDQ#A1 ODT VDDQ#A1 ODT VDDQ#A1
L2 A8 M_B_CS#0 L2 A8 M_B_CS#0 L2 A8 M_B_CS#0 L2 A8
<4> M_B_CS#0 CS VDDQ#A8 CS VDDQ#A8 CS VDDQ#A8 CS VDDQ#A8
J3 C1 M_B_RAS# J3 C1 M_B_RAS# J3 C1 M_B_RAS# J3 C1
<4> M_B_RAS# RAS VDDQ#C1 RAS VDDQ#C1 RAS VDDQ#C1 RAS VDDQ#C1
K3 C9 M_B_CAS# K3 C9 M_B_CAS# K3 C9 M_B_CAS# K3 C9
<4> M_B_CAS# CAS VDDQ#C9 CAS VDDQ#C9 CAS VDDQ#C9 CAS VDDQ#C9
L3 D2 M_B_WE# L3 D2 M_B_WE# L3 D2 M_B_WE# L3 D2
<4> M_B_WE# WE VDDQ#D2 WE VDDQ#D2 WE VDDQ#D2 WE VDDQ#D2
E9 E9 E9 E9
VDDQ#E9 F1 VDDQ#E9 F1 VDDQ#E9 F1 VDDQ#E9 F1
M_B_DQSP0 F3 VDDQ#F1 H2 M_B_DQSP2 F3 VDDQ#F1 H2 M_B_DQSP4 F3 VDDQ#F1 H2 M_B_DQSP6 F3 VDDQ#F1 H2
M_B_DQSP1 C7 DQSL VDDQ#H2 H9 M_B_DQSP3 C7 DQSL VDDQ#H2 H9 M_B_DQSP5 C7 DQSL VDDQ#H2 H9 M_B_DQSP7 C7 DQSL VDDQ#H2 H9
DQSU VDDQ#H9 DQSU VDDQ#H9 DQSU VDDQ#H9 DQSU VDDQ#H9
E7 A9 E7 A9 E7 A9 E7 A9
B DML VSS#A9 DML VSS#A9 DML VSS#A9 DML VSS#A9 B
D3 B3 D3 B3 D3 B3 D3 B3
DMU VSS#B3 E1 DMU VSS#B3 E1 DMU VSS#B3 E1 DMU VSS#B3 E1
VSS#E1 G8 VSS#E1 G8 VSS#E1 G8 VSS#E1 G8
M_B_DQSN0 G3 VSS#G8 J2 M_B_DQSN2 G3 VSS#G8 J2 M_B_DQSN4 G3 VSS#G8 J2 M_B_DQSN6 G3 VSS#G8 J2
M_B_DQSN1 B7 DQSL VSS#J2 J8 M_B_DQSN3 B7 DQSL VSS#J2 J8 M_B_DQSN5 B7 DQSL VSS#J2 J8 M_B_DQSN7 B7 DQSL VSS#J2 J8
DQSU VSS#J8 M1 DQSU VSS#J8 M1 DQSU VSS#J8 M1 DQSU VSS#J8 M1
VSS#M1 M9 VSS#M1 M9 VSS#M1 M9 VSS#M1 M9
VSS#M9 P1 VSS#M9 P1 VSS#M9 P1 VSS#M9 P1
T2 VSS#P1 P9 DDR3_DRAMRST# T2 VSS#P1 P9 DDR3_DRAMRST# T2 VSS#P1 P9 DDR3_DRAMRST# T2 VSS#P1 P9
<4,13> DDR3_DRAMRST# RESET VSS#P9 RESET VSS#P9 RESET VSS#P9 RESET VSS#P9
T1 T1 T1 T1
M_B_ZQ1 L8 VSS#T1 T9 M_B_ZQ2 L8 VSS#T1 T9 M_B_ZQ3 L8 VSS#T1 T9 M_B_ZQ4 L8 VSS#T1 T9
ZQ VSS#T9 ZQ VSS#T9 ZQ VSS#T9 ZQ VSS#T9
Should be 240 Should be 240 Should be 240 Should be 240
B1 B1 B1 B1
Ohms +-1% VSSQ#B1 Ohms +-1% VSSQ#B1 Ohms +-1% VSSQ#B1 Ohms +-1% VSSQ#B1
2
2
B9 B9 B9 B9
R185 VSSQ#B9 D1 R198 VSSQ#B9 D1 R216 VSSQ#B9 D1 R235 VSSQ#B9 D1
VSSQ#D1 D8 VSSQ#D1 D8 VSSQ#D1 D8 VSSQ#D1 D8
240/F_4 240/F_4 240/F_4 240/F_4
VSSQ#D8 E2 VSSQ#D8 E2 VSSQ#D8 E2 VSSQ#D8 E2
M_B_CLK0 J1 VSSQ#E2 E8 J1 VSSQ#E2 E8 J1 VSSQ#E2 E8 J1 VSSQ#E2 E8
1
1
L1 NC#J1 VSSQ#E8 F9 L1 NC#J1 VSSQ#E8 F9 L1 NC#J1 VSSQ#E8 F9 L1 NC#J1 VSSQ#E8 F9
J9 NC#L1 VSSQ#F9 G1 J9 NC#L1 VSSQ#F9 G1 J9 NC#L1 VSSQ#F9 G1 J9 NC#L1 VSSQ#F9 G1
C301 L9 NC#J9 VSSQ#G1 G9 L9 NC#J9 VSSQ#G1 G9 L9 NC#J9 VSSQ#G1 G9 L9 NC#J9 VSSQ#G1 G9
1.6P/50V_4 NC#L9 VSSQ#G9 NC#L9 VSSQ#G9 NC#L9 VSSQ#G9 NC#L9 VSSQ#G9
M_B_CLK0# 100-BALL 100-BALL 100-BALL 100-BALL
SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
RAM _DDR3 RAM _DDR3 RAM _DDR3 RAM _DDR3
R543 R544
30/F_4 30/F_4
SMDDR_VREF_DQ1
+SMDDR_VREF_DIMM
C593 +SMDDR_VREF_DIMM SMDDR_VREF_DQ1

C 0.1u/10V_4 C
C202 C203 C233 C280 C313 C314 C279

C175 C262 C296 C169 C258 C293 C209 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4
0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4
Place these Caps near Memory Down

+1.5VSUS +1.5VSUS
+1.5VSUS
+1.5VSUS
+1.5VSUS
C196 C198 C191 C194 C188 C187 C189 C195 C167 C171 C165 C173 C174 C179 C172 C166
1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 C193 C199 C168 C170 C176 R200 +SMDDR_VREF_DIMM R585
10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 change to 1K/F_4 +SMDDR_VREF
1K/F_4 1K/F_4
+SMDDR_VREF
+1.5VSUS +1.5VSUS +SMDDR_VREF_DIMM R201 *0_6 SMDDR_VREF_DQ1_M3 1 3 SMDDR_VREF_DQ1 R586 *0_6

+1.5VSUS
R199 Q40 R584
2
1K/F_4 C211 REV:B Add *AP2302GN 1K/F_4 C234
C223 C229 C227 C222 C220 C221 C226 C228 C206 C207 C216 C212 C214 C208 C218 C213 0.1u/10V_4 0.1u/10V_4
1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 C210 C205 C217 C224 C230
10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 <4,13> DEEPS3_EC
+1.5VSUS
+1.5VSUS +1.5VSUS
4/27 add
201201118 Unstuff U34 and C732
C271 C276 C270 C274 C275 C268 C269 C273 +3V
D D
1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 C255 C263 C260 C259 C261 C257 C256 C265 C254 C264 C266 C272 C277
1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 U34
CLK_SCLK 6 1
<9,13,19> CLK_SCLK SCL A0
+1.5VSUS CLK_SDATA 5 2
<9,13,19> CLK_SDATA SDA A1 3
A2
+1.5VSUS +1.5VSUS 7 8 C732
WP VCC 4
GND *0.1u/10V_4
C303 C304 C309 C306 C308 C307 C302 C305
1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 C679 *M24C02-WMN6TP Quanta Computer Inc.
+
C300 C294 C291 C289 C295 C297 C290 C298 C299 C286 C288 C287 C310 address:A2
1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 *150u/6.3V_3528
PROJECT : Z09
WP =1 : WRITE DISABLE 3A
DDR3 MEMORY DOWN
1 2 3 4 5 6 7 8
5 4 3 2 1
Lid Switch (Hall sensor) eDP 7/28 modify
+3VPCU
25mil
EDP_AUX C33 0.1U/10V_4 EDP_AUX_C

<2> EDP_AUX
EDP_AUX# C34 0.1U/10V_4 EDP_AUX#_C
<2> EDP_AUX#
D2 *5.5V/25V/410P_4 25mil EDP_TX0 C42 0.1U/10V_4 EDP_TX0_C
D <2> EDP_TX0 D
1 2 EDP_TX0# C41 0.1U/10V_4 EDP_TX0#_C
<2> EDP_TX0#
C9 0.1u/10V_4_X7R
R19
1
*100K_4
2 LID#
INT_LVDS_DIGON
<7> INT_LVDS_DIGON
2
INT_LVDS_BLON
<7> INT_LVDS_BLON
D4
3
HE1 *5.5V/25V/410P_4
EM-6781-T3
1
R32 *0_4 LVDS_BRIGHT

<24> CONTRAST
R25 0_4
<7> INT_LVDS_BRIGHT
PT3661-BB : AL003661003
+3V
R52 *100K_4 EDP_AUX_C R45 *100K_4

R61 *100K_4 EDP_AUX#_C R65 *100K_4
C C
Penal SPEC: LCD CONNECTOR LCD Power

Iout:78~79.5mA +3V
Vout:32~34V
+3V
LED Driver-IC C26 C22
0.1u/10V_4_X7R C17 U2
1000p/50V_4
1U/6.3V_4 6 1 LCDVCC
IN OUT
VIN 4 2
IN GND C25 C21
INT_LVDS_DIGON 3 5 20111118 Remove C21/C12. C29
ON/OFF GND 0.1u/10V_4 .01u/25V_4 2.2U/6.3V_6
20120222 del 0 ohm R299. 20111122 change to 10u 1A inductor for FAE suggest.
20111121 change to 10u 0.1A indecator. 40V, 2A, 1mm(max) AAT4280-4
L22 D9
10uH_1A DFLS240-7-F VOUT
2 1 R24
20120111 Change C407 to 4.7uf 50V 1206 size. VOUT

LVDS_BRIGHT R20 10K_4 LVDS_BRIGHT_R C407 20120222 del 0 ohm R315. 20120221 add CN7 pin33/34 to GND. 100K_4
20111024 If phas shift PWM mode replace R65 to 10K. 0.8A
4.7u/50V_1206 R324 LVDS
1M_4 30
C369 29 30 34
28 29 34
2.2U/25V_6 28
27 33
23
22
21
20
19
18
17
16
U22 FB1 26 27 33
FB2 25 26 32
PAD
PAD
PAD
VIN
NC
SW
PWM
FAULT
24 FB3 24 25 32
PAD 23 24 31
25 22 23 31
B
30
PAD
PAD
26
R334
CCD_PWR
21
20
22
21
Backlight Control B
GNDP 56K_4 +3V 20
C20 1u/6.3V_4 VDDIO 1 CCD +3V-current budget 0.2A 19
VDDIO 15 20111111 change to R423 to 56K. 18 19
BL_ON R21 1.2K_4 2 PGND 17 18 +3VPCU
EN TPS61187 14 LCDVCC R34 *SHORT_6 16 17
R23 620K/F_4 3 OVC 15 16
FSLCT 13 MODE 14 15
R26 45.3K_4 4 RFPWM/MODE 13 14 R275
ISET 12 FB1 USBP8-_R 12 13 *100K_4
R33 *10K_4 5 IFB1 CCD-USB USBP8+_R 11 12 +3V LID#
+3V FPO 11 LID# <24>
11 FB2 10
20111024 Reserve if Host need to know any IFB2 9 10
GND
IFB6
IFB5
IFB4
IFB3
PAD
PAD
PAD
fault trigger on backlight driver EDP_HPD 8 9

<2> EDP_HPD 8
7
EDP_AUX_C 6 7 R314
Vovc=[Rupper/Rdowm+1]*Vov_th LID#,EC intrnal PU
27
28
29
10
EDP_AUX#_C 5 6 R296
(Rupper=1M,Vov_th=1.95V) 5
1
4 10K_4
EDP_TX0_C 3 4 10K_4 D8
EDP_TX0#_C 2 3
2 BAS316
1
1 BL#
FB3
2
CN7
R FLCT F SW
20111013 Create LED D-IC BL_ON
833K 600KHz
R41 *SHORT_4 INT_LVDS_BLON
3
625K 800KHz Q16
USBP8+_R R284 2N7002DW
<9> USBP8+
USBP8-_R 2
<9> USBP8- EC_FPBACK# <24>
499K 1MHz 100K_4
Q17
R36 *SHORT_4 DTC144EUA
1
4
1
A A
VIN VOUT
R67 Select is from 210Hz~20KHz,866K~9.09K.
VDDIO R22 *0_4 MODE 20120111 Un-stuff C410 for LCD flacking
C393 C397 C406 issue, FAE suggestion.
*0.1u/50V_8 C410
4.7u/25V_8 1000p/50V_4 R341
9.09K_4 *0.033u/16V_4_X7R
20111024 Bypass CAP for FAE request.

Close to Pin1 Quanta Computer Inc.
20120116 change Bypass CAP to 50V.
20111024 Reserve Phase shift PWM mode cirucit, PROJECT : Z09
if R67 high impedance, bypassing capacitor is Size Document Number Rev
for improves noise sensitivit and not exceed 33pf. 3A
LVDS/CAMERA/LID
5 4 3 2 1
5 4 3 2 1
HDMI from PCH

C354 0.1u/10V_4 INT_HDMITX0N
<7> INT_HDMITX0N_C
C353 0.1u/10V_4 INT_HDMITX0P
<7> INT_HDMITX0P_C
<7> INT_HDMITX2N_C
<7> INT_HDMITX2P_C
<7> INT_HDMITX1N_C
<7> INT_HDMITX1P_C
C356 0.1u/10V_4 INT_HDMICLK-
D <7> INT_HDMICLK-_C D
C355 0.1u/10V_4 INT_HDMICLK+
<7> INT_HDMICLK+_C
R7 R8 R1 R2 R3 R4 R5 R6
680_4 680_4 680_4 680_4
680_4 680_4 680_4 680_4
3
Q1
+3V 2
R294 2N7002D
*100K/F_4
1
20111118 change R747 to 100K.
I2C
C +5V C
MOS close to connector
2
D6
+3V +3V +3V RB501V-40
HDMI-detect
1
R310 R288 Q12
10K_4 2.2K_4 R260
<24> HDMI_HPD_EC#
2
BSN20 2.2K_4
+3V HDMI_DDCCLK_SW 1 3 HDMI_DDCCLK_MB

<7> HDMI_DDCCLK_SW
+5V
follow CRB 1.0 change to 2.2K
R292 R266 +5V

*10K_4 10K_4
2
HDMI_MB_HP
HDMI_HP <7>
D7
5
+3V +3V RB501V-40

Q10
2N7002DW
1
R289 Q13
2.2K_4 R261
2
BSN20 2.2K_4
4
B B
HDMI_DDCDATA_SW 1 3 HDMI_DDCDATA_MB
<7> HDMI_DDCDATA_SW
follow CRB 1.0 change to 2.2K
EMI
INT_HDMITX2P
HDMI connector
CN1
R254 *100/F_4 20
INT_HDMITX2P 1 SHELL1
INT_HDMITX2N 2 D2+
INT_HDMITX2N 3 D2 Shield
INT_HDMITX1P INT_HDMITX1P 4 D2-
5 D1+
R253 *100/F_4 INT_HDMITX1N 6 D1 Shield
INT_HDMITX0P 7 D1-
INT_HDMITX1N 8 D0+
INT_HDMITX0N 9 D0 Shield 23
INT_HDMITX0P INT_HDMICLK+ 10 D0- GND
11 CK+ 22
R255 *100/F_4 INT_HDMICLK- 12 CK Shield GND
+5V 13 CK-
INT_HDMITX0N 14 CE Remote
F1 HDMI_DDCCLK_MB 15 NC
A INT_HDMICLK+ KMC3S110RY D1 HDMI_DDCDATA_MB 16 DDC CLK A
2 1 HDMI_5V_R SSM22LLPT 17 DDC DATA
R256 *100/F_4 HDMI_5V 18 GND
19 +5V
INT_HDMICLK- C1 HDMI_MB_HP HP_DET_CN HP DET 21
R263 *SHORT_4 SHELL2
470p/X7R_4
R262
HDMI
20K_4
20110919 change to 20k. PROJECT : Z09

3A
HDMI (PS8101)
5 4 3 2 1
5 4 3 2 1
Giga-LAN BCM57780
+3V_LAN
31
U10
15mil
+3V_LAN 42 25 BIASVDD L15 BLM18AG601SN1D_6
VDDO BIASVDDH C344 0.1u/10V_4_X7R
6
VAUX_12 VDDC
20110214 Add C622 and C621 for power noise. 15 14 XTALVDD L13 BLM18AG601SN1D_6
41 VDDC XTALVDDH C337 0.1u/10V_4_X7R
D D
L21 VDDC
VAUX_12
15mil AVDDL 27 30 AVDDH L20 BLM18AG601SN1D_6
C370 4.7U/6.3V_6 33 AVDDL AVDDH
BLM18AG601SN1D_6 C347
C622
0.1u/10V_4_X7R
4.7U/6.3V_6
39 AVDDL
AVDDL
BCM57780
7mm X 7mm AVDDH
36 C365
C357
0.1u/10V_4_X7R
0.1u/10V_4_X7R
48-Pin QFN C621 4.7U/6.3V_6
L16
15mil GPHY_PLLVDD 24 37
GPHY_PLLVDDL TRD3_N LAN_TRD3N <18>
C343 4.7U/6.3V_6 38
TRD3_P LAN_TRD3P <18>
BLM18AG601SN1D_6 C342 0.1u/10V_4_X7R
35
TRD2_N LAN_TRD2N <18>
L14 34
15mil PCIE_PLLVDD 18 TRD2_P LAN_TRD2P <18>
PCIE_PLLVDDL 31
BLM18AG601SN1D_6 C335 4.7U/6.3V_6 32
C341 0.1u/10V_4_X7R 21
PCIE_PLLVDDL 29
28
48 LAN_LINKLED#
LINKLED# LAN_LINKLED# <18>
47
SPD100LED# 46
SPD1000LED# 45 LAN_ACTLED#
TRAFFICLED# LAN_ACTLED# <18>
C340 0.1u/10V_4_X7R PCIE_RX3+_R 17
<9> PCIE_RX3+ PCIE_TXDP
C339 0.1u/10V_4_X7R PCIE_RX3-_R 16
<9> PCIE_RX3- PCIE_TXDN
22 5
<9> PCIE_TX3+ PCIE_RXDP MODE
23
<9> PCIE_TX3- PCIE_RXDN
PCIE_LAN_WAKE# 4
C <7> PCIE_LAN_WAKE# WAKE# C
2
<9,19,20,24,25> PLTRST# 20 PERST#
<9> CLK_PCIE_LOM PCIE_REFCLK_P
<9> CLK_PCIE_LOM# 19
PCIE_REFCLK_N
44 BCM_EEC
EECLK
20120201 Change CAP from 27P to 15P. 43 BCM_EED
R286 1K/F_4 VMA_PRES 40 EEDATA VAUX_12
+3V VMAIN_PRSNT
R267 4.7K_4 LOW_PWR 1
LOW_PWR
C334 15p/50V_4 R248 200_4 XTALO 11 L17 4.7uh
SR_LX 8 Don't route under Choke.
SR_VFB
4
3
XTALO 13
Y3 XTALI 12 XTALO 10
XTALI SR_VDDP +3V_LAN
25MHz-LAN 9
R250 1.24K/F_4 RDAC 26 SR_VDD C348 C387 C372 C345
RDAC 10u/6.3V_6
2
1
4.7U/6.3V_6 0.1u/10V_4_X7R 0.1u/10V_4_X7R

C336 15p/50V_4 XTALI
R264 4.7K_4 3 7
+3V_LAN CLK_REQ# NC
BCM_CLKREQ# 2111201 change C6108 power from +3V_S5 to +3V_LAN.

GND
BCM57780
49
B B
+3V_LAN
LAN POWER
EEPROM
2
+3V_LAN
REV:B Q18 R303
6/11 *DTC144EUA *4.7K_4
3 1 PCIE_LAN_WAKE#
<24> WAKE_SRC_2
R326 R306 R298 0_4

20111122 Remove Q44 and change plant to +3V_S5. *1K_4 1K_4
U21 20120305 Stuff R298.
BCM_EED 5 1
BCM_EEC 6 SDA A0 2
SCL A1 3 +3V_LAN
+3V_LAN 7 A2
R291 2.2/F_6 C373 4.7U/6.3V_6

R327 R307
*1K_4 4
WP
8
S5 IOAC
+3V_S5 1K_4 GND VCC +3V_S5
C362 0.1u/10V_4_X7R *AT24C02 C385
2
0.1u/10V_4_X7R
3 1 BCM_CLKREQ#
<9> CLK_PCIE_LAN_REQ#
A A
Q8
VAUX_12 20mil EEPROM Strapping 2N7002K
R251 *0_4
C374 4.7U/6.3V_6 EEPROM Type EECLK EEDATA
C358 0.1u/10V_4_X7R
24LC02 1 1
C338 0.1u/10V_4_X7R Quanta Computer Inc.
C359 0.1u/10V_4_X7R Internal 1 0 PROJECT : Z09
3A
GLAN BCM57780
5 4 3 2 1
1 2 3 4 5 6 7 8
TRANSFORMER
U11
<17> LAN_TRD3P LAN_TRD3P 1 TD1+ MX1+ 24 X-TX3P
<17> LAN_TRD3N LAN_TRD3N 2 TD1- MX1- 23 X-TX3N
3 TCT1 MCT1 22
A A
C13 C12
4 21
0.1u/10V_4_X7R 0.1u/10V_4_X7R TCT2 MCT2
<17> LAN_TRD2N LAN_TRD2N 5 20 X-TX2N
TD2+ MX2+
<17> LAN_TRD2P LAN_TRD2P 6 19 X-TX2P
TD2- MX2-

TD3+ MX3+
TD3- MX3-
9 16
TCT3 MCT3
C10 C11
10 15
0.1u/10V_4_X7R 0.1u/10V_4_X7R TCT4 MCT4
TD4+ MX4+
TD4- MX4-
NS692417
B 2011/08/31 Change to small size B
DB0KL3LAN0
R9 R13 R12 R11
20111121 change from dual to single transformer. 75/F_8 75/F_8 75/F_8 75/F_8
2
D3
R17
C6 *1M_8
1500p/3KV_18 *P640P3100SBRP
1
For EMI
CN2
LAN_ACTLED# 9
<17> LAN_ACTLED# YELLOW_N U18
R18 220_8 LAN_ACT_LED_PWR 10
+3V_S5 YELLOW_P 16 LAN_TRD1P 1 8 LAN_TRD1P
GND4 15 LAN_TRD1N 2 1 8 7 LAN_TRD1N
X-TX0P 1 GND3 14 R257 *0_6 LAN_TRD0N 3 2 7 6 LAN_TRD0N
C 0+ GND2 3 6 C
X-TX0N 2 13 LAN_TRD0P 4 5 LAN_TRD0P
X-TX1P 3 0- GND1 4 5
X-TX2P 4 1+ *UCLAMP2512T.TCT
X-TX2N 5 2+
2- U17
X-TX1N 6
X-TX3P 7 1- LAN_TRD3P 1 8 LAN_TRD3P
X-TX3N 8 3+ LAN_TRD3N 2 1 8 7 LAN_TRD3N
3- LAN_TRD2N 3 2 7 6 LAN_TRD2N
LAN_TRD2P 4 3 6 5 LAN_TRD2P
LAN_LINKLED# 11 4 5
<17> LAN_LINKLED# GREEN_N
+3V_S5 R14 220_8 LAN_LNK_LED_PWR 12 *UCLAMP2512T.TCT
GREEN_P
RJ45
LAN_ACTLED#
LAN_LINKLED#
C368 C16
*0.1u//50V_8 *0.1u//50V_8
D D

PROJECT : Z09
LAN Transformer and RJ45 3A

1 2 3 4 5 6 7 8
5 4 3 2 1
LED/Card reader/Touchpad B CON TPM

C328 C326 C321
*0.1U/10V_4 *0.1U/10V_4 *0.1U/10V_4 CN13
1
+3VPCU
2
+3V_S5 3
+3V CN14
+5V +3V 4 R242 0_4 1
L10 0_6 +TPVDD 5 <7,24> CLKRUN# PLTRST# 2 1
L9 *0_6 +TPVDD TPCLK_R 6 *0.1U/10V_4 3 2
C322 TPDATA_R 7 C330 4 3
D +3V *0_4 R236 8 5 4 D
<9,13,14> CLK_SDATA +3V_S5 5
0.1u/10V_4_X7R *0_4 R237 9 6
<9,13,14> CLK_SCLK +3V 6
10 7
11 8 7
<9> PCIE_TX2+ 8
12 R241 *0_4 SERIRQ_R 9
+5V +3V <9> PCIE_TX2- 13 <8,24> SERIRQ 10 9
R247 *0_4 LPCPD#_R
<7> LPCPD# 10
2
0_4 R243 20111128 change net name to SMBALERT# 14 11
<9> CLK_PCIE_MMC <8,20,24> LPC_LAD0 11
*0_4 R245 15 12
3 1 <9> CLK_PCIE_MMC# 16 <8,20,24> LPC_LAD1 13 12
<9> SMBALERT# TP_INT#_D
<8,20,24> LPC_LFRAME# 13
17 C325 *10p/50V_4 PCLK_TPM_C 14
<9> PCIE_RX2+ 18 15 14
R244 R246 Q45 R240 0_4
<9> PCIE_RX2- <9> PCLK_TPM 15
10K_4 10K_4 *2N7002K 19 16
<8,20,24> LPC_LAD2 16
20
<9,17,20,24,25> PLTRST# 21 <8,20,24> LPC_LAD3
TPM_CON
<9> PCIE_CLKREQ0#
22
<24> TPCLK L11 0_6 TPCLK_R 23 20111127 add R221/C6496 for EMI request. 20111121 change footprint
<24> KEY_BL_EN
<24> TPDATA L12 0_6 TPDATA_R 24
<24> PWRLED#
25
<24> SUSLED# 26 20111201 modify pin define for BTB connector.
<24> BATLED1#
C327 C329 27 20111205 modify pin out define.
<24> BATLED0# 28
<24> NBSWON#
*.01u/25V_4 *.01u/25V_4 TP_INT#_D 29 31
30 32
<9,10> BOARD_ID4
C C
20120302 Add net BOARD_ID 4. CON30P
20111122 change pin29/30 for Touch pad use. 20111114 Change con
CPU FAN Audio Connector
C225 C219
+3V +5V +3V +5V *0.1U/10V_4
*0.1U/10V_4 CN11
+5V 1
2 1
3 2
R553 R561 R552 R551 4 3
+3V 5 4
1K_4 *SHORT_8
10K_4 10K_4 <24> PCBEEP_EC 6 5
7 6
<8> SPKR
CN10 8 7
<24> FANSIG <24> AMP_MUTE#
9 8
2
4 6 10 9
3 5 <8> PCH_AZ_CODEC_RST#
<8> PCH_AZ_CODEC_SYNC 11 10
1 3 FAN_PWM_CN 2 12 11
B <8> PCH_AZ_CODEC_SDIN0 B
<24> CPUFAN# 1 13 12
<8> PCH_AZ_CODEC_SDOUT
Q37 30mil FAN <8> PCH_AZ_CODEC_BITCLK PCH_AZ_CODEC_BITCLK_R 14 13
MMBT3904 L8 FCM1608KF-121T04 15 14 17
16 15 17 18
C204 16 18
Top layer
L6, C6495 CN9 22p/50V_4 Audo_CON
20111116 For EMI solution.

20111116 Change R256 to L6 for EMI reqeust.
3/5VPCU reset switch
SWITCH_1.5 SW2
2 3 8223_EN <32>
4 1
1
D5
A C346 A
5
0.1u/16V_4 *14V/38V/100P_4
2

PROJECT : Z09
3A
mSATA/CR/LED
5 4 3 2 1
1 2 3 4 5 6 7 8
MINI-CARD WLAN(MPC) 20120217 reserve R648 PU 100k. Q11 AO3413

+3VPCU
+3.3V: 1000mA 1 3
Check LED signal. (active high or low)
+3.3Vaux:330mA 20111207 change Pin51 net name to BT_POWERON R648 20111122 change to Pmose
+1.5V:500mA 20111107 move debuge port to cn3 H=7.0mm *100K_4
2
CN5
R332 *SHORT_4 51 52 <24> IOAC_LANPWR# high Mini card +3V power enable
<24> BT_POWERON Reserved +3.3V +WL_VDD
R320 *0_4 CL_RST1#_WLAN 49 50
<9> CL_RST1# Reserved GND
R321 *0_4 CL_DATA1_WLAN 47 48 +1.5V_Mini1_VDD
<9> CL_DATA1 45 Reserved +1.5V 46
R311 *0_4 CL_CLK1_WLAN low Mini card +3V power disable
<9> CL_CLK1 Reserved LED_WPAN# WLAN_OFF <24>
A 43 44 TP57
A
41 GND LED_WLAN# 42 201201118 add IOAC WLAN OFF function. +WL_VDD
+WL_VDD +3.3Vaux LED_WWAN#
39 40
37 +3.3Vaux GND 38 R293 *SHORT_8 +WL_VDD
GND USB_D+ USBP10+ <9>
35 36 USBP10- <9> BT
33 GND USB_D- 34 20120221 add R650 for PLTRST#.
<9> PCIE_TX8+ PETp0 GND
31 32 WLAN_CLK_SDATA 20120216 add R643/R646 un-stuff for iRST reserve. C389 C405 C361 C332
<9> PCIE_TX8- 29 PETn0 SMB_DATA 30 WLAN_CLK_SCLK 10u/6.3V_6 0.1u/10V_4 *0.1u/10V_4 *0.1u/10V_4
27 GND SMB_CLK 28
GND +1.5V +1.5V_Mini1_VDD
25 26 R650 *0_4 PLTRST#
<9> PCIE_RX8+ PERp0 GND
23 24 +WL_VDD
<9> PCIE_RX8- PERn0 +3.3Vaux
21 22 R643 0_4 IOAC_PCIERST#
19 GND PERST# 20 IOAC_PCIERST# <7,24>
UIM_C4 W_DISABLE# RF_EN <24>
17 18 R646 *0_4
UIM_C8 GND PCIERST# <24>
15 16
13 GND UIM_VPP 14 +1.5V_Mini1_VDD +1.5V
<9> CLK_PCIE_WLAN 11 REFCLK+ UIM_RESET 12 20111107 move debuge port to cn3
<9> CLK_PCIE_WLAN# REFCLK- UIM_CLK
9 10
CLK_PCIE_WLAN_REQ#_R 7 GND UIM_DATA 8
5 CLKREQ# UIM_PWR 6
500mA for +1.5V R249 *0_8
Reserved +1.5V +1.5V_Mini1_VDD
3 4
GND
GND
PCIE_WAKE#_R 1 Reserved GND 2
WAKE# +3.3V +WL_VDD
C404 C367 C333
MINI-CARD1 1000p/50V_4 0.1u/10V_4 10u/6.3V_6
53
54
B B
2011017 : stuff q21 to enable wake function on WLAN for IOAC Close CN13
check IOAC power rail can reduce Q21
20120105 Change power plant for leakage issue.
mSATA Close CN3 leakage circuit +3V_S5 +WL_VDD
+3V_SATA
+3V
R10 *SHORT_8 S5 2N7002DW R287 R285 IOAC
4.7K_4 4.7K_4
C3 C23 C24 5
10U/10V_8 0.1U/10V_4 0.1U/10V_4 <9> SMB_PCH_DAT 4 3 WLAN_CLK_SDATA
+3V_SATA 1 6 WLAN_CLK_SCLK
<9> SMB_PCH_CLK
rating = 1000mA @ 128G
C C
Q14
CN6 20120105 Change power plant for leakage issue.
Debug 20111107 move debuge port to cn3 51 52
49 Reserved +3.3V 50 +3V_S5 +WL_VDD
R269 *0_4 47 Reserved GND 48
<9,17,19,24,25> PLTRST# Reserved +1.5V
R295 *0_4 45 46
<9> CLK_LPC_DEBUG
43 Reserved LED_WPAN# 44 IOAC
41
39
GND
+3.3Vaux
LED_WLAN#
LED_WWAN#
42
40
S5 2N7002DW R265 R252
4.7K_4 4.7K_4
37 +3.3Vaux GND 38 5
35 GND USB_D+ 36
C378 .01u/25V_4 SATA_TXP1_C 33 GND USB_D- 34 4 3 CLK_PCIE_WLAN_REQ#_R
<8> SATA_TXP1 PETp0 GND <9> PCIE_CLKREQ5#
C379 .01u/25V_4 SATA_TXN1_C 31 32
<8> SATA_TXN1 29 PETn0 SMB_DATA 30
27 GND SMB_CLK 28 2
C380 .01u/25V_4 SATA_RXN1_C 25 GND +1.5V 26
<8> SATA_RXN1 PERp0 GND
<8> SATA_RXP1 C381 .01u/25V_4 SATA_RXP1_C 23 24 1 6 PCIE_WAKE#_R
PERn0 +3.3Vaux <24> WAKE_SRC_1
21 22 20111107 move debuge port to cn3
19 GND PERST# 20
17 UIM_C4 W_DISABLE# 18
UIM_C8 GND Debug Q9
15 16 A_LFRAME#_R R27 0_4 R258 *0_4
GND UIM_VPP LPC_LFRAME# <8,19,24>
13 14 A_LAD3_R R28 0_4
11 REFCLK+ UIM_RESET 12 LPC_LAD3 <8,19,24>
A_LAD2_R R29 0_4 R259 *0_4
REFCLK- UIM_CLK LPC_LAD2 <8,19,24>
9 10 A_LAD1_R R30 0_4
D 7 GND UIM_DATA 8 LPC_LAD1 <8,19,24> D
A_LAD0_R R31 0_4 20111118 change mose footprint to dual type.
CLKREQ# UIM_PWR LPC_LAD0 <8,19,24>
5 6
3 Reserved +1.5V 4
GND
GND
1 Reserved GND 2
WAKE# +3.3V
MINI-CARD1 Quanta Computer Inc.
53
54
PROJECT : Z09
modify 20111102 3A
MINI PCI-E card/TV
1 2 3 4 5 6 7 8
1 2 3 4
MAIN SATA HDD RE-DRIVER
A A
B B
MAIN SATA HDD 21111207 change Cn12 Pin define following ZHA. EE RETURN-PATH CAPACITORS +1.5VSUS
VIN
+3V *0.1u/25V_4
C315 VIN *.1u/10V_4
+3V
CN9 *.1u/10V_4 C607 +1.05V_VTT
C311 +1.5VSUS 0.1u/25V_4 C125
26 24 C30 *2200p/50V_4 .1u/10V_4
+3V
25 23 C740 VIN
22 *.1u/10V_4 *0.1u/25V_4
21 C249 C15 *.1u/10V_4
+1.5VSUS +5V
20 C606 +3V
19 *0.1u/25V_4
18 *.1u/10V_4 C741 .1u/10V_4
+1.5VSUS
17 C122 C164
+1.05V_VTT +1.05V_GFX
16 +5V_HDD *0.1u/25V_4 .1u/10V_4
15 C201 C765
+VCC_CORE
14
13 +3V *0.1u/25V_4 .1u/10V_4 201201117 C765 for EMI suggestion.
12 C163 C197 201201119 Add C2765 for EMI suggestion to GND.
+VGPU_CORE VIN
11 *.1u/10V_4
10 C32 *0.1u/25V_4 *470p/X7R_4
+1.05V_VTT
9 C46 C742
+VGPU_CORE +3V
8
7 *.1u/10V_4 *0.1u/25V_4
6 SATA_RXP0_C C596 .01u/25V_4 C102
SATA_RXP0 <8> +1.05V_GFX C444 +VGPU_CORE
5 SATA_RXN0_C C597 .01u/25V_4
4 SATA_RXN0 <8>
*0.1u/25V_4
3 SATA_TXN0_C C598 .01u/25V_4 SATA_TXN0 <8> *.1u/10V_4 C18 +3VPCU +1.05V_VTT
2 SATA_TXP0_C C599 .01u/25V_4 SATA_TXP0 <8> C433 20111128 del C508/C704/C479/C497 and change path cap power well.
+VGPU_CORE
1
*.1u/10V_4 C316 *0.1u/25V_4
C28 C35 *.1u/10V_4
MAIN_SATA_CONN
C319 0.1u/25V_4
C27 *470p_4 C72 *2200p/50V_4
C C
1A (MAX.)
C14 *0.1u/25V_4
R528 *SHORT_8 +5V_HDD C124 *2200p/50V_4 *220p/50V_4
+5V
C360 *0.1u/25V_4 C545 +1.05V_GFX
C595 C592 C159 C157 C160 C158 C252 *2200p/50V_4
+ *220p/50V_4
100u/6.3V_3528 10u/6.3V_6 *.1u/16V_4 *.1u/16V_4 .01u/25V_4 .01u/25V_4 C331 *2200p/50V_4 C7 0.1u/25V_4 C123 +1.05V_VTT
C320 *2200p/50V_4 *220p/50V_4
C2 *0.1u/25V_4 C579 +1.5VSUS
ODD Power (SATA) +3VPCU

+15V +5V
Q32
AO6402A +5V_ODD
+5V
1
6
R469 5 4 R477 *0_8
100K 2
1 R475
22_8
2
R470 3
ODD_EN_Q 2 1
MOD_EN_5V
ODD (SATA) 100K
3
CN8
14 <24> ODD_POWER R461 *SHORT_4 ODD_EN
GND14 ODD_EN_Q 2
1
1 <8> PCH_ODD_EN R462 *0_4

GND 2 SATA_TXP5_C C60 .01u/25V_4 C492 Q28
A+ SATA_TXP5 <8> R463
3 SATA_TXN5_C C64 .01u/25V_4 SATA_TXN5 <8> 0.1u/25V_6 DMN601K-7
2
A- 4 *100K
1
GND 5 SATA_RXN5 C75 .01u/25V_4
2
B- 6 SATA_RXP5 SATA_RXN5_C <8> 2N7002DW

C83 .01u/25V_4
B+ 7 SATA_RXP5_C <8> Q30
GND R154 10K_4 201201117 C766 for EMI suggestion.
+3V
4
C766 15p/50V_4 20120201 change R154 to 10k PU +3V. +5V_ODD

D D
8
DP 9 ODD_PRSNT# <9>
5V 10
5V 11
+
C107 C117 C113 C110 C507 C532

MD 12
GND 13 .01u/25V_4 .01u/25V_4 *.1u/16V_4 *.1u/16V_4 10u/6.3V_6 100u/6.3V_3528
GND 20111118 change mose footprint to dual type.
15
GND15
SATA_ODD_H=7.7
EC_ODD_EJ <24>
R166 10K_4 +3V PROJECT : Z09
3A
SATA-HDD/ODD/USB-ESATA
1 2 3 4
1 2 3 4 5 6 7 8
201201113 change KB con footprint.
K/B 7 8 MX3
201201117 change KB con footprint. SCREW HOLE
5 6 MX2 KB
3 4 MX4 MY0 1
<24> MY0
1 2 MX5 MY1 2
<24> MY1 3
CP6 *100p/50Vx4 MY2
7 8 <24> MY2 4
MX6 MY3
<24> MY3
5 6 MX7 MY4 5 HOLE8 HOLE6 HOLE4 HOLE2 HOLE1
<24> MY4
3 4 MY17 MY5 6 HG-C217D118P2 *HG-C217D118P2 H-C236D142P2 *H-C236D118P2 *HG-C256D118P2
<24> MY5
1 2 MY16 MY6 7 7 6 7 6 7 6
<24> MY6 8 8 5 8 5 8 5
CP5 *100p/50Vx4 MY7
7 8 <24> MY7 9 9 4 9 4 9 4
MY3 MY8
<24> MY8
5 6 MY2 MY9 10 HOLE9
<24> MY9
3 4 MY1 MY10 11 *H-TC236I150BC276D150NP2
<24> MY10
1
2
3
1
2
3
1
2
3
A 1 2 MY0 MY11 12 A
<24> MY11 13
CP1 *100p/50Vx4 MY12
7 8 <24> MY12 14
MY7 MY13
<24> MY13
5 6 MY6 MY14 15
<24> MY14
3 4 MY5 MY15 16
<24> MY15
1
1 2 MY4 MY16 17 HOLE3 HOLE15 HOLE5
<24> MY16 18
CP2 *100p/50Vx4 MY17 HOLE10 *HG-C256D118P2 *HG-C256D118P2 HG-C236D122P2 HOLE7
7 8 <24> MY17 19 7 6 7 6 7 6
MY11 MX7 *H-TC236I150BC276D150NP2 H-C236I122D122NP2
<24> MX7
5 6 MY10 MX6 20 8 5 8 5 8 5
<24> MX6
3 4 MY9 MX5 21 9 4 9 4 9 4
<24> MX5
1 2 MY8 MX4 22
<24> MX4 23
CP3 *100p/50Vx4 MX3
<24> MX3
1
2
3
1
2
3
1
2
3
7 8 MY15 MX2 24 27
<24> MX2
1
5 6 MY14 MX1 25 28
<24> MX1
3 4 MY13 MX0 26 HOLE13
<24> MX0
1 2 MY12 *H-TC236I150BC276D150NP2
CP4 *100p/50Vx4 CN12
C750 *100p/50V_4 MX1 HOLE17
C751 *100p/50V_4 MX0 +3VPCU *HG-C256D118P2 HOLE18 HOLE16
7 6 *H-C94D94N H-C217D102P2
8 5
1
RP5 10K_10P8R 9 4
10 1 MX3 HOLE12
MX4 9 2 MX2 *H-TC236I150BC276D150NP2
1
2
3
MX5 8 3 MX1
1
MX6 7 4 MX0
MX7 6 5
1
20111125 modify pin define
B B
BATT Enable short pad

ICT TEST FIXTURE(VOLTAGE TRANSLATOR) HOLE11
*hg-te256x256i118bc256d118p2-v3
1
2 3
BATT_EN# <31>
PAD1
*spad-re118x362np
+3V +1.05V_VTT
20111208 Change Hole8 to BATT short pad.
TP44
1
TP43
R639 R638
TP10
10K_4 10K_4 XDP_TMS_VT <3,8>
U37 XDP_TCLK_VT <3,8>
XDP_TDI_VT <3>
1 16
2 VCCA VCCB 15
TP8 1DIR 1OE# TP77
3 14
2DIR 2OE# TP84
4 13
<28> JTAG_TDO 1A1 1B1
5 12
<28> JTAG_CLK_VT 6 1A2 1B2 11 R636 R637
<28> JTAG_TMS_VT 7 2A1 2B1 10 100/F_4 100/F_4
8 2A2 2B2 9
TP45 GND GND
TP46
C *74AVC4T245PW C
HOLE14
*hg-te256x256i118bc256d118p2-v3
1
2 3
BATT_EN# <31>
D D

PROJECT : Z09
3A
XDP/ Hole
1 2 3 4 5 6 7 8
5 4 3 2 1
USB3.0 CONN Reserve for Debug

<9> USBP9- R16 *0_4 USBP0-_R
<9> USBP9+ R15 *0_4 USBP0+_R
D
USB 3.0 D
USBPWR1
R282 15_4 R271 *SHORT_4 CN4
USB3.0 CONN
1
1 VBUS
C382 0.1U/10V_4 USB30_TX2-_C USB30_TX2-_R USBP0-_R 2
<9> USB30_TX2- <9> USBP0- 2 D-
C383 0.1U/10V_4 USB30_TX2+_C USB30_TX2+_R USBP0+_R 3
<9> USB30_TX2+
USB 3.0 <9> USBP0+
USB30_RX1-_R
4
5
3
4
5
D+
GND
SSRX-
USBPWR2 U13 USB30_RX1+_R 6
R283 15_4 R273 *SHORT_4 CN3 USB30_RX2-_R 1 10 USB30_RX2-_R R270 *SHORT_4 7 6 SSRX+
USB3.0 CONN USB30_RX2+_R 2 1 10 9 USB30_RX2+_R USB30_TX1-_R 8 7 GND
1 3 2 9 USB30_TX1+_R 9 8 SSTX-
2 1 VBUS 4 GND_3/8 7 9 SSTX+
USB1-_CHARGER USB1-_CHARGER_R USB30_TX2-_R USB30_TX2-_R
13
12
11
10
USB1+_CHARGER USB1+_CHARGER_R 3 2 D- USB30_TX2+_R 5 4 7 6 USB30_TX2+_R
4 3 D+ 5 6
13
12
11
10
USB30_RX2-_R 5 4 GND *RClamp0524P
USB30_RX2+_R 6 5 SSRX- R277 15_4
R272 *SHORT_4 7 6 SSRX+
R280 15_4 USB30_TX2-_R 8 7 GND
USB30_TX2+_R 9 8 SSTX- USB30_RX1+_R
9 SSTX+ <9> USB30_RX1+
USB30_RX1-_R
13
12
11
10
<9> USB30_RX1-
USB30_RX2-_R
<9> USB30_RX2-
USB30_RX2+_R
<9> USB30_RX2+
13
12
11
10
R276 15_4
U12
1 6 USBPWR2 R279 15_4
R281 15_4 USB1-_CHARGER_R 2 GND 6 5 USB1-_CHARGER_R
USB1+_CHARGER_R 3 2 5 4 USB1+_CHARGER_R 0.1U/10V_4
3 4 C376 USB30_TX1+_C USB30_TX1+_R
<9> USB30_TX1+
C *RClamp0582N C375 USB30_TX1-_C USB30_TX1-_R C
<9> USB30_TX1-
0.1U/10V_4
R278 15_4
USB charger
20111117 remove 0ohm resistor R61112/R61110 +5V_S5
USBP1-
USBP1- <9> +5VPCU
USBP1+
USBP1+ <9>
*0_4 R304 MAINON <24,34,35,37,39>
U19 C5
USB_CHG_MODE <24> G547E1P81U Close USB3.0 U1
R305 *SHORT_4 2 8 USBPWR2 1U/6.3V_4 2 8 USBPWR1
3 IN1 OUT3 7 3 IN1 OUT3 7
+5VPCU +5VPCU IN2 OUT2 6 C363 C366 IN2 OUT2 6 C8 C4
+
USB_BC_EN 4 OUT1 4 OUT1
+
1 EN C364 <24> USBON# 1 EN# 150u/6.3V_3528 1000p/50V_4
C392 0.1u/10V_4 GND 5 150u/6.3V_3528 GND 5
U20 C395 OC# 470P/50V_4 .1U/10V_4 OC#
BC_CEN 1 8 C400 *10u/6.3V_6 1U/6.3V_4 G547F2P81U
R300 USB1-_CHARGER 2 CEN CB1 7 USBP1-
USB1+_CHARGER 3 DM TDM 6 USBP1+ USB_OC0#
4.7K_4 DP TDP
4 5
SELCDP VDD 9
PGND USB_OC0# <9>
R290 SLG55584A
B *4.7K_4 B
+3VPCU
System status(CB) 2010/11/21
add 47K pull high U15
> Hi: S0 Charging with CDP/SDP. USB30_RX1-_R 1 10 USB30_RX1-_R
> Lo: S3,DCP autodetect. C371 *0.1U/10V_4 USB30_RX1+_R 2 1 10 9 USB30_RX1+_R
Pull high CDP/SDP autodetect. 2 9
3
Pull Low SDP only. R268 USB30_TX1-_R 4 GND_3/8 7 USB30_TX1-_R
47K_4 USB30_TX1+_R 5 4 7 6 USB30_TX1+_R
5 6
*RClamp0524P
5
BC_CEN 2
4 USB_BC_EN
1
<24> USB_CHG_EN
3
U16
TC7SH08FU U14
Battery Status, EC GPO control it. 1 6 USBPWR1
USBP0-_R 2 GND 6 5 USBP0-_R
> Hi: S0 and S3~S5 Battery over 30% USBP0+_R 3 2 5 4 USBP0+_R
> Lo: S3~S5/ Battery under 30% R274 *0/J_4 3 4
*RClamp0582N
Name USB data State Max Current Apple Device
SDP YES S0~S3 500mA 500mA
CDP YES S0~S3 1500mA 500mA
A DCP,Auto NO S4~S5 1800mA 1800mA A

PROJECT : Z09
3A
USB 3.0
5 4 3 2 1
5 4 3 2 1
EC(KBC) L29 PBY160808T-250Y-N/3A/25ohm_6 +A3VPCU

+3V
C738 C734
30mil 201201117 C762 for EMI suggestion.
0.1u/10V_4 10u/6.3V_6 +3VPCU
+3VPCU E775AGND D15

R618 2.2_6 RB500V-40 C744 C746 C762 S5_ON R630 795@47K_4
1 2 +3VPCU_EC 0.03A(30mils)
4.7u/6.3V_6 0.1u/10V_4 0.1u/10V_4
C743 C735 C745 C747 C748 C752
115
102
20120217 Change R630 from10k to 47k for S5 current reduce..
19
46
76
88
4
4.7u/6.3V_6 0.1u/10V_4 *.1u/16V_4 0.1u/10V_4 *.1u/16V_4 0.1u/10V_4 U36
AVCC
VDD
VCC1
VCC2
VCC3
VCC4
VCC5
E775AGND C733 10u/6.3V_6 ICMNT
D D
CLK_PCI_EC
C737 0.01u/16V_4
3 97
<8,19,20> LPC_LFRAME# LFRAME GPIO90/AD0 TEMP_MBAT <31>
126 98
<8,19,20> LPC_LAD0 127 LAD0 GPIO91/AD1 99 WAKE_SRC_1 <20>
R617 A/D
<8,19,20> LPC_LAD1 LAD1 GPIO92/AD2 WAKE_SRC_2 <17>
128 100 ICMNT_R
<8,19,20> LPC_LAD2 LAD2 GPIO93/AD3
*22_4 1 R615 *SHORT_4 ICMNT
<8,19,20> LPC_LAD3 LAD3 ICMNT <31>
2
<9> CLK_PCI_EC LCLK 101 EC_DRAMRST_CNTRL
8 GPIO94/DA0 105 EC_DRAMRST_CNTRL <4> 20120220 Add KB backlight EN function.
<7,19> CLKRUN# GPIO11/CLKRUN D/A GPI95/DA1 KEY_BL_EN <19>
C739 106
GPI96/DA2 WK_GPIO27 <10>
*10p/50V_4 121
<10> SIO_A20GATE GPIO85/GA20
122
<10> SIO_RCIN# KBRST/GPIO86 64
<10> SIO_EXT_SCI#
29
ECSCI/GPIO54 LPC
GPIO01/TB2
GPIO02
79
95
ACIN <31>
SUSACK# <7> SM BUS PU(KBC) +3VPCU
GPIO03 NBSWON# <19>
6 96 TP89 MBCLK R629 10K_4
<15> EC_FPBACK# GPIO24/LDRQ GPIO04 108 20120217 Change SUSWRAN# to IOAC_PCIRST#. MBDATA R631 10K_4
GPIO05 IOAC_PCIERST# <7,20>
124 93
<19> AMP_MUTE# GPIO10/LPCPD GPIO06/IOX_DOUT/RTS1 LID# <15>
94
GPIO07 SB_ACDC <7,20>
7 114 SM_DRAMRST# 20120119 AddSM_DRAMRST# for deep S3.
<9,17,19,20,25> PLTRST# LREST GPIO16 109 20120104 Add DPWROK for deep S3.
GPIO30 DPWROK <7>
123 15
<20> RF_EN GPIO67/PWUREQ GPIO36/CTS1 dGPU_OPP# <28>
80
GPIO41 VRON <33>
125 17 HWPG +3V_S5
<8,19> SERIRQ SERIRQ GPIO42/SCL3B/TCK 20
GPIO43/SDA3B/TMS GPU_THAL# <28>
9 21
<10> SIO_EXT_SMI# GPIO65/SMI GPIO44/TDI SUSB# <7>
GPIO 24 20120105 Add GPU_TRIP# to NV GPIO8. 2ND_MBCLK R633 10K_4
GPO47/SCL4 25 GPU_TRIP# <28>
2ND_MBDATA R632 10K_4
GPIO50/PSCLK3/TDO D/C# <31>
54 26
<22> MX0 KBSIN0 GPIO51 S5_ON <32,37>
55 27
<22> MX1 KBSIN1 GPIO52/PSDAT3/RDY HDMI_HPD_EC# <16>
56 28 20120105 Add GPU_PWR_ALERT# to GPU_core IC.
<22> MX2 KBSIN2 GPIO53/SDA4 GPU_PWR_ALERT# <38>
C
57 73
<22> MX3 58 KBSIN3 GPIO70 74 SUSC# <7> C
PWROK_EC_uR R628 *SHORT_4
<22> MX4 KBSIN4 GPIO71 PWROK_EC <7>
59 75 RSMRST#_uR R626 *SHORT_4 R609 *SHORT_4
<22> MX5 KBSIN5 GPIO72 PCH_RSMRST# <7> H_PROCHOT# <3,33>
60 82
<22> MX6 KBSIN6 GPIO75/SPI_SCK MAINON <23,34,35,37,39>
3
61 83 TP90
<22> MX7 KBSIN7 GPO76/SHBM 84 Q43
GPIO77 EC_ODD_EJ <21>
53 91
<22> MY0 KBSOUT0/JENK GPIO81 DNBSWON# <7>
52 110 Do not use it TP56 PROCHOT_EC 2
<22> MY1 KBSOUT1/TCK GPO82/IOX_LDSH/TEST
51 112
<22> MY2 KBSOUT2/TMS GPO84/IOX_SCLK/XORTR USBON# <23>
50 107
<22> MY3 KBSOUT3/TDI GPIO97 USB_CHG_MODE <23>
49 KB R613 2N7002K
<22> MY4 KBSOUT4/JEN0
48
<22> MY5
1
47 KBSOUT5/TDO 31 100K_4
<22> MY6 KBSOUT6/RDY GPIO56/TA1 SLP_SUS# <7,11> Q5006 need Replacement at BOT layer.
43 117
<22> MY7 KBSOUT7 GPIO20/TA2/IOX_DIN_DIO SUSON <35>
42 63
<22> MY8 KBSOUT8 GPIO14/TB1 FANSIG <19>
41
<22> MY9 KBSOUT9/SDP_VIS
40 TIMER 32
<22> MY10 KBSOUT10/P80_CLK GPIO15/A_PWM CONTRAST <15>
39 118
<22> MY11 KBSOUT11/P80_DAT GPIO21/B_PWM PCBEEP_EC <19>
38 62
<22> MY12 KBSOUT12/GPIO64 GPIO13/C_PWM PWRLED# <19>
37 65 +3V_S5
<22> MY13 KBSOUT13/GPIO63 GPIO32/D_PWM BATLED0# <19>
36 22
<22> MY14 35 KBSOUT14/GPIO62 GPIO45/E_PWM 16 CPUFAN# <19>
<22> MY15 KBSOUT15/GPIO61/XOR_OUT GPIO40/F_PWM/RI1 SUSLED# <19>
34 81 20120117 Add WLAN_OFF to CN5 pin46 for IOAC.
<22> MY16 GPIO60/KBSOUT16 GPIO66/G_PWM WLAN_OFF <20>
33 66
<22> MY17 GPIO57/KBSOUT17 GPIO33/H_PWM/SOUT1 BATLED1# <19>
R640 R641
*1K_4 *10K_4
MBCLK 70
<31> MBCLK GPIO17/SCL1 <3,4> CPU_DRAMRST#
MBDATA 69 SM_DRAMRST#
<31> MBDATA GPIO22/SDA1
6
<9> 2ND_MBCLK 2ND_MBCLK 67 SMB 113
GPIO73/SCL2 GPIO87/CIRRXM/SIN_CR USB_CHG_EN <23>
<9> 2ND_MBDATA 2ND_MBDATA 68 14
GPIO74/SDA2 GPIO34/SIN1/CIRRXL +0.75V_ON <35>
VGA_CLK 119 IR 23
<28> VGA_CLK GPIO23/SCL3 GPIO46/CIRRXM/TRST IOAC_LANPWR# <20>
VGA_DATA 120 111 PROCHOT_EC
<28> VGA_DATA GPIO31/SDA3 GPO83/SOUT_CR/TRIST
*2N7002DW
B 72 86 PCH_SPI_SO_R R622 33_4 Q46 B
<19> TPCLK GPIO37/PSCLK1 F_SDI/F_SDIO1 PCH_SPI_SO_EC <8>
71 87 PCH_SPI_SI_R R621 33_4
<19> TPDATA PCH_SPI_SI_EC <8>
1
10 GPIO35/PSDAT1 F_SDO/F_SDIO0 90
Reserve for writing ME ROM <8> ME_WR# GPIO26/PSCLK2 PS/2 FIU F_CS0 SPI_CS0#_UR_ME <8>
11 92 PCH_SPI_CLK_R R619 33_4 201201119 Add Q46 for DS3 function.
<20> BT_POWERON GPIO27PSDAT2 F_SCK PCH_SPI_CLK_EC <8>
77 30 TP93
20111129 add 33ohm series resistor and for EC FAE suggestion
<21> ODD_POWER GPIO00/32KCLKIN GPIO55/CLKOUT/IOX_DIN_DIO contact to SPI 4M ROM. +3V
R623 *SHORT_4
+1.05V_VTT_EC 12 VCC_POR
85 VCC_POR# R624 47K/F_4 +3VPCU HWPG(KBC)
VCORF
+1.05V_VTT VTT
AGND
GND1
GND2
GND3
GND4
GND5
GND6
<3,10> EC_PECI R625 43_4 EC_PECR_R 13 104 VREF_uR R614 *SHORT_4 +A3VPCU R627
PECI VREF
VTT - the power supply for the PECI signal NPCE885LA0DX 10K_4
5
18
45
78
89
116
103
VCORF_uR 44
PECI - the PECI 3.0 data bus, bidirectional signal. D20 BAS316 HWPG
SM BUS ARRANGEMENT TABLE <36> HWPG_VCCSA
DG0.9 and chklist 0.9 apply one series 43ohm near EC side D17 BAS316
<37> HWPG_1.8V
SM Bus 1 Battery
L28 PBY160808T-250Y-N/3A/25ohm_6 D18 BAS316
<34,36> HWPG_VTT
C749 SM Bus 2 PCH D21 BAS316
<35> HWPG_1.5V
1u/6.3V_4 D19 BAS316
pin14 +VCC_GFX pin13 GFX_PWRGD <32> SYS_HWPG
E775AGND SM Bus 3 VGA
pin22 +3V_D for ATI pin21 dGPU_VRON D16 *BAS316
<7,33> GFX_PWRGD
pin24 +1V for ATI pin23 +VGPU_CORE
pin26 +1.8V_GPU for ATI pin25 +1.5V_GPU SM Bus 4 HDMI
pin28 GPU_RST# pin27 dGPU_PWROK
+3V
RSVD for power on iRST 20120217 reserve iRST function.
A C644 A
*0.1u/10V_4
5
SW1
*SWITCH_1.5 IOAC_PCIERST# 2
4 PCIERST# PCIERST# <20>
NBSWON# 1 2 1
<3,9> PCI_PLTRST#
3 4
5 U38
3
6 *TC7SH08FU
R649 R645
*100K_4 *100K_4
PROJECT : Z09
1A
WPCE791 & FLASH
5 4 3 2 1
1 2 3 4 5 6 7 8
D13 EV@BAS316 +3V_GFX

GF108:N12P Feedback179
+VGPU_CORE
GF117:N13M
+1.5V_GFX D12 EV@BAS316 +3V_GFX
GK107:N13P
For power-down sequence purpose
+3V_NV
U6A +VGPU_CORE
bga908-nvidia-n13p-gs-a1
COMMON
A A
1/19 PCI_EXPRESS
+1.5V_NV
PEX_IOVDD+PEX_IOVDDQ+PEX_PLLVDD >2.2A
AJ11 PEX_WAKE
TP28
PEX_IOVDD AG19 IFPx_IOVDD (1.05V)
+1.05V_GFX
PEGX_RST# AJ12 PEX_RST PEX_IOVDD AG21 C536 EV@1U/6.3V/X7R_4
PEX_IOVDD AG22 C535 EV@1U/6.3V/X7R_4 FAE suggest change to 1uF
PCIE_CLKREQ_PEG# AK12 PEX_CLKREQ PEX_IOVDD AG24
PEX_IOVDD AH21 PEX_VDD (1.05V)
<9> CLK_PCIE_VGAP
AL13 PEX_REFCLK PEX_IOVDD AH25 C518 EV@4.7U/6.3V_6 PLACE NEAR BGA
<9> CLK_PCIE_VGAN
AK13 PEX_REFCLK C591 EV@10U/6.3V_8
C525 EV@10U/6.3V_8
C582 EV@0.22u/10V_4 GRP0C AK14 C547 EV@22U/6.3V_8
<2> GRP0
<2> GRN0
C581 EV@0.22u/10V_4 GRN0C AJ14
PEX_TX0
PEX_TX0 C539 EV@22U/6.3V_8 3300mA All rails must be powered off within 10 ms from the first rail powering off.
AN12 PEX_RX0
<2> GTP0
AM12 AG13
<2> GTN0 PEX_RX0 PEX_IOVDDQ
AG15
+1.05V_GFX NB9M: VGACORE +0.90V (Normal) , +1.09V
PEX_IOVDDQ
C558 EV@0.22u/10V_4 GRP1C AH14 AG16
<2> GRP1
<2> GRN1
C559 EV@0.22u/10V_4 GRN1C AG14
PEX_TX1
PEX_TX1
PEX_IOVDDQ
PEX_IOVDDQ AG18 C533 EV@1U/6.3V/X7R_4 FAE suggest change to 1uF NVVDD Maximum Settling Time
PEX_IOVDDQ AG25 C546 EV@1U/6.3V/X7R_4
AN14 PEX_RX1 PEX_IOVDDQ AH15
<2> GTP1
AM14 PEX_RX1 PEX_IOVDDQ AH18
<2> GTN1
PEX_IOVDDQ AH26 C550 EV@4.7U/6.3V_6 PLACE NEAR BGA
C584 EV@0.22u/10V_4 GRP2C AK15 PEX_TX2 PEX_IOVDDQ AH27 C526 EV@10U/6.3V_8
<2> GRP2
C583 EV@0.22u/10V_4 GRN2C AJ15 PEX_TX2 PEX_IOVDDQ AJ27 C527 EV@10U/6.3V_8
<2> GRN2
PEX_IOVDDQ AK27 C568 EV@22U/6.3V_8 +VGPU_CORE
AP14 PEX_RX2 PEX_IOVDDQ AL27 C548 EV@22U/6.3V_8
<2> GTP2
AP15 PEX_RX2 PEX_IOVDDQ AM28
<2> GTN2
PEX_IOVDDQ AN28
C561 EV@0.22u/10V_4 GRP3C AL16 PEX_TX3
<2> GRP3
C560 EV@0.22u/10V_4 GRN3C AK16 PEX_TX3
<2> GRN3
AN15 PEX_RX3
<2> GTP3
AM15 PEX_RX3
<2> GTN3
C586 EV@0.22u/10V_4 GRP4C AK17 PEX_TX4
<2> GRP4
B C585 EV@0.22u/10V_4 GRN4C AJ17 PEX_TX4 B
<2> GRN4
AN17
GPIO
<2> GTP4 PEX_RX4
AM17 PEX_RX4
<2> GTN4
PLACE NEAR BALLS
C563 EV@0.22u/10V_4 GRP5C AH17
<2> GRP5
C562 EV@0.22u/10V_4 GRN5C AG17
PEX_TX5 210mA
<2> GRN5 PEX_TX5
PEX_PLL_HVDD AH12 +3V_GFX tsNVVDD<= 192us
AP17 PEX_RX5
<2> GTP5
AP18 PEX_RX5 PEX_SVDD_3V3 AG12 C521 EV@0.1U/10V_4
<2> GTN5
C534 EV@4.7U/6.3V_6
C588 EV@0.22u/10V_4 GRP6C AK18 PEX_TX6 C528 EV@4.7U/6.3V_6
<2> GRP6
C587 EV@0.22u/10V_4 GRN6C AJ18 PEX_TX6
<2> GRN6
AN18 PEX_RX6 20110907 del C6219,C6221,L5077,L5059
<2> GTP6
AM18 PEX_RX6
<2> GTN6
C553 EV@0.22u/10V_4 GRP7C AL19
<2> GRP7
<2> GRN7
C554 EV@0.22u/10V_4 GRN7C AK19
PEX_TX7
PEX_TX7
PEX_RST timing
AN20 PEX_RX7
<2> GTP7
AM20 PEX_RX7
<2> GTN7
C590 EV@0.22u/10V_4 GRP8C AK20 PEX_TX8 I/O 3.3V
<2> GRP8
<2> GRN8
VDD_SENSE L4
GPUVCC_SENSE <38>
AP20 PEX_RX8 PEX_RST
<2> GTP8
AP21 PEX_RX8
<2> GTN8
GND_SENSE L5 GPUVSS_SENSE <38>
C564 EV@0.22u/10V_4 GRP9C AH20 PEX_TX9
<2> GRP9
C565 EV@0.22u/10V_4 GRN9C AG20 PEX_TX9
<2> GRN9
Trise >= 1uS Tfail <=500nS
AN21 PEX_RX9
<2> GTP9
AM21 PEX_RX9
<2> GTN9
<2> GRP10
<2> GRN10
3V3AUX_NC P8
C TP27 C
AN23 PEX_RX10
<2> GTP10
AM23 PEX_RX10
<2> GTN10
C569 EV@0.22u/10V_4 GRP11C AL22 PEX_TX11
<2> GRP11
<2> GRN11
AP23 PEX_RX11
<2> GTP11
AP24 PEX_RX11
<2> GTN11
AJ26 PEX_TSTCLK R501 *EV@200_4
<2> GRP12
PEX_TSTCLK_OUT
PEX_TSTCLK_OUT AK26 PEX_TSTCLK# GPU all PWROK +3V_GFX
<2> GRN12
AN24 +3V_S5
<2> GTP12 PEX_RX12
AM24 R178
<2> GTN12 PEX_RX12
R512
150mA
*SHORT_6 EV@10K_4
+1.05V_GFX
C573 EV@0.22u/10V_4 GRP13C AH23 PEX_TX13
<2> GRP13
C574 EV@0.22u/10V_4 GRN13C AG23 PEX_TX13 PEX_PLLVDD AG26 +PEX_PLLVDD C552 EV@4.7U/6.3V/X7R_6
<2> GRN13
C522 EV@1U/6.3V/X7R_4 R182 DGPU_PWROK <10>
AN26 PEX_RX13 C516 EV@0.1U/10V/X7R_4 EV@10K_4
<2> GTP13
3
AM26 PEX_RX13
<2> GTN13
PLACE NEAR BGA
<2> GRP14 EV@10K_4
C576 EV@0.22u/10V_4 GRN14C AJ24 PEX_TX14 TESTMODE AK11 TESTMODE R515 2 Q3
<2> GRN14
EV@2N7002D
AP26 PEX_RX14
<2> GTP14
3
AP27 PEX_RX14
<2> GTN14
1
C577 EV@0.22u/10V_4 GRP15C AL25 PEX_TX15 +1.05V_GFX
2
<2> GRP15
<2> GRN15
AN27 PEX_RX15 PEX_TERMP AP29 PEX_TERMP R507 EV@2.49K/F_4 Q4
<2> GTP15
1
AM27 PEX_RX15 EV@PDTC143TT
<2> GTN15
+3V_GFX
D D
C540 EV@0.1U/10V_4
5
+3V_GFX
<9,17,19,20,24> PLTRST# R511 *SHORT_4 2
4 PEGX_RST#
<9> DGPU_HOLD_RST#
1
R499
+3V_GFX R514 EV@10K/F_4 U29
3
2
EV@MC74VHC1G08DFT2G
PCIE_CLKREQ_PEG# 1 3 EV@100K/F_4
PEG_CLKREQ# <9>
EV@2N7002D Q34 PROJECT :Z09
3A
R497 *EV@0_4
N13P-LP (PCIE I/F) 1/5
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
VMA_DQ[63..0] VMB_DQ[63..0]
<30> VMA_DQ[63..0] <30> VMB_DQ[63..0]
FBA_DBI[7..0] FBC_DBI[7..0]
<30> FBA_DBI[7..0] <30> FBC_DBI[7..0]
FBA_EDC[7..0] FBC_EDC[7..0]
17
<30> FBA_EDC[7..0] <30> FBC_EDC[7..0]
5500mA
A A
U6C
U6B 3/19 FBB
2/19 FBA
VMB_DQ0 G9 FBB_D0
VMA_DQ0 L28 FBA_D0 RSVD E1 R92 EV@10K_4 VMB_DQ1 E9 FBB_D1
VMA_DQ1 M29 FBA_D1 VMB_DQ2 G8 FBB_D2
VMA_DQ2 L29 FBA_D2 VMB_DQ3 F9 FBB_D3
VMA_DQ3 M28 FBA_D3 VMB_DQ4 F11 FBB_D4
VMA_DQ4 N31 FBA_D4 VMB_DQ5 G11 FBB_D5
VMA_DQ5 P29 FBA_D5 FB_DLL_AVDD K27 FB_PLL_AVDD VMB_DQ6 F12 FBB_D6
VMA_DQ6 R29 FBA_D6 VMB_DQ7 G12 FBB_D7
VMA_DQ7 P28 FBA_D7 C488 VMB_DQ8 G6 FBB_D8
VMA_DQ8 J28 FBA_D8 VMB_DQ9 F5 FBB_D9
VMA_DQ9 H29 FBA_D9 EV@0.1U/10V_4 VMB_DQ10 E6 FBB_D10
VMA_DQ10 J29 FBA_D10 VMB_DQ11 F6 FBB_D11
VMA_DQ11 H28 FBA_D11 VMB_DQ12 F4 FBB_D12
VMA_DQ12 G29 FBA_D12 VMB_DQ13 G4 FBB_D13
VMA_DQ13 E31 FBA_D13 VMB_DQ14 E2 FBB_D14
VMA_DQ14 E32 FBA_D14 VMB_DQ15 F3 FBB_D15
VMA_DQ15 F30 FBA_D15 VMB_DQ16 C2 FBB_D16
VMA_DQ16 C34 FBA_D16 VMB_DQ17 D4 FBB_D17
VMA_DQ17 D32 FBA_D17 VMB_DQ18 D3 FBB_D18
VMA_DQ18 B33 FBA_D18 VMB_DQ19 C1 FBB_D19
VMA_DQ19 C33 FBA_D19 VMB_DQ20 B3 FBB_D20
VMA_DQ20 F33 FBA_D20 VMB_DQ21 C4 FBB_D21
VMA_DQ21 F32 FBA_D21 VMB_DQ22 B5 FBB_D22
VMA_DQ22 H33 FBA_D22 VMB_DQ23 C5 FBB_D23
VMA_DQ23 H32 FBA_D23 VMB_DQ24 A11 FBB_D24
VMA_DQ24 P34 FBA_D24 VMB_DQ25 C11 FBB_D25
VMA_DQ25 P32 FBA_D25 VMB_DQ26 D11 FBB_D26
VMA_DQ26 P31 FBA_D26 VMB_DQ27 B11 FBB_D27
VMA_DQ27 P33 FBA_D27 VMB_DQ28 D8 FBB_D28
VMA_DQ28 L31 FBA_D28 VMB_DQ29 A8 FBB_D29
VMA_DQ29 L34 FBA_D29 VMB_DQ30 C8 FBB_D30
B VMA_DQ30 L32 VMB_DQ31 B8 FBC_CMD[31:0] <30> B
FBA_D30 FBB_D31
VMA_DQ31 L33 FBA_CMD[31:0] <30> VMB_DQ32 F24
FBA_D31 FBB_D32
VMA_DQ32 AG28 FBA_D32 VMB_DQ33 G23 FBB_D33 FBB_CMD0 D13 FBC_CMD0
VMA_DQ33 AF29 FBA_D33 FBA_CMD0 U30 FBA_CMD0 VMB_DQ34 E24 FBB_D34 FBB_CMD1 E14 FBC_CMD1
VMA_DQ34 AG29 FBA_D34 FBA_CMD1 T31 FBA_CMD1 VMB_DQ35 G24 FBB_D35 FBB_CMD2 F14 FBC_CMD2
VMA_DQ35 AF28 FBA_D35 FBA_CMD2 U29 FBA_CMD2 VMB_DQ36 D21 FBB_D36 FBB_CMD3 A12 FBC_CMD3
VMA_DQ36 AD30 FBA_D36 FBA_CMD3 R34 FBA_CMD3 VMB_DQ37 E21 FBB_D37 FBB_CMD4 B12 FBC_CMD4
VMA_DQ37 AD29 FBA_D37 FBA_CMD4 R33 FBA_CMD4 VMB_DQ38 G21 FBB_D38 FBB_CMD5 C14 FBC_CMD5
VMA_DQ38 AC29 FBA_D38 FBA_CMD5 U32 FBA_CMD5 VMB_DQ39 F21 FBB_D39 FBB_CMD6 B14 FBC_CMD6
VMA_DQ39 AD28 FBA_D39 FBA_CMD6 U33 FBA_CMD6 VMB_DQ40 G27 FBB_D40 FBB_CMD7 G15 FBC_CMD7
VMA_DQ40 AJ29 FBA_D40 FBA_CMD7 U28 FBA_CMD7 VMB_DQ41 D27 FBB_D41 FBB_CMD8 F15 FBC_CMD8
VMA_DQ41 AK29 FBA_D41 FBA_CMD8 V28 FBA_CMD8 VMB_DQ42 G26 FBB_D42 FBB_CMD9 E15 FBC_CMD9
VMA_DQ42 AJ30 FBA_D42 FBA_CMD9 V29 FBA_CMD9 VMB_DQ43 E27 FBB_D43 FBB_CMD10 D15 FBC_CMD10
VMA_DQ43 AK28 FBA_D43 FBA_CMD10 V30 FBA_CMD10 VMB_DQ44 E29 FBB_D44 FBB_CMD11 A14 FBC_CMD11
VMA_DQ44 AM29 FBA_D44 FBA_CMD11 U34 FBA_CMD11 VMB_DQ45 F29 FBB_D45 FBB_CMD12 D14 FBC_CMD12 GDDR5 Mode H Mapping
VMA_DQ45 AM31 FBA_D45 FBA_CMD12 U31 FBA_CMD12 VMB_DQ46 E30 FBB_D46 FBB_CMD13 A15 FBC_CMD13
VMA_DQ46 AN29 FBA_D46 FBA_CMD13 V34 FBA_CMD13 VMB_DQ47 D30 FBB_D47 FBB_CMD14 B15 FBC_CMD14 < 0-31 > < 32-63 > Memory
VMA_DQ47 AM30 FBA_D47 FBA_CMD14 V33 FBA_CMD14 VMB_DQ48 A32 FBB_D48 FBB_CMD15 C17 FBC_CMD15 CMD0 CMD16 CS*
VMA_DQ48 AN31 FBA_D48 FBA_CMD15 Y32 FBA_CMD15 VMB_DQ49 C31 FBB_D49 FBB_CMD16 D18 FBC_CMD16 CMD1 CMD17 A3_BA3
VMA_DQ49 AN32 FBA_D49 FBA_CMD16 AA31 FBA_CMD16 VMB_DQ50 C32 FBB_D50 FBB_CMD17 E18 FBC_CMD17 CMD2 CMD18 A2_BA0
VMA_DQ50 AP30 FBA_D50 FBA_CMD17 AA29 FBA_CMD17 VMB_DQ51 B32 FBB_D51 FBB_CMD18 F18 FBC_CMD18 CMD3 CMD19 A4_BA2
VMA_DQ51 AP32 FBA_D51 FBA_CMD18 AA28 FBA_CMD18 VMB_DQ52 D29 FBB_D52 FBB_CMD19 A20 FBC_CMD19 CMD4 CMD20 A5_BA1
VMA_DQ52 AM33 FBA_D52 FBA_CMD19 AC34 FBA_CMD19 VMB_DQ53 A29 FBB_D53 FBB_CMD20 B20 FBC_CMD20 CMD5 CMD21 WE*
VMA_DQ53 AL31 FBA_D53 FBA_CMD20 AC33 FBA_CMD20 VMB_DQ54 C29 FBB_D54 FBB_CMD21 C18 FBC_CMD21 CMD6 CMD22 A7_A8
VMA_DQ54 AK33 FBA_D54 FBA_CMD21 AA32 FBA_CMD21 VMB_DQ55 B29 FBB_D55 FBB_CMD22 B18 FBC_CMD22 CMD7 CMD23 A6_A11
VMA_DQ55 AK32 FBA_D55 FBA_CMD22 AA33 FBA_CMD22 VMB_DQ56 B21 FBB_D56 FBB_CMD23 G18 FBC_CMD23 CMD8 CMD24 ABI*
VMA_DQ56 AD34 FBA_D56 FBA_CMD23 Y28 FBA_CMD23 VMB_DQ57 C23 FBB_D57 FBB_CMD24 G17 FBC_CMD24 CMD9 CMD25 A12_RFU
VMA_DQ57 AD32 FBA_D57 FBA_CMD24 Y29 FBA_CMD24 VMB_DQ58 A21 FBB_D58 FBB_CMD25 F17 FBC_CMD25 CMD10 CMD26 A0_A10
VMA_DQ58 AC30 FBA_D58 FBA_CMD25 W31 FBA_CMD25 VMB_DQ59 C21 FBB_D59 FBB_CMD26 D16 FBC_CMD26 CMD11 CMD27 A1_A9
VMA_DQ59 AD33 FBA_D59 FBA_CMD26 Y30 FBA_CMD26 VMB_DQ60 B24 FBB_D60 FBB_CMD27 A18 FBC_CMD27 CMD12 CMD28 RAS*
VMA_DQ60 AF31 FBA_D60 FBA_CMD27 AA34 FBA_CMD27 VMB_DQ61 C24 FBB_D61 FBB_CMD28 D17 FBC_CMD28 CMD13 CMD29 RST*
VMA_DQ61 AG34 FBA_D61 FBA_CMD28 Y31 FBA_CMD28 VMB_DQ62 B26 FBB_D62 FBB_CMD29 A17 FBC_CMD29 CMD14 CMD30 CKE*
VMA_DQ62 AG32 FBA_D62 FBA_CMD29 Y34 FBA_CMD29 VMB_DQ63 C26 FBB_D63 FBB_CMD30 B17 FBC_CMD30 CMD15 CMD31 CAS*
VMA_DQ63 AG33 FBA_D63 FBA_CMD30 Y33 FBA_CMD30 FBB_CMD31 E17 FBC_CMD31
FBA_CMD31 V31 FBA_CMD31
FBC_DBI0 E11 FBB_DQM0 FBB_CMD_RFU0 C12
TP58
FBA_DBI0 P30 FBA_DQM0 FBA_CMD_RFU0 R32 TP62 FBC_DBI1 E3 FBB_DQM1 FBB_CMD_RFU1 C20 TP87
FBA_DBI1 F31 FBA_DQM1 FBA_CMD_RFU1 AC32 TP63 FBC_DBI2 A3 FBB_DQM2
C C
FBA_DBI2 F34 FBA_DQM2 FBC_DBI3 C9 FBB_DQM3 POP For Debug only
FBA_DBI3 M32 FBA_DQM3 POP For Debug only FBC_DBI4 F23 FBB_DQM4
FBA_DBI4 AD31 FBA_DQM4 FBC_DBI5 F27 FBB_DQM5
Place close to ball+1.5V_GFX
FBA_DBI5 AL29 FBA_DQM5
Place close to ball FBC_DBI6 C30 FBB_DQM6
FBA_DBI6 AM32 FBA_DQM6 FBC_DBI7 A24 FBB_DQM7 FBB_DEBUG0 G14 FBB_DEBUG0 R452 *EV@60.4/F_4
FBA_DBI7 AF34 FBA_DQM7 FBA_DEBUG0 R28 FBA_DEBUG0 R468 *EV@60.4/F_4 +1.5V_GFX FBB_DEBUG1 G20 FBB_DEBUG1 R453 *EV@60.4/F_4
FBA_DEBUG1 AC28FBA_DEBUG1 R493 *EV@60.4/F_4
FBC_EDC0 D10 FBB_DQS_WP0
FBA_EDC0 M31 FBA_DQS_WP0 FBC_EDC1 D5 FBB_DQS_WP1
FBA_EDC1 G31 FBA_DQS_WP1 FBC_EDC2 C3 FBB_DQS_WP2 FBB_CLK0 D12 VMC_CLKP0 <30>
FBA_EDC2 E33 FBA_DQS_WP2 FBA_CLK0 R30 VMA_CLKP0 <30> FBC_EDC3 B9 FBB_DQS_WP3 FBB_CLK0 E12 VMC_CLKN0 <30>
FBA_EDC3 M33 FBA_DQS_WP3 FBA_CLK0 R31 VMA_CLKN0 <30> FBC_EDC4 E23 FBB_DQS_WP4 FBB_CLK1 E20 VMC_CLKP1 <30>
FBA_EDC4 AE31 FBA_DQS_WP4 FBA_CLK1 AB31 FBC_EDC5 E28 FBB_DQS_WP5 FBB_CLK1 F20
VMA_CLKP1 <30> VMC_CLKN1 <30>
FBA_EDC5 AK30 FBA_DQS_WP5 FBA_CLK1 AC31 FBC_EDC6 B30 FBB_DQS_WP6
VMA_CLKN1 <30>
FBA_EDC6 AN33 FBA_DQS_WP6 FBC_EDC7 A23 FBB_DQS_WP7
FBA_EDC7 AF33 FBA_DQS_WP7
D9 FBB_DQS_RN0 FBB_WCK01 F8
VMC_WCK01 <30>
M30 FBA_DQS_RN0 FBA_WCK01 K31 VMA_WCK01 <30>
E4 FBB_DQS_RN1 FBB_WCK01 E8 VMC_WCK01# <30>
H30 FBA_DQS_RN1 FBA_WCK01 L30 VMA_WCK01# <30>
B2 FBB_DQS_RN2 FBB_WCK23 A5 VMC_WCK23 <30>
E34 FBA_DQS_RN2 FBA_WCK23 H34 VMA_WCK23 <30>
A9 FBB_DQS_RN3 FBB_WCK23 A6 VMC_WCK23# <30>
M34 FBA_DQS_RN3 FBA_WCK23 J34 D22 FBB_DQS_RN4 FBB_WCK45 D24
VMA_WCK23# <30> VMC_WCK45 <30>
AF30 FBA_DQS_RN4 FBA_WCK45 AG30 VMA_WCK45 <30>
D28 FBB_DQS_RN5 FBB_WCK45 D25 VMC_WCK45# <30>
AK31 FBA_DQS_RN5 FBA_WCK45 AG31 VMA_WCK45# <30>
A30 FBB_DQS_RN6 FBB_WCK67 B27 VMC_WCK67 <30>
AM34 FBA_DQS_RN6 FBA_WCK67 AJ34 B23 FBB_DQS_RN7 FBB_WCK67 C27
VMA_WCK67 <30> VMC_WCK67# <30>
AF32 FBA_DQS_RN7 FBA_WCK67 AK34 VMA_WCK67# <30>
FBB_WCKB01 D6
FBA_WCKB01 J30 FBB_WCKB01 D7
FBA_WCKB01 J31 FBB_WCKB23 C6
FBA_WCKB23 J32 FBB_WCKB23 B6
FBA_WCKB23 J33 FBB_WCKB45 F26
FBA_WCKB45 AH31 FBB_WCKB45 E26
FBA_WCKB45 AJ31 FBB_WCKB67 A26
FBA_WCKB67 AJ32 FBB_WCKB67 A27
FBA_WCKB67 AJ33
30ohm FBB_PLL_AVDD H17 FB_PLL_AVDD
H26 FB_VREF FBA_PLL_AVDD U27 FB_PLL_AVDD L23 EV@BLM18PG300SN1
TP60 +1.05V_GFX
D D
C437 EV@22U/6.3V_8 EV@U_GPU_GB4_128 C453
EV@U_GPU_GB4_128 EV@0.1U/10V_4
C464 EV@0.1U/10V_4
C443 EV@0.1U/10V_4

PROJECT :Z09
3A
N13P-LP (MEMORY I/F) 2/5
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
18
U6M
9/19 IFPEF
U6J ALL PINS NC FOR GF117

6/19 IFPAB
DVI-DL DVI-SL/HDMI DP
IFPAB ONLY: NO STUFF RSET is default ALL PINS NC FOR GF117
Required when external reference is used
IFPA_TXC AN6 220 mA I2CY_SDA I2CY_SDA IFPE_AUX AB4
IFPA_TXC AM6 I2CY_SCL I2CY_SCL IFPE_AUX AB3
R181 *EV@1K/F_4 AJ8 IFPAB_RSET R151 EV@10K_4 AB8 IFPEF_PLLVDD
IFPA_TXD0 AN3 IFPE_L3 AC5

TXC TXC
IFPA_TXD0 AP3 R161 *EV@1K/F_4 AD6 IFPEF_RSET IFPE_L3 AC4
A TXC TXC A
R179 EV@10K_4 AH8 IFPAB_PLLVDD IFPE_L2 AC3
AM5 TXD0 TXD0 AC2
IFPA_TXD1 IFPE_L2
AN5 TXD0 TXD0
IFPA_TXD1
IFPE_L1 AC1
TXD1 TXD1
IFPE_L1 AD1
IFPA_TXD2 AK6 IFPE TXD1 TXD1
IFPA_TXD2 AL6 IFPE_L0 AD3

TXD2 TXD2 AD2
IFPE_L0
TXD2 TXD2
IFPA_TXD3 AH6
IFPA_TXD3 AJ6
IFPB_TXC AH9 HPD_E HPD_E GPIO18 R1

IFPB_TXC AJ9
R177 EV@10K_4 AG8 IFPA_IOVDD

IFPB_TXD4 AP5
AG9 IFPB_IOVDD IFPB_TXD4 AP6
IFPB_TXD5 AL7 R157 EV@10K_4 AC7 IFPE_IOVDD

IFPB_TXD5 AM7 IFPF_AUX AF2
I2CZ_SDA
I2CZ_SCL IFPF_AUX AF3
R153 EV@10K_4 AC8 IFPF_IOVDD
IFPB_TXD6 AM8
IFPB_TXD6 AN8 TXC IFPF_L3 AF1
TXC IFPF_L3 AG1
IFPB_TXD7 AL8 IFPF_L2 AD5

TXD3 TXD0
IFPB_TXD7 AK8 IFPF_L2 AD4
TXD3 TXD0
TXD4 TXD1 IFPF_L1 AF5

IFPF TXD4 TXD1 IFPF_L1 AF4
IFPF_L0 AE4
TXD5 TXD2
B GPIO14 N4 IFPF_L0 AE3 B
TXD5 TXD2
IFPAB
EV@U_GPU_GB4_128
HPD_F GPIO19 P3
EV@U_GPU_GB4_128
U6K
7/19 IFPC
ALL PINS NC FOR GF117
R165 *EV@1K/F_4 AF8 IFPC_RSET U6N

4/19 DACA +3V_GFX
DVI/HDMI DP
220 mA 120 mA GF108/GKx GF117 GF117 GF108/GKx
R487 EV@10K_4 AF7 IFPC_PLLVDD I2CW_SDA IFPC_AUX AG2 R180 EV@10K_4 +DACA_VDD AG10 DACA_VDD I2CA_SCL R4 I2CA_SCL EV@2.2K_4 R155
NC NC
I2CW_SCL IFPC_AUX AG3 I2CA_SDA R5 I2CA_SDA EV@2.2K_4 R160
NC
AP9 DACA_VREF TSEN_VREF
IFPC_L3 AG4 AP8 DACA_RSET DACA_HSYNC AM9

TXC NC NC
IFPC_L3 AG5 DACA_VSYNC AN9
TXC NC
IFPC_L2 AH4
TXD0
IFPC TXD0 IFPC_L2 AH3
NC DACA_RED AK9
TXD1 IFPC_L1 AJ2 DACA_GREEN AL10

NC
TXD1 IFPC_L1 AJ3
DACA_BLUE AL9
NC
IFPC_L0 AJ1
TXD2
IFPC_L0 AK1
TXD2
EV@U_GPU_GB4_128
C (1.05V +/- 3% ) C
R498 EV@10K_4 AF6 IFPC_IOVDD GPIO15 P2
EV@U_GPU_GB4_128
30ohm
+1.05V_GFX L25 EV@BLM18PG300SN1
C524 EV@0.1U/10V_4
U6L C486 EV@22U/6.3V_8 U6O

8/19 IFPD 12/19 XTAL_PLL
ALL PINS NC FOR GF117 180ohm AD8

105mA L27 EV@180ohm/5A AE8
PLLVDD
+1.05V_GFX SP_PLLVDD
R175 *EV@1K/F_4 IFPD_RSET AN2 IFPD_RSET C523 EV@0.1U/10V_4
DVI/HDMI DP C519 EV@0.1U/10V_4 AD7 VID_PLLVDD NC
C510 EV@4.7U/6.3V_6 GF108/GKx GF117

R176 EV@10K_4 AG7 IFPD_PLLVDD I2CX_SDA IFPD_AUX AK2
I2CX_SCL IFPD_AUX AK3 C506 EV@22U/6.3V_8
H1 XTALSSIN XTALOUTBUFF J4
IFPD_L3 AK5
TXC
IFPD_L3 AK4
TXC
R122 H3 XTALIN XTALOUT H2
AL4 EV@10K_4
TXD0 IFPD_L2 EV@10K_4
IFPD TXD0 IFPD_L2 AL3 EV@U_GPU_GB4_128 R454
R109
TXD1 IFPD_L1 AM4 *SHORT_4
TXD1 IFPD_L1 AM3
Y1
D D
IFPD_L0 AM2 XTALI_27M 1 3 XTALO_27M
TXD2
IFPD_L0 AM1 2 4
TXD2
C45
EV@27MHz C54
R174 EV@10K_4 AG6 IFPD_IOVDD GPIO17 M6 EV@10p/50V_4 EV@10p/50V_4
EV@U_GPU_GB4_128
20120201 Change CAP from 27P to 10P.

PROJECT :Z09
3A
N13P-LP (DISPLAY) 3/5
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
20111128 add PU+3V resistor on VGA_CLK and DATA.
+3V_GFX VGA Thermal
19
20120217 Change +3V to +3VPCU.
20120220 Change +3V . Logical Logical Logical Logical N13P-GS N13P-GL
+3V
Strapping Bit3 Strapping Bit2 Strapping Bit1 Strapping Bit0
I2CS_SCL EV@2.2K_4 R476 R547 *EV@0_4
I2CS_SDA EV@2.2K_4 R474
R548 *EV@0_4 ROM_SO N13P-LP FB[1] N13P-LP FB[0] SMB_ALT_ADDR VGA_DEVICE 1001
I2CC_SCL EV@2.2K_4 R142 R527 R516 N13P-GL XCLK_417 N13P-GL FB_0_BAR_SIZE
I2CC_SDA EV@2.2K_4 R145
Q35
EV@10K_4
EV@10K_4
PU to VDD33 PD to GND
I2CB_SCL EV@2.2K_4 R150 I2CS_SCL 1 6 N13P-LP PCI_DEVIDE[5]
4.99K 1000 0000
VGA_CLK <24> ROM_SCLK PCI_DEVIDE[4] SUB_VENDOR PEX_PLL_EN_TERM 1010
I2CB_SDA EV@2.2K_4 R152 N13P-GL SLOT_CLK_CFG
2 10K 1001 0001
ROM_SI RAMCFG[3] RAMCFG[2] RAMCFG[1] RAMCFG[0] xxxx 15K 1010 0010
I2CS_SDA 4 3 STRAP0 USER[3] USER[2] USER[1] USER[0] 1111
U6Q
VGA_DATA <24> 20K 1011 0011
5 STRAP1 3GIO_PADCFG[3] 3GIO_PADCFG[2] 3GIO_PADCFG[1] 3GIO_PADCFG[0] 0110
11/19 MISC1
T4 I2CS_SCL
24.9K 1100 0100
I2CS_SCL
T3 I2CS_SDA STRAP2 PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0] 0011
I2CS_SDA
EV@2N7002DW 30.1K 1101 0101
A R2 I2CC_SCL STRAP3 SOR_EXPOSED[3] SOR_EXPOSED[2] SOR_EXPOSED[1] SOR_EXPOSED[0] 0000 A
I2CC_SCL
R3 I2CC_SDA
+3V_GFX 34.8K 1110 0110
I2CC_SDA
STRAP4 Reserve PCIE_SPEED_ PCI_MAX_SPEED DP_PLL_VDD33V 0001 45.3K 1111 0111
I2CB_SCL R7 I2CB_SCL 20111117 change mose footprint to dual type.
CHANGE_GEN3
VGA_THERMDN K4 THERMDN I2CB_SDA R6 I2CB_SDA
TP48
VGA_THERMDP K3 THERMDP
TP47
VRAM Configuration Table 4.99K/F_4 ==> CS24992FB26
AM10 JTAG_TCK RAMCFG 10K/F_4 ==> CS31002FB26
<22> JTAG_CLK_VT
AP11 JTAG_TMS [3:0] DESCRIPTION Quanta PN(Q buy) Quanta PN(W buy) Vendor PN
<22> JTAG_TMS_VT
JTAG_TDI AM11 JTAG_TDI 15K/F_4 ==> CS31502FB24
TP3 AP12
<22> JTAG_TDO JTAG_TDO
JTAG_TRST# AN11 P6
TP39 JTAG_TRST GPIO0
GPIO1 M3
GPU_VID4
GPU_VID3
<38>
<38>
* 0x1(0001) 1250MHz 2GB(64M*32) Samsung AKG5MWDT505 K4G20325FD-FC04 20K/F_4 ==> CS32002FB29
GPIO2 L6 0x0(0000) 1250MHz 2GB(64M*32) Hynix AKG5MWUTW01 H5GQ2H24MFR-T2C 24.9K/F_4 ==> CS32492FB16
TP49
GPIO3 P5
TP50
GPIO4 P7 0x0(0100) 1250MHz 2GB(64M*32) Hynix AKG5MWUTW10 H5GQ2H24AFR-T2C 30.1K/F_4 ==> CS33012FB18
TP51
GPIO5 L7
GPU_VID1 <38>
GPIO6 M7 1250MHz 2GB(64M*32) Elpida AKG5MGUT400 EDW2032BBBG-50-F 34.8K/F_4 ==> CS33482FB22
GPU_VID2 <38>
GPIO7 N8
TP52
GPIO8 M1 VGA_OVT# LOW active , need external PU. Elpida Need confirmation with NV RVL 35.7K/F_4 ==> CS33572FB13
GPIO9 M2 GPU_ALERT# LOW active , need external PU.
L1 Hynix H5GQ2H24AFR-T2C will build next or MP.
GPIO10 GPIO10_VREF <30> 45.3K/F_4 ==> CS34532FB18 GF108:N12P
GPIO11 M5
GPU_VID0 <38>
GPIO12 N3 VGA_ACIN LOW active , need external PU. Register value GF117:N13M
GPIO13 M4
GPU_VID5 <38>
R8 GPU_DPRSLPVR_R
GPIO16
P4
ROM_SO N13P-LP 10K pull up. GK107:N13P
GPIO20 TP38
GPIO21 P1 R484 ROM_SCLK N13P-LP need 4.99K pull up;
TP41
*SHORT_4
2G:Hynix =4.99k pull down(M-die)
GPU_DPRSLPVR <38> ROM_SI 2G:Hynix =24.9k pull down(A-die)
20111129 add 0ohm at net GPU_DPRSLPVR for NV FAE request. STRAP0 N13P-LP 45.3K pull high
STRAP1 N13P-LP 4.99k pull down
EV@U_GPU_GB4_128
STRAP2 N13P-LP need 20K pull down.
STRAP3 STRAP3 N13P-LP need 4.99K pull down.
B B
STRAP4 STRAP4 N13P-LP need 45.3K pull down for GEN3.
ROM_SI Strap Bit for RAM Mapping N13P-LP DID => 0X0FD3
+3V_GFX +3V_GFX +3V_GFX
+3V_GFX
U6P
13/19 MISC2 N13P-LP N13P-LP
R95 R42 R37 R46 R81 R53 R63 R66 R77
EV@10K/F_4 *EV@4.99K/F_4 EV@10K/F_4 EV@4.99K/F_4 EV@45.3K/F_4 *EV@4.99K/F_4 *EV@4.99K/F_4 *EV@34.8K/F_4 *EV@10K/F_4
ROM_CS H6 ROM_SI STRAP0

ROM_SO STRAP1 STRAP3
ROM_SI H5 ROM_SI ROM_SCLK STRAP2 STRAP4
ROM_SO H7 ROM_SO
STRAP0 J2 STRAP0 ROM_SCLK H4 ROM_SCLK N13P-LP N13P-LP
STRAP1 J7 STRAP1
STRAP2 J6 R43 R38 R47 R80 R54 R64 R67 R78
STRAP3 J5
STRAP2
STRAP3
Hynix EV@4.99K/F_4 *EV@10K/F_4 *EV@34.8K/F_4 *EV@4.99K/F_4 EV@4.99K/F_4 EV@20K/F_4 EV@4.99K/F_4 EV@45.3K/F_4
STRAP4 J3 STRAP4
Strap4 QS smple need PD 45.3K.

20120113 Strap1 NV change to PD 4.99K.
BUFRST L2 R137 EV@10K/F_4
J1 MULTISTRAP_REF_GND CEC L3 R140 *EV@10K/F_4 +3V_GFX

R129 unstuff @ N13P-GS
stuff @ N13P-PL
C
EV@40.2K/F_4
GPIO ASSIGNMENTS C
EV@U_GPU_GB4_128
GPIO I/O ACTIVE USAGE
0 OUT N/A NVVDD VID4

+3V 1 OUT N/A NVVDD VID3
dGPU_OPP# 2 OUT HIGH PANEL BACKLIGHT PWM

R651 *EV@10K_4
GPU_THAL# R644 *EV@10K_4
+3V_GFX 20111117 change mose footprint to dual type. GPU_TRIP# R647 *EV@10K_4 3 OUT HIGH PANEL POWER ENABLE
20111128 change to singal mose because re-allocation GPIO for ADPS.
4 OUT HIGH PANEL BACKLIGHT ENABLE
+3V_GFX +3V_GFX
5 OUT N/A NVVDD VID1
Q26 JTAG_TMS_VT R183 *EV@10K_4 OUT N/A NVVDD VID2
6
2
R451 R450 EV@2N7002D JTAG_TDI R184 *EV@10K_4

EV@10K_4 EV@10K_4 VGA_OVT# R356 EV@10K_4 OUT N/A 3D STEREO
GPU_ALERT# 1 3 GPU_ALERT# R434 EV@10K_4 7
20110907 del R6035. JTAG_TDO R299 *EV@10K_4
8 I/O LOW GPU Overtemp
20120223 add PU resistor for ICT request. I/O LOW GPU ALERT
VGA_ACIN R435 *EV@0_4
GPU_THAL# <24> 9
+3V_GFX JTAG_TRST# R188 EV@10K_4
10 OUT N/A FB Vref Control (not used sDDR3)
<24> dGPU_OPP# JTAG_CLK_VT
C761 R189 *EV@10K_4 OUT N/A NVVDD VID0
11
5
Q27 .1u/10V_4 Q25 IN N/A PWR_Level AC Detect

12
2
EV@2N7002DW EV@2N7002D
VGA_OVT# 1 3 13 OUT N/A NVVDD VID5

GPU_TRIP# <24>
14 IN N/A HPD for IFP AB (not used)
20120106 contact to EC for ADPS.
15 IN N/A HPD for IFP C (HDMI)
4
R383 *EV@0_4
16 OUT N/A MEM_VDD_CTL
201201117 c761 for EMI suggestion. 17 IN N/A HPD for IFP D (not used)
D D
20111128 change Q5044 to dual mose, because NV FAE suggestion prevent backdriver GPIO12, ACIN high DC low. 18 IN N/A HPD for IFP E (TMDS)
19 IN N/A HPD for IFP F (not used)
20 N/A N/A NVGEM Debug GPIO13
21 N/A N/A NVGEM Debug GPIO14

ADDRESS:
98H PROJECT : Z09
3A
N13P-LP (GPIO&STRAPS)4/5
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
NVDD Turbo:40A
+VGPU_CORE U6E
+VGPU_CORE 14/19 NVVDD
NVDD P0:21A U6G
U6D U6I
C482 EV@0.1U/10V_4 AA12 VDD 15/19 FBVDDQ
NVDD EDP:30A A2 GND
16/19 GND_1/2
GND AM25 17/19 GND_2/2
C491 EV@0.1U/10V_4 AA14 VDD AA17 GND GND AN1
C509 EV@0.1U/10V_4 AA16 AA27 AA18 AN10 N19 T28
C490 EV@0.1U/10V_4 AA19
VDD
VDD
+1.5V_GFX
AA30
FBVDDQ
FBVDDQ 1.5V_GFX GDDR5:9A AA20
GND
GND
GND
GND AN13 N2
GND
GND
GND
GND T32
C470 EV@0.1U/10V_4 AA21 AB27 AA22 AN16 N21 T5
C469 EV@0.1U/10V_4 AA23
VDD
VDD C484 EV@0.1U/10V_4 AB33
FBVDDQ
FBVDDQ 1.05V_GFX:3.5A AB12
GND
GND
GND
GND AN19 N23
GND
GND
GND
GND T7
PLACE UNDER BALLS C517 EV@0.1U/10V_4 AB13 VDD C446 EV@0.1U/10V_4 AC27 FBVDDQ AB14 GND GND AN22 N28 GND GND U12
C483 EV@0.1U/10V_4 AB15 VDD C500 EV@0.1U/10V_4 AD27 FBVDDQ AB16 GND GND AN25 N30 GND GND U14
A AB17 VDD C531 EV@0.1U/10V_4 AE27 FBVDDQ AB19 GND GND AN30 N32 GND GND U16 A
C480 EV@4.7U/6.3V_6 AB18 VDD C452 EV@0.1U/10V_4 AF27 FBVDDQ AB2 GND GND AN34 N33 GND GND U19
C514 EV@4.7U/6.3V_6 AB20 VDD PLACE UNDER BALLS C467 EV@0.1U/10V_4 AG27 FBVDDQ AB21 GND GND AN4 N5 GND GND U21
C495 EV@4.7U/6.3V_6 AB22 VDD C445 EV@0.1U/10V_4 B13 FBVDDQ A33 GND GND AN7 N7 GND GND U23
C481 EV@4.7U/6.3V_6 AC12 VDD C449 EV@0.1U/10V_4 B16 FBVDDQ AB23 GND GND AP2 P13 GND GND V12
C502 EV@4.7U/6.3V_6 AC14 VDD B19 FBVDDQ AB28 GND GND AP33 P15 GND GND V14
C487 EV@4.7U/6.3V_6 AC16 VDD C454 EV@1U/10V_6 E13 FBVDDQ AB30 GND GND B1 P17 GND GND V16
C511 EV@4.7U/6.3V_6 AC19 VDD PLACE UNDER BALLS C477 EV@1U/10V_6 E16 FBVDDQ AB32 GND GND B10 P18 GND GND V19
C479 EV@4.7U/6.3V_6 AC21 VDD E19 FBVDDQ AB5 GND GND B22 P20 GND GND V21
C493 EV@4.7U/6.3V_6 AC23 VDD C465 EV@4.7U/6.3V_6 H10 FBVDDQ AB7 GND GND B25 P22 GND GND V23
C468 EV@4.7U/6.3V_6 M12 VDD PLACE UNDER BALLS C542 EV@4.7U/6.3V_6 H11 FBVDDQ AC13 GND GND B28 R12 GND GND W13
M14 VDD H12 FBVDDQ AC15 GND GND B31 R14 GND GND W15
M16 VDD H13 FBVDDQ AC17 GND GND B34 R16 GND GND W17
M19 VDD C462 EV@10U/6.3V_8 H14 FBVDDQ AC18 GND GND B4 R19 GND GND W18
M21 VDD PLACE NEAR BALLS C471 EV@10U/6.3V_8 H15 FBVDDQ AA13 GND GND B7 R21 GND GND W20
M23 VDD C461 EV@10U/6.3V_8 H16 FBVDDQ AC20 GND GND C10 R23 GND GND W22
N13 VDD C455 EV@10U/6.3V_8 H18 FBVDDQ AC22 GND GND C13 T13 GND GND W28
N15 VDD H19 FBVDDQ AE2 GND GND C19 T15 GND GND Y12
P12 VDD H24 FBVDDQ AE5 GND GND D2 T22 GND GND Y23
P14 VDD H8 FBVDDQ AE7 GND GND D31
+VGPU_CORE P16 VDD H9 FBVDDQ AH10 GND GND D33
P19 VDD L27 FBVDDQ AA15 GND GND E10
C503 EV@22U/6.3V_8 P21 VDD M27 FBVDDQ AH13 GND GND E22
C126 EV@22U/6.3V_8 P23 VDD N27 FBVDDQ AH16 GND GND E25
C556 EV@22U/6.3V_8 R13 VDD P27 FBVDDQ AH19 GND GND E5
C485 EV@4.7U/6.3V_6 R15 VDD R27 FBVDDQ AH2 GND GND E7 AG11 GND GND AH11
C478 EV@4.7U/6.3V_6 R17 VDD T27 FBVDDQ AH22 GND GND F28
C496 EV@4.7U/6.3V_6 R18 VDD T30 FBVDDQ AH24 GND GND F7
B C515 EV@4.7U/6.3V_6 R20 VDD T33 FBVDDQ AH28 GND GND G10 B
C494 EV@4.7U/6.3V_6 R22 VDD V27 FBVDDQ AH29 GND GND G13
T12 VDD W27 FBVDDQ AH30 GND GND G16
T14 VDD W30 FBVDDQ AH32 GND GND G19
C463 EV@4.7U/16V_8 T16 VDD W33 FBVDDQ AH33 GND GND G2
C557 EV@4.7U/16V_8 T19 VDD Y27 FBVDDQ AH5 GND GND G22 GND_OPT C16
C555 EV@4.7U/16V_8 T21 VDD AH7 GND GND G25 GND_OPT W32
C489 EV@4.7U/16V_8 T23 VDD AJ7 GND GND G28
C475 EV@4.7U/16V_8 U13 VDD FBVDDQ_PROBE F1 FBVDDQ_SENSE_P AK10 GND GND G3 Optional CMD GNDs (2)
TP91
C466 EV@22U/6.3V_8 U15 VDD AK7 GND GND G30 NC for 4-Lyr cards
C505 EV@47U/4V_8 U17 VDD AL12 GND GND G32
U18 VDD GND_PROBE F2 FBVDDQ_SENSE_N AL14 GND GND G33 EV@U_GPU_GB4_128
TP92
C594 U20 VDD AL15 GND GND G5
U22 AL17 G7 U6H
+
VDD GND GND

V13 VDD FB_CAL_PD_VDDQ J27FB_CAL_PD_VDDQ R456 EV@40.2/F_4 AL18 GND GND K2 10/19 XVDD
+1.5V_GFX
EV@330u/2V_7343 V15 VDD AL2 GND GND K28
V17 VDD AL20 GND GND K30 CONFIGURABLE
V18 VDD FB_CAL_PU_GND H27FB_CAL_PU_GND R455 EV@40.2/F_4 AL21 GND GND K32 POWER
V20 VDD AL23 GND GND K33 CHANNELS
V22 VDD AL24 GND GND K5 XVDD U1
W12 VDD FB_CALTERM_GND H25FB_CALTERM_GND R447 EV@60.4/F_4 AL26 GND GND K7 XVDD U2
W14 VDD AL28 GND GND M13 XVDD U3
W16 VDD PLACE NEAR BALLS AL30 GND GND M15 XVDD U4
W19 VDD EV@U_GPU_GB4_128 AL32 GND GND M17 XVDD U5
Y13 VDD AM13 GND GND M22 XVDD U8
Y15 VDD AM16 GND GND N12
Y17 VDD AM19 GND GND N14
Y18 VDD AM22 GND GND N16 XVDD V1
Y20 VDD XVDD V2
Y22 VDD XVDD V3
C XVDD V4 C
EV@U_GPU_GB4_128 XVDD V5
XVDD V6
EV@U_GPU_GB4_128 XVDD V7
XVDD V8
150mA To be configured as needed on the PCB

XVDD W2
Width : 15mil XVDD W3
W4
XVDD
+3V_GFX XVDD W5
XVDD W7
XVDD W8
1
Q31
R481 2 XVDD Y1
EV@0_6 DGPU_D <39> XVDD Y2
XVDD Y3
*EV@AO3404 XVDD Y4
XVDD Y5
3
3V3MISC XVDD Y6
U6F XVDD Y7
18/19 NC/VDD33 XVDD Y8
C451 EV@0.1U/10V_4 PLACE UNDER BALLS
AC6 NC VDD33 J8 C459 EV@0.1U/10V_4
AJ28 NC VDD33 K8 C456 EV@1U/10V_6 XVDD AA1
AJ4 NC VDD33 L8 C501 EV@4.7U/6.3V_6 PLACE NEAR BALLS XVDD AA2
AJ5 NC VDD33 M8 XVDD AA3
AL11 NC XVDD AA4
C15 NC XVDD AA5
D D19 NC XVDD AA6 D
D20 NC XVDD AA7
D23 NC XVDD AA8
D26 NC +3V_GFX
H31 NC EV@U_GPU_GB4_128
T8 NC C472 EV@0.1U/10V_4 PLACE UNDER BALLS
V32 NC C460 EV@0.1U/10V_4
C473 EV@1U/10V_6
C474 EV@4.7U/6.3V_6 PLACE NEAR BALLS Quanta Computer Inc.
EV@U_GPU_GB4_128
PROJECT : Z09
1.Level 1 Environment-related Substances Should Never be Used. 3A
2.Recycled Resin and Coated Wire should be procured from Green Partners. N13P-LP(POWER&THM)5/5
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
VMA_DQ[63..0]
<26> VMA_DQ[63..0]
<26> FBA_DBI[7..0]
FBA_DBI[7..0] CHANNEL A: 1024MB GDDR5x32
FBA_EDC[7..0]
<26> FBA_EDC[7..0]
<26> VMB_DQ[63..0]
VMB_DQ[63..0]
Channel 0 Channel 0 Channel 1 Channel 1
<26> FBC_DBI[7..0]
FBC_DBI[7..0]
<0-31> LOWER HALF <32-63> <0-31> UPPER HALF <32-63>
FBC_EDC[7..0]
<26> FBC_EDC[7..0]
MF=0 Non-mirrored MF=1 Mirrored MF=0 Non-mirrored MF=1 Mirrored

+1.5V_GFX +1.5V_GFX +1.5V_GFX +1.5V_GFX
U5 U7 U3 U4
VMA_DQ31 M2 B1 VMA_DQ39 M2 B1 VMB_DQ31 M2 B1 VMB_DQ39 M2 B1
VMA_DQ30 M4 DQ31 | DQ7 VDDQ-B1 B3 VMA_DQ38 M4 DQ31 | DQ7 VDDQ-B1 B3 VMB_DQ30 M4 DQ31 | DQ7 VDDQ-B1 B3 VMB_DQ38 M4 DQ31 | DQ7 VDDQ-B1 B3
VMA_DQ29 N2 DQ30 | DQ6 VDDQ-B3 B12 VMA_DQ37 N2 DQ30 | DQ6 VDDQ-B3 B12 VMB_DQ29 N2 DQ30 | DQ6 VDDQ-B3 B12 VMB_DQ37 N2 DQ30 | DQ6 VDDQ-B3 B12
A QD24~31
VMA_DQ28
VMA_DQ27
VMA_DQ26
N4
T2
T4
DQ29 | DQ5
DQ28 | DQ4
DQ27 | DQ3
DQ26 | DQ2
VDDQ-B12
VDDQ-B14
VDDQ-D1
VDDQ-D3
B14
D1
D3
QD32~39 VMA_DQ36
VMA_DQ35
VMA_DQ34
N4
T2
T4
DQ29 | DQ5
DQ28 | DQ4
DQ27 | DQ3
DQ26 | DQ2
VDDQ-B12
VDDQ-B14
VDDQ-D1
VDDQ-D3
B14
D1
D3 QD24~31
VMB_DQ28
VMB_DQ27
VMB_DQ26
N4
T2
T4
DQ29 | DQ5
DQ28 | DQ4
DQ27 | DQ3
DQ26 | DQ2
VDDQ-B12
VDDQ-B14
VDDQ-D1
VDDQ-D3
B14
D1
D3
QD32~39 VMB_DQ36
VMB_DQ35
VMB_DQ34
N4
T2
T4
DQ29 | DQ5
DQ28 | DQ4
DQ27 | DQ3
DQ26 | DQ2
VDDQ-B12
VDDQ-B14
VDDQ-D1
VDDQ-D3
B14
D1
D3 A
VMA_DQ25 U2 D12 VMA_DQ33 U2 D12 VMB_DQ25 U2 D12 VMB_DQ33 U2 D12
VMA_DQ24 U4 DQ25 | DQ1 VDDQ-D12 D14 VMA_DQ32 U4 DQ25 | DQ1 VDDQ-D12 D14 VMB_DQ24 U4 DQ25 | DQ1 VDDQ-D12 D14 VMB_DQ32 U4 DQ25 | DQ1 VDDQ-D12 D14
VMA_DQ23 M13 DQ24 | DQ0 VDDQ-D14 E5 VMA_DQ47 M13 DQ24 | DQ0 VDDQ-D14 E5 VMB_DQ23 M13 DQ24 | DQ0 VDDQ-D14 E5 VMB_DQ47 M13 DQ24 | DQ0 VDDQ-D14 E5
VMA_DQ22 M11 DQ23 | DQ15 VDDQ-E5 E10 VMA_DQ46 M11 DQ23 | DQ15 VDDQ-E5 E10 VMB_DQ22 M11 DQ23 | DQ15 VDDQ-E5 E10 VMB_DQ46 M11 DQ23 | DQ15 VDDQ-E5 E10
VMA_DQ21 N13 DQ22 | DQ14 VDDQ-E10 F1 VMA_DQ45 N13 DQ22 | DQ14 VDDQ-E10 F1 VMB_DQ21 N13 DQ22 | DQ14 VDDQ-E10 F1 VMB_DQ45 N13 DQ22 | DQ14 VDDQ-E10 F1
QD16~23 VMA_DQ20
VMA_DQ19
VMA_DQ18
N11
T13
T11
DQ21 | DQ13
DQ20 | DQ12
DQ19 | DQ11
DQ18 | DQ10
VDDQ-F1
VDDQ-F3
VDDQ-F12
VDDQ-F14
F3
F12
F14
QD40~47 VMA_DQ44
VMA_DQ43
VMA_DQ42
N11
T13
T11
DQ21 | DQ13
DQ20 | DQ12
DQ19 | DQ11
DQ18 | DQ10
VDDQ-F1
VDDQ-F3
VDDQ-F12
VDDQ-F14
F3
F12
F14
QD16~23 VMB_DQ20
VMB_DQ19
VMB_DQ18
N11
T13
T11
DQ21 | DQ13
DQ20 | DQ12
DQ19 | DQ11
DQ18 | DQ10
VDDQ-F1
VDDQ-F3
VDDQ-F12
VDDQ-F14
F3
F12
F14
QD40~47 VMB_DQ44
VMB_DQ43
VMB_DQ42
N11
T13
T11
DQ21 | DQ13
DQ20 | DQ12
DQ19 | DQ11
DQ18 | DQ10
VDDQ-F1
VDDQ-F3
VDDQ-F12
VDDQ-F14
F3
F12
F14
VMA_DQ17 U13 G2 VMA_DQ41 U13 G2 VMB_DQ17 U13 G2 VMB_DQ41 U13 G2
VMA_DQ16 U11 DQ17 | DQ9 VDDQ-G2 G13 VMA_DQ40 U11 DQ17 | DQ9 VDDQ-G2 G13 VMB_DQ16 U11 DQ17 | DQ9 VDDQ-G2 G13 VMB_DQ40 U11 DQ17 | DQ9 VDDQ-G2 G13
VMA_DQ15 F13 DQ16 | DQ8 VDDQ-G13 H3 VMA_DQ55 F13 DQ16 | DQ8 VDDQ-G13 H3 VMB_DQ15 F13 DQ16 | DQ8 VDDQ-G13 H3 VMB_DQ55 F13 DQ16 | DQ8 VDDQ-G13 H3
VMA_DQ14 F11 DQ15 | DQ23 VDDQ-H3 H12 VMA_DQ54 F11 DQ15 | DQ23 VDDQ-H3 H12 VMB_DQ14 F11 DQ15 | DQ23 VDDQ-H3 H12 VMB_DQ54 F11 DQ15 | DQ23 VDDQ-H3 H12
VMA_DQ13 E13 DQ14 | DQ22 VDDQ-H12 K3 VMA_DQ53 E13 DQ14 | DQ22 VDDQ-H12 K3 VMB_DQ13 E13 DQ14 | DQ22 VDDQ-H12 K3 VMB_DQ53 E13 DQ14 | DQ22 VDDQ-H12 K3
QD8~15
VMA_DQ12
VMA_DQ11
VMA_DQ10
E11
B13
B11
DQ13 | DQ21
DQ12 | DQ20
DQ11 | DQ19
DQ10 | DQ18
VDDQ-K3
VDDQ-K12
VDDQ-L2
VDDQ-L13
K12
L2
L13
QD48~55 VMA_DQ52
VMA_DQ51
VMA_DQ50
E11
B13
B11
DQ13 | DQ21
DQ12 | DQ20
DQ11 | DQ19
DQ10 | DQ18
VDDQ-K3
VDDQ-K12
VDDQ-L2
VDDQ-L13
K12
L2
L13
QD8~15 VMB_DQ12
VMB_DQ11
VMB_DQ10
E11
B13
B11
DQ13 | DQ21
DQ12 | DQ20
DQ11 | DQ19
DQ10 | DQ18
VDDQ-K3
VDDQ-K12
VDDQ-L2
VDDQ-L13
K12
L2
L13
QD48~55 VMB_DQ52
VMB_DQ51
VMB_DQ50
E11
B13
B11
DQ13 | DQ21
DQ12 | DQ20
DQ11 | DQ19
DQ10 | DQ18
VDDQ-K3
VDDQ-K12
VDDQ-L2
VDDQ-L13
K12
L2
L13
VMA_DQ9 A13 M1 VMA_DQ49 A13 M1 VMB_DQ9 A13 M1 VMB_DQ49 A13 M1
VMA_DQ8 A11 DQ9 | DQ17 VDDQ-M1 M3 VMA_DQ48 A11 DQ9 | DQ17 VDDQ-M1 M3 VMB_DQ8 A11 DQ9 | DQ17 VDDQ-M1 M3 VMB_DQ48 A11 DQ9 | DQ17 VDDQ-M1 M3
VMA_DQ7 F2 DQ8 | DQ16 VDDQ-M3 M12 VMA_DQ63 F2 DQ8 | DQ16 VDDQ-M3 M12 VMB_DQ7 F2 DQ8 | DQ16 VDDQ-M3 M12 VMB_DQ63 F2 DQ8 | DQ16 VDDQ-M3 M12
VMA_DQ6 F4 DQ7 | DQ31 VDDQ-M12 M14 VMA_DQ62 F4 DQ7 | DQ31 VDDQ-M12 M14 VMB_DQ6 F4 DQ7 | DQ31 VDDQ-M12 M14 VMB_DQ62 F4 DQ7 | DQ31 VDDQ-M12 M14
VMA_DQ5 E2 DQ6 | DQ30 VDDQ-M14 N5 VMA_DQ61 E2 DQ6 | DQ30 VDDQ-M14 N5 VMB_DQ5 E2 DQ6 | DQ30 VDDQ-M14 N5 VMB_DQ61 E2 DQ6 | DQ30 VDDQ-M14 N5
QD0~7 VMA_DQ4
VMA_DQ3
VMA_DQ2
E4
B2
B4
DQ5 | DQ29
DQ4 | DQ28
DQ3 | DQ27
DQ2 | DQ26
VDDQ-N5
VDDQ-N10
VDDQ-P1
VDDQ-P3
N10
P1
P3
QD56~63 VMA_DQ60
VMA_DQ59
VMA_DQ58
E4
B2
B4
DQ5 | DQ29
DQ4 | DQ28
DQ3 | DQ27
DQ2 | DQ26
VDDQ-N5
VDDQ-N10
VDDQ-P1
VDDQ-P3
N10
P1
P3
QD0~7 VMB_DQ4
VMB_DQ3
VMB_DQ2
E4
B2
B4
DQ5 | DQ29
DQ4 | DQ28
DQ3 | DQ27
DQ2 | DQ26
VDDQ-N5
VDDQ-N10
VDDQ-P1
VDDQ-P3
N10
P1
P3
QD56~63 VMB_DQ60
VMB_DQ59
VMB_DQ58
E4
B2
B4
DQ5 | DQ29
DQ4 | DQ28
DQ3 | DQ27
DQ2 | DQ26
VDDQ-N5
VDDQ-N10
VDDQ-P1
VDDQ-P3
N10
P1
P3
VMA_DQ1 A2 P12 VMA_DQ57 A2 P12 VMB_DQ1 A2 P12 VMB_DQ57 A2 P12
VMA_DQ0 A4 DQ1 | DQ25 VDDQ-P12 P14 VMA_DQ56 A4 DQ1 | DQ25 VDDQ-P12 P14 VMB_DQ0 A4 DQ1 | DQ25 VDDQ-P12 P14 VMB_DQ56 A4 DQ1 | DQ25 VDDQ-P12 P14
DQ0 | DQ24 VDDQ-P14 T1 DQ0 | DQ24 VDDQ-P14 T1 DQ0 | DQ24 VDDQ-P14 T1 DQ0 | DQ24 VDDQ-P14 T1
VDDQ-T1 T3 VDDQ-T1 T3 VDDQ-T1 T3 VDDQ-T1 T3
VDDQ-T14 VDDQ-T14 VDDQ-T14 VDDQ-T14
J5 J5 J5 J5
<26> FBA_CMD9 K4 RFU/A12/NC C5 <26> FBA_CMD25 K4 RFU/A12/NC C5 <26> FBC_CMD9 K4 RFU/A12/NC C5 <26> FBC_CMD25 K4 RFU/A12/NC C5
<26> FBA_CMD6 A7/A8 | A0/A10 VDD-C5 <26> FBA_CMD26 A7/A8 | A0/A10 VDD-C5 <26> FBC_CMD6 A7/A8 | A0/A10 VDD-C5 <26> FBC_CMD26 A7/A8 | A0/A10 VDD-C5
K5 C10 K5 C10 K5 C10 K5 C10
<26> FBA_CMD7 K10 A6/A11 | A1/A9 VDD-C10 D11 <26> FBA_CMD27 K10 A6/A11 | A1/A9 VDD-C10 D11 <26> FBC_CMD7 K10 A6/A11 | A1/A9 VDD-C10 D11 <26> FBC_CMD27 K10 A6/A11 | A1/A9 VDD-C10 D11
<26> FBA_CMD4 A5/BA1 | A3/BA3 VDD-D11 <26> FBA_CMD17 A5/BA1 | A3/BA3 VDD-D11 <26> FBC_CMD4 A5/BA1 | A3/BA3 VDD-D11 <26> FBC_CMD17 A5/BA1 | A3/BA3 VDD-D11
K11 G1 K11 G1 K11 G1 K11 G1
<26> FBA_CMD3 A4/BA2 | A2/BA0 VDD-G1 <26> FBA_CMD18 A4/BA2 | A2/BA0 VDD-G1 <26> FBC_CMD3 A4/BA2 | A2/BA0 VDD-G1 <26> FBC_CMD18 A4/BA2 | A2/BA0 VDD-G1
H10 G4 H10 G4 H10 G4 H10 G4
<26> FBA_CMD1 H11 A3/BA3 | A5/BA1 VDD-G4 G11 <26> FBA_CMD20 H11 A3/BA3 | A5/BA1 VDD-G4 G11 <26> FBC_CMD1 H11 A3/BA3 | A5/BA1 VDD-G4 G11 <26> FBC_CMD20 H11 A3/BA3 | A5/BA1 VDD-G4 G11
<26> FBA_CMD2 A2 /BA0 | A4/BA2 VDD-G11 <26> FBA_CMD19 A2 /BA0 | A4/BA2 VDD-G11 <26> FBC_CMD2 A2 /BA0 | A4/BA2 VDD-G11 <26> FBC_CMD19 A2 /BA0 | A4/BA2 VDD-G11
H5 G14 H5 G14 H5 G14 H5 G14
<26> FBA_CMD11 H4 A1/A9 | A6/A11 VDD-G14 L1 <26> FBA_CMD23 H4 A1/A9 | A6/A11 VDD-G14 L1 <26> FBC_CMD11 H4 A1/A9 | A6/A11 VDD-G14 L1 <26> FBC_CMD23 H4 A1/A9 | A6/A11 VDD-G14 L1
<26> FBA_CMD10 A0/A10 | A7/A8 VDD-L1 L4 <26> FBA_CMD22 A0/A10 | A7/A8 VDD-L1 L4 <26> FBC_CMD10 A0/A10 | A7/A8 VDD-L1 L4 <26> FBC_CMD22 A0/A10 | A7/A8 VDD-L1 L4
VDD-L4 L11 VDD-L4 L11 VDD-L4 L11 VDD-L4 L11
VDD-L11 L14 VDD-L11 L14 VDD-L11 L14 VDD-L11 L14
D4 VDD-L14 P11 D4 VDD-L14 P11 D4 VDD-L14 P11 D4 VDD-L14 P11
B <26> VMA_WCK01 D5 WCK01 | WCK23 VDD-P11 R5 <26> VMA_WCK67 D5 WCK01 | WCK23 VDD-P11 R5 <26> VMC_WCK01 D5 WCK01 | WCK23 VDD-P11 R5 <26> VMC_WCK67 D5 WCK01 | WCK23 VDD-P11 R5 B
<26> VMA_WCK01# WCK01# | WCK23# VDD-R5 <26> VMA_WCK67# WCK01# | WCK23# VDD-R5 <26> VMC_WCK01# WCK01# | WCK23# VDD-R5 <26> VMC_WCK67# WCK01# | WCK23# VDD-R5
R10 R10 R10 R10
P4 VDD-R10 P4 VDD-R10 P4 VDD-R10 P4 VDD-R10
<26> VMA_WCK23 P5 WCK23 | WCK01 <26> VMA_WCK45 P5 WCK23 | WCK01 <26> VMC_WCK23 P5 WCK23 | WCK01 <26> VMC_WCK45 P5 WCK23 | WCK01
<26> VMA_WCK23# WCK23# | WCK01# <26> VMA_WCK45# WCK23# | WCK01# <26> VMC_WCK23# WCK23# | WCK01# <26> VMC_WCK45# WCK23# | WCK01#
A1 A1 A1 A1
FBA_EDC3 R2 VSSQ-A1 A3 FBA_EDC4 R2 VSSQ-A1 A3 FBC_EDC3 R2 VSSQ-A1 A3 FBC_EDC4 R2 VSSQ-A1 A3
FBA_EDC2 R13 EDC3 | EDC0 VSSQ-A3 A12 FBA_EDC5 R13 EDC3 | EDC0 VSSQ-A3 A12 FBC_EDC2 R13 EDC3 | EDC0 VSSQ-A3 A12 FBC_EDC5 R13 EDC3 | EDC0 VSSQ-A3 A12
FBA_EDC1 C13 EDC2 | EDC1 VSSQ-A12 A14 FBA_EDC6 C13 EDC2 | EDC1 VSSQ-A12 A14 FBC_EDC1 C13 EDC2 | EDC1 VSSQ-A12 A14 FBC_EDC6 C13 EDC2 | EDC1 VSSQ-A12 A14
FBA_EDC0 C2 EDC1 | EDC2 VSSQ-A14 C1 FBA_EDC7 C2 EDC1 | EDC2 VSSQ-A14 C1 FBC_EDC0 C2 EDC1 | EDC2 VSSQ-A14 C1 FBC_EDC7 C2 EDC1 | EDC2 VSSQ-A14 C1
EDC0 | EDC3 VSSQ-C1 C3 EDC0 | EDC3 VSSQ-C1 C3 EDC0 | EDC3 VSSQ-C1 C3 EDC0 | EDC3 VSSQ-C1 C3
FBA_DBI3 P2 VSSQ-C3 C4 FBA_DBI4 P2 VSSQ-C3 C4 FBC_DBI3 P2 VSSQ-C3 C4 FBC_DBI4 P2 VSSQ-C3 C4
FBA_DBI2 P13 DBI3# | DBI0# VSSQ-C4 C11 FBA_DBI5 P13 DBI3# | DBI0# VSSQ-C4 C11 FBC_DBI2 P13 DBI3# | DBI0# VSSQ-C4 C11 FBC_DBI5 P13 DBI3# | DBI0# VSSQ-C4 C11
FBA_DBI1 D13 DBI2 #| DBI1# VSSQ-C11 C12 FBA_DBI6 D13 DBI2 #| DBI1# VSSQ-C11 C12 FBC_DBI1 D13 DBI2 #| DBI1# VSSQ-C11 C12 FBC_DBI6 D13 DBI2 #| DBI1# VSSQ-C11 C12
FBA_DBI0 D2 DBI1# | DBI2# VSSQ-C12 C14 FBA_DBI7 D2 DBI1# | DBI2# VSSQ-C12 C14 FBC_DBI0 D2 DBI1# | DBI2# VSSQ-C12 C14 FBC_DBI7 D2 DBI1# | DBI2# VSSQ-C12 C14
DBI0# | DBI3# VSSQ-C14 E1 DBI0# | DBI3# VSSQ-C14 E1 DBI0# | DBI3# VSSQ-C14 E1 DBI0# | DBI3# VSSQ-C14 E1
VSSQ-E1 E3 VSSQ-E1 E3 VSSQ-E1 E3 VSSQ-E1 E3
VSSQ-E3 E12 VSSQ-E3 E12 VSSQ-E3 E12 VSSQ-E3 E12
G3 VSSQ-E12 E14 G3 VSSQ-E12 E14 G3 VSSQ-E12 E14 G3 VSSQ-E12 E14
<26> FBA_CMD12 L3 RAS# | CAS# VSSQ-E14 F5 <26> FBA_CMD31 L3 RAS# | CAS# VSSQ-E14 F5 <26> FBC_CMD12 L3 RAS# | CAS# VSSQ-E14 F5 <26> FBC_CMD31 L3 RAS# | CAS# VSSQ-E14 F5
<26> FBA_CMD15 CAS# | RAS# VSSQ-F5 <26> FBA_CMD28 CAS# | RAS# VSSQ-F5 <26> FBC_CMD15 CAS# | RAS# VSSQ-F5 <26> FBC_CMD28 CAS# | RAS# VSSQ-F5
F10 F10 F10 F10
VSSQ-F10 H2 VSSQ-F10 H2 VSSQ-F10 H2 VSSQ-F10 H2
J3 VSSQ-H2 H13 J3 VSSQ-H2 H13 J3 VSSQ-H2 H13 J3 VSSQ-H2 H13
<26> FBA_CMD14 J11 CKE# VSSQ-H13 K2 <26> FBA_CMD30 J11 CKE# VSSQ-H13 K2 <26> FBC_CMD14 J11 CKE# VSSQ-H13 K2 <26> FBC_CMD30 J11 CKE# VSSQ-H13 K2
<26> VMA_CLKN0 J12 CK# VSSQ-K2 K13 <26> VMA_CLKN1 J12 CK# VSSQ-K2 K13 <26> VMC_CLKN0 J12 CK# VSSQ-K2 K13 <26> VMC_CLKN1 J12 CK# VSSQ-K2 K13
<26> VMA_CLKP0 CK VSSQ-K13 M5 <26> VMA_CLKP1 CK VSSQ-K13 M5 <26> VMC_CLKP0 CK VSSQ-K13 M5 <26> VMC_CLKP1 CK VSSQ-K13 M5
VSSQ-M5 M10 VSSQ-M5 M10 VSSQ-M5 M10 VSSQ-M5 M10
G12 VSSQ-M10 N1 G12 VSSQ-M10 N1 G12 VSSQ-M10 N1 G12 VSSQ-M10 N1
<26> FBA_CMD0 CS# | WE# VSSQ-N1 <26> FBA_CMD21 CS# | WE# VSSQ-N1 <26> FBC_CMD0 CS# | WE# VSSQ-N1 <26> FBC_CMD21 CS# | WE# VSSQ-N1
L12 N3 L12 N3 L12 N3 L12 N3
<26> FBA_CMD5 WE# | CS# VSSQ-N3 N12 <26> FBA_CMD16 WE# | CS# VSSQ-N3 N12 <26> FBC_CMD5 WE# | CS# VSSQ-N3 N12 <26> FBC_CMD16 WE# | CS# VSSQ-N3 N12
VSSQ-N12 N14 VSSQ-N12 N14 VSSQ-N12 N14 VSSQ-N12 N14
R415 EV@120/F_4 J13 VSSQ-N14 R1 R510 EV@120/F_4 J13 VSSQ-N14 R1 R335 EV@120/F_4 J13 VSSQ-N14 R1 R333 EV@120/F_4 J13 VSSQ-N14 R1
R438 EV@1K_4 SEN_A J10 ZQ VSSQ-R1 R3 SEN_A J10 ZQ VSSQ-R1 R3 R323 EV@1K_4 SEN_B J10 ZQ VSSQ-R1 R3 SEN_B J10 ZQ VSSQ-R1 R3
SEN VSSQ-R3 R4 SEN VSSQ-R3 R4 SEN VSSQ-R3 R4 SEN VSSQ-R3 R4
VSSQ-R4 R11 VSSQ-R4 R11 VSSQ-R4 R11 VSSQ-R4 R11
J2 VSSQ-R11 R12 J2 VSSQ-R11 R12 J2 VSSQ-R11 R12 J2 VSSQ-R11 R12
<26> FBA_CMD13 J1 RESET# VSSQ-R12 R14 <26> FBA_CMD29 J1 RESET# VSSQ-R12 R14 <26> FBC_CMD13 J1 RESET# VSSQ-R12 R14 <26> FBC_CMD29 J1 RESET# VSSQ-R12 R14
MF VSSQ-R14 +1.5V_GFX MF VSSQ-R14 MF VSSQ-R14 +1.5V_GFX MF VSSQ-R14
R465 EV@1K_4 U1 R471 EV@1K_4 U1 R328 EV@1K_4 U1 R329 EV@1K_4 U1
VSSQ-V1 U3 VSSQ-V1 U3 VSSQ-V1 U3 VSSQ-V1 U3
A5 VSSQ-V14 A5 VSSQ-V14 A5 VSSQ-V14 A5 VSSQ-V14
U5 Vpp,NC U5 Vpp,NC U5 Vpp,NC U5 Vpp,NC
Vpp,NC1 B5 Vpp,NC1 B5 Vpp,NC1 B5 Vpp,NC1 B5
VREFD_VMA1 A10 VSS-B5 B10 VREFD_VMA2 A10 VSS-B5 B10 VREFD_VMC1 A10 VSS-B5 B10 VREFD_VMC2 A10 VSS-B5 B10
C U10 VREFD1 VSS-B10 D10 U10 VREFD1 VSS-B10 D10 U10 VREFD1 VSS-B10 D10 U10 VREFD1 VSS-B10 D10 C
2 1 VREFD2 VSS-D10 G5 2 1 VREFD2 VSS-D10 G5 2 1 VREFD2 VSS-D10 G5 2 1 VREFD2 VSS-D10 G5
C442 EV@820P/50V_4 VSS-G5 G10 C530 EV@820P/50V_4 VSS-G5 G10 C390 EV@820P/50V_4 VSS-G5 G10 C384 EV@820P/50V_4 VSS-G5 G10
2 1 VSS-G10 H1 2 1 VSS-G10 H1 2 1 VSS-G10 H1 2 1 VSS-G10 H1
C441 EV@820P/50V_4 VSS-H1 H14 C541 EV@820P/50V_4 VSS-H1 H14 C428 EV@820P/50V_4 VSS-H1 H14 C427 EV@820P/50V_4 VSS-H1 H14
VSS-H14 K1 VSS-H14 K1 VSS-H14 K1 VSS-H14 K1
VREFC_VMA1 J14 VSS-K1 K14 VREFC_VMA2 J14 VSS-K1 K14 VREFC_VMC1 J14 VSS-K1 K14 VREFC_VMC2 J14 VSS-K1 K14
2 1 VREFC VSS-K14 L5 2 1 VREFC VSS-K14 L5 2 1 VREFC VSS-K14 L5 2 1 VREFC VSS-K14 L5
C432 EV@820P/50V_4 VSS-L5 L10 C551 EV@820P/50V_4 VSS-L5 L10 C409 EV@820P/50V_4 VSS-L5 L10 C416 EV@820P/50V_4 VSS-L5 L10
VSS-L10 P10 VSS-L10 P10 VSS-L10 P10 VSS-L10 P10
J4 VSS-P10 T5 J4 VSS-P10 T5 J4 VSS-P10 T5 J4 VSS-P10 T5
<26> FBA_CMD8 ABI# VSS-T5 T10 <26> FBA_CMD24 ABI# VSS-T5 T10 <26> FBC_CMD8 ABI# VSS-T5 T10 <26> FBC_CMD24 ABI# VSS-T5 T10
VSS-T10 VSS-T10 VSS-T10 VSS-T10
EV@GDDR5 U5 EV@GDDR5 U7 EV@GDDR5 U3 EV@GDDR5 U4
VREF_VMA3_MOS VREF_VMA3_MOS
VREF_VMA1_MOS VREF_VMA1_MOS
VREF_VMA3_MOS
VREF_VMA1_MOS
2
VMA_CLKP0 VMA_CLKP1
2
R330 R301 R297 R302

R410 R446 R513 R495 R331 EV@931/F_4 R312 EV@931/F_4 R381 EV@931/F_4 R313 EV@931/F_4
3
R417 EV@931/F_4 R442 EV@931/F_4 R509 EV@931/F_4 R485 EV@931/F_4 EV@549/F_4 EV@549/F_4 EV@549/F_4 EV@549/F_4
3
EV@549/F_4 EV@549/F_4 EV@549/F_4 EV@549/F_4
1
R426 R500 Q15 VREFC_VMC1 VREFD_VMC1 VREFC_VMC2 VREFD_VMC2
1
EV@80.6/F_4 EV@80.6/F_4 VREFC_VMA1 VREFD_VMA1 VREFC_VMA2 VREFD_VMA2 Q29 2

GPIO10_VREF <28>
2
GPIO10_VREF <28>
R337 R325 R367 R322
VMA_CLKN0 VMA_CLKN1 R416 R441 R508 R496 EV@2N7002D EV@1.33K/F_4 EV@1.33K/F_4 EV@1.33K/F_4 EV@1.33K/F_4
EV@1.33K/F_4 EV@1.33K/F_4 EV@1.33K/F_4 EV@1.33K/F_4 EV@2N7002D
1
1
VMC_CLKP0 VMC_CLKP1
+1.5V_GFX
D D
FBC_CMD14 R308 EV@10K_4 GDDR5 Mode H Mapping
+1.5V_GFX +1.5V_GFX +1.5V_GFX +1.5V_GFX FBC_CMD30 R309 EV@10K_4
< 0-31 > < 32-63 > Memory R336 R342
+1.5V_GFX C448 EV@1u/6.3V_4 C439 EV@1u/6.3V_4 C438 EV@0.1u/16V_4 FBA_CMD14 R467 EV@10K_4 CMD0 CMD16 CS* EV@80.6/F_4 EV@80.6/F_4
C394 EV@1u/6.3V_4 C401 EV@1u/6.3V_4 C421 EV@1u/6.3V_4 C402 EV@1u/6.3V_4 FBA_CMD30 R473 EV@10K_4 CMD1 CMD17 A3_BA3
C538 EV@1u/6.3V_4 C398 EV@1u/6.3V_4 C422 EV@1u/6.3V_4 C403 EV@1u/6.3V_4 CMD2 CMD18 A2_BA0
C73 VMC_CLKN0 VMC_CLKN1
+
EV@330u/2V_7343 C498 EV@1u/6.3V_4 C543 EV@1u/6.3V_4 C513 EV@1u/6.3V_4 C457 EV@1u/6.3V_4 CKE* is strap pin to set ODT value of memory chip CMD3 CMD19 A4_BA2
C549 EV@0.047u/10V_4 C391 EV@0.047u/10V_4 C388 EV@0.1u/16V_4 C419 EV@0.047u/10V_4 CMD4 CMD20 A5_BA1
C764 EV@0.1u/16V_4 C440 EV@0.047u/10V_4 C377 EV@0.047u/10V_4 C436 EV@0.1u/16V_4 C420 EV@0.047u/10V_4 CMD5 CMD21 WE*
C408 EV@10U/6.3V_6 C413 EV@0.1u/16V_4 C497 EV@0.1u/16V_4 C423 EV@0.1u/16V_4 C544 EV@0.1u/16V_4 FBA_CMD13 R466 EV@10K_4 CMD6 CMD22 A7_A8
C399 EV@10U/6.3V_6 C396 EV@0.1u/16V_4 C386 EV@0.1u/16V_4 C418 *EV@0.1u/16V_4 C458 EV@0.1u/16V_4 FBA_CMD29 R472 EV@10K_4 CMD7 CMD23 A6_A11
C447 EV@10U/6.3V_6 C499 EV@0.1u/16V_4 C435 EV@0.1u/16V_4 C415 *EV@0.1u/16V_4 C450 EV@0.1u/16V_4 CMD8 CMD24 ABI*
C19 EV@0.1u/16V_4 C537 EV@0.1u/16V_4 C504 *EV@0.1u/16V_4 C414 EV@0.1u/16V_4 FBC_CMD13 R318 EV@10K_4 CMD9 CMD25 A12_RFU
201201117 Add C764 for EMI suggestion. FBC_CMD29 R319 EV@10K_4 CMD10 CMD26 A0_A10
CMD11 CMD27 A1_A9 Quanta Computer Inc.
CMD12 CMD28 RAS*
RST PD place @ the end of daisy-chain. CMD13 CMD29 RST* PROJECT : Z09
CMD14 CMD30 CKE*
CMD15 CMD31 CAS* Size Document Number Rev
3A
N13PGV GDDR5x32-VRAM
1 2 3 4 5 6 7 8
5 4 3 2 1
POWER_JACK
dcjk-2dc2003-000111-3p-v 201201117 PC187 For EMI suggestion
201201117 PC204 for EMI suggestion 201201117 PC197 for EMI suggestion PR10
20111102 Change fooptprint VA1 201201119 Add PC205 for EMI suggestion. PQ3 PD3 0.01/F_0612 PQ48
PJ1 PL3 AOL1413 SBR1045SP5-13 VIN AOL1413
1 FBMA-11-201209-800A50T PC201 PC197 1 1 PC187 1
2 VA 0.1u/50V_6 0.1u/50V_6 2 5 3 1 2 0.1u/50V_6 2 5
3 2 3
3 PR17
1
PC1 *SHORT_4
PC86 PR131 24707_ACN PC155
7
6
5
4
4
0.1u/50V_6 220K_4 0.1u/50V_6 PR101
PL2 0.1u/50V_6 PD1 33K/F_4
FBMA-11-201209-800A50T SMAJ20A 24707_ACP
2
D D
PC11 PC9 PR16 PC158
0.1u/50V_6 2200p/50V_6 PC204 1 6 *SHORT_4 2200p/50V_6
PD5 0.1u/50V_6
1N4148WS PR134 2 5 PR135 *SHORT_4 PR97
D/C# <24>
220K_4 10K_4
201201117 PC202 for EMI suggestion recommend 200mA at least. 3 4
3
20120220 remove VA2 plant and PC205/PC202 PR124, PQ25
move PD3 between PQ3 and PR10 for S5 current reduce. IMD2AT108
2
PQ22
201201119 Add PC205 for EMI suggestion. 24707_ACP 2N7002K
1
24707_ACN
PR265
*SHORT_6 3/30 REV:E add PC84 PC82 PC83
0.1u/50V_6 0.1u/50V_6 0.1u/50V_6
+3VPCU 68n/10V_4
PC196 PR116
63.4K/F_4 201201117 PC189 For EMI suggestion
1
PC189 VIN
PR115 PC77 0.1u/50V_6
ACN
ACP
10K/F_4 1u/10V_6
C PR266 +3VPCU 24707_ACDET 6 16 24707_REGN C
*10K_4 PR123 ACDET REGN
100K_4
20120110 add Acpresent to PCH. PD4
24707_VCC 20 RB500V-40
<24> VCC
R653 0_4 PR117 PC195 PC186 PC182
SB_ACDC <31> ACIN
100K_4 0.1u/25V_4 PR118 PC81 2200p/50V_6 4.7u/25V_8
R652 *0_4 20_1206 0.47u/25V_6 17 24707_BST PR113
<7> ACPRESENT BTST
5
*SHORT_6 PC79
47n/50V_6
6
20111102 ADD Switch 201201117 PC197/PC196 for EMI suggestion PQ51

20111117 change to 0402 18 24707_DH 4 AON7410
5 HIDRV
20111129 Remove R5760 ACOK#
19 24707_LX
3
2
1
PHASE PR240
BATT_EN# BATT_EN# <22> PQ50 0.01/F_0612
2N7002DW MBDATA PR114 *SHORT_4 8 PU6 PL13
1
SDA BQ24707A 6.8uH_7X7X2.4

15 24707_DL 1 2 BAT-V
LCDRV
PJ9002 componet pin1 and footprint pin1 is reverse. MBCLK PR112 *SHORT_4 9
SCL
5
PC71 +3VPCU
0.1u/50V_6 PR107 14 PR263
10K_4 PGND *4.7_6
24707_IFAULT# 11 4 PR232 PR233
PC70 IFAULT# PQ49 *SHORT_4
B *SHORT_4 B
100p/50V_4 20111123 del PL9004/PL9005. PR119 PR110 PC72 AON7410
*10K_4 24707_CMPOUT 3 10_6 0.1u/25V_4
3
2
1
CMPOUT 13 24707_SRP 24707_SRP PC170 PC167 PC166
BAT-V SRP PC179 2200p/50V_6 10u/25V_1206 10u/25V_1206
HEADER _BATT 24707_ILIM 10 PC75 *680p/50V_6 24707_SRN
PC203 ILIM 0.1u/25V_4
1
11/22
0.1u/25V_4 PR108
2 PR242 316K/F_4 24707_CMPIN 4 12 24707_SRN
3 BATT_EN# 100_4 CMPIN SRN
4 TEMP_MBAT PR111
IOUT
GND
GND
GND
GND
GND
5 TEMP_MBAT <24>
7.5_6 PC73
6 201201117 PC203 for EMI suggestion 0.1u/25V_4
7 For battery reverse
PR243 PR122 7
21
22
23
24
25
8 1M_4
9 *100K_4
10 +3VPCU
PJ2 PC178 PC173
*47p/50V_6 *47p/50V_6
ErP lot6
PR109 PC78
100K/F_4 0.01u/25V_4
PR256
*0_4 PR258 PR245 20111101 change net name from ICM to ICMNT
100_4 100_4
MBCLK <24> <24> ICMNT ICMNT

C stage must un-stuff PR9023.
A MBDATA <24> A
PU11
REGN MAX voltage 6.5V
1
IP4223-CZ6 PC80
1 6 MBDATA 100p/50V_4
CH1 CH4 V_ILIM=20*(VSRP-VSRN)=20*Ichg*Rsr
2
2 5
VN VP +3VPCU =0.793V for 3.965A current limit
TEMP_MBAT 3 4 MBCLK
CH2 CH3 PROJECT : Z09
Pin10 ILIM=0.793V Size Document Number Rev
Rsr = 0.01ohm Charger(BQ24707A) 3A

5 4 3 2 1
5 4 3 2 1
MAIND SYS_SHDN#
MAIND <5,35,37> SYS_SHDN# <3,37>
Ven=7.23V
<24> SYS_HWPG VIN VIN VL 8223REF VL

+3VPCU
20120216 remove JP6 for C stage.
PC104 PC194
15u/25V_7343 1000p/50V_4 VIN
D VIN D
PR18
10u/6.3V_8
4.7u/6.3V_6
PR40 10_8
1
665K/F_4 20120216 remove JP4 for C stage.
+
PR29
PC7 *0_4 PR19
8223_VIN
PC4
8223_EN
PC6 PC13 1u/6.3V_4 *SHORT_4 PC27 PC28
PC29
2200p/50V_6 PR7 0.1u/25V_4 2200p/50V_6 4.7u/25V_8
*SHORT_4
+5VPCU PR32 PR15
+5VPCU 5 Volt +/- 5% PC192 PR8 PR39 *SHORT_4 *0_4
5
PC5 *100K/F_4 330K/F_4 +3VPCU
TDC : 5.9A 0.1u/50V_6 +3VPCU
5
PC193 4.7u/25V_8
16
17
8
3
PEAK : 7.8A 2200p/50V_6
201201117 PC192~PC194 for EMI suggestion
PQ13
AON7410
3.3 Volt +/- 5%
VREG3
VREG5
VIN
REF
OCP : 9.5A 4 TDC : 6.5A
PQ2 4 SYS_SHDN# 13 14 +3V_SKIP
Width : 240mil AON7410 EN SKIPSEL PEAK : 8.5A
+3V_PG 23 4 +3V_TON OCP : 10A
3
2
1
PGOOD TONSEL PC23
Width : 260mil
1
2
3
+5V_DH 21 10 +3V_DH 0.1u/50V_6
UGATE1 UGATE2
20120216 remove JP1 for C stage. PL1 PC2 PR5 +5V_B 22 9 +3V_B PR42 PL4 20120216 remove JP2 for C stage.
2.2uH_7X7X3 0.1u/50V_6 1/F_6 BOOT1 PU1 BOOT2 1/F_6 2.2uH_7X7X3
+5V_LX 20 RT8223P 11 +3V_LX
PHASE1 PHASE2
+5V_DL 19 12 +3V_DL
5
20120130 for C change.. LGATE1 LGATE2
5
C PR6 24 7 C
ENTRIP1
ENTRIP2
15.4K/F_4 VOUT1 OUT2 PR31
PQ6 +5V_FB 2 5 +3V_FB PR142 6.81K/F_4
GND
GND
ENC
+ PR138 AON7702 4 FB1 FB2 *4.7_6 +
*4.7_6 4
PC8 PC12 PC35
18
25
15
0.1u/50V_6 1 PR1 0.1u/50V_6 220u/6.3V_7343
2
3
*SHORT_4 PQ10 PC95
3
2
1
8223_EN AON7702 *680p/50V_6
PR13 PC90
2
10K/F_4 *680p/50V_6
PR3 PC3 PR20
100K/F_4 0.1u/10V_4 10K/F_4
1
PC85
220u/6.3V_7343
PR30
PR9 127K/F_4
115K/F_4
<19> 8223_EN
20111101 Add 3/5VPCU reset net. 20111103 change footprint becasue wrong.
OCP:10A
PC96 L(ripple current)
2 0.1u/50V_6
OCP:9.5A PD6 +3V_DL =(9-3.3)*3.3/(2.2u*0.5M*9)
1PS302 3 PR151 *SHORT_6 PR2 *SHORT_6 ~1.9A
L(ripple current)
=(9-5)*5/(2.2u*0.4M*9) 1
=2.525A PC97
Iocp=10-(1.9/2)=9.05A
B
0.1u/50V_6 Vth=9.05A*14mOhm=126.7mV B
2 R(Ilim)=(126.7mV*10)/10uA
Iocp=9.5-(2.525/2)=8.24A PD7
Vth=8.24A*14mOhm=115.32mV 1PS302 3 ~126K
R(Ilim)=(115.32mV*10)/10uA PC102 Inductor max current ~9.24A
1 0.1u/50V_6
~115K
Inductor max current ~10A +15V_ALWP
+15V
PR28
22_8
PC103
0.1u/50V_6
VIN +3V_S5 +5V_S5 +15V VIN +5VPCU +5VPCU +3VPCU

+3VPCU
PR159 PR149 PR148 PR150 PR141

5
5
1M_6 22_8 22_8 1M_6 *1M_6
3
S5D 4 MAIND 4 MAIND 4 S5D 2
A PQ5 PQ9 PQ11 A
3
MDV1528Q MDV1528Q MDV1528Q

PQ28
3
2
1
3
2
1
3
2
1
2 AO3404
<24,37> S5_ON
1
2 2 2
+5V_S5 +5V +3V +3V_S5
PR160 PQ29 PQ30 PQ31
1
PQ32 1M_6 2N7002K 2N7002K 2N7002K

DTC144EU PC109
TDC : 3.75A TDC : 2.13A TDC : 4.21A TDC : 0.5A
1
*2.2n/50V_4
PEAK : 5A PEAK : 2.84A PEAK : 5.6A PEAK : 0.65A PROJECT : Z09
Width : 150mil Width : 90mil Width : 160mil Width : 20mil SYSTEM 5V/3V (RT8223M) 3A

5 4 3 2 1
5 4 3 2 1
201201117 PC191 For EMI suggestion
+VCC_CORE 20120222 Un-stuff PR219/PC137. PC139 20120216 remove JP11 for C stage.
20111202 del PC1005/PC1004. 15u/25V_7343
PR221 20111205 add PC1004.
VIN
2.2/F_6
PC165 51650_CBST1
2200p/50V_4
1
PR210 *330p/50V_4
0.1u/50V_6
4.7u/25V_8
0.1u/50V_6
5
1
PC144 +
PC140
*10_4
PC64
PC62
0.22u/25V_6
PC191
2
2
51650_CDH1 4
<5> VCC_SENSE
<5> VSS_SENSE
1
2
3
PQ19 PL9
AON6414AL 0.36uH DCR=1.1mOhm
D D
Parallel 51650_CSW1 1 2
+VCC_CORE
21111207 remove PR1001/PR1004 0ohm. PR209
5
PC172
PR219
*10_4
4
*0.01u/50V_4
*2.2_6
13K/F_4
*SHORT_4
Close to the 51650_CDL1 4 +
330u/2V_7343
CPU side.
0.1u/10V_4
10u/6.3V_8
PC60
PC136
PC135
*2200p/50V_6
1
2
3
PQ18
PC137
AON6780
51650_VREF
PR216
51650_VREF
51650_VREF 51650_CCSP1 +VCC_CORE
PR213
TDC : 16A
47p/50V_4
8.06K/F_4
23.2K/F_4
PR84
200K/F_4 PC66 PEAK : 33A
4.7K/F_4
200K/F_4
69.8K/F_4
*22.6K/F_4
*0.1u/25V_4
OCP : 40A
PR226
PR247
PR102
PR255
PR230
PR227
*0_4
Close to the
VR side. Width : 1320mil
100K/F_4_4250NTC
33n/25V_4
51650_COCP-R
PC162
PR237
PC157
PR83
51650_CCSN1
VCORE Load Line :
*140K/F_4
PR231
20K/F_4
100K/F_4
30.1K/F_4
51650_VREF 2.9mV/A
PR91
PR99
PR96
PR92
PR90
PC68
PR100
75K/F_4
30K/F_4
100K/F_4
+3V_S5 VIN +5V_S5 *0.1u/25V_4
51650_CTHERM
51650_CCOMP
51650_CCSN1
51650_CCSP1
Close with
PR222
10K/F_4
phase1 inductor
0.1u/10V_4
PR88
PR87
PC148
0_6
10_6
20111205 change PC1015 to 33n 25V.
PC76
1u/6.3V_4
14
12
11
10
2.2u/6.3V_4
4.7u/6.3V_6
PC143
C C
CGFB
CVFB
CCOMP
VREF
CTHERM
CCSN3
CCSP3
CCSP2
CCSN2
CCSN1
CCSP1
2
PC145
COCP-R
51650_CF-IMAX 3 37 51650_VBAT
CF-IMAX VBAT
Check pull up resister to +1.05V_VTT +3V +3V_S5 51650_GOCP-R 13 48 51650_V5
1.05V for H_PROCHOT# GOCP-R V5
51650_SLEW 22 43 51650_V5DRV
SLEW V5DRV
20111106 unstuff. 51650_GF-IMAX 24 47 51650_CDH1
GF-IMAX CDH1
1.91K/F_4
1.91K/F_4
*100K/F_4
33 46
PR95
51650_GSKIP# 51650_CBST1
PR249
PR253
PR254
*499/F_4
GSKIP CBST1
15 45 51650_CSW1
V3R3 CSW1
<24> VRON PR261 *SHORT_4 51650_VRON 16 PU9 44 51650_CDL1
VR_ON TPS51650RSLR CDL1
17 41
<3,7> IMVP_PWRGD CPGOOD CDL2
<7,24> GFX_PWRGD PR248 *0_4 23 40
GPGOOD CSW2
21 39 201201117 Add GND on PU9 Pin40.
<3,24> H_PROCHOT# VR_HOT CBST2
<5> VR_SVID_CLK VR_SVID_CLK 18 38
PC175 VCLK CDH2
43p/50V_4 PC177 VR_SVID_ALERT# 19 42
GTHERM
<5> VR_SVID_ALERT# ALERT GCOMP PGND
GPWM1
GPWM2
TPAD10
TPAD11
TPAD12
TPAD13
TPAD14
TPAD15
TPAD16
CPWM3
1u/6.3V_4
GCSN1
GCSN2
GCSP1
GCSP2
TPAD1
TPAD2
TPAD3
TPAD4
TPAD5
TPAD6
TPAD7
TPAD8
TPAD9
GGFB
GVFB
VR_SVID_DATA 20
PAD
<5> VR_SVID_DATA VDIO
26
25
27
28
29
30
31
32
34
35
36
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
51650_GTHERM
51650_GPWM1
51650_GCSN1
51650_GCSP1
PR98
*SHORT_6
+VCC_GFX
B B
PC164
*330p/50V_4
PR211 +3V
*10_4 PC154
0.1u/10V_4
201201117 PC190/PC200 For EMI suggestion
<5> VCC_AXG_SENSE
<5> VSS_AXG_SENSE
Parallel
PC168
*0.01u/50V_4
PR229
2.2/F_6
20120222 Un-stuff PR228/PC151. AXG PC180
15u/25V_7343
100p/50V_4
VIN
21111207 remove PR1043/PR1044 0ohm. PR212 51650_CBST3
5.49K/F_4
*10_4
2200p/50V_4
1
PC150
0.1u/50V_6
4.7u/25V_8
4.7u/25V_8
0.1u/50V_6
0.1u/50V_6
5
PC74
0.22u/25V_6 +
PC163
PC153
PC159
PC190
PC200
Close to the PU5
2
CPU side. 4
1 8 51650_CDH3
PC169
PR103
51650_GSKIP# 2 BST DRVH 7 51650_CSW3
1
2
3
51650_GPWM1 3 SKIP SW 6 PQ23 PL10
PWM VDD +5V_S5
51650_VREF 4 5 AON6414AL 0.36uH DCR=1.1mOhm
12 GND DRVL 9 PC147 1 2
PAD PAD +VCC_GFX
13 10 1u/10V_4
PAD PAD
5
14 11
*2.2_6
4
PAD PAD
PR228
*SHORT_4
17.4K/F_4
51650_VREF +
51650_CDL3 4
330u/2V_7343
+5V_S5 +1.05V_VTT
Close to VR
0.1u/10V_4
10u/6.3V_8
PC61
PC138
PC142
*2200p/50V_6
1
2
3
PQ21
PC151
AON6780
TPS51601DRBR +3V +VCC_GFX
PR264 PR234 TDC : 21.5A
PR252
PR250
PR251
PR223
PR220
130/F_4
*75/F_4
0.1u/10V_4
54.9/F_4
PR93 *0_4
PC176
*0_4
15.8K/F_4 PR224 51650_GCSP1 PEAK : 33A
A 15.8K/F_4
OCP : 35.8A A
28.7K/F_4
PR89
VR_SVID_ALERT#
51650_VRON 51650_GTHERM 51650_CTHERM PC65 Width : 1320mil
VR_SVID_DATA *0.1u/25V_4
PR260 VR_SVID_CLK
PR94 PR85
GFX_CORE Load Line :
27n/16V_4
100K/F_4
100K/F_4_4250NTC 100K/F_4_4250NTC -3.9mV/A for GT2
PC160
100K/F_4_4250NTC
PR86
51650_GCSN1
191K/F_4
PR236
PR238 PC67
*0_4 *0.1u/25V_4 Quanta Computer Inc.
Place NTC close to the Place NTC close to the IV@ for Internal VGA(+VCC_GFX enable)
GFX_CORE Hot-Spot. VCORE Hot-Spot. EV@ for External VGA(+VCC_GFX disable discrete only) PROJECT :Z09
Close to the Close with Size Document Number Rev
3A
VR side. AXG inductor +VCC_CORE/+VGFX (TPS51650)
5 4 3 2 1
5 4 3 2 1
VIN
201201117 PC199 for EMI suggestion
D D
PC199
PC31 PC32 PC33 0.1u/50V_6
+3V +5V_S5 2200p/50V_4 4.7u/25V_8 4.7u/25V_8
20111121 Change
PR24 PR154
100K_4 10_6 +1.05V_VTT
22
21
20
19
18
17
2
51219_DH
PAD
PAD
PAD
PAD
PAD
PAD
PQ12
D1
D1
D1
FDMS3606S
16 11 PR27 PC20
<24,36> HWPG_VTT PGOOD DH 2_6 0.1u/25V_6
51219_EN 14 13 1 G1 PL6 Close to output cap
23,24,35,37,39> MAINON EN BST 0.68uH_7X7X3
PR25 51219_V5 9 PU3 12 51219_SW S1/D2 951219_SW
*SHORT_4 V5 TPS51219RTER SW
51219_MODE 15 10 51219_DL
C MODE DL 8 G2 PR155 C
51219_TRIP 6 8 20120216 remove JP5/9 and power plant +5V_PCH for C stage.
TRIP PGND PR46 +
*100_4 PC45 PC43
S2
S2
S2
COMP
REFIN
GSNS
VSNS
VREF
4.7_6 330u/2V_7343 0.1u/50V_6
+1.05V_PCH+VTT
GND
PC205
7
6
5
PC98
*0.1u/10V_4
PC38
1u/6.3V_4
PR143
1K/F_4
PR153
41.2K/F_4 PC108 *1000p/50V_6
1.05 Volt +/- 2%
TDC : 13.5A
7
VREF=2V PR139 1000p/50V_4
*SHORT_6
PEAK : 18A
51219_REFIN
51219_REF
51219_GSNS
51219_VSNS
20120130 for A2 change.. 201201117 PC108 for EMI suggestion OCP : 20A
Width : 520mil
PC36
0.01u/16V_4 PR47 RDSon 3.5mOhm
+3V_S5 PC18 PR35 10_4 PR156
0.1u/10V_4 *10K/F_4 *SHORT_4
PR152 VCCP_SENSE <5>
10_4
0.01u/25V_4
PR144 *SHORT_4 VSSP_SENSE <5>
1n/50V_4
1n/50V_4
B PR45 B
*SHORT_4
RC filter is for improve
PR140 PR44
Jitter performance.
PC22
PC34
PC37
*11K/F_4 *100_4
OCP=20A
L ripple current
=(19-1.05)*1.5/(0.68u*500k*19)
=2.918A
Vtrip=20-(2.918/2)*3.5mohm
=0.06489V
A Rlimit = 0.06489/10uA*8=51.9Kohm A

PROJECT : Z09
3A
+PCH&VTT (TPS51219)
5 4 3 2 1
5 4 3 2 1
TDC : 0.75A +0.75V_DDR_VTT

PEAK : 1A 20111109 remove PC2002
Width : 40mil 20111116 Add PC2002
PC184 PC185
10u/6.3V_8 10u/6.3V_8
D TDC : 0.38A D
PEAK : 0.5A +SMDDR_VREF
Width : 20mil
Close to IC
Greater than or equal 40mil
PC181
0.22u/10V_4
+5VPCU
+3V 20120209 change power plant from +5V_S5 to +5VPCU.
PC183 PC161 20111109 remove Jump.
22
21
10u/6.3V_8 1u/10V_4
2
PR259
VIN
100K/F_4
PAD
PAD
VTTGND
VLDOIN
VTTREF
VTT
VTTSNS
20 12
<24> HWPG_1.5V PGOOD V5IN
C
PC149 C
2
4.7u/25V_8
PR244 51216_S3 17 14 51216_DRVH
D1
D1
D1
<23,24,34,37,39> MAINON S3 DRVH
*0_4 PR235 PC156
2_6 0.1u/50V_6 PC69 PC152
PR239 51216_S5 16 15 51216_VBST 2200p/50V_4 4.7u/25V_8
<24> SUSON S5 VBST
*SHORT_4 PU10 1 G1 20111109 remove Jump.
TPS51216RUKR
PR257 51216_MODE 19 13 51216_SW S1/D2 9 51216_SW +1.5VSUS
200K/F_4 MODE SW
PL11
PR246 51216_TRIP 18 11 51216_DRVL 8 G2 0.68uH_7X7X3
39.2K/F_4 TRIP DRVL
+1.5V_SUS
VDDQSNS
PR225
26 10 PQ20 4.7_6 1.5 Volt +/- 5%
S2
S2
S2
REFIN
PAD PGND FDMS3606S
GND
TDC : 15A
PAD
PAD
PAD
REF
7
6
5
PC202 PC146
20120130 for A2 change.. VREF=1.8V
+
PC141 PC63
PEAK : 18A
6
25
24
23
7 1000p/50V_4 330u/2V_7343 0.1u/50V_6 OCP : 20A

51216_REF
PR262 *SHORT_6 *1000P/50V_6 Width : 600mil
51216_REFIN
PC174
B 0.1u/10V_4 RDSon=3.5mohm 201201117 PC146 for EMI suggestion B
PR104
10K/F_4 Close to output cap
+1.5VSUS
3
20120130 for A2 change..
PR241 PC171
60.4K/F_4 0.01u/25V_4 MAIND 2
<5,32,37> MAIND
PR106 51216_S3 PR105 51216_S5
<24> +0.75V_ON
*SHORT_4 *0_4 PQ37
AO3404
1
20111101 add
If S3 power reduce then stuff PR2012 else stuff PR2002 +1.5V
OCP=20A
A L ripple current A
=(19-1.5)*1.5/(0.68u*400k*19) S3 S5 +1.5VSUS REF VTT
=5.079A
S0 1 1 ON ON ON
Vtrip=20-(5.079/2)*3.5mohm
=0.06111V
Rlimit=0.06111/10uA*8=48.88Kohm S3 (mainon off) 0 1 ON ON OFF PROJECT : Z09
S4/S5 0 0 OFF OFF OFF 3A
DDR 1.5V(TPS51216)
5 4 3 2 1
5 4 3 2 1
+3V
D +VCCSA D

0.9 Volt +/- 2%
TDC : 3A
PC94 PC92 PC93
PEAK : 4A
0.1u/10V_4 10u/10V_8 10u/10V_8 Width : 120mil
+5V_S5
+VCCSA
PC89
2.2u/6.3V_6
+3V
24
23
22
21
20
19
PC88
0.1u/50V_6 11/21 Change
VIN
VIN
VIN
PGND
PGND
PGND
PR130
*SHORT_6 18 12 51461_BST
PC87 V5DRV BST PL12 20120216 remove JP8 for C stage.
PR132 1u/6.3V_4 0.47uH_7X7X2.4
100K_4 51461_FILT 17 11
V5FILT SW
10u/6.3V_8
10u/6.3V_8
10u/6.3V_8
10u/6.3V_8
10u/6.3V_8
10u/6.3V_8
0.1u/50V_6
C C
16 10 51461_SW
<24> HWPG_VCCSA PGOOD SW
PU7
PR133 *SHORT_4 51461_EN 13 TPS51463 9
<24,34> HWPG_VTT EN SW PR146
PC24
PC39
PC30
PC42
100/F_4
PC106
PC110
PC105
14 8
<5> VCCSA_VID0 VID0 SW
PC10
*0.1u/10V_4 15 7
<5> VCCSA_VID1
MODE
COMP
VID1 SW
SLEW
VOUT
VREF
GND
25
AGND
5
4.99K/F_4
PR11 PR12
51461_MODE
51461_SLEW
51461_VREF
1K_4 1K_4 PR36
*SHORT_4
51461_VOUT
VCCSA_SENSE <5>
PR147
B PR145 PR43 B
*33K/F_4 PC99 *10K/F_4
0.01u/16V_4
PC100
0.22u/10V_4
PR158 *SHORT_6 PC101
3.3n/50V_4
PR157 *SHORT_6
201201117 PR146 change to 365ohm,un-stuff PR36,stuff PR43,stuff PR145, PU7 change to TPS51463.
20120220 PR145 un-stuff,PR145 change to 100,PR43 un-stuff, PR36 short pad.
VID0 VID1 +VCCSA PR145 33kohm

A A
0 0 0.9V PR146 change to 365ohm
0 1 0.85V PR36 nc
1 0 0.775V PR43 10kohm Quanta Computer Inc.
1 1 0.75V PU7 Change to 51463 PROJECT : Z09
default 0.9V 3A
VCCSA(TPS51461)
5 4 3 2 1
5 4 3 2 1
+3VPCU +1.8V
1.8 Volt +/- 5%
PC25 PC26 TDC : 1.54A
+3V 10u/6.3V_8 0.1u/25V_4 +1.8V
PU2 TPS54318RTER PEAK : 2A
16
VIN PH
10 Width : 60mil
PR23 1 11 PL5
D VIN PH 1uH_7X7X3 D
*100K/F_4
2 12
VIN PH PR26
14 13
<24> HWPG_1.8V PWRGD BOOT PR48
15 6 *SHORT_6 PC19 100K/F_4
<23,24,34,35,39> MAINON EN VSNS 0.1u/50V_6
PR21 7 3
*SHORT_4 COMP GND
8 4 54318_VSNS
R1
RT/CLK GND
PAD
PAD
PAD
PAD
PAD
PAD
PR22 PC14 PR50 9 5
*100K/F_4 1000p/50V_4 10K/F_4 SS AGND
PR49
V0=0.8*(R1+R2)/R2
22
21
20
19
18
17
78.7K/F_4 PC17 PC16 PC15
0.1u/25V_4 10u/6.3V_8 10u/6.3V_8
PC107 PR51 PC41 R2
*100p/50V_4 121K/F_4 0.01u/25V_4
PC40
1200p/50V_4
C C
VIN
PD2
DA2J10100L
PR14
1M_6
Thermal protection
1
PQ1
AO3409
2
3
S5_ON 2
<24,32> S5_ON
PQ4 PR4
1
DTC144EUA *SHORT_6
B B
VL VL
SYS_SHDN# <3,32>
201201117 PC198 for EMI suggestion
PR38
200K_6
PR33 PC44 +1.5V
PR34 200K/F_4 0.1u/50V_6 VIN +3V +5V +0.75V_DDR_VTT PC198 +1.8V +15V
3
1.74K/F_4 201201117 PC188 For EMI suggestion .1u/10V_4

8
PR37
10K_6_NTC 2.469V 3
+ 1 2 PC188 PR218 PR208 PR207 PR214 PR205 PR206 PR203
2 0.1u/50V_6 1M_4 22_8 22_8 22_8 22_8 *22_8 1M_4
- PQ8
3
PU4A 2N7002K
4
BA10393F PC21 MAINON_G MAIND

1
0.1u/50V_6 <3,5> MAINON_G MAIND <5,32,35>
3
S5_ON 2
3
PR41
PQ7 200K/F_4 PR217
2N7002K MAINON 2 PQ47 1M_4 2 2 2 2 2 2
DTC144EUA PC133
1
PQ45 PQ44 PQ46 PQ41 PQ43 PQ38 *2200p/50V_4

2N7002K 2N7002K 2N7002K 2N7002K *2N7002K 2N7002K
1
PR215
1
*100K/F_6
A A
LM393_PIN2
5
+ 7
6
-
PU4B
BA10393F Quanta Computer Inc.
PROJECT : Z09
For EC control thermal protection (output 3.3V) Size Document Number Rev
3A
+1.8V/Discharge/Thermal
5 4 3 2 1
5 4 3 2 1
+3V_GFX
default 0.90V
H_VID0
PR73 *EV@10K/F_4
H_VID1
PR72 *EV@10K/F_4
H_VID2
PR67 *EV@10K/F_4
H_VID3
PR68 *EV@10K/F_4
H_VID4
D D
PR69 EV@10K/F_4 20120222 Un-stuff PR195/PC125.
H_VID5 20111123 Change footprint to 4P choke. 20111109 remove Jump.
PR70 EV@10K/F_4 PR175
EV@2.2/F_6 VIN
20111116 adjust strap to 0.09V +3V 51728_VBST2
EV@10K/F_4
EV@10K/F_4
EV@10K/F_4
EV@10K/F_4
*EV@10K/F_4
*EV@10K/F_4
1
EV@2200p/50V_4
EV@0.1u/50V_6
EV@4.7u/25V_8
EV@4.7u/25V_8
PC119 +
PC55
PC123
PC122
2
EV@0.22u/25V_6
PC56
EV@100K/F_4
EV@100K/F_4
*EV@10K/F_4
PC52
EV@200_4
D1
D1
D1
2
51728_DRVH2 EV@15u/25V_7343
PR182
PR181
PR180
PR179
PR178
PR177
+5V_S5 PR65
*EV@10K/F_4 1 G1 PL7
EV@0.24uH_7X7X3 DCR=1.1mOhm
51728_LL2 S1/D2 9 51728_LL2 1 2
PR63
PR61
PR172
PR171
+VGPU_CORE
4
51728_DRVL2 8 G2
PR195
*EV@2200p/50V_4*EV@2.2_6
PC120
EV@27K/F_4
EV@2.2u/10V_6 PC206 +
*SHORT_4
S2
S2
S2
EV@0.1u/10V_4
EV@10u/6.3V_8
<39> VGA_PG
PQ15 *1000p/50V_6
PC54
PC53
EV@FDMS3606S PC124
PC125
26
<28> GPU_DPRSLPVR
7
6
5
EV@330u/2V_7343
V5IN
PR58 EV@*100K/F_4 33 30 51728_DRVH2
PGD DRVH2
PR77
34 29 51728_VBST2
PR74
PR55 EV@2.2K_4 PG VBST2
C C
51728_PCNT 13 28 51728_LL2
PCNT LL2 51728_CSP2
PR59 EV@100K/F_4 12 27 51728_DRVL2
SLP DRVL2
EV@30K/F_4
EV@75K/F_4
PR170 *SHORT_4 51728_EN 35 3 51728_CSP2 PC48
PR76
<10,39> dGPU_VRON EN CSP2 *EV@0.1u/25V_4
<24> GPU_PWR_ALERT# 10 4 51728_CSN2 Close to the
+VGPU_CORE
THAL CSN2
VR side. Countinue current:30A
EV@15n/25V_4
PR189 *SHORT_4 H_VID0 20
PC111
<28> GPU_VID0 VID0
PR190 *SHORT_4 H_VID1 19 21 51728_DRVH1 51728_CSN2 Peak current:40A
<28> GPU_VID1 VID1 DRVH1
PR165
PR191 *SHORT_4 H_VID2 18 22 51728_VBST1 PC49 OCP minimum 48A
<28> GPU_VID2 VID2 VBST1 *EV@0.1u/25V_4
PR192 *SHORT_4 H_VID3 17 23 51728_LL1 Loadline=0mV/A
<28> GPU_VID3 VID3 LL1
PR193 *SHORT_4 H_VID4 16 24 51728_DRVL1 PR75
<28> GPU_VID4 VID4 DRVL1 EV@100K/F_4_3540NTC
PR194 *SHORT_4 H_VID5 15 6 51728_CSP1
<28> GPU_VID5 VID5 CSP1
14 5 51728_CSN1 20120217 Change Resistor value.PR77/PR165/PR76/PR166/PR80/PR81
VID6 PU8 CSN1 +3V
51728_DROOP EV@TPS51728RHAR
PC117 EV@68p/50V_4 25
PGND 20120222 Un-stuff PR120/PC126. 20111109 remove Jump.
39 PR174 PR176 20111123 Change footprint to 4P choke.
DROOP EV@2.2/F_6
*SHORT_4 VIN
PC116 PR167 51728_VBST1
EV@1200p/50V_4 EV@8.2K/F_4 36 51728_TONSEL
B
51728_V5FILT +3V 51728_VREF 40 TONSEL B
EV@2200p/50V_4
EV@0.1u/50V_6
EV@4.7u/25V_8
EV@4.7u/25V_8
VREF
1
31 51728_TRIPSEL PC121
PC58
PC57
PC130
PC129
TRIPSEL
2
EV@0.22u/25V_6 + PC132
PC115 PR57 32 51728_OSRSEL EV@15u/25V_7343
D1
D1
D1
EV@0.22u/10V_6 OSRSEL 51728_DRVH1
*EV@0_4
2
*EV@0_4
PR173 PR66
51728_SLEW 37 *EV@10K/F_4 1 G1 PL8
PR168 PR169 PR60 PR56 EV@309K/F_4 SLEW EV@0.24uH_7X7X3
PR71
*EV@0_4 *EV@0_4 *SHORT_4 51728_LL1 S1/D2 9 51728_LL1 1 2
DCR=1.1mOhm
+VGPU_CORE
9 *SHORT_4
THRM 1
EV@27K/F_4
3
4
PR82 PR54 PU 51728_DRVL1 8 G2
PR201
*EV@2200p/50V_4*EV@2.2_6
51728_TONSEL EV@100K/F_4_3540NTC
EV@11.8K/F_4 38 51728_V5FILT +
PR78
V5FILT
TPAD10
TPAD11
TPAD12
TPAD13
TPAD14
TPAD15
TPAD16
TPAD1
TPAD2
TPAD3
TPAD4
TPAD5
TPAD6
TPAD7
TPAD8
TPAD9
PwPd
IMON
Place NTC close to the *EV@0_4 PQ16 PC207
*EV@0_4
S2
GND
S2
S2
EV@0.1u/10V_4
EV@10u/6.3V_8
GFB
VFB
EV@FDMS3606S PC128
PC59
PC134
GPU Hot-Spot.
20111206 PR3034 and CPC3018 change to AGND, PR3041 change to DGND. *1000p/50V_6 EV@330u/2V_7343
PC126
7
6
5
PC47
PR62
PR64
8
11
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
+VGPU_CORE EV@2.2u/10V_6
PR81
*SHORT_4
51728_CSP1
PR161
*EV@100_4 51728_IMON
EV@75K/F_4
PR162 PC51
PR80
EV@30K/F_4
*SHORT_4 *EV@0.1u/25V_4
<25> GPUVCC_SENSE 51728_VFB PR52 Close to the
A *SHORT_8 VR side. A
EV@15n/25V_4
51728_GFB
PC112
<25> GPUVSS_SENSE
PR163
*SHORT_4 PR53 PC46
PR166
Parallel
PR164 EV@16.9K/F_4 EV@3300p/50V_4 PC50
*EV@100_4 *EV@0.1u/25V_4
51728_CSN1 Quanta Computer Inc.
Close to the PR79
GPU side. PC114 PC113 EV@100K/F_4_3540NTC PROJECT : Z09
EV@1n/50V_4 EV@1n/50V_4 Size Document Number Rev
3A
VGPU Core (TPS51728)
5 4 3 2 1
5 4 3 2 1
D VIN +1.5V_GFX +15V +1.5VSUS D
PR200 PR204 PR199
5
EV@1M_4 EV@22_8 EV@1M_4 TDC : 5.67A
<38> VGA_PG
PR197 *SHORT_4
dGPU_D1 4
PEAK : 7.56A
Width : 240mil
1
2
3
3
PR196 PQ17
*EV@0_4 PR202 EV@AOL1718
2 EV@1M_4 2 2 +1.5V_GFX
<10,38> dGPU_VRON PC131
PQ42 PQ40 *EV@2200p/50V_4
PR198 PQ39 EV@2N7002K EV@2N7002K
1
PC127 EV@100K_4 EV@PDTC143TT
1
EV@1u/10V_4
<29> DGPU_D
C C
+3V
VIN +3V_GFX +15V
PR129 PR137 PR136 TDC : 1.04A
3
PR127
*EV@0_4
EV@1M_4 EV@22_8 EV@1M_4 PEAK : 1.38A
<23,24,34,35,37> MAINON
Width : 50mil
dGPU_D 2
3
PQ14
3
EV@AO3404
PR128
1
PR125 *SHORT_4 2 EV@1M_4 2 2 +3V_GFX
<9> dGPU_PWR_EN PC91
PQ27 PQ26 *EV@2200p/50V_4
PR126 PQ24 EV@2N7002K EV@2N7002K
1
EV@100K_4 EV@PDTC143TT
1
B B
VIN +1.05V_GFX +15V +1.05V_VTT
TDC : 2.33A
5
PR187 PR186 PR183
EV@1M_4 EV@22_8 EV@1M_4 PEAK : 3.1A
Width : 100mil
+1.5V_GFX dGPU_D2 4 PQ36
EV@MDV1528Q
3
3
3
3
2
1
PR185
PR188 *SHORT_4 2 EV@1M_4 2 2
PC118 +1.05V_GFX
PQ35 PQ33 *EV@2200p/50V_4
A PR184 PQ34 EV@2N7002K EV@2N7002K A
1
EV@100K_4 EV@PDTC143TT
1

PROJECT : Z09
3A
GPU_PWR
5 4 3 2 1
5 4 3 2 1
MODEL
CHANGE LIST Z09
Model REV FROM To
10.28 FIRST RELEASED
Z09 1A 1. 20111031 Modify U18 symbol(Add PAD gnd*9).

2. 20111031 Page 19 Add LED/Cardreader con.(only Power and Battery)
3. 20111031 Page 20/21 remove mSATA/Mian HDD re-driver IC.
4. 20111031 Page24 Change U5039 USB power switch power well from +5VPCU to +5V_S5.
5. 20111031 Page 24 Un-staff USB9+/- resistor because it si reserve only debug use.
6. 20111031 Page 11 Add Q18/19 mose for DSW circuit.
7. 201111101 Page 07 Remove LVDS Data/clock.
8. 201111101 Page 03 Add Resistor R182/R185.
9. 201111101 Page 20 stuff R304 for BT power.
10. 201111101 Page 32~40 Power updata circuit.
12. 201111102 Page17 Change R554 from 0ohm to 2.2ohm for Prevent EDS issue.
13. 20111102 del R160
14. 20111102 page7 FDI and DMI reverse.
15. 20111102 page6 R5757 stuff for PGE reverse.
16. 20111102 page6 Ball G48 connect test point.
17. 20111102 update connector list without LVDS/HDMI/Audio/USB3/RJ45/ODD/KB.
18. 20111102 Page 02 Reverse PEG.
19. 20111103 page 25 add pull up 10k R305 to PSI CS#.
20. 20111103 page 9 remove dGPU_PWM_SELECT# change to dGPU_PRW_RN PD.
21. 20111104 page 3 R5332 PU from +1.5VSUS TO +1.5V_CPU becaue leakage issue.
22. 20111104 page 40,41 add memory down.
23. 20111104 page 26~31 change GPU solution from 13P-GV to 13P-PL.
24. 20111104 page 02 change R5459 from 10K to 1K PU.PR1029
D D
25. 20111106 page 32 Un-stuf PR1029.base on CRB.20111107 R5180 un-stuff.
26. 20111107 page 07 R5180 un-stuff. because DRAMPWEGD change to +5V_CPU.
27. 20111107 page 14 unstuff R5347/R362 and stuff Q5010 for Deep S3.
28. 20111107 page 14 remove R5144 PU +1.5VSUS.
28. 20111107 page 20 move debuge port to CN3.
29. 20111107 page 07 R469 change from 10k to 4.99k.
30. 20111108 page08 PU 10k to +3V, becaue no sata LED.
31. 20111108 page15 add feature board con.
32. 20111108 page19 add TPM con.
33. 20111109 page09 VCC core CAP change to.
total : 22uF x 12
tatal : 470u x 3(power side*1)
AXG:
tatal : 470u x 1(power side*1)
34. 20111109 page36 remove PC2002 and JUMP.

35. 20111109 page39 remove JUMP.
36. 20111109 page14 remove XDP.
37. 20111109 page02 add PEG tox16.
38. 20111110 page07 remove R600/R601.
39. 20111110 page08 R411 change power plant to +3V_PCH_ME
40. 20111110 Move R6168 to page04.
41. 20111111 page07 Reverse DMI/FDI to normal.
42. 20111111 page16 R423 change to 56K(Vout=36V,R65 to 10K,
R36 un-stuff,stuff R67/C27 and R67 change to 9.09K (for phas shif mode). R5312
2A 3A
43. 20111111 page07 add 0ohm R5312 on DRB#.
2A 3A
44. 20111111 Remove codec to DB board.
2A 3A
45. 20111111 page20 Remove Feature con and CRT cricuit, add RJ45.
2A 3A
46. 20111114 Update CN25,CN5008,CN5007 footprint .
2A 3A
47. 20111114 Page19 Un-stuff D8/R45.
2A 3A
48. 20111114 Page20 CN17 from 24pin change to 30pin, add TP function and add TPM and Audio connector
2A 3A
49. 20111115 Update CN23 footprint.
2A 3A
50. 20111116 page36 add PC2002.
2A 3A
51. 20111116 page08 Base on EMI request add C2494 22P on PCH BlTCLK and R256/C6495 and Stuff R411.
2A 3A
52. 20111116 page25 EC add GPIO36 dGPU_OVT# to GPU for ADPS,Change net name GPIO87 to USB_CHG_EN,
GPIO97 to USB_CHG_MODE,GPI043 net name change to GPU_THAL#. 2A 3A
53. 20111116 page19 change transfromer from GigaLan to 10/100*2, remove ESD U8/12. 3A 3B
54. 20111116 page08 Change RTC connector and un-stuff Q36,R415,R416,R422,R414. 3A 3B
55. 20111116 page08 Change back RTC connector and stuff Q36,R415,R416,R422,R414. 3A 3B
56. 20111117 page32 BTT_EN# from push button change to short pad and connect to DB board. 3A 3B
57. 20111117 page11 Remove 0ohm short pad,R5051/R5044/R5034/R5149/R5220/R5039/R5042. 3A 3B
58. 20111117 update CN3/Cn18/CN12/CN17/SW2 footprint. 3A 3B
59. 20111117 page24 remove R61112/R61110 no charge option.R5176,del PQ35 change Q48 for dul mose type. 3A 3B
60. 20111117 page09 R5176 change to singal resistor becaue GPIO40~42 GPIO9 for memory down ID. 3A 3B
61. 20111117 change Q5003/Q29/Q16/Q30/Q26/Q41/Q4040/Q5043 footprint to dual type mose Del Q17/Q31/Q27/Q42/Q5041/Q5045. 3A 3B
62. 20111117 page20 Change R256 to L6 for EMI reqeust. 3A 3B
63. 20111118 page17 Change R474 to 100kohm. 3A 3B
64. 20111118 page16 Remove LCD power C21/C12 3A 3B
65. 20111118 page16 Change RTC connector. 3A 3B
66. 20111118 change Q21/Q39 footprint to dual type mose Del Q43/Q40, mose return back to Q26/Q27. 3A 3B
67. 20111118 page09 GPIO40~42,GPIO09 change net name to RAM_ID0~3. 3A 3B
68. 20111121 page08 Change RTC battery back to socket. 3A 3B
69. 20111121 page21 change back transformer to single giga LAN. 3A 3B
70. 20111121 page23 Add screw hole*13. 3A 3B
71. 20111121 page16 change L96 to 10u 0.1A . 3A 3B
72. 20111121 page03 remove R5306/R5311/R5474/R5475 .CX12B900000 3A 3B
73. 20111121 page16 L2 change P/N to CX12B900000. 3A 3B
74. 20111121 page06 add R95 for G48 ball to GND for sandy bridge. 3A 3B
75. 20111121 page03 add Q31 and R182 to 1k/R185 10K. 3A 3B
C C
76. 20111121 page20 change CN8 footprint and update CN9 footprint. 3A 3B
77. 20111121 page23 modify all hole footprint. 3A 3B
78. 20111122 page19 Swap U5103 pin define for layout. 3A 3B
79. 20111122 page20 modify CN6/cn17 pin define, cn17 pin29/30 for TP. 3A 3B
80. 20111122 Update footprint PJ9002. 3A 3B
81. 20111122 page35 add a jump JP6008 at 1.05V. 3A 3B
82. 20111122 Q37 change to P mose and remove Q44 change power plant to +3V_S5.
83. 20111122 page16 L97 Change inductor to 1A for FAE reqeust.
83. 20111122 page08 add net TP_INT# pin at CN17 pin29 to PCH N32 and add Q5005 and R444 for leakage issue..
84. 20111123 page20 CN8 add LPCPD# net to PCH G8.
85. 20111123 change PJ9002 pin define.
86. 20111123 update Hole3/4/10 footprint.
87. 20111123 page39 PL3002/PL3001 change footprint to 4pin.
88. 20111123 page32 Del PL9004/PL9005.
89. 20111123 page23 modify Keyboard Pin define for match matrix.
90. 20111124 midfy CN5008/CN5007 USB footprint.
91. 20111124 page09 modify RAM_ID from GPIO40~42,GPIO09 change to GPIO42,9,10,14.
92. 20111124 page14 DDRIII on board RAM change to 256x16.
93. 20111125 Update Cn11/JDIM1/RJ45 footprint.
94. 20111125 Update KB pin define.
95. 20111128 Update CN5010/CN2/U32~U35 footprint.
96. 20111128 page28 change Q5044 to dual mose and del Q5042, GPIO12 ACIN high DC low prevent backdriver add mose.
add PU +3V resistor R5306/R5308 reserve.
97. 20111128 page08 change net TP_INT# to pin E12 GPIO11 and net name to SMBALERTL, add R444 10K to PCH_ODD_EN not use.
98. 20111128 page19 add R221/C6496 for EMI request and change Cn8 pin9 to LPC_LFRAME#,Pin10,pin12 to GND,Pin11 PCLK_TPM.
99. 20111129 page29 change Q5043 to singal mose and add back Q5045, VGA_OVT# connect to SYS_SHDN# un-stuff,
GPU_ALERT# to EC GPU_THAL, DGPU_OPP# to VGA_ACIN.
100. 20111129 page22 Remove BKT1 and add hole14~16.

101. 20111129 page03 change U5013.3 net to PCI_PLTRST#.
102. 20111129 page09 change U5001 power plant to +3V.
103. 20111129 page21 change path cap power well and del C497/C704/C479/C508.
104. 20111129 page28 add R27 0ohm at net GPU_DPRSLPVR.
105. 20111129 page31remove R5068 becasue double connect GND.
106. 20111129 page24 add R437~R439 SPI series resistor,and SPI net contact to SPI 4M ROM.
107. 20111130 page22 add hole18.
108. 20111130 page18 CN5010 add two GND pin15/16.
108. 20111130 page09 change PCIE_CLKREQ5# PU +3V_S5, PCIE_CLKREQ2# PU +3V.
109. 20111201 page17 change C6108 power from +3V_S5 to +3V_LAN.
110. 20111201 page19 update CN8 footprint.
111. 20111201 Power Update :
a.PL3001 and PL3002 change to 0.24uH inductor.
b.PR3019 and PR3046 change to 26.14kohm.
c.PR3021 and PR3049 change to 29.65kohm.
d.PR3023 and PR3053 change to 76.49kohm.
e.PC3013 and PC3030 change to 15nF.
f.Change PR3040 to 312.5kohm.
g.Change PR3055 to 17kohm.
h.Change PR3031 to 8.2kohm.
i.Change PC3016 to 1200PF.
j.Change PC3015 to 68PF.
k.change PR3011 to 200ohm.
l.Change PR1007 to 13.07khom.
m.Change PR1015 to 23.02kohm.
n.Change PR1022 to 30kohm
o.Change PR1013 to 201.8kohm.
p.Add PR1066 for default test mode.
112. 20111202 Hole18 change Footprint to HG-C256D118P2-V3

113. 20111202 page03 ADD NET DEEPS3_EC .connect to Q15 , Q5050.
114. 20111202 page33 Del PC1004/PC1005 for Power reqeust.
115. 20111205 page19 Change CN8 pin define and add 0ohm R222 on net SERIRQ.
116. 20111205 page33 add back PC1004.
B B
117. 20111206 page38 PR3034 and CPC3018 change to AGND, PR3041 change to DGND.
118. 20111206 page07 add R5193 un-stuff for normal s3 PCIE LAN wake up.
119. 20111207 page33 remove PR1001/PR1004/ PR1043/PR1044 0ohm
120. 20111207 page21 Modify CN12 Pin define following up ZHA.
121. 20111207 page20 CN3 Pin51 to GND.
122. 20111207 page20 change CN13 Pin5/U5006.11 net name BT_POWERON# to BT_POWERON.
123. 20111207 page38 swap PR3042 and PR3041.
124. 20111207 page08 Change Y5000 footprint.
125. 20111207 page22 modify hole8 footprint and add net BATT_EN at Pin2.
126. 20111207 page22 modify hole8 footprint and change net BATT_EN to Pin3.
1. 20120104 page11 VCCDSW3_3 change power plant to +3VPCU.

1B
2. 20120104 page07 Change DPWEOK from REREST# to EC.
3. 20120109 page08 change Q33 footprint.
4. 20120105 page11 +3V_VCCM_SPI change to +3V_S5 and reserve +3V.
5. 20120105 page20 Q14/Q9 change transistor direct and power plant to +3V_S5.
6. 20120111 page15 Change C407 to 50V CAP and un-stuff C410 and change C406 to 50V 0805 size.
7. 20120112 page04 Add C753~C758 1uf CAP on +0.75V_DDR_VTT.
8. 20120113 page22 Change KB con footprint.
9. 20120113 page28 Change Q25.2 to GPU_TRIP# EC.
10. 20120113 page28 Change GPU Strap1 PD4.99k,strap4 PD 45.3k.
11. 20120113 page31 stuff PR256 for Battery enable, change PQ50 to dual mose of ACIN to EC and PCH acpresent# pin.
13. 20120117 Update EMI CAP.
11. 20120117 page24 Add net WLAN_OFF for IOAC on U36.81 to CN5.64.
12. 20120117 page36 PR146 change to 365ohm,un-stuff PR36,stuff PR43,stuff PR145, PU7 change to TPS51463.
13. 20120118 page22 Change CN12 footprint.
14. 20120118 page22 Add u37 for ICT test use.
15. 20120119 page24 Add Q46 to EC U36.114.
16. 20120119 Unstuff PR266 and stuff R346 .
17. 20120119 move R358 to near Q38 and del net DRAMRST_CNTRL_PCH,and EC_DRAMRST_CNTRL and R616.
18. 20120119 Change PR266 from 100k to 10k .
19. 20120120 Remove C644/C621/C622.
20. 20120120 Page 24 change R640/R61 power plant to +3V_S5.
21. 20120120 unstuff R573 and stuff R574 for DS3 function.
1. 20120214 Page17Add c613 and c614 for LAN power noise.

1C
2. 20120214 Page07 Add R642 between SUSWARN to SUSACK.
3. 20120216 Page24 Add iRST Gate and change 108pin SUSWRAN# to IOAC_PCIERST#.
4. 20120216 Page20 CN5 pin22 reserve IOAC_PCIERST# solution.
5. 20120217 Page28 un-stuff R547/R548, stuff Q35,un-stuff R383/R435, stuff Q26/Q25,add PU 10k +3V GPU_THAL# and GPU_TRIP#.
R543/R548 PU from+3V to +3VPCU, for S5 current reduce.
6. 20120217 Page38 change PR77/PR81 to 27k,PR165/PR166 to 75k,PR76/PR80 to 30k
7. 20120217 change 0ohm to short pad.
8. 20120220 page 31 remove VA2 plant and PC205/PC202 PR124, move PD3 between PQ3 and PR10 for S5 current reduce.
9. 20120220 change PQ11, PQ2, PQ6, PQ10, PQ13, PQ5, PQ9, PQ49, PQ51 footprint to WDFN5-3_05X3_05-65.
10. 20120220 page7 Change net suswarn# to suswarn#_R PU.
11. 20120220 page36 PR145 un-stuff,PR145 change to 100,PR43 un-stuff, PR36 short pad.
12. 20120220 page24 add U36.105 GPIO KB_BL_EN pin to CN13.23.
13. 20120220 page20 Change Cn6 footprint
14. 20120221 page28 R527/R516 change power plant to +3V.
15. 20120221 page08 Change R620/R534 to 47K and stuff R620, R524 un-stuff
16. 20120221 page20 Add R650 for iRST selection.
17. 20120221 page15 CN7 pin33/34 connect to GND.
18. 20120222 page38 Unstuff PR219/PC137/PR288PC151.
19. 20120222 page38 Unstuff PR195/PC125/PR201/PC126.
20. 20120222 page15 del R299/R315.
21. 20120222 page14 Change Footprint U30/31/32/35.
22. 20120223 page15 Change Footprint L22.
A 23. 20120223 page08 Change JTAG TDI form CPU TDO, TCK and TMS form U37 and CPU . A
24. 20120223 page28 add dGPU_OPP# PU reserve R651.

25. 20120223 page28 add JTAG_TDO PU reserve R299.
1. 20120302 page19 add CN13.30 net to BIOAED_ID4.

2C
2. 20120305 page07 R397 from short pad to RC0402 footprint.
3. 20120322 page23 Remove RP1/RP2/RP3/RP4/L18/L19
4. 20120322 page31&37 , delete PR120 & PR121.
5. 20120322 page32 Reserve PC196 for PU1_PIN13
6. 20120322 page15 delete L1
7. 20120322 page24&31 Add NET<SB_ACDC> , add R653,Unstuff PR266 & R652
Wait for EC confirm by the result.
8. 20120328 page32 Remove PC196
9. 20120328 page35 Reserve PC202
10. 20120328 page34 Reserve PC205
11. 20120328 page38 Reserve PC206 , PC207
12. 20120328 page3 R204,R605 CS12002FB00 change to CS12002FB25
13. 20120328 page22 HOLE14 follow Hole11
14. 20120329 page22 HOLE11,HOLE14 footprint change to H-TE256X256I118BC256D118P2
14. 20120330 page23 R280/R281/R282/R283/R276/R277/R278/R279 change back to 0 ohm resistor.
15. 20120330 page31 PC196 add
15. 20120405 page23 R276,R277,R278,R279,R280,R281,R282,R283 change to 15 ohm

PROJECT : Z09 DOC NO. PROJECT MODEL : Z09 APPROVED BY: DATE: 2010/7/20
3A
Change list PART NUMBER: DRAWING BY: REVISON: 1A
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Z09 SYSTEM BLOCK DIAGRAM

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SATA - HDD FDI DMI

Ivy Bridge Processor (DMI,PEG,FDI)

PCI EXPRESS -- GRAPHICS

G17 GTP8C C139 EV@0.22u/10V_4 GTP8

SNB_2CBGA_1P0 0.22uF AC coupling Caps for PCIE GEN1/2/3

100K_4 Size Document Number Rev

TP78 TP_CATERR# C49

BF44 SM_RCOMP_0 R209 140/F_4 CAD NOTE: All DDR_COMP signals

JTAG & BPM

PM_DRAM_PWRGD_R BE45 G58 Option for Prochot# function +1.05V_VTT

*750/F_4 XDP_TCLK_VT R611 51_4

SNB_2CBGA_1P0 When MP, JTAG PU/PD resistor can be

If PM_DRAM_PWEGD connector,the R5180 must stuff. C190

*1K_4 *10K_4 0.1u/10V_4

R186 *1.5K/F_4 CPU_PLTRST#_R

Sandy Bridge Processor (DDR3)

SA_DQ[35] SA_DQS#[4] SB_DQ[35] SB_DQS#[4]

DDR SYSTEM MEMORY B

SNB_2CBGA_1P0 SNB_2CBGA_1P0 M_B_CLK1

C758 C757 C756 C755 C753 C754 C759

20120112 for memory down PU CAP.

PEG AND DDR

N26 VCC[72] +1.05V_VTT C200 C192 + C177 BC4 VCCPLL[2]

VIDSCLK C44 P17 VCCSA[5]

VCC_SENSE G43 VCCSA[16] A 1-K pull-down resistor should be placed on the

Sandy Bridge Processor (GND) Sandy Bridge Processor (RESERVED, CFG)

AJ20 AY55 L26 BE4

Date: Monday, April 09, 2012 Sheet 6 of 40

Digital Display Interface

System Power Management

PM_BATLOW# E10 AP14

PM_RI# A10 +3V_S5 K14 SLP_LAN#

PCH Pull-high/low(CLG) System PWR_OK(CLG) IMVP_PWRGD PU +3V

CLKRUN# R429 8.2K_4 PM_RI# R359 10K_4 C434

to PCH Pin12, XDP and EE debug U24 2

201201119 stuff R346. R411

PM_DRAM_PWRGD R396 200/F_4 Quanta Computer Inc.

RTC Circuitry(RTC) +3V_RTC PCH2(CLG)

68.1K/F_4 ZRH use 2N7002D AM3 SATA_RXN0 <21>

150K/F_4 R348 ACZ_RST#_R K34 SATA1RXP AP11

PCH_SPI_CLK T3 AH1 SATA3_RBIAS R464 750/F_4

(CLG) W25Q32BVSSIG / AKE391P0N00----->4MB

10/11 add +3V_PCH_ME

Intel ME Crypto Transport Layer 0 = Disable (Default)

+3V_PCH_ME R479 *1K_4

SPI_CS0#_UR_ME R620 47K_4

PCI_PIRQC# H38 PIRQB# USBP7P L30 PCIECLKRQ2# / GPIO20 CLKIN_DMI_P

C44 REQ1# / GPIO50 USBP9P C30 USBP9+ <23> CLKOUT_PCIE3P CLKIN_GND1_P

PLTRST#(CLG) +3V 20111128 change power plant to +3V. PCI/USBOC# Pull-up(CLG)

R430 10K_4 PCIE_CLKREQ0#

TC7SH08FU R351 EXTTS_SNI_DRV1_PCH 8 3 dGPU_SELECT# +3V

S_GPIO R112 100_4

BMBUSY# / GPIO0 +3V +3V TACH4 / GPIO68

Date: Monday, April 09, 2012 Sheet 10 of 40

20111021 remove vcc core power sense net

20111117 remove 0ohm resistor.

Clock and Miscellaneous

R158 *SHORT_8 V1 1u/6.3V_4 AH13 +1.05V_VTT

C40 C37 C39 Panther Point_R1P0 C53 C429

+5VCC_S5 +3V_S5 +3VCC_S5

+3V C411 R354 AO3413 Q23 C412 R355 AO3413 Q22

1K_4 10K_4 0.1u/10V_4

+1.5VSUS +1.5VSUS +SMDDR_VREF_DIMM R201 0_6 SMDDR_VREF_DQ1_M3 1 3 SMDDR_VREF_DQ1 R586 0_6

R52 100K_4 EDP_AUX_C R45 100K_4