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SP1_RF

C1726_RF

L1732_RF
FL1701_RF

C97_RF

U7_RF
L67_RF
C96_RF

L68_RF
C98_RF

L66_RF

L6_RF
C38_RF

L69_RF
C247_RF C99_RF L8_RF

J10_RF
C170_RF

C107_RF
F
L33_R
C281_RF
U8_RF

U12_RF
RF
R13_
J6_RF

C106_RF
C283_RF

C103_RF
L9_RF

C104_RF

U15
C329

C372

C137
U12
C130

C54

C52

C165
C371 C102_RF

C662

C762

C150
R26

C79

C147
U3

R86
C370
C330 R136

C170
C69

DZ4
C97
C27

D1

R10
C369
C214

L3
C328

C163
C346
C364
C365
C306
C59
L19 C252 C213
L21

U23

C349

C149
C315
C98
C297
C47
C321 C156
C320
C562
C347
C344 C345 C11

C3

U8

C109
R17
C107
C50
C26
C334

C336

U18
C997

C95
C307

C394
C209
C171

C396
C154

U4
R463 C73
C488
C166

U17
C746
C162

C115 C151
C6 C7

C133

C68 L5
C387
C386
C114 C135
C174
C152 C187

C173 C185 C605 C627

C169
C34
C77
C392
Q3

Q4
C265
C294
C288
C292
C285
C290
C282
C278
C281

C276
C271

C295
C302 C305 C312
L11

C273

C301 C318
R55
C260
C291
C245
C203
C190
C195
C204
C189
C205
C243
C257
C299
C264

C686
C687

C325
R60

R488

C326
C74
C310
C319

C317

U7
C246
D4

C239
C217

R66
U11

L17
C323
C16
R65

C261
C385
C332 C379
C262
C267
C247
C293
C248

C277
C444

R56
R54
C255

C207

Y2 C389 C391
C689
C258

C17 C987
C251

C263
C92
C378
C250

C688
Q5
L4

C55 C227 C223 C228 C225


C234
C413

C61 C64 C230 C222 C231 C224


C65 C229
C335

C220
C422
U14
R50

C4

C420 C333
C221
R59

R592
R15 C226

U21
C99
R145

C337
R129

C424
C421 C942 C348
R857

U22
C918 R35
R593

C961

C416
C233 C414

C341
C935
C425 C232

C342

C412
C143
FL96

C29

C962
C338

R103
C340
R594

R102
D5
D2

C237
C38

R100
C235

C236

C339

C138
C304

C360
C363
C238
C429
C218
C219

FL9
FL6

R5_RF
C39
C254

R3_RF
C44_RF
U5_RF

C8_RF

C1_RF
C43_RF C6_RF
U2
C368

C500
C501
C42_RF
C12_RF

Y1_RF C2_RF C54_RF C5_RF


R21_RF

R20_RF

Q2

R22_RF
C53_RF
C7_RF
C4_RF
C48_RF
C11_RF C13_RF C10_RF

R83
R84

C127_RF
C52_RF

C50_RF
L2_RF

C45_RF
C57_RF
R8401

R73
R58

R74

C153

U2_RF
L3_RF
C58_RF
C3_RF
C9_RF

C145_RF
R34_RF
R25_RF R26_RF
C1214_RF

C51_RF
C189_RF

C47_RF C46_RF C49_RF


U11_RF
C169_RF

C59_RF
C1201_RF
R24_RF
R23_RF

C56_RF C55_RF
C1215_RF

L5_RF L1_RF L4_RF L21_RF


J5_RF
C41_RF

C168_RF

SH3

C217_RF
L19_RF C109_RF L18_RF C108_RF C110_RF C253_RF
L75_RF
C119_RF
C39_RF
L73_RF
C195_RF

C239_RF

C156_RF

C233_RF
L16_RF
L17_RF

U23_RF U58_RF
U207_RF U14_RF

C214_RF
C212_RF

C118_RF
C111_RF

U1317_RF
C257_RF
L10_RF
C256_RF

L7_RF

C215_RF

C216_RF
C63_RF
C66_RF

C120_RF
C254_RF

L77_RF

R55_RF

L13_RF
C252_RF
C242_RF L74_RF C149_RF
C201_RF
C228_RF

C227_RF

C229_RF

C230_RF

C226_RF

R90

C240_RF C200_RF C210_RF


R30_RF R29_RF C248_RF C190_RF
R28_RF

C251_RF
C234_RF L72_RF C153_RF C148_RF
U2000_RF

R27_RF C322
C165_RF
L70_RF
C249_RF
C167_RF

C163_RF
C238_RF
C231_RF
C65_RF
L12_RF
C237_RF C232_RF
FL1_RF

C202_RF

C67_RF

C203_RF

C243_RF
C250_RF
L71_RF

FL10_RF
C236_RF

C208_RF

C164_RF

L44_RF
L11_RF

C40_RF

C126_RF

C93_RF
SH1
R35_RF
C255_RF
J4_RF

FL9_RF
L79_RF
C9

C121_RF
L78_RF
L65_RF
C245_RF
C22

L22_RF

U16_RF
L54_RF
C275

L53_RF

L55_RF
FL6_RF

C187_RF
C25

C82_RF
L39_RF
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C188_RF
C184_RF
C246_RF
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C81_RF C185_RF
C83_RF
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C186_RF
C85_RF C183_RF
C86_RF L49_RF L45_RF
C125_RF
C23

C76_RF L51_RF L50_RF


L25_RF
C74_RF
L46_RF

L52_RF
C73_RF
C75_RF
J6

U3_RF
C279

R46_RF
C87_RF

R47_RF
FL11

R48_RF
C128_RF
C89_RF
C78_RF
C79_RF
C80_RF

C92_RF
C90_RF
C91_RF

C242 R107
DZ75
C8

FL10

C5

C193_RF FL1
FL68
L14_RF

DZ9 DZ76
L15_RF

C147_RF

R19_RF
R53_RF
U9_RF

FL2_RF
C88_RF
C72_RF

DZ6
FL17
DZ12 L7
DZ5 FL16
L6 DZ11
C2307
C36_RF
C33_RF C188
C35_RF C206
C70_RF
C34_RF
C62_RF

FL69
C68_RF DZ10
C32_RF
C29_RF
C28_RF

C18_RF FL5
C359
C176
C15_RF C855
C240
C22_RF
C17_RF

C215
C16_RF

C879
C26_RF R130
J7

FL495
C913
C71
C23_RF
C19_RF

C914 FL49
C21_RF
C24_RF

FL60
C20_RF C878 C355
C70
FL2302
C71_RF

R7_RF C14_RF C119


FL53

U1_RF
R6_RF R10_RF C12
R33_RF
C144_RF

C13
C69_RF
C27_RF
C30_RF
C25_RF
R4_RF
C177_RF

R9_RF
J11_RF

SH2
R921
C87
R46

C134
R53

C343

Y1
C327
C308
C21

C316
C37
FL40
C123
C90
R25
R27
R6

C141

C20

R71

C303 C36 R7
R52

C91
C183

C296
C172

C81
C388
C953

C168
C76

R57 C175
C2

C28
C178

C179 C89
C164
C128

C85 C72
C35

R28
C94
C157
C111

C83

C96
R29
C32
C127
C155

C177
R82

C181 U1 C158 C88


R78

C390
R137 R143 C883
C86
C136 C144
C104
C142
C161

C101

C106
C108

R5
R16 R14 R24
R33 C78 C80

C113
C103 C100 C182
C437 R47 C58
C132 C53
C146

C140
C75
C745 C145

C266
C117
C112
C139
R67 C268
C105 C57

R34
C259 C66 C60

R953
C1 R38 C274 C191 R40 C284 R13 R11

C148
C93

BS1 BS2
C46 C311 C434
C438
C436

FL27
C40
L1

FL61
FL34
C18

R31
C41
C19
R32
C24

C435
C433
R12
R41
R37
R21
R19
R39
R18
R42
FL36
FL18

FL24
FL35

C10
FL12 C14
FL57 C42
FL14 C15
FL20 C30
FL8
FL15 FL58 DZ2
C192
C1201

FL26
DZ3
C202
J5 C102

FL13

C198
FL46
C196
DZ7 C241
FL25 C197
C208
C194 C381
FL7

C610

R8
C63
L2 L9 L8 L10 C399

R92
R79

FL45
C313
C62 C398

C441

L35 L39
C201 C324 C397
FL21
FL2

J2

FL44
FL4_RF

C402
R91
C211
C212 FL23

C410
C407
C61_RF
DZ23

D3 C118
Q7
C210
R9401 FL47

C49
C67 DZ1

C45
C199
C216 C244
R1
FL4

R
C314
FL3
C48

J1
C56
FL48

C253
DZ24
C331 C43
DZ17 U6_RF

C380
R45
C200 R20

DZ16
R22

R85

FL753
C256

U16
C44

Q1
L29
C249

FL751
FL52
FL51
U13 C193
L28
U25
C82

FL43

FL39

FL752
C300
R36

R2

FL29
C361

FL31
FL30
C287
C350 C286 C357
FL28

FL38
C373 C358
C353 C376 C352 C351 R72
U5

C298
FL22
C31

C84
L27
C427
C430

R18_RF
BS3
C432
J3

J4
R43_RF

R16_RF
C37_RF
R17_RF
L33 L34 L37 L36 L38

R51_RF
R52_RF
R44_RF
R110
C167

R15_RF
C105_RF
C159

CL1
R108
U20_RF

C282_RF
L20_RF

R12_RF
SP3_RF

8 7 6 5 4 3 2 1
CK


1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. APPD
REV ECN DESCRIPTION OF REVISION
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. DATE
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
2 0001669557 ENGINEERING RELEASED 2012-10-14

X155 PROTO1 SINGLE_BRD


D Mon Oct 8 11:06:07 2012 D

TO DO: CLEANUP ALTERNATES FOR X155

PDF PAGE CSA PAGE CONTENTS SYNC MASTER DATE


ALTERNATES TABLE_ALT_HEAD
X155 BOM CALLOUTS TABLE_5_HEAD

TABLE_TABLEOFCONTENTS_HEAD

PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION
PART NUMBER
2 2 H5P JTAG, USB ,PLL N/A N/A TABLE_ALT_ITEM

051-9584 1 SCH, SINGLE_BRD, X155 SCH Y ?


TABLE_5_ITEM

TABLE_TABLEOFCONTENTS_ITEM
138S0648 138S0652 ALTERNATE ? 4.7UF CERM 0402 6.3V TABLE_5_ITEM

TABLE_ALT_ITEM

820-3329 1 PCB, SINGLE_BRD, X155 PCB Y ?


3 3 H5P GPIO & CONTROL N/A N/A 339S0177 339S0176 ALTERNATE ? H5P ALTERNATE TABLE_5_ITEM

TABLE_ALT_ITEM

825-6838 1 LABEL FOR X155 639-3796 EEEE_F284 Y EEEE_16G


TABLE_TABLEOFCONTENTS_ITEM

339S0178 339S0176 ALTERNATE ? H5P ALTERNATE

4 4 H5P IO POWER N/A N/A


TABLE_TABLEOFCONTENTS_ITEM

5 5 H5P SOC/CPU/SRAM PWR N/A N/A


TABLE_TABLEOFCONTENTS_ITEM

6 6 H5P W/ NAND N/A N/A


TABLE_TABLEOFCONTENTS_ITEM

7 7 H5P VIDEO N/A N/A


TABLE_TABLEOFCONTENTS_ITEM COMPASS BOM OPTIONS GYRO BOM OPTIONS
8 8 BUTTON FLEX B2B N/A N/A PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION
TABLE_5_HEAD

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION


TABLE_5_HEAD

TABLE_TABLEOFCONTENTS_ITEM

C
TABLE_5_ITEM TABLE_5_ITEM

C 9 9 L67 AUDIO CODEC (1/2) N/A N/A


639-4024 1 ST GYRO - COMPASS POP U16 Y COMPASS_POP 338S1158

132S0391
1

1
ST GYRO

ST GYRO - CP CAP
U8

C11
Y

Y
GYRO_ST

GYRO_ST
TABLE_5_ITEM

NAND BOM OPTIONS


TABLE_TABLEOFCONTENTS_ITEM

10 10 L67 AUDIO CODEC (2/2) N/A N/A


TABLE_TABLEOFCONTENTS_ITEM

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION


TABLE_5_HEAD

CHESTNUT BOM OPTIONS


11 11 CG FLEX B2B N/A N/A 335S0878 1 NAND,19NM,16GX8,MLC,PPN1.5 U4 Y NAND_16G
TABLE_5_ITEM

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION


TABLE_5_HEAD

TABLE_TABLEOFCONTENTS_ITEM

TABLE_5_ITEM

338S1172 1 TI CHESTNUT U3 Y CHESTNUT_TI


12 12 AGATHA PMU(1/2) N/A N/A
TABLE_TABLEOFCONTENTS_ITEM HORIZONTAL CAP BOM OPTIONS 152S1649 1 TI CHESTNUT - 1.5 UH IND L19 Y CHESTNUT_TI
TABLE_5_ITEM

13 13 AGATHA PMU(2/2) N/A N/A


TABLE_5_HEAD TABLE_5_ITEM

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION 338S1168 1 INTERSIL CHESTNUT U3 Y CHESTNUT_INTERSIL
TABLE_5_ITEM TABLE_5_ITEM

TABLE_TABLEOFCONTENTS_ITEM

138S0801 5 HRZN CAPS_1:10UF,0402,6.3V C422,C74,C92,C250,C265 Y HRZN_CAP_GRP1 152S1611 1 INTERSIL CHESTNUT -2.2 UH IND L19 Y CHESTNUT_INTERSIL
14 14 CHESTNUT + BACKLIGHT DRIVER N/A N/A 138S0801 5 HRZN CAPS_1:10UF,0402,6.3V C293,C294,C257,C299,C262 Y HRZN_CAP_GRP2
TABLE_5_ITEM

TABLE_TABLEOFCONTENTS_ITEM

15 15 SPKR AMP + LED DRIVER N/A N/A 138S0801 5 HRZN CAPS_1:10UF,0402,6.3V C264,C378,C189,C203,C245 Y HRZN_CAP_GRP3
TABLE_5_ITEM

TABLE_5_ITEM
TRISTAR BOM OPTIONS TABLE_5_HEAD

TABLE_TABLEOFCONTENTS_ITEM 138S0801 5 HRZN CAPS_1:10UF,0402,6.3V C190,C204,C239,C246,C195 Y HRZN_CAP_GRP4 PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION

16 16 TRISTAR N/A N/A


TABLE_5_ITEM

TABLE_5_ITEM

138S0801 5 HRZN CAPS_1:10UF,0402,6.3V C205,C243,C247,C252,C297 Y HRZN_CAP_GRP5 343S0614 1 CBTL1608A1UK,WCSP,TRISTAR U2 Y TRISTAR


TABLE_5_ITEM

TABLE_TABLEOFCONTENTS_ITEM TABLE_5_ITEM

138S0801 5 HRZN CAPS_1:10UF,0402,6.3V C386,C387,C333,C332,C335 Y HRZN_CAP_GRP6 343S0639 1 CBTL1610A0UK,WCSP,TRISTAR2 U2 Y TRISTAR2


17 17 DOCKFLEX B2B N/A N/A 138S0801 3 HRZN CAPS_1:10UF,0402,6.3V C42_RF,C43_RF,C44_RF Y HRZN_CAP_GRP7
TABLE_5_ITEM

TABLE_5_ITEM

TABLE_TABLEOFCONTENTS_ITEM
118S0671 2 RES 15OHM 01005 5% R102,R103 Y TRISTAR
TABLE_5_ITEM

TABLE_5_ITEM

138S0801 1 HRZN CAPS_1:10UF,0402,6.3V C1201_RF Y HRZN_CAP_GRP8


18 18 D404 (TOUCH B2B, DRIVER ICS) N/A N/A TABLE_5_ITEM
117S0202 2 RES 200HM 01005 5% R102,R103 Y TRISTAR2

TABLE_TABLEOFCONTENTS_ITEM 138S0801 4 HRZN CAPS_1:10UF,0402,6.3V C182,C307,C209,C187 Y HRZN_CAP_GRP10

19 19 LCM CONNECTOR N/A N/A


TABLE_5_ITEM

138S0794 2 HRZN CAPS_1:10UF,0402,10V C52,C156 Y HRZN_CAP_GRP11

B TABLE_TABLEOFCONTENTS_ITEM

138S0582 1 4.7UF 0.55MM HEIGHT C193 Y LOW_Z_CAP


TABLE_5_ITEM

B
20 20 SENSORS N/A N/A
TABLE_TABLEOFCONTENTS_ITEM

21 21 CAM0 CONNECTOR N/A N/A BOARD_ID RADIO BOM OPTIONS


TABLE_TABLEOFCONTENTS_ITEM

TABLE_5_HEAD

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION


22 22 BATT B2B, TPS, PD FEATURES N/A N/A TABLE_5_ITEM

TABLE_TABLEOFCONTENTS_ITEM 118S0621 1 1.00M 1% 01005 R25_RF Y N51_CFG_A

23 23 RADIO_MLB HIERARCH. SYMBOL N/A N/A


TABLE_5_ITEM

118S0732 1 50K 1% 01005 R26_RF Y N51_CFG_A


TABLE_5_ITEM

TABLE_TABLEOFCONTENTS_ITEM

117S0159 1 470K 5% 01005 R25_RF Y N51_CFG_B


TABLE_5_ITEM

118S0626 1 100K 1% 01005 R26_RF Y N51_CFG_B


TABLE_5_ITEM

118S0626 1 100K 1% 01005 R25_RF Y N53_CFG_A


TABLE_5_ITEM

118S0726 1 162K 1% 01005 R26_RF Y N53_CFG_A

SCH 051-9584
TABLE_5_ITEM

118S0626 1 100K 1% 01005 R25_RF Y N53_CFG_B


TABLE_5_ITEM

118S0623 1 267K 1% 01005 R26_RF Y N53_CFG_B

BRD 820-3329
TABLE_5_ITEM

118S0659 1 255K 1% 01005 R25_RF Y N48_CFG_A


TABLE_5_ITEM

118S0626 1 100K 1% 01005 R26_RF Y N48_CFG_A


TABLE_5_ITEM

118S0689 1 147K 1% 01005 R25_RF Y N48_CFG_B


TABLE_5_ITEM

118S0626 1 100K 1% 01005 R26_RF Y N48_CFG_B

A
TABLE_5_ITEM

118S0626 1 100K 1% 01005 R25_RF Y N49_CFG_A


A
BOM 639-3796 X155
TABLE_5_ITEM

118S0650 1 499K 1% 01005 R26_RF Y N49_CFG_A DRAWING TITLE

118S0732 1 50K 1% 01005 R25_RF Y N49_CFG_B


TABLE_5_ITEM

SCH,SINGLE_BRD,X155
TABLE_5_ITEM DRAWING NUMBER SIZE
118S0621 1 1.00M 1% 01005 R26_RF Y N49_CFG_B
Apple Inc. 051-9584 D
REVISION
R
2.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
1 OF 23
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 1 OF 46
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D
PP1V0 2 7 12
D
1 C34
0.01UF
10%
6.3V
NO_XNET_CONNECTION=TRUE 2 X5R
01005

19 18 14 12 11 10 7 6 5 4 3 2
PP1V8 1
SM
XW5
2 PP1V8_PLL
21 20

PP3V3_USB
1 C33 1 C20 1 C21 C141 1 12

0.01UF 0.01UF 0.01UF 100PF


10%
6.3V
2 X5R
10%
6.3V
2 X5R
10%
6.3V
2 X5R
5%
10V
1 C32 1 C35 1 C128 1 C157
NP0-C0G 2 0.01UF 56PF 10UF 0.22UF
01005 01005 01005 01005 10% 5% 20% 20%
NOSTUFF 6.3V
2 X5R
6.3V
2 NP0-C0G
6.3V
2 CERM-X5R
6.3V
2 X5R
01005 01005 0402-1 0201

12 7 2
PP1V0

PP1V2 PP1V8
C93 1 1 C392 12 4 2 3 4 5 6 7 10 11 12 14 18 19
20 21

0.22UF 0.22UF
20%
6.3V
20%
6.3V C2 1 1 C28
X5R 2 2 X5R
0.22UF 0.22UF
0201 0201 20% 20%
6.3V 6.3V
2 X5R

(3X 11.9MA)
X5R 2

(3X 2.7MA)
0201 0201

(2X 1MA)

(2X 1MA)

(5.4MA)
(28MA)
(22MA)
(1MA)
(1MA)
(1MA)
(1MA)

(1MA)
C C

HSIC_VDD123 AK17

HSIC3_DVDD103 AK16
HSIC_VDD121 L29
HSIC_VDD122 J29

HSIC1_DVDD101 M29
HSIC2_DVDD102 K29

G19
J19
G18
J18
J21
G20
J20
G21

VDD_ANA_PLLUSB J22

USB_DVDD G29
USB_VDD330 J26
USB_ASW_VDD18 G28
VDD_ANA_PLL0
VDD_ANA_PLL1
VDD_ANA_PLL2
VDD_ANA_PLL3
VDD_ANA_PLL4
VDD_ANA_PLL5
VDD_ANA_PLL6
VDD_ANA_PLL7
U1
23 50_AP_BI_BB_HSIC1_DATA F34 HSIC1_DATA H5P-SC58950C03 WDOG AT13 WDOG 13
C36
BASEBAND 23 50_AP_BI_BB_HSIC1_STB F33 HSIC1_STB FCMSP 12PF
SYM 1 OF 12 FINAL XTAL PASSIVES 11/30/2011
XI0 A12 45_XTAL_24M_I 1 2
E34 HSIC2_DATA XO0 A13 45_XTAL_24M_O
5%

1.00M2
E33 HSIC2_STB 16V

3
Y1

1/32W
01005
R7
CERM

2 4
1%
MF
USB11_DP C34 01005
AV15 HSIC3_DATA NO_CONNECT OKAY 24.000MHZ-30PPM-9.5PF-60OHM
50_AP_BI_WLAN_HSIC3_DATA USB11_DM D34 C37
WLAN (TOP)
23
R71 XW44

1
1
1.60X1.20MM-SM
23 50_AP_BI_WLAN_HSIC3_STB AU15 HSIC3_STB 12PF SHORT-10L-0.1MM-SM
1.00K2 XTAL_24M_O_R
USB_DP A32 90_USBHS_H5P_P 1 1 2 XTAL_GND 1 2
AN15 5% MF
JTAG_SEL USB_DM A31 90_USBHS_H5P_N 1/32W 01005 5%
AM15 JTAG_TRTCK USBHS ON/OFF TOLERANCE 5V/1.98V 16V
CERM
AN13 JTAG_TRST* USB_ANALOGTEST E27 01005
AP15 JTAG_TDO
R1
1
0.00 2 90_AP_BI_TRISTAR_USB0_P
AM16 JTAG_TDI USB_VBUS F29 USB_VBUS_DETECT 12 16
1/32W 0% MF 01005
16 TRISTAR_BI_AP_JTAG_SWDIO AN16 JTAG_TMS
SERIAL MODE NAMES
16 TRISTAR_TO_AP_JTAG_SWCLK AM14 JTAG_TCK USB_ID E29 R30
0.00 2
B AT15 TESTMODE
USB_BRICKID F28 1
0%
90_AP_BI_TRISTAR_USB0_N 16
B
1/32W
USB_REXT A30 USB_REXT MF
01005
R28 FUSE1_FSRC
CPU0_SWITCH AR9 CPU0_SWITCH 12
1
R6
AV10 TST_STPCLK CPU1_SWITCH AU10 CPU1_SWITCH 12 43.2
AR16 TST_CLKOUT 1%
19 18 14 12 11 10 7 6 5 4 3 2 PP1V8 13 AP_TO_PMU_TEST_CLKOUT 1/32W
21 20 USB_BRICKID_DM_MON G27 MF
2 01005
1
R67 A19 FAST_SCAN_CLK
47.0K
5%
1/32W
MF AP14 HOLD_RESET

USB_ASW_VSS18
2 01005
L28 HSIC_VSS121
J28 HSIC_VSS122
AL17 HSIC_VSS123

1.8V TOLERANT
M28 HSIC1_DVSS
K28 HSIC2_DVSS
AL16 HSIC3_DVSS
RESET_1V8_L AV11 RESET*

USB_VSSA0
USB_VSSA0
USB_VSSA0
23 22 19 16 14 13 12

1 C1 AV13 CFSB
1000PF K16 DDR0_CKEIN
10%
6.3V N8 DDR1_CKEIN
2 X5R-CERM
01005
H27
H26
H29

H28
PLACE R49 AND C1 CLOSE TO EACH OTHER AND U1 PER EMC

A SYNC_MASTER=N/A SYNC_DATE=N/A A
PAGE TITLE

H5P JTAG, USB ,PLL


DRAWING NUMBER SIZE

Apple Inc. 051-9584 D


REVISION
R
2.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
2 OF 23
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 2 OF 46
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
BOARD_REV[3:0]={EHCI_PORT3,EHCI_PORT_PWR2,EHCI_PORT_PWR1,EHCI_PORT_PWR0}
FLOAT=LOW, PULLUP=HIGH PP1V8 2 3 4 5 6 7 10 11 12 14 18 19
20 21
1111 X155 INITIAL 2 01005 2 01005
1101 - PROTO1 TRISTAR
1100 - PROTO1 TRISTAR 2
<---PROTO1 SELECTED R171 MF
1/32W
R18
1
R19
1
R21
1 MF
1/32W
2.2K 5% 2.2K 2.2K 2.2K 5%
1
5% 2.2K 5% 5% 5% 2.2K PP P4MM
PP13
1/32W
MF 1
R91 1/32W
MF 1/32W
MF
1/32W
MF
R92
1 1
SM

PP P4MM
R16 01005 2 2 01005 2 01005 2 01005 SM PP15
45_AP_TO_CODEC_I2S_MCLK 33.2 2 AP30 AR7 AGATHA PMU: 1110100X
10 1 45_I2S0_MCK_R I2S0_MCK I2C0_SCL AP_TO_I2C0_SCL 13 14 15 16 20 CS35L20 AMP: ????????
1%
1/32W
1045_AP_TO_CODEC_ASP_I2S0_BCLK AM30 I2S0_BCLK U1 I2C0_SDA AT4 AP_BI_I2C0_SDA 13 14 15 16 20
AP3GDL20-BC GYRO:
TRISTAR:
LM3534:
1101010X
0011010X
1100011X
MF
01005
10 AP_TO_CODEC_ASP_I2S0_LRCLK
AH31 H5P-SC58950C03
I2S0_LRCK I2C0 CHESTNUT: 0100111X

D BOARD_ID[3:0]={GPIO16,SPIO0_MISO,SPI0_MOSI,SPI0_SCLK} CODEC ASP 10 CODEC_TO_AP_ASP_I2S0_DIN AH30

10 AP_TO_CODEC_ASP_I2S0_DOUT
AJ30
I2S0_DIN
I2S0_DOUT
FCMSP I2C1_SCL
I2C1_SDA
AV6
AT3
AP_TO_I2C1_SCL
AP_BI_I2C1_SDA
20

20
I2C1 AP3DSH ACCEL: 0011101X
AK8963C COMPASS: 0001100X
D
FLOAT=LOW, PULLUP=HIGH
SYM 3 OF 12
1010 X155 MLB <--- SELECTED AK29 AT9
I2S1_MCK I2C2_SCL AP_TO_I2C2_SCL 11 I2C2 CT814 ALS: 0101001X
23 45_AP_TO_BB_I2S1_BCLK AL31 I2S1_BCLK I2C2_SDA AR8 AP_BI_I2C2_SDA 11

23 AP_TO_BB_I2S1_LRCLK AN31 I2S1_LRCK


BASEBAND
23 BB_TO_AP_I2S1_DIN AH29 I2S1_DIN SWI_DATA AP5
23 AP_TO_BB_I2S1_DOUT AH32 I2S1_DOUT 1%
R47 MF
R5 DWI_CLK AT7 45_AP_TO_PMU_DWI_CLK_H5P 1 33.2 2 45_AP_TO_PMU_DWI_CLK
BOOT_CONFIG[3:0]={GPIO29_CONFIG3,GPIO28_CONFIG2,GPIO25_CONFIG1,GPIO18_CONFIG0} 33.2 2 1/32W 01005
13 14

15 45_AP_TO_SPKAMP_I2S2_MCLK 1 45_I2S2_MCK_R AM29 I2S2_MCK DWI_DI AV7 45_AP_TO_PMU_DWI_DI 13


FLOAT=LOW, PULLUP=HIGH AM28 AM8
1% 15 10 45_AP_TO_CODEC_XSP_I2S2_BCLK I2S2_BCLK DWI_DO 45_AP_TO_PMU_DWI_DO 13 14
0000 SPI0 1/32W
MF 15 10 AP_TO_CODEC_XSP_I2S2_LRCLK AJ31 I2S2_LRCK
0001 SPI3 01005
0010 SPI0 W/TEST 15 10 CODEC_TO_AP_XSP_I2S2_DIN
AM33 I2S2_DIN
0011 SPI3 W/TEST CODEC XSP & SPKR AMP 10 AP_TO_CODEC_XSP_I2S2_DOUT AN30 I2S2_DOUT
0100 FMI0 2CS 15

0101 FMI0 4CS


0110 FMI0 4CS W/TEST AM31 I2S3_MCK
0111 RESERVED 23 45_AP_TO_BT_I2S3_BCLK AK31 I2S3_BCLK
1000 FMI1 2 CS AL28
23 AP_TO_BT_I2S3_LRCLK I2S3_LRCK
1001 FMI1 4 CS BLUETOOTH
1010 FMI1 4CS W/TEST 23 BT_TO_AP_I2S3_DIN AL30 I2S3_DIN
1100 FMI0/1 2/2 CS <--- SELECTED 23 AP_TO_BT_I2S3_DOUT AP31 I2S3_DOUT
1101 FMI0/1 4/4 CS
1110 FMI0/1 4/4 CS W/TEST
1111 RESERVED AK30 I2S4_MCK
10 45_AP_TO_CODEC_VSP_I2S4_BCLK AM32 I2S4_BCLK
10 AP_TO_CODEC_VSP_I2S4_LRCLK AP32 I2S4_LRCK
COMMON PULL UP FOR BOARD_REV, BOARD_ID AND BOOT_CONFIG PINS AK32
CODEC VSP 10 CODEC_TO_AP_VSP_I2S4_DIN I2S4_DIN
BOARD_INFO 1
R12 2 PP1V8 AP_TO_CODEC_VSP_I2S4_DOUT AR32
3 2 3 4 5 6 7 10 11 12 14 18 19 10 I2S4_DOUT
01005 1.00K 20 21

C R12 MUST WIN OVER 6X INTERNAL PULL-DOWNS THAT ARE ~100K


AR31 SPDIF C
BOARD_ID2 AM4 SPI0_MISO
BOARD_ID1 3 BOARD_INFO AR5 SPI0_MOSI
BOARD_ID0 AM2 SPI0_SCLK
19 LCM_TO_AP_PIFA AP3 SPI0_SSIN
NOSTUFF FOR TRISTAR2
STUFF FOR TRISTAR
18 TOUCH_TO_AP_SPI1_MISO AN3 SPI1_MISO
01005
1
R51 2 PP1V8 11 12 14 18 19 20 21
AP_TO_TOUCH_SPI1_MOSI AL3
2 3 4 5
GRAPE 18 SPI1_MOSI
1.00K 6 7 10
AK1
18 AP_TO_TOUCH_SPI1_CLK SPI1_SCLK
18 AP_TO_TOUCH_SPI1_CS_L AR4 SPI1_SSIN

23 16 14 13 12 10 4 PP1V8_SDRAM 11 FCAM_TO_AP_ALS_INT_L AN4 SPI2_MISO


23 BB_TO_AP_IPC_GPIO AM3 SPI2_MOSI
R52 1
BUTTON_TO_AP_MENU_KEY_BUFF_L
13 3 W3 GPIO0 EHCI_PORT_PWR0 AE4 BOARD_REV0 BOARD_REV0
23 AP_TO_WLAN_HSIC2_RDY AN6
AN1
SPI2_SCLK
220K 21 WLAN_TO_AP_HSIC2_RDY
5%
1/32W
BUTTON_TO_AP_HOLD_KEY_BUFF_L
13 3 N2 GPIO1 U1
EHCI_PORT_PWR1 AD3 19 20
12 14
10 11
BOARD_REV1
23 SPI2_SSIN

13 8 BUTTON_TO_AP_VOL_UP_L
MF
01005 2
M4 GPIO2 H5P-SC58950C03 EHCI_PORT_PWR2 AD4 PP1V8 6 7 18
2 3 4
5
BOARD_REV2
CODEC_TO_AP_SPI3_MISO AP9 SPI3_MISO
BUTTON_TO_AP_VOL_DOWN_L V3 GPIO3 FCMSP EHCI_PORT_PWR3 AE3 PP1V8 20 21
BOARD_REV3
10
13 8 2 3 4
5 6 7 10 11 12 14 18 19 10 AP_TO_CODEC_SPI3_MOSI AM9 SPI3_MOSI
13 8 BUTTON_TO_AP_RINGER_A T4 GPIO4 CODEC
10 AP_TO_CODEC_SPI3_CLK AM13 SPI3_SCLK
15 SPKAMP_TO_AP_INT_L W2 GPIO5 SYM 2 OF 12 TMR32_PWM0 AT6 GYRO_TO_AP_INT2 20
10 AP_TO_CODEC_SPI3_CS_L AN12 SPI3_SSIN
(OPEN DRAIN@PMU) NEW ---> 13 PMU_TO_AP_IRQ_L P3 GPIO6 TMR32_PWM1 AP8 VIB_PWM 8
23 AP_TO_BT_WAKE M3 GPIO7 TMR32_PWM2 AP1 45_AP_TO_TOUCH_CLK32K_RESET_L 18
U3 GPIO8
L19A KEEP (STAYING) ALIVE --> 15 AP_TO_SPKAMP_BEE_GEES P4 GPIO9 UART0_RXD AR15 VIB_LDO_EN 8

23 BB_TO_AP_HSIC1_REMOTE_WAKE W1 GPIO10/SDIO_D3 UART0_TXD AU12 AP_TO_LEDDRV_EN 15


BB_JTAG_TCK 23 AP_TO_BB_JTAG_TCK M2 GPIO11/SDIO_D2
B RESERVED BB_JTAG_TDI 23 AP_TO_BB_JTAG_TDI
BB_JTAG_TMS 23 AP_TO_BB_JTAG_TMS
R3
N3
GPIO12/SDIO_D1 UART1_CTSN AA3
AB2
BB_TO_AP_UART1_CTS_L 23 B
GPIO13/SDIO_D0 UART1_RTSN AP_TO_BB_UART1_RTS_L 23 BB
BB_JTAG_TDO 23 BB_TO_AP_JTAG_TDO M1 GPIO14/SDIO_CMD UART1_RXD AB3 BB_TO_AP_UART1_RXD 16 23
AC3 GPIO15/SDIO_CLK UART1_TXD AF5 AP_TO_BB_UART1_TXD 16 23
BOARD_ID3 3 BOARD_INFO T3 GPIO16
23 AP_TO_BB_HSIC1_RDY V1 GPIO17 UART2_CTSN AG3 TRISTAR_TO_AP_INT 13 16

BOOT_CONFIG0 AC2 GPIO18 UART2_RTSN AA1 ACCEL_TO_AP_INT1 20


V4 AE2
MENU & POWER / HOLD KEY
13 KEEPACT GPIO19 UART2_RXD TRISTAR_TO_AP_ACC_UART2_RXD 16
23 WLAN_TO_AP_HSIC2_REMOTE_WAKE R31 GPIO20 UART2_TXD AF3 AP_TO_TRISTAR_ACC_UART2_TXD 16
18 TOUCH_TO_AP_INT_L P34 GPIO21
19 AP_TO_LCM_RESET_L P33 GPIO22 UART3_CTSN AH3 BT_TO_AP_UART3_CTS_L 23

19 18 LCM_TO_AP_HIFA_BSYNC P32 GPIO23 UART3_RTSN AB1 AP_TO_BT_UART3_RTS_L 23


BT
23 AP_TO_BB_RST_L
N32 GPIO24 UART3_RXD AF4 BT_TO_AP_UART3_RXD 23

BOOT_CONFIG1 L33 GPIO25 UART3_TXD AG4 AP_TO_BT_UART3_TXD 23 12 PP1V8_ALWAYS


22 FORCE_DFU P30 GPIO26
DFU STATUS P31 GPIO27 UART4_CTSN/SPI4_SSIN AJ4 AP_TO_BB_JTAG_TRST_L 23
BOOT_CONFIG2 3 2
21
PP1V8 L34 GPIO28 UART4_RTSN/SPI4_SCLK AE1 AP_TO_CAM_RF_VDDCORE_EN 21 R22
1
R20
1

5
20 19 18 14 12 11 10 7 6 5 4
M32 AJ2 392K 392K
21 BOOT_CONFIG3 3 2 PP1V8 GPIO29 UART4_RXD/SPI4_MISO WLAN_TO_AP_UART4_RXD 23 1% 1% VCC
20 19 18 14 12 11 10 7 6 5 4
K32 AH4 WIFI UART 1/32W 1/32W
10 CODEC_TO_AP_INT_L GPIO30 UART4_TXD/SPI_MOSI AP_TO_WLAN_UART4_TXD 23 MF MF U25
DEV_HSIC1_RDY 23 BB_TO_AP_HSIC1_RDY L32 GPIO31 2 01005 2 01005 74AUP2G34GN
SOT1115
23 AP_TO_RADIO_ON_L
C22 GPIO32 UART5_RXD AK4 AP_BI_BATTERY_SWI 13 22
GAS GAUGE 17 BUTTON_TO_AP_MENU_KEY_L 1 1A 1Y 6 BUTTON_TO_AP_MENU_KEY_BUFF_L 3 13
20 GYRO_TO_AP_INT1
D22 GPIO33 UART5_TXD AJ3 BB_TO_AP_RESET_DET_L
SMPP5
1 20 COMPASS_TO_AP_INT_2 C21 GPIO34
23

P2MM PP 8 BUTTON_TO_AP_HOLD_KEY_L 3 2A 2Y 4 BUTTON_TO_AP_HOLD_KEY_BUFF_L 3 13


23 AP_TO_BB_WAKE_MODEM D21 GPIO35 UART6_CTSN AH2 BB_TO_AP_PP_SYNC 23
20 ACCEL_TO_AP_INT2
C20 GPIO36 UART6_RTSN AL1 AP_TO_SPKAMP_RESET_L 15 GND
D20 AK3
A TRISTAR_TO_AP_DEBUG_UART6_RXD 16

2
RESERVED FOR NON-TRISTAR DESIGN ---> GPIO37 <50MHZ UART6_RXD
11 ALS_TO_AP_INT_L
C19 GPIO38 UART6_TXD AD1 AP_TO_TRISTAR_DEBUG_UART6_TXD 16 DEBUG UART: TOLERANCE 1.98V SYNC_MASTER=N/A SYNC_DATE=N/A A
18 AP_TO_TOUCH_GRAPE_RESET_L D19 GPIO39 <50MHZ PAGE TITLE

AT11 GPIO_3V0
GPIO_SVSEL18_FMI AU13
AR14
H5P GPIO & CONTROL
17 AP_TO_HEADSET_HS3_CTRL GPIO_SVSEL25_FMI DRAWING NUMBER SIZE
FMI, 00=1.8V | 01=3.0V | 10=3.3V
17 AP_TO_HEADSET_HS4_CTRL AP12 GPIO_3V1
Apple Inc. 051-9584 D
GPIO_VSEL25_I2C2 AR13 REVISION
GPIO_VSEL25_SPI3 AT12 I2C2, 0=1.8V | 1=3.0V
R
2.0.0
SPI3, 0=1.8V | 1=3.0V NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
3 OF 23
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 3 OF 46
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

A1 12 4 2
PP1V2 G11 AE13
U1 A2
POR CAPS NOV/1/2010
G13 U1 AE15

PP1V2_SDRAM
4 DDR0_ZQ AV4 H5P-SC58950C03
DDR0_RREF AT30
CAPS FOR VDDIOD ARE SHARED WITH VDDQ
G15 H5P-SC58950C03 AE17
12 4
4 DDR1_ZQ AN34 DDR1_RREF FCMSP AV9 G17 FCMSP AE19
L16 SYM 7 OF 12 B15 G5 SYM 9 OF 12 AE21
DDR0_VDD_CKE(<1MA)
1 C81 N9 DDR1_VDD_CKE(<1MA) C1 G7 AE23
0.1UF
20% 4 DDR0_VREF_CA AV8 DDR0_VREF_CA C12 G9 AE25
6.3V

D
2 X5R-CERM
01005 4 DDR1_VREF_CA
4 DDR0_VREF_DQ
AK34
B31
DDR1_VREF_CA
DDR0_VREF_DQ
C27
D18
NOSTUFF
C816 1
H10
H12
AE27
K26
D
R34 4 DDR1_VREF_DQ R2 DDR1_VREF_DQ D7 0.1UF H14 AF10
1
243 2 4 DDR0_ZQ AV3 E1 20%
H16 AF12
DDR0_ZQ 6.3V
X5R-CERM 2
1% 4 DDR1_ZQ AP34 DDR1_ZQ E12 01005 H6 AF14
(DDR IMPEDANCE CONTROL) R33 1/32W
MF E23 H8 AF16
1
243 2
01005
AD33 F16 J10 AF18
1% AJ33 F5 J11 AF20
1/32W
MF AN33 G3 J12 AF22
01005 (80MA)
AU14 VDDCA G32 J13 AF24
AU5 BUCK4 1P2 H15 J14 AF26
AU9 J1 J15 AF28
12 4 PP1V2_SDRAM K3 J16 AF29
AA34 K30 J17 AF30
1 C68 1 C75 1 C88 AF1 L19 J5 AF31
1 C388 1 C390 10UF 1UF 0.47UF
20% 20% 20% AL33 M16 J7 AF32
56PF 56PF 2 6.3V 2 4V 2 4V
5% 5% CERM-X5R X6S X7S AR33 N15 J8 AF33
6.3V 6.3V 0402-1 0204 0204
2 NP0-C0G 2 NP0-C0G AT1 P10 J9 AF34
01005 01005 VSS VDDIOD(INCLUDED IN VDDQ)
AU16 R32 K6 AF6
AU7 VDD2 (340MA) R9 K7 AF8
B10 T20 L5 AG1
B11 U6 L7 AG11
B29 V2 M6 AG13
M34 V29 M7 AG15
P1 W21 N5 AG17
R1 W23 N7 AG19
W25 P6 AG21

C 23 16 14 13 12 10 3
PP1V8_SDRAM A10
A11
Y1
Y12
P7
R5
AG23
AG25
C
1 C883 1 C87 AB33 Y14 R7 AG27
0.47UF 4.3UF
20% 20% AF2 Y16 T6 AG28
4V 4V
2 X7S 2 X5R-CERM AT33 Y18 T7 AG29
0204 0610 VDD1 (20MA)
AU3 Y2 U5 AG30
AV16 Y20 U7 AG31
B32 Y22 V6 AG32
M33 Y24 V7 VSS AG33
T2 Y10 W5 AG34
Y29 W7 AG5
12 4 2
PP1V2 A3 Y3 Y6 AG6
AA2 Y32 Y7 AG9
1 C76 1 C85 1 C89 AD2 Y4 AH10
10UF 4.3UF 0.47UF
20% 20% 20% AG2 Y5 AH12
6.3V 4V 4V
POR CAPS 9/1/11 2 CERM-X5R 2 X5R-CERM 2 X7S AK2 Y8 PP1V8 AA7 AH14
19 18 14 12 11 10 7 6 5 3 2
0402-1 0610 0204 21 20
AN2 AB7 AH16
AR2 AC7 AH18
B12 AD7 AH20
B14 AE7 AH22
1 C72 1 C77 1 C953 B17 AF7 AH24
4.3UF 1UF 15PF B20 AG7 AH26
20% 20% 5%
4V 4V 16V B22 AH7 AH28
2 X5R-CERM 2 X6S 2 NP0-C0G-CERM
0610 0204 01005 B25 AJ7 VDDIO18_GRP1(45MA) AH33
B27 AK10 AH5
B30 AK11 AH6

B B5
B7
VDDQ (666MA) AK12
AK13
AH8
AJ1
B
B9 AK14 AJ11
C33 AK15 AJ13
D2 AK7 AJ15
F2 AK8 AJ17
G33 AK9 AJ19
J2 FL40 AJ21
K33 1KOHM-25%-0.2A AJ23
L2 1 2 PP1V8_XTAL K20 AJ25
N33 0201 K21 VDDIO18_GRP2 (8MA) AJ27
P2 AJ29
T33 C123 1 AJ32
2.2UF
U2 20% R29 VDDIO18_GPIO22(7MA) AJ5
4V
W33 X5R-CERM 2 AJ6
0201
AJ9
AJ28 AK33
AK28 VDDIO18_I2S0_MCK(18MA) AK5
AK6
AT10 PVDDP_I2C2_SDA
AR25
D33

12 4 PP1V2_SDRAM 12 4 2 PP1V2

1 C60 R11
1 R14
1 1
R25 1 C94 R28
1

0.01UF 10K
1 C78 10K
1 C90 4.7K 0.01UF 4.7K
A 10%
6.3V
2 X5R
1%
1/32W
MF
0.01UF
10%
2 6.3V
1%
1/32W
MF
0.01UF
10%
2 6.3V
1%
1/32W
MF
10%
6.3V
2 X5R
1%
1/32W
MF SYNC_MASTER=N/A SYNC_DATE=N/A A
01005 X5R
2 01005
X5R 01005 2 01005 PAGE TITLE
2 01005 2 01005
DDR0_VREF_CA 4
01005

DDR1_VREF_CA 4
01005

DDR0_VREF_DQ 4
DDR1_VREF_DQ 4 H5P IO POWER
DRAWING NUMBER SIZE

C66 C96 R29


1
Apple Inc. 051-9584 D
1
0.01UF
R13
1
1 C80 R24
1
1 C91
1
R27 1
0.01UF 4.7K REVISION
10K 0.01UF 10K 0.01UF 4.7K 1%
10%
6.3V
2 X5R
1%
1/32W 10% 1%
1/32W 10% 1%
1/32W
10%
6.3V
2 X5R
1/32W
MF
R
2.0.0
01005 MF 2 6.3V
X5R MF 2 6.3V
X5R MF 01005 2 01005 NOTICE OF PROPRIETARY PROPERTY: BRANCH
2 01005 01005 2 01005 01005 2 01005 THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
4 OF 23
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 4 OF 46
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

C86 MOVED TO PP1V1_SOC FROM PP1V2, PER SEG SIMS

12 PP1V1_SOC

C83 MOVED TO CPUB FROM 1V2_SDRAM PER SEG SIM RESULTS


1 C162 1 C171 1 C86
10UF 10UF 1UF
20% 20% 20% AA10 N18
PP1V1_CPUB AA16 A14 6.3V 6.3V 4V
12

U1
2 CERM-X5R 2 CERM-X5R 2 X6S
AA12 U1 N20
D
D 1 C83 1 C127 C135 C151 1 C158
AA18
AA20 H5P-SC58950C03
A15
A16
0402-1 0402-1 0204
AA14 H5P-SC58950C03
FCMSP
N22
AA26 N24
1UF 4.3UF 0.47UF 1UF 0.47UF AA22 FCMSP A17
20% 20% 20% 20% 20% SYM 8 OF 12 AA8 SYM 10 OF 12 N26
4V 6.3V 4V 4V AA24 A18
4V
2 X6S 2 X5R-CERM CERM CERM 2 X7S VDD_CPUB AB11 P11
0204 0610
1
0402
3 1
0402
3
0204 AC16 (716MA) A20 1 C164 1 C172 AB13 P13
AC18 A23 4.3UF 4.3UF
20% 20% AB15 P15
AC20 A26 2 4V
X5R-CERM 2 4V
X5R-CERM
2 4 2 4 AB9 P17
R46 XW1
SHORT-10L-0.1MM-SM
AC22 A29 0610 0610
AC10 P19
CPU0_SW_S 1
0.00 2 CPU0_SENSE 1 2
AC24 A33
AC12 P21
12
A34
0% AC14 P23
1/32W A4
MF AC26 P25
12 PP1V1_CPU0 01005 AE16 A5 C166 1 C175 1 C179 AC8 P27
AE18 A6 1UF 1UF 1UF
1 C104
1 C106 1 C103 C132 C113
1 C140 1 C146 AE20 A7
20%
4V
20%
4V
2 X6S
20%
4V
2 X6S
AD11 P9
4.3UF 1UF 0.47UF 4.3UF CERM AD13 R10
1UF 20% 20% 0.47UF 1UF 20% 20% AF19 A8 0402 0204 0204
20% 4V 4V 20% 20% 4V 4V AD15 R12
2 X5R-CERM 2 X6S 2 X7S 2 X5R-CERM AG16 A9 1 3
2 4V
X6S 0610 0204
6.3V
CERM
4V
CERM 0204 0610 AD9 R14
0204 0402 0402 AG18 AA11
VDD_CPU0 2 4 AE10 R16
1 3 1 3 AG20 AA13
(1500MA)
AE12 R18
C104 MOVED TO CPU0 FROM PP1V8 PER SEG SIMS 2 4 2 4
AH17 AA15 C169 1 C181 1 C177 AE14 R20
AH19 AA17 0.47UF 1UF 1UF
20% 20% 20% AE26 R22
R53 XW3
SHORT-10L-0.1MM-SM
AJ16 AA19
C173 6.3V
CERM 2 4V
X6S 2 4V
X6S AE8 R24
0.00 2 AJ20 AA21 1UF 0402 0204 0204
12 CPU1_SW_S 1 CPU1_SENSE 1 2 20% 1 3 AF11 R26
AA23 4V
0% CERM AF13 R8
1/32W AA25 0402
MF 2 4 AF15 T11
12 PP1V1_CPU1 01005 AE22 AA33 1 3
AF27 T13
1 C108 1 C142 1 C152
AE24 AA4
2 4
1 C178 1 C183 AF9 T15
C101 C133 C114 0.1UF 0.1UF
C POR CAPS 9/1/2011
1
1UF
20%
4.3UF
20%
2 4V
0.47UF
20%
1UF
20%
20%
2 4V
0.47UF 4.3UF
20%
2 4V
AF21
AF23
AA5
AA6
C174
20%
6.3V
2 X5R-CERM
20%
6.3V
2 X5R-CERM
AG10
AG12
T17
T19
C
2 4V
X6S
X5R-CERM
0610
6.3V
CERM
4V
CERM
X7S
0204
X5R-CERM
0610
AG22 AA9 1UF 01005 01005
20% AG14 T21
0204 0402 0402 AG24 VDD_CPU1 AB10 4V
1 3 1 3 CERM AG26 T23
AH21 (1500MA) AB12 0402
AG8 T25
AH23 AB14 1 3
2 4 2 4 AH11 T27
AH25 AB16
2 4 AH13 T9
AJ24 AB18
AH15 U10
AB20
AH27 U12
AB22 (VDD_SOC 3700MA)
AH9 VDD VDD U14
12 PP1V0_SRAM AB17 AB24
AJ10 U16
AB19 AB26 C181,C177,C174 CHANGED FROM 0.47UF TO 1UF
PER SEG - ZHENGGANG - 09/01/12 PRE-PROTO1 AJ12 U18
AB21 AB29
1 C100 1 C112 1 C117 1 C745 1 C145 1 C154 1 C746 AB23 AB32
AJ14 U20
10UF 4.3UF 4.3UF 1UF 1UF 0.47UF 0.47UF AJ26 U22
POR CAPS 5/6/2011 20% 20% 20% 20% 20% 20% 20% AB25 AB4
2 6.3V
CERM-X5R 2 4V
X5R-CERM 2 4V
X5R-CERM 2 4V
X6S 2 4V
X6S
4V
2 X7S 2 4V
X7S
AJ8 U24
AD17 VDD_SRAM VSS AB5
0402-1 0610 0610 0204 0204 0204 0204 K11 U26
AD19 (400MA) AB6
K13 U8
AD21 AB8
K15 V11
AD23 AC1
K17 V13
AD25 AC11
K23 V15
AF17 AC13
K25 V17
AF25 AC15
K27 V19
AC17
K9 V21
AC19
L10 V23
AC21
L12 V25
R953 19 18 14 12 11 10 7 6 5 4 3 2PP1V8 F19 PVDDP_FAST_SCAN_CLK (2MA) AC23
0.00 2 21 20
F20 AC25
L14 V9
PP3V0_NAND_XW 1 PP3V0_IO VDDIO30_FAST_SCAN_CLK (40MA)
B
6

0%
1/32W 1 C148 1 C139
G30
AR10
VDDIO30_USB11_DM (5MA) AC34
AC4
L18
L20
W10
W12
B
MF VDDIO30_GPIO_3V0 (7MA)
01005 56PF 0.22UF L22 W14
5% 20% AC5
6.3V 6.3V L24 W16
2 NP0-C0G 2 X5R
AC6
01005 0201 L26 W18
AN10 VDDIOD0 (2MA SPI3) AC9
L8 W20
AD10
M11 W22
AP11 VDDIOD1 AD12
(2MA I2C2) M13 W24
AD14
M15 W26
AD16
M17 W8
AB27 AD18
M19 Y11
AC27 VDDIOD2 (45MA NAND 1CH) AD20
M21 Y13
AD27 AD22
M23 Y15
AD24
M25 Y9
AD26
M27 Y19
V27 AD29
M9 Y21
W27 VDDIOD3 (45MA NAND 1CH) AD32
N10 Y23
Y26 AD5
N12 Y25
NAND POWER GROUP
AD6 XW4
SHORT-10L-0.1MM-SM N14
AD8
POR CAPS 12/14/2011 12 BUCK2_FB 1 2 N16
AJ18 VDD_ANA0(5MA) AE11
THERE WERE 10X 0.01UF HERE AJ22 VDD_ANA1 AE5
BUT THEY WERE NOT NEEDED PER P.CODD 1/6/11 (5MA)
AE6
Y17 VDD_ANA_TMPSADC0
AE9
19 18 14 12 11 10 7 6 5 4 3 2
PP1V8 K18 VDD_ANA_TMPSADC1
21 20 AK27
1 C111 1 C115 1 C134 1 C155 1 C161 AL13
10UF 4.3UF 10UF 10UF 10UF AM22
A 20%
6.3V
2 CERM-X5R
20%
4V
2 X5R-CERM
20%
6.3V
2 CERM-X5R
20%
6.3V
2 CERM-X5R
20%
6.3V
2 CERM-X5R AN21 SYNC_MASTER=N/A SYNC_DATE=N/A A
0402-1 0610 0402-1 0402-1 0402-1 AP16 PAGE TITLE
AP33
AR26
H5P SOC/CPU/SRAM PWR
DRAWING NUMBER SIZE
AT19
Apple Inc. 051-9584 D
REVISION
R
2.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
5 OF 23
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 5 OF 46
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

NAND
D D
FOR NAND CURRENT MEASUREMENT XW2
SM
5 PP3V0_NAND_XW 1 2 PP3V0_NAND
12

1 C105 1 C3 1 C185
1 C182 1 C307 1 C209 1 C187
0.47UF 1UF 10UF 10UF 10UF 10UF
20%
4V
20%
4V
1UF 20%
6.3V 20% 20% 20%
2 X7S 2 X6S 20% 2 CERM-X5R 6.3V 6.3V 6.3V
0204 0204 2 4V
X6S 0402-1
2 CERM-X5R 2 CERM-X5R 2 CERM-X5R
0402-1 0402-1 0402-1
0204 OMIT_TABLE OMIT_TABLE OMIT_TABLE OMIT_TABLE
PP1V2_NAND_VDDI
PP1V8 2 3 4 5 6 7 10 11 12 14 18 19
NOSTUFF 20 21

1 C50 1 C26 1 C95 1 C107 1 C627


1 C109 1 C605
10UF 1UF 15UF
2.2UF 2.2UF 20% 20% 4.3UF 20% 0.47UF POR CAPS 1/7/11
20% 20% 20% 4V 20%
4V 4V 1000MA 500MA 6.3V
2 CERM-X5R
4V
2 X6S 4V 2 X5R 4V
2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 0402 2 X7S
0201 0201 0402-1 0204 0610 0204
19 18 14 12 11 10 7 6 5 4 3 2 PP1V8
21 20

R78
1 1
R82 R137
1

C136

OB8

OC8
OD8
OE0
OF8

OA8
1 50K

B6
F2
M6

N1
N7

G0
100K 100K 0.01UF 1% OMIT
5% 5% 10% 1/32W
1/32W 1/32W 6.3V MF VDDI
MF MF 2 X5R 2 01005 VCC VCCQ
2 01005 2 01005 01005
FMI0_DQVREF 6
6 FMI0_CEN0 AE29 FMI0_CEN0 FMI1_CEN0 W28 FMI1_CEN0 6 6 FMI0_IO<0> G3 IO0-0 R48
1

AE30 FMI0_CEN1 U1 FMI1_CEN1 Y34 6 FMI0_IO<1> H2 IO1-0 U4 CE0* A5


A3
FMI0_CEN0 6
FMI0_CLE 6 5%
100K
AE32 H5P-SC58950C03FMI1_CEN2
FMI0_CEN2 AA32 1 C144 R143
1 6 FMI0_IO<2> J3 IO2-0 LGA-12X17 CLE0 1/32W
FCMSP ALE0 C1 FMI0_ALE 6 MF
AE34 Y33 0.01UF 50K 6 FMI0_IO<3> K2 2 01005

XXNM-XGBX8-MLC-PPN1.5-ODP
FMI0_CEN3 FMI1_CEN3 IO3-0
C AA29
AB30
FMI0_CEN4
FMI0_CEN5
SYM 4 OF 12 FMI1_CEN4
FMI1_CEN5
T34
V31
10%
6.3V
2 X5R
01005
1%
1/32W
MF
6 FMI0_IO<4>

6 FMI0_IO<5>
L5
K6
IO4-0
IO5-0
WE0* E3 FMI0_WE_L 6
NOSTUFF C
2 01005 RE0 B4
AA30 FMI0_CEN6 FMI1_CEN6 U34 6 FMI0_IO<6> J5 IO6-0
RE0* C7 45_FMI0_RE_L 6
AB28 FMI0_CEN7 FMI1_CEN7 U31 6 FMI0_IO<7> H6 IO7-0 1
R160
100K
AA28 U33 G1 DQS0 H4 45_FMI0_DQS 6 5%
6 FMI0_IO<0> FMI0_IO0 FMI1_IO0 FMI1_IO<0> IO0-1 1/32W
AA31 U29 J1 DQS0* F4 MF
FMI0_IO<1> FMI0_IO1 FMI1_IO1 FMI1_IO<1> IO1-1
6
2 01005
6 FMI0_IO<2> AB34 FMI0_IO2 FMI1_IO2 V32 FMI1_IO<2> L1 IO2-1 NOSTUFF
AB31 W32 N3 R/B0* E5 NAND_RDYBSY0_L
6 FMI0_IO<3> FMI0_IO3 FMI1_IO3 FMI1_IO<3> IO3-1
6 FMI0_IO<4> AD31 FMI0_IO4 FMI1_IO4 W34 FMI1_IO<4> N5 IO4-1
CE1* C5 FMI1_CEN0 6
6 FMI0_IO<5> AE31 FMI0_IO5 FMI1_IO5 W31 FMI1_IO<5> L7 IO5-1
CLE1 C3 FMI1_CLE 6
6 FMI0_IO<6> AD34 FMI0_IO6 FMI1_IO6 Y30 FMI1_IO<6> J7 IO6-1
ALE1 D2 FMI1_ALE 6
6 FMI0_IO<7> AE33 FMI0_IO7 FMI1_IO7 Y31 FMI1_IO<7> G7 IO7-1
WE1* E1 FMI1_WE_L 6
AC28 FMI0_WENN/RE_P FMI1_WENN/RE_P U28 RE1 D4
6 FMI0_ALE AC31 FMI0_ALE FMI1_ALE W29 FMI1_ALE 6 RE1* D6 45_FMI1_RE_L 6
6 FMI0_CLE AD30 FMI0_CLE FMI1_CLE Y28 FMI1_CLE 6
6 FMI0_WE_L AC29 FMI0_WEN FMI1_WEN V28 FMI1_WE_L 6 DQS1 M4 45_FMI1_DQS 6

6 45_FMI0_RE_L AC30 FMI0_REN FMI1_REN W30 45_FMI1_RE_L 6 DQS1* K4


6 45_FMI0_DQS AC33 FMI0_DQS FMI1_DQS V34 45_FMI1_DQS 6
AC32 FMI0_DQSN V33 R/B1* E7 NAND_RDYBSY1_L
FMI1_DQSN
FMI0_DQVREF AD28 FMI0_DQVREF FMI1_DQVREF V30 FMI0_DQVREF
6 6
PP17
P2MM
VREF G5 FMI0_DQVREF 6
R8
19 18 14 12 11 10 7 6 5 4 3 2 PP1V8 AA27 PVDDP_FMI0 PVDDP_FMI1 U27 PP1V8 2 3 4 5 6 7 10 11 12 14 18 19
PP19
P2MM
SM
1 NAND_TCKC OA0 TCKC ZQ A1 PPN_ZQ 1
243 2
PP
21 20 20 21 SM
1 NAND_TMSC OB0 TMSC 1%
6 FMI0_DQVREF AE28 FMI0_VREF FMI1_VREF Y27 FMI0_DQVREF 6
PP VSS VSSQ 1/32W
MF
01005
B B

B2
F6
L3

A7
M2
OC0
OD0
OE8
OF0
G8
1 NOTE: NAND PADS SHOULD BE SHIELDED FROM TRACES WITH A GROUND PLANE
P4MM FMI0_IO<0>
PP2 SM PP 6

P4MM 1 45_FMI0_RE_L
PP3 SM PP 6

P4MM 1 45_FMI0_DQS 6
PP14 SM PP

A SYNC_MASTER=N/A SYNC_DATE=N/A A
PAGE TITLE

H5P W/ NAND
DRAWING NUMBER SIZE

Apple Inc. 051-9584 D


REVISION
R
2.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
6 OF 23
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 6 OF 46
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

PP1V8
12 7 2
PP1V0 2 3 4 5 6 7 10 11 12 14 18 19
20 21
AL10 B1 E31 M14 MIPI0D_VREG
U1 U1 1 C191

AK18
AK19
AK20
AK21
AK22
AK23
AK24
AK25
AK26

MIPI0D_VDD10_PLL AM21
MIPI1D_VDD10_PLL AM23

MIPI0D_VDD18 AM19
MIPI1D_VDD18 AM25

MIPI0D_VREG_0P4V AM20
MIPI1D_VREG_0P4V AM24
AL11 B13 E32 M18 1 C53 1 C57 1 C266 MIPI1D_VREG 0.1UF
AL12 H5P-SC58950C03 B16 F1 H5P-SC58950C03 M20 0.1UF 0.1UF 4.3UF C6 1 1 C7 20%
AL14 FCMSP B18 F10 FCMSP M22 20%
6.3V 20% 20%
4V 2200PF 2200PF 2 6.3V
X5R-CERM
2 X5R-CERM 6.3V 2 X5R-CERM 10% 10% 01005
AL15 SYM 11 OF 12 B19 F11 SYM 12 OF 12 M24 2 X5R-CERM MIPI_VDD10 6.3V 6.3V
01005 01005 0610 X5R-CERM 2 2 X5R-CERM
AL29 B2 F12 M26 (28MA) 01005 01005

D
AL32
AL4
B21
B23
F13
F14
M5
M8
D

(2MA)
PP1V8

(2MA)
2 3 4 5 6 7 10 11 12 14 18 19
20 21
AL5 B24 F15 N1
AL6 B26 F17 N11 1
R37 R39
1 1
R41 R42
1
AL7 B28 F18 N13 1.00K 1.00K 1.00K 1.00K
5% 5% 5% 5%
AL8
AL9
B3
B33
F21
F22
N17
N19
AR3 MIPI_VSYNC ISP0_FLASH U1 AR12 1/32W
MF
1/32W
MF
1/32W
MF
1/32W
MF
H5P-SC58950C03 ISP0_PRE_FLASH AM11 CAM0_TORCH 15
2 01005 2 01005 2 01005 2 01005
AM1 B34 F27 N21 FCMSP
21 90_CAM0_TO_AP_MIPI_DATA0_P AU21 MIPI0C_DPDATA0 ISP0_SCL AR6 AP_TO_CAM_RF_SCL 15 21
AM17 B4 F3 N23 SYM 5 OF 12
21 90_CAM0_TO_AP_MIPI_DATA0_N AV21 MIPI0C_DNDATA0 ISP0_SDA AH1 AP_BI_CAM_RF_SDA 15 21
AM18 B6 F30 N25
AM26 B8 F31 N27
21 90_CAM0_TO_AP_MIPI_DATA1_P AU20 MIPI0C_DPDATA1 ISP1_FLASH AU11
AM5 C10 F32 N31
21 90_CAM0_TO_AP_MIPI_DATA1_N AV20 MIPI0C_DNDATA1 ISP1_PRE_FLASH AM12
AM6 C11 F4 N34 AP_TO_CAM_FF_SCL
ISP1_SCL AL2 11
AM7 C13 F6 N4
21 90_CAM0_TO_AP_MIPI_DATA2_P AU18 MIPI0C_DPDATA2 ISP1_SDA AU6 AP_BI_CAM_FF_SDA 11
AN11 C14 F7 N6
90_CAM0_TO_AP_MIPI_DATA2_N AV18 MIPI0C_DNDATA2
AN14 C15 F8 P12 21

SENSOR0_CLK AN9 45_AP_TO_CAM_RF_CLK_R


R38
1 2
33.2 45_AP_TO_CAM_RF_CLK 21
AN17 C16 F9 P14
AN18 C17 G1 P16 21 90_CAM0_TO_AP_MIPI_DATA3_P AU17 MIPI0C_DPDATA3 SENSOR0_RST AP6 AP_TO_CAM_RF_SHUTDOWN 21 1% 1/32W MAIN CAMERA
90_CAM0_TO_AP_MIPI_DATA3_N AV17 MIPI0C_DNDATA3 MF 01005
AN19 C18 G10 P18 21

SENSOR1_CLK AP2 45_AP_TO_CAM_FF_CLK_R


R40
1
33.2
2 45_AP_TO_CAM_FF_CLK 11
AN20 C2 G12 P20
AN22 C23 G14 P22 21 90_CAM0_TO_AP_MIPI_CLK_P AU19 MIPI0C_DPCLK SENSOR1_RST AM10 AP_TO_CAM_FF_SHUTDOWN 11
1% 1/32W FF CAMERA
AN23 C24 G16 P24 21 90_CAM0_TO_AP_MIPI_CLK_N AV19 MIPI0C_DNCLK
SHUTDOWN IS ALSO
1 C259 1 C274 1 C280
MF 01005
1 C284
MIPI1D_DNDATA0 AV27 56PF
AN24 C25 G2 P26 RESET CAM1 5% 56PF 56PF 56PF
AU26 MIPI0D_DPDATA0 6.3V
AN25 C26 G22 P5 19 90_AP_TO_LCM_MIPI_DATA0_P MIPI1D_DPDATA0 AU27 2 NP0-C0G 5%
6.3V
5%
6.3V
5%
6.3V
01005 2 NP0-C0G 2 NP0-C0G 2 NP0-C0G
19 90_AP_TO_LCM_MIPI_DATA0_N AV26 MIPI0D_DNDATA0
AN26 C28 M31 P8 01005 01005 01005
AN32 C29 G31 R11 MIPI1D_DNDATA1 AV29
19 90_AP_TO_LCM_MIPI_DATA1_P AU25 MIPI0D_DPDATA1 MIPI1D_DPDATA1 AU29
AN5 C3 G34 R13

C AN7
AN8
C30
C31
G4
G6
R15
R17
19 90_AP_TO_LCM_MIPI_DATA1_N AV25 MIPI0D_DNDATA1
MIPI1D_DNCLK AV28
C
19 90_AP_TO_LCM_MIPI_DATA2_P AU23 MIPI0D_DPDATA2 MIPI1D_DPCLK AU28
AP10 C32 G8 R19
19 90_AP_TO_LCM_MIPI_DATA2_N AV23 MIPI0D_DNDATA2
AP13 C4 H1 R21
AP17 C5 H11 R23 MIPI1C_DPDATA0 AU30 90_CAM1_TO_AP_MIPI_DATA0_P 11

19 90_AP_TO_LCM_MIPI_DATA3_P AU22 MIPI0D_DPDATA3 MIPI1C_DNDATA0 AV30 90_CAM1_TO_AP_MIPI_DATA0_N 11


AP18 C6 H13 R25
19 90_AP_TO_LCM_MIPI_DATA3_N AV22 MIPI0D_DNDATA3
AP19 C7 H17 R27
AP20 C8 H18 R30 MIPI1C_DPDATA1 AU32
19 90_AP_TO_LCM_MIPI_CLK_P AU24 MIPI0D_DPCLK MIPI1C_DNDATA1 AV32
AP21 C9 H19 R33
19 90_AP_TO_LCM_MIPI_CLK_N AV24 MIPI0D_DNCLK
AP22 D1 H2 R34
AP23 D10 H20 R4 MIPI1C_DPCLK AU31 90_CAM1_TO_AP_MIPI_CLK_P 11

AP24 D11 H21 R6 MIPI1C_DNCLK AV31 90_CAM1_TO_AP_MIPI_CLK_N 11

AP25 D12 H22 T1 MIPI_VSS


VSS VSS
AP26 D13 H3 T10
VSS VSS

AL18
AL19
AL20
AL21
AL22
AL23
AL24
AL25
AL26
AP4 D14 H30 T12
AP7 D15 H31 T14
AR1 D16 H32 T16
AR11 D17 H33 T18
AR17 D23 H4 T22
AR18 D24 H5 T24 LPDP NOT USED, NO CAP NEEDED ON THIS PIN
AR19 D25 H7 T26 PP1V8 2 3 4 5 6 7 10 11 12 14 18 19
20 21
AR20 D26 H9 T28 12 7 2 PP1V0

LPDP_PAD_LN1_AVDD AP29
LPDP_PAD_LN0_AVDD AP28

LPDP_PAD_CMN_AVDDH AL27
LPDP_PAD_CMN_AVDD AM27

LPDP_PAD_AUX_AVDD AP27
AR21 D27 J27 T29

DP_PAD_DVDD J25

DP_PAD_AVDDX G25

DP_PAD_AVDDP0 G24

DP_PAD_AVDD1 G23
DP_PAD_AVDD0 J23

DP_PAD_AVDD_AUX J24

DAC_AVDD18D L30

DAC_AVDD18A N29
AR22 D28 J3 T30 C58 1 1 C268
AR23 D29 J30 T31 0.1UF 0.1UF
20% 20%
AR24 D3 J31 T32 6.3V 2 6.3V
X5R-CERM 2 X5R-CERM

B AR27 D30 J32 T5 01005 01005


B

(15MA)
AR28 D31 J33 T8

(12MA)

(12MA)
(11MA)
AR29 D32 J4 U1

(1MA)

(2X 65MA)
AT14 D4 J6 U11

(8MA)
AT16 D5 K1 U13
N30 DAC_VREF DAC_OUT3 H34
AT17 D6 K10 U15
AT18 D8 K12 U17
P29 DAC_IREF U1 DAC_OUT2 J34
AT2 D9 K14 U19 H5P-SC58950C03
(0MA LPDP)
AT20 E10 U30 U21 FCMSP
P28 DAC_COMP SYM 6 OF 12 DAC_OUT1 K34
AT21 E11 K19 U23
AT22 E13 K2 U25
G26 DP_PAD_DC_TP
AT23 E14 K22 U32
AT24 E15 K24 U4
F26 DP_PAD_R_BIAS
AT25 E16 K31 U9
AT26 E17 K4 V10 DP_HPD AU8
AV12 LPDP_HPD
AT27 E18 K5 V12
AT28 E19 K8 V14
AT34 LPDP_PAD_AUXP
AT29 E2 L1 V16
AR34 LPDP_PAD_AUXN DP_PAD_AUXP A28
AT31 E20 L11 V18
AT32 E21 L13 V20 DP_PAD_AUXN A27
AM34 LPDP_PAD_TX0P
AT5 E22 L15 V22
AL34 LPDP_PAD_TX0N
AT8 E24 L17 V24
AU1 E25 L21 V26 DP_PAD_TX0P A25
AJ34 LPDP_PAD_TX1P DP_PAD_TX0N A24
AU2 E26 L23 V5
AH34 LPDP_PAD_TX1N
AU33 E28 L25 V8
AU34 E3 L27 W11 DP_PAD_TX1P A22
AR30 LPDP_PAD_R_BIAS DP_PAD_TX1N A21
A AU4 E30 L3 W13
SYNC_MASTER=N/A SYNC_DATE=N/A A

H24 DP_PAD_AVSS_AUX
AV1 E4 L31 W15

AN29 LPDP_PAD_AVSS2
AN28 LPDP_PAD_AVSS1
AN27 LPDP_PAD_AVSS0
PAGE TITLE

F24 DP_PAD_AVSSP0
AV14 E5 L4 W17
H5P VIDEO

F25 DP_PAD_AVSSX

F23 DP_PAD_AVSS1
H23 DP_PAD_AVSS0

N28 DAC_AVSS18A2
H25 DP_PAD_DVSS

M30 DAC_AVSS18D
AV2 E6 L6 W19
AV33 E7 L9 W4 DRAWING NUMBER SIZE

AV34 E8 M10 W6 Apple Inc. 051-9584 D


REVISION
AV5 E9 M12 W9 R
2.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
7 OF 23
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 7 OF 46
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

BUTTON FLEX (VIBE DRIVER, BUTTONS, ANC REF MIC, STROBE, STROBE_NTC)
FL21
120-OHM-210MA
2 1 CAM_RF_TO_STROBE_NTC 15
STROBE:
01005 STROBE NTC
1 C397
D 5%
56PF
6.3V
2 NP0-C0G
D
01005

FL47
120-OHM-210MA
CODEC_TO_MIC2_BIAS_CONN 1 2 PP_CODEC_TO_MIC2_3_BIAS
8 10 11
01005
WIFI FLEX PAC: R977 1 C45 1
NO_XNET_CONNECTION=TRUE
C216
0.00 2 PP3V0_ALWAYS_CONN 56PF
VDD (3.0V) 16 12 PP3V0_ALWAYS 1
0%
8 5%
6.3V
2 NP0-C0G
1.0UF
20%
6.3V
1/32W 01005 2 X5R
MF
01005
ON MLB ----> 516S1040 PLUG
0201-1
MIC2 (ANC REF MIC):
1 C697 516S1041 RCPT (FLEX) MIC2/3 BIAS,
56PF
5%
6.3V 2 MIC2_P,_N
2 NP0-C0G
01005
J2 XW41
105847-018 SHORT-10L-0.1MM-SM
M-ST-SM
20 NO_XNET_CONNECTION=TRUE
1
19

1 2
MIC2_TO_CODEC_N 8 9
BUTTON_TO_AP_HOLD_KEY_CONN_L CAM_RF_TO_STROBE_NTC_CONN
MIC2_TO_CODEC_P 8 9 22
9 8 MIC2_TO_CODEC_N 3 4

22 9 8 MIC2_TO_CODEC_P 5 6
CODEC_TO_MIC2_BIAS_CONN 7 8
8
9 10 BB_TO_ANT_PAC_SPI_MOSI_BUTTON_CONN
C244 1
56PF
BB_TO_ANT_PAC_SPI_SCLK_BUTTON_CONN 11 12 PP_VIBE 8 5%
6.3V
BUTTON_TO_AP_RINGER_A_CONN 13 14 NP0-C0G 2

C BUTTON_TO_AP_VOL_UP_CONN_L
BUTTON_TO_AP_VOL_DOWN_CONN_L
15
17
16
18
PP3V0_ALWAYS_CONN 8
BB_TO_ANT_PAC_SPI_CS_BUTTON_CONN_L
01005
C
FL3 FL71
120-OHM-210MA
120-OHM-210MA 21
1 2 BB_TO_ANTENNA_PAC_SPI_SCLK 23
3 BUTTON_TO_AP_HOLD_KEY_L 1 2 22
01005

C314 1
01005 1 DZ1 FL70
12V-33PF
100PF
5%
01005-1 120-OHM-210MA WIFI FLEX PAC:
10V
NP0-C0G 2
01005
2 1 2 BB_TO_ANTENNA_PAC_SPI_MOSI 23 PAC SPI BUS
01005
FL7 FL72
120-OHM-210MA 120-OHM-210MA
BUTTON_TO_AP_RINGER_A 1 2 1 2
13 3 BB_TO_ANTENNA_PAC_SPI_CS_L 23
C313 1 01005 1 DZ7 C382 1 C384 1 1 C383
01005
100PF 12V-33PF
5% 01005-1 56PF 56PF 56PF
BUTTONS: 10V
NP0-C0G 2 2 5%
6.3V
5%
6.3V
5%
2 6.3V
RINGER, HOLD, 01005 01005 2 01005 2 01005

VOL_UP/DOWN FL8
120-OHM-210MA
13 3 BUTTON_TO_AP_VOL_DOWN_L 1 2
PGND_VIBE_RETURN
VIBE RETURN
01005 8
C311 1 1 DZ2
100PF 12V-33PF
5%
10V
01005-1 C1201 1
NP0-C0G 2 2 100PF
01005 5%
16V
NP0-C0G 2
FL46 01005
120-OHM-210MA
B 13 3 BUTTON_TO_AP_VOL_UP_L 1 2 B
01005
C197 1 1 DZ3 PP_STRB_DRIVER_TO_LED 15
STROBE:
100PF 12V-33PF
5%
10V 2
01005-1 1 C208 1 C241 LED COOL
NP0-C0G 2 27PF 100PF
01005 5% 5%
16V 16V
2 NP0-C0G 2 NP0-C0G
01005 01005

NOSTUFF
U70 NOSTUFF
LP5907UVX-3.3V R70
A1 VIN USMD 0.00 2 PP_VIBE
23 22 15 12 PP_BATT_VCC VOUT A2PP3V3_VIB 1 8

0%
3 VIB_LDO_EN B1 VEN
1/32W
MF
1 C118 C120 1
GND 01005 4.7UF 100PF
20% 5%
6.3V 16V
R69 1 2 X5R
B2

R970 TO VIB NET MINIMIZE 0402 NP0-C0G 2


100K 01005
DCR
5%
1/32W
MF
01005 2 R970 K
0.00 2
NOSTUFF 12 PP3V0_VIBE 1 D3
LLP-DFN1006-2
0% BAS40LP
1/32W
VIBE DRIVE MF
01005
A

PGND_VIBE_RETURN 8

A 3
SYNC_MASTER=N/A SYNC_DATE=N/A A
PAGE TITLE

XW80 D BUTTON FLEX B2B


SM Q7 DRAWING NUMBER SIZE
3 VIB_PWM 1 2 VIBE_PWM_G 1 G DMN3730UFB4 Apple Inc. 051-9584 D
S DFN1006H4-3 REVISION
1
R9401 SYM_VER_1 R
2.0.0
10K NOTICE OF PROPRIETARY PROPERTY: BRANCH
1% 2
1/32W THE INFORMATION CONTAINED HEREIN IS THE
MF PROPRIETARY PROPERTY OF APPLE INC.
2 01005 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
8 OF 23
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 8 OF 46
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

L67 AUDIO CODEC


D D

AUDIO I/O
(ANALOG MIC IN, DIG MIC IN, HPOUT, LINEOUT, RECEIVER OUT, MIKEYBUS)
TO DO: REVIEW AUDIO MIC PATHS,
WHICH BIAS OUTPUT USED FOR WHICH MIC,
WHICH INPUT FOR WHICH MIC, ETC.
C222
0.1UF
1 2
20% X5R
4V 01005
22 17 MIC1_TO_CODEC_P
VOICE MIC
17 MIC1_TO_CODEC_N C223
0.1UF 1 C227 1 C230
1 2 56PF 56PF
5% 5%
20% X5R 6.3V 6.3V
4V 01005 2 NP0-C0G 2 NP0-C0G
01005 01005

U21
C220 WLCSP
50PF LIMIT ON AOUTX PINS
C 0.1UF MIC1_TO_CODEC_L67_P G2 AIN1+ PRIMARY
SYM 1 OF 3
AOUT1+ K7 CODEC_TO_RCVR_P 11 C

CS42L67-CWZR-A0
1 2
MIC1_TO_CODEC_L67_N G1 AIN1- (VOICE) MIC AOUT1- L7 CODEC_TO_RCVR_N 11
20% X5R
4V 01005
EXTMIC_TO_CODEC_P EXTMIC_TO_CODEC_L67_P F4 AIN2+ HEADPHONE AOUT2+ L5 CODEC_TO_HAC_P 11
17
HEADPHONE MIC EXTMIC_TO_CODEC_L67_N F3 AIN2- MIC AOUT2- K5 CODEC_TO_HAC_N 11
17 EXTMIC_TO_CODEC_N C221 F2 AIN3+ ANALOG
0.1UF LINEOUT_REF K8
1 2 F1 AIN3- MIC IN
20% X5R
1 C226 1 C229 LINEOUTA J8
4V 01005 56PF 56PF RCVR_TO_CODEC_RCVR_TEST_L67 E4 AIN4+ ANC LINEOUTB H8
5% 5% REF MIC2
6.3V 6.3V E3 AIN4-
2 NP0-C0G 2 NP0-C0G N/C,INTERNAL WEAK BIAS TO VCM
01005 01005 HPOUTA J9 CODEC_TO_HPHONE_L 17

MIC2_TO_CODEC_L67_P E1 AIN5+ ANC HPOUTB K9 CODEC_TO_HPHONE_R 17


HEADPHONES
MIC2_TO_CODEC_L67_N E2 AIN5- REF MIC1
HS3 K1 CODEC_TO_HPHONE_HS3
C224 MIC3_TO_CODEC_L67_P D1 AIN6+ ANC
17
C235 1 C236 1

0.1UF HS4 L2 CODEC_TO_HPHONE_HS4 56PF 56PF


MIC3_TO_CODEC_L67_N D2 AIN6- ERROR MIC 17
5% 5%
1 2 6.3V 6.3V
NP0-C0G 2 NP0-C0G 2
20% X5R D3 AIN7+ ANALOG HS3_REF L9 CODEC_TO_HPHONE_HS3_REF 17 01005 01005
HPHONE_TO_CODEC_HPHONE_TEST_L67
4V 01005
D4 AIN7- LINEIN HS4_REF L8 CODEC_TO_HPHONE_HS4_REF 17
22 8 MIC2_TO_CODEC_P N/C,INTERNAL WEAK BIAS TO VCM
HPDETECT G8 HPHONE_TO_CODEC_DET 17
ANC REF MIC 8 MIC2_TO_CODEC_N C225 HAC_TO_CODEC_TEST_L67 C1 AIN8+ ANALOG
LINEIN
0.1UF C2 AIN8- DN G10
N/C,INTERNAL WEAK BIAS TO VCM
1 2
A6 DMIC1_SD DP F10
20% X5R
4V 01005 1 C228 1 C231 B6 DMIC1_SCLK MBUS_REF F11 C138
56PF 56PF 100PF
5% 5% A3 DMIC2_SD 1 2
2 6.3V
NP0-C0G 2 6.3V
NP0-C0G OMIT_TABLE
A2 DMIC2_SCLK
01005 01005 5%
R102 10V
15.0 2 NP0-C0G
01005
C55 1
B 0.1UF
1 2 90_CODEC_BI_TRISTAR_MIKEYBUS_L67_N
5%
1/32W
MF
01005 1 C51 90_CODEC_BI_TRISTAR_MIKEYBUS_N 16
B
90_CODEC_BI_TRISTAR_MIKEYBUS_L67_P
100PF MIKEY TO TRISTAR
20% X5R 5% NOSTUFF
4V 01005 R103 10V
2 NP0-C0G
90_CODEC_BI_TRISTAR_MIKEYBUS_P 16
15.0 2 01005
22 11 MIC3_TO_CODEC_P 1
ANC ERROR MIC C61 5% MF
C143
11 MIC3_TO_CODEC_N 1/32W 01005
0.1UF OMIT_TABLE 100PF
1 2 1 C64 1 C65 1 2
20% X5R 56PF 56PF
4V 01005 5% 5% 5%
6.3V 6.3V 10V
2 NP0-C0G 2 NP0-C0G NP0-C0G
01005 01005 01005

R102, R103 VALUE CONTROLLED VIA BOMOPTION


15OHM FOR TRISTAR, 20OHM FOR TRISTAR2
C354
0.01UF
11 RCVR_TO_CODEC_RCVR_TEST 1 2

10%
6.3V
X5R
01005

C356
0.01UF
17 HPHONE_TO_CODEC_HPHONE_TEST 1 2

10%
6.3V
X5R
01005

A C362
0.01UF SYNC_MASTER=N/A SYNC_DATE=N/A A
11 HAC_TO_CODEC_TEST 1 2 PAGE TITLE

10%
6.3V
L67 AUDIO CODEC (1/2)
X5R DRAWING NUMBER SIZE
01005
Apple Inc. 051-9584 D
REVISION
R
2.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
9 OF 23
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 9 OF 46
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

L67 AUDIO CODEC


D D
POWER, MICBIAS DIGITAL SYSTEM I/O

XW43
SHORT-10L-0.1MM-SM
23 14 13 12 PP_VCC_MAIN 1 2 PP_VCC_MAIN_CODEC
3 45_AP_TO_CODEC_I2S_MCLK A9 MCLK U21 A1
C5
WLCSP
1 C422 1 C421 1 C420 SYM 3 OF 3 B1
0.1UF 0.1UF

CS42L67-CWZR-A0
10UF 3 45_AP_TO_CODEC_ASP_I2S0_BCLK C10 ASP_SCLK
20% 10% 10% F9
6.3V 6.3V
2 X5R 6.3V
2 X5R 3 AP_TO_CODEC_ASP_I2S0_LRCLK B11 ASP_LRCK
OMIT_TABLE 2 CERM-X5R D5
0402-1 201 201 3 AP_TO_CODEC_ASP_I2S0_DOUT C9 ASP_SDIN D7
CODEC_TO_AP_ASP_I2S0_DIN A8 ASP_SDOUT
20 19 18 14 12 11 7 6 5 4 3 2PP1V8 PCB: C421 AT U21.L6 3
E5
21
1 C413 3 45_AP_TO_CODEC_VSP_I2S4_BCLK E9 VSP_SCLK E6
0.1UF 3 AP_TO_CODEC_VSP_I2S4_LRCLK E8 VSP_LRCK/FSYNC E7
20% GND
4V AP_TO_CODEC_VSP_I2S4_DOUT D10 F5
2 X5R 3 VSP_SDIN
01005 CODEC_TO_AP_VSP_I2S4_DIN D11 F6
3 VSP_SDOUT
23
13 F7
4 3 PP1V8_SDRAM 15 3 45_AP_TO_CODEC_XSP_I2S2_BCLK B8 XSP_SCLK
12 10 F8
16 14
1 C414 1 C416 15 3 AP_TO_CODEC_XSP_I2S2_LRCLK B7 XSP_LRCK/FSYNC G7
10UF 0.1UF 15 3 AP_TO_CODEC_XSP_I2S2_DOUT C7 XSP_SDIN/DAC2B_MUTE
20% 20% H3
FL96 2 6.3V
CERM-X5R 2 4V
X5R 15 3 CODEC_TO_AP_XSP_I2S2_DIN A7 XSP_SDOUT H4
120-OHM-210MA 0402-1 01005
J3
2 1 PP1V7_VA_L67 3 AP_TO_CODEC_SPI3_CS_L B5 CS* J4
C AP_TO_CODEC_SPI3_CLK B4
C

VCP G11
A11
B10

VPROG_CP H11
CCLK
01005 1 C412 3

VA J1

VL B9

VP L6
AP_TO_CODEC_SPI3_MOSI B3 CDIN
1.0UF PP1V8_SDRAM
3
20% 23 16 14 13 12 10 4 3
3 CODEC_TO_AP_SPI3_MISO A4 CDOUT

VD
6.3V
2 X5R
0201-1 KEEP THESE CAPS AT CODEC PINS
R145
1
3 CODEC_TO_AP_INT_L G4 INT*
1 C232 1.00K
5%
U21 FLYP J11 PP_CODEC_VHP_FLYP
4.7UF
20%
1/32W
MF 13 CODEC_TO_PMU_MIKEY_INT_L G5 WAKE*
WLCSP 6.3V
2 X5R-CERM1 2 01005
D8
SYM 2 OF 3 G9 PP_CODEC_VHP_FLYC 402 G3 D9
CODEC_RESET_L RESET*

CS42L67-CWZR-A0
FLYC H10 1 C233 KEEP THESE CAPS AT CODEC PINS E10
B2
J10 PP_CODEC_VHP_FLYN 4.7UF E11
TSTI C3
20%
J5 MIC1_BIAS FLYN H9 6.3V
2 X5R-CERM1
1 C425 A5
C4
402 4.7UF C11
20% C6 TSTO
+VCP_FILT K11 PP_CODEC_VCPFILT+ XW48
SHORT-10L-0.1MM-SM
6.3V
2 X5R-CERM1
C8
402
1
R100 J6 MIC1_BIAS_FILT GNDCP0 K10 PGND_CODEC_GNDCP 1 2 D6
2.21K GNDCP1 L11
1%
1/32W
1 C429
MF -VCP_FILT L10 PP_CODEC_VCPFILT- 4.7UF TSTO MUST BE NC
2 01005 20%
6.3V
PP_EXTMIC_BIAS_IN L4 MIC2_BIAS_IN SPEAKER_VQ J7 PP_CODEC_SPKR_VQ 2 X5R-CERM1
402
KEEP THESE CAPS AT CODEC PINS 1 C237 PP_EXTMIC_BIAS L3 MIC2_BIAS
1 C234
1.0UF GNDP K6 4.7UF
20% K4 20%
PP_EXTMIC_BIAS_FILT_IN MIC2_BIAS_FILT_IN 6.3V
2 6.3V
X5R FILT+ H1 PP_CODEC_FILT+ 2 X5R-CERM1
0201-1 402
PP_EXTMIC_BIAS_FILT K3 MIC2_BIAS_FILT FILT- H2
C424 1 KEEP THIS CAP AT CODEC PINS
1 C238 17 PP_CODEC_TO_MIC1_BIAS H7 MIC3_BIAS GNDA J2 10UF
20%
4.7UF PGND_MIC1_TO_CODEC_RET_FILT G6 MIC3_BIAS_FILT 6.3V
20% CERM-X5R 2 KEEP THIS CAP AT CODEC PINS
B 6.3V
2 X5R-CERM1
11 8 PP_CODEC_TO_MIC2_3_BIAS H6 MIC4_BIAS
0402-1
B
L1 GNDHS0
K2 GNDHS1

402
PGND_MIC2_3_TO_CODEC_RET_FILT H5 MIC4_BIAS_FILT
A10 GNDD

C218
4.7UF
2 1

20%
6.3V
X5R-CERM1
402

C219
4.7UF
2 1

20%
6.3V
X5R-CERM1
402

A SYNC_MASTER=N/A SYNC_DATE=N/A A
PAGE TITLE

L67 AUDIO CODEC (2/2)


DRAWING NUMBER SIZE

Apple Inc. 051-9584 D


REVISION
R
2.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
10 OF 23
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 10 OF 46
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

CG FLEX B2B FL13


120-OHM-25%-250MA-0.5DCR
(FF CAM, PROX, ALS, RECEIVER, ANC ERROR MIC)
7 45_AP_TO_CAM_FF_CLK 1 2
01005
1 C198
56PF
5%
2 6.3V
NP0-C0G
L35
90-OHM-50MA
FL15 01005 TCM0605-1
1 4
D
SYM_VER-2
120-OHM-25%-250MA-0.5DCR
D 7 AP_TO_CAM_FF_SCL 1 2
90_CAM1_TO_AP_MIPI_CLK_N
90_CAM1_TO_AP_MIPI_CLK_P
7

7
2 3
01005 1 C192
FRONT CAM: 5%
56PF THIS ON ONE MLB ---> 516S0986 RCPT L39
516S0987 PLUG 90-OHM-50MA
2 6.3V
CLK, I2C, SHDN FL12 NP0-C0G
01005 45_AP_TO_CAM_FF_CLK_CONN 1
TCM0605-1
SYM_VER-2 4
120-OHM-25%-250MA-0.5DCR 90_CAM1_TO_AP_MIPI_DATA0_N 7

1 2 90_CAM1_TO_AP_MIPI_DATA0_P
7 AP_TO_CAM_FF_SHUTDOWN
7
2 3
01005
1 C202 J1
56PF AP_TO_CAM_FF_SCL_CONN
AA22L-S034VA1 FL44
5% F-ST-SM
2 6.3V AP_TO_CAM_FF_SHUTDOWN_CONN 39 70-OHM-300MA
FL14
NP0-C0G
01005
AP_BI_CAM_FF_SDA_CONN 35 36 2 1 OMIT_TABLE PP2V8_CAM_AVDD 12 21
FRONT CAM:
120-OHM-25%-250MA-0.5DCR
01005-1 1 C193
50 MA POWER AND MIPI
7 AP_BI_CAM_FF_SDA 1 2 C402 1
4.7UF
01005 1 2 56PF 20%
5%
1 C196 3 4 MIPI GROUND 6.3V 2 6.3V
X5R
NP0-C0G 2 603
56PF 5 6 90_CAM1_TO_AP_MIPI_CLK_CONN_N 01005
5%
6.3V 7 8 90_CAM1_TO_AP_MIPI_CLK_CONN_P
2 NP0-C0G
01005 9 10 MIPI GROUND FL23
11 12
70-OHM-300MA
PP3V0_PROX 90_CAM1_TO_AP_MIPI_DATA0_CONN_N
FL45 45_PROX_TO_CUMULUS_RX_CONN 13 14 90_CAM1_TO_AP_MIPI_DATA0_CONN_P
1 2 PP1V8 2
21
3 4 5 6 7 10 12 14 18 19 20

120-OHM-25%-250MA-0.5DCR 01005-1

2 1
PROX GROUND 15 16 MIPI GROUND C407 1 C410 1 NO_XNET_CONNECTION=TRUE
12 11 PP3V0_PROX_ALS CUMULUS_TO_PROX_RX_EN_1V8_CONN 17 18 PP2V8_FCAM_CONN 0.1UF 56PF
20% 5%
5 MA 01005 AP_BI_I2C2_SDA_ALS_CONN 19 20 FCAM ANALOG GROUND 4V 6.3V
C194 1 C63 1
ALS_TO_AP_INT_CONN_L 21 22 PP1V8_FCAM_CONN
X5R 2
01005
NP0-C0G 2
01005
1.0UF 56PF
20% 5% AP_TO_I2C2_SCL_ALS_CONN 23 24 NOTE: MIC3_TO_CODEC_P
PROX_RX SIGNAL MUST BE TREATED WITH CARE 6.3V 6.3V

C PROX: POWER, R125


X5R 2
0201-1
NP0-C0G 2
01005 PP3V0_ALS
CODEC_TO_HAC_CONN_N
25
27
26
28
NOTE: MIC3_TO_CODEC_N
PP_CODEC_TO_MIC3_BIAS_CONN
C
RX, RX_EN 0.00 1 CODEC_TO_HAC_CONN_P 29 30 FCAM_TO_AP_ALS_INT_CONN_L
1 C67
18 45_PROX_TO_CUMULUS_RX 2
31 32 PGND_IRLED_K
56PF
5% MIC3_TO_CODEC_P 9 22
MF 0% 6.3V
01005 1/32W 1 C62 33 34 NOTE: IRLED_A 2 NP0-C0G
01005
MIC3_TO_CODEC_N 9
56PF
5%
2 6.3V MIC3
NP0-C0G
01005
37
40
38
(ANC ERROR MIC)
FL58 2 NO_XNET_CONNECTION=TRUE
C380
18 CUMULUS_TO_PROX_RX_EN_1V8 2 1 XW42
SHORT-10L-0.1MM-SM
1
1UF
20%
120-OHM-210MA 6.3V
01005
1 C201 1 2 X5R
0201 FL48
56PF 120-OHM-210MA
5%
6.3V
2 NP0-C0G 1 2
01005
PP_CODEC_TO_MIC2_3_BIAS 8 10
FL2 01005
1 2
1 C253
3 AP_BI_I2C2_SDA 56PF
5%
120-OHM-210MA 2 6.3V
NP0-C0G
01005 01005
FL57 R133
1 2 1 DZ16 R451 0.00 2
3 ALS_TO_AP_INT_L 1 DZ18 12V-33PF 11.5
1%
1 FCAM_TO_AP_ALS_INT_L 3
CAM1 ALS INT
120-OHM-210MA 12V-33PF 01005-1 1/20W
0% MF
01005-1 1/32W 01005
01005 2 MF NOTE: J1.30 IS GND ON POR BOARDS,
2 201 2 FF_ALS_INT
FL20 J1.30 IS ALS_INT FROM FF CAM FOR
ALS: POWER, R132 SPECIAL CONFIG OF PROTO2
(CONTROLLED VIA BOMOPTION)
3 AP_TO_I2C2_SCL 1 2 0.00 2
I2C, INT PCB: PLACE THESE AT J1 CONN PGND_IRLED_DRAIN 1

B 120-OHM-210MA
01005
1

5%
C211
56PF
1 C212
56PF
1 C210
56PF
0%
1/32W
MF
01005 B
2 6.3V
NP0-C0G
5%
6.3V
5%
6.3V 1 DZ19 1 DZ17 3 NO_FF_ALS_INT
FL4 01005
2 NP0-C0G
01005
2 NP0-C0G
01005 12V-33PF
01005-1
12V-33PF
01005-1 Q1
120-OHM-25%-250MA-0.5DCR 2
D
1 2
2 DMN3730UFB4
12 11 PP3V0_PROX_ALS DFN1006H4-3
0.25 MA 01005 G 1 CUMULUS_TO_PROX_TX_EN_BUFF 18
1 C56 1 C199 S
0.1UF
20% 5%
56PF SYM_VER_1 1
R85
2 4V 2 6.3V 1.00M
X5R NP0-C0G 5%
01005 01005 2 1/32W
MF
2 01005 PROX: PWR, TX EN
FL65
70-OHM-300MA
1 2 IRLED = 104-128MA
PP3V0_PROX_IRLED 12
01005-1
R95
1
C200 1 1 C44 1 C256
15.8K 56PF 0.1UF 4.7UF
1% 5% 20% 20%
1/32W 6.3V 4V 6.3V SPECIAL Z = 0.60 MM MAX
MF NP0-C0G 2 2 X5R 2 X5R
9 CODEC_TO_HAC_N 2 01005 01005 01005 0402
HAC_TO_CODEC_TEST
HAC 9 CODEC_TO_HAC_P
9
-21.4 DB SIGNAL OF HAC VPP
R94
1

10K
FL64 1%
1/32W
70-OHM-300MA MF
1 2 2 01005

01005-1

FL51
A 70-OHM-300MA SYNC_MASTER=N/A SYNC_DATE=N/A A
2 1 PAGE TITLE
01005-1
R3
1 CG FLEX B2B
10K DRAWING NUMBER SIZE
1%
1/32W Apple Inc. 051-9584 D
MF REVISION
2 01005 CODEC_TO_RCVR_CONN_P
RECEIVER 9 CODEC_TO_RCVR_P
CODEC_TO_RCVR_N
9 RCVR_TO_CODEC_RCVR_TEST
R
2.0.0
9 -21.4 DB SIGNAL OF RCVR VPP CODEC_TO_RCVR_CONN_N NOTICE OF PROPRIETARY PROPERTY: BRANCH
R9
1
THE INFORMATION CONTAINED HEREIN IS THE
15.8K PROPRIETARY PROPERTY OF APPLE INC.
FL52 1%
1/32W
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
70-OHM-300MA MF I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 11 OF 23
2 1 2 01005 II NOT TO REPRODUCE OR COPY IT
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
01005-1 IV ALL RIGHTS RESERVED 11 OF 46
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
23 14 13 12 10 PP_VCC_MAIN
Q3 Q4
CSD58874W1015 CSD58874W1015
PP1V1_CPU0 C2 PP1V1_CPU1 C2
5 BGA 5 BGA
B2 B2
1 C74 1 C92 1 C250 1 C265 1 C293 1 C257 1 C262 1 C264 1 C378 A2
S
A2
S
10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF G G
20% 20% 20% 20% 20% 20% 20% 20% 20% C1 C1
6.3V
2 CERM
6.3V
2 CERM
6.3V
2 CERM
6.3V
2 CERM
6.3V
2 CERM
6.3V
2 CERM
6.3V
2 CERM
6.3V
2 CERM
6.3V
2 CERM
1 C273 1 C301
B1 15UF B1 15UF
0402 0402 0402 0402 0402 0402 0402 0402 0402 20% 20%
OMIT_TABLE OMIT_TABLE OMIT_TABLE OMIT_TABLE OMIT_TABLE OMIT_TABLE A1 4V A1 4V
D 2 X5R D 2 X5R
OMIT_TABLE OMIT_TABLE OMIT_TABLE 0402 0402

D 23 14 13 12 10 PP_VCC_MAIN 12 VCENTER
D

1.5UH-20%-2A-0.142OHM

1.5UH-20%-2A-0.142OHM
PP1V1_CPU0_FET PP1V1_CPU1_FET
1 C688 C689 1 1 C686 C687 1 1 C294 1 C299

SHORT-10L-0.1MM-SM

NO_XNET_CONNECTION=TRUE
10UF 10UF

XW10

XW16
NO_XNET_CONNECTION=TRUE
56PF 100PF 56PF 100PF

SHORT-10L-0.1MM-SM
C269 1 C271 C276 C278 C281 C282 C295 C302 C305 C312 C318

2
20% 20% 1 1 1 1 1 1 1 1 1 1
5% 5% 5% 5% 6.3V
C289 1

SAME POLARITY
6.3V 2 CERM
6.3V 16V 6.3V 16V 2 CERM 0.01UF 15UF 15UF 15UF 15UF 15UF 15UF 15UF 15UF 15UF 15UF

2
SAME POLARITY
2 NP0-C0G NP0-C0G 2 2 NP0-C0G NP0-C0G 2 0402 10% 20% 20% 20% 20% 20% 0.01UF 20% 20% 20% 20% 20%

TFA201610G-SM
TFA201610G-SM
01005 01005 01005 01005 0402 OMIT_TABLE 6.3V 4V 4V 4V 4V 4V 10% 4V 4V 4V 4V 4V
OMIT_TABLE VPUMP X5R 2 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 6.3V 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R

1
X5R 2

L18

L23
01005 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402
01005
23 22 15 8 PP_BATT_VCC C16 1 NOSTUFF
NOSTUFF
0.01UF

1.5UH-20%-2A-0.142OHM

1.5UH-20%-2A-0.142OHM
10%
C1
B2
B1
A2

10V
X5R 2
Q5

1
201
D
CSD68803W15 L26
BGA 2.2UH-20%-1.7A-200MOHM

2
TFA201610G-SM
TFA201610G-SM
G 1 2 PP1V1_CPUB 5

L12

L13
TFA201610G-SM
U7
A1
R55 BATTERY_TO_PMU_SENSE
1 C310 1 C317 1 C319
22
D2013B28HGAHVCC2 10UF 10UF 10UF
USB_VBUS_DETECT 1
68.1K2 VCENTER
20% 20% 20%
S 2 12 BGA 2 6.3V 2 6.3V 2 6.3V
1/32W 01005 E1 CERM-X5R CERM-X5R CERM-X5R
(1 OF 3) VPUMP L21
1% MF
XW20 0402-1 0402-1 0402-1
C3
C2
B3
A3

1
C291 1 C260 1 E2 IBAT
SHORT-10L-0.1MM-SM
10UF 10UF CPUA_EN B19CPU0_SWITCH 2 1 2
20% 20% NO_XNET_CONNECTIO=TRUE
6.3V 6.3V C1 VBAT CPUA_SW_S N21 5 CPU0_SW_S
CERM-X5R 2 CERM-X5R 2
0402-1 0402-1 CPUA_SW_OUT L19 CPU0_SW_CONTROL L11-L13 POLARITY ALL SAME
PP1V1_SOC 5
ACT_DIO C2 ACT_DIO BUCK0A_LXM A12 BUCK0A_LXM

2.2UH-20%-1.7A-200MOHM

2.2UH-20%-1.7A-200MOHM

2.2UH-20%-1.7A-200MOHM
BUCK0A_LXL A14 BUCK0A_LXL 1 C285 1 C288 1 C290 1 C292
J1 BUCK0A_FB D21 BUCK0A_FB 15UF 15UF 15UF 15UF
20% 20% 20% 20%
J2 VCENTER 4V
2 X5R
4V
2 X5R
4V
2 X5R
4V
2 X5R
CPUB_EN A22 CPU1_SWITCH 2 0402 0402 0402 0402

2
L1 K19

TFA201610G-SM

TFA201610G-SM

TFA201610G-SM
17 PP5V0_USB_PROT CPUB_SW_S 5 CPU1_SW_S

C L11 VBUS
C

2.2UH-20%-1.7A-200MOHM
L2 J19
C444 C248 1 CPUB_SW_OUT CPU1_SW_CONTROL

L14

L15

L16
1
1UF 2.2UH-20%-1.7A-200MOHM BUCK0B_LXM A16 BUCK0B_LXM 1 C283
56PF 10%
5% 25V 1 2 VSW_CHG H1 BUCK0B_LXL A18 BUCK0B_LXL 0.01UF
2 25V X5R 2
NP0-C0G-CERM 0402 CHG_LX
10%
0201
TFA201610G-SM H2 BUCK0B_FB C22 BUCK0B_FB 2 6.3V
X5R PP1V8_SDRAM 3 4 10 12 13 14 16 23

D4 01005

NO_XNET_CONNECTION=TRUE
1

SHORT-10L-0.1MM-SM
PP_VCC_MAIN
SOD523
F1 BUCK0C_LX A20 BUCK0C_LX
NOSTUFF 1 C379 1 C385 1 C389 1 C391

2
23 14 13 12 10
A K 15UF 15UF 15UF

TFA201610G-SM
F2 VCC_MAIN BUCK0C_FB C21 BUCK0C_FB 20% 20% 20% 15UF

XW15
2
4V 4V 4V 20%

2.2UH-20%-1.7A-200MOHM
2 X5R 2 X5R 2 X5R
C189 C203 C217 C245

L17
1 1 1 1 K1 VCC_MAIN_S 4V
PMEG3010EB/S500 0402 0402 0402 2 X5R
10UF 10UF 1.0UF 10UF BUCK2_LXL A6 BUCK2_LXL 0402

2.2UH-20%-1.7A-200MOHM
20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V A13 A4

1
2 CERM-X5R 2 CERM-X5R 2 X5R 2 CERM-X5R VDD_BUCK0A BUCK2_LXM BUCK2_LXM
0402-1 0402-1 0201-1 0402-1 A17 A2 BUCK2_LXR PP1V2_SDRAM
OMIT_TABLE OMIT_TABLE OMIT_TABLE VDD_BUCK0B BUCK2_LXR 4 12

1
A21 VDD_BUCK0C BUCK2_FB D2 BUCK2_FB
A5
5
TO SOC 1 C296 1 C303 1 C308 1 C316

2
VDD_BUCK2LM 10UF 10UF 10UF 10UF

TFA201610G-SM
TFA201610G-SM
PP1V8_SDRAM

SAME POLARITY
23 16 14 13 12 10 4 3
A1 VDD_BUCK2R BUCK3_LX H22 BUCK3_LX 20% 20% 20% 20%
C190 C204 C239 C246 2 6.3V 2 6.3V 2 6.3V 2 6.3V

NO_XNET_CONNECTION=TRUE
1 1 1 1

L24

L25
G22 VDD_BUCK3 BUCK3_FB E22 BUCK3_FB CERM-X5R CERM-X5R CERM-X5R CERM-X5R

SHORT-10L-0.1MM-SM
10UF 10UF 10UF 10UF 1 C261 0402-1 0402-1 0402-1 0402-1
20% 20% 20% 20% A9 VDD_BUCK4
2 6.3V
CERM-X5R 2 6.3V 2 6.3V 2 6.3V 1.0UF
CERM-X5R CERM-X5R CERM-X5R
0402-1 0402-1 0402-1 0402-1
20%
10V VBUCK3_SW K22
OMIT_TABLE OMIT_TABLE OMIT_TABLE OMIT_TABLE 2 X5R-CERM
Q3 VDD_LDO1_6 WDIG_SW K21 PP1V8_GRAPE 18
0201-1

XW17
2
P4 VDD_LDO2 CPU1V8_SW L22 PP1V8 2 3 4 5 6 7 10 11 12 14 18 19
20 21
Q19 VDD_LDO3_8
12 4 PP1V2_SDRAM Q10 VDD_LDO4_7 BUCK4_LXL A10 BUCK4_LXL

1
1 C195 1 C205 1 C243 1 C247 1 C258
N22 VDD_LDO5 BUCK4_LXM A8 BUCK4_LXM
10UF 10UF 10UF 10UF P5 VDD_LDO9 BUCK4_FB D1 BUCK4_FB
20% 20% 20% 20% 1.0UF
6.3V
2 CERM-X5R 6.3V
2 CERM-X5R 2 6.3V 6.3V
2 CERM-X5R 20% P8 VDD_LDO10
CERM-X5R 2 10V
0402-1 0402-1 0402-1 0402-1 X5R-CERM P7
OMIT_TABLE OMIT_TABLE OMIT_TABLE OMIT_TABLE 0201-1 VDD_LDO11 VBUCK4_SW M21
P6 VDD_LDO12

B CALIBRATION
Q12 VDD_LDO16 CPU1V2_SW M22 PP1V2 2 4
B
PLACE CLOSE TO PMU Q1 P3
22 17 BATTERY_TO_PMU_NTC 12 NTC_FOREHEAD_P TDEV1 VLDO1 PP3V0_ALWAYS 8 16
C207 1
1
R54 NTC_CAM_P P2 TDEV2 VLDO2 Q5 PP1V7_VA_L20
19-25 MILLIOHM
100PF 3.92K
0.1%
1 C255 12

NTC_PA_P Q2 TDEV3 VLDO3 P18 PP3V3_USB 2


15

U11
5% 1/20W 100PF 12
16V
NP0-C0G 2 MF 5%
16V 12 NTC_H5P_P M2 TDEV4 VLDO4 P9 PP2V5_CAM0_AF 21 TPS22924X
01005 2 0201 2 NP0-C0G CSP
TCAL L4 TCAL VLDO5 P22 PP3V0_NAND 6 23 16 14 13 12 10 4 3 PP1V8_SDRAM A2 A1 PP1V8 2 3 4 5 6 7 10 11 12 14 18 19
01005 20 21
M4 TBAT VLDO6 Q4 PP3V0_ACC 16 B2 VIN VOUT B1
VLDO7 P10 PP3V0_IMU 20 1 C17
1 C277 TBD: VALUE MUST BE TUNED
Q17 VDD_VIB VLDO8 P19 PP3V0_PROX_ALS 11 4.7UF 23 22 19 16 14 13 2 RESET_1V8_L C2 ON
4.7UF 20%
Q18 VIB Q6 20% 2 6.3V GND
P20 VIB_PWM_EN
VLDO9 PP3V0_VIBE
Q9 PP3V0_PROX_IRLED 11
8
6.3V
2 X5R-CERM1
X5R-CERM1
402
R56
10.2 2

C1
VLDO10 402 1 PP2V5_CAM0_AF_COMP 21
VLDO11 Q8 PP2V8_CAM_AVDD 11 21
1%
OSC32I P1 XTAL1 VLDO12 Q7 PP1V0 2 7 1/32W
MF
OSC32O N1 XTAL2 VLDO16 Q13 PP1V0_SRAM 01005
Y2 ON_BUF P17 PP1V8_ALWAYS 3
5

32.768K-20PPM-12.5PF 1 C270
1 C272 XW14
1 2 1 C267 1 C987 0.1UF
0.1UF
10% SM
0.1UF 1.0UF
C251 1 2012-1 1 C263 20% 20% 10%
6.3V 2 6.3V
X5R
1 2 PGND_CAM0_AF_RET 21
6.3V 6.3V 2 X5R 201
18PF 18PF 2 X5R-CERM 2 X5R
2% 2% 0201-1 201 NOSTUFF
16V 16V 01005 NOSTUFF THIS XW LINK AT PMU AREA
CERM 2 2 CERM
01005 01005 NOTE: PLACE C987 UNDERNEATH C270
NOTE: ROUTE TRACES BETWEEN LDO AND CAP TO ALLOW 0.050 OHM ESR

FOREHEAD NTC CAMERA NTC H5P NTC RADIO PA NTC


A NTC_FOREHEAD_P 12 NTC_CAM_P 12 NTC_H5P_P 12 NTC_PA_P 12 SYNC_MASTER=N/A SYNC_DATE=N/A A
I394 I390 I382 I649 PAGE TITLE

NO_XNET_CONNECTION=TRUE
2 R108 NO_XNET_CONNECTION=TRUE
2 R110 NO_XNET_CONNECTION=TRUE 2 R57 NO_XNET_CONNECTION=TRUE R90
2 AGATHA PMU(1/2)
DRAWING NUMBER SIZE
C159 1 NO_XNET_CONNECTION=TRUE C167 1 NO_XNET_CONNECTION=TRUE C168 1 NO_XNET_CONNECTION=TRUE
C322 1 NO_XNET_CONNECTION=TRUE
051-9584 D
100PF 100PF 100PF Apple Inc.
100PF 5%
16V
5%
16V
5%
16V REVISION
5%
NP0-C0G 2 NP0-C0G 2 NP0-C0G 2
16V
NP0-C0G 2 PLACE CLOSE TO PMU 01005
PLACE CLOSE TO PMU
01005 PLACE CLOSE TO PMU 01005 PLACE CLOSE TO PMU
R
2.0.0
01005 1 1 1 10KOHM-1%-0.31MA 1
10KOHM-1%-0.31MA NOTICE OF PROPRIETARY PROPERTY: BRANCH
10KOHM-1%-0.31MA
0201
SHORT-10L-0.1MM-SM
XW6 10KOHM-1%-0.31MA
0201 XW8
SHORT-10L-0.1MM-SM
0201 XW9
SHORT-10L-0.1MM-SM
0201
SHORT-10L-0.1MM-SM
XW11 THE INFORMATION CONTAINED HEREIN IS THE
NTC_CAM_N PROPRIETARY PROPERTY OF APPLE INC.
NTC_FOREHEAD_N 1 2 1 2 NTC_H5P_N 1 2 NTC_PA_N 1 2 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
12 OF 23
100PF IS NEEDED FOR SAMPLING CAP IN ADC IN PMU III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 12 OF 46
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

U7
D2013B28HGAHVCC2
BGA
A15 VSS_BUCK0AB G14
A3 (3 OF 3) G15
VSS_BUCK2
D J22
A7
VSS_BUCK3 G16
G17
D
VSS_BUCK24
A11 VSS_BUCK40 G18
H7
A19 VSS_BUCK0BC H8
G4 VSSA_BUCK2 H9
E19 VSSA_BUCK3 H10
E21 VSSA_BUCK40 H11
H12
P16 VSS_WLED H13
P15 VSS_LCM H14
H15
D22 VSS_REF H16 R921
H17 R65 1/32W
G1 H18 1
200K 2 1
6.34K2 TRISTAR_TO_PMU_USB_BRICKID
16
1% MF MF 01005 CHESTNUT_TO_PMU_ADCIN7
G2 VSS_SW_CHG J7 1/20W 201 1% 13 14
J8
D7 J9 C323
0.1UF C327 1
D8 J10
1 2
1 C343 0.01UF
D9 J11 0.01UF 10%
10% X5R 10% 6.3V 2
D10 J12 6.3V 201 2 6.3V
X5R X5R
D11 J13 C325 01005 01005

D12 J14 1.0UF


1 2
D13 J15 AMUX VOLTAGE LIMIT IS APPROX. = VDD_REF = PP_VCC_MAIN U7 20% X5R
D14 J16 D2013B28HGAHVCC2 6.3V 0201-1
D15 J17 BGA
1.8V ---> 13 3
BUTTON_TO_AP_HOLD_KEY_BUFF_L K6 AMUX_A0 (2 OF 3) IREF P21 IREF C326
C D16
D17
J18
K7 1.8V ---> 13 3 BUTTON_TO_AP_MENU_KEY_BUFF_L
K5
K4
AMUX_A1 VREF Q21
B22
VREF
0.1UF
1 2
PP_VCC_MAIN 10 12 14 23
C
D18 K8 1.8V ---> 13 8 3 BUTTON_TO_AP_RINGER_A AMUX_A2 VDD_REF VDD_REF
10% X5R R68
1

E6 K9 1.8V ---> 8 3 BUTTON_TO_AP_VOL_UP_L J6 AMUX_A3 VDD_RTC F22 VDD_RTC 6.3V 201 220K
5%
VSS 8 3 BUTTON_TO_AP_VOL_DOWN_L J5 AMUX_A4 1/32W
E7 K10 1.8V ---> BRICK_ID M1 13 TRISTAR_TO_PMU_USB_BRICKID_R EMC REVIEW REQUESTS THIS GO TO 1K MF
J4
E8 K11 19 14 LCD_PWR_EN AMUX_A5
ADC_IN7 K2 R487 2 01005
E9 K12 3.33V ---> 13 TRISTAR_TO_PMU_USB_BRICKID_R H6 AMUX_A6 0.00 2
1 E75_TO_PMU_ACC_DETECT 16 17
14 13 CHESTNUT_TO_PMU_ADCIN7 H5 AMUX_A7 ADC_REF F21
E10 K13 0%
22 PMU_AMUX_AY H4 AMUX_AY ACC_ID Q20 1/32W KEEPACT 3
E11 K14 MF
23 RADIO_TO_PMU_ADC_SMPS1_MSMC_1V05
F4 AMUX_B0 01005
E12 K15 BASEBAND ---> DPHP B18
E13 K16 23 RADIO_TO_PMU_ADC_SMPS3_MSME_1V8 F5 AMUX_B1
FW_DPHP_DET N2 NOSTUFF R66
1

16 TRISTAR_TO_PMU_MIKEYBUS_TEST_POS
E4 AMUX_B2 1.00M
E14
VSS
K17
16 TRISTAR_TO_PMU_MIKEYBUS_TEST_NEG
E5 AMUX_B3
ACC_DET B21 E75_TO_PMU_ACC_DETECT_R R488
1
5%
E15 K18 1.8V ---> BUTTON1 B12 BUTTON_TO_AP_MENU_KEY_BUFF_L 3 13
0.00 1/32W
MF
23 13 45_PMU_TO_WLAN_CLK32K
D4 AMUX_B4 0%
E16 L5 1.8V ---> BUTTON2 B13 BUTTON_TO_AP_HOLD_KEY_BUFF_L 3 13
1/32W 2 01005
23 RADIO_TO_PMU_ADC_LDO6_RUIM_1V8
D5 AMUX_B5 MF
E17 L6 BASEBAND ---> BUTTON3 B14 BUTTON_TO_AP_RINGER_A 3 8 13 2 01005
2 AP_TO_PMU_TEST_CLKOUT D6 AMUX_B6
E18 L7
23 RADIO_TO_PMU_ADC_LVS1 B1 AMUX_B7 KEEPACT G21
F6 L8
22 PMU_AMUX_BY
B2 AMUX_BY SHDN F19
F7 L9
F8 L10 PMU_AP_TO_LCM_RESET_L
19
B3 GPIO1 LCM_LX Q15
F9 L11 R60 BB_TO_PMU_HOST_WAKE
23 B4 GPIO2 VBOOST_LCM P12
F10 L12
1.00K2 B5 P13
23 PMU_TO_BB_RST_L 1 BB_RST_PMU_R_L GPIO3 VLCM1
F11 L13 5% 16 3 TRISTAR_TO_AP_INT B6 GPIO4 VLCM2 Q11
1/32W
F12 L14 MF 23 13 45_PMU_TO_WLAN_CLK32K B7 GPIO5 LCM2_EN B20
01005
F13 L15 22 3 AP_BI_BATTERY_SWI B8 GPIO6 VLCM3 P11
F14 L16 23 WLAN_TO_PMU_HOST_WAKE B9 GPIO7
WLED_LX Q16
F15 L17 R63 10 CODEC_TO_PMU_MIKEY_INT_L
B10 GPIO8
10K VOUT_LED Q22
F16 L18 23 PMU_TO_BT_REG_ON 1 2 BT_REG_ON_R B11 GPIO9
B F17
F18
M5
M6
5%
1/32W
MF
01005 R64
10K
23 BT_TO_PMU_HOST_WAKE B15
B16
GPIO10
WLED1
WLED2
P14
Q14
B
23 PMU_TO_WLAN_REG_ON 1 2 WIFI_REG_ON_R GPIO11
5% MF
G5 M7 DRIVEN TO VCC_MAIN ------------> 1/32W 0100523 PMU_TO_BB_VBUS_DET B17 GPIO12
G6 M8
20 16 15 14 3 AP_TO_I2C0_SCL G19 SCL
G7 M9
20 16 15 14 3 AP_BI_I2C0_SDA H19 SDA
G8 M10 SM
G9 M11 14 3 45_AP_TO_PMU_DWI_CLK 1 2 XW26 PMU_DWI_CLK M19 DWI_CK
SM
G10 M12 14 3 45_AP_TO_PMU_DWI_DO 1 2 XW27 PMU_DWI_DI M18 DWI_DI
SM
G11 M13 3 45_AP_TO_PMU_DWI_DI 1 2 XW28 PMU_DWI_DO M17 DWI_DO
G12 M14 ACCESS POINTS PMU_RESET_IN J21 RESET_IN
G13 M15 RESET_1V8_L
22 19 16 14 12 2
D19 RESET*
23
M16 3 PMU_TO_AP_IRQ_L H21 IRQ*

23 16 14 12 10 4 3 PP1V8_SDRAM
I2C ADDRESS: 1110100X
6 74LVC1G32
2 WDOG 2 SOT891
FROM H5P
TRISTAR_TO_PMU_HOST_RESET 1
U14 4 ACTIVE HIGH
16 GPIO1 PP1V8_SDRAM OUPUT 0
NC GPIO2 INPUT, W/O PD
FROM TRISTAR 5 3
1 C99 GPIO3
GPIO4
PP1V8_SDRAM OUPUT 0
PP1V8_SDRAM OUPUT 0
R591 100PF GPIO5 PP1V8_SDRAM OUPUT 0
5% GPIO6 INPUT, W/ PU IN BATTERY PCM
100K 2 10V
NP0-C0G GPIO7 INPUT, W/ PD IN PMU
5% 01005 GPIO8 INPUT, W/ PU TO PP1V8_SDRAM
1/32W GPIO9 PP1V8_SDRAM OUTPUT 0
MF GPIO10 INPUT, W/ PD IN PMU
01005 2 GPIO11 PP1V8_SDRAM OUTPUT 0
GPIO12 VCC_MAIN OUPUT 0
A RESET_IN
RESET*
ACTIVE HIGH INPUT W/ INTERNAL 200K PD
OPEN DRAIN OUTPUT
SYNC_MASTER=N/A SYNC_DATE=N/A A
IRQ* OPEN DRAIN OUTPUT PAGE TITLE

AGATHA PMU(2/2)
DRAWING NUMBER SIZE

Apple Inc. 051-9584 D


REVISION
R
2.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
13 OF 23
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 13 OF 46
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

CHESTNUT, BACKLIGHT DRIVER

D404 DISPLAY PMU (INTERSIL CHESTNUT, 338S1168) NOSTUFF

D (TI CHESTNUT, 338S1172) U10 D


TPS799L57
WCSP
14 PP6V0_LCM_BOOST C3 IN OUT C1 PP5V7_TO_LCD_AVDDH 14 19

19 14 13 LCD_PWR_EN
A1 EN NR A3 U10_BYPASS
23 14 13 12 10 PP_VCC_MAIN

GND
I2C0: 0100111X NOSTUFF
1 1 C562 C47 1 1 C121
1 C592
4.7UF B2 4.7UF
56PF 20% OMIT_TABLE 4.7UF C122 1 20%
L19 5%
16V 6.3V PP_CHESTNUT_CP
20%
6.3V 0.01UF 2 6.3V
X5R
X5R-CERM1 2
2.2UH-20%-1.7A-200MOHM
2 NP0-C0G
01005 402 U3 2 X5R
0402
10%
6.3V 2
0402
NOSTUFF
TFA201610G-SM
OMIT_TABLE
ISL97751IIA0PZ
WLCSP CP C4
1 C54 X5R
01005
10UF
D1 VIN CN E4 20% NOSTUFF
10V
2 2 X5R-CERM
PP_CHESTNUT_LXP B2 LXP PP_CHESTNUT_CN 0402-1

18 LCM_TO_AP_HIFA_BSYNC_BUFF A2 SYNC VPOS B3


B4
14 PP6V0_LCM_BOOST
D3 SCL VPOS
AP_TO_I2C0_SCL
20 16 15 14 13 3
R512
20 16 15 14 13 3 AP_BI_I2C0_SDA D2 SDA VNEG E3 1 C662
1 C329 PP5V7_TO_LCD_AVDDH_CHESTNUT 1 0.00 2 PP5V7_TO_LCD_AVDDH
NOSTUFF PN5V7_SAGE_AVDDN 22UF 14 14 19

C3 EN E2
19 18
56PF 20% 0%
R49 19 14 13 LCD_PWR_EN VSUB 5%
16V 2 10V
X5R-CERM
1/32W
MF
0.00 2 2 NP0-C0G 0603
19 18 14 12 11 10 7 6 5 4 3 2
21 20
PP1V8 1 CHESTNUT_NRESET C2 NRST VO1 A4 PP5V7_SAGE_AVDDH 18
1 C330 1 C762 01005
01005

0% 10UF 56PF
E1 AMUX A3

PGND
CHESTNUT_TO_PMU_ADCIN7 PP5V7_TO_LCD_AVDDH_CHESTNUT 20% 5%
1/32W
MF
13 VO2 14
2 10V 2 16V OPTION TO ZERO OUT U10 AND POWER IT DOWN

C1 AGND
01005 TO DO: ADD 1NF CAP HERE ON ADCIN7 X5R-CERM NP0-C0G
VO3 A1 PP5V1_GRAPE_VDDH 18
0402-1 01005

R61 1 C52 1 C69

B1
D4
0.00 2 10UF 10UF
RESET_1V8_L 1
1 C441 20% 20%
23 22 19 16 13 12 2
1UF 10V
2 X5R-CERM
10V
2 X5R-CERM SAGE NEG BOOST TIMING INFO:
C 0%
1/32W
MF
01005
20%
6.3V
2 X5R
0201
0402-1
OMIT_TABLE
0402-1
2 MS NOMIAL START UP DELAY FOR LCM POWER SEQUENCING C
0 MS DELAY AT SHUTDOWN
REFER TO RADAR 12410499. THIS IS PART OF BUILD MATRIX ACTIVE DISCHARGE 2MS TO RAIL DOWN
TO POTENTIALLY IMPLEMENT LCD PANIC FUNCTION

D404 BACKLIGHT DRIVER


I2C0: 1100011X

B 22UH-20%-0.38A-0.876OHM
L3
NSR0620P2XXG
D1 B
23 14 13 12 10 PP_VCC_MAIN 1 2 PP_WLED_LX A K
VLF302510T-SM
C252 1 1 C297 U23
SOD-923-HF
10UF 10UF
20%
6.3V
20%
6.3V
LM3534TMX-A1
CERM-X5R 2 2 CERM-X5R A3 SW BGA OVP D1 PP_LCM_BL_ANODE 19
0402-1 0402-1
OMIT_TABLE OMIT_TABLE C3 IN
ILED1 D3 PP_LCM_BL_CAT1 1 C27 1 C97 1 C98
AP_BI_I2C0_SDA A1 SDA ILED2 D2 PP_LCM_BL_CAT2
19
1 C213 2.2UF 2.2UF 2.2UF
20 16 15 14 13 3
A2
19
56PF 20% 20% 20%
AP_TO_I2C0_SCL SCL 5%
20 16 15 14 13 3
SCK B2 45_AP_TO_PMU_DWI_CLK 3 13
16V
2 NP0-C0G 2 25V
X5R-CERM 2 25V
X5R-CERM 2 25V
X5R-CERM
0402-1 0402-1 0402-1
19 18 14 12 11 10 7 6 5 4 3 2 PP1V8 C1 VIO_SPI SDI C2 45_AP_TO_PMU_DWI_DO 3 13
01005
21 20 LCM_DESENSE
PP1V8_SDRAM B1 HWEN
23 16 13 12 10 4 3
1 C214
GND 56PF
5%
16V
B3
2 NP0-C0G
01005

NOTE: STACKED TO MEET VOLTAGE REQ, LOOK INTO 18+V CAPS

A SYNC_MASTER=N/A SYNC_DATE=N/A A
PAGE TITLE

CHESTNUT + BACKLIGHT DRIVER


DRAWING NUMBER SIZE

Apple Inc. 051-9584 D


REVISION
R
2.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
14 OF 23
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 14 OF 46
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

SPEAKER AMP, LED DRIVER


SPEAKER AMP (REPLACED WITH L20) D
D I2C ADDRESS: 1000000X

PCB: PLACE AT C335.1 1 C335 1 C337 TO DO: CHANGE NETNAMES WITH L19 TO L20 WHEN WE UPDATE TO NEW SILICON
10UF 1.0UF
20% 20%
6.3V 6.3V
2 CERM-X5R 2 X5R
0402-1 0201-1
OMIT_TABLE
PP1V7_VA_L20 12
PCB: PLACE C335,337 AT VP INPUT
PP_L20_VBOOST
1 C348 1 C342 1 C339
23 22 15 12 8 PP_BATT_VCC 22UF 0.1UF 0.1UF V= VA PIN
20% 10% 10% C= 2.2UF MIN
2 10V 2 16V 2 6.3V

VBST_B A1
VBST_A B1
VBST_A C1
VBST_A D1

VA F5
VP A4
VP A5
X5R-CERM X5R-CERM X5R
0603 0201 201 V = 1.0V C= 1UF MIN

1 C29 1 C341 1 C340


1.0UF 1.0UF 4.7UF
L4 U22 20% 20% 20%
1.0UH-20%-3.2A-0.065OHM 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R-CERM1
CS35L20 0201-1 0201-1 402 R126
1 2 PP_SPKAMP_SW A2 WLCSP FILT+ F2 PP_SPKAMP_FILT 10K
TFA252010-SM B2 SW VER1 LDO_FILT C5 PP_SPKAMP_LDO_FILT
1 2 SPEAKER_TO_SPKAMP_VSENSE_N 17
C333 1 C332 1
1 C367
1%
1/32W
MF
01005
PCB: PLACE C332, C333 AT L4.1 10UF 10UF AP_BI_I2C0_SDA D5
SDA
20% 20% 20 16 14 13 3
VSENSE- E3 L20_SPKAMP_VSENSE_N 220PF
6.3V 6.3V 10%
CERM-X5R 2 CERM-X5R 2 AP_TO_I2C0_SCL D6 SCL
VSENSE+ E2 L20_SPKAMP_VSENSE_P 2 10V
0402-1
OMIT_TABLE
0402-1
OMIT_TABLE
20 16 14 13 3 X7R-CERM
01005 R127
SPKAMP_TO_AP_INT_L A7
INT* ISENSE- F1 SPEAKER_TO_SPKAMP_ISENSE_N 10K
3 1 2 SPEAKER_TO_SPKAMP_VSENSE_P 17
1% MF
ISENSE+ E1 SPEAKER_TO_SPKAMP_ISENSE_P
C 3 AP_TO_SPKAMP_RESET_L A6 RESET*

D7 ALIVE OUT+ D2 SPKAMP_TO_SPEAKER_OUT_P


1/32W 01005
C
1
R129 3 AP_TO_SPKAMP_BEE_GEES
OUT- C2 SPKAMP_TO_SPEAKER_OUT_N
510K C7 ADO 1 C309
5%
1/32W (LEFT CONFIG) IREF+ B7 SPKAMP_IREF 0.1UF
MF E7 20%
45_AP_TO_SPKAMP_I2S2_MCLK MCLK
2 01005 3
2 6.3V
X5R-CERM
E6 SCLK
1
R35 01005
10 3 45_AP_TO_CODEC_XSP_I2S2_BCLK 44.2K FL6
F6 LRCK/FSYNC
1%
1/32W
120OHM-25%-1.8A-0.06DCR
10 3 AP_TO_CODEC_XSP_I2S2_LRCLK MF 1 2 SPKAMP_TO_SPEAKER_OUT_CONN_P
2 01005
17 22
AP_TO_CODEC_XSP_I2S2_DOUT F7 SDIN
10 3 0402
E5 SDOUT
FL9
10 3 CODEC_TO_AP_XSP_I2S2_DIN ~700MA RMS @ 4.1W INTO 8OHM
120OHM-25%-1.8A-0.06DCR
GNDP GNDA 1 2 SPKAMP_TO_SPEAKER_OUT_CONN_N 17 22

0402
C500 C501 C545 C546

A3
B3
B4

B5
B6
C3
C4
D3
D4

C6
E4
F3
F4
1 1 1 1
C360 1 C363 1 1000PF 1000PF 1000PF 1000PF
1000PF 1000PF 10% 10% 10% 10%
10% 10% 10V 2 2 10V 10V 2 2 10V
10V 10V X5R X5R X5R X5R
X5R 2 X5R 2 01005 01005 01005 01005
01005 01005 NOSTUFF NOSTUFF

B LED DRIVER B
I2C ADDRESS: 1100011X
23 22 15 12 8 PP_BATT_VCC

C386 1 C387 1
U17
10UF 10UF
20% 20% LM3563A3TMX
6.3V
CERM 2
6.3V
CERM 2 L5 C4 BGA OUT0 A2 LED_BOOST_OUT
0402 0402 0.47UH-20%-3.2A-0.046OHM IN
OMIT_TABLE OMIT_TABLE
1 2 A3 OUT1 B2
LED_DRV_LX SW0
TFA201610G-SM B3 SW1 LED0 A1
1 C394 1 C396 1 C488
10UF 10UF 100PF
D4 LED1 B1 20%
6.3V
20%
6.3V
5%
16V
3 AP_TO_LEDDRV_EN ENABLE 2 CERM-X5R 2 CERM-X5R 2 NP0-C0G
TEMP C1 0402-2 0402-2 01005
R463
1 21 CAM0_TO_LEDDRV_STROBE_EN C3 STROBE
220K C2
5% 7 CAM0_TORCH TORCH
1/32W PP_STRB_DRIVER_TO_LED 8
MF D1
2 01005
BB_TO_LEDDRV_GSM_BLANK TX
23
C73 1
21 7 AP_BI_CAM_RF_SDA D2 SDA 100PF
5%
16V
GND0
GND1

21 7 AP_TO_CAM_RF_SCL D3 SCL NP0-C0G 2


01005
CAM_RF_TO_STROBE_NTC 8
A4
B4

A SYNC_MASTER=N/A SYNC_DATE=N/A A
PAGE TITLE

SPKR AMP + LED DRIVER


DRAWING NUMBER SIZE

Apple Inc. 051-9584 D


REVISION
R
2.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
15 OF 23
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 15 OF 46
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

12C ADDRESS: 0011010X

12 8 PP3V0_ALWAYS

PP1V8_SDRAM
1 C38 1 C254 23 14 13 12 10 4 3

1.0UF 0.1UF 1 C39


20% 20%
2 6.3V 2 4V 0.01UF
X5R X5R 10%
0201-1 01005 6.3V

TRISTAR D
2 X5R

D 01005 PP3V0_ACC
ACC_PWR
12

VDD_1V8 F3

VDD_3V0 F4

ACC_PWR D5
13 TRISTAR_TO_PMU_MIKEYBUS_TEST_POS NO_XNET_CONNECTION=TRUE OMIT_TABLE

R83
1

100K
5%
1/32W
MF
R43 2 01005
U2
1
0 2
5% MF CBTL1608A1
1/20W 201 C3 WCSP
9 90_CODEC_BI_TRISTAR_MIKEYBUS_P 90_CODEC_BI_TRISTAR_MIKEYBUS_DIG_P DIG_DP P_IN F6 PP5V0_USB_RPROT 17
C4
9 90_CODEC_BI_TRISTAR_MIKEYBUS_N
R44 90_CODEC_BI_TRISTAR_MIKEYBUS_DIG_N DIG_DN ACC1 C5 PP_E75_TO_TRISTAR_ACC1 17
C304 1 PIN FOR HANDSHAKE
0 A1 ACC2 E5 PP_E75_TO_TRISTAR_ACC2 17 1UF
1 2 23 90_TRISTAR_BI_BB_USB_P USB1_DP 10%
5% MF B1 25V
1/20W 201 BB DEBUG USB 23 90_TRISTAR_BI_BB_USB_N USB1_DN DP1 A2 90_TRISTAR_BI_E75_PAIR1_P 17 22 X5R 2
0402
R84
1
C2 DN1 B2 90_TRISTAR_BI_E75_PAIR1_N 17 22
BRICK_ID 13 TRISTAR_TO_PMU_USB_BRICKID BRICK_ID
PLACEHOLDERS FOR INDUCTORS 100K
5% A3 DP2 A4 90_TRISTAR_BI_E75_PAIR2_P 17 22
1/32W 2 90_AP_BI_TRISTAR_USB0_P USB0_DP
MF SOC USB B3 DN2 B4 90_TRISTAR_BI_E75_PAIR2_N 17 22
2 01005 2 90_AP_BI_TRISTAR_USB0_N USB0_DN
PP22
TRISTAR_TO_PMU_MIKEYBUS_TEST_NEG NO_XNET_CONNECTION=TRUE E2 CON_DET_L E3 E75_TO_PMU_ACC_DETECT 13 17 1
PP P4MM
13
3 AP_TO_TRISTAR_ACC_UART2_TXD UART0_TX SM
ACCESSORY UART E1
3 TRISTAR_TO_AP_ACC_UART2_RXD UART0_RX OVP_SW_EN* D6 TRISTAR_TO_PMU_OVP_SW_EN_L 17

3 AP_TO_TRISTAR_DEBUG_UART6_TXD F2 UART1_TX SWITCH_EN E4 RESET_1V8_L 2 12 13 14 19 22 23


DEBUG UART F1
3 TRISTAR_TO_AP_DEBUG_UART6_RXD UART1_RX HOST_RESET B6 TRISTAR_TO_PMU_HOST_RESET 13
HOST_RESET
23 3 BB_TO_AP_UART1_RXD D2 UART2_TX SDA D3 AP_BI_I2C0_SDA 3 13 14 15 20
ACTIVE HIGH
TO DO: ADD PPS TO SOC-SIDE USB 23 3 AP_TO_BB_UART1_TXD D1 UART2_RX SCL D4 AP_TO_I2C0_SCL 3 13 14 15 20
1
R8401
AMBER HAS 200K INT PD

INT C6 TRISTAR_TO_AP_INT 100K


A5 3 13

C 2

2
TRISTAR_TO_AP_JTAG_SWCLK
TRISTAR_BI_AP_JTAG_SWDIO B5
JTAG_CLK
JTAG_DIO
BYPASS E6 TRISTAR_BYPASS
5%
1/32W
MF
C
C338 2 01005

DVSS
DVSS
DVSS
1
1.0UF NO_XNET_CONNECTION=TRUE
20%
6.3V
2 X5R

F5
C1
A6
0201-1
C110 1
100PF
5%
10V
NP0-C0G 2
01005

B B

A SYNC_MASTER=N/A SYNC_DATE=N/A A
PAGE TITLE

TRISTAR
DRAWING NUMBER SIZE

Apple Inc. 051-9584 D


REVISION
R
2.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
16 OF 23
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 16 OF 46
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

DOCKFLEX B2B (USB VBUS, MENU BTN, SPEAKER, HP, HP EXTMIC, NAVAJO, ANTENNA PAC/LAT SW CTRL,
MIC1 (VOICE MIC), ACC DET/ID/PWR, E75 DIFFPAIRS)
FL2302
FL5 120-OHM-210MA
120-OHM-210MA
3 BUTTON_TO_AP_MENU_KEY_L 2 1
1 2 BATTERY_TO_PMU_NTC 12 22 BATTERY NTC
01005
01005 50NA @ 2.5V
MENU BUTTON 1 C176 DZ15 1 1 C2307
56PF 12V-33PF
5% 01005-1 56PF
2 6.3V
NP0-C0G 2
5%
16V
01005 2 NP0-C0G
FL10 NOSTUFF
D 120-OHM-210MA
01005
L7 D
1 2 120-OHM-210MA
01005 2 1
9 CODEC_TO_HPHONE_HS3 CODEC_TO_HPHONE_HS3_CONN
HPHONE: 9 CODEC_TO_HPHONE_HS4 FL1 CODEC_TO_HPHONE_HS4_CONN
17
DZ6 1 1
R23
01005
120-OHM-210MA
HS3/HS4 1 2
6.8V-100PF
01005 1%
100K
C5 1 1 C8 2 1/32W
MF
01005 100PF 100PF 2 01005 CODEC_TO_HPHONE_L
5% 5% 9
16V
NP0-C0G 2
01005
16V
2 NP0-C0G
01005
HPHONE_TO_CODEC_HPHONE_TEST 9
HPHONE AUDIO
FL49 R10 1
CODEC_TO_HPHONE_R 9

120-OHM-210MA
100K
10 PP_CODEC_TO_MIC1_BIAS 2 1 PP_CODEC_TO_MIC1_BIAS_CONN 1%
1/32W L6
01005 MF 120-OHM-210MA
C215 1 01005 2
2 1
1.0UF
20%
6.3V 01005
MIC1 X5R 2
0201-1
DZ5 1 PER STAN, REPLACING L7 AND L6 WITH 01005 PARTS
6.8V-100PF
PRIMARY MIC NO_XNET_CONNECTION=TRUE
01005
2
2
1 C355 1 C359 XW45
56PF 56PF SHORT-10L-0.1MM-SM
5% 5% THIS ONE ON MLB ---> 516S1032 PLUG
2 6.3V 2 6.3V 516S1031 RCPT (USED ON FLEX)
MIC1_TO_CODEC_N
NP0-C0G
01005 NP0-C0G
01005
1 PCB: PUT XW
AT J7.17
BB_TO_LAT_SW2_CTL 23 ANTENNA:
9

22 9 MIC1_TO_CODEC_P J7 BB_TO_LAT_SW1_CTL 23
105847038102829
M-ST-SM LAT SW CTRL
R107 39 40 1 C188 1 C206
HPHONE_TO_CODEC_DET 1
3.3K 2 56PF 56PF
9

C HPHONE:
5%
1/32W
MF
01005
1 C242 NOTE: RSVD ANTENNA
1
3
2
4
AP_TO_HEADSET_HS4_CTRL_CONN
CODEC_TO_HPHONE_HS3_CONN 17
17
5%
6.3V
2 NP0-C0G
01005
5%
6.3V
2 NP0-C0G
01005
C
HS3/HS4 CTRL, FL69 01005
150OHM-25%-200MA-0.7DCR 56PF HPHONE_TO_CODEC_DET_CONN 5 6 CODEC_TO_HPHONE_HS4_REF_CONN 17
5% 22

HPDET 3 AP_TO_HEADSET_HS3_CTRL 1 2 2 6.3V


NP0-C0G
CODEC_TO_HPHONE_L_CONN
7
9
8
10
CODEC_TO_HPHONE_R_CONN
BATTERY_NTC_CONN
01005
FL68 01005 AP_TO_HEADSET_HS3_CTRL_CONN 17 CODEC_TO_HPHONE_HS3_REF_CONN 11 12
150OHM-25%-200MA-0.7DCR AP_TO_HEADSET_HS4_CTRL_CONN 17
22
13 14 C4 1
EXTMIC_TO_CODEC_N
3 AP_TO_HEADSET_HS4_CTRL 1 2
BUTTON_TO_AP_MENU_KEY_CONN_L 15 16 220PF EXTMIC_TO_CODEC_P
9
10% 9
DZ9 1 1 DZ10 17 18 90_TRISTAR_BI_E75_PAIR1_CONN_P
10V
X7R-CERM 2
6.8V-100PF 6.8V-100PF 01005
01005
2 2
01005 19
21
20
22
90_TRISTAR_BI_E75_PAIR1_CONN_N NOSTUFF HS3/HS4 REF
NO_XBET_CONNECTION=TRUE NO_XBET_CONNECTION=TRUE EXTMIC
23 24 90_TRISTAR_BI_E75_PAIR2_CONN_N R151 1
R50
PP_LDO14_2P65_CONN 25 26 90_TRISTAR_BI_E75_PAIR2_CONN_P FL16 01005
0.00
0% 0%
0.00
27 28 120-OHM-210MA 1/32W 1/32W
30 MF MF
29 22 E75_TO_PMU_ACC_DETECT_CONN 17 CODEC_TO_HPHONE_HS3_REF_CONN 1 2 01005 2 2 01005
22

FL495 01005
150OHM-25%-200MA-0.7DCR
31
33
32
34
22 PP_E75_TO_TRISTAR_ACC1_CONN FL17 01005 CODEC_TO_HPHONE_HS3_REF 9
22 PP_E75_TO_TRISTAR_ACC2_CONN
17 CODEC_TO_HPHONE_HS4_REF_CONN 120-OHM-210MA CODEC_TO_HPHONE_HS4_REF 9
1 2 35 36 22
23 PP_LDO14_2P65 1 2
38
37
DZ11 1 1 DZ12
1 C855 41
6.8V-100PF
01005
6.8V-100PF
01005
56PF 42
ANTENNA: 5%
6.3V
PCB: PLACE THESE XW
LINKS AT DOCK CONNECTOR
2 2
2 NP0-C0G
SM
PAC VDD (2.65V) 01005
XW21 2 1
PP5V0_USB_CONN
C70 1
SM 17
56PF
XW22 2 1
22
5%
6.3V TO DO: REMOVE L20, L22 TO OPEN USB EYE? (SEE EUGENE)
NP0-C0G 2
R617
B Q2 Q2
01005
1
0.002 B
CSD75202W15 CSD75202W15 MF 1% 0201
CSP CSP
(2 OF 2) (1 OF 2) C71 1 1/20W
PCB: PLACE NEAR J7
(DESENSE CAPS)
56PF R618
12 PP5V0_USB_PROT A2 B2 22 17 PP5V0_USB_CONN 5%
6.3V
NP0-C0G 2
L20
90-OHM-50MA 1
0.00 2
A3 D1 S B1 B1 S D2 C2 01005 NOSTUFFTCM0605-1
VBUS B3 C3 C12 1 1 SYM_VER-2 4 MF 1% 0201
1/20W
1 C153 100PF
G1 G2 1 C119 5%
90_TRISTAR_BI_E75_PAIR1_P 16 22

A1
1.0UF
20% C1 10%
16V
0.01UFNP0-C0G 2
C240 1 2 3
90_TRISTAR_BI_E75_PAIR1_N 16 22
E75 DIFFPAIRS
10V 01005
2 X5R-CERM 2 25V 27PF
0201-1
REVERSE_GATE 1 C368 X5R-CERM
0201
USB_CONN_SNUB 5%
16V
2 3 90_TRISTAR_BI_E75_PAIR2_N 16 22
R58 R73 0.01UF NP0-C0G 2
FROM TRISTAR
15.00K 100K 1
C13 1 01005
90_TRISTAR_BI_E75_PAIR2_P 16 22

16 TRISTAR_TO_PMU_OVP_SW_EN_L 2 1 OVP_GATE 2
1
R74 10%
25V
2 X5R-CERM 100PF
C879 1 1 C878 R619 1 0.00 2
5.1K 0201
5%
16V
1
TCM0605-1
SYM_VER-2
4
1%
1/32W
1%
1/20W
5% NP0-C0G 2 56PF 56PF NOSTUFF 90-OHM-50MA
MF 1% 0201
MF
01005
MF
201
1/20W
MF 01005 5%
16V
NP0-C0G 2
5%
16V
2 NP0-C0G
L22 1/20W
PP5V0_USB_RPROT 2 201
16
TO TRISTAR
01005 01005
R620 1 0.00 2
R1301 1.00K2 1/32W MF 1% 0201
1/20W E75_TO_PMU_ACC_DETECT 13 16

01005
5% MF

FL60 10-OHM-750MA ACCESSORY:


C913 1 1
C914 2 1 PP_E75_TO_TRISTAR_ACC1 16 DETECT,
100PF
5% 100PF
5%
01005-1 ID, PWR
16V
NP0-C0G 2
01005
2 16V
NP0-C0G FL53 10-OHM-750MA
01005
NOSTUFF NOSTUFF 2 1 PP_E75_TO_TRISTAR_ACC2 16

A 01005-1
SYNC_MASTER=N/A SYNC_DATE=N/A A
PAGE TITLE

DOCKFLEX B2B
DRAWING NUMBER SIZE

Apple Inc. 051-9584 D


SPEAKER: 15 SPEAKER_TO_SPKAMP_VSENSE_P REVISION

SPEAKER LEADS 15 SPEAKER_TO_SPKAMP_VSENSE_N


R
2.0.0
VSENSE, NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
22 15 SPKAMP_TO_SPEAKER_OUT_CONN_P PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
22 15 SPKAMP_TO_SPEAKER_OUT_CONN_N I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
17 OF 23
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 17 OF 46
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SAGE2 C0
D404 (B2B,DRIVER ICS) 19 18 PP_SAGE_TO_TOUCH_VCPL
1 C381 1 C306 1 C315 1 C324 1 C331 C365 1
-12V
343S0628: B0 APN FOR PROTO1
343S0645: C0 APN FOR EVT1

0.1UF 0.1UF 1UF 1UF 1UF 0.1UF


10% 10% 10% 10% 10% 10%
16V 16V 16V 16V 16V 16V
2 X5R-CERM 2 X5R-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM X5R-CERM 2 18 PP_SAGE_TO_TOUCH_VCPH
0201 0201 0402 0402 0402 0201 13.5V
C170 1 PP_SAGE_VCPL_F 18
3.5V
0.1UF
10%
16V
C163 1

X5R-CERM 2 0.1UF
XW79 0201 10%

D
6.3V 2

D 19 14 PN5V7_SAGE_AVDDN 1
SM
2 PN5V7_SAGE_AVDDN_FILT
X5R
201

A PP5V7_SAGE_AVDDH
1 C149 DZ4
18 14
5.45-5.98V PP1V8 2 3 4 5 6 7 10 11 12 14 19 20
21
10UF
CUMULUS C0
GDZT2R6.2B
C156 1 C165

D2
A3
F3
F6

AVDDL1 H5

VCPH A1

VCPL F1

VCPL_F E2

VDDIO C3
20% GDZ-0201 1
2 10V
X5R-CERM K 10UF 0.1UF

AVDDH1
AVDDH2
AVDDH3
AVDDH4
0402-1 20% 20%
TO CLAMP THE 10V
NEGATIVE RAIL X5R-CERM 2 2 4V
X5R
343S0574 0402-1 01005
OMIT_TABLE

SAGE_PANEL_IN IS SENSITIVE
U15 CUMULUS_IN IS SENSITIVE
KEEP THESE NETS FROM XTALK SAGE2-C06 KEEP THESE NETS FROM XTALK
(TURN ON LATER THAN PP1V8_GRAPE)
(TURN OFF SAME TIME AS PP1V8_GRAPE) XW36
SM 18 TOUCH_TO_SAGE_SENSE_IN<4> E4 SNS_IN0
CSP
SNS_OUT0 E5 SAGE_TO_CUMULUS_IN<4> 18
TOUCH_TO_SAGE_SENSE_IN<3> D4 SNS_IN1 SNS_OUT1 D5 SAGE_TO_CUMULUS_IN<3> 18
14 PP5V1_GRAPE_VDDH 18 PP1V8_CUMULUS_VDDLDO 1 2 PP1V8_GRAPE 12 18
18

18 TOUCH_TO_SAGE_SENSE_IN<5> C4 SNS_IN2 SNS_OUT2 C5 SAGE_TO_CUMULUS_IN<5> 18


B4 B5
PP_CUMULUS_VDDCORE 1 C372 18 TOUCH_TO_SAGE_SENSE_IN<0>
A4
SNS_IN3 SNS_OUT3
A5
SAGE_TO_CUMULUS_IN<0> 18
1.0UF 18 TOUCH_TO_SAGE_SENSE_IN<12> SNS_IN4 SNS_OUT4 SAGE_TO_CUMULUS_IN<12> 18
20%
1 C369 6.3V
2 X5R 18 TOUCH_TO_SAGE_SENSE_IN<7> A6 SNS_IN5 SNS_OUT5 A7 SAGE_TO_CUMULUS_IN<7> 18
10UF PP_CUMULUS_VDDANA 0201-1 18 TOUCH_TO_SAGE_SENSE_IN<10> B6 SNS_IN6 SNS_OUT6 B7 SAGE_TO_CUMULUS_IN<10> 18
20%
10V
2 X5R-CERM TOUCH_TO_SAGE_SENSE_IN<1> C6 SNS_IN7 SNS_OUT7 C7 SAGE_TO_CUMULUS_IN<1> 18
0402-1
1 C370 1 C371 SAGE_VBIAS_DRAIN
18

TOUCH_TO_SAGE_SENSE_IN<11> D6 SNS_IN8 SNS_OUT8 D7 SAGE_TO_CUMULUS_IN<11> 18


4.7UF 4.7UF 18
20% 20% 18 TOUCH_TO_SAGE_SENSE_IN<2> E6 SNS_IN9 SNS_OUT9 E7 SAGE_TO_CUMULUS_IN<2> 18
2 6.3V
X5R-CERM1 2 6.3V
X5R-CERM1 3 E8 E9
TOUCH_TO_SAGE_SENSE_IN<13> SNS_IN10 SNS_OUT10 SAGE_TO_CUMULUS_IN<13> 18
402 402
R86 18

VDDANA B1

VDDCORE C1

VDDH C8

C5
F4

VDDLDO A1
TOUCH_TO_SAGE_SENSE_IN<14> D8 SNS_IN11 SNS_OUT11 D9 SAGE_TO_CUMULUS_IN<14> 18
1
220K 2 D C366 18

TOUCH_TO_SAGE_SENSE_IN<8> C8 SNS_IN12 SNS_OUT12 C9 SAGE_TO_CUMULUS_IN<8> 18


VDDIO Q6 0.1UF 18
B8
5% TOUCH_TO_SAGE_SENSE_IN<9> SNS_IN13 SNS_OUT13 B9 SAGE_TO_CUMULUS_IN<9> 18
45_PROX_TO_CUMULUS_RX 1/32W RV1C002UN G 2 SAGE_DUMP_GATE 2 1 18
11 CUMULUS_IN IS SENSITIVE MF A8 A9
01005 SM S 18 TOUCH_TO_SAGE_SENSE_IN<6> SNS_IN14 SNS_OUT14 SAGE_TO_CUMULUS_IN<6> 18
R1211 10%
SAGE_TO_CUMULUS_IN<2> B9 U12 E9 CUMULUS_TO_SAGE_VSTM_OUT<2> 18 1.00M
16V
CUMULUS_TO_SAGE_VSTM_OUT<8> G1 G6 SAGE_TO_TOUCH_VSTM_OUT<8>
C C79
1000PF R26
18

18 SAGE_TO_CUMULUS_IN<1> B8
IN0_0
IN1_0 CUMULUS-C0
WLBGA
VSTM_0
VSTM_1 E5 CUMULUS_TO_SAGE_VSTM_OUT<5> 18 1
5%
1/32W
MF
X5R-CERM
0201
18

18 CUMULUS_TO_SAGE_VSTM_OUT<6> H1
J1
DRV_IN0
DRV_IN1
DRV_OUT0
DRV_OUT1 H6
J6
SAGE_TO_TOUCH_VSTM_OUT<6>
18

18 C
1 2 22.1K 18 SAGE_TO_CUMULUS_IN<6> A9 IN2_0 VSTM_2 F7 CUMULUS_TO_SAGE_VSTM_OUT<16> 18 01005 2 18 CUMULUS_TO_SAGE_VSTM_OUT<12> DRV_IN2 DRV_OUT2 SAGE_TO_TOUCH_VSTM_OUT<12> 18
45_PROX_TO_CUMULUS_RX_FILT 1 2
K1 K6
1% MF 18 SAGE_TO_CUMULUS_IN<7> B7 IN3_0 VSTM_3 E6 CUMULUS_TO_SAGE_VSTM_OUT<18> 18 18 CUMULUS_TO_SAGE_VSTM_OUT<1> DRV_IN3 DRV_OUT3 SAGE_TO_TOUCH_VSTM_OUT<1> 18
10% 1/32W 01005
18 SAGE_TO_CUMULUS_IN<4> B6 IN4_0 VSTM_4 E7 CUMULUS_TO_SAGE_VSTM_OUT<17> 18 18 CUMULUS_TO_SAGE_VSTM_OUT<7>
L1 DRV_IN4 DRV_OUT4 L6 SAGE_TO_TOUCH_VSTM_OUT<7> 18
6.3V
X5R-CERM 18 SAGE_TO_CUMULUS_IN<8> A8 IN5_0 VSTM_5 F8 CUMULUS_TO_SAGE_VSTM_OUT<11> 18 18 CUMULUS_TO_SAGE_VSTM_OUT<15>
G2 DRV_IN5 DRV_OUT5 G7 SAGE_TO_TOUCH_VSTM_OUT<15> 18
01005
C130 1 18 SAGE_TO_CUMULUS_IN<3> B5 IN6_0 VSTM_6 G9 CUMULUS_TO_SAGE_VSTM_OUT<13> 18 18 CUMULUS_TO_SAGE_VSTM_OUT<14>
H2 DRV_IN6 DRV_OUT6 H7 SAGE_TO_TOUCH_VSTM_OUT<14> 18
27PF B4 D6 J2 J7
5% 18 SAGE_TO_CUMULUS_IN<5> IN7_0 VSTM_7 CUMULUS_TO_SAGE_VSTM_OUT<7> 18 18 CUMULUS_TO_SAGE_VSTM_OUT<18> DRV_IN7 DRV_OUT7 SAGE_TO_TOUCH_VSTM_OUT<18> 18
16V K2 K7
NP0-C0G 2 18 SAGE_TO_CUMULUS_IN<9>
A7 IN8_0 VSTM_8 D7 CUMULUS_TO_SAGE_VSTM_OUT<3> 18 18 CUMULUS_TO_SAGE_VSTM_OUT<5> DRV_IN8 DRV_OUT8 SAGE_TO_TOUCH_VSTM_OUT<5> 18
01005 L2 L7
18 SAGE_TO_CUMULUS_IN<0> B3 IN9_0 VSTM_9 D8 CUMULUS_TO_SAGE_VSTM_OUT<9> THESE ARE ROUTED TOGETHER DRV_IN9 DRV_OUT9 SAGE_TO_TOUCH_VSTM_OUT<9> 18

18 SAGE_TO_CUMULUS_IN<14> A6 IN10_0 VSTM_10 F9 CUMULUS_TO_SAGE_VSTM_OUT<10> SPECIAL - CANNOT SWAP L3 DRV_IN10 DRV_OUT10 L8 SAGE_TO_TOUCH_VSTM_OUT<10> 18

18 SAGE_TO_CUMULUS_IN<10> A3 IN11_0 VSTM_11 D5 CUMULUS_TO_SAGE_VSTM_OUT<1> 18 SPECIAL - CANNOT SWAP 18 CUMULUS_TO_SAGE_VSTM_OUT<4> K3 DRV_IN11 DRV_OUT11 K8 SAGE_TO_TOUCH_VSTM_OUT<4> 18

18 SAGE_TO_CUMULUS_IN<13> A5 IN12_0 VSTM_12 F6 CUMULUS_TO_SAGE_VSTM_OUT<4> 18 18 CUMULUS_TO_SAGE_VSTM_OUT<19>


J3 DRV_IN12 DRV_OUT12 J8 SAGE_TO_TOUCH_VSTM_OUT<19> 18

18 SAGE_TO_CUMULUS_IN<11> A4 IN13_0 VSTM_13 F5 CUMULUS_TO_SAGE_VSTM_OUT<8> 18 18 CUMULUS_TO_SAGE_VSTM_OUT<13>


H3 DRV_IN13 DRV_OUT13 H8 SAGE_TO_TOUCH_VSTM_OUT<13> 18
PP7 P4MM
SM PP
1
18 SAGE_TO_CUMULUS_IN<12> B2 IN14_0 VSTM_14 G4 CUMULUS_TO_SAGE_VSTM_OUT<12> 18 2 18 PP_SAGE_VCPL_F 18 CUMULUS_TO_SAGE_VSTM_OUT<16>
G3 DRV_IN14 DRV_OUT14 G8 SAGE_TO_TOUCH_VSTM_OUT<16> 18
L4 L9
PP8 P4MM
SM PP
1 45_PROX_TO_CUMULUS_RX_IN A2 IN14_1 VSTM_15 E8 CUMULUS_TO_SAGE_VSTM_OUT<0> 18 XW37 18 CUMULUS_TO_SAGE_VSTM_OUT<3>
K4
DRV_IN15 DRV_OUT15
K9
SAGE_TO_TOUCH_VSTM_OUT<3> 18

VSTM_16 G8 CUMULUS_TO_SAGE_VSTM_OUT<15> 18 SM 18 CUMULUS_TO_SAGE_VSTM_OUT<2> DRV_IN16 DRV_OUT16 SAGE_TO_TOUCH_VSTM_OUT<2> 18


A
3 AP_TO_TOUCH_SPI1_CS_L E4 H_CS* VSTM_17 G7 CUMULUS_TO_SAGE_VSTM_OUT<19> 18 1 D2
SM-201
18 CUMULUS_TO_SAGE_VSTM_OUT<0>
J4 DRV_IN17 DRV_OUT17 J9 SAGE_TO_TOUCH_VSTM_OUT<0> 18

TOUCH_TO_AP_INT_L F1 H_INT* VSTM_18 G6 CUMULUS_TO_SAGE_VSTM_OUT<14> 18 18 CUMULUS_TO_SAGE_VSTM_OUT<11>


H4 DRV_IN18 DRV_OUT18 H9 SAGE_TO_TOUCH_VSTM_OUT<11>
3
DSF01S30SC G4 G9
18

3 AP_TO_TOUCH_SPI1_CLK D3 H_SCLK VSTM_19 G5 CUMULUS_TO_SAGE_VSTM_OUT<6> 18 NOSTUFF 18 CUMULUS_TO_SAGE_VSTM_OUT<17> DRV_IN19 DRV_OUT19 SAGE_TO_TOUCH_VSTM_OUT<17>


3 AP_TO_TOUCH_SPI1_MOSI D2 H_SDI
K 18
PP11
P4MM
SAGE_VBIAS D3 VBIAS BSYNC K5 LCM_TO_AP_HIFA_BSYNC 3 18 19 SM
E1 G1 NOTE: LCM_TO_AP_HIFA_BSYNC_BUFF 1
R1362 H_SDO GPIO_1/CK
A2
PP
3 TOUCH_TO_AP_SPI1_MISO 1 TOUCH_TO_AP_SPI1_MISO_R GPIO_2/SD D4 CUMULUS_TO_SAGE_BOOST_EN 18 18 SAGE_TO_TOUCH_VCPH_REF VCPH_REF/EN GCM_TEST F9 CUMULUS_TO_SAGE_GCM_SEL 18
MF 1% F2
01005 10.2 1/32W C4 JTAG_TCK GPIO_3 F2 U12_GPIO_3 1
PP P4MM SAGE_TO_TOUCH_VCPL_REF VCPL_REF/EN
C3 F3
SM PP9 18
GO F7
JTAG_TDI GPIO_4 CUMULUS_TO_SAGE_GCM_SEL 18
C150 1 C147 1 C137 1 PP_SAGE_VBST_OUTH B1 VBST_OUTH
E2 JTAG_TDO 0.01UF 0.01UF 0.1UF VCM_IN J5 TOUCH_TO_SAGE_VCM_IN
PP_SAGE_VBST_OUTL E1
18
C6 10% 10% 10% VBST_OUTL
PP1V8_CUMULUS_VDDLDO JTAG_TMS TM_ACS* C2 CUMULUS_TO_PROX_RX_EN_1V8 6.3V 6.3V 6.3V
I2C_SCL F5
18 11

B E3 BCFG_RTCK
TM_OVR G3
X5R 2
01005
X5R 2
01005
X5R 2
201 PP_SAGE_LX C1
PP_SAGE_LY D1
L_X
I2C_SDA G5 B
1
R79

AGND1
AGND2
AGND3
AGND4
AGND5
AGND6
18 CUMULUS_TO_PROX_TX_EN_1V8_L L_Y
D1 CLKIN/RESET*
5%
100K BOOST_EN B2 CUMULUS_TO_SAGE_BOOST_EN PP18
P4MM
18

3 AP_TO_TOUCH_GRAPE_RESET_L D9 RSTOVR* 1/32W SM


MF 1
3 45_AP_TO_TOUCH_CLK32K_RESET_L PP

C2
B3
F4
F8
E3
L5
(ALSO A RESET IF CLOCK STOPS) GND 2 01005 1
C321 1 C328 1 C349 1
C7
C9
G2

PP1V8_GRAPE 1000PF 1000PF


12 18
0.33UF 10% 10% L21
20% 25V 25V
PP12 P4MM
SM PP
1 20V 2
TANT X7R-CERM 2
0201
X7R-CERM 2
0201
10UH-0.32A-1.56OHM
PSB12101T-SM
0402
18 14 PP5V7_SAGE_AVDDH
J4 2
ON MLB ---> 516S1061 PLUG
516S1060 RCPT (ON FLEX)
504459-4210
43
M-ST-SM
TOUCH B2B
C5 18 TOUCH_TO_SAGE_SENSE_IN<5> 1 2 TOUCH_TO_SAGE_SENSE_IN<6> 18 C6
C4 18 TOUCH_TO_SAGE_SENSE_IN<4> 3 4 TOUCH_TO_SAGE_SENSE_IN<13> 18 GS3
C0 18 TOUCH_TO_SAGE_SENSE_IN<0> 5 6 TOUCH_TO_SAGE_SENSE_IN<7> 18 C7 NO_XNET_CONNECTION=TRUE 0603-LLP
C3 18 TOUCH_TO_SAGE_SENSE_IN<3>
7 8 SAGE_TO_TOUCH_VCPH_REF_CONN 18 VGH_REF
TANT 2 C346 1 C364 1
GS1 18 TOUCH_TO_SAGE_SENSE_IN<11> 9 10 SAGE_TO_TOUCH_VCPL_REF_CONN 18 VGL_REF SM
XW7 25V
20% 1000PF
10%
1000PF
10%
1UF 25V 25V
18 TOUCH_TO_SAGE_SENSE_IN<2>
11 12 TOUCH_TO_SAGE_VCM_IN_CONN 18 VCOM 18 SAGE_TO_TOUCH_VCPH_REF_CONN 1 2 SAGE_TO_TOUCH_VCPH_REF X7R-CERM 2 X7R-CERM 2
C2
13 14
18
C320 1
0201 0201
C1 18 TOUCH_TO_SAGE_SENSE_IN<1> TOUCH_TO_SAGE_SENSE_IN<12> 18 GS2 NO_XNET_CONNECTION=TRUE
GS0 18 TOUCH_TO_SAGE_SENSE_IN<10>
15 16 TOUCH_TO_SAGE_SENSE_IN<9> 18 C9
VGL 19 18 PP_SAGE_TO_TOUCH_VCPL_CONN 17 18 TOUCH_TO_SAGE_SENSE_IN<8> 18 C8 SM
XW13
VGH 18 PP_SAGE_TO_TOUCH_VCPH_CONN 19 20 TOUCH_TO_SAGE_SENSE_IN<14> 18 GS4 18 SAGE_TO_TOUCH_VCPL_REF_CONN 1 2 SAGE_TO_TOUCH_VCPL_REF 18

R10 18 SAGE_TO_TOUCH_VSTM_OUT<10> 21 22

A R7 18 SAGE_TO_TOUCH_VSTM_OUT<7> 23 24 SAGE_TO_TOUCH_VSTM_OUT<17> 18 R17


NO_XNET_CONNECTION=TRUE
PP1V8_GRAPE 12 18
SYNC_MASTER=N/A SYNC_DATE=N/A A
R1 18 SAGE_TO_TOUCH_VSTM_OUT<1> 25 26 SAGE_TO_TOUCH_VSTM_OUT<16> 18 R16 XW18 PAGE TITLE

5
R5 18 SAGE_TO_TOUCH_VSTM_OUT<5> 27 28 SAGE_TO_TOUCH_VSTM_OUT<15> 18 R15
TOUCH_TO_SAGE_VCM_IN_CONN 1
SM
2 TOUCH_TO_SAGE_VCM_IN VCC
1
R2 D404 (TOUCH B2B, DRIVER ICS)
R6 18 SAGE_TO_TOUCH_VSTM_OUT<6> 29 30 SAGE_TO_TOUCH_VSTM_OUT<14> 18 R14 18 18
100K
R8 18 SAGE_TO_TOUCH_VSTM_OUT<8> 31 32 SAGE_TO_TOUCH_VSTM_OUT<13> R13 NO_XNET_CONNECTION=TRUE U5 5%
1/32W
DRAWING NUMBER SIZE

R9 18 SAGE_TO_TOUCH_VSTM_OUT<9> 33 34 SAGE_TO_TOUCH_VSTM_OUT<12>
18

R12 XW19
74AUP2G3404GN
SOT1115 MF
Apple Inc. 051-9584 D
18
SM 2 01005 REVISION
R4 18 SAGE_TO_TOUCH_VSTM_OUT<4> 35 36 SAGE_TO_TOUCH_VSTM_OUT<11> R11 LCM_TO_AP_HIFA_BSYNC_BUFF 6 1Y 1A 1 LCM_TO_AP_HIFA_BSYNC
R3 18 SAGE_TO_TOUCH_VSTM_OUT<3> 37 38 SAGE_TO_TOUCH_VSTM_OUT<0>
18
PP_SAGE_TO_TOUCH_VCPL_CONN
19 18 1 2 PP_SAGE_TO_TOUCH_VCPL 18 19
14 3 18 19 R
2.0.0
R2 18 SAGE_TO_TOUCH_VSTM_OUT<2> 39 40 SAGE_TO_TOUCH_VSTM_OUT<18>
18
R0_RIGHT
R18 NO_XNET_CONNECTION=TRUE R361 CUMULUS_TO_PROX_TX_EN_BUFF 4 2Y 2A 3 CUMULUS_TO_PROX_TX_EN_1V8_L
NOTICE OF PROPRIETARY PROPERTY: BRANCH
18 100K 11 18

R0_LEFT 18 SAGE_TO_TOUCH_VSTM_OUT<0> 41 42 SAGE_TO_TOUCH_VSTM_OUT<19> 18 R19 XW23


SM
5%
1/32W GND
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
MF
18 OF 23
2
18 PP_SAGE_TO_TOUCH_VCPH_CONN 1 2 PP_SAGE_TO_TOUCH_VCPH 18
01005 2 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
44 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 18 OF 46
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

LCM B2B FL25


120-OHM-210MA
2 1 PN5V7_SAGE_AVDDN 14 18

D 01005
D
FL18
80-OHM-0.2A-0.4-OHM
1 2 PP1V8 2 3 4 5 6 7 10 11 12 14 18 19
20 21
1 C610 0201-1
NO_XNET_CONNECTIO=TRUE
5%
56PF 1 C42 1 C46
16V 56PF 0.1UF
2 NP0-C0G 5% 10%
01005 6.3V
2 NP0-C0G 6.3V
2 X5R
01005 201

FL26
80-OHM-0.2A-0.4-OHM
1 2 PP5V7_TO_LCD_AVDDH 14
0201-1

1 C30 C43 1 C48 1 C49 1 C59 1


56PF 2.2UF 2.2UF 2.2UF 2.2UF
5% 20% 20% 20% 20%
16V 6.3V 6.3V 6.3V 6.3V
2 NP0-C0G X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2

LCM CONNECTOR 01005

FL27
0402 0402 0402 0402

120-OHM-210MA SPECIAL Z = 0.33 MM

THIS ONE ON MLB ---> 516S1066 PLUG 1 2 LCD_PWR_EN 13 14

516S1065 RCPT (FLEX) 01005


1 C40 1
R971
R932 56PF 100K
0.00 2 J5 5% 1%

C 18 PP_SAGE_TO_TOUCH_VCPL 1
1/32W 0% MF 01005
18 PP_SAGE_TO_TOUCH_VCPL_CONN
AA22LB-P
M-ST-SM
2 6.3V
NP0-C0G
01005
1/32W
MF
2 01005
C
L2
90-OHM-50MA
30 29 BOMOPTION=NOSTUFF
TCM0605-1
1 SYM_VER-2 4
90_LCM_MIPI_DATA0_CONN_P 2 1 PN5V7_LCM_AVDDN_CONN
7 90_AP_TO_LCM_MIPI_DATA0_P
90_LCM_MIPI_DATA0_CONN_N 4 3 PP5V7_LCD_AVDDH_CONN
7 90_AP_TO_LCM_MIPI_DATA0_N
2 3 6 5 PP1V8_LCM_CONN
L9
90-OHM-50MA
8 7 LCD_PWR_EN_CONN R4
TCM0605-1 10 9 LCD_RESET_L_CONN 1.00K2
1 SYM_VER-2 4 1 LCM_TO_AP_PIFA 3
90_LCM_MIPI_DATA1_CONN_P 12 11 LCD_HIFA_BSYNC_CONN
7 90_AP_TO_LCM_MIPI_DATA1_P 5% NOSTUFF
90_LCM_MIPI_DATA1_CONN_N 14 13 LCD_PANIC_L_CONN 1/32W
7 90_AP_TO_LCM_MIPI_DATA1_N MF
2 3 16 15 LCD_PIFA 01005
L8 18 17 22 LCD_BL_CA_CONN
90-OHM-50MA
1
TCM0605-1
SYM_VER-2 4
20 19 22 LCD_BL_CC1_CONN 1 C24
90_AP_TO_LCM_MIPI_CLK_P 90_LCM_MIPI_CLK_CONN_P 22 21 22 LCD_BL_CC2_CONN 56PF
7 5%
90_LCM_MIPI_CLK_CONN_N 24 23 6.3V
7 90_AP_TO_LCM_MIPI_CLK_N 2 NP0-C0G
2 3
L10 26 25 01005
FL34
90-OHM-50MA
TCM0605-1
28 27 120-OHM-210MA
1 SYM_VER-2 4 1 2
90_LCM_MIPI_DATA2_CONN_P LCM_TO_AP_HIFA_BSYNC 3 18
7 90_AP_TO_LCM_MIPI_DATA2_P 32 31 01005
90_AP_TO_LCM_MIPI_DATA2_N 90_LCM_MIPI_DATA2_CONN_N
7
L1
90-OHM-50MA
2 3 1 C19
TCM0605-1 56PF
1 SYM_VER-2 4 5%
7 90_AP_TO_LCM_MIPI_DATA3_N 90_LCM_MIPI_DATA3_CONN_N 2 6.3V
NP0-C0G
01005
7 90_AP_TO_LCM_MIPI_DATA3_P 90_LCM_MIPI_DATA3_CONN_P R32
2 3
1
100K 2 PP1V8 2 3 4 5 6 7 10 11 12 14 18 19
20 21
20
18 5%

B 12
10
6
4
2 PP1V8
FL37
150OHM-25%-200MA-0.7DCR
1/32W
MF
01005 B
3
5
1 2 RESET_1V8_L
7
11
14 R62
1
NOSTUFF 01005
2 12 13 14 16 22 23

19
21 100K
NOSTUFF 1%
1/32W
MF FL61
2 01005
120-OHM-210MA R75
1 2 0.00 2
1 PMU_AP_TO_LCM_RESET_L 13
01005 0%
R31
1
1/32W

1%
100K 1 C41 MF
01005 REFER TO RADAR 12410499. THIS IS PART OF BUILD MATRIX
1/32W 56PF TO POTENTIALLY IMPLEMENT LCD PANIC FUNCTION
MF 5% NOSTUFF
6.3V AP_TO_LCM_RESET_L
2 01005 2 NP0-C0G 3
01005
FL35
1 2 PP_LCM_BL_CAT2 14
0201-1
240-OHM-0.2A-0.8-OHM
FL24
1 2 PP_LCM_BL_CAT1 14
0201-1
240-OHM-0.2A-0.8-OHM
1 C10 1 C15
56PF 56PF
5% 5%
16V
2 16V
NP0-C0G
2 NP0-C0G
01005 01005
FL36
1 2 PP_LCM_BL_ANODE 14
A 1 C14
0201-1
240-OHM-0.2A-0.8-OHM SYNC_MASTER=N/A SYNC_DATE=N/A A
PAGE TITLE
56PF
5%
16V
2 NP0-C0G
LCM CONNECTOR
01005 DRAWING NUMBER SIZE
LCD_DESENSE_CONN
Apple Inc. 051-9584 D
1 C18 REVISION

5%
56PF
R
2.0.0
16V
2 NP0-C0G NOTICE OF PROPRIETARY PROPERTY: BRANCH
01005 THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
19 OF 23
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 19 OF 46
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

SENSORS
THIS PART OUTSIDE OF SHIELD THESE PARTS INSIDE OF SHIELD

D COMPASS
COMPASS DEVICE: 338S1014
GYRO D
COMPASS INTERPOSER: 998-5120 AP3GDL20H, APN 338S1158

PP3V0_IMU PP1V8 2 3 4 5 6 7 10 11 12 14 18 19
20 12 20 21

FL38 FL39 1 C347 C344 1


150OHM-25%-200MA-0.7DCR 150OHM-25%-200MA-0.7DCR
21
19
14
1 C345 1.0UF 0.1UF
PP3V0_IMU 1 2 PP3V0_COMP PP1V8_COMP 2 1 PP1V8
11
6 7 0.1UF 20% 20%
20 12 20 2 3 20% 6.3V 4V
4 5 4V 2 X5R X5R 2
01005 01005 10 2 X5R
12 0201-1 01005
C298 1 C300 18 01005

B1

C4
1 OMIT_TABLE 20

1.0UF 0.1UF
20% VDD VID 20%
4V
6.3V 2 2 X5R PWRTERM2GND
X5R
0201-1 U16 01005

15
VDD 16
AK8963C

1
OMIT_TABLE
CSP FL751 120-OHM-210MA
RES/VDD VDD_IO
D1 CAD0 SCL/SK A3 I2C_SCL_COMP 1 2 AP_TO_I2C1_SCL
U8
3 20
D2 CAD1 SDA/SI A4 I2C_SDA_COMP 01005
AP3GDL20HAA18
FL752 120-OHM-210MA LGA
C2 TST1 CSB* A2 1 2 AP_BI_I2C1_SDA 3 20 19 18 14 12 11 10 7 6 5 4 3 2 PP1V8 5 CS SCL/SPC 2 AP_TO_I2C0_SCL 3 13 14 15 16
21 20
01005 3 GYRO_TO_AP_INT2 6 DRDY/ SDA/SDI/SDO 3 AP_BI_I2C0_SDA 3 13 14 15 16
B3 RSV SO B4 INT2
8 DEN SDO/SA0 4
FL753 120-OHM-210MA NO CAMERA VSYNC PIN
C3 TRG DRDY A1 COMP_INT2 1 2 COMPASS_TO_AP_INT_2 3
3 GYRO_TO_AP_INT1 7 INT1 RES0 9
01005
D4 RST* RES1 10
20 PP1V8_COMP
VSS RES2 11
11V CHARGE PUMP
C

13 GND
C

12 GND
CAP 14
C1

GYRO_CP
TO DO: 1 C11
ADD ALTERNATE AICHI 0.01UF
COMPASS (APN 338S1133) 10%
25V
2 X5R-CERM
0201

ACCELEROMETER
AP2DHAA, APN 338S1114

20 12 PP3V0_IMU PP1V8 2 3 4 5 6 7 10 11 12 14 18 19
20 21

C334 1 C336 1
1.0UF
20%
0.01UF
10%
C997 1

6.3V 2 6.3V 2 0.1UF


X5R X5R 20%
4V
B 0201-1 01005 X5R 2
01005 B

7
VDD VDD_IO

U18
AP2DHAA24
LGA
4 CS SCL/SPC 1 AP_TO_I2C1_SCL 3 20

NEED TO CHECK CONNECTION 12 RES SDA/SDI/SDO 2 AP_BI_I2C1_SDA 3 20

11 RES SDO/SA0 3
10 RES

3 ACCEL_TO_AP_INT1 6 INT1 RES 13


3 ACCEL_TO_AP_INT2 5 INT2 RES 14
NEED TO CHECK CONNECTION

GND

9
TO DO: VERIFY CONNECTIONS ON ACCEL (CS, SDO PINS)

A SYNC_MASTER=N/A SYNC_DATE=N/A A
PAGE TITLE

OSCAR + SENSORS
DRAWING NUMBER SIZE

Apple Inc. 051-9584 D


REVISION
R
2.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
20 OF 23
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 20 OF 46
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

CAM0: MAIN CAMERA CONNECTOR


D D

FL22
120-OHM-210MA
7 45_AP_TO_CAM_RF_CLK 1 2
01005
1 C31 1 C84
56PF 56PF
5% 5%
6.3V 6.3V
2 NP0-C0G 2 NP0-C0G
01005 01005

FL28
120-OHM-210MA
7 AP_TO_CAM_RF_SHUTDOWN1 2
01005

FL29 R721
120-OHM-210MA 100K
5%
1 2 1/32W
15 CAM0_TO_LEDDRV_STROBE_EN MF
01005 2
01005
C376 1
56PF THIS ONE ON MLB ---> 516S0940 PLUG
FL30 5%
6.3V
NP0-C0G 2
516S0939 RCPT (USED ON FLEX)
120-OHM-210MA 01005
AP_BI_CAM_RF_SDA 1 2
15 7
L34
C 01005
FL31 C361
56PF
1
J3
BB35-PA 1
90-OHM-50MA
TCM0605-1
SYM_VER-2 4
C
120-OHM-210MA 5% M-ST-SM 90_CAM0_TO_AP_MIPI_DATA3_P 7
6.3V
15 7 AP_TO_CAM_RF_SCL 1 2 NP0-C0G 2 33 34 90_CAM0_TO_AP_MIPI_DATA3_N 7
01005 2 3
01005
C353 1 L33
56PF 1 2
90-OHM-50MA
5%
6.3V PGND_CAM0_AF_RET 3 4 90_CAM0_MIPI_DATA3_CONN_P TCM0605-1
FL43 NP0-C0G 2
01005
12

PP2V5_CAM0_AF_CONN 5 6 90_CAM0_MIPI_DATA3_CONN_N
1 SYM_VER-2 4
10-OHM-750MA 90_CAM0_TO_AP_MIPI_DATA2_P 7
PP1V2_CAM0_CONN 7 8
12 11 PP2V8_CAM_AVDD 1 2 90_CAM0_TO_AP_MIPI_DATA2_N 7
9 10 90_CAM0_MIPI_DATA2_CONN_P 2 3
01005-1
C82 1 0.07 OHMS C287 1 1 C352 AP_BI_CAM_RF_SCL_CONN 11 12 90_CAM0_MIPI_DATA2_CONN_N L37
1.0UF 1.0UF 56PF AP_BI_CAM_RF_SDA_CONN 13 14 90-OHM-50MA
20%
6.3V 2
20%
6.3V 2
5%
CAM0_TO_LEDDRV_STROBE_EN_CONN 15 16 90_CAM0_MIPI_CLK_CONN_P 1
TCM0605-1
SYM_VER-2 4 CAM0:
2 6.3V
X5R
0201-1
X5R
0201-1
NP0-C0G
01005 PP2V8_CAM0_CONN 17 18 90_CAM0_MIPI_CLK_CONN_N 90_CAM0_TO_AP_MIPI_CLK_P 7 4-LANE MIPI
19 20 90_CAM0_TO_AP_MIPI_CLK_N 7
2 3
PP1V8_CAM0_CONN 21 22 90_CAM0_MIPI_DATA1_CONN_P
L28
FERR-22-OHM-1A-0.065-OHM 23 24 90_CAM0_MIPI_DATA1_CONN_N L38
AP_TO_CAM_RF_SHUTDOWN_CONN 25 26 90-OHM-50MA
18 14 12 11 10 7 6 5 4 3 2 PP1V8 1 2 TCM0605-1
21 20 19 27 28 90_CAM0_MIPI_DATA0_CONN_P 1 SYM_VER-2 4
0201
NO_XNET_CONNECTIO=TRUE C351 1 45_AP_TO_CAM_RF_CLK_CONN 29 30 90_CAM0_MIPI_DATA0_CONN_N 90_CAM0_TO_AP_MIPI_DATA1_P 7

56PF 31 32 90_CAM0_TO_AP_MIPI_DATA1_N 7
5% 2 3
6.3V
NP0-C0G 2
NO_XNET_CONNECTIO=TRUE
L29
01005
35 36
L36
90-OHM-50MA
FERR-22-OHM-1A-0.065-OHM 1
TCM0605-1
SYM_VER-2 4
19 18 14 12 11 10 7 6 5 4 3 2 PP1V8 1 2 PP1V8_CAM0_REG 90_CAM0_TO_AP_MIPI_DATA0_P 7
21 20
0201 90_CAM0_TO_AP_MIPI_DATA0_N
B C249 1
1.0UF
20%
2 3
7

B
6.3V 2
X5R
0201-1 U13
LP5908AP-1.28V
USMD
A1 VIN VOUT A2
C357 1 1 C358
B1 VEN
GND
1.0UF 56PF
ROUTING CRITICAL, FOLLOW N41 20% 5%
3 AP_TO_CAM_RF_VDDCORE_EN
6.3V 2 2 6.3V
X5R NP0-C0G
B2

0201-1 01005

XW29
SM
12 PP2V5_CAM0_AF_COMP 1 2
THIS XW LINK AT CONNECTOR PIN
L27
FERR-22-OHM-1A-0.065-OHM
12 PP2V5_CAM0_AF 1 2
0201
C286 1 C350 1
1.0UF 1.0UF
1 C373
20%
6.3V 2
20% 56PF
6.3V 2 5%
X5R X5R 6.3V
0201-1 0201-1 2 NP0-C0G
01005

A SYNC_MASTER=N/A SYNC_DATE=N/A A
PAGE TITLE

CAM0 CONNECTOR
DRAWING NUMBER SIZE

Apple Inc. 051-9584 D


REVISION
R
2.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
21 OF 23
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 21 OF 46
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

BATT CONN, TPS, STANDOFFS/SHIELDS/FIDUCIALS


TESTPOINTS
BATTERY CONN SPKAMP OUTPUT TP
THIS ONE ON MLB ---> 516S1022 RCPT POWER TP TP91
D
516S1023 PLUG (USED ON BATTERY PCM)

FL11
17 15 SPKAMP_TO_SPEAKER_OUT_CONN_P 1
TP-P6
A D
J6 120-OHM-210MA PP5V0_USB_CONN TP1
1
RCPT-BATT-N41
17 A VBUS
1 2 AP_BI_BATTERY_SWI TP-P6
F-ST-SM
11
3 13
TP92
1
8 7
C279 1 01005 17 15 SPKAMP_TO_SPEAKER_OUT_CONN_N A
56PF TP2 TP-P6
5% 1
16V A POWER GROUND
2 1 NP0-C0G 2 TP-P6
01005
AP_BI_BATTERY_SWI_CONN 4 3 AP_BI_BATTERY_SWI_CONN

E75 - USB/UART/ID/POWER
22 22

PP_BATT_VCC 6 5 PP_BATT_VCC
23 22 15 12 8 8 12 15 22 23

PP_BATT_VCC TP3
1

SHORT-10L-0.25MM-SM
C23 1 C25 1 23 22 15 12 8 A VBATT
56PF 56PF
10 9 2 1 C9 1 C275 1 C22 TP-P80
56PF 220PF 56PF
5%
16V
5%
16V
12 XW12 5%
16V
10%
10V
5%
16V
NP0-C0G 2 NP0-C0G 2 2 NP0-C0G 2 X7R-CERM 2 NP0-C0G
01005 01005
1 01005 01005 01005
TP11
1 TP21
A VBATT GROUND 17 16 90_TRISTAR_BI_E75_PAIR1_P 1
A
TP-P6 TP-P6

TP34
1
PCB: PLACE XW12 AT BATT CONN, PIN 7 A POWER GROUND TP22
1
TP-P90 90_TRISTAR_BI_E75_PAIR1_N
BATTERY_TO_PMU_SENSE 12
17 16
A
TP-P6

PP_BATT_VCC TP4
1 VBATT TP23
22 15 12 8
A 90_TRISTAR_BI_E75_PAIR2_P 1
23
TP-P55
17 16 A
TP-P6

BATTERY_TO_PMU_NTC TP5
1 BATTERY NTC
17 12
A TP24
TP-P6 90_TRISTAR_BI_E75_PAIR2_N 1
17 16 A
C
SHIELDS SUPER TP TP-P6
C
FIDUCIALS 17 PP_E75_TO_TRISTAR_ACC1_CONN
TP26
1
TP-P6
A
FD1 PMU_AMUX_AY
TP6
1 ACCESSORY ID AND POWER
13
A ANALOG MUX A OUTPUT
FID TP-P6
0P5SM1P0SQ-NSP
1
PP_E75_TO_TRISTAR_ACC2_CONN
TP27
1
1 SH1 17

TP-P6
A
SM 806-4834
FD2 PMU_AMUX_BY TP7
1
FID
13
A ANALOG MUX B OUTPUT
0P5SM1P0SQ-NSP SHLD-EMI-UPPER-FRONT TP-P6
TP25
1
1 A POWER GROUND
1 TP-P6
FD3
FID
0P5SM1P0SQ-NSP
1
SH2
SM 806-4228 RESET
FD4
SHLD-X145-EMI-LOWER-FRONT TP32
1
FID RESET_1V8_L TP8
1
A POWER GROUND
0P5SM1P0SQ-NSP 1
23 19 16 14 13 12 2 A H6P & BB RESET TP-P6
TP-P6
1 SH3
SM 806-4832
FD5
TP10
FID
0P5SM1P0SQ-NSP
1
SHLD-EMI-UPPER-BACK
DFU 17 E75_TO_PMU_ACC_DETECT_CONN 1
TP-P6
A FOR DIAGS

FD6 1 TP9
FID SH4 FORCE_DFU 1
0P5SM1P0SQ-NSP
3 A FORCE DFU
SM 806-4230
MIC AUDIO
1 TP-P6

B B
SHLD-X145-EMI-LOWER-BACK
HEADPHONE MIC
MIC1_TO_CODEC_P TP15
1 MIC1 POSITIVE
17 9
A
TP-P6

CODEC_TO_HPHONE_HS3_REF_CONN
TP28
1
17 A HEADPHONE MIC NEG
TP-P6
MIC2_TO_CODEC_P
TP16
1 MIC2 POSITIVE
9 8
A
TP-P6
AC COUPLED SCREW HOLES + STANDOFFS 17 CODEC_TO_HPHONE_HS4_REF_CONN
TP29
1
A HEADPHONE MIC POS
(ON NORTH END OF SINGLE_BRD, TO MITIGATE COMPASS RETURN CURRENTS) TP-P6 TP17
11 9 MIC3_TO_CODEC_P 1
A MIC3 POSITIVE
TP-P6

SCREW HOLES STANDOFFS DRIVE MIC WRT NEAREST GROUND TEST POINT

BS1
STDOFF-2.7OD1.4ID-1.04H-SM-1 LCM BACKLIGHT
PGND_SCREW_HOLE1 PGND_STANDOFF1 1
860-1511
1 C433 1 C435 1 C437 TP18
1 LCD BACKLIGHT SINK1
1 C427 1 C430 1 C432 100PF 56PF 27PF
19 LCD_BL_CC2_CONN A
100PF 56PF 27PF 5% 5% 5%
TP-P6
5% 5% 5% 16V 16V 16V
16V 16V 16V 2 NP0-C0G 2 NP0-C0G 2 NP0-C0G
2 NP0-C0G 2 NP0-C0G 2 NP0-C0G
01005 01005 01005 01005 01005 01005
LCD_BL_CC1_CONN TP19
1
19
A LCD BACKLIGHT SINK2
A BS2
TP-P6
SYNC_MASTER=N/A SYNC_DATE=N/A A
PAGE TITLE
STDOFF-2.7OD1.4ID-1.04H-SM-1
LCD_BL_CA_CONN TP20
1 BATT B2B, TPS, PD FEATURES
PGND_STANDOFF2 1 19 A LCD BACKLIGHT SOURCE
860-1511 TP-P6 DRAWING NUMBER SIZE
1 C434 1 C436 1 C438 Apple Inc. 051-9584 D
100PF 56PF 27PF REVISION
5% 5% 5%
16V
2 NP0-C0G
16V
2 NP0-C0G
16V
2 NP0-C0G
R
2.0.0
01005 01005 01005 NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
22 OF 23
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 22 OF 46
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

RADIO_MLB HIERARCHICAL SYMBOL


AP/RADIO INTERFACE
RF
I612
D 25 22 15 12 8 IN PP_BATT_VCC MAKE_BASE=TRUE PP_BATT_VCC_CONN
D
46 14 13 12 10 PP_VCC_MAIN MAKE_BASE=TRUE PP_VCC_MAIN_WLAN
IN
46 16 14 13 12 10 4 3 PP1V8_SDRAM MAKE_BASE=TRUE PP_WL_BT_VDDIO_AP
IN
26 17 PP_LDO14_2P65 MAKE_BASE=TRUE PP_LDO14_2V65
OUT

25 3 AP_TO_RADIO_ON_L MAKE_BASE=TRUE RADIO_ON_L BB_JTAG_TCK MAKE_BASE=TRUE AP_TO_BB_JTAG_TCK 3 25


IN BI
25 3 BB_TO_AP_RESET_DET_L MAKE_BASE=TRUE RESET_DET_L BB_JTAG_TDI MAKE_BASE=TRUE AP_TO_BB_JTAG_TDI 3 25
OUT BI
25 13 PMU_TO_BB_RST_L MAKE_BASE=TRUE RESET_PMU_L BB_JTAG_TMS MAKE_BASE=TRUE AP_TO_BB_JTAG_TMS 3 25
IN BI
MAKE_BASE=TRUE AP_TO_BB_JTAG_TRST_L
MAKE_BASE=TRUE BB_JTAG_TRST_L BI 3 25
25 3 IN AP_TO_BB_RST_L BB_RST_L MAKE_BASE=TRUE
MAKE_BASE=TRUE BB_JTAG_TDO BB_TO_AP_JTAG_TDO BI 3 25
25 22 19 16 14 13 12 2 OUT RESET_1V8_L RF_RESET_L

25 13 45_PMU_TO_WLAN_CLK32K MAKE_BASE=TRUE CLK32K_AP


IN

29 15 BB_TO_LEDDRV_GSM_BLANK MAKE_BASE=TRUE TX_GTR_THRESH


OUT

25 16 90_TRISTAR_BI_BB_USB_N MAKE_BASE=TRUE 90_BB_USB_D_N


BI
25 16 90_TRISTAR_BI_BB_USB_P MAKE_BASE=TRUE 90_BB_USB_D_P
BI
25 13 PMU_TO_BB_VBUS_DET MAKE_BASE=TRUE BB_USB_VBUS
IN

25 3 AP_TO_BB_UART1_RTS_L MAKE_BASE=TRUE BB_UART_CTS_L


IN
BB_TO_AP_UART1_CTS_L MAKE_BASE=TRUE
25 3 OUT BB_UART_RTS_L
25 16 3 AP_TO_BB_UART1_TXD MAKE_BASE=TRUE BB_UART_RXD
IN
25 16 3 BB_TO_AP_UART1_RXD MAKE_BASE=TRUE BB_UART_TXD
OUT
BB_TO_PMU_HOST_WAKE MAKE_BASE=TRUE
25 13 OUT HOST_WAKE_BB

29 3 BB_TO_AP_PP_SYNC MAKE_BASE=TRUE PP_SYNC


OUT
25 3 45_AP_TO_BB_I2S1_BCLK MAKE_BASE=TRUE BB_I2S_CLK RADIO_MLB
IN
25 3 AP_TO_BB_I2S1_DOUT MAKE_BASE=TRUE BB_I2S_RXD
IN

C 25 3

25 3
OUT
IN
BB_TO_AP_I2S1_DIN
AP_TO_BB_I2S1_LRCLK
MAKE_BASE=TRUE
MAKE_BASE=TRUE
BB_I2S_TXD
BB_I2S_WS
C
RADIO_TO_PMU_ADC_SMPS1_MSMC_1V05 MAKE_BASE=TRUE
25 13 OUT ADC_SMPS1_MSMC_1V05
25 13 RADIO_TO_PMU_ADC_SMPS3_MSME_1V8 MAKE_BASE=TRUE ADC_SMPS3_MSME_1V8
OUT
25 13 RADIO_TO_PMU_ADC_LDO6_RUIM_1V8 MAKE_BASE=TRUE ADC_LDO6_RUIM_1V8
OUT
RADIO_TO_PMU_ADC_LVS1 MAKE_BASE=TRUE
25 13 OUT ADC_LVS1

25 13 PMU_TO_WLAN_REG_ON MAKE_BASE=TRUE WLAN_REG_ON


IN
46 3 AP_TO_WLAN_UART4_TXD MAKE_BASE=TRUE WLAN_UART_RXD
IN
46 3 WLAN_TO_AP_UART4_RXD MAKE_BASE=TRUE WLAN_UART_TXD
OUT
46 13 WLAN_TO_PMU_HOST_WAKE MAKE_BASE=TRUE HOST_WAKE_WLAN
OUT

PMU_TO_BT_REG_ON MAKE_BASE=TRUE
25 13 IN BT_REG_ON
46 3 AP_TO_BT_UART3_RTS_L MAKE_BASE=TRUE BT_UART_CTS_L
IN
46 3 BT_TO_AP_UART3_CTS_L MAKE_BASE=TRUE BT_UART_RTS_L
OUT
AP_TO_BT_UART3_TXD MAKE_BASE=TRUE
25 3 IN BT_UART_RXD
25 3 BT_TO_AP_UART3_RXD MAKE_BASE=TRUE BT_UART_TXD
OUT

25 3 AP_TO_BT_WAKE MAKE_BASE=TRUE BT_WAKE


IN
46 13 BT_TO_PMU_HOST_WAKE MAKE_BASE=TRUE HOST_WAKE_BT
OUT

46 3 45_AP_TO_BT_I2S3_BCLK MAKE_BASE=TRUE BT_PCM_CLK


BI
46 3 AP_TO_BT_I2S3_DOUT MAKE_BASE=TRUE BT_PCM_IN
BI
46 3 BT_TO_AP_I2S3_DIN MAKE_BASE=TRUE BT_PCM_OUT
BI
46 3 AP_TO_BT_I2S3_LRCLK MAKE_BASE=TRUE BT_PCM_SYNC
BI
B B
25 2 50_AP_BI_BB_HSIC1_DATA MAKE_BASE=TRUE 50_HSIC_BB_DATA
BI
25 2 50_AP_BI_BB_HSIC1_STB MAKE_BASE=TRUE 50_HSIC_BB_STROBE
BI
25 3 AP_TO_BB_HSIC1_RDY MAKE_BASE=TRUE AP_HSIC1_RDY
IN
25 3 BB_TO_AP_HSIC1_RDY MAKE_BASE=TRUE PBL_RUN_BB_HSIC1_RDY
OUT
29 3 BB_TO_AP_HSIC1_REMOTE_WAKE MAKE_BASE=TRUE BB_HSIC1_REMOTE_WAKE
BI
29 3 AP_TO_BB_WAKE_MODEM MAKE_BASE=TRUE AP_WAKE_MODEM
IN

25 2 50_AP_BI_WLAN_HSIC3_DATA MAKE_BASE=TRUE 50_HSIC_WLAN_DATA


BI
25 2 50_AP_BI_WLAN_HSIC3_STB MAKE_BASE=TRUE 50_HSIC_WLAN_STROBE
BI
25 3 AP_TO_WLAN_HSIC2_RDY MAKE_BASE=TRUE AP_HSIC3_RDY
OUT
25 3 WLAN_TO_AP_HSIC2_RDY MAKE_BASE=TRUE WLAN_HSIC3_DEVICE_RDY
OUT
25 3 WLAN_TO_AP_HSIC2_REMOTE_WAKE MAKE_BASE=TRUE WLAN_HSIC3_RESUME
BI

25 17 BB_TO_LAT_SW1_CTL MAKE_BASE=TRUE LAT_SW1_CTL


OUT
29 17 BB_TO_LAT_SW2_CTL MAKE_BASE=TRUE LAT_SW2_CTL
OUT
<OUT> BB_TO_LAT_SW3_CTL
29 8 BB_TO_ANTENNA_PAC_SPI_CS_L MAKE_BASE=TRUE BB_SPI_TO_PAC_CS
OUT
29 8 BB_TO_ANTENNA_PAC_SPI_SCLK MAKE_BASE=TRUE BB_SPI_TO_PAC_CLK
OUT
BB_TO_ANTENNA_PAC_SPI_MOSI MAKE_BASE=TRUE
29 8 OUT BB_SPI_TO_PAC_DATA_MOSI
29 ANTENNA_PAC_TO_BB_SPI_MISO MAKE_BASE=TRUE PAC_TO_BB_SPI_DATA_MISO
IN

29 3 BB_TO_AP_IPC_GPIO MAKE_BASE=TRUE BB_IPC_GPIO


BI
OSCAR_CONTEXT_A
OSCAR_CONTEXT_B

A SYNC_MASTER=N/A SYNC_DATE=N/A A
BB_I2S2_CLK PAGE TITLE
BB_I2S2_WS
BB_I2S2_RXD
RADIO_MLB HIERARCH. SYMBOL
DRAWING NUMBER SIZE
BB_I2S_MCLK
Apple Inc. 051-9584 D
REVISION
R
2.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
23 OF 23
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 23 OF 46
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CK
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. APPD
REV ECN DESCRIPTION OF REVISION
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. DATE
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
2 0001669557 ENGINEERING RELEASED 2012-10-14

X155 RADIO_MLB SUBDESIGN - PROTO1


D 10/3/2012 D

PDF PAGE
TABLE_TABLEOFCONTENTS_HEAD
CONTENTS
2
TABLE_TABLEOFCONTENTS_ITEM
AP INTERFACE & DEBUG CONNECTORS
3
TABLE_TABLEOFCONTENTS_ITEM
CELLULAR PMU: (1 OF 2)
4
TABLE_TABLEOFCONTENTS_ITEM
CELLULAR PMU: (2 OF 2)
5 CELLULAR BASEBAND: (1 OF 2)
TABLE_TABLEOFCONTENTS_ITEM

6
TABLE_TABLEOFCONTENTS_ITEM
CELLULAR BASEBAND: (2 OF 2)
7
TABLE_TABLEOFCONTENTS_ITEM
CELLULAR RF TRANSCEIVER: (1 OF 2)
8 CELLULAR RF TRANSCEIVER: (2 OF 2)
TABLE_TABLEOFCONTENTS_ITEM

9 CELLULAR FRONT END: TX AND RX MATCHING BOARD_ID BOM OPTIONS


C TABLE_TABLEOFCONTENTS_ITEM

TABLE_5_HEAD
C
10 CELLULAR FRONT END: SAW BANKS PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION
TABLE_5_ITEM

TABLE_TABLEOFCONTENTS_ITEM

118S0621 1 1.00M 1% 01005 R25_RF Y N51_CFG_A

11
TABLE_TABLEOFCONTENTS_ITEM
CELLULAR FRONT END: BAND 1/4 PAT 118S0732 1 50K 1% 01005 R26_RF Y N51_CFG_A
TABLE_5_ITEM

TABLE_5_ITEM

117S0159 1 470K 5% 01005 R25_RF Y N51_CFG_B


12
TABLE_TABLEOFCONTENTS_ITEM
CELLULAR FRONT END: BAND 2/3 PAD 118S0626 1 100K 1% 01005 R26_RF Y N51_CFG_B
TABLE_5_ITEM

TABLE_5_ITEM

13 CELLULAR FRONT END: BAND 20 PAD 118S0626 1 100K 1% 01005 R25_RF Y N53_CFG_A
TABLE_5_ITEM

TABLE_TABLEOFCONTENTS_ITEM

118S0726 1 162K 1% 01005 R26_RF Y N53_CFG_A

14 CELLULAR FRONT END: BAND 5/8 PAD


TABLE_5_ITEM

118S0626 1 100K 1% 01005 R25_RF Y N53_CFG_B


TABLE_TABLEOFCONTENTS_ITEM TABLE_5_ITEM

118S0623 1 267K 1% 01005 R26_RF Y N53_CFG_B


15 CELLULAR FRONT END: BAND 13/17 PAD 118S0659 1 255K 1% 01005 R25_RF Y N48_CFG_A
TABLE_5_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_5_ITEM

16 CELLULAR FRONT END: PA DCDC CONVERTER 118S0626 1 100K 1% 01005 R26_RF Y N48_CFG_A
TABLE_5_ITEM

TABLE_TABLEOFCONTENTS_ITEM

118S0689 1 147K 1% 01005 R25_RF Y N48_CFG_B

17 CELLULAR FRONT END: 2G FEM 118S0626 1 100K 1% 01005 R26_RF Y N48_CFG_B


TABLE_5_ITEM

TABLE_TABLEOFCONTENTS_ITEM TABLE_5_ITEM

118S0626 1 100K 1% 01005 R25_RF Y N49_CFG_A


18 CELLULAR FRONT END: RX DIVERSITY 118S0650 1 499K 1% 01005 R26_RF Y N49_CFG_A
TABLE_5_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_5_ITEM

19 CELLULAR FRONT END: GPS LNA 118S0732 1 50K 1% 01005 R25_RF Y N49_CFG_B
TABLE_5_ITEM

TABLE_TABLEOFCONTENTS_ITEM

118S0621 1 1.00M 1% 01005 R26_RF Y N49_CFG_B

B 20
TABLE_TABLEOFCONTENTS_ITEM
CELLULAR FRONT END: ANTENNA FEEDS B
21
TABLE_TABLEOFCONTENTS_ITEM
FRONT END LOGIC TABLE (1 OF 2)
22
TABLE_TABLEOFCONTENTS_ITEM
FRONT END LOGIC TABLE (2 OF 2)
23
TABLE_TABLEOFCONTENTS_ITEM
WIFI/BT: MODULE AND FRONT END

SCH :951-2446
A BOM :939-0308 A
BOARD :920-2148
DRAWING TITLE

X155 RADIO_MLB SCHEMATIC


DRAWING NUMBER SIZE

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION


TABLE_5_HEAD

Apple Inc. 051-9584 D


TABLE_5_ITEM REVISION
951-2446 1 X145_RADIO_MLB SCH Y R
2.0.0
NOTICE OF PROPRIETARY PROPERTY:
TABLE_5_ITEM

825-2029 1 EEE FOR 939-0308 EEEE_???? Y NA BRANCH


THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
1 OF 23
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST IV ALL RIGHTS RESERVED 24 OF 46
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

AP INTERFACE & DEBUG CONNECTORS


DEBUG CONNECTOR
AP CONNECTIONS PROBE POINTS PP_BATT_VCC_CONN
IN 232526 34 35 36 37 38 39 40

IN = FROM AP
D OUT = TO AP PP1_RF
P4MM
SM
1 BB_ERROR_FLAG NOSTUFF
D
17 16 15 14 13 12 11 3 2 PP_BATT_VCC_CONN OUT PP 6
J1_RF
PP_VCC_MAIN_WLAN
23 OUT AXE654124
PP2_RF M-ST-SM
6 TX_GTR_THRESH P4MM
OUT
SM 56 55
4 2 BB_RST_L 1 SLEEP_CLK_32K 4 5
IN PP
6 2 RESET_DET_L OUT
PP3_RF 2 1
4 2 RADIO_ON_L P4MM
IN
SM 4 3
4 2 RESET_PMU_L
1 PMIC_SSBI 4 5
IN PP 6 5
6 2 HOST_WAKE_BB OUT 8 7
2 RF_RESET_L OUT
28 DEBUG_RST_L 10 9 PP_SMPS3_MSME_1V8 252628 2931
OUT IN
6 2 PBL_RUN_BB_HSIC1_RDY OUT
27 2523 RESET_PMU_L 12 11 BT_WAKE 2325 46
OUT OUT
23 2 WLAN_HSIC3_RESUME OUT
PP10_RF 27 2523 RADIO_ON_L 14 13
OUT
6 AP_WAKE_MODEM P4MM-NSM
OUT SM 16 15 PP_LDO6_RUIM_1V8 252628
1 19P2M_MDM IN
6 2 AP_HSIC1_RDY 4 5
IN PP
28 2523 BB_USB_VBUS 18 17 WLAN_REG_ON 2325 46
OUT OUT
5 2 50_HSIC_BB_DATA IO
PP11_RF 28 2523 90_BB_USB_D_N 20 19 NC
BI
5 2 50_HSIC_BB_STROBE P4MM
IO
SM 28 2523 90_BB_USB_D_P 22 21 NC
1 CLK32K_AP BI
6 BB_HSIC1_REMOTE_WAKE 2 23
OUT PP
25 23 RF_RESET_L 24 23 PMIC_RESOUT_L 2728
OUT IN
6 2 BB_UART_TXD OUT
PP14_RF 28 2523 BB_JTAG_TCK 26 25 NC
OUT
6 2 BB_UART_RXD P4MM
IN
SM 28 2523 BB_JTAG_TMS 28 27
1 AP_HSIC3_RDY OUT
6 2 BB_UART_RTS_L 2 23 AP_HSIC1_RDY
OUT PP
28 2523 BB_JTAG_TDO 30 29 2325 29
IN IN
6 2 BB_UART_CTS_L BT_REG_ON
IN
PP15_RF 28 2523 BB_JTAG_TDI 32 31 2325 46
OUT IN
5 2 BB_USB_VBUS P4MM HOST_WAKE_BB
IN
SM 28 2523 BB_JTAG_TRST_L 34 33 2325 29
1 WLAN_HSIC3_DEVICE_RDY OUT IN
5 2 90_BB_USB_D_P 2 23
IO PP
28 BB_JTAG_RTCLK 36 35 NC
OUT
5 2 90_BB_USB_D_N IO
PP18_RF 38 37 RESET_DET_L 2325 29
IN
6 2 BB_I2S_CLK P4MM
IN
SM 27 PS_HOLD_PMIC 40 39 SIMCRD_CLK_CONN 2529
6 2 BB_I2S_WS
1 WLAN_HSIC3_RESUME OUT IN
IN PP 2 23
29 2523 BB_UART_TXD 42 41 SIMCRD_IO_CONN
2529

C
IN BI
C 6 2 BB_I2S_TXD

6 2 BB_I2S_RXD
OUT
IN
PP19_RF
P4MM-NSM
SM
29

29
2523

2523
OUT BB_UART_RXD
BB_UART_RTS_L
44
46
43
45
SIM_TRAY_DETECT
BB_RST_L
OUT 2529

2325 27
1 WTR_SSBI_TX_GPS IN OUT
6 PP_SYNC 6 7 SIMCRD_RST_CONN
OUT PP
29 2523 BB_UART_CTS_L 48 47 2529
OUT IN
23 PP_WL_BT_VDDIO_AP IN
PP20_RF 29 GPIO_DEBUG_LED 50 49 PBL_RUN_BB_HSIC1_RDY 2325 29
IN IN
23 2 CLK32K_AP P4MM-NSM
IN SM 29 GPIO_51 GPIO51/BOOT_CONFIG_3 52 51 GPIO54/BOOT_CONFIG_0 2G_FEM_S1 2940
1 WTR_SSBI_PRX_DRX OUT OUT
23 2 WLAN_REG_ON 6 7
IN PP
41 40 29 2G_FEM_S4 GPIO53/BOOT_CONFIG_1 54 53 GPIO48/BOOT_CONFIG_6 LAT_SW1_CTL 2325 29
OUT OUT
23 WLAN_UART_TXD OUT
PP21_RF
23 WLAN_UART_RXD P4MM
IN
SM 58 57
23 HOST_WAKE_WLAN 1 WTR_RX_ON 6 7
OUT PP
23 2 WLAN_HSIC3_DEVICE_RDY OUT
PP22_RF
23 2 AP_HSIC3_RDY IN P4MM
SM
23 2 50_HSIC_WLAN_DATA 1 WTR_RF_ON 6 7
IO PP GPIO/BOOT_CONFIG CONFIGURATION
23 2 50_HSIC_WLAN_STROBE IO
PP40_RF
23 HOST_WAKE_BT OUT P4MM BOOT_CONFIG 6 5 4 3 2 1 0
SM BOOT OPTIONS SW REGISTER
23 2 BT_WAKE 1 WLAN_COEX_TXD 23
IN PP
VALUE 47 48 49 50 51 52 53 54 55
23 2 BT_UART_TXD OUT
PP41_RF BOOT_DEFAULT_OPTION
23 2 BT_UART_RXD IN P4MM 0X00 X 0 0 0 0 0 0 0 X
SM
23 BT_UART_RTS_L
1 LTE_COEX_TXD 6 23
OUT PP BOOT_NAND_OPTION 0X01 X 1 0 0 0 0 0 1 X
23 BT_UART_CTS_L IN
PP42_RF
23 2 BT_REG_ON IN P4MM BOOT_HSIC_OPTION 0X02 X 1 0 0 0 0 1 0 X
SM
23 BT_PCM_CLK
1 50_HSIC_BB_STROBE 2 5
IO PP BOOT_USB_OPTION 0X03 X 1 0 0 0 0 1 1 X
23 BT_PCM_SYNC IO
PP43_RF
23 BT_PCM_OUT IO P4MM ENABLE SAHARA PROTOCOL 0X08 X 1 0 0 1 0 X X X
SM
23 BT_PCM_IN 1 50_HSIC_BB_DATA 2 5
IO PP
6 2 LAT_SW1_CTL OUT
PP44_RF PP4_RF J2_RF
6 LAT_SW2_CTL P4MM P4MM
OUT SM
1 50_HSIC_WLAN_STROBE
SM
1 BB_I2S_CLK
MM4829-2702
F-ST-SM
B 20 6 BB_SPI_TO_PAC_CS OUT
PP

PP45_RF
2 23 PP

PP5_RF
2 6
NOSTUFF
1 50_HSIC_BB_DATA 2 5
B
20 6 BB_SPI_TO_PAC_DATA_MOSI OUT P4MM P4MM
SM SM
20 6 BB_SPI_TO_PAC_CLK 1 50_HSIC_WLAN_DATA 2 23 1 BB_I2S_WS 2 6
PP PP

2
3
4
OUT
20 6 PAC_TO_BB_SPI_DATA_MISO IN
20 18 17 10 3 PP_LDO14_2V65
PP46_RF PP6_RF
OUT P4MM P4MM
SM SM
5 2 BB_JTAG_TCK IN 1 BT_UART_TXD 1 BB_I2S_RXD
PP 2 23 PP 2 6
5 2 BB_JTAG_TDI IN J3_RF
5 2 BB_JTAG_TMS
PP47_RF PP7_RF MM4829-2702
IN P4MM P4MM F-ST-SM
SM SM
5 2 BB_JTAG_TRST_L 1 BT_UART_RXD 1 BB_I2S_TXD
IN PP 2 23 PP 2 6 NOSTUFF
5 2 BB_JTAG_TDO
1 50_HSIC_BB_STROBE 2 5
OUT
2 ADC_SMPS1_MSMC_1V05 OUT

2
3
4
2 ADC_SMPS3_MSME_1V8 OUT
2 ADC_LDO6_RUIM_1V8 OUT
2 ADC_LVS1 OUT
6 BB_IPC_GPIO OUT
23 6 OSCAR_CONTEXT_A IN
23 6 OSCAR_CONTEXT_B IN

SIM CARD CONNECTOR


6 BB_I2S2_CLK OUT
6 BB_I2S2_WS OUT
6 BB_I2S_MCLK 5 3 2
PP_LDO6_RUIM_1V8
OUT
6 BB_I2S2_RXD IN
1
R3_RF
15.00K
SIM CARD ESD PROTECTION
1

1%

A VCC
J11_RF
1/32W
MF
2 01005
A
PAGE TITLE
2 RST SIM-CARD-N48 I/O 7
XW12_RF
SHORT-10L-0.1MM-SM
2925 IN
SIMCRD_RST_CONN
F-ST-SM
SIMCRD_IO_CONN
BI 25 29 U5_RF
TPD4E101DPWR
AP INTERFACE & DEBUG CONNECTORS
PP_SMPS1_MSMC_1V05 1 2 ADC_SMPS1_MSMC_1V05 SON4 DRAWING NUMBER SIZE
SIMCRD_CLK_CONN 3 CLK DETECT 12 SIM_TRAY_DETECT
5 3

XW13_RF
2
2925 IN OUT 2529
PP_LDO6_RUIM_1V8 2 3 5 6 2 SIMCRD_IO_CONN 1 4 SIM_TRAY_DETECT 2 6 Apple Inc. 051-9584 D
SHORT-10L-0.1MM-SM REVISION
PP_SMPS3_MSME_1V8 1 2 ADC_SMPS3_MSME_1V8 SWP 6 1 C177_RF 1 C1_RF
R
2.0.0
8 6 5 3 2 2 GND
XW14_RF 100PF 12V-33PF 5 GND NOTICE OF PROPRIETARY PROPERTY: BRANCH
5% 01005-1
8
9
10
11
13
5

SHORT-10L-0.1MM-SM 6.3V
ADC_LDO6_RUIM_1V8 2 CERM 2 THE INFORMATION CONTAINED HEREIN IS THE
5 3 2 PP_LDO6_RUIM_1V8 1 2 2 PROPRIETARY PROPERTY OF APPLE INC.
01005
2 3 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
XW15_RF SIMCRD_RST_CONN SIMCRD_CLK_CONN
SHORT-10L-0.1MM-SM
6 2 2 6
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
2 OF 23
5 3 PP_LVS1 1 2 ADC_LVS1 2 SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST IV ALL RIGHTS RESERVED 25 OF 46
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

PMU (1 OF 2)
PP_LVS1 OUT 2528

PP_VREG INTERNAL USE ONLY

D 1 C12_RF
1.0UF
D
20%
6.3V
2 X5R
L1_RF 0201-1
2.2UH-20%-1.2A-0.15OHM
1 2 PP_SMPS1_MSMC_1V05 OUT 2528
0806
1 C55_RF
22UF
20%
6.3V
2 X5R-CERM-1
603

L4_RF S1_GND 3 4
2.2UH-20%-1.2A-0.15OHM
1 2 PP_SMPS2_RF1_1V3 OUT 2831
0806
1 C56_RF
22UF
20%
6.3V
2 X5R-CERM-1
603

L2_RF S2_GND 3 4
REF_BYP U2_RF 2.2UH-20%-1.2A-0.15OHM
PM8018-0 1 2 PP_SMPS3_MSME_1V8 2526282931
1 OUT
C50_RF BGA 0806
0.1UF VREG
20% (SYM 5 OF 5) 1 1 C60_RF
XW17_RF 4V
2 X5R C57_RF
SHORT-10L-0.1MM-SM 28 REF_BYP VOUT_LVS1 53 22UF 0.1UF
01005 20%
1 2 34 REF_GND 20% 4V
2 6.3V
X5R-CERM
2 X5R
01005
NOSTUFF REF_GND VREG_RFCLK 13 0603-3
NOSTUFF
S3_GND
C 40 39 38 37 36 35 34 25 23 IN PP_BATT_VCC_CONN 104 VDD_S1 92 PP_VSW_S1 L3_RF
2.2UH-20%-1.2A-0.15OHM
3 4
C
VSW_S1 97
1 2 PP_SMPS4_RF2_2V05 OUT 2631
1 C42_RF 1 C43_RF 1 C44_RF 1 C45_RF VREG_S1 79
0806
10UF 10UF 10UF 56PF 95 VDD_S2 90 PP_VSW_S2
20% 20% 20% 5% 1
2 6.3V 2 6.3V 2 6.3V 2 16V VSW_S2 102 C58_RF
CERM CERM CERM NP0-C0G
0402 0402 0402 01005 83 22UF
VREG_S2 20%
6.3V
6 42 2 X5R-CERM
VSW_S3 PP_VSW_S3 0603-3
18 48
VDD_S3 S4_GND
24 VSW_S5_2 100 L5_RF 3 4

VREG_S3 12 2.2UH-20%-2.3A-0.115OHM
98 VDD_S4 81 PP_VSW_S4 1 2 PP_SMPS5_DSP_1V05 26
OUT
VSW_S4 87 TFA252010-SM

VREG_S4 105 1 C59_RF


89 82 PP_VSW_S5 22UF
VDD_S5 VSW_S5 20%
101 88 6.3V
2 X5R-CERM-1
VREG_S5 76 603
1 C46_RF 1 C47_RF 1 C48_RF 1 C49_RF 1 C51_RF S5_GND 3
4.7UF 4.7UF 4.7UF 4.7UF 4.7UF 4
20% 20% 20% 20% 20%
10V 10V 10V 10V 10V
2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM PP_LDO1
8 VDD_XO VREG_XO 20
0402 0402 0402 0402 0402 INTERNAL USE ONLY
44 VDD_L2_L3 VREG_L2 31 PP_LDO2_XO_HS_1V8 OUT 28
4 3 S1_GND 4 3 S2_GND 4 3 S3_GND 4 3 S4_GND 4 3 S5_GND 32 PP_LDO3_AMUX_1V8
VREG_L3 OUT 2728
78 VDD_L4 VREG_L4 84 PP_LDO4_VDDA_3V3 OUT 28

VREG_L5 11 PP_LDO5_GPS_LNA_2V5 OUT 42


5 VDD_L5_L6_L13_L14 VREG_L6 17 PP_LDO6_RUIM_1V8 OUT 2528

VREG_L13 23 PP_LDO13_VDDPX_2V95 OUT 28

VREG_L14 29 PP_LDO14_2V65
B 3126 IN
PP_SMPS4_RF2_2V05
PP_SMPS3_MSME_1V8
75
58
VDD_L7 VREG_L7 63
54
PP_LDO7_DAC_1V8
PP_LDO8_VDDPX_1V2
OUT
OUT
2325 33 40 41

28
43

B
3129282625 IN VDD_L8 VREG_L8 OUT 28
70 VDD_L9 VREG_L9 77 PP_LDO9_PLL_1V05 OUT 28

26
PP_SMPS5_DSP_1V05 59 VDD_L10_L11 VREG_L10 65 PP_LDO10_ADSP_1V05 28
IN OUT
VREG_L11 55 PP_LDO11_MDSP_FW_1V05 OUT 28
64 VDD_L12 VREG_L12 43 PP_LDO12_MDSP_SW_1V05 OUT 28

1 C2_RF 1 C3_RF 1 C4_RF 1 C6_RF 1 C8_RF 1 C10_RF 1 C13_RF


1.0UF 1.0UF 1.0UF 1.0UF 10UF 10UF 10UF
20% 20% 20% 20% 20% 20% 20%
2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM
0201-1 0201-1 0201-1 0201-1 0402 0402 0402

1 C52_RF 1 1 1 1 1 1
C53_RF C54_RF C5_RF C7_RF C9_RF C11_RF
1.0UF 1.0UF 1.0UF 1.0UF 1.0UF 10UF 10UF
20% 20% 20% 20% 20% 20% 20%
2 6.3V
X5R 6.3V
2 X5R
6.3V
2 X5R
6.3V
2 X5R
6.3V
2 X5R
6.3V
2 CERM
6.3V
2 CERM
0201-1 0201-1 0201-1 0201-1 0201-1 0402 0402

A A
PAGE TITLE
CELLULAR PMU: (1 OF 2)
DRAWING NUMBER SIZE

Apple Inc. 051-9584 D


REVISION
R
2.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
3 OF 23
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST IV ALL RIGHTS RESERVED 26 OF 46
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

PMU (2 OF 2)
282726 PP_LDO3_AMUX_1V8
IN

1
1
R23_RF R25_RF
BOARD_ID REVISION 100K 102K
1% 1% PA_ID > 1.00V FOR MAV7
D 0.7V PROTO1 1/32W
MF
2 01005
1/32W
MF
2 01005
NOSTUFF PA_ID < 1.00V FOR MAV8
D
0.9V PROTO2 BOARD_ID PA_ID

1.1V EVT1 1
R24_RF
1
R26_RF
61.9K 15.8K
1%
1.3V EVT2 1%
1/32W
MF
1/32W
MF U2_RF
2 01005 2 01005 PM8018-0
NOSTUFF
1.5V DVT BGA
MPP MISC
(SYM 4 OF 5)
1.7V PVT 85 MPP_01 GPIO_01 33
NC
67 MPP_02 GPIO_02 38
NC
28 VDDPX_BIAS 66 MPP_03 GPIO_03 50
OUT NC
72 MPP_04 GPIO_04 60
NC NC
NC 73 MPP_05 GPIO_05 71
NC
29 VREF_DAC_BIAS 80 MPP_06 GPIO_06 49
IN NC

R21_RF
1.00K2 PA THERMISTOR REMOVED TO MATCH N41, AP SECTION
25 23 IN BB_RST_L 1
NEEDS ITS OWN THERMISTOR PLACED NEAR THE PAS.
5%
1/32W
MF
U2_RF
01005 PM8018-0
BGA
CONTROL
R20_RF (SYM 1 OF 5)
20.0K2 PS_HOLD_PMIC 47 PS_HOLD
29 IN PS_HOLD 1 2
LED_DRV_N 86 NC

C 5%
1/32W
MF
01005
C
25 23 RADIO_ON_L 69 KPD_PWR* PON_RESET* 4 PMIC_RESOUT_L 2528
IN OUT
25 23 RESET_PMU_L 16 PM_RESIN_N
IN
PM_USR_INT_N 21 PM_USR_IRQ_L OUT 29

NC 62 OPT_1 PM_MDM_INT_N 14 PM_MDM_IRQ_L OUT 29

NC 74 OPT_2

PON_TRIG 41
2825 PMIC_SSBI 68 SSBI BAT_ID 35
BI

GND NEEDS TO BE CLEARED UNDER THIS CRYSTAL


TO MINIMIZE THERMAL DRIFT
Y1_RF
19.200MHZ
2.0X1.6-SM
1 3 19P2M_XTAL_IN

4 2 U2_RF
PM8018-0
BGA
CLOCKS
(SYM 2 OF 5)
1 XTAL_19M_IN
19P2M_XTAL_OUT 2 XTAL_19M_OUT XO_OUT_A0 19 19P2M_WTR 30
OUT
XO_OUT_D0 25 19P2M_MDM 2528
OUT
282726 IN
PP_LDO3_AMUX_1V8

B XW1_RF B
U2_RF SHORT-10L-0.25MM-SM
1 2
1
R22_RF 3 XTAL_32K_IN XO_OUT_A1 37 NC
PM8018-0 100K NC 15 XTAL_32K_OUT
NOSTUFF 1% 19P2M_CLK_EN
BGA 1/32W XO_OUT_D0_EN 9 IN 28
INPUT PWR XW2_RF MF
45 GND1
(SYM 3 OF 5) SHORT-10L-0.25MM-SM 2 01005
91 3 S1_GND 1 2
GND_S1 103 27 GND0 SLEEP_CLK 26 SLEEP_CLK_32K 2528
NOSTUFF OUT
XW3_RF XO_THERM_Y1 10 XO_THERM
GND_S2 96 3 S2_GND SHORT-10L-0.25MM-SM
30 1 2 22 XOADC_GND
3 S3_GND 1 C127_RF
GND_S3 36 NOSTUFF 1000PF RSVD 7
10%
93 3 S4_GND XW4_RF 6.3V
2 X5R-CERM
GND_S4 99 SHORT-10L-0.25MM-SM
01005
1 2
GND_S5 94 3 S5_GND
NOSTUFF
39 XW16_RF
SHORT-10L-0.25MM-SM XO_GND
51 1 2

NC 57 VCOIN 61 NOSTUFF 2
56
GND XW10_RF
46 SHORT-10L-0.1MM-SM
52
1
40

A A
PAGE TITLE

CELLULAR PMU: (2 OF 2)
DRAWING NUMBER SIZE

Apple Inc. 051-9584 D


REVISION
R
2.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
4 OF 23
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST IV ALL RIGHTS RESERVED 27 OF 46
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

BASEBAND (1 OF 2) U1_RF
282625 IN PP_SMPS1_MSMC_1V05 MDM9615M
BGA
1 C15_RF 1 C18_RF 1 C20_RF 1 C23_RF 1 C26_RF (6 OF 6)
1.0UF 1.0UF 1.0UF 1.0UF 1.0UF GND
20% 20% 20% 20% 20% A21 M14
6.3V
2 X5R 6.3V
2 X5R 6.3V
2 X5R 6.3V
2 X5R 6.3V
2 X5R
AA1 M15
0201-1 0201-1 0201-1 0201-1 0201-1
AA21 M16
B2 M17

D B7
B11
M19
N6
D
PP_LDO9_PLL_1V05 PP_LDO10_ADSP_1V05 PP_LDO11_MDSP_FW_1V05
2826 IN 2826 IN 2826 IN B14 N7
1 C30_RF
1 C16_RF 1 C19_RF 1 C21_RF 1 C24_RF 1 C27_RF 1 C34_RF 1 C35_RF 1 C36_RF B15 N10
1.0UF
1.0UF 1.0UF 1.0UF 1.0UF 1.0UF 20% 1.0UF 1.0UF 1.0UF C19 N11
20% 20% 20% 20% 20% 6.3V 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 2 X5R 6.3V 6.3V 6.3V F6 N14
2 X5R
0201-1
2 X5R
0201-1
2 X5R
0201-1
2 X5R
0201-1
2 X5R
0201-1
0201-1 2 X5R
0201-1
2 X5R
0201-1
2 X5R
0201-1 F7 P6 U1_RF
F10 P10 MDM9615M
BGA
F15 P11 (2 OF 6) R10_RF
F16 GND R6 EBI1_EBI2 240
PP_SMPS3_MSME_1V8 PP_SMPS3_MSME_1V8 PP_LDO12_MDSP_SW_1V05 F19 R10 EBI1_CAL C21 EBI1_CAL 1 2
3129 282625 IN 31292826 25 IN 2826 IN 1%
G2 R11 1/32W
1 C14_RF 1 C17_RF 1 C22_RF 1 C25_RF 1 C28_RF 1 C29_RF 1 C32_RF NC D21 EBI2_NAND_CS* EBI2_AD_0 J20 NC MF
G6 R15 01005
1.0UF 1.0UF 1.0UF 1.0UF 1.0UF 1.0UF 1.0UF NC E19 EBI2_OE* EBI2_AD_1 J19 NC
20% 20% 20% 20% 20% 20% 20% G10 R16
2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R
6.3V
2 X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R NC D20 EBI2_WE* EBI2_AD_2 G19 NC
G11 R17
0201-1 0201-1 0201-1 0201-1 0201-1 0201-1 0201-1 D19 H20
G15 R19 NC EBI2_BUSY* EBI2_AD_3 NC
EBI2_AD_4 J21 NC
G16 T10
EBI2_AD_5 H19 NC
G17 T12
NC C20 EBI2_CLE* EBI2_AD_6 H21 NC
G20 T13
NC E20 EBI2_ALE* EBI2_AD_7 E21 NC
H6 T14
H10 GND U2
U1_RF H11 V19
MDM9615M H15
BGA
(5 OF 6) H16 F11
PWR J6 J16
282625
PP_SMPS1_MSMC_1V05 F8 AA20 PP_SMPS3_MSME_1V8 25262829 31
IN IN J7 K16
F9 B19

C 282625
PP_SMPS1_MSMC_1V05
IN
F12
F13
VDD_DDR F20
M20
J10
J11
L16
T6 C
J14 T7
1 C68_RF F14
J15 T11
1.0UF G9 C5 PP_LDO10_ADSP_1V05
IN 2628
20% K6 U9
6.3V
2 X5R G12 C6 GND_ANA
K7 U12
0201-1 H9 E6
VDD_ADSP K10 W7
H12 E7
K11 W14
J8 F5
K14 Y7
J9
K15 Y11
J12 T15 PP_LDO11_MDSP_FW_1V05 2628
IN K20 Y15
J13 T16
L2 Y18
K8 T17
L6 U13
K9 U14
L7 W13
K12 VDD_MDSP_FW U15
L10
K13 U16
L11
L8 U17
VDD_CORE L14
L9 U19
L15
L12 T19
M6
L13
M7
M8 N15 PP_LDO12_MDSP_SW_1V05 2628
IN M10
M9 N16
M11
M12 N17
M13 N19 PP_LVS1 2526
IN
N8 VDD_MDSP_SW P15
1
N9 P16 R6_RF
N12 P17
470K
5%
U1_RF
B N13
P9
P19 1/32W
MF
2 01005 MDM9615M
BGA
B
P12 VDD_QFUSE_PRG B13 (1 OF 6)
R9 DIGITAL
PMIC_RESOUT_L Y20 RESIN* RESOUT* U20 NC
R12 VDD_USB_1P8 E12 PP_LDO2_XO_HS_1V8 26
2725 IN
IN DEBUG_RST_L Y4 SRST*
25 IN
T8 VDD_USB_3P3 E10 PP_LDO4_VDDA_3V3 IN 26
1 AA19 SLEEP_CLK
T9 C71_RF 2725 IN SLEEP_CLK_32K
VDDPX_BIAS
1.0UF
VDD_HVPAD_BIAS E16 IN 27
20%
PP_LDO9_PLL_1V05 C17
6.3V
2 X5R 25 23 IN BB_JTAG_TCK Y3 TCK TDO AA3 BB_JTAG_TDO OUT 23 25
2826 IN 0201-1 25 23 BB_JTAG_TDI AA2 TDI RTCK Y2 BB_JTAG_RTCLK 25
C18 K17 1 IN OUT
C31_RF BB_JTAG_TMS W4 R9_RF
VDD_PLL1 PP_LDO9_PLL_1V05 0.1UF 25 23 IN TMS
E17 L17 IN 26 28
AA4 50_HSIC_CAL 240
F17 PP_LDO3_AMUX_1V8
20%
4V 25 23 IN BB_JTAG_TRST_L TRST* HSIC_CAL A8 1 2
VDD_PLL2 W12 IN 26 27 2 X5R 50_HSIC_BB_DATA
G7 01005 HSIC_DATA C7 BI 23 25 1%
1/32W
NOSTUFF W20 MODE_0 HSIC_STB B8 50_HSIC_BB_STROBE 23 25 MF
G8 NC BI
VDD_A2 U6 PP_LDO7_DAC_1V8 IN 26
Y19 MODE_1
01005
G13 VDD_A2 U7 NC
G14 GND AA11 PP_SMPS2_RF1_1V3
2631 2725
19P2M_MDM V20 CXO
H7 IN IN
GND AA18 U21 CXO_EN
1 C70_RF 1 C33_RF 27 OUT 19P2M_CLK_EN
H8
1.0UF 1.0UF 27 25 PMIC_SSBI Y21 SSBI_PMIC
H13 BI
VDD_MEM VDD_A1 W9 20% 20% E8
H14
6.3V 6.3V NC
VDD_A1 AA7 2 X5R 2 X5R
C11 C8
0201-1 0201-1 25 23 BI 90_BB_USB_D_P USB_HS_DP NC
P7 GND AA15
25 23 90_BB_USB_D_N E11 USB_HS_DM DNC B9 NC
P8 BI
PP_SMPS3_MSME_1V8 RREFEXT A12 USB_HS_REXT A9 NC
P13 A15 IN 252628 2931
ID IS NC C12 USB_HS_ID
P14 G1
1 C69_RF B12 USB_HS_SYSCLK
R7 G21
1.0UF 25 23 IN BB_USB_VBUS C10 USB_HS_VBUS
R8 VDD_P3 L1 20%
6.3V E9
A R13
R14
U1
W19
2 X5R
0201-1 C9
NC
NC A
DNC B10 NC PAGE TITLE

3129 282625 IN
PP_SMPS3_MSME_1V8 A14 VDD_P4 A2 PP_LDO6_RUIM_1V8 IN 2526
1
R7_RF
200
A10 NC CELLULAR BASEBAND: (1 OF 2)
A19 A3 PP_SMPS3_MSME_1V8 1% DRAWING NUMBER SIZE
VDD_P5 1/32W
F21 VDD_P6 A7 PP_LDO8_VDDPX_1V2
IN 252628 2931
MF SDC1_CMD K19 NC
Apple Inc. 051-9584 D
VDD_P1 IN 26
2 01005 SDC1_CLK L21 NC REVISION
M1 VDD_P7 A11 PP_SMPS3_MSME_1V8
M21
IN 252628 2931 R
2.0.0
SDC1_DATA0 L19 NC NOTICE OF PROPRIETARY PROPERTY: BRANCH
SDC1_DATA1 L20 NC THE INFORMATION CONTAINED HEREIN IS THE
26 PP_LDO13_VDDPX_2V95 K21 VDD_P2 PROPRIETARY PROPERTY OF APPLE INC.
IN N20
SDC1_DATA2 NC THE POSESSOR AGREES TO THE FOLLOWING: PAGE
SDC1_DATA3 N21 NC I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
5 OF 23
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST IV ALL RIGHTS RESERVED 28 OF 46
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

BASEBAND (2 OF 2)

D D

U1_RF
MDM9615M
BGA
(4 OF 6)
ANALOG
DAC0_VREF W5 VREF_DAC_BIAS
OUT 27

1 C62_RF
30 IN PRX_BB_I_P U8 BBRX_IP_CH0 0.1UF 8 6 5 3 2 PP_SMPS3_MSME_1V8
20%
PRX_BB_I_N W8 BBRX_IM_CH0
30 IN 2 4V
X5R
PRX_BB_Q_P Y8 BBRX_QP_CH0 TX_DAC1_QP Y13 NC 01005 1
30 IN R4_RF
30 IN PRX_BB_Q_N AA8 BBRX_QM_CH0 TX_DAC1_QM AA13 NC
1%
100K U1_RF
1/32W
MF
MDM9615M
DRX_BB_I_P Y10 BBRX_IP_CH1 TX_DAC0_IP Y6 TX_BB_I_P BGA
30 IN BI 30
2 01005 (3 OF 6)
30 IN DRX_BB_I_N AA10 BBRX_IM_CH1 TX_DAC0_IM AA6 TX_BB_I_N OUT 30
Y9 Y5 TX_BB_Q_P B6 GPIO P3
30 IN DRX_BB_Q_P BBRX_QP_CH1 TX_DAC0_QP OUT 30 25 IN SIM_TRAY_DETECT GPIO_0 GRFC_14 GPIO_44 PA_R1 OUT 34 35 36 37 38

30 DRX_BB_Q_N AA9 BBRX_QM_CH1 TX_DAC0_QM AA5 TX_BB_Q_N 30 SIMCRD_RST_CONN A6 GPIO_1 GRFC_15 GPIO_45 R1
IN OUT 25 OUT
NC, SECOND TRANSCEIVER RF_ON CONTROL
TX_DAC0_IREF W6 WTR_BB_TX_DAC_IREF 30 25 OUT SIMCRD_CLK_CONN A5 GPIO_2 GRFC_18,SW GPIO_46 N5 LAT_SW3_CTL
OUT
W17 SIMCRD_IO_CONN B5 N3 2G_FEM_S6
C
NC
NC W18
BBRX_IP_CH2
BBRX_IM_CH2 TX_DAC1_IP Y14 NC 43
25

25 23 OUT
BI
BB_SPI_TO_PAC_CLK C4
GPIO_3
GPIO_4
GRFC_19,SW GPIO_47
GRFC_20 GPIO_48 P2 LAT_SW1_CTL BOOT_CONFIG_6
OUT
OUT
33 40 41

23 25 C
NC W15 BBRX_QP_CH2 TX_DAC1_IM AA14 NC 43 25 23 OUT BB_SPI_TO_PAC_CS B3 GPIO_5 GRFC_21 GPIO_49 M2 TX_GTR_THRESH BOOT_CONFIG_5 OUT 23 25

NC W16 BBRX_QM_CH2 43 25 23 OUT PAC_TO_BB_SPI_DATA_MISO B4 GPIO_6 GRFC_22 GPIO_50 N1 BOOT_CONFIG_4


NC, ELNA CONTROL
43 25 23 OUT BB_SPI_TO_PAC_DATA_MOSI A4 GPIO_7 GRFC_23 GPIO_51 N2 GPIO_51 BOOT_CONFIG_3 25
IN
H17 NC SPI_CLK A16 GPIO_8 GRFC_24,SW GPIO_52 M3 2G_FEM_S5 BOOT_CONFIG_2
29 OUT OUT 40 41
J17 NC 29 OUT SPI_CS_L A13 GPIO_9 GRFC_25,SW GPIO_53 L3 2G_FEM_S4 BOOT_CONFIG_1 2540 41
OUT
30 GPS_BB_I_P W10 GNSS_BB_IP 29 SPI_DATA_MISO E14 GPIO_10 GRFC_26,SW GPIO_54 M5 2G_FEM_S1 BOOT_CONFIG_0 2540
IN IN OUT
30 IN GPS_BB_I_N U10 GNSS_BB_IM V21 NC 29 OUT SPI_DATA_MOSI E13 GPIO_11 GRFC_27,SW GPIO_55 L5 2G_FEM_S0 OUT 40

30 GPS_BB_Q_P W11 GNSS_BB_QP W21 NC 25 23 OUT BB_UART_RTS_L C14 GPIO_12 GRFC_28,SW GPIO_56 K1
IN NC
30 IN GPS_BB_Q_N U11 GNSS_BB_QM Y12 NC 25 23 IN BB_UART_CTS_L C13 GPIO_13 GRFC_29,SW GPIO_57 K5 2G_FEM_S2 OUT 33 40
DNC Y16 E15 K3
NC 25 23 OUT BB_UART_RXD GPIO_14 GRFC_30,SW GPIO_58 2G_FEM_S3 OUT 33 40 41
Y17 NC 25 23 BB_UART_TXD A18 GPIO_15 GRFC_31 GPIO_59 K2 LAT_SW2_CTL 23 25
IN OUT
AA12 NC NC C15 GPIO_16 GRFC_32 GPIO_60 J2 DCDC_EN 39
OUT
AA16 NC 46 25 IN OSCAR_CONTEXT_A B16 GPIO_17 GRFC_33 GPIO_61 J5 DCDC_MODE OUT 39
AA17 NC 25 23 IN AP_WAKE_MODEM B18 GPIO_18 GRFC_34 GPIO_62 J1
NC, APT_BYPASS
25 OUT GPIO_DEBUG_LED C16 GPIO_19 GRFC_35,SW GPIO_63 J3
NC
25 23 BB_I2S_CLK A17 GPIO_20 GRFC_36 GPIO_64 H3 BB_PDM 39
BI OUT
25 23 OUT BB_I2S_WS B21 GPIO_21 GRFC_37 GPIO_65 H5 LTE_COEX_RXD 29 46
IN
25 23 BB_I2S_RXD B20 GPIO_22 GRFC_38 GPIO_66 G5 LTE_COEX_TXD 2529 46
BI OUT
25 23 OUT BB_I2S_TXD A20 GPIO_23 GRFC_39 GPIO_67 H1 LTE_ACTIVE 46
OUT
25 OUT BB_I2S_MCLK B17 GPIO_24 GPIO_68 H2 BB_HSIC1_REMOTE_WAKE 23 25
OUT
25 OUT BB_I2S2_CLK P21 GPIO_25 GPIO_69 F3 BB_IPC_GPIO 23 25
BI
25 OUT BB_I2S2_WS R21 GPIO_26 GPIO_70 F1 WTR_SSBI_PRX_DRX 25 30
BI
25 BB_I2S2_RXD P20 GPIO_27 GPIO_71 G3 WTR_SSBI_TX_GPS 25 30
IN BI
NC R20 GPIO_28 GPIO_72 V3
NC
T20 GPIO_29 GPIO_73 W3 BB_ERROR_FLAG 25
I2C_SCL OUT
B I2C_SDA
T21
U5
GPIO_30 GPIO_74
GPIO_31 GRFC_0,PA_ON GPIO_75
W2
W1
WTR_GP_DATA0 GPH
WTR_GP_DATA1 GPH
OUT 30

30
B
GSM_PA_LB_EN OUT
V2 GPIO_32 GRFC_1,PA_ON GPIO_76 Y1
GSM_PA_HB_EN NC, WTR_GP_DATA2
FL4_RF 35 OUT PA_ON_B2_B3 V1 GPIO_33 GRFC_2,PA_ON GPIO_77 F2 WLAN_TX_BLANK
IN 46
70-OHM-300MA 34 PA_ON_B1_B4 U3 GPIO_34 GRFC_3,PA_ON GPIO_78 E2 OSCAR_CONTEXT_B 25 46
OUT IN
3129282625
PP_SMPS3_MSME_1V8 1 2 PP_SPI_NOR_1V8 T3 GPIO_35 GRFC_4,PA_ON GPIO_79 E3 PBL_RUN_BB_HSIC1_RDY 23 25
IN NC OUT
01005-1 37 OUT PA_ON_B5_B8 T1 GPIO_36 GRFC_5,PA_ON GPIO_80 D1 AP_HSIC1_RDY IN 23 25
1 C61_RF 36 OUT PA_ON_B20 T5 GPIO_37 GRFC_6,PA_ON GPIO_81 E1 PM_MDM_IRQ_L OUT 27
0.1UF 38 OUT PA_ON_B13_B17 R5 GPIO_38 GRFC_7,PA_ON GPIO_82 D2 RESET_DET_L OUT 23 25
20%
4V PA_BS R3 D3 PS_HOLD
2 X5R 38 37 35 34 OUT GPIO_39 GRFC_8,PA_ON GPIO_83 OUT 27
01005 T2 C1
NC GPIO_40 GRFC_9,SW GPIO_84 NC
3025 OUT WTR_RX_ON R2 GPIO_41 GRFC_10 GPIO_85 B1 PP_SYNC OUT 23 25

3025 OUT WTR_RF_ON P5 GPIO_42 GRFC_11 GPIO_86 C2 HOST_WAKE_BB OUT 23 25


P1 C3 PM_USR_IRQ_L
B2

PA_R0 GPIO_43 GRFC_13 GPIO_87 OUT 27

VCC

U6_RF
SERIAL-SPI-2MX8-1.8V
WLCSP
MX25U1635EBAI-10G B3 SPI_CS_L
D3 CS* IN 29
WP*/SIO2
SO/SIO1 C3 SPI_DATA_MISO 29
LTE_WLAN_PRIORITY LTE_COEX_RXD 2946
SPI_DATA_MOSI E2 OUT ALIAS IN
29 IN SI/SIO0 LTE_FRAME_SYNC LTE_COEX_TXD
ALIAS OUT 252946
A4 NC
29 SPI_CLK D2 SCLK
IN F1 NC
C2 NC
NC/SIO3 F4 NC
GND

A A
E3

PAGE TITLE

CELLULAR BASEBAND: (2 OF 2)
DRAWING NUMBER SIZE

Apple Inc. 051-9584 D


REVISION
R
2.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
6 OF 23
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST IV ALL RIGHTS RESERVED 29 OF 46
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

RF TRANSCEIVER (1 OF 4)
PRX TRANSCEIVER RF AND IQ PORTS TRANSCEIVER PHASE CONTROL, TX RF & IQ PORTS

D U3_RF
U3_RF D
WTR1605 WTR1605
SM
SM SYM 2 OF 5
SYM 3 OF 5 TX
78 PRX TX_BB_I_P 130 140 50_XCVR_B13_B17_B20_TX
33 IN
100_XCVR_B13_B17_B20_PRX_P PRX_LB1_INP PRX_BB_IP 84 PRX_BB_I_P
OUT 29
29 IN TX_BB_IP TX_LB1 OUT 33

69 TX_BB_I_N 138 132 50_XCVR_2G_LB_TX


33 IN
100_XCVR_B13_B17_B20_PRX_N PRX_LB1_INM PRX_BB_IM 92 PRX_BB_I_N OUT 29
29 IN TX_BB_IM TX_LB2 OUT 40

TX_LB3 141 50_XCVR_B8_TX


61 TX_BB_Q_P 131 OUT 33
32 IN
100_XCVR_B8_PRX_N PRX_LB2_INP PRX_BB_QP 91 PRX_BB_Q_P OUT 29
29 IN TX_BB_QP
TX_LB4 133 50_XCVR_B5_B18_TX
54 TX_BB_Q_N 139 OUT 33
32 IN
100_XCVR_B8_PRX_P PRX_LB2_INM PRX_BB_QM 82 PRX_BB_Q_N OUT 29
29 IN TX_BB_QM
TX_MB1 126 50_XCVR_B2_B25_TX
48 WTR_BB_TX_DAC_IREF 109 OUT 32
32 IN
100_XCVR_B5_B18_PRX_P PRX_LB3_INP DNC 86 NC
29 IN DAC_REF
TX_MB2 119 50_XCVR_2G_HB_TX 40
OUT
32
100_XCVR_B5_B18_PRX_N 43 PRX_LB3_INM WTR_GP_DATA0 GPH 105 112 50_XCVR_B3_B4_TX
IN 29 IN GP_DATA0 TX_MB3 OUT 32

100_XCVR_B2_B25_PRX_P 36 29
WTR_GP_DATA1 GPH 121 GP_DATA1 TX_MB4 95 50_XCVR_B1_TX 32
32 IN PRX_MB1_INP IN OUT
100_XCVR_B2_B25_PRX_N 30 88 GP_DATA2
32 IN PRX_MB1_INM WTR_GP_DATA2, NC 114 TX_HB 103NC
NC 96 DNC
32 IN
100_XCVR_B3_PRX_P 23 PRX_MB2_INP
NC DNC DNC 93 NC
C248_RF R29_RF
32 IN
100_XCVR_B3_PRX_N 17 PRX_MB2_INM 56PF 47
90 DNC PDET_IN 101 50_PDET_IN 1 2 50_PDET_PAD_OUT 1 2 50_PDET_PAD_IN
100_XCVR_DCS_PCS_PRX_N 8 R27_RF NC IN 40
33 IN PRX_MB3_INP 4.75K2 5%
100_XCVR_DCS_PCS_PRX_P 16 1 WTR_RBIAS 60 RBIAS 5% 1/32W
33 IN PRX_MB3_INM 16V MF
1% NP0-C0G 1 01005 1
100_XCVR_B1_B4_PRX_P 7 1/32W 79 VTUNE_PRX 01005 R28_RF R30_RF
32 IN PRX_HB_INP MF WTR_VTUNE 130 130
100_XCVR_B1_B4_PRX_N 15 01005 45
DC-BLOCK NEEDED 1% 1%
32 IN PRX_HB_INM 29 25
WTR_RX_ON RX_ON FOR SELF CAL 1/32W 1/32W
IN
WTR_RF_ON 100 MF MF
29 25 IN RF_ON 2 01005 2 01005
2925
WTR_SSBI_TX_GPS 89 SSBI_TX_GNSS
BI
DRX TRANSCEIVER RF AND IQ PORTS 2925
WTR_SSBI_PRX_DRX 80 SSBI_PRX_DRX
BI
134 GND 7 DB ATTENUATOR
C U3_RF
WTR1605 C128_RF
100PF
120 XO_IN
C
SM 27 IN
19P2M_WTR 1 2 19P2M_WTR_IN
SYM 1 OF 5
DRX_GPS 5%
41
100_XCVR_B8_B20_DRX_P 5 DRX_LB1_INP DRX_BB_IP 63 DRX_BB_I_P 29
16V
IN OUT NP0-C0G 1 C182_RF
41
100_XCVR_B8_B20_DRX_N 14 DRX_LB1_INM DRX_BB_IM 72 DRX_BB_I_N 29
01005
IN OUT 10PF
5%
100_XCVR_B5_B18_B13_B17_DRX_P 4 DRX_LB2_INP DRX_BB_QP 50 DRX_BB_Q_P 2 16V
41 IN OUT 29 CERM
41
100_XCVR_B5_B18_B13_B17_DRX_N 13 DRX_LB2_INM DRX_BB_QM 57 DRX_BB_Q_N 29
01005
IN OUT NOSTUFF
41
100_XCVR_B2_B25_B3_DRX_P 3 DRX_MB_INP
IN
41
100_XCVR_B2_B25_B3_DRX_N 12 DRX_MB_INM
IN

41
100_XCVR_B1_B4_DRX_P 2 DRX_HB_INP
IN
41
100_XCVR_B1_B4_DRX_N 11 DRX_HB_INM
IN

41
100_XCVR_GPS_RX_P 10 GNSS_INP GNSS_BB_IP 56 GPS_BB_I_P 29
IN OUT
41
100_XCVR_GPS_RX_N 18 GNSS_INM GNSS_BB_IM 62 GPS_BB_I_N 29
IN OUT

GNSS_BB_QP 70 GPS_BB_Q_P OUT 29

GNSS_BB_QM 71 GPS_BB_Q_N OUT 29

GND 1

TRANSCEIVER GROUND CONNECTIONS

U3_RF
B WTR1605
SM
B
SYM 5 OF 5
GND
46 GND
77 GND 125
GND
47 GND 124
GND
68 GND GND 123
29 GND GND 110
22 GND GND 102
27 GND GND 99
21 GND GND 129
20 GND GND 94
33 GND GND 115
6 GND
GND 137
75 GND
GND 122
38 GND
GND 107
41 GND GND 106
58 GND GND 135
74 GND GND 128
59 GND GND 104
52 GND GND 113
39 GND
73 GND 19
GND
34 GND 32
GND
64 GND 49
A 81
GND
GND A
PAGE TITLE
35

142
GND
CELLULAR RF TRANSCEIVER: (1 OF 2)
GND GND 9 DRAWING NUMBER SIZE

Apple Inc. 051-9584 D


REVISION
R
2.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
7 OF 23
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 30 OF 46
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

RF TRANSCEIVER (2 OF 2)
RF1_1V3 RF1_1V3 RF2_2V05
R53_RF STAR ROUTING STAR ROUTING STAR ROUTING STAR ROUTING R19_RF STAR ROUTING
PP_SMPS2_RF1_1V3 1
0 2 8 PP_SMPS2_RF1_1V3_FILT PP_RF1_1V3_PRX_PLL PP_SMPS2_RF1_1V3_FILT PP_RF1_1V3_GPS_LNA 8 PP_SMPS4_RF2_2V05 1
0 2 PP_SMPS4_RF2_2V05_FILT PP_RF2_2V05_DRX_BB 8
5 3 ALIAS 8 8 ALIAS 3 ALIAS
5% 5%
1/20W 1 1 C73_RF 1 C85_RF 1/20W
MF C72_RF MF 1

D
201 10UF
20%
2 6.3V
0.1UF
20%
6.3V
2 X5R-CERM
0.1UF
20%
6.3V
2 X5R-CERM
ALIAS
PP_RF1_1V3_GPS_DIG 8 201 C88_RF
10UF
20%
ALIAS
PP_RF2_2V05_TX_DA 8
D
CERM 6.3V
0402 01005 01005 2 CERM 1 C244_RF
PLACE NEAR U3.66 PLACE NEAR U3.24 AND U3.31 0402
100PF
STAR ROUTING 5%
16V
2 NP0-C0G
PP_RF1_1V3_SHDR_PLL 8 PP_RF1_1V3_GPS_VCO 8 01005
ALIAS ALIAS PLACE NEAR U3.111
1 C86_RF
1 C74_RF PP_RF1_1V3_GPS_PLL STAR ROUTING
0.1UF ALIAS
8
PP_RF2_2V05_PRX_BB
0.1UF 20% ALIAS 8
20% 6.3V
2 X5R-CERM
2 6.3V
X5R-CERM 01005
01005 PLACE NEAR U3.37 AND U3.55 PP_RF2_2V05_TX_BB
PLACE NEAR U3.65 ALIAS 8

PP_RF1_1V3_PRX_VCO

RF1_1V8
ALIAS 8 STAR ROUTING
PP_RF2_2V05_PRX_VCO 8
ALIAS
1 C75_RF
0.1UF 1 C89_RF
20% 6 5 3 2 PP_SMPS3_MSME_1V8 PP_RF1_1V8_DIG
6.3V
2 X5R-CERM ALIAS 8 0.1UF
20%
01005 2 6.3V
PLACE NEAR U3.76 1 C87_RF X5R-CERM
01005
1.0UF PLACE NEAR U3.67
20%
6.3V
PP_RF1_1V3_SHDR_VCO 8
2 X5R PP_RF2_2V05_SHDR_VCO 8
ALIAS
0201-1 ALIAS
PLACE NEAR U3.87
1 C76_RF
0.1UF 1 C90_RF
20% 0.1UF
2 6.3V
X5R-CERM 20%
01005 6.3V
2 X5R-CERM
PLACE NEAR U3.40 01005
PLACE NEAR U3.51

C ALIAS
PP_RF1_1V3_TX_DA 8
PP_RF2_2V05_TX_VCO
C
ALIAS 8
1 C77_RF
0.1UF
20% 1 C91_RF
6.3V
2 X5R-CERM 0.1UF
01005 20%
PLACE NEAR U3.118 6.3V
2 X5R-CERM
NOSTUFF
01005
STAR ROUTING PLACE NEAR U3.136
PP_RF1_1V3_TX_SYNTH 8
ALIAS
PP_RF2_2V05_TX_PLL 8
ALIAS
1 C78_RF
0.1UF
20%
2 6.3V PP_RF2_2V05_XO_FILT 8
X5R-CERM ALIAS
01005
PLACE NEAR U3.98 1 C92_RF
0.1UF
PP_RF1_1V3_TX_LO 20%
ALIAS 8 6.3V
2 X5R-CERM
01005
1 PLACE NEAR U3.127
C79_RF
0.1UF
20%
6.3V
2 X5R-CERM
01005
PLACE NEAR U3.116

PP_RF1_1V3_TX_UPCONVERTER 8
TRANSCEIVER POWER CONNECTIONS
ALIAS

1 C80_RF U3_RF
100PF WTR1605
B 5%
16V
2 NP0-C0G SM
SRM 4 OF 5
B
01005
PLACE NEAR U3.117 PWR
8 PP_RF1_1V3_PRX_FELO1 53 VDD_RF1_P_FELO VDD_RF2_T_DA 111 PP_RF2_2V05_TX_DA 8
STAR ROUTING PP_RF1_1V3_PRX_FELO2 42 118 PP_RF1_1V3_TX_DA
STAR ROUTING 8 VDD_RF1_P_FELO VDD_RF1_T_DA 8
PP_RF1_1V3_PRX_FELO1 8
28 117
ALIAS 8
PP_RF1_1V3_DRX_LBLO VDD_RF1_D_LBLO VDD_RF1_T_UPC PP_RF1_1V3_TX_UPCONVERTER 8

1 PP_RF1_1V3_DRX_FE 26 VDD_RF1_D_FE VDD_RF1_T_LO 116 PP_RF1_1V3_TX_LO


C81_RF 8 8

0.1UF 8
PP_RF1_1V3_DRX_MBLO 25 VDD_RF1_D_MBLO VDD_RF2_T_BB 108 PP_RF2_2V05_TX_BB 8
20% PP_RF1_1V3_DRX_FE 8
PP_RF1_1V3_JAM_DET 85
2 6.3V
ALIAS 8 VDD_RF1_JDET 136 PP_RF2_2V05_TX_VCO
X5R-CERM
PP_RF2_2V05_PRX_BB 83 VDD_RF2_T_VCO 8
01005 8 VDD_RF2_P_BB 127 PP_RF2_2V05_XO_FILT
PLACE NEAR U3.53 AND U3.26 44 VDD_RF2_XO 8
8 PP_RF2_2V05_DRX_BB VDD_RF2_D_BB 98
VDD_RF1_T_SYN PP_RF1_1V3_TX_SYNTH 8

8
PP_RF2_2V05_PRX_VCO 67 VDD_RF2_P_VCO VDD_RF2_T_PLL 97 PP_RF2_2V05_TX_PLL 8
PP_RF1_1V3_PRX_FELO2 8
ALIAS 8
PP_RF1_1V3_PRX_VCO 76 VDD_RF1_P_VCO
VDD_RF1_G_LNA 24 PP_RF1_1V3_GPS_LNA
1 PP_RF1_1V3_PRX_PLL 66 VDD_RF1_P_PLL
8
C82_RF 8
VDD_RF1_G_VCO 37 PP_RF1_1V3_GPS_VCO
0.1UF 8 PP_RF2_2V05_SHDR_VCO 51 VDD_RF2_S_VCO
8

20% VDD_RF1_G_PLL 55 PP_RF1_1V3_GPS_PLL


8 PP_RF1_1V3_SHDR_VCO
40 VDD_RF1_S_VCO
8
2 6.3V
X5R-CERM VDD_RF1_G_BB 31 PP_RF1_1V3_GPS_DIG
01005 8
PP_RF1_1V3_SHDR_PLL 65 VDD_RF1_S_PLL
8

PLACE NEAR U3.42


VDD_DIO 87 PP_RF1_1V8_DIG 8

STAR ROUTING
PP_RF1_1V3_DRX_LBLO 8
ALIAS

1 C83_RF PP_RF1_1V3_DRX_MBLO 8
0.1UF ALIAS
20%
6.3V
2 X5R-CERM
01005

A PLACE NEAR U3.25 AND U3.28


A
PAGE TITLE
ALIAS
PP_RF1_1V3_JAM_DET 8
CELLULAR RF TRANSCEIVER: (2 OF 2)
DRAWING NUMBER SIZE

Apple Inc. 051-9584 D


REVISION
R
2.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
8 OF 23
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 31 OF 46
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

TRANSCEIVER TX AND RX MATCHING


TX MATCHING NETWORKS

D 30
50_XCVR_B1_TX
R46_RF
1
0.00 2 50_B1_TX_SAW_IN 33
D
IN OUT
0%
1/32W
MF
01005

R47_RF
50_XCVR_B3_B4_TX1 0.00 2 50_B3_B4_TX_SAW_IN
30 IN OUT 33

0%
1/32W
MF
01005

R48_RF
50_XCVR_B2_B25_TX1 0.00 2 50_B2_B25_TX_SAW_IN
30 IN OUT 33

0%
1/32W
MF
01005

C C

RX MATCHING NETWORKS
L47_RF
0.6NH+/-0.1NH-0.85A
100_B1_B4_DUPLX_RX_P 100_XCVR_B1_B4_PRX_N
34 IN OUT 30
0201

C185_RF 1
0.6PF
50_B2_DUPLX_RX 1 2 100_XCVR_B2_B25_PRX_N
35 IN OUT 30
L44_RF
+/-0.1PF 3.1NH+/-0.1NH-0.45A-025OHM
1 16V 0201
NP0-C0G 1
01005
L48_RF
L36_RF L38_RF
2 0.6NH+/-0.1NH-0.85A
8.2NH-5%-0.34A-0.27OHM 6.7NH-5%-0.46A-0.15OHM 100_B1_B4_DUPLX_RX_N 1 2 100_XCVR_B1_B4_PRX_P
0201DS 0201DS
34 IN OUT 30
0201

2 C186_RF
27PF 2
L49_RF
50_B2_RX_BALUN 1 2 100_XCVR_B2_B25_PRX_P
OUT 30 10NH-3%-250MA
B 5%
16V
NP0-C0G
37 IN
100_B5_B18_DUPLX_RX_N
0201
100_XCVR_B5_B18_PRX_N
OUT 30
B
01005 1
1 C183_RF
1.1PF
+/-0.1PF
2 16V
NP0-C0G
L45_RF
01005 22NH-150MA
0201
C187_RF
0.7PF L50_RF
35 IN
50_B3_DUPLX_RX 1 2 100_XCVR_B3_PRX_N
OUT 30
2 10NH-3%-250MA
+/-0.1PF 37
100_B5_B18_DUPLX_RX_P 1 2 100_XCVR_B5_B18_PRX_P 30
IN OUT
1 16V 1 0201
NP0-C0G
01005

L37_RF L39_RF L51_RF


5.1NH-3%-0.35A 5.1NH-3%-0.35A 10NH-3%-250MA
0201 0201 100_B8_DUPLX_RX_P 100_XCVR_B8_PRX_P
37 IN OUT 30
0201
2 C188_RF 2 1
27PF
50_B3_RX_BALUN 1 2 100_XCVR_B3_PRX_P 30
OUT
L46_RF
5% 18NH+/-3%-0.2A-0.8OHM
16V
NP0-C0G 0201
01005
1 C184_RF L52_RF
1.2PF 2 10NH-3%-250MA
+/-0.1PF
16V
2 NP0-C0G 100_B8_DUPLX_RX_N 1 2 100_XCVR_B8_PRX_N
37 IN OUT 30
01005
0201

A A
PAGE TITLE

CELLULAR FRONT END: TX AND RX MATCHING


DRAWING NUMBER SIZE

Apple Inc. 051-9584 D


REVISION
R
2.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
9 OF 23
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 32 OF 46
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

SAW BANKS

D D

HB TX SAW BANK +
B13/B17/B20 DP6T SWITCH AND MATCHING
41 40 29
2G_FEM_S6
IN
41 40 29
2G_FEM_S3
IN
40 29
2G_FEM_S2
IN
43 41 40 26 2523 IN
PP_LDO14_2V65
LB TX SAW BANK
FL2_RF
LMTPFJGA-E50
LGA
6

7
8
9

1 B5/18/BC10_TX_IN 50_B5_TX_SAW_OUT
VDD V1 V2 V3 30 IN 50_XCVR_B5_B18_TX B5/18/BC10_TX_OUT 11 OUT 37

U9_RF 30 50_XCVR_B8_TX 2 B8_TX_IN B8_TX_OUT 10 50_B8_TX_SAW_OUT 37

C
IN OUT
C HFQSMXXFA
LGA
30 IN 50_XCVR_B13_B17_B20_TX 3 B13/17/20_TX_IN B13_TX_OUT 9 50_B13_TX_SAW_OUT OUT 38
3 B1TXIN 50_B1_TX_SAW_OUT
50_B1_TX_SAW_IN BAND1TXOUT 14
B17_TX_OUT 8 50_B17_TX_SAW_OUT
32 IN OUT 34
OUT 38
50_B2_TX_SAW_OUT
B25TXOUT 11
5 B25_TXIN B20_TX_OUT 7 50_B20_TX_SAW_OUT
OUT 35
32 IN 50_B2_B25_TX_SAW_IN GND OUT 36
50_B3_TX_SAW_OUT
4 B3TXOUT 12 OUT 35
32 IN 50_B3_B4_TX_SAW_IN B3/4_TXIN

4
5
6
12
13
BAND4TXOUT 13
50_B4_TX_SAW_OUT 34
OUT

38 100_B13_DUPLX_RX_N 15 B13_RXIN
IN
38 100_B13_DUPLX_RX_P 16 B13_RXIN B13_17_20_RXOUT0 1 100_XCVR_B13_B17_B20_PRX_N OUT 30
IN
17 B13_17_20_RXOUT1 2 100_XCVR_B13_B17_B20_PRX_P OUT 30
38 IN 100_B17_DUPLX_RX_P B17_RXIN
38 100_B17_DUPLX_RX_N 18 B17_RXIN
IN

36 100_B20_DUPLX_RX_P 19 B20_RXIN
IN
36 100_B20_DUPLX_RX_N 20 B20_RXIN
IN

GND THRM
PAD

DCS/PCS 2-IN-1 RX FILTER


10

21
22
23

L54_RF
1.1NH+/-0.1NH
L64_RF 1 2 100_XCVR_DCS_PCS_PRX_P
2.5NH+/-0.1NH-500MA FL6_RF OUT 30
0201
40 IN
50_PCS_RX 1 2 50_PCS_RX_MATCH SAWFD1G84BU0F57
FILTER 1

BAND S6 S3 S2 0201

1 UNBAL_PORT_1960MHZ
LGA-1
BAL_PORT_1842.5MHZ/1960MHZ 6
100_DCS_PCS_RX_FILTER_P
L53_RF
L65_RF 4.3NH-3%-0.35A
B B3 TX HIGH X X 2.5NH+/-0.1NH-500MA
50_DCS_RX 1 2 50_DCS_RX_MATCH
4 UNBAL_PORT_1842.5MHZ BAL_PORT_1842.5MHZ/1960MHZ 9
100_DCS_PCS_RX_FILTER_N 0201

L55_RF
B
B4 TX LOW X X
40 IN
0201 GND 2 1.1NH+/-0.1NH
1 C245_RF 1 C246_RF 1 2 100_XCVR_DCS_PCS_PRX_N

2
3
5
7
8
10
OUT 30
1.3PF 1.4PF
B13 RX X HIGH HIGH +/-0.05PF
25V
2 C0G-CERM
0201
+/-0.05PF
25V
2 C0G-CERM
0201
0201

B17 RX X HIGH LOW


B20 RX X LOW HIGH

A A
PAGE TITLE

CELLULAR FRONT END: SAW BANKS


DRAWING NUMBER SIZE

Apple Inc. 051-9584 D


REVISION
R
2.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
10 OF 23
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 33 OF 46
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

BAND 1/4 PAT


D D

PA_ON_B1_B4 29
IN
PA_BS 2935 37 38
IN
PA_R1 2935 36 37 38
PP_PA IN
40 39 38 37 36 35 IN
PP_BATT_VCC_CONN
40 39 38 37 36 35 26 2523 IN 1 C236_RF
1 C237_RF
1 C238_RF
1 C164_RF 1 C208_RF
1 C165_RF 1 C209_RF 56PF 56PF 56PF
5% 5% 5%
0.1UF 1000PF 1.0UF 27PF 16V
2 NP0-C0G
16V
2 NP0-C0G
16V
2 NP0-C0G
20% 10% 20% 5%

C 2 6.3V
X5R-CERM
01005
2 6.3V
X5R-CERM
01005
2 6.3V
X5R
0201-1
2 25V
NP0-C0G
201
01005 01005 01005
C
NOSTUFF

C191_RF

VBATT 29

VEN_B1_B4 24
VCC 22

BS 25

VMODE 30
56PF
33 50_B1_TX_SAW_OUT 1 2
IN
5%
1 16V
C162_RF NP0-C0G 1 C258_RF
1.2PF 01005 1.2PF U14_RF
L70_RF
+/-0.1PF +/-0.1PF 1.2NH+/-0.1NH-0.75A
16V
2 NP0-C0G
16V
2 NP0-C0G 50_B1_TX_PAD_IN 28 RFIN_B1 TRIPLEXER-BAND1-4 CPL_IN 4
50_B1_B4_DPLX_ANT 1 2 50_B1_B4_ANT 40
01005 01005 50_B4_TX_PAD_IN 26 RFIN_B4 LGA BI
NOSTUFF NOSTUFF CPL_OUT 20 0201
9 RX_P_B1_B4
C192_RF 8 RX_N_B1_B4
56PF
ANT_B1_B4 16
33 IN 50_B4_TX_SAW_OUT 1 2 1 C249_RF 1 C167_RF
0.5PF 27PF
5% +/-0.05PF 5%
1 C163_RF 16V GND THRM_PAD 25V
2 COG-CERM 25V
NP0-C0G 2 NP0-C0G
1.2PF 01005 0201 201
+/-0.1PF

1
2
3
5
6
7
10
11
12
13
14
15
17
18
19
21
23
27

31
32
33
34
35
36
37
38
39
40
41
42
NOSTUFF
2 16V
NP0-C0G
01005
NOSTUFF

100_B1_B4_DUPLX_RX_N 32
OUT
100_B1_B4_DUPLX_RX_P 32
OUT

B B

BAND PA POWER MODE PA_BS PA_ON_B1_B4 PA_R1


============================================================
POWER DOWN X 0 0 0
A STANDBY X X 0 X PAGE TITLE
A
CELLULAR FRONT END: BAND 1/4 PAT
B4 HPM 0 1 0 DRAWING NUMBER
051-9584
SIZE
D
B4 LPM 0 1 1 R
Apple Inc. REVISION
2.0.0
B1 HPM 1 1 0 NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
BRANCH

B1 LPM 1 1 1
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
11 OF 23
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST IV ALL RIGHTS RESERVED 34 OF 46
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

BAND 2/3 PAD


D D

40 39 38 37 36 34
PP_PA
IN PA_ON_B2_B3
IN 29
40 39 38 37 36 34 26 2523
PP_BATT_VCC_CONN
IN
PA_BS
1 C148_RF 1 C210_RFC149_RF
1 1 C211_RF IN 2934 37 38

0.1UF 1000PF 1.0UF 27PF PA_R1


IN 2934 36 37 38
20% 10% 20% 5%
6.3V 6.3V 6.3V 25V

C
2 X5R-CERM
01005
2 X5R-CERM
01005
2 X5R
0201-1
2 NP0-C0G
201
NOSTUFF C

C193_RF

BS 29
VBATT 25

VEN_B2_B3 30

VMODE 24
VCC 2
56PF
33 50_B3_TX_SAW_OUT 1 2
IN
5%
1 C146_RF 16V
1.2PF
NP0-C0G
01005
L71_RF
+/-0.1PF U23_RF 2.4NH+/-0.1NH-0.50A
16V
2 NP0-C0G 50_B3_TX_PAD_IN 26 RFIN_B3 CPL_IN 4
DUPLEXER-BAND2-3 NC 50_B3_DPLX_ANT 1 2 50_B3_ANT BI 40
01005 50_B2_TX_PAD_IN 28 RFIN_B2 CPL_OUT 20
NOSTUFF LGA NC 0201
13 RX_B3
C194_RF
56PF 14 GND
ANT_B3 16
1 C250_RF
50_B2_TX_SAW_OUT 1 2 1.1PF 1
33 IN 11 RX_B2 ANT_B2 8 +/-0.1PF C152_RF
2 25V
CERM 27PF
5% 10 GND 5%
1 C147_RF 16V 1 C259_RF GND THRM_PAD 0201 25V
NP0-C0G 2 NP0-C0G
1.2PF 01005 1.2PF 0201
+/-0.1PF +/-0.1PF

1
3
5
6
7
9
12
15
17
18
19
21
22
23
27

31
32
33
34
35
36
37
38
39
40
41
42
NOSTUFF
2 16V
NP0-C0G 2 16V
NP0-C0G
01005 01005
NOSTUFF NOSTUFF

L72_RF
1.3NH+/-0.1NH-600MA
50_B2_DPLX_ANT 1 2 50_B2_ANT 40
BI
50_B2_DUPLX_RX 32 0201
OUT
50_B3_DUPLX_RX 32
OUT
B 1 C251_RF
0.9PF
B
+/-0.05PF
25V
1 C153_RF
2 C0G-CERM 27PF
0201 5%
2 25V
NP0-C0G
201
NOSTUFF

BAND PA POWER MODE PA_BS PA_ON_B2_B3 PA_R1


============================================================
POWER DOWN X 0 0 0
A STANDBY X X 0 X A
B3 HPM 0 1 0
PAGE TITLE
CELLULAR FRONT END: BAND 2/3 PAD
DRAWING NUMBER SIZE

B3 LPM 0 1 1 Apple Inc. 051-9584


REVISION
D

B2 HPM 1 1 0 2.0.0
R

NOTICE OF PROPRIETARY PROPERTY: BRANCH

B2 LPM 1 1 1
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
12 OF 23
SHEET
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 35 OF 46
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

BAND 20 PAD
D D

PP_PA BULK BYPASSING SHARED WITH B1/4 PAT


40 39 38 37 35 34
PP_PA PA_ON_B20 29
IN IN
40 39 38 37 35 34 26 25 23
PP_BATT_VCC_CONN
IN

1 C156_RF 1 C233_RF 1 C234_RF PA_R1


IN 2934 35 37 38
0.1UF 1000PF 27PF
20% 10% 5%
6.3V
2 X5R-CERM
6.3V
2 X5R-CERM
25V
2 NP0-C0G 1 C239_RF
1 C240_RF

C 01005 01005 201


NOSTUFF 5%
56PF
16V
2 NP0-C0G
5%
56PF
16V
2 NP0-C0G
C
01005 01005

C195_RF

VBATT 25

VEN_B20_B7 30
BS 29

VMODE 24
VCC 2
56PF
33 50_B20_TX_SAW_OUT 1 2
IN
5%
1 C154_RF
1.2PF
16V
NP0-C0G
1 C84_RF
1.2PF
L73_RF
+/-0.1PF
01005
+/-0.1PF
6.2NH-0.30A
16V
2 NP0-C0G
16V
2 NP0-C0G 50_B20_TX_PAD_IN 26 RFIN_B20 U207_RF CPL_IN 4 NC 50_B20_DPLX_ANT 1 2 50_B20_ANT BI 40
01005
NOSTUFF
01005
NOSTUFF
28 RFIN_B7 DUPLEXER-BAND7-20 CPL_OUT 20 NC 0201

12 RX_P_B20 LGA
13 RX_N_B20
1 C39_RF
2.4PF
ANT_B20 16 +/-0.1PF 1
11 RX_B7
25V C160_RF
ANT_B7 8 2 NP0-C0G
3.6PF
201
10 GND +/-0.05PF
GND THRM_PAD 25V
2 C0G-CERM
0201

1
3
5
6
7
9
14
15
17
18
19
21
22
23
27

31
32
33
34
35
36
37
38
39
40
41
42
NOSTUFF

100_B20_DUPLX_RX_P
B 100_B20_DUPLX_RX_N
OUT 33

33
B
OUT

BAND PA POWER MODE PA_ON_B20 PA_R1


=====================================================
A POWER DOWN LPM 0 0 A
STANDBY X 0 X PAGE TITLE

CELLULAR FRONT END: BAND 20 PAD


B20 HPM 1 0 Apple Inc.
DRAWING NUMBER
051-9584
SIZE
D

B20 LPM 1 1
REVISION
R
2.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
13 OF 23
SHEET
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 36 OF 46
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

BAND 5/8 PAD


D D

40 39 38 36 35 34
PP_PA PA_ON_B5_B8 29
IN IN
40 39 38 36 35 34 26 2523
PP_BATT_VCC_CONN
IN PA_BS
IN 2934 35 38
1 C118_RF 1 C212_RF
1 C119_RF 1 C213_RF PA_R1
0.1UF 1000PF 1.0UF 27PF IN 2934 35 36 38
20% 10% 20% 5%
6.3V
2 X5R-CERM
6.3V
2 X5R-CERM
6.3V
2 X5R
25V
2 NP0-C0G 1 C214_RF
1 C215_RF
1 C216_RF

C 01005 01005 0201-1 201


NOSTUFF 5%
16V
56PF
2 NP0-C0G
56PF
5%
16V
2 NP0-C0G
56PF
5%
16V
2 NP0-C0G
C
01005 01005 01005

L7_RF

VBATT 29

VEN_B5_B8 24
BS 25

VMODE 30
2.7NH+/-0.1NH-200MA

VCC 2
33 50_B5_TX_SAW_OUT 1 2
IN
01005
1 C116_RF
1.2PF
1 C256_RF
0.7PF
L74_RF
+/-0.1PF +/-0.1PF U58_RF 6.2NH-0.30A
16V 16V 50_B5_TX_PAD_IN 26 RFIN_B5 CPL_IN 4
2 NP0-C0G
01005
2 NP0-C0G
01005 50_B8_TX_PAD_IN
DUPLEXER-BAND5-8 NC 50_B5_DPLX_ANT 1 2 50_B5_ANT BI 40
28 RFIN_B8 CPL_OUT 20
NOSTUFF LGA NC 0201

L10_RF 13 RX_P_B5
2.2NH+/-0.1NH-200MA 14 RX_N_B5
ANT_B5 16
1 C252_RF
33 IN 50_B8_TX_SAW_OUT 1 2
11 RX_P_B8 ANT_B8 8
4.8PF
+/-0.05PF
1 C122_RF
01005 25V 27PF
10 RX_N_B8 2 C0G-CERM 5%
1 C117_RF 1 C257_RF GND THRM_PAD 0201 25V
2 NP0-C0G
1.2PF 0.7PF 201
+/-0.1PF +/-0.1PF NOSTUFF

1
3
5
6
7
9
12
15
17
18
19
21
22
23
27

31
32
33
34
35
36
37
38
39
40
41
42
2 16V
NP0-C0G 2 16V
NP0-C0G
01005 01005
NOSTUFF

L75_RF
4.3NH-3%-0.35A
50_B8_DPLX_ANT 1 2 50_B8_ANT 40
BI
100_B8_DUPLX_RX_N 32 0201
OUT
100_B8_DUPLX_RX_P
B 100_B5_B18_DUPLX_RX_N
OUT

OUT
32

32
1 C253_RF
1.9PF 1
B
+/-0.05PF C123_RF
25V
100_B5_B18_DUPLX_RX_P
OUT 32
2 C0G-CERM 27PF
0201 5%
2 25V
NP0-C0G
0201
NOSTUFF

BAND PA POWER MODE PA_BS PA_ON_B5_B8 PA_R1


============================================================
POWER DOWN X 0 0 0
A STANDBY X X 0 X A
B5 HPM 0 1 0 PAGE TITLE

CELLULAR FRONT END: BAND 5/8 PAD


B5 LPM 0 1 1
DRAWING NUMBER SIZE

Apple Inc. 051-9584 D


REVISION

B8 HPM 1 1 0 R

NOTICE OF PROPRIETARY PROPERTY: BRANCH


2.0.0

B8 LPM 1 1 1 THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
PAGE
14 OF 23
SHEET
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 37 OF 46
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

BAND 13/17 PAD


D D

40 39 37 36 35 34
PP_PA PA_ON_B13_B17 29
IN IN
40 39 37 36 35 34 26 2523
PP_BATT_VCC_CONN
IN PA_BS 2934 35 37
IN
1 C110_RF 1 C217_RF 1 C111_RF 1 C235_RF PA_R1
0.1UF 1000PF 1.0UF 27PF IN 2934 35 36 37

C
20%
6.3V
2 X5R-CERM
01005
10%
6.3V
2 X5R-CERM
01005
20%
6.3V
2 X5R
0201-1
5%
25V
2 NP0-C0G
201
C
NOSTUFF

VBATT 25

VEN_B13_B17 30
BS 29
VCC 22
C198_RF

VMODE 24
56PF
33 50_B13_TX_SAW_OUT 1 2
IN
5%
16V 1 C108_RF
NP0-C0G FL3_RF
01005 1.2PF L76_RF
+/-0.1PF
16V 50_B13_TX_PAD_IN 26 RFIN_B13 18PF BAND13-50OHM
LFL0Q766MTM1D497
2 NP0-C0G U1317_RF CPL_IN 4 2 INPUT 50_B13_ANT
01005 50_B17_TX_PAD_IN 28 RFIN_B17 50_B13_DPLX_ANT 1 2 50_B13_LPF_IN OUTPUT 1 BI 40
CPL_OUT 20
NOSTUFF DUPLEXER-BAND13-17 2% GND
13 RX_P_B13 LGA 1 C113_RF 25V
C199_RF C0H-CERM
56PF 14 RX_N_B13 2.2PF 0201

3
4
1 2 ANT_B13 16 +/-0.05PF
25V
50_B17_TX_SAW_OUT 2 C0G-CERM 1
33 IN 11 RX_P_B17 ANT_B17 8 C114_RF
0201 27PF
5% 10 RX_N_B17 NOSTUFF 5%
16V 1 C109_RF GND THRM_PAD
NP0-C0G 2 25V
NP0-C0G
01005 1.2PF 0201
+/-0.1PF

1
2
3
5
6
7
9
12
15
17
18
19
21
23
27

31
32
33
34
35
36
37
38
39
40
41
42
NOSTUFF
2 16V
NP0-C0G
01005
NOSTUFF

L77_RF
6.8NH-3%-140MA
50_B17_DPLX_ANT 1 2 50_B17_ANT 40
100_B17_DUPLX_RX_N BI
OUT 33
01005
100_B17_DUPLX_RX_P 1 C254_RF
B 100_B13_DUPLX_RX_N
OUT

OUT
33

33
2.2PF
+/-0.1PF
16V
2 NP0-C0G
B
1 C115_RF
01005-1
100_B13_DUPLX_RX_P 33 56PF
OUT
5%
2 16V
NP0-C0G
01005
NOSTUFF

BAND PA POWER MODE PA_BS PA_ON_B13_B17 PA_R1


============================================================
POWER DOWN X 0 0 0
A STANDBY X X 0 X PAGE TITLE
A
B17 HPM 0 1 0 CELLULAR FRONT END: BAND 13/17 PAD
DRAWING NUMBER SIZE

B17 LPM 0 1 1 R
Apple Inc. 051-9584
REVISION
2.0.0
D

B13 HPM 1 1 0 NOTICE OF PROPRIETARY PROPERTY:


THE INFORMATION CONTAINED HEREIN IS THE
BRANCH

B13 LPM 1 1 1 PROPRIETARY PROPERTY OF APPLE INC.


THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
PAGE

SHEET
15 OF 23
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST IV ALL RIGHTS RESERVED 38 OF 46
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

PA DC/DC CONVERTER
D D

XW47_RF
SHORT-10L-0.25MM-SM
40 38 37 36 35 34 26 25 23
PP_BATT_VCC_CONN 1 2 PP_BATT_VCC_PA_DCDC
IN

C 1 C189_RF
56PF
1 C1214_RF 1 C1201_RF
0.01UF 10UF 1 C1215_RF
1 C169_RF
0.01UF
C
5% 10% 20% 10%
16V
2 NP0-C0G
6.3V
2 X5R
6.3V
2 CERM 1.0UF 6.3V
2 X5R
20%
01005 01005 0402 6.3V 01005
2 X5R
0201-1

16 DCDC_PGND DCDC_PGND 16

IN1 B2

IN2 C2
PLACE NEAR U1.H3 PLACE NEAR U11.A2

R33_RF R34_RF
1.00K BB_PDM_FILT 1.00K DCDC_ADJ A2 REFIN
BB_PDM 1 2 1 2 OUT C3
29 IN
1% 1%
U11_RF L21_RF
1/32W 1 1/32W DCDC_EN B1 EN MAX77100 2.2UH-20%-1.5A-0.160OHM
MF C144_RF MF 1 C145_RF
29 IN
WLP
01005 6800PF 01005 LX B3 DCDC_OUT 1 2 PP_PA
10% 4700PF 29 IN
DCDC_MODE C1 MODE OUT 34 35 36 37 38 40
10% MAKK2016-SM
2 6.3V
X5R 2 6.3V

A1 AGND

A3 PGND
01005 X5R
01005
1 C41_RF 1 C168_RF
4.7UF 1000PF
20% 10%
XW6_RF 2 6.3V 2 6.3V
SHORT-10L-0.25MM-SM X5R X5R-CERM
16 DCDC_PGND 1 2 402 01005

NOSTUFF
DCDC_PGND 16
XW8_RF
SHORT-10L-0.25MM-SM
1 2 PLACE C41 CLOSE TO L21
NOSTUFF

B B

A A
PAGE TITLE

CELLULAR FRONT END: PA DCDC CONVERTER


DRAWING NUMBER SIZE

Apple Inc. 051-9584 D


REVISION
R
2.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
16 OF 23
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST IV ALL RIGHTS RESERVED 39 OF 46
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

2G FEM
D D

43
26 2523
PP_LDO14_2V65
41 33 IN
39 38
35 34
PP_PA
37 36 IN

FL1_RF
70-OHM-300MA
39
37 36
26 25 23
PP_BATT_VCC_CONN 1 2 PP_BATT_VCC_2G_FEM
35 34
IN
38 01005-1 2G_FEM_S6 2933 41
IN
1 C202_RF 1 C65_RF 1 C66_RF 1 C190_RF 1 C242_RF 1 C67_RF 1 C243_RF1 C203_RF 2G_FEM_S5
IN 2941
56PF 0.1UF 10UF 0.1UF 0.01UF 0.1UF 0.01UF 56PF 2G_FEM_S4
IN 252941
5% 20% 20% 20% 10% 20% 10% 5%
16V
2 NP0-C0G
6.3V
2 X5R-CERM
6.3V
2 CERM
6.3V
2 X5R-CERM
6.3V
2 X5R
6.3V
2 X5R-CERM
6.3V
2 X5R
16V
2 NP0-C0G 2G_FEM_S3 2933 41
IN
01005 01005 0402 01005 01005 01005 01005 01005 2G_FEM_S2 2933
IN

C
2G_FEM_S1
2G_FEM_S0
IN
IN
2529

29
C
R54_RF C200_RF
0.00 2
56PF 1 C226_RF
C227_RF
C228_RF
1 C229_RF
C230_RF
1 C231_RF
C232_RF1 1 1 1

30 IN
50_XCVR_2G_LB_TX1 50_XCVR_2G_LB_TX_MATCH 1 2 56PF 56PF 56PF 56PF 56PF 56PF 56PF
5% 5% 5% 5% 5% 5% 5%
0%
1 5% 2 16V
NP0-C0G 2 16V
NP0-C0G 2 16V
NP0-C0G 2 16V
NP0-C0G 2 16V
NP0-C0G 2 16V
NP0-C0G 2 16V
NP0-C0G
1/32W
MF
C63_RF 16V 01005 01005 01005 01005 01005 01005 01005
01005 1.5PF NP0-C0G
+/-0.1PF 01005
16V
2 NP0-C0G
01005

29

34

27

38
NOSTUFF

6
5
4
3
2
1
FL10_RF
C201_RF FIL-COUPLER+LPF-BROADBAND

VBATT

VCC

VDD_SWITCH

S6
S5
S4
S3
S2
S1
S0
R55_RF 56PF 50_2G_LB_PA_IN 32 LBRF_IN T1 13 50_DRX_ANT
OUT 41
LDJ21832M22HC033
0805-6SM
0.00 2 50_XCVR_2G_HB_TX_MATCH 1 2 50_2G_HB_PA_IN 36 HBRF_IN 19 50_B3_ANT 3 6 50_LAT_TEST
30 IN 50_XCVR_2G_HB_TX1 T2 BI 35 IN MAIN OUT BI 43

0%
1/32W
MF
1 C64_RF
5%
16V 34 BI
50_B1_B4_ANT 25 TRX1 U2000_RF 4 COUPLE OUT TERMINATE 1
01005 1.5PF NP0-C0G 37
50_B8_ANT 24 TRX2 FEM-2G-TX
01005 BI GND 1
+/-0.1PF 50_B5_ANT 23 TRX3 LGA
2 16V
NP0-C0G
37 BI

2
5
01005 22 TRX4
NOSTUFF 50_B2_ANT 21 TRX5 ANT1 15 50_LAT_ASM L56_RF
35 BI
ANT2 17 50_UAT_ASM 30 OUT 50_PDET_PAD_IN 15NH-250MA
33
50_DCS_RX 11 TRX6 50_LAT_COUPLER_IN IN 40 0201
BI
50_PCS_RX 10 TRX7 NOSTUFF
33 BI
36
50_B20_ANT 9 TRX8 2
BI
50_B17_ANT 8 TRX9 FL9_RF
38 BI
50_B13_ANT 7 TRX10 L78_RF FIL-COUPLER+LPF-BROADBAND
38 BI 2.4NH+/-0.1NH-0.50A LDJ21832M22HB042
0805-6SM
GND THRM_PAD 1 2 50_UAT_LPF 1 3 50_UAT_TEST
IN MAIN OUT BI 43
0201
12
14
16
18
20
26
28
30
31
33
35
37

39
40
41
42
43
44
45
46
47
48
49
50
6 4 50_COUPLER_TERM
B 1 C207_RF
0.4PF
COUPLE OUT
GND
TERMINATE 1
B
L57_RF

2
5
+/-0.05PF
25V
2 C0G 15NH-250MA
40 OUT 50_LAT_COUPLER_IN
201 0201
1 NOSTUFF
R35_RF
49.9 2
1%
1/32W
MF
2 01005

A A
PAGE TITLE

CELLULAR FRONT END: 2G FEM


DRAWING NUMBER SIZE

Apple Inc. 051-9584 D


REVISION
R
2.0.0
SEE PGS. 21-22 FOR 2G FEM LOGIC TABLE NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
BRANCH

PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
17 OF 23
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST IV ALL RIGHTS RESERVED 40 OF 46
8 7 6 5 4 3 2 . 1
8 7 6 5 4 3 2 1

RX DIVERSITY
D D

43 40 33 26 2523 PP_LDO14_2V65 100PF BYPASS INCLUDED IN MODULE 2G_FEM_S3 2933 40


IN IN
2G_FEM_S4 252940
IN
2G_FEM_S5 2940
IN
2G_FEM_S6 2933 40
IN

C C

5
6
7
8
VDD

V1
V2
V3
V4
U16_RF
HFQSWXXUA
L79_RF LGA
3.3NH+/-0.2NH-0.45A
40 50_DRX_ANT 1 2 50_DIVERSITY_SWITCH_MATCH 1 ANT GPS/GNSS_OUT_P 12 100_XCVR_GPS_RX_N 30
IN OUT
0201 GPS/GNSS_OUT_N 13 100_XCVR_GPS_RX_P
OUT 30

1 C255_RF 10 BAND1/4_OUT_P 15 100_XCVR_B1_B4_DRX_P


OUT 30
1.0PF 42 IN 50_GPS_LNA_OUT GPS/GNSSIN
+/-0.1PF BAND1/4_OUT_N 16 100_XCVR_B1_B4_DRX_N
OUT 30
25V
2 C0G
201 B5/18/13/17_OUT_P 19 100_XCVR_B5_B18_B13_B17_DRX_P
OUT 30

B5/18/13/17_OUT_N 20 100_XCVR_B5_B18_B13_B17_DRX_N
OUT 30

B8/20_OUT_P 21 100_XCVR_B8_B20_DRX_P
OUT 30

B8/20_OUT_N 22 100_XCVR_B8_B20_DRX_N
OUT 30

B25/3_OUT_P 17 100_XCVR_B2_B25_B3_DRX_P
OUT 30

B25/3_OUT_N 18 100_XCVR_B2_B25_B3_DRX_N
OUT 30

GND THRM
PAD

2
3
9
11
14
23
24
25
26

27
28
B B

BAND S6 S5 S4 S3
B1/B4 LOW LOW LOW LOW
B2/25 LOW HIGH LOW LOW
B3 HIGH LOW LOW LOW
B5/6/18 LOW LOW HIGH LOW
B8 LOW LOW LOW HIGH
B13/17 LOW HIGH HIGH HIGH
A B20 LOW HIGH HIGH LOW A
PAGE TITLE

OFF LOW LOW HIGH HIGH CELLULAR FRONT END: RX DIVERSITY


DRAWING NUMBER SIZE
051-9584 D
SWITCH IS TERMINATED IN ALL OTHER POSSIBLE STATES R
Apple Inc. REVISION
2.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
18 OF 23
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST
IV ALL RIGHTS RESERVED 41 OF 46
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

GPS
D D

C C

PP_LDO5_GPS_LNA_2V5 IN 26

BYPASSING INCLUDED IN MODULE

J12_RF
GPS FEED L62_RF MM8830-2600B

7
9.1NH-5%-250MA F-RT-SM VDD
1 2
0201
U20_RF
SKY65716-11
20 50_UPPER_ANT_FEED 50_GPS_ANT_CONN 2 1 50_GPS_ANT_FEED 5 RFIN LGA RFOUT 9 50_GPS_LNA_OUT 41
R C OUT
C221_RF
3.9PF
NOTE: ADD SP2 BACK FOR EVT 1 1 2 GND
GND
THRM_PAD

3
+/-0.05PF
25V
L11_RF

1
2
3
4
6
8
10
11
12

13
C0G-CERM
10NH-3%-250MA 0201
0201
NOSTUFF
2

B B

A A
PAGE TITLE

CELLULAR FRONT END: GPS LNA


DRAWING NUMBER SIZE

Apple Inc. 051-9584 D


REVISION
R
2.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
19 OF 23
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 42 OF 46
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

ANTENNA FEEDS
D D

UAT1 FEEDSP1_RF FL1701_RF


L1732_RF
1.6X1.21MM FLTR-GPS-0603 4.7NH+/-0.2NH-0.44A
LFE18832MHC1D449 R1_RF
SM-NSP
1 19 50_UPPER_ANT_FEED 1 3
50_NTCH_FILT_OUT
1
0.00 2 50_UPPER_MCH_2 1 2 50_UPPER_MCH_1
L69_RF
IN OUT 5.6NH-3%-140MA
NC 1% 03015
PP_LDO14_PAC_2V65 PP_LDO14_2V65
1/20W
MF
1 C1726_RF 1 2
IN 232526 33 40 41
0.8PF

2
0201 01005
+/-0.1PF
NC 25V
2 NP0-C0G
201-HF 1 C247_RF1 C99_RF
56PF 0.01UF

VDD 9
5% 10%
16V 6.3V
2 NP0-C0G 2 X5R

PAC_TO_BB_SPI_DATA_MISO 1
L6_RF
5.6NH-3%-140MA
2 PAC_TO_BB_SPI_DATA_MISO_FILT
U7_RF
RF1112
01005 01005

UAT1 COAX
29 2523 IN
WLCSP
TP1_RF
1
J6_RF J5_RF
01005 A
8 MISO TP-P6 MM5829-2700 MM5829-2700
L66_RF F-ST-SM F-ST-SM
5.6NH-3%-140MA 3 RF1 RF2 10
50_UAT_COAX_DOWN
1 1 50_UAT_TEST 40
BI
BB_SPI_TO_PAC_CS 1 2 BB_SPI_TO_PAC_CS_FILT 7 CS
29 2523 IN 1
01005 NC 1

4
3
2

2
3
4
5 MOSI 12
L67_RF NC 13
NC
5.6NH-3%-140MA 6 SCLK NC L8_RF
C 29 2523 IN
BB_SPI_TO_PAC_DATA_MOSI 1
01005
2 BB_SPI_TO_PAC_DATA_MOSI_FILT
GND
14
NC 6.8NH-+/-0.2NH-440MA
03015 C
L68_RF

2
4
11
5.6NH-3%-140MA 2
BB_SPI_TO_PAC_CLK 1 2 BB_SPI_TO_PAC_CLK_FILT
29 2523 IN
01005
1 C96_RF 1 C97_RF 1 C98_RF 1 C38_RF
56PF 56PF 56PF 56PF
5% 5% 5% 5%
16V 16V 16V 16V
2 NP0-C0G 2 NP0-C0G 2 NP0-C0G 2 NP0-C0G
01005 01005 01005 01005

B LAT J9_RF
MM8930-2600B
F-RT-SM
B
J4_RF
MM5829-2700
F-ST-SM R11_RF
0 2 1
1 50_LAT_COAX 1 2 50_LAT_MATCH 50_LAT_TEST BI 40
R C
5%
1/20W
MF
2
3
4

1 C94_RF 201 1 GND


C95_RF
1.0PF 1.0PF
+/-0.1PF
6
5
4
3

+/-0.1PF
2 25V
NP0-C0G 25V
2 NP0-C0G
201 201
NOSTUFF NOSTUFF

A A
PAGE TITLE

CELLULAR FRONT END: ANTENNA FEEDS


DRAWING NUMBER SIZE

Apple Inc. 051-9584 D


REVISION
R
2.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
20 OF 23
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST
IV ALL RIGHTS RESERVED 43 OF 46
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

FRONT
BAND
END LOGIC
S6 S5
TABLE
S4
(1 S2OF S1
S3
2) S0 TX/PRX PATH DRX PATH
LB TX, IDLE, LAT HIGH HIGH HIGH LOW LOW HIGH HIGH LAT UAT
LB TX, IDLE, UAT HIGH HIGH HIGH LOW LOW LOW HIGH UAT LAT
D LB TX, LAT, HPM HIGH HIGH HIGH LOW HIGH HIGH HIGH LAT UAT D
LB TX, UAT, HPM HIGH HIGH HIGH LOW HIGH LOW HIGH UAT LAT
LB TX, LAT, LPM HIGH HIGH HIGH LOW HIGH HIGH LOW LAT UAT
LB TX, UAT, LPM HIGH HIGH HIGH LOW HIGH LOW LOW UAT LAT
LB TX, HIGH Z, LAT, HPM HIGH HIGH LOW LOW HIGH HIGH HIGH LAT UAT
LB TX, HIGH Z, UAT, HPM HIGH HIGH LOW LOW HIGH LOW HIGH UAT LAT
LB TX, HIGH Z, LAT, LPM HIGH HIGH LOW LOW HIGH HIGH LOW LAT UAT
LB TX, HIGH Z, UAT, LPM HIGH HIGH LOW LOW HIGH LOW LOW UAT LAT
HB TX, IDLE, LAT HIGH HIGH HIGH HIGH LOW HIGH HIGH LAT UAT
HB TX, IDLE, UAT HIGH HIGH HIGH HIGH LOW LOW HIGH UAT LAT
C
HB TX, LAT, HPM HIGH HIGH HIGH HIGH HIGH HIGH HIGH LAT UAT C
HB TX, UAT, HPM HIGH HIGH HIGH HIGH HIGH LOW HIGH UAT LAT
HB TX, LAT, LPM HIGH HIGH HIGH HIGH HIGH HIGH LOW LAT UAT
HB TX, UAT, LPM HIGH HIGH HIGH HIGH HIGH LOW LOW UAT LAT
HB TX, HIGH Z, LAT, HPM HIGH HIGH LOW HIGH HIGH HIGH HIGH LAT UAT
HB TX, HIGH Z, UAT, HPM HIGH HIGH LOW HIGH HIGH LOW HIGH UAT LAT
HB TX, HIGH Z, LAT, LPM HIGH HIGH LOW HIGH HIGH HIGH LOW LAT UAT
HB TX, HIGH Z, UAT, LPM HIGH HIGH LOW HIGH HIGH LOW LOW UAT LAT
GSM850 RX, LAT HIGH LOW HIGH HIGH LOW HIGH HIGH LAT UAT
GSM850 RX, UAT HIGH LOW HIGH HIGH LOW LOW HIGH UAT LAT
GSM900 RX, LAT HIGH LOW HIGH HIGH HIGH HIGH HIGH LAT UAT
B GSM900 RX, UAT HIGH LOW HIGH HIGH HIGH LOW HIGH UAT LAT B
GSM1900 RX, LAT LOW HIGH LOW HIGH HIGH HIGH HIGH LAT UAT
GSM1900 RX, UAT LOW HIGH LOW HIGH HIGH LOW HIGH UAT LAT
GSM1800 RX, LAT HIGH LOW LOW HIGH HIGH HIGH HIGH LAT UAT
GSM1800 RX, UAT HIGH LOW LOW HIGH HIGH LOW HIGH UAT LAT
TERMINATED, UAT HIGH LOW HIGH LOW HIGH HIGH HIGH UAT LAT
TERMINATED, LAT HIGH LOW HIGH LOW HIGH LOW HIGH LAT UAT
LAT = LOWER ANTENNA
UAT = UPPER ANTENNA

A A
PAGE TITLE

FRONT END LOGIC TABLE (1 OF 2)


DRAWING NUMBER SIZE

Apple Inc. 051-9584 D


REVISION
R
2.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
21 OF 23
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 44 OF 46
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

FRONT
BAND
END LOGIC
S6 S5
TABLE
S4
- DEV2
S3 S2 S1
(2 S0OF TX/PRX
2)PATH DRX PATH
B1/BC6, LAT LOW LOW LOW LOW HIGH HIGH HIGH LAT UAT
B1/BC6, UAT LOW LOW LOW LOW HIGH LOW HIGH UAT LAT
D D
B2/B25/BC1, LAT LOW HIGH LOW LOW HIGH HIGH HIGH LAT UAT
B2/B25/BC1, UAT LOW HIGH LOW LOW HIGH LOW HIGH UAT LAT
B3, LAT HIGH LOW LOW LOW HIGH HIGH HIGH LAT UAT
B3, UAT HIGH LOW LOW LOW HIGH LOW HIGH UAT LAT
B4/BC15, LAT LOW LOW LOW LOW HIGH HIGH HIGH LAT UAT
B4/BC15, UAT LOW LOW LOW LOW HIGH LOW HIGH UAT LAT
B5/B6/B18/BC0/BC10, LAT LOW LOW HIGH LOW HIGH HIGH HIGH LAT UAT
B5/B6/B18/BC0/BC10, UAT LOW LOW HIGH LOW HIGH LOW HIGH UAT LAT
B8, LAT LOW LOW LOW HIGH HIGH HIGH HIGH LAT UAT
B8, UAT LOW LOW LOW HIGH HIGH LOW HIGH UAT LAT
C B13, LAT LOW HIGH HIGH HIGH HIGH HIGH HIGH LAT UAT C
B13, UAT LOW HIGH HIGH HIGH HIGH LOW HIGH UAT LAT
B17, LAT LOW HIGH HIGH HIGH LOW HIGH HIGH LAT UAT
B17, UAT LOW HIGH HIGH HIGH LOW LOW HIGH UAT LAT
B20, LAT LOW HIGH HIGH LOW HIGH HIGH HIGH LAT UAT
B20, UAT LOW HIGH HIGH LOW HIGH LOW HIGH UAT LAT
OFF LOW LOW HIGH HIGH X X X X X
STANDBY LOW LOW LOW LOW LOW LOW LOW X X
LAT = LOWER ANTENNA
UAT = UPPER ANTENNA
OFF = LOWEST POWER STATE WITHOUT REMOVING LDO14_2V65 POWER
B STANDBY = ADDED TO SUPPORT EXISTING SW ARCHITECTURE. NOT TO BE USED AS A LOW POWER STATE. B

A A
PAGE TITLE

FRONT END LOGIC TABLE (2 OF 2)


DRAWING NUMBER SIZE

Apple Inc. 051-9584 D


REVISION
R
2.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
22 OF 23
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 45 OF 46
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

WLAN/BT
UAT2

J10_RF
MM5829-2700 L33_RF
F-ST-SM 8.2PF R13_RF
1 2
0
1 50_WLAN_ANT_FD 50_WLAN_ANT_MATCH_T 1 2 50_WLAN_ANT_MATCH

D +/-0.1PF
25V 1
5%
1/20W
D
C101_RF MF

2
3
4
CER 201
0201 0.2PF
+/-0.1PF
25V
2 COG-CERM
201
NOSTUFF U12_RF
DPX205850DT-9038A1SJ
SM

46 50_WLAN_A 1 HI COM 5
BI
XW20_RF
SHORT-L9-SM 50_WLAN_G 3 LO
46 BI
1 2

XW9_RF GND
SHORT-L9-SM

2
4
6
25 23
PP_VCC_MAIN_WLAN 1 2 PP_BATT_VCC_WLAN
IN
1 C103_RF 1 C104_RF
10UF 27PF
20% 5%
6.3V 16V
2 CERM-X5R 2 NP0-C0G
0402-1 01005

R17_RF
0.00
23 PP_WLAN_VDDIO_1V8 1 2 PP_WL_BT_VDDIO_AP IN 23 25

0%
1 C105_RF 1 C37_RF 1/32W
MF
0.01UF 27PF 01005
10% 5%
6.3V 16V
1 2 X5R 2 NP0-C0G
R16_RF 01005 01005 C106_RF
10K 18PF
5% 1 2 50_WLAN_G
1/32W BI 46
MF

16

BATT_VCC 27
BATT_VCC 28

VBATT_RF_VCC 46
VBATT_RF_VCC 47
C 32K INTERFACE TO AP
XW11_RF
2 01005
VDDIO_1P8V
2%
25V
C0H-CERM
1 C280_RF
C
SHORT-01005 0201 0.2PF
+/-0.05PF
25 23 CLK32K_AP 1 2 WLAN_CLK32K 36 CLK32K_AP 2G_ANT 43 50_WLAN_G_ANT 2 25V
IN COG-CERM
5G_ANT 54 50_WLAN_A_ANT 0201
GPIO_6 3 GPIO_6 NOSTUFF
HOST_WAKE_BT 41 HOST_WAKE_BT
OUT 23 25
C107_RF
WLAN_BUCK_OUT 31 VIN_1P2LDO 4.7PF
BT_WAKE 49 BT_WAKE
IN 23 25
1 2 50_WLAN_A
BI 46

+/-0.05PF
25 23 IN WLAN_REG_ON 51 WL_REG_ON U8_RF 25V
C0G-CERM
MOD-WIFI-BT-IMPERIAL 0201
BT_REG_ON 50 BT_REG_ON LGA BT_UART_RXD 39 BT_UART_RXD 1
25 23 IN IN 23 25
R18_RF 1 C170_RF 1 C281_RF
L9_RF BT_UART_TXD 40 BT_UART_TXD 100K
2.5UH-30%-0.7A-0.24OHM 23 JTAG_SEL 52 JTAG_SEL
OUT 23 25
5% 0.2PF 0.2PF
BT_UART_RTS* 37 BT_UART_RTS_L 23 25 1/32W +/-0.05PF +/-0.05PF
OUT 25V 25V
1 2 30 38 BT_UART_CTS_L MF 2 COG-CERM 2 COG-CERM
WLAN_SR_VLX1 SR_VLX BT_UART_CTS* IN 23 25
2 01005 0201 0201
0603 NOSTUFF NOSTUFF
25 23 50_HSIC_WLAN_DATA 24 WLAN_HSIC_DATA BT_PCM_CLK 32 BT_PCM_CLK 23 25
BI BI
25 23 50_HSIC_WLAN_STROBE 25 WLAN_HSIC_STROBE BT_PCM_SYNC 35 BT_PCM_SYNC 23 25
BI BI
BT_PCM_OUT 33 BT_PCM_OUT 23 25
17 OUT
NC SDIO_CLK 34 BT_PCM_IN
1 C102_RF 18 BT_PCM_IN IN 23 25
NC SDIO_CMD
4.7UF 20 10 HOST_WAKE_WLAN
20% 23 WLAN_COEX_RXD SDIO_DATA0 GPIO_0 OUT 23 25
2 6.3V
X5R-CERM1 23 SDIO_DATA_1 19 SDIO_DATA1 GPIO_1 5 AP_HSIC3_RDY 23 25
402 IN
23 SDIO_DATA_2 21 SDIO_DATA2 GPIO_2 11 WLAN_HSIC3_RESUME 23 25
OUT
23 2 WLAN_COEX_TXD 22 SDIO_DATA3 GPIO_3 2 WLAN_TX_BLANK 29
OUT
GPIO_4 4 WLAN_UART_RXD 23 25
45 IN
NC RF_SW_CTRL_3 12 WLAN_UART_TXD
14 GPIO_5 OUT 23 25
NC RF_SW_CTRL_7 13 WLAN_HSIC3_DEVICE_RDY
GPIO_12
B NC
WIFI_SW_CTRL
15
48
RF_SW_CTRL_8
RF_SW_CTRL_9
GPIO_9 8
6
OSCAR_CONTEXT_A
OUT
IN
23 25

2529 B
GPIO_10 LTE_ACTIVE IN 29

GPIO_11 7 OSCAR_CONTEXT_B 2529


IN
GPIO_15 9 LTE_AGG_PA_ON

VOUT_3P3 29 NC 1
GND THRML_PAD R45_RF
100K
5%

1
23
26
42
44
53

55
56
57
58
59
60
1/32W
MF
2 01005
PP_WLAN_VDDIO_1V8 23

1 1
R14_RF R43_RF
10K 10K
5% 5%
1/32W 1/32W R51_RF
MF MF
2 01005 2 01005
0.00 2
NOSTUFF 6 2 LTE_COEX_TXD 1 WLAN_COEX_RXD 23

0%
SDIO_DATA_2 23 1/32W
MF
JTAG_SEL 23 01005
SDIO_DATA_1 23
R52_RF
0.00 2
6 LTE_COEX_RXD 1 WLAN_COEX_TXD 2 23
1
R15_RF R44_RF
1 0%
1/32W
10K 10K MF
5% 5% 01005
1/32W 1/32W
MF MF
2 01005 2 01005

A A
PAGE TITLE

WIFI/BT: MODULE AND FRONT END


DRAWING NUMBER SIZE

Apple Inc. 051-9584 D


REVISION
R
2.0.0
PULL-UP ON GPIO6, SDIO_DATA_2 & PULL-DOWN ON SDIO_DATA_1 REQUIRED FOR HSIC BOOTSTRAPPING NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
23 OF 23
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST
IV ALL RIGHTS RESERVED 46 OF 46
8 7 6 5 4 3 2 1

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