A Fully Digital Architecture for Wideband Wireless Transmitters
Viral K. Parikh1 , Poras T. Balsara1 and Oren E. Eliezer2
1
Dept. of Electrical Engineering, University of Texas at Dallas. 2 Texas Instruments Inc., Dallas, Texas
Abstract— A fully digital architecture for wideband wire-
less transmitters is presented, which replaces high dynamic-
range analog circuits with high-speed digital circuits and thus
offers lower cost and higher performance compared to those
of conventional analog transmitters. The proposed transmit-
ter modulates wideband data in Cartesian coordinates and
generates its RF output using a fully Digital Quadrature
Modulator (DQM). The novel architecture employs a single
digital-to-RF converter, as it is based on fully digital com-
bining of the quadrature baseband signals. The design is
based on a standard 90nm CMOS process and is suitable for
integration with a digital signal processor, memory and logic
implemented in such digital process. Although the presented
results demonstrate compliance of the transmitter’s output
with the IEEE 802.16a (WiMAX) standard, the proposed
architecture may also be used for many other wideband
wireless and non-wireless communication standards.
Index Terms— Digital Quadrature Modulator (DQM), Dig-
ital RF Processor (DRPT M ), Fully Digital Transmitter, SDR,
SoC, WiMAX
I. I NTRODUCTION
II. P REVALENT T RANSMITTER A RCHITECTURES
A. Analog Intensive Direct Conversion Transmitter
In a direct conversion transmitter, as depicted in Figure
1, the baseband data is directly upconverted to the de-
sired RF carrier with in-phase and quadrature-phase Local
Oscillator (LO) signals, using two mixers [2]. Although
the baseband signals are typically generated digitally, the
low-pass filters ensure sufficient suppression of the spectral
replicas and quantization noise, thus meeting the spectral
requirements of the upconverted signal while relaxing the
specifications for the RF band-pass filter. As this architec-
ture is analog intensive, it is not amenable to integration
and is also prone to gain and phase imbalances, typically
requiring complex digital compensation techniques.




 
In current advanced nanometer-CMOS process tech-
nologies, the digital design flow offers significant advan-
tages over conventional analog circuit design, providing
numerous incentives to explore digitally-intensive RF so-
lutions. Contrary to digital circuitry, traditional RF and
analog circuits do not follow Moore’s Law as they migrate
to a more advanced process technology. Furthermore, the
technology scaling results in the reduction of the available
voltage swing, making RF design increasingly challenging.
While size and cost constraints drive the integration of
the radio with the processor, with the memory and with
other digital functions into a single System-on-Chip (SoC),
the demand for wider bandwidths and dynamic ranges, to
accommodate emerging standards, further complicates the
use of conventional analog circuitry. On the other hand,
the digital design flow enables a higher level of system
integration, simplifies testability and offers reduced power,
area and cost. It is also of interest to provide a flexible radio
architecture suitable for a Software Defined Radio (SDR)
platform, to support multiple wireless standards. The work
presented here addresses all these needs and constraints.
This paper is organized as follows: Section II surveys
several alternative transmitter architectures. Section III
introduces the proposed fully digital transmitter and the
Digital Quadrature Modulator (DQM) on which it is based.
Section IV presents simulation results and demonstrates
compliance with the IEEE 802.16a requirements [1].
1-4244-1463-6/08/$25.00 © 2008 IEEE
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Fig. 1. Conventional analog direct conversion transmitter
B. Digitally Intensive Architectures
1) A Fully Digital Polar Transmitter: The most digi-
tally intensive demonstrated transmitter is the Digital RF
Processor (DRPT M ) based polar architecture from Texas
Instruments, as presented in [3] and [4]. This transmitter,
shown in Figure 2, uses the CORDIC algorithm to gener-
ate output signals in polar coordinates (amplitude-A and
phase-θ) from the quadrature baseband signals I and Q
[5]. An All-Digital PLL (ADPLL) is used to synthesize
the carrier frequency and the phase modulation on it,
thereby acting as a Digital-to-Frequency Converter (DFC)
[6]. The fundamental frequency of the modulated square-
wave carrier from the ADPLL is given by cos[ωc (t)+θ(t)],
where ωc denotes the carrier frequency and θ(t) denotes
the required phase modulation. As shown in Figure 2, the
digital amplitude signal, A[n], is passed through predis-
tortion and interpolation to generate Â[n], which is fed to
the Digitally-controlled Power Amplifier (DPA) [7]. The
DPA acts as a Digital-to-RF Amplitude Converter (DRAC)
and merges the amplitude and phase paths to generate the
complex modulated signal, as expressed in equation 1.
147 RWS 2008
 This fully digital architecture possesses all the advan-
tages listed in Section I and provides a solution of lower
power and cost compared to conventional analog trans-
mitters. However, it encounters various challenges when
targeting wideband wireless systems. As the conversion
from the Cartesian to the polar coordinates in the CORDIC
is non-linear, it results in bandwidth expansion that neces-
sitates higher sampling rates and increases implementation
complexity. Furthermore, the peak frequency deviations
that are to be supported for wideband phase modulation
in the ADPLL may be very demanding. Additionally, the
recombination of the amplitude and the phase paths is
compromised due to the inherent filtering in each path,
potentially resulting in excessive out-of-band noise.
x(t) = A(t) · cos[ωc t + θ(t)]


 
III. T HE D IGITAL Q UADRATURE M ODULATOR (DQM)
Figure 4 depicts a simplified block diagram of the
proposed Digital Quadrature Modulator (DQM). The I and
Q samples of the baseband data are upsampled and filtered
to place the spectral replicas further in frequency and offer
initial suppression that relaxes the RF filtering require-
ments. Though zero-order-hold based upsampling places
notches at the integer multiples of the input sampling
frequency, where the replicas are located, these narrow
notches do not attenuate the wideband spectral replicas
sufficiently and thus additional filtering is essential.
By simple addition and subtraction, the signals abs(I −
Q) and abs(I + Q) are generated from the original I and
Q baseband signals. These two signals are alternately fed
(1) to the thermometer encoder to control N unit-weighted
transistors (i.e., the smallest size, referred to as ”1x”) in
the Differential-like Digital Power Amplifier (DDPA).



 
 
  The sampling rate of the input baseband signals is about

 
 11.4 MHz for the 10 MHz WiMAX modulation bandwidth.






The upsampler and filter interpolate these signals by an


oversampling ratio of 16. The sampling rate for the encoder

 



 
 is, therefore, about 183 MHz, which is not challenging,


  

  considering the low complexity of this function and the



    
 capabilities of the advanced CMOS process. The outputs
of the encoders are converted to the RF rate by N single-
Fig. 2. A fully digital polar transmitter bit 2-1 multiplexers, whose select lines are toggled at a rate
which is double the RF clock. The quadrant information
2) Transmitter based on Σ∆ Digital-RF Modulation:
of the I and Q signals, derived from their signs, is used to
In the recently proposed wideband transmitter, shown in
generate the control signal, which selects the appropriate
Figure 3, the quadrature baseband signals are separately
phase of the RF clock, referred to as RFCLKSEL . The
converted into RF signals, which are summed as analog
selected clock phase and data patterns drive the DDPA,
currents [8]. The transmitter incorporates an on-chip tun-
which acts as a digital-to-analog converter to generate the
able RF band-pass filter to suppress the quantization noise
RF output waveform given by equation 3.
generated by the sigma-delta structure. In this approach, a
high degree of tunability and careful analysis are required ##/* $-.
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to determine the optimal trade-off between the complexi- 


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ties of the sigma-delta structure and that of the RF band- 1
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pass filter. Additionally, it is not suitable for standards 
  
with modulation bandwidths below 100 MHz due to the ##/* $-.

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impractical band-pass filtering requirement (Q-factor). )
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Fig. 4. The Digital Quadrature Modulator (DQM)



 
 

A. The Digital Synthesis Process of the Modulated Signal

Fig. 3. A Σ∆ digital-RF modulator based transmitter
As evident from Figure 1 and equation 3, the modulated
3) Transmitter based on Direct-Digital RF Modulator: RF signal can be produced by summing the two products,
The quadrature transmitter architecture presented in [9] I(t) · cos(ωc t) and Q(t) · sin(ωc t). It is also possible to
uses two separate 10-bit digital to RF converters to produce synthesize such a signal digitally, as given by equation 2.
a WCDMA compliant RF output. Therefore, this architec- This synthesis process is shown in Figure 5 using (I, Q) =
ture is prone to the IQ imbalance problem. (4, 3), as an example of the baseband instantaneous values.

148
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The digital sequence LOI [n] represents one of the RF 


clock phases and LOQ [n] denotes the 90o phase shifted  


version of LOI [n] (i.e., shifted by Ts , a quarter of the car-
rier period). The I input signal is multiplied with the LOI 
     

clock to produce the first term in equation 2 and similarly,


the Q input signal is multiplied with the LOQ clock to  


produce the second term. These two terms are added to
generate the sequence x[n], which is the digital form of 







the modulated signal. Although the digitally synthesized

modulated signal x[n] is shown to have transitions at every

Ts interval, which is a quarter of the carrier period, none 
 

of the digital blocks actually require a 4×RF clock.


As shown in Figure 5, in every RF clock period, the 

sequence x[n] cyclically alternates between the four values 
abs(I − Q), abs(I + Q), -abs(I − Q) and -abs(I + Q), 
 


justifying the computation of abs(I + Q) and abs(I − Q) 

signals in the DQM, as shown in Figure 4. The multiplica- 


tion and addition operations of equation 2 are implemented 


digitally by simple AND gates and an adder respectively. 
  

 

 
x[n] = I[n] · LOI [n] + Q[n] · LOQ [n] (2) 


After filtering and extracting the fundamental frequency;
Fig. 5. An example of RF waveform synthesis for (I, Q)=(4, 3)
x(t) = I(t) · cos(ωc t) + Q(t) · sin(ωc t) (3)
The instantaneous positive values in the RF waveform
B. The Differential-like Digital Power Amplifier (DDPA) x[n · Ts ] of Figure 7 are generated by the left side of the
transistor pairs when the clock signal, RFCLKSEL , is ’1’,
The DDPA is an efficient implementation for the syn-
whereas the negative values are created by the right side of
thesis of the digital RF waveform given in equation 2 and
the pairs when the clock signal, RFCLKSEL , is ’0’. With
shown in Figure 5. It also merges the functionalities of a
this implementation, the data input (D0 − DN ) is toggled
mixer, a digital-to-analog converter and an RF band-pass
between only two values rather than four, thus reducing the
filter, to generate the final RF output current signal that
hardware complexity associated with its generation. The
corresponds to equation 3.
digitally synthesized waveform x[n] in equation 2 contains
The DDPA consists of pairs of unit-weighted NMOS
the desired RF modulated carrier and harmonics of it. The
transistors in a differential-like structure, acting as
matching network, tuned to the RF carrier, suppresses the
ON/OFF switches with finite ON-resistance. Each transis-
harmonics and recovers the required RF signal of equation
tor is preceded by a controlling AND gate, which is imple-
3, shown as waveform x(t) in Figure 7.
mented with pass-gate logic. The left side of the differen-
tial pair (transistors ML1 ...MLN ) is controlled by the clock  
RFCLKSEL and the right side (transistors MR1 ...MRN ) is   
controlled by the inverted clock RFCLKSEL . The DDPA    !  
   
is constructed with 128 transistor pairs (i.e. N =128) of size %
2x and 1 pair of size 1x, thus providing a resolution of 8- &%
     
 
bits, which is sufficient for compliance with the WiMAX '%



(%
standard. Whenever the output of an AND gate is ’1’, the 
 

transistor it controls will be turned ON and will pass the 

 !"

 
RF clock to the matching network. The matching network "!#$ 

is designed to suppress out-of-band replicas and noise,


generated due to the digital nature of the system, and to
provide impedance matching to the load.
Figure 7 illustrates the operation of the DDPA using
the example values of Figure 5, (I, Q) = (4, 3). The 



selected clock phase, RFCLKSEL , and the high-speed data



pattern, D0 − DN , are given as pairs of inputs to the AND 


gates. The data pattern determines the number of active

transistors, dictating the RF current through the load. Fig. 6. A Differential-like Digital Power Amplifier (DDPA)

149
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 It should be noted that the topology presented in [8] and 0

explained in Section II uses a cascoded stage to provide

active isolation between the two separate converters for the
I and Q branches, thus creating a challenge in terms of

Relative Power [dBc/Hz]

voltage headroom, whereas the digital combining of the −50 −50 dB
DQM completely eliminates such interaction concerns.




−100

 

!
"#$

−150
   %  %  %  %  %  5900 6000 6100 6200 6300 6400 6500 6600
Frequency [MHz]



Fig. 9. Far-out spectrum for the transmitter output
 "

 
 V. C ONCLUSION


  A novel fully digital architecture for wideband wireless


transmitters was presented, which realizes the complex
 modulation in Cartesian coordinates. As the combining
Fig. 7. Input and output signals of the DDPA of the quadrature branches is performed digitally, the
proposed Digital Quadrature Modulator (DQM) employs
IV. S IMULATION R ESULTS only one digital-to-RF-converter, thus eliminating gain
The proposed transmitter architecture was developed in imbalances and other impairments associated with alterna-
VHDL RTL and the high-speed DDPA was designed in tive quadrature modulators. The proposed architecture was
Agilent’s Advanced Design System (ADS) [10] using a shown to be compliant with the IEEE 802.16a (WiMAX)
90nm CMOS process technology. The presented simula- requirements. Its digital nature allows it to reach even
tion results for WiMAX were obtained using 64-QAM wider bandwidths and to be fully reconfigurable, making
modulation, 10 MHz of bandwidth, 256 sub-carriers for it suitable for a Software Defined Radio (SDR).
the OFDM signal, and an RF carrier at 5.84 GHz.
Figure 8 and Figure 9 show the transmitter’s output R EFERENCES
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