VLSI Important Questions

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VLSI DESIGN
QUESTION BANK
UNIT I Syllabus
INTRODUCTION : Introduction to IC Technology MOS, PMOS, NMOS, CMOS & BiCMOS
technologies- Oxidation, Lithography, Diffusion, Ion implantation, Metallisation, Encapsulation, Probe
testing, Integrated Resistors and Capacitors. CMOS Nanotechnology
Questions
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1.With neat sketches, explain in detail, all the steps involved in electron lithography process. April
2010, Set No. 1
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2.(a) What are the steps involved in the nMOS fabrication?
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(b) In what way PMOS fabrication is different from nMOS fabrication.
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(c) Which fabrication is preferred and why? Apr10 - Set No 2
3.Explain the following:
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(a) Thermal oxidation technique
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(b) Kinetics of thermal oxidation. Apr10 - Set No 4
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4.With neat sketches explain BICMOS fabrication process in a P well. [16] Apr10 - Set No 3
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5.Describe in detail, the diffusion process in IC fabrication. [16] Apr/May09 - Set No 2
6.(a) Define threshold voltage of a MOS device and explain its significance.
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(b) Explain the effect of threshold voltage on MOSFET current Equations. [8+8] Apr/May 2007, set
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7.A MOS Transistor in the active region measured to have a drain current of 20A when VDS=Veff.
When VDS is increased by 0.5V, ID increases to 23 A. Estimate the out impedance rds, and the out
impedance constant . Apr/May 2007, set 2
8.(a) With neat sketches explain the formation of the inversion layer in P-channel Enhancement
MOSFET.
(b) An NMOS Transistor is operated in the triode region with the following parameters VGS = 4V ;
Vtn = 1V ; VDS = 2V ; W/L = 100; nCox = 90 A/V 2 Find its drain current and drain source
resistance. [8+8] Apr/May 2007, set 3
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9. Describe in detail metallization process in IC technogly. [16] May/Jun 2009, set 1

10.With neat sketches necessary, explain the oxidation process in the IC fabrication process. [16]
May/Jun 2009, set 2
11.(a)Discuss fabrication differences between NMOS and CMOS technologies. Which fabrication is
preferred and why?
(b) Explain the various steps in PMOS fabrication. May/Jun 2009, set 3
12.Distinguish between thin film resistors and thin film capacitors in all aspects. [16] May/Jun 2009,
set 4
13. Explain the following terms related to the fabrication of IC
(a) Diffusion
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(b) Oxidation
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(c) Lithography
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(d) Metallization. [4+4+4+4] November 2008, set 1
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14. Briefly discuss the steps involved in the manufacturing process of an IC. [16] November 2008,
set2
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15. Describe Ion implantation mechanism in IC fabrication. [16] November 2008, set 3
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16.(a) What are the advantages of BICMOS Technology over CMOS Technology?
(b) Explain how a bipolar NPN transistor is included in N well CMOS processing Draw the cross
section of BICMOS transistor. [4+12]
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17. Describe different methods for fabricating integrated resistors. [16] Apr/May09 - Set No 1
18. Mention different growth technologies of thin oxides and describe any one technique in detail. [16]
Apr/May09 - Set No 3 w
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19. Describe probe testing in VLSI design process. [16] Apr/May09 - Set No 4
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20. (a) Explain the processing steps in fabrication of PMOS technology with neat
sketches.
(b) What are the additional two layers in BICMOS technology compared to other.
April 11 Set2
21. Explain about oxidation, Di_usion and Ion Implantation Processes of I C Fabri-
cation. [16] April Set4

22. (a) What is the purpose of metallisation in I.C. manfacturing? Explain the methods
employed for metallisation.
(b) What is probe testing? Why it is used? April 11 Set1
23. Explain about the process steps

(a) Crystal Growth
(b) Oxidation
(c) Diffusion
(d) Lithography
(e) Matallisation
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involved in the fabrication of ICs. April11 Set3
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UNIT II Syllabus
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BASIC ELECTRICAL PROPERTIES : Basic Electrical Properties of MOS and BiCMOS Circuits:
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Ids-Vds relationships, o; Pass transistor, MOS transistor threshold Voltage, gm, gds, figure of merit
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NMOS Inverter, Various pull ups, CMOS Inverter analysis and design, Bi-CMOS Inverters.
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1.(a) What is body affect? Discuss different parameters on which threshold voltage depends?
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(b) Determine Zpu to Zpd ratio for nMOS inverter driven through one or more pass transistor? [8+8]
November 2008, set 4
2.(a) Discuss the gate source and gate drain capacitance of an nFET.
(b) Calculate the gate capacitance of an nFET with following parameter. W=8m, L=0.5m, Cox =
3.45 107F/cm2. November 2008, set 3
3.(a) Clearly explain the body effect of a MOS FET.
(b) Clearly explain channel length modulation of a MOS FET. November 2008, set2
4.(a) With neat sketches, explain the transfer characteristic of a CMOS inverter.

(b) Derive an equation for Ids of an n-channel enhancement MOSFET operating in saturation region.
November 2008, set1
5.(a) Explain the operation of BiCMOS inverter? Clearly specify its characteristics.
(b) Explain how the BiCMOS inverter performance can be improved. Apr10 - Set No 4
6.(a) A CMOS inverter is built in a process where kn=100A/V2, Vtn=+0.7V, k'p =42 A/V2 , Vtp=-
0.8V, and a power supply of VDD =3.33V is used .Find mid point voltage VM if (W/L)n =10 and
(W/L)p= 14.
(b) Discuss the CMOS invertors transfer characteristics. [8+8] Apr/May09 - Set No 2
7.(a) Find gm for an n-channel transistor with Vgs=1.2V: Vtn =0.8V; (W/L) = 10; nCox = 92A/V2.
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(b) Define the term threshold voltage of MOSFET and explain its significance. Apr10 - Set No 3
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8. (a) Derive an equation for Transconductance of an n channel enhancement MOS-FET operating in
active region.
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(b) A PMOS transistor is operated in triode region with the following parameters. VGS= - 4.5V,
Vtp= -1V; VDS=-2.2 V, (W/L) =95, nCox =95A/V2. Find its drain current and drain source
resistance. Apr10 - Set No 2
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9.(a) Derive an equation for Ids of an n channel enhancement MOSFET operating in saturation region.
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(b) An n MOS transistor is operating in saturation region with the following parameters.Vgs=5V, Vtn
=1.2V, (W/L) =10: ncox=110A/V 2. Find transconductance of the device. May/Jun 2009, set1
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10.(a) Why resistor pull up is not used in MOS circuits?
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(b) Discuss different forms of pull up, mentioning merits and demerits of each form.[4+12] .
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11.(a) Explain briefly about MOS transistor switch.
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(b) Discuss the square law model of FET. May/Jun 2009, set3
2007, set 1
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12. With neat sketches explain how npn transistor is fabricated in Bipolar process. [16] Apr/May
13. With neat sketches explain how Diodes and Resistors are fabricated in pMOS process. [16]
Apr/May 2007, set2
14.(a) Compare between CMOS and bipolar technologies.
(b) With neat sketches explain nMOS fabrication process. Apr/May 2007, set4
15.(a) Define the threshold voltage of a MOS device and explains its significance.
(b) Explain the effect of threshold voltage on MOSFET current equation. April 2010, Set No. 1

16.(a) Find gm and rds for an n channel transistor with Vgs =1.2V,Vtn =0.8V,(W/L) =10;nCox =92
A/V2 and Vds =Veff+0.5V, the output impedance constant = 95.3 10-3/V-1.
(b) Explain figure of merit of MOS transistor. [8+8] Apr/May09 - Set No 1
17.(a) Derive the nMOS inverter transfer characteristics. Apr/May09 - Set No 3
(b) Explain the possibility of using a CMOS inverter as an amplifier. [8+8]
18. (a) Derive the relationship between drain to source current Ids and drain to source voltage Vds in
non saturation and saturation region
(b) Sketch the Ids versus Vds graph for enhancement mode device. [10+6] Apr/May09 - Set No 4
19. (a) Derive the relation between IDS & VDS of MOSFET.
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(b) Draw the circuit for NMOS inverter and explain its operation. Apr11 Set2
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20. Draw the circuit for nMOS Inverter and explain its operation and characteristics. Apr11Set4
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21.
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23. For nMOS Inverter driven by another nMOS Inverter, derive the expression for
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Zpu/Zpd ratio. Apr11 Set1
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UNIT III Syllabus
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VLSI CIRCUIT DESIGN PROCESSES : VLSI Design Flow, MOS Layers, Stick Diagrams, Design
Rules and Layout, 2 m CMOS Design rules for wires, Contacts and Transistors Layout Diagrams for
NMOS and CMOS Inverters and Gates, Scaling of MOS circuits,
Questions
1.Design a stick diagram for two input n-MOS NAND and NOR gates. Apr/May 2007, set1
2.What is a stick diagram and explain about different symbols used for components in stick diagram.
Apr/May 2007,set4
3. Draw the stick diagram and layout for
(a) NMOS inverter.

(b) P-Well CMOS inverter. April 2010, Set No. 1

4. Draw the stick diagram and layout for
(a) NMOS inverter.
(b) P-Well CMOS inverter. Apr10 - Set No 2
5.(a) Draw the following transistors using lambda based design rules
i. NMOS enhancement
ii. NMOS depletion
iii. PMOS enhancement.
Apr10 - Set No 4
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(b) Discuss the design rules for wires (both NMOS and CMOS) using lambda based design rules.
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6. Design a stick diagram and layout diagram for the CMOS logic shown below
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Y = (A + B) (C + D). Apr10 - Set No 3
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7. (a) what is a stick diagram? Draw the stick diagram and layout for a CMOS inverter.
(b) What are the effects of scaling on Vt?
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(c) What are design rules? Why is metal- metal spacing larger than poly -poly spacing. [8+4+4]
Apr/May09 - Set No 2
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8.(a) what is a stick diagram? Draw the stick diagram and layout for a CMOS inverter.
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(c) What are design rules? Why is metal- metal spacing larger than poly poly spacing. May/Jun
9. Explain the following w

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(a) Double metal MOS process rules.
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(b) Design rules for P- well CMOS process May/Jun 2009, set2
10. (a) Discuss the rule for n well and VDD and Vss contacts (2m CMOS).
(b) Discuss the rule for pad and over glass geometry (2m CMOS). May/Jun 2009, set3
11. Implement following logic functions using CMOS logic
November 2008, set1

12. Design a stick diagram for the N MOS logic shown below. Draw the circuit diagram and layout.

November 2008, set2

13. (a) Distinguish between RTL Simulation and RTLSynthesis.
(b) Explain the place and route tools used in VLSI design flow. November 2008, set3
15. Draw the CMOS representation stick diagram and layout for a two Input EX-NOR gate. [16]
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17. (a) Why scaling is required?
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(b) How does Depletion Regions around Source and Drain are affected due to
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scaling down of device dimensions? Explain. Apr11 set2
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18. (a) Draw the stick diagram and layout for the following function
f = A B + AC + B C
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(b) What is the difference between ' ' and ' ' scaling factors? Give some exam-
ples. Apr11 set4
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19. (a) Explain about Design Rule Check. Why is it employed?
(b) For various processes in MOS IC fabrication, explain about Design Rules. Apr11 set1
20. Due to scaling and smaller dimensions of MOSFETs, explain the e_ect on
(a) Drain Induced Barrier lowering
(b) Lower Transconductance
(c) Inter - connect capacitance. Apr11 set3

UNIT IV Syllabus
GATE LEVEL DESIGN : Logic Gates and Other complex gates, Switch logic, Alternate gate
circuits, Time delays, circuit Driving large Capacitive Loads, Wiring Units, Calculations -
Capacitances, Fan-in and fan-out, Choice of layers
Questions
1. Calculate on resistance of the circuit shown in the figure 4 from VDD to GND. If n- channel sheet
resistance Rsn=104 per square and P-channel sheet resistance Rsp = 3.5 104 per square. April
2010, Set No. 1
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2. Design a layout diagram for two input nMOS NAND gate Apr/May 2007, set1
3. (a) What do you mean by layout of a component.
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4. Design a layout diagram for the PMOS logic shown below
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(b) Draw neat layout diagrams for NMOS and PMOS transistor. Apr/May 2007, set2
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Apr/May 2007, set3
minimize area. Apr/May 2007,set4

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5. Explain with suitable examples how design the layout of a gate to maximize performance and
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6. (a) Differentiate between nMOS inverter pair delay and CMOS inverter pair delay.
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(b) Derive the expressions for rise and fall time of CMOS inverter delay.
(c) What is the total input capacitance value offered by the inverter to achieve symmetrical operation?
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7. Calculate ON resistance of the circuit shown in figure 4. From VDD to ground. If n channel
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resistance is Rsn = 104 per square. May/Jun 2009, set3

8.Calculate on resistance of the circuit shown in the figure 4 from VDD to GND. If n- channel sheet
resistance Rsn=104 per square and P-channel sheet resistance
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Rsp = 3.5 104
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per square.
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May/Jun 2009, set4
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9. Describe three sources of wiring capacitances. Explain the effect of wiring capacitance on the
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performance of a VLSI circuit. Apr10 - Set No 4
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10. (a) Explain the concept of sheet resistance and apply it to compute the ON resis-tance (VDD to
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GND) of an NMOS inverter having pull up to pull down ratio of 4:1, If n channel resistance is Rsn =
104 per square.
(b) Calculate the gate capacitance value of 5m technology minimum size transistor with gate to
channel capacitance value is 4 104pF/m2. [10+6] November 2008, set1
performance of a VLSI circuit. November 2008, set2
12. Explain the following:
(a) The delay unit.
(b) Inverter delays. November 2008, set3

performance of a VLSI circuit. Apr10 - Set No 2
14. (a) For a 5m technology, the standard unit of capacitances for metal 1,polysilicon and n-diffusion
are 0.0075 ?Cg, 0.1 ?Cg and 0.25 ?Cg respectively. Calculate the capacitances for area shown in figure
4. Consider same area for calculation.
i. metal
ii. polysilicon
iii. n-diffusion.
(b) Implement a 3-input NOR gate in dynamic logic and explain its operation. Apr10 - Set No 3
15(a) Describe the following briefly cascaded inverters as drivers.
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(b) Super buffers.
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(c) BiCMOS drivers. [8+4+4] Apr/May09 - Set No 2
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16. (a) For a 5m technology,the standard unit of capacitances for metal 1,polysilicon and n-diffusion
are 0.0075 Cg, 0.1 Cg and 0.25 Cg respectively. Calculate the capacitances for area shown in figure 4.
Consider same area for calculation.
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i. metal
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ii. polysilicon
iii. n-diffusion.
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(b) Impliment a 3-input NOR gate in dynamic logic and explain its operation. [8+8]Apr/May09 - Set
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No 1
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17. Calculate the rise time and fall time of the CMOS inverter (W/L)n= 6 and (W/L)p=8, K'n =150
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A/V2, Vtn =0.7V,K'p= 62 A/V2, Vtp=-0.85V , VDD =3.3V. Total output capacitance =150 fF. [16]
Apr/May09 - Set No 3 w
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performance of a VLSI circuit. [16] Apr/May09 - Set No 4
19. (a) Derive the expression for _SD in the case of a MOSFET.
(b) Explain about sheet resistance and sheet capacitance. Apr11 Set2
20. (a) Explain about BICMOS Driver circuits.
(b) Derive the expression for propogation delay D in the case of cascaded pass
Transistors. Apr11 set3

21. (a) Derive the expressions for Rise-Time R and fall time f in the case of CMOS
Inverter.
(b) Express the Area capacitance interms of standard capacitance units. Apr11 Set1
22. (a) Draw the CMOS circuit to realize the Boolean expression y=A-B, and explain
the same.
(b) What is meant by fan in & fanout of gate.
UNIT V Syllabus
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DATA PATH SUBSYSTEMS : Subsystem Design, Shifters, Adders, ALUs, Multipliers, Parity
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generators, Comparators, Zero/One Detectors, Counters
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Questions
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1.(a) Draw and explain the schematic of Pseudo-nMOS comparator.
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manner. April 2010, Set No. 1
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(b) Draw and explain the structure of multiplier which computes the partial products in a radix-2
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2. Calculate the gate capacitance value of 1.2m Technology minimum sized transistor with gate to
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channel capacitance value is16 104pF/m Apr/May 2007, set3
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3. Calculate ON resistance from VDD to GND for the given inverter circuit shown in Figure 5, if n-
channel sheet resistance is 5 104 per square.
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Apr/May 2007, set4

4.(a) Explain how the transistor might be sized to optimize the delay through the carry stage in parallel
adder.

(b) Design a two input XOR using a ROM. May/Jun 2009, set1
5. Develop a model of word line decoder delay for a RAM with 2n rows and 2m columns. Assume true
and complementary inputs are available and that the input capacitance equals the capacitance of one of
the columns of H=2m. Use static CMOS gates and express result in terms of n and m. May/Jun 2009,
set2
6.(a) Explain how the transistor might be sized to optimize the delay through the carry stage in parallel
adder.
(b) Design a two input XOR using a ROM. May/Jun 2009, set3
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7. Draw the logic diagram for a ripple-carry binary counter using T registers and ex-plain its operation
with the help of truth table and also compare it with synchronous counters. Draw the schematic for T
register. May/Jun 2009, set4
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Apr10 - Set No 4
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8. (a) Draw the multiplier array using a square array and explain the operation of multiplication.
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(b) How is the parity generator designed as a linear column of XOR gates with a tree routing channel
and draw the layout of it.
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9. (a) Compare different types of CMOS subsystem Adders.
set1
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(b) Draw the mask layout for 6 transistors static RAM used in ASIC memories. November 2008,
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10. (a) Draw the schematic for Transmission gate adder and explain its operation with truth table.
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(b) Show the basic one row and one column RAM architecture and explain its operation. November
2008, set2
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11.(a) Design a comparator using XNOR and AND gate and draw its schematic.
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(b) Design a zero/one detector and draw its schematic and also calculate its delay. November 2008,
set3
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12. Develop a model of word line decoder delay for a RAM with 2n rows and 2mcolumns. Assume true
and complementary inputs are available and that the input capacitance equals the capacitance of one of
the columns of H=2m. Use staticCMOS gates and express result in terms of n and m. November
2008, set4
13.(a) Design a magnitude comparator based on the data path operators.
(b) Draw the Schematic and mask layout of array adder used in Booth Multiplier and explain the
principle of multiplication in Booth Multiplier. Apr10 - Set No 2

14. (a) Explain how the transistor might be sized to optimize the delay through the carry stage in
parallel adder.
(b) Design a two input XOR using a ROM. Apr10 - Set No 3
15. (a) Explain the CMOS system design based on the control structures with suitable example.
(b) What are the different types of Memory elements? Compare them with respect to CMOS design.
[8+8]
16. (a) Explain the CMOS system design based on the data path operators with a suitable example.
(b) Draw and explain the basic Memory- chip architecture. [8+8] Apr/May09 - Set No 2
17. (a) Draw and explain the Booth decode cell used for Booth multiplier.
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(b) Compare different types of CMOS subsystem shifters. [8+8] Apr/May09 - Set No 3
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18. (a) Explain how the partial products are independently computed in parallel multiplier.
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[8+8] Apr/May09 - Set No 4
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(b) Draw the circuit and layout for ROM and explain how the dynamic power dissipation is minimized.
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19. (a) Explain about bit sliced Data path organization. What is the significance of
Data paths in digital processors?
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(b) Give the Truth Table for full adder and explain its Boolean expression. Apr11 Set2
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20. With the help of a schematic explain the principle of Tree Multiplier. Apr11 Set4
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21. What are the circuit design considerations in the case of static adder circuits. Apr11 Set1
22. Give the schematic for a 44 carry-save multiplier and explain its operation. Apr11Set3
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UNIT VI Syllabus
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Array Subsystems: SRAM, DRAM ,ROM,Serial Access Memories, Content Addressable Memory.
Questions
1 (a) Explain how the partial products are independently computed in parallel multiplier.
(b) Draw the circuit and layout for ROM and explain how the dynamic power dissipation is
minimized. [8+8] Apr/May09

2. Develop a model of word line decoder delay for a RAM with 2n rows and 2mcolumns. Assume true
and complementary inputs are available and that the input capacitance equals the capacitance of one
of the columns of H=2m. Use staticCMOS gates and express result in terms of n and m. November
2008, set4
3.Draw the mask layout for 6 transistors static RAM used in ASIC memories. November 2008, set1
4. (a) Explain how the transistor might be sized to optimize the delay through the carry stage in parallel
adder.
(b) Design a two input XOR using a ROM. Apr10 - Set No 3
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5 Show the basic one row and one column RAM architecture and explain its operation. November
2008, set2
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6.
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UNIT VII Syllabus
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SEMICONDUCTOR INTEGRATED CIRCUIT DESIGN : PLAs, FPGAs, CPLDs, Standard Cells,
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Programmable Array Logic, Design Approach,parameters influencing low power design
Questions
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1.(a) Explain the methods of programming of PAL CMOS device.
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(b) Draw and explain the architecture of an FPGA April 2010, Set No. 1
2.(a) What are different classes of Programmable CMOS devices? Explain them briefly.
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(b) What is the basis for standard-cell? What are basic classes of circuits for Library cells?
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3.(a) What are the advantages and disadvantages of the reconfiguration.
(b) Mention different advantages of Anti fuse Technology. [8+8] Apr/May 2007, set1
4. Using PLA Implement Full-adder circuit. Apr/May 2007, set2
5. (a) Compare the Antifuse and Vialink programmable interconnections for PAL devices.
(b) What are different typically available SSI Standard-cell types and compare them. [8+8]
6.(a) Draw the diagram of programmed I/O pad and explain how the antifuses are used in this.
(b) Draw and explain the AND/OR representation of PLA. May/Jun 2009, set1

7(a) what are the differences between a gate array chip and standard-cell chip? What benefits does each
implementation style have?
(b) Write the equations for a full adder in SOP form. Sketch a 3-input, 2- output PLA implementing
this logic.. May/Jun 2009, set3
8.(a) Draw the typical architecture of PAL and explain the operation of it.
(b) What is CPLD? Draw its basic structure and give its applications. May/Jun 2009, set4
9.(a) Draw and explain the Antifuse Structure for programming the PAL device.
(b) Explain how the I/O pad is programmed in FPGA. November 2008, set1
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10.(a) What are different classes of Programmable CMOS devices? Explain them briefly.
(b) What is the basis for standard-cell? What are basic classes of circuits for Library cells?
November 2008, set2
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11.(a) Draw the typical standard-cell structure showing regular-power cell and explain it.
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and disadvantages of it. Apr10 - Set No 2
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(b) Draw and explain the pseudo-nMOS PLA schematic for full adder and what are the advantages
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12.(a) What are the characteristics of 22V10 PAL CMOS device and draw its I/O structure.
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(b)Explain any one chip architecture that used the antifuse and give its advantages. Apr10 - Set No
3
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13.(a) Draw a self timed dynamic PLA and what are the advantages of it compared to footed dynamic
PLA.
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(b) Explain the tradeoffs between using a transmission gate or a tristate buffer to implement an
FPGA routing block. [8+8] Apr/May09 - Set No 1
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14.Draw the structure, explain the function and write the applications characteristics of the following
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programmable CMOS devices: [16]
(a) PLA
(b) PAL
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(c) FPGA
(d) CPLD. Apr/May09 - Set No 3
15.(a) Draw the typical standard-cell structure showing low-power cell and explain it.
(b) Sketch a diagram for two input XOR using PLA and explain its operation with the help of truth
table. [8+8] Apr/May09 - Set No 4

16. Explain about the principle and operation of FPGAs. What are its applications? Apr11 Set1
17. Compare PLAs, PALs, CPLDs, FPGAs, and standard cells in all respects. Apr11 set3
UNIT VIII Syllabus

CMOS TESTING : CMOS Testing, Need for testing, Test Principles, Design Strategies for test, Chip
level Test Techniques, System-level Test Techniques, Layout Design for improved Testability.
Questions
1.(a) Mention the properties of the twin oxide.
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(b) Clearly explain about ION implantation step in IC fabrication. Apr/May 2007 set 1
2. Explain about the following two oxidation methods.
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(a) High pressure oxidation.
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(b) Plasma oxidation. Apr/May 2007 set 2
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3.With neat sketches explain Atmospheric-pressure chemical vapor deposition method.Apr/May 2007
set3
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4. Explain about the following Die bandings.
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(a) Eutectic die bonding.
(b) Epoxy die bonding. Apr/May 2007 set 4
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5. (a) Explain different fault models in detail.
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(b) Draw the general view of the TAP data register and explain how a boundary scan register is used
for testing. May/Jun 2009 set 1
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6.(a) Explain how function of system can be tested.
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(b) Explain any one of the method of testing bridge faults.
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(c) What type of faults can be reduced by improving layout design? May/Jun 2009 set 2
7.(a) Why the chip testing is needed? At what levels testing a chip can occur?
(b) What is the drawback of serial scan ? How to overcome this?
(c) What is the percentage fault coverage? How it is calculated? May/Jun 2009 set 3
8.(a) Explain the gate level and function level of testing.
(b) A sequential circuit with in? inputs and m storage devices. To test this circuit how many test
vectors are required.
(c) What is sequential fault grading? Explain how it is analyzed. May/Jun 2009 set 4

9. Explain the following with respect to CMOS testing:

(a) ATPG
(b) Fault simulation
(c) Statistical Fault Analysis
(d) Fault Sampling. . November 2008 set1
10.(a) Explain how the cost of chip can effect with the testing levels,
(b) Explain how observability is used to test the output of a gate within a larger circuit.
(c) How the Iterative Logic Array Testing can be reduced number of tests. November 2008 set2
12.(a) What type of defects are tested in manufacturing testing methods?
o m
(b) What is the Design for Autonomous Test and what is the basic device used in this?
. c
(c) What type of tests are used to check the noise margin for CMOS gates? November 2008 set3
ls
13.(a) Explain the manufacturing test of a chip with suitable examples.
a
r i
(b) Explain how an Ad-hoc test technique used to test long counters. November 2008 set4
t e
(b) A sequential circuit with n inputs and m storage devices. To test this circuit how many test
vectors are required?
a
u m
(c) What is sequential fault grading? Explain how it is analyzed. April 2010, Set No. 1
15.(a) Why stuck-at faults occur in CMOS circuits? Explain with suitable logical diagram and layout.
t
(b) Draw a schematic for a CMOS edge-sensitive scan-register and also draw some circuit level
n
.j
diagrams of its implementation. Apr10 - Set No 2
16.(a) Explain how function of system can be tested.
w
(b) Explain any one of the method of testing bridge faults.
w
(c) What type of faults can be reduced by improving layout design? Apr10 - Set No 4
w
17.(a) Explain the functionality test of a chip with suitable examples.
(b) What are the categories of Design for testability? Explain them briefly. Apr10 - Set No 3
(b) A sequential circuit with ?n? inputs and m storage devices. To test this circuit how many test
(c) What is sequential fault grading? Explain how it is analyzed. [6+4+6] Apr/May09 - Set No 1

(b) A sequential circuit with ?n? inputs and m storage devices. To test this circuit how many test
(c) What is sequential fault grading? Explain how it is analyzed. [6+4+6] Apr/May09 - Set No 2
(c) How the Iterative Logic Array Testing can be reduced number of tests. [5+6+5] Apr/May09 -Set
No 3
o m
(c) How the Iterative Logic Array Testing can be reduced number of tests. [5+6+5] Apr 09 - Set No 4
. c
ls
22. (a) How layout design can be done for improving testability? Explain.
a
r i
(b) Explain about different fault models in VLSI testing with examples. Apr11 set3
23. (a) With the help of a schematic explain about Memory-self Test.
t e
(b) What are the issues to be considered while implementing BIST? Explain. Apr11 Set1
a
24. (a) What are the di_erent categories of DFT techniques? Explain.
u m
(b) What is meant by signature analysis in Testing? Explain with an example. Apr11 set4
25. Explain about Testing and Fault Simulation in VLSI Design. Apr11 set2
n t
.j
w
w
w

VLSI Important Questions

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9. Describe in detail metallization process in IC technogly. [16] May/Jun 2009, set 1

n t November 2008, set 4

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23. Explain about the process steps

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(b) P-Well CMOS inverter. April 2010, Set No. 1

9. Explain the following w

November 2008, set1

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November 2008, set2

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minimize area. Apr/May 2007,set4

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Apr/May 2007, set4

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UNIT VIII Syllabus

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9. Explain the following with respect to CMOS testing:

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