3 YNIIT—Vv SUBSYSTEM DESIGN UBSISTEM DESIGN Most chips ae built from collection of subsystem \ke adders, Teqs , State machines etc. Digital fng can be divided inity : — dalapath operate im memory eleme — ctw) structnes — fo cells. Aven bd cost can be reduced oe of ae wi. of abstvachon : bg optimiga Lovouk , Circuit, logic, Register -bransfer . SHIFTERS shiftes dre icmp elems in roany micxoptoc® - designs fos arithmetic shifting, logical sh ting & rotchim functions. fB bamel shifter can perform m-bit shifts me gingle corabinational fn . Banet shifter accept: ‘an’ data biti 2 ‘mn’ ctr! signals and Produces ‘on? olp bits.> Tt shiPG by tranemitti an m-bit alice of the ‘an’ dil. bia tp the olps. > he position of the transmitted slice is detexrnimed by the ctrl bi; exact oper is deberrnined by values placed ot the dah Tipe. ex: Right shift alth pro Fall. noe f = n bile biti J Flee i dole word W wit top Sip. ak ole into bottor Alp. the olp i2 wight shift with ger fill. by Setting atl bik te select “tep- mast Se’ bite «tk ShiPE Of Zero. Setecti bottom ‘’ bik ie an n- bit shee Pushing entive word out. of the shifter. > 27? = Reale Opeshon Ushen, both top & bottom lps have same dota. Rotate operalion shitting out top bik of work cami those bik to reappear al the bottom olpcute out i, oy) Cori in ( O thitty>-0 ‘ehcttge Shitty= > Bone shift with “w’ ofp bits cs built from ‘gn’ vertical by ‘vn’ hovgl anay of celle, each hos Single Tr & few wires. > Cll ig Tk gal formed uring single m- type Tr: 5 Ceel_dings van vatieally; fp tun dignally upward nu the System} olp hovigentally ,Ctrl limeg Set to ‘a’, tune G7 gate in Single column. Tre %% gah connect chagonad Sip wires to hor, olp usures) when col is turned on, a\\ Ips are shurted to the olps. he Length of the shift i debermine cl by position of the selectid column. ADDERS: t) Futl_addu: 4-bit sum; 12-bit Carry . Sums ABC +ABCt ABC+ ABT Sum. “OBe@c, Crays Cony= : Abt ace Ac, Sums = Sum at ith” stage i Cite Cong, :SDpD 2—=>-— spp” ¢ hee ase)7] ? eee we) Pe pb) ey A) 6°? to ra) § 35 Cpe) Cenp : “Ce Sn) S&) sean, SQ Single bit adder C2@ Tes) SME Aloe + Chr Bred CARRY @ = AwCy Cateroo( PB (PAB): ey Se (R@Epec= POC FA using ROR gates uses 22 tronsisbrg, FA Weding carcaded logte gates uses 28 transits, CARRY oe ; = ABtAC+Bc = Alt c/Caea!) —= ca Bit Parallel Adda C Ripple Camy Adder). > > 3 n- bit adder built by cascading tw’ a- bit addes - f Ripple - cay adder is easy to design but ig glowo §=0 when ‘n’ ts Lange. he lps we a bit ALB. the cany Signal by Stage Si? it fed te the c’ signed of abage ix"? 2 ‘sum 8 signal forms ao bt olfCD wbtt subtrachr- \ ec oy WW 88D neo — 825 mo D, 801) ec) — Sto? A) Vag. eq: A-B. : re (4) Addu / Subtract. # bats aa Be) Leca> a sce 7 a Dg Dh sa 3a) a) 2) Scedbaviduea dm shevhdos 6 oxtas eS 2% torte \nbbA <5) - cori. Be oe Pac wey ® eA ce5e 5 @a C (Os @a Rayeyy Catty~ lek ahead adder. Sf ais, bis ae ripe, pe Pacpagale G= Geneols Sum 5 CE® P-® 6; Celt Get Pee Co Get Cage Pea Send Cen = GE PeGe) > RC, Gea t PR Pah Sous Cray depends On Cry & not on ye ot Yee,), > the cavvy- look ahead umits ean be vecurtins comected te form a tree; eoch ante generals th oton ‘P?2 Gy’ values , which are wed +t feed carry lookahead unit at the next level of the tree,CH) Carry- Select Adder. TT / > Computis two versions ef the addition ‘with’ GFF camy-ing , then Seleck the. vight ove- > mbt stages. -> The amd stage compiles 2 values one at suring eany-in iS & another Y. > The cary out of prey Stage te oned Select which version %& covvech: Muxes ctrlled by prev stoyele carry -out choose corvect gum & Cary- out > te apeeds up odd Coa, 1h stoge can be compicting two versions of the sum tm parallel eotth tit's computation of re tarry. 2 Serial Addlers : > Require Many clk cycled te odd too nrbit nos. > Small / / Veoo lle 4— dal. Powmat abit FF Lap- tohen curry dats bi aw Lene oF the addende. @ Menchester Cony Cheio : 4f Ge=l 1» dusting evalua st, e, storage mode t& discharged, Producing ont ty ints neat Stoge. af Pet, then ith Srage node te connected te GW storage node , ith Storage mode can be dachaged by Pe, pd, > ie-bit adders. CPwr Comseump> adder Pwo Cv * Ripple-Cany- onze Const width O'lo Wi Camy- Skip : u + Cany- lookahead 0 I$) % Canty. Select O-216-ww _ Cas y- Save Adda : Save ecanyd sum for each cycle, m bit addere: S cantea & WW sume. mbit ceA veqe “om” Degisters. peduces ervitical patt,. of veg, adda ddloy See up time. tle 7. We - Gate Adda CTE) a! A@®DB fig: Ten gak wor. CTiny ORD 62 logie ae Ol low. Pe N, t tnveter with @' at olp. Tr gale by paiv % &No tg open. Aclow, als high , (Pa, Mo) = closed, Passing \p’ th olp. the tMmv® CP, om) ie Datiallu Meallot( Casty- Skip Adder : > Bie looks for caree there cauy out ofa Ree of bit ds Same as the camry tn te those bets. this addel is erganized trio m- bit groupe: if the Carry is propagated for every bit ly the Stage, ‘then bypass gate Senda the g stogek Canny Xp directly t Canty olp. > dwided units 2 groupe of biti; w Tue Carty énto group ¥ Wae cond” ‘Pat every bit wm tthe Qroup us needed to came cany te &kip. GH yet =oPARITY GENERATORS Detects mo. of 4 in 4ip word os odd or even Function ts Parity = M@ M® --- OAn. (*) Qtaic OR tree BOD: D> € D— DY FH 2OcHDo POD Ly erase ‘ =p COMPARATOR: > Used to compare the magnitude of tio binary nos. 3) St cen be ‘elt using an adder and complementer.ae@oeaev-z YOX Indu-y oneys (9) ‘uosianoimeudp (q) £90 YOX oneIs (e) :uON -e1oue6 Awed z"g eunBiaFig: Comparato® using adda. > A geo detect (Nor gate) provides A=28 staal wohile final camy olp provides B>A Signal. > other Signals like AcB ov ASB, can be generatid by logical combination of these Signals. > For wequality, Teed only xNOR & AnD gale. 9 Figo: rove te ate (em gate) mo DC curr , Slow fr long Compe. D> Figo: com ~NOR/ NoR De Cun, 6 eral & fost , i bLo | wo gop wom @ by be Comparator cir- xe t= ALB+ 978;! (= SD = WANA = | 2) > | eZERO /ONE DETECTOR : > Detecting all omes or all gews on wide words veq, large fan-in anp ew oR qa > Oelay te lp % logN — Crs bit width of word) > pseude- mMos Nor galt lmplementabion of pol one detects tg very fast & emall fr word widths lese than 22 bits. a.(%) a(6> ats) acu) = azcome ot? " Qzr treo Cusing Altomle N AWD & NOR)COUNTERS + Count gees tha Sequence of binary reg. “specs Court at anging times 0-8 > olpg ¢ clk cycle or edge. eqi- cripple Counter: > The cling of each Stage te carried out by the previous counter stage , & thus the time tt takee the last ceuntes Stage can be quite lange for a long > tw settle Counter chain. Synchronous Counters + > elpe Change ot substantially game time, ex: Up! down Courter. up! down Counter basically uses adda 5 & a D-FF. > he speed vs determined by the aipple- omny time from L3e te the MgB,COUNTERS + = Count gece thee a Sequence of binary reg. ‘epcnceie Comme > olps change at varying times wot clk cycle ov edge. ex:- wipple counter: > The cl king of each Stage te carried ouk by the previous counter Stage, & thus the tire tt takee the Last countes tae t settle can be quite e fo lo | Counter chain. “4 "* "8 Syncmonous Counters : | > clea change at -sehebetinlly Some Line ex up! down Counter. -5 vp! down eauaheast basically wes addu &£ a D-FF. > he speed ce determined by the vipple- omy dime from L8B te the Map.sieisi6e: pue sieppe se9p- | ‘dn—jumop 6ursn seyunN09 umop/dn snouosyoudg gg aun Th bt O on op NSISSG W3LSASSNS 8 H3LdVHO aesALUs : Arithmetic. Legic Onit Peforrng beth arithrnetic £ logical oper’s. Basic ALY takes two dak Ips £ a set of ctrl Signals , Called opcode. The ©pco de along wth AL's , Car ry-tn, determine ALUS function . Logic te comput, all possible atu ne can be Lange unless carefully designed.8.2 DAIAPAINUrEnAIUnS ote = / Signal me de = falee Carithmetic) = truc Cboolean). SCo>=) , “b’? pawed to elp. , ' FIGURE 8.34 181 ALU |MOLTIPLIERS > Used in Cemy, Covselation, filtering , freq, Analysis , > shift & add- > & Steps: Cb Evaluation of padtial products WD Accumulation of shifted partial Products. Partial prodiucl = = - ANDing ef multiplicand 4 multiplier bit. > Classification of multipliers : — Serial ferry — Seval/ parallel ‘orm — Parallel form. >4n Parallel multiplier , partial producdi computed in Parallel . - ex = ie = pi n- EY ™ Ee ok c. Pastial “¥ ko a = SwomandsFoo 4-bit Multip lien. Te oe Ox; WM Multiplicand Yo W a YD Muttiplier %sYo X2Yo XYp XoYe Ma, B2¥, os AND BY. KIY2 Xove2 *aXa, ONS XD AovS Gite Pe fi, a he By Po = > men Multiplier vege: m(n-2 FAS, T HAs , ot ann oe a Worst- Care delay = (2m+ 1) % pg = werst- Care adder : P delay Aavay Mutiplier Cel).2 Propagaicl diagonally from top wight te bettom Left. ee horigontally. athe bit- Wise AND Ls performed én the cell, & Som ts parsed to neat cell below. > “camy- out” is = pased ts the bottom left the cell. = xcs C2) 0) Ko) 7 co) GE | ¥o¥o WYO %oYD YO) Fy O44 anay moultip lita, Rodia- Mubtiplier :- i eee 3 Poeve te vadta.2 anultiplte™, 63 Computalion done by ene bit of omultiplican at atime. 3 High- tadin Multipliers teduee mo. of adders, & delay gyeqid tb cempult partial gume,558 CHAPTER® SUBSYSTEM DESIGN Figure 8.41 A4:2 (5:3) ‘compressor circuit FIGURE 8.42 Serial multi- plier iat eo Bo 4 go ‘The two numbers X and ¥ are presented serially to the circuit (at differ- cent rates to account for multiplier and multiplicand word-lengths). The par- tial product is evaluated for every bit of the multiplier, and a serial addition is performed with the partial additions already stored in the register. The AND gate (G2) between the input to the adder and the output of the register is used to reset the partial sum at the beginning of the multiplication cycle. If the register is made of N’- 1 stages, then the I-bit shift required for each par- tial product is obtained automatically. As far as the speed of operation is con- cerned, the complete product of M + N bits can be obtained in MN intervals of the multiplicand clock.Per> Pb Pes> Pet array cell). In this case the appropriate inputs to the first and second row would be connected to ground, as shown in Fig. 8.36. The cell design for this mul ier is relatively straightforward, with the main attention paid to the adder. An adder with equal carry and sum propa- gation times is advantageous, because the worst-case multiply time depends ‘on both paths. 8.2 DATAPATH OPERATORS 547 FIGURE 8.36 A4x 4 array . multiplier82 DATAPATHOPERATORS 559 Yee vers veo ve =o 818 | | 6 4} [4] Cy 4] Using the general approach discussed previously, itis possible to realize a serial/parallel multiplier with a very modular structure that can easily be modified to obtain a pipelined system. The basic implementation is illus- trated by Fig. 8.43. In this structure, the multiplication is performed by means of successive additions of columns of the shifted partial products matrix. As left-shifting by one bit in serial systems is obtained by a I-bit delay clement, the multiplier is successively shifted and gates the appropri- ate bit of the multiplicand. The delayed, gated instances of the multiplicand must all be in the same column of the shifted partial-product matrix. They are then added to form the required product bit for the particular column. This structure requires M + N clock cycles to produce a product. The ‘main limitation is that the maximum frequency is limited by the propagation through the array of adders. The structure of Fig. 8.43 can be pipelined with the introduction of two delay elements in each cell, as shown in Fig, 8.44. If rounding or truncation of the product term to the same word length as the input is tolerated, then the time necessary to produce a product is 2M clock cycles. In this case the multiplier accumulates partial product sums, starting with the least significant partial product. After each addition, the result is an FIGURE 8.43 Serial/ parallel multiplier FIGURE 8.44 Pipelined serial/parallel multiplier8.2 DATAPATHOPERATORS 557 pn Pio or RES8 235 25 8 3 4 Pa Pt 9) layout fora 54-by-54 bit multiplier using the compressor shown in Fig, 8.41 may be found in Goto et al.'® 8.2.7.4 Serial Multiplication Multiplication may be performed serially. The simplest form of serial multi- plier, shown in Fig. 8.42, uses the successive addition algorithm and is implemented using a full adder, a logical AND circuit, a delay element (i.e., either static or dynamic flip-flop), and a serial-to-parallel register. FIGURE8.40 Wallace adder tree (for 6 x 6 multiplier)Booth Mubtiplie? eaionines > wie of raultipleandl ok a «(time te determine whether te add Hr, i+, -\*, gt) -a™ of that wank of aaultiplicand- Booth- recoding table : wa Neat CPpestion NEG =ERO Two oO © addo oe 2 add2 0 Sub) ! D | a= add 4. Sub 4 add 4 oO Sub 2 ) addo 0 i oea¢s © 0 7 = eo aor = eo = a = @ > Booth- auay accep tuo 16-bit Ips, & fede CPA C Camy Propagale Array) - > the ¢PA alto accepe S2-bit Tip +e perem multiple qacumbibala. en oe Fagen 16 boot Mult® orm CPiver plas) Manches te. cP C2cols),