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  • Unit 3

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    15 Ansichten32 Seiten

    Unit 3

    Hochgeladen von

    ratnams
    unit-3 of vlsi

    Copyright:

    © All Rights Reserved
    Als PDF herunterladen oder online auf Scribd lesen
    Markieren Sie unangemessene Inhalte
    von 32
    VLSI CIRCUIT DESIGN PROCESS VLSI DESIGN FLow (fete the “4ront -end” heging wlth Ptgurt out — baste appevach & building bloke at the block dliagyam Level, She ment Level sy wetting Hn code fos mockules, they tmtebaces » £ thelr internal oletaile. She HDL Compiler analyzes — Cocka fox Sarita. evore and also cheeks it for compel bility wth other modules on rte She HDL Stmulactoy allows, do Aakfine and cry ilps tb desta and to observe th olpe totthow having to build phyateal — cevcutli. CHunctional vestdication. Back end Stage. stat, with Synthesis, thate converte pt deseatpbin ‘ot a xt of primitives ox components that can be amembled im the target’ “technology : Dh, ds called netlist that spect fies how they Should be — interconnected , Sn Fitting Step, a fitter maps the syntheeiged cornponentz onto available device. sescurcer. Place & wult proces lays components ancl Finds coaya to commect them, he. dosigner can usually — Speciby additonal constrain at thir Stage, dike placement ef Modules twithin a chip ov the. pin aniguromt, of externol Ilp £ Op ping, dhe final Sep ds — post- fitting ning verification dk the fitted civeuit + At th Stage actual ckt delaye due to wire lengths, electrical loading and othr faclore can be calculated « Mos LAYERS Moe ctscedti are. forme on basic Layers’ cy m- Atffuston. diy pe Ai ffuston, dup Poly 8 dv) Meta). 5 She thinen «mask vegion trelude, m- diff, podiff 4 Avant channele, > Polyse & thinor reatorne Urrteract eo that a tvanutir is) formed thee they croce one another. 2 contacti formed — yj vting ayers, Zz sume paow ees CUCU, ee WE LOK aged, abo ond pely et deer » 5 Prpolar -trantstore addition of STICK DIAGRAMS : A stick — cdiagvar Tt vepresenti tectangles wires and component’ Represent ation ° co ud Colors, — Red? Poly Gren: n-defe Blue ! Metal Blok: Contact Yellows émplant extia de CnMog, design style). can be included dev deston by saver tb 4 CMoe procen, a LLr—— Jayout - with dines which tepreserit’ Symbol e, ry a ne dite —— p-iff metal 4 metal o- metal 3 contact implant. Cemos. cost Style) Red: Poly n- diff Yelloco: P- cleft Blue: Metal Black: Contact Green: 3 8 Te dy formect — wherever poly crosees déMfuston > Area and aspect ratio are diifhicult to estimate fron Stick Hiagrams . 2 Faster do design « 3 Aepostant tool for tayo, built From Jorge celle + testing connechom “blo celle. > A Stick dingrarn i interPace bho agmbe lic okt £ the actual dayout. + Often wed to slve wouting problems, > Ruled > When two or more Sticke ok Same type, ewee, of touch each other. Acpresent electiical contact. ae T (OD then two ot move. Sticks of Aikberent type. eee or touch each other there tis mo electrical corttact. ¥ cviad, © when Poly croaces ole ff, ib represents Moerer, mmo Peeign Style oe A tronsister dy formed wherwve poly crogces n-Aihf (red over gre) and alt dibbuston — Lotres interconnections) OAL oy type Cgpoen) - Daaw Mpp & gnd Aaih tn parallel using metal Clue) allo wing enough space blw them for other Cirentt elems , ex:-Qnmos tnvely ye 8 + (Fs ange PP C blue) foe a 4a] Chin. nf ry B ap" Shin a - crea) EY Vee toe Vee thine “eee a ? trplant: ty yellow. cme Design Site 5 logical extension ef Moe approach. 3 She two typs of tee usec WW’ & fp’ ae Separdled in the Shick dayouk by the. clermarealion dine above which all p~type daices are placect, the n- devices Cgreeny ane Plced below the. demarcation ine. and aw thus Jocatid un the p-well. ae ‘ (nmov) Pthpuston paths oust not croce the demarcation line and n-dihky & pediby wives rust mot joins nec he features au normally joined by meta) whee a Conneclicn da Tequired - v op . pp -4 wl, Wo i Cw) “yy ca s : Veo. More. Ezaraplee DO Ys BB Cnand Gate) mMos logic — Vo p Yop 6 SE if eal e Ly. Vee 7 bpp oo @.. “os soe “Wop 4 ie clenaredtion —, wine —_— vec é. Vic 9 Ye Bae CNoA). eee Yep a a Fa \ eT & oo ‘ : Veo DP ook caps logic Yap Vp 6 4c ] Swe i = Y. 6 — a a : a é o Moe a Y= he TCD emo Logic aa Pp ae oe pt = ta ——— 7 Pp _ : ° - Be 2)2 onc 00) Tyee ¥ Steiilaaly nme Logic . a tke coe GP YE AP . Ms . 5S) Ys Pte = FS a” ¢ 4 ‘pp & 4 os A D + 0 a i ~ mee Die |e ae - “og eo “5h A a7 x oe . ‘og Vee 6) Y= AlerAw Cxmer) ‘pp eee L b—® # for mos beafe: Replace Pull up with mos depletion mode tromixby with gale comnected Source, +) Sioatlarky yo alerag Cxox gated : y= +48) comnect tnvater te Olp of aor gala 8) ve Grae Mp A = bre a4 ~ ey Va 9° YS ABTE i 1 qe q al ba & a — p os _. + ig - A AG Re ; 0 a 0 ht oy 8 c Veo ro 4 design RULES and LAYOUT Design Audes allow the translation of clvoult dat, concep, vsually un &tiok diageoms Cr eymbolie. form into actual geometry in Silicon . 2 Design ules govern the. oyout of individual Companeil, and mteroction — spacings electrical connechion, bliy the component . 3 Detgn rales are. specibic to a particular semicondudsy manubactweng proces. St deteemince Low Level Prope of chip designs Chow smalt tndividuall logic. gates are mode, how small can the wires be), os orca component Sige ar possible ds desivest to imerease the m0, of Punchons in the chip. But fabrication ear ate such ax shoring tegether of wives, oy — abaence oly connection blu elves, Fouutty traniters ete. Design Furs wre eee Tote cre negs b= of cormmoon fabyication paoblems and to ore ete bring gid of corvect chips to acceptatle evel.” One of fabrication, parcblem ds thib a Utwe oy ony Recture- being made too wide or too anarow, A top Masao wie. Mary Never conduct or may busn of tshen conducting » A wide wire may Short itself with other wire, 3b poly etosses ov cul, difputon, then tt dh foamation |p oa mew element, Remedy 1D Bntredaction d- Spacing aules 2 Thioduclin, of onl ~ twidlth Fates. Min width vale: Gives min sige fos da yout element. St also emures thet even woth = intext — Variations , the elern will be of acceptable size. Spacing : aule;. Caver win distone bls the edaex a cle, So that even % “t * wee woth aninos vositachions ‘tb twill not cause the element dp verlap nearky Layout elem» - 9 wu compan sls Ensures that Component, a2 two formed. construchion, rales ¢viae) > Moteigl on beth clapere ato be extencl beyond Stor cit and nist Comectd rust weet ba at ben Scalable. Design Rules 9 Design mules can be cated im terme of y, tohich ts the Sige of the smallect elem in the Layout . . 5 When device, ehrink, tayouts meek not be comptletely redesigned . All eatutes can be measured tn integral multiples — > By choosin ao value for A, all dimencions gel ot a Scalable Layout . > Scalable Jayoute are odvaritogeous os chipe become faster as Size shvin kg, > Digital ckt designs scale, bieog the cap leads that rust be daiven by dogic gates shrink fastes than the Curvents eupplied by the Ts. [suming Chet the basic Physical paromtre of chip ene shrunk by a” factor of Y/,, Dye Length = Lb PUlgy Widthe ke > fy, 6 Thickness = D > Dix Supply vt > Vop-Me Opp-Vee'/, Deping oe Ra 5 iy! et Te tranconduclang : am= * Er Threshold veo = Sat Drain Current: The = kw Vge-Vi | + “de 2 YC Qe od ‘Kr MeoEing 2 k= Ka 7 ges ele “Sa, * « (Qo “3 x Ss) & ib Measure of speed of okt over eal ev/e vev/y oy. > Scaling te done on A 7 thus B -), J x (thas specd up by Lact Pie Destan vules fox wiree Cnmog & aS) g ee n- diff p- diff meted | va, UE. ~~ MMT» ? x » WA, WLLITZA MUTT 3+ cm: alee CaRbA implan ° Suxomaty : 9 Metal 22 ‘min-width = 3r amin- ep" = ep » Meta) 2 ! min - width = wh» main- Sep) = a) » Poly ? min - usidth: 2) ~~ rain poly- poly sep? = or 4 Pk 0 diffution: min widths or min sep? bli _ game diff ~ a cp) ee Ue lor wide, Min Separation blig tub & eve[daain= SA, Tab Te: tub tie + aaron cut, 4anlea metol, ae a "Nye one tuletie.. pt didf construction vues oe * D Tramisbrs * wotdth = 2A Length = 2A — extendg 2A beyond active re gion. 3) Diffusion extends ga. A) Adve tegion must be atleast 12 from poly- metal viay 2A frem another Tr, Ving ! > CatS: 2ax2r D Metesiol on both Layers extend \A tn al) LULU y via Sigez GARGD- “ toct Sep Fae cori cut to Tr Droplant for ie nmog dep modelv fe extend’ 2a min devend ch tm all direc’. Tr channel. AW wan Sep from am plant” te anethex Tr- Eatentiens & fepardtions (ws) Contact Cubs :- % says te make contacts bli poly & diffucion im mMog Ckt: (ty) poly te metal Gy did then wnetal t& diffusion buvied contact Cpoly & diff). butting contact ( poly te diff using metal ). the aawrr contoct cut indicates on area in which the oxide is to be temoved down te the underlying polygi or Afr o urface When deposition of metol layer ctokes place the metal is deposibe dA thre contact cubarusy ovo undealy inq arer 80 that covtact vs made blu ‘the Layers . eRe 1) Metalite PelySi ov te diffusion. Metal te poly. . mi —w- anwar? Cut centered en 4x4 superimposed eu, of lagers te be deined m all caces- pa (a VA Min Sep ; Multiple cdi zs 2X Nia Contact from metalo tb metal 1) viet fe 2 me sep? si] Cut x AXA arog of ovelop With 2x2 ela at ™etad) conf. Metale NoTe’ min ep) blio ompedefP" aire and poly wives 1A. oe ——r—C—CF= cule. fe 3 Contact cut typess cb Mp Adib te pelyst gp Poly tb metals CIV mp Ahh to metal | av) metal) ty metal o. Contact bluo poly2t and diffusion wiser can be clone nm ds boouye CO) Polyi_ to the metal and then metal to poly 8; % oxide us removed from 2ax2A contact cut down to underlying poly2t wire, Then metal us deposited. 4t flows then the oxide etched acon to polyst awn Shen polyse tb deposited on the Suiface, tshieh acti as conduction path. () Buxed Contact Before. stasting the paocen, there vin onide, Layer om Si gurkace, obide is etched to expose the tanderliging ot a ewhat ein Anmmeited om the Surkaco Cb UA CLA ee ALFIM takes place tmpe wil) tm the = mext Step; expsed ewrface. when diffure tl priate ell. os diffused area within the contacl area. eompec” bles satisfaclor: Buried contac ae Srmaltes Yi, emures oO CC contack « than butting «> trating Contacts > a Complex proces: > 2are2r . contact, te be jeimed, Layets Ue cut, — hecome ovelap & thin dn the athe” proces - cut iy made doum to each layers outlet ogether ¢ that contiguous ‘the poly & oxide undu poly two contact Poly & differed, Ate outlines ach, a Tork layers 0- butted ethe, . She contact blo too Layered then mode by metal overlay « I 7 Poly & RK I] 5 meted 4 ; LH iho MEL Douke TELAT ius pRuce eure dn tha pasces a Second metal ayer ta used £0 that Vop & Vac Cgndd rails im the Systery are. Aicbit bated mote. flexibly en the chip . vias are ured ‘to ectablish er ——r——C—C——=_—=_N connec She feat devet mmeta) ean be ued for local dlixtriludion, ol pow 4 for signal ines. CM0% = Lambda- bared destin cules . oo —.—.L.__— substrate contac are added te the existing Mog, wales, atm CMoe DESIGN RULES &2umM double metal, oubl poly > m- well! brown buried mb Sutscoll + pale are Polya : ved P- bare. & pink Poly 2. 3 Owange CMoe n-iffs Green P- ALPE & Yellow Bicmog. ade ae 3 ALIS = 92 p dP canst “eet scars.um } CFF tediff Separates suf 77Z, Te Lei Sur) (Mattie. Contact cui. (2) Via metal s/metal 2 >Buy + “J le Suny Ly, | D 1-Siuny Liraitations of Sealing @ (0 Subeali doping, d= [ee Gv Cishiwe Y= aN) oN, (2 Linn on enbniaburigalion ° wD Lemmits of imterconnect 2 contact vesttbance . (WD Limits due ty Subthseshold currents, @ lumi, = om dogic devele & Supply yo Umit due do Vt clue to noise , Cument density (= It am aan’ 2] / Examples : D Ner CInverter> Ypp ee * ee ire | * olp Olp “Se ~~ pte ke \sg ioe o deroarca line. Jip: poly °b: Metal Vop Vag! Mélal Metel- Blue Poly - Red. . nv deff — Gveer Via - Black. NOTE '- yia tyPes ? eo nIp diff - poly ci) metal 4. -metala Gi? Pely~ metal 2 (i) mp diffe — metals, Nie and OH Mogan hi out rok 1 Ss 1 (AB +C) Ye IIT) U f ee Sclny. Fadiers for device Paremetae O Gal frrea C9): Age Wek NEL Seah f by Ue a, Ag Scaled is ; af 2 Y Gate Cap Pa Umit Arer co oy oe Cont Cox = & ing D (4) Parasitic Capacitance Cz? Ce U Aa ad whee dd: Bepletion Uidth avound S4rD az a/y. Ax: Area of depletion Tegion eound Src or drain Aza Pa/ye. Qe Me 1 1 fe x2 din” KA D Camer Density t Channel Qoy: Son= Conrgs where Gent ang charge per unit area in ch én ‘on’ stale. Coy= Scaled by B Vas uw Up nN Qon* igen te Meee Gon D> @oen Scaled bg 4. () Channel Resistance Ron: Ren= bk. WY Gon Ae Wohere 44= Caomieyr mobility Ceongt). Ron Sealed by t--4..45 OD Gate Delay Ty. Ta a: Rem: Sg. ~ Ta AH 4: Ro»: P. AX N Tad, 8... + (D Max, Operating Frequency fo: f, = ee 14% Vop fo xt IL Th (D Saturation Cunvent Tyee. 2 Gna> JCal Gigs Veo a 1 yy by, Sealed by Vp &

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