DSD Dica Lab Manual

NARASARAOPETA ENGINEERING COLLEGE
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING
DSD & DICA LAB
LIST OF EXPERIMENTS
1. Realization of Logic Gates.

2. 3-to-8 decoder - IC 74138.
3. 8 x 1 multiplexer - IC 74151 and 2 x 4 de multiplexer IC 74155
4. 4-bit comparator - IC 7485
5. D-flip flop - IC 7474
6. Decade counter - IC 7490
7. 4-bit counter - IC 7493.
8. Shifts registers - IC 7495.
9. Universal shift registers - IC 74194/195.
10. RAM (16 x 4) IC 74189 (Read and Write operations ).
11. Stack and Queue implementation using RAM .
12. ALU Design.
WORKING WITH XILINX ISE 10.1
1. Entering the XILINX environment.
a. Click on XILINX ISE 10.1 icon on windows-XP desktop.
b. Click on OK button on tip of the day window.
2. Creating a new project
3. Adding a VHDL source file.
Select option add existing source in process window
Browse your VHDL source file and add it to your project.
4. Synthesizing.
Double click on your .vhd file in sources window and the file opens in editor
area.
Select synthesis/implementation option in sources for pull down menu on top
of sources window.
Double click on synthesize XST in process window.
Wait a moment to get process synthesis completed successfully prompt in
console window.
.
5. creating user constraints file(.ucf)
open user constraints in process window. Select assign package pins option.
Xilinx PACE window will be opened. assign pin numbers for your enetity and
save the file.
6. Generation programming file.
Open generate programming file option in process window.
Select configure device(impact) option right click on it, open properties
In properties window select standard for property display level.and select
boundary scan as configuration mode.
Again set advanced property display level specify port to be used
LPT1PC,Baud rate AUTO, click OK.
Select configure device(impact) option right click on it, select run option.
Now program downloaded into FPGA kit . verify the operation of the system applying
inputs from the appropriate inputs according to the system requirements
1. REALIZATION OF LOGIC GATES
AIM: To simulate and verify the truth tables of OR, AND, NOT, NAND, NOR and X-OR
gates.
APPARATUS:
1. Personal computer -1 no.
2. XILINX 10.1 software.
3. Spartan-3 FPGA trainer kit-1 no.
4. power supply- 1no.
5. boundary scan cable- 1no.
(1)AND gate:
PROGRAM:
Library IEEE;
Use ieee.std_logic_1164.all;
Entity and1 is
Port (a, b: in std_logic; y: out std_logic);
End and1;
Architecture and1 of and1 is
Begin
Y<= a and b;
End and1;
HARDWARE MODEL:
SYMBOL:
PIN DIAGRAM:
TRUTH TABLE:
INPUT OUT PUT

A B Y
0 0 0
0 1 0
1 0 0
1 1 1
AND gate: If two or more operands are ANDed, then the result will be logic 1 only if all
the operands are 1.A . Sign is used to represent the AND operation. If A and B are
the logic operands and Z is the result of the AND operation, then Z is 1(TRUE) only if
both A AND B are 1(TRUE). For all other combinations of the inputs, Z is 0(FALSE).
The expression for AND operation is given as Z=A . B.
SIMULATION OUTPUTS:
SYNTHESIS REPORT:
Final Results
RTL Top Level Output File Name : and1.ngr
Top Level Output File Name : and1
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs :3
Cell Usage :
# BELS :1
# LUT2 :1
# IO Buffers :3
# IBUF :2
# OBUF :1
TECHNOLOGY SCHEMATICS:
UCF for AND Gate:

NET a LOC = P76; #DIP 1
NET b LOC = P77; #DIP 2
NET c LOC = P16; # LED 1
RESULT: AND gate is synthesized and implemented on Spartan-3

FPGA .
(2) OR gate:
PROGRAM:
Library IEEE,
Entity or1 is
End or1;
Architecture or1 of or1 is
Begin
Y<= a or b;
End or1;
HARDWARE MODEL:
SYMBOL:
PIN DIAGRAM:
TRUTH TABLE:
INPUT OUT PUT

A B Y
0 0 0
0 1 1
1 0 1
1 1 1
OR gate: If two or more operands are ORed, then the result will be logic 1 if any of the
operands is a logic1. A + Sign is used to represent the OR operation. If A and B are
the logic operands and Z is the result of the OR operation, then Z is 1(TRUE) if either
A OR B is 1(TRUE). Z is 0(FALSE) only when both A and B are 0. The expression for
OR operation is given as Z=A + B.
SIMULATION OUTPUT:
SYNTHESIS REPORT:
Final Results
RTL Top Level Output File Name : or1.ngr
Top Level Output File Name : or1
Output Format : NGC
Keep Hierarchy : NO
Design Statistics
# IOs :3
Cell Usage :
# BELS :1
# LUT2 :1
# IO Buffers :3
# IBUF :2
# OBUF :1
UCF for OR Gate:
RESULT: OR gate is simulated and verified.
(3) NOT gate:
PROGRAM:
Library IEEE,
Entity not is
Port (a: in std_logic; y: out std_logic);
End not1;
Architecture not1 of not1 is
Begin
Y<= not a;
End not1;
HARDWARE MODEL:
SYMBOL:
PIN DIAGRAM:
TRUTH TABLE:
INPUT OUT PUT

A Y
0 1
1 0
NOT gate: The NOT operation corresponds to complementing the input variable. In
this there could be only one input and one output and the output is NOT the input. If
the input is 1 (TRUE) then the output is 0 (FALSE) and if the input is 0 (FALSE), the
output is 1 (TRUE). The NOT operation is given by the expression Z = .
SIMULATION OUTPUTS:
SYNTHESIS REPORT:
Final Results
RTL Top Level Output File Name : not1.ngr
Top Level Output File Name : not1
Output Format : NGC
Keep Hierarchy : NO
Design Statistics
# IOs :2
Cell Usage :
# BELS :1
# INV :1
# IO Buffers :2
# IBUF :1
# OBUF :1
UCF for NOT Gate:
RESULT:NOT gate is simulated and verified.
(4) NAND gate:
PROGRAM:
Library IEEE,
Entity nand1 is
End nand1;
Architecture nand1 of nand1 is
Begin
Y<= a nand b;
End nand1;
HARDWARE MODEL:
SYMBOL:
PIN DIAGRAM:
TRUTH TABLE:
INPUT OUT PUT

A B Y
0 0 1
0 1 1
1 0 1
1 1 0
NAND gate: NAND gate is the gate indicating NOT AND i.e., the output of the NAND
gate will be the complement of the output of the AND gate. This is shown in the above
table. In the table, A and B are the inputs, Y corresponds to the output of an AND gate
and Z corresponds to the output of a NAND gate. It can be seen that the output of the
NAND gate is the complement of that of the AND gate. The NAND operation is given
by the expression Z = A . B.
SIMULATION OUTPUTS:
SYNTHESIS REPORT:
Final Results
RTL Top Level Output File Name : nand1.ngr
Top Level Output File Name : nand1
Output Format : NGC
Keep Hierarchy : NO
Design Statistics
# IOs :3
Cell Usage :
# BELS :1
# LUT2 :1
# IO Buffers :3
# IBUF :2
# OBUF :1
UCF for NAND Gate:
RESULT: NAND gate is simulated and verified
(5) NOR gate:
PROGRAM:
Library IEEE,
Entity nor1 is
End nor1;
Architecture nor1 of nor1 is
Begin
Y<= a nor b;
End nor1;
HARDWARE MODEL:
SYMBOL:
PIN DIAGRAM:
TRUTH TABLE:
INPUT OUTPUT
A B Y
0 0 1
0 1 0
1 0 0
1 1 0
NOR gate: NAND gate is the gate indicating NOT OR i.e., the output of the
NOR gate will be the complement of the output of the OR gate. This is shown in the
above table. In the table, A and B are the inputs, Y corresponds to the output of an OR
gate and Z corresponds to the output of a NOR gate. It can be seen that the output of
the NOR gate is the complement of that of the OR gate. The NOR operation is given
by the expression Z = A + B.
SIMULATION OUTPUTS:
SYNTHESIS REPORT:
Final Results
RTL Top Level Output File Name : nor1.ngr
Top Level Output File Name : nor1
Output Format : NGC
Keep Hierarchy : NO
Design Statistics
# IOs :3
Cell Usage :
# BELS :1
# LUT2 :1
# IO Buffers :3
# IBUF :2
# OBUF :1
UCF for NOR Gate:

RESULT: NOR gate is simulated and verified.
(6) XOR gate:
PROGRAM:
Library IEEE,
Entity xor1 is
End xor1;
Architecture xor1 of xor1 is
Begin
Y<= a xor b;
End xor1;
HARDWARE MODEL:
SYMBOL :
PIN DIAGRAM:
TRUTH TABLE:
INPUT OUTPUT
A B Y
0 0 0
0 1 1
1 0 1
1 1 0
X-OR gate: The X-OR logic is different from other gates whose output is one, only
when the applied inputs are different i.e., it is an odd function and is one when it
contains odd number of ones.
So, at A=0, B=1 or A=1, B=0 the output of X-OR is 1.
SIMULATION OUTPUTS:
SYNTHESIS REPORT:
Final Results
RTL Top Level Output File Name : xor1.ngr
Top Level Output File Name : xor1
Output Format : NGC
Keep Hierarchy : NO
Design Statistics
# IOs :3
Cell Usage :
# BELS :1
# LUT2 :1
# IO Buffers :3
# IBUF :2
# OBUF :1
UCF for XOR Gate:

RESULT: XOR gate is simulated and verified.

2. D-FLIP FLOP IC 7474
AIM: Simulation and verification of D-FLIP FLOP using IC-74LS74A.
APPARATUS:

PROGRAM:
library ieee;
use ieee.std_logic_1164.all;
entity dff is
port(d,clk,pre_l,clr_l:in std_logic;q,qn:out std_logic);
end dff;
architecture dff1 of dff is
signal pre,clr:std_logic;
begin
process(clk,pre_l,pre,clr_l,clr)
begin
pre<=not pre_l; clr<=not clr_l;
if(clr='1' and pre='0')then q<='0';qn<='1';
elsif(pre='1'and clr ='0')then q<='1';qn<='0';
elsif( clk'event and clk='1')then q<=d;qn<=not d;
end if;
end process;
end dff1;
HARDWARE MODEL:
PIN DIAGRAM:
CIRCUIT DIAGRAM:
LOGIC DIAGRAM:
TRUTH TABLE:
THEORY:
The D flip-flop is also known as the Data flip-flop or the Delay flip-flop. It is used
to either store the data or introduce a delay. If a 0 is given at Din ,then S is 0 and R
will be 1. This resets the flip-flop. If a 1 is given at Din, then S is 1 and R 0. This sets
the flip-flop. Thus we find that Dout is always equal to Din. Hence this flip-flop can be
used to store a binary digit. So it is known as the Data flip-flop. The D flip-flop can
also be clocked similar to the RS flip-flop. In the clocked D flip-flop Dout will be made
equal to Din only when the clock arrives. Thus the data bit is sent to the output after a
delay. Therefore, the D flip-flop is also known as the Delay flip-flop.
SIMULATION OUTPUTS:
SYNTHESIS REPORT:
Final Results
RTL Top Level Output File Name : dff.ngr
Top Level Output File Name : dff
Output Format : NGC
Keep Hierarchy : NO
Design Statistics
# IOs :6
Cell Usage :
# BELS :3
# INV :1
# LUT2 :2
# FlipFlops/Latches :2
# FDCP :2
# Clock Buffers :1
# BUFGP :1
# IO Buffers :5
# IBUF :3
# OBUF :2
UCF for D-FLIP FLOP:
NET clk LOC = P68; #PB 1
NET clr_1 LOC = P76; #DIP 1
NET pre_1 LOC = P77; #DIP 2
NET d LOC = P78; #DIP 3
NET q LOC = P16; # LED 1
NET qn LOC = P16; # LED 2
RESULT: D flip-flop is synthesized and verified.

3. DECADE COUNTER IC 7490
AIM: Simulation and verification of DECADE COUNTER using IC-7490.
APPARATUS:

PROGRAM:
library ieee;
use ieee.std_logic_unsigned.all;
entity dec is
port(clk,rst,st:in std_logic;cout:out std_logic_vector(3 downto 0));
end dec;
architecture dec of dec is
signal ci:std_logic_vector(3 downto 0):="0000";
begin
process (clk)
begin
if rst='1' then ci<="0000";
elsif st='1' then ci<="1001";
elsif(clk'event and clk='1') then
ci<=ci+'1';
if(ci="1001")then ci<="0000";
end if;end if;end process;cout<=ci;end dec;
HARDWARE MODEL:
PIN DIAGRAM:
LOGIC SYMBOL:
OBSERVATIONS:
Decimal
QD QC QB QA Equivalent
output
0 0 0 0 0
0 0 0 1 1
0 0 1 0 2
0 0 1 1 3
0 1 0 0 4
0 1 0 1 5
0 1 1 0 6
0 1 1 1 7
1 0 0 0 8
1 0 0 1 9
THEORY:
The decade counter (mod-10 counter) is used most often. In order to count from
0 through 9, a counter with 3 flip-flops is not sufficient. With 4 flip-flops one can count
from 0 to15 (16 states). Out of these 16 states, we should skip any 6 states. In the
decade counter, when the output is 1010(for the 10 th clock pulse), all the flip-flops
should be reset. Thus the outputs Q3 and Q1 are given directly to the inputs of the AND
gate and the outputs Q2 and Q0 are given through inverters. Therefore, for the 10th
clock pulse, the counter output would be 1010 for a moment. This sends the output of
the AND gate to HIGH clearing all the flip-flops. Thus a decade counter has been
developed.
SIMULATION OUTPUTS:
SYNTHESIS REPORT:
Final Results
RTL Top Level Output File Name : dec.ngr
Top Level Output File Name : dec
Output Format : NGC
Keep Hierarchy : NO
Design Statistics
# IOs :7
Cell Usage :
# BELS :4
# INV :1
# LUT3_L :1
# LUT4_L :2
# FDC :4
# Clock Buffers :1
# BUFGP :1
# IO Buffers :5
# IBUF :1
# OBUF :4
TECHNOLOGY ASCHEMATICS:
UCF for Decade Counter:

NET rst LOC = P76; #DIP 1
NET st LOC = P77; #DIP 2
NET cout(3:0) LOC = P16, P18,P19,P20; #LED 1:4
RESULT: Decade counter is synthesized and verified.

4. 4 - BIT COUNTER IC 7493
AIM : Simulation and verification of 4 BIT COUNTER using IC-7493.
APPARATUS:

PROGRAM:
library ieee;
use ieee.std_logic_unsigned.all;
entity bit4 is
port(clk,rst:in std_logic;cout:out std_logic_vector(3 downto 0));
end bit4;
architecture bit4 of bit4 is
signal ci:std_logic_vector(3 downto 0):="0000";
begin
process (clk)
begin
if rst='1' then ci<="0000";
elsif(clk'event and clk='1') then
ci<=ci+'1';
end if;
end process;
cout<=ci;
end bit4;
HARDWARE MODEL:
PIN DIAGRAM:
LOGIC SYMBOL:
FUNCTION TABLE:
Decimal
QD QC QB QA Equivalent
output
0 0 0 0 0
0 0 0 1 1
0 0 1 0 2
0 0 1 1 3
0 1 0 0 4
0 1 0 1 5
0 1 1 0 6
0 1 1 1 7
1 0 0 0 8
1 0 0 1 9
1 0 1 0 10
1 0 1 1 11
1 1 0 0 12
1 1 0 1 13
1 1 1 0 14
1 1 1 1 15
THEORY:
4-bit counter is designed using 4 flip-flops. With 4 flip-flops one can count from
0 to15 (16 states). In the 4-bit counter, when the output is 1111(for the 16th clock
pulse), all the flip-flops should be reset. Therefore, for the 16th clock pulse, the counter
output would be 1111 for a moment. This sends the output of the AND gate to HIGH
clearing all the flip-flops. Thus a 4-bit counter has been developed.
SIMULATION OUTPUTS:
SYNTHESIS REPORT:
Final Results
RTL Top Level Output File Name : bit4.ngr
Top Level Output File Name : bit4
Output Format : NGC
Keep Hierarchy : NO
Design Statistics
# IOs :6
Cell Usage :
# BELS :4
# INV :1
# LUT2_L :1
# LUT3_L :1
# LUT4_L :1
# FDC :4
# Clock Buffers :1
# BUFGP :1
# IO Buffers :5
# IBUF :1
# OBUF :4
UCF for 4-Bit Counter:
NET rst LOC = P76; #DIP 1
RESULT: 4- bit counter is simulated and verified.

5. SHIFT REGISTERS IC 7495
AIM: Simulation and verification of SHIFT REGISTER usingIC-7495A.
APPARATUS:

PROGRAM:
library ieee;
entity shiftregister is
port(clk,sein,mode:in std_logic;
pllin:in std_logic_vector(3 downto 0);
cout:out std_logic_vector(3 downto 0));
end shiftregister;
architecture sr of shiftregister is
signal cout1:std_logic_vector(3 downto 0);
begin
process (clk)
begin
if (mode='1' )then cout1<=pllin;
elsif (mode='0')then
cout1(0)<= cout1(1);cout1(1)<= cout1(2);cout1(2)<= cout1(3);
(3)<= cout1sein;
else
cout1<="0000" ;
end if;end process;cout<=cout1;end sr;
HARDWARE MODEL:
PIN DIAGRAM:
CIRCUIT DIAGRAM:
THEORY:
A shift register is an n-bit register with a provision for shifting its stored data by
one bit position at each tick of the clock. The serial input, SERIN, specifies a new bit to
be shifted into one end at each clock tick. This bit appears at the serial output,
SEROUT, after n clock ticks, and is lost one tick later. Thus, an n-bit serial-in, serial-
out shift register can be used to delay a signal by n clock ticks.
A serial-in, parallel-out shift register has outputs for all of its stored bits, making
them available to other circuits. Such a shift register can be used to perform serial-to-
parallel conversion.
Conversely, it is possible to build a parallel-in, serial-out shift register. At each
clock tick the register either loads new data from inputs 1D-ND or it shifts its current
contents, depending on the value of the LOAD/SHIFT control input. The device uses a
2-input multiplexer on each flip-flops D input to select between the two cases. A
parallel-in, serial-out shift register can be used to perform parallel-to-serial conversion.
By providing outputs for all of the stored bits in a parallel-in shift register, we
obtain the parallel-in, parallel-out shift register. Such a device is general enough to be
used in any of the applications of the previous shift registers.
SIMULATION OUTPUTS:
SYNTHESIS REPORT:
Final Results
RTL Top Level Output File Name : shiftreg.ngr
Top Level Output File Name : shiftreg
Output Format : NGC
Keep Hierarchy : NO
Design Statistics
# IOs : 11
Cell Usage :
# BELS :4
# LUT3 :1
# LUT3_L :3
# FD :5
# Clock Buffers :1
# BUFGP :1
# IO Buffers : 10
# IBUF :6
# OBUF :4
UCF for shift regester:
NET pllin(3:0) LOC = P76; p77;p80;p81 #DIP 1:4
NET mode LOC = P82; #DIP 5
NET sein LOC = P83; #DIP 6
RESULT: shift register is synthesized and verified

6. UNIVERSAL SHIFT REGISTERS IC 74194/195
AIM: Simulation and verification of UNIVERSAL SHIFT REGISTER using
IC-74194.
APPARATUS:

PROGRAM:
Library ieee;
entity usr is
port(clk,clrbr,ls,rs:in std_logic;pllin:in std_logic_vector(3 downto 0);
modein:in std_logic_vector(1 downto 0);outvalue:out std_logic_vector(3
downto 0));
end usr;
architecture usr of usr is
signal clr:std_logic;
signal outvalue1:std_logic_vector(3 downto 0);
begin
process (clk,clr)
begin
clr<=not clrbr;
if (clr='1')
then outvalue1<="0000";
else
if (clk'event and clk='1') then
If modein="11" then
outvalue1<=pllin;
elsif (modein ="01" ) then
outvalue1(0)<= outvalue1(1);outvalue1(1)<= outvalue1(2);
outvalue1(2)<= outvalue1(3);outvalue1(3)<= rs;
elsif( modein ="10") then
outvalue1(3)<= outvalue1(2);outvalue1(2)<= outvalue1(1);
outvalue1(1)<= outvalue1(0);outvalue1(0)<= ls;
else
outvalue1<=outvalue1;end if;end if;end if;end
process;
outvalue<=outvalue1;
end usr;
LOGIC SYMBOL:
TRUTH TABLE:
THEORY:
The 74x194 is an MSI 4-bit bidirectional shift register. This is a parallel-in,
parallel-out shift register. Ordinary (uni-directional) shift registers shift the data in only
one direction (i.e. either left or right). Shifting left means shifting the data from QD to
QA. Shifting right means shifting the data from QA TO QD. But this 74x194 universal
shift register will shift the data in both the directions based on the status of the control
inputs S0, S1. The status of these control inputs for different operations is shown in
the tabular form. CLK input synchronizes the shift operation with different peripherals.
CLR input clears the operation of the shift register. LIN works as serial input for shift
left operation. RIN acts as serial input for shift right operation. A, B, C, D is the parallel
input lines. QA, QB, QC, QD are called parallel output lines.
SIMULATION OUTPUTS :
SYNTHESIS REPORT:
Final Results
RTL Top Level Output File Name : usr.ngr
Top Level Output File Name : usr
Output Format : NGC
Keep Hierarchy : NO
Design Statistics
# IOs : 14
Cell Usage :
# BELS : 13
# INV :1
# LUT3 :1
# LUT3_L :7
# MUXF5 :4
# FDC :4
# Clock Buffers :1
# BUFGP :1
# IO Buffers : 13
# IBUF :9
# OBUF :4
TECHNOLGY SCHEMATICS:
UCF for universal shift regester:

NET pllin(3:0) LOC = P76; p77;p80;p81 #DIP 1:4
NET mode(1:0) LOC = P82; p83 #DIP 5,6
NET sein LOC = P84; #DIP 7
RESULT: Universal shift register is synthesized and verified.

7. 3-TO-8 DECODER IC 74138
AIM: Simulation and verification of 3-8 DECODERS using IC-74138.
APPARATUS:

PROGRAM:
library ieee;
entity dec38 is
port(e1,e2,e3:in std_logic;
a:in std_logic_vector(2 downto 0);
cout:out std_logic_vector(7 downto 0));
end
dec38;
architecture dec38 of dec38 is
signal cout1:std_logic_vector(7 downto 0);
begin
process(a,e1,e2,e3)
begin
if( not e1 and not e2 and e3) ='1'
then
cout1<="11111111";
else
case a is
when "000"=> cout1<="01111111";
when "001"=> cout1<="10111111";
when "010"=> cout1<="11011111";
when "011"=> cout1<="11101111";
when "100"=> cout1<="11110111";
when "101"=> cout1<="11111011";
when "110"=> cout1<="11111101";
when "111"=> cout1<="11111110";
when others=>cout1<="11111111";
end case;
end if;
end process;
cout<=cout1;
end dec38;
HARDWARE MODEL:
PIN DIAGRAM:
LOGIC DIAGRAM:
OBSERVATIONS:
THEORY:
Decoder is the combinational circuit which contains n input lines to 2 n output

lines. The decoder is used for converting the binary code into the octal code. The
IC74138 is the 3*8 decoder which contains three inputs and eight outputs and also
three enables out of them two are active low and one is active high. Decoders are
used in the circuit where required to get more outputs than that of the inputs which
also used in the chip designing process for reducing the IC chip area.
SYNTHESIS REPORT:
Final Results
RTL Top Level Output File Name : dec38.ngr
Top Level Output File Name : dec38
Output Format : NGC
Keep Hierarchy : NO
Design Statistics
# IOs : 14
Cell Usage :
# BELS : 10
# LUT3 :8
# LUT4 :2
# IO Buffers : 14
# IBUF :6
# OBUF :8
UCF for universal shift regester:

NET a(2:0) LOC = P76; p77 #DIP 1:2
NET e1 LOC = p80; #DIP 3
NET e2 LOC = P81; #DIP 4
NET e3 LOC = P82; #DIP 5
NET cout(7:0) LOC = P16, P18,P19,P20;p21,p22,p23,p24 #LED 1:8
RESULT: 3-8 DECODERS using IC-74138 is synthesized and verified.

8. 4 - BIT COMPARATOR IC 7485
AIM: Simulation and verification of 4 BIT COMPARATOR using IC-7485.
APPARATUS:

PROGRAM:
library ieee;
use ieee.std_logic_arith.all;
entity cmp4 is
port(a,b:in std_logic _vector(3 downto 0);
a_gt_b,a_eq_b,a_lt_b: out std_logic);
end cmp4;
architecture cmp4 of cmp4 is
begin
process(a,b)
begin
if(a>b) then
a_gt_b<='1';
a_lt_b<='0';
a_eq_b<='0';
elsif(a<b)then
a_gt_b<='0';
a_lt_b<='1';
a_eq_b<='0';
else
a_gt_b<='0';
a_lt_b<='0';
a_eq_b<='1';
end if;
end process;
end cmp4;
HARDWARE MODEL:
PIN DIAGRAM:
LOGIC DIAGRAM:
FUNCTION TABLE:\
THEORY:
Comparing two binary words for equality is a commonly used operation in

computer systems and device interfaces. A circuit that compares two binary words and
indicates whether they are equal is called a comparator. Some comparators interpret
their input words as signed or unsigned numbers and also indicate an arithmetic
relationship (greater or less than) between the words. These devices are often called
magnitude comparators. A 1-bit Comparator is designed using Ex-OR and Ex-NOR
gates. The outputs of 4 XOR gates are ORed to create a 4-bit comparator. The IC
7485 is 4-bit magnitude comparator. With respect to the 8 inputs 3 inputs are
cascaded inputs. After the 8 input operations are performed further the outputs are
based on the cascaded inputs.
SYNTHESIS REPORT:
Final Results
RTL Top Level Output File Name : cmp4.ngr
Top Level Output File Name : cmp4
Output Format : NGC
Keep Hierarchy : NO
Design Statistics
# IOs : 11
Cell Usage :
# BELS :7
# LUT3 :3
# LUT4 :4
# IO Buffers : 11
# IBUF :8
# OBUF :3
UCF for 4-bit comparator:
NET a(3:0) LOC = P76; p77,p78,p80 #DIP 1:4
NET b(3:0) LOC = p80;p81,p85,p86,p87 #DIP 5:8
NET a_gt_b LOC = P16 #LED 1
NET a_lt_b LOC = P18 #LED 2
NET a_eq_b LOC = P19 #LED 3
RESULT: 4 BIT COMPARATOR using IC-7485 is simulated and verified.

9. 8 x 1 MULTIPLEXER IC 74151 AND
2x4 DEMULTIPLEXER IC 74155
AIM: (A) Simulation and verification of 8*1 MULTIPLEXER using IC-74150.

(B) Simulation and verification of 2x4 DE MULTIPLEXER using IC-74155.
APPARATUS:
(A). PROGRAM: 8 x 1 MULTIPLEXER
library ieee;
entity mux8 is
port(a,b,c,d,e,f,g,h,strobe:in std_logic;
ds:in std_logic_vector(2 downto 0);
z:out std_logic);
end mux8;
architecture mux8 of mux8 is
signal z1 : std_logic;
begin
process(strobe,a,b,c,d,e,f,g,h,ds)
begin
if strobe='1' then z1<='1';
elsif strobe='0' then
case ds is
when "000"=>z1<=not a;
when "001"=>z1<=not b;
when "010"=> z1<=not c;
when "011"=> z1<=not d;
when "100"=> z1<=not e;
when "101"=> z1<=not f;
when "110"=> z1<=not g;
when "111"=> z1<=not h;
when others=>z1<='1';
end case;end if;
end process;
z<=z1;
end mux8;
HARDWARE MODEL:
PIN DIAGRAM
LOGIC DIAGRAM;
TRUTH TABLE:
THEORY:
A multiplexer is a digital switch- it connects data from one of n sources to its

output. An 8*1 is multiplexer consists of 3 input lines as select lines and 8 input lines
and 1 output line. A multiplexer is a unidirectional device which follows the data from
input lines to output lines. Multiplexers are obviously useful device in any application in
which data must be multiple source to destination. A common application in computers
is the mux between the processors registers and its ALU.
SYNTHESIS REPORT
Final Results
RTL Top Level Output File Name : mux8.ngr
Top Level Output File Name : mux8
Output Format : NGC
Keep Hierarchy : NO
Design Statistics
# IOs : 13
Cell Usage :
# BELS :6
# LUT4 :6
# IO Buffers : 13
# IBUF : 12
# OBUF :1
UCF for 8X1 multiplexer:

NET a,b,c,d,e,f,g,h,strobe LOC = P76; p77,p78,p80; p81,p85,p86,p87 #DIP 1:8
NET ds(2:0) LOC = p90;p93, #DIP 9,10
NET z LOC = P16 #LED 1
RESULT: 8*1 MULTIPLEXER using IC-74150 is simulated and verified

(A). PROGRAM: 2x4 DE MULTIPLEXER
library ieee;
entity demux24 is
port(a:in std_logic;
sel:in std_logic_vector(1 downto 0);
y0,y1,y2,y3:out std_logic);
end demux24;
architecture demux of demux24 is
begin
process(a,sel)
begin
case sel is
when "00"=>y0<=a;y1<='0';y2<='0';y3<='0';
when "01"=>y1<=a;y0<='0';y2<='0';y3<='0';
when "10"=>y2<=a;y1<='0';y0<='0';y3<='0';
when "11"=>y3<=a;y1<='0';y2<='0';y0<='0';
when others=>y0<='0';y1<='0';y2<='0';y3<='0';
end case;
end process;
end demux;
SIMULATION OUTPUTS:
SYNTHESIS REPORT:
Final Results
RTL Top Level Output File Name : demux24.ngr
Top Level Output File Name : demux24
Output Format : NGC
Keep Hierarchy : NO
Design Statistics
# IOs :7
Cell Usage :
# BELS :4
# LUT3 :4
# IO Buffers :7
# IBUF :3
# OBUF :4
UCF for 2X4 De multiplexer:

NET sel(1:0) LOC = P76; p77 #DIP 1:2
NET a LOC = P78 #DIP 3
NET y0,y1,y2,y3 LOC = P16; P18;P19;P20 #LED 1:4
RESULT: 2X4 DE MULTIPLEXER using IC-74155 is synthesized and verified

10.RAM (16 x 4) IC 74189 (Read and Write operations)
AIM: To Perform Read And Write Operations On 16x4 Random Access

Memory(Ram)
APPARATUS:
PROGRAM :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity RAM1 is
port ( clk : in std_logic;
enr : in std_logic; --enable read,should be '0' when not in use.
enw : in std_logic; --enable write,should be '0' when not in use.
addr_in : in std_logic_vector( 3 downto 0);
addr_out : in std_logic_vector( 3 downto 0);
dataout : out std_logic_vector(3 downto 0); --output data
datain : in std_logic_vector (3 downto 0) --input data
);
end RAM1;
architecture ram of RAM1 is
type memory_type is array (0 to 15) of std_logic_vector(3 downto 0);
signal mem : memory_type ;
begin
process (clk)
begin
if clk'event and clk = '1' then
if (enw = '1') then
mem( conv_integer( addr_in)) <= datain ;
elsif(enr ='1') then
dataout <= mem( conv_integer( addr_out)) ;
end if ;
end if;
end process;
end ram;
HARDWARE MODEL:
PIN DIAGRAM:
CIRCUIT DIAGRAM:
SIMULATION OUTPUTS:
SYNTHESIS REPORT:
Final Results
RTL Top Level Output File Name : ram1.ngr
Top Level Output File Name : ram1
Output Format : NGC
Keep Hierarchy : NO
Design Statistics
# IOs : 19
Cell Usage :
# BELS :4
# GND :1
# LUT2 :2
# VCC :1
# RAMS :1
# RAMB16_S4_S4 :1
# Clock Buffers :1
# BUFGP :1
# IO Buffers : 18
# IBUF : 14
# OBUF :4
UCF for 16x4 RAM:

NET addr_in(3:0) LOC = P76; p77; P78;P80 #DIP 1:4
NET addr_out(3:0) LOC = P16; p18; P19;P20 #LED 1:4
NET data_in(3:0) LOC = P81; p85; P86;P87 #DIP 5:8
NET data_out(3:0) LOC = P21; p22; P24;P26 #LED 5:8
NET clk LOC= p68 #PB1
NET enr LOC =P90 #DIP9
NET enw LOC =P93 #DIP10
RESULT: 16x4 RAM is synthesized read and write operations are verified .

DSD Dica Lab Manual

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NARASARAOPETA ENGINEERING COLLEGE

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

DSD & DICA LAB

1. Realization of Logic Gates.

INPUT OUT PUT

UCF for AND Gate:

RESULT: AND gate is synthesized and implemented on Spartan-3

INPUT OUT PUT

RESULT: OR gate is simulated and verified.

(3) NOT gate:

INPUT OUT PUT

RESULT:NOT gate is simulated and verified.

(4) NAND gate:

INPUT OUT PUT

RESULT: NAND gate is simulated and verified

(5) NOR gate:

UCF for NOR Gate:

RESULT: NOR gate is simulated and verified.

(6) XOR gate:

UCF for XOR Gate:

RESULT: XOR gate is simulated and verified.

AIM: Simulation and verification of D-FLIP FLOP using IC-74LS74A.

1. Personal computer -1 no.

RESULT: D flip-flop is synthesized and verified.

1. Personal computer -1 no.

UCF for Decade Counter:

RESULT: Decade counter is synthesized and verified.

1. Personal computer -1 no.

RESULT: 4- bit counter is simulated and verified.

1. Personal computer -1 no.

RESULT: shift register is synthesized and verified

1. Personal computer -1 no.

UCF for universal shift regester:

RESULT: Universal shift register is synthesized and verified.

1. Personal computer -1 no.

Decoder is the combinational circuit which contains n input lines to 2 n output

UCF for universal shift regester:

RESULT: 3-8 DECODERS using IC-74138 is synthesized and verified.

AIM: Simulation and verification of 4 BIT COMPARATOR using IC-7485.

1. Personal computer -1 no.

Comparing two binary words for equality is a commonly used operation in

RESULT: 4 BIT COMPARATOR using IC-7485 is simulated and verified.

AIM: (A) Simulation and verification of 8*1 MULTIPLEXER using IC-74150.

(A). PROGRAM: 8 x 1 MULTIPLEXER

A multiplexer is a digital switch- it connects data from one of n sources to its

UCF for 8X1 multiplexer:

RESULT: 8*1 MULTIPLEXER using IC-74150 is simulated and verified

UCF for 2X4 De multiplexer:

RESULT: 2X4 DE MULTIPLEXER using IC-74155 is synthesized and verified

AIM: To Perform Read And Write Operations On 16x4 Random Access

UCF for 16x4 RAM:

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