VIGNANA JYOTHI GROUP OF

INSTITUTIONS

7 HABITS OF SUCCESSFUL PEOPLE

Be Proactive
Begin With The End In Mind
Put First Things First
Think Win-Win
Seek First To Understand, Then To Be Understood
Synergize
Sharpen The Saw

I have followed the above 7 steps during the course of our project work.

D.NITHISH - 13071A04G2

i
 DESIGN OF GOLAY ENCODER AND DECODER
(23, 12, 7)
A MAJOR PROJECT REPORT

SUBMITTED IN PARTIAL FULFILMENT OF THE REQUIREMENTS FOR THE

AWARD OF THE DEGREE

BACHELOR OF TECHNOLOGY

IN

ELECTRONICS & COMMUNICATION ENGINEERING

SUBMITTED BY

D.NITHISH -- 13071A04G2

UNDER THE GUIDANCE OF

Mrs.G.SHANTHI

ASSISTANT PROF.

DEPT. OF E.C.E

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

VNR VIGNANA JYOTHI INSTITUTE OF ENGINEERING & TECHNOLOGY

(Approved By AICTE and Affiliated to JNTU, HYD)

Bachupally, Hyderabad.

2013-2017

ii
 DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

VNR VIGNANA JYOTHI INSTITUTE OF ENGINEERING & TECHNOLOGY

(Approved By AICTE and Affiliated to JNTU, HYD)

CERTIFICATE

This is to certify that the thesis entitled DESIGN OF GOLAY (23, 12, 7)

ENCODER AND DECODER that is being submitted by Mr.D.Nithish

(13071A04G2) in partial fulfilment for the award of B.Tech degree in Electronics &
communication of the VNR VJIET, Hyderabad during the academic year 2013-2017 is a
record of bonafide work carried out by him under our guidance and supervision.
The results embodied in this thesis have not been submitted to any other university or
institute for the award of any degree or diploma.

Supervisor Head of Department

Mrs.G.Shanthi Dr.Y.Padmasai

Assistant Prof. Professor and Head of Department

Dept. of E.C.E Dept. of E.C.E

iii
 DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

VNR VIGNANA JYOTHI INSTITUTE OFENGINEERING & TECHNOLOGY

(Approved By AICTE and Affiliated to JNTU, HYD)

DECLARATION

I do declare that the thesis work entitled DESIGN OF GOLAY (23, 12,7)

ENCODER AND DECODER submitted in the department of Electronics and

Communication Engineering (ECE), Vallurupalli Nageswara Rao Vignana Jyothi
Institute of Engineering and Technology, Hyderabad, in partial fulfilment of the
requirement for the award of the degree of Bachelor of Technology in Electronics &
Communication is a bonafide record of my own work carried out under the supervision
of Mrs.G.Shanthi, Assistant Professor.

Also, I declare that the matter embodied in this thesis has not been submitted by me in
full or in any part for the award of any degree/diploma of any other institution or
university previously.

Place: Hyderabad Date:

D.NITHISH

iv
 ACKNOWLEDGEMENT
Its a great privilege for me to present this major project. I would like to take this
opportunity to thank those who made this endeavour a success.

I am thankful to Dr.D.N. RAO, President, VNRVJIET and Dr.C.D. NAIDU, principal,

VNR VJIET, Hyderabad for giving me permission to carry out this project.

I would like to express my sincere gratitude to Dr.Y.Padmasai (H.O.D) Dept. of E.C.E

for giving this opportunity to do this project.

I am highly indebted to Mrs.G.Shanthi for her guidance and constant supervision as well
as for providing necessary information regarding the project & also for her support in
completing the project.

I would like to thank our VNRVJIET faculty for valuable suggestions and guide lines
given by them during the execution of this documentation. I would also like to thank the
teaching, non teaching staff and also those who have directly or indirectly helped in
completion of this project and document.

Above all I pay my sincere gratitude to parents and my friends who blessed me with
patience and vigour to complete this document with full efficiency.

D.NITHISH - 13071A04G2

v
 ABSTRACT

Research using Error Detection and Correction techniques is very important and widely
used for the last five decades. It has attracted the interest of researchers in many domains
like aviation technology, computer science Engg. Data base Management systems. The
Golay code addresses error correction phenomena. Binary code (G23) is represented as
(23,12,7).Golay code plays a vital role in different applications like coded excitation for a
laser and ultrasound imaging due to the complete side lobe nullification property of
complementary Golay pair. All these applications need generation of Golay sequence,
which is fed as trigger to the laser modules. However, for generating Golay code an
automatic pattern generator is used, which is of very high cost. To combat this problem, a
hardware module programmed to yield a Golay encoded codeword may be used. Golay
decoder is used extensively in communication links for forward error correction.
Therefore, a high speed and high throughput hardware for decoder could be useful in
communication links for forward error correction.

This project describes about a type of error correcting code called binary Golay code (23,
12, 7) where 23 indicates the length of the codeword,12 indicates the number of message
bits and 7 indicates the minimum hamming distance between 2 code words. An error-
correcting code is a technique where the message is expressed in the form of numbers in
which the errors can be detected and corrected based on the pattern of the remaining
numbers. There are many methods for detecting the errors occurred after transmission,
whereas only few can correct them. Hamming codes and Golay codes are the technique
which helps in detecting and also correcting the errors in the code.Golay code is the only
code which can correct up to 3 errors.Golay codes are the perfect linear error correcting
codes which also helps to detect and correct the errors in the code. There are two types of
Golay codes binary Golay code (G23(23,12,7)) and ternary Golay code(G11(11,6,5) and
it is the unique code with these parameters. .

Golay Encoder encodes the message bits by adding parity bits in such a way that the last
12 bits are message bits and remaining 11 bits are parity bits. The encoding of the data is

vi
carried out using the generator matrix and decoding of the data is carried out using
Syndrome calculation. Syndrome is calculated using the parity check matrix. The
architecture will be authored in Verilog, will be synthesized, and implemented using
Xilinx ISE Foundation 10.1i. For Behavioral simulation, Place and Route simulation
Modesim6.0 is used.
We have designed the encoder and decoder using Verilog, matlab and we have compared
the results. Moreover we have synthesized the encoder using Xilinx ISE and analyzed the
RTL, Technology schematics, and Synthesis reports.

vii
 INDEX
CONTENTS PAGE NO.

CHAPTER 1
INTRODUCTION : 1-5

1.1Literature Survey : 1

1.2Need for Golay code : 2

1.3 Different Golay codes : 2-4

1.3.1 Binary Golay code : 2-3

1.3.2 Extended Binary Golay code : 3-4

1.3.3 Ternary Golay Code : 4

1.4 Objectives : 5

CHAPTER 2

TERMINOLOGY AND SOFTWARES USED : 6-17

2.1Generator Matrix : 6-7

2.2 Parity Check Matrix : 7-8

2.3 Introduction to Verilog : 9-13

2.3.1 Verilog History : 10

2.3.2 Types of Verilog : 10

2.3.3 Simulation and Debugging of Verilog Code : 10-11

2.3.4 Abstraction levels in Verilog Code : 12

2.3.5 Behavioural Level : 12

2.3.6 Register Transfer level : 12-13

2.3.7 Gate level : 13

2.3.8 Test Benches in Verilog : 13

viii
2.4 Introduction to Modelsim : 14-15

2.4.1 Features of Modelsim : 14-15

2.5 Introduction to Matlab : 15-16

2.5.1 Features of Matlab : 15-16

2.6 Introduction to Xilinx : 16-17

CHAPTER 3

GOLAY ENCODER AND DECODER : 18-22

3.1 Golay Encoder : 18

3.2 Codeword Generation : 18-19

3.3 Golay Decoder : 20-21

3.3.1 Procedure for Decoding : 20-21

3.4 Syndrome Computation : 22

3.4.1 Equations to compute Syndrome : 22

CHAPTER 4

RESULTS OF ENCODER AND DECODER : 23-28

4.1 Results of Encoder using Modelsim : 23

4.2 Results of Encoder using Matlab : 24

4.3 Synthesis Reports of Encoder : 25-26

4.4 Results of Decoder using Modelsim : 27

4.5 Results of Decoder using Matlab : 28

CHAPTER 5

CONCLUSION AND FUTURE SCOPE : 29

5.1 Conclusion : 29

5.2 Future Scope : 29

ix
BIBILIOGRAPHY : 30

APPENDIX-A : 31-39
A.1 Verilog Code for Encoder : 31

A.2 Verilog Code for Decoder : 32-36

A.3 Matlab Code for Encoder : 37

A.4 Matlab Code for Decoder : 38-39

x
LIST OF FIGURES PAGE NO.
1.1 Matrix B used for Generator Matrix : 4

1.2Process of Encoding and decoding the data : 5

2.1 Generator polynomial represented in matrix form : 6

2.2 Generator Matrix : 7

2.3 Parity check polynomial represented in matrix form : 7

2.4 Parity check Matrix : 8

2.5 Abstraction levels in Verilog : 12

3.1 Block diagram of Golay Encoder : 19

3.2 Block diagram of Golay Decoder : 20

xi
LIST OF TABLES PAGE NO.
1.1 Codeword format of Golay code : 3

3.1List of Syndromes Computed : 21

xii
 CHAPTER 1

1.1 Literature Survey:

Error detection and correction plays an important role in information theory. It enables
reliable transmission of digital data over noisy communication channel. In wireless
communication, when a message is transmitted from source to destination, data may get
distorted or corrupted by noise. Error detection involves detection of errors, whereas error
correction implicates restoration of original message. Redundant bits areadded to the data
bits at the time of transmission called as check bits. Forward error correction (FEC) codes
are of two types, namely block codes and convolution codes. Theblock code notation (n;
k; d) describes a block with length n, message with length k and the minimum hamming
distance between two code words is d. There are various types of block codes are
available. One of the most powerful known block code is the binary Golay code (23, 12,
7), represented as G23. This code was discoveredby M .J .E Golay in 1949 to address
error correction.

In the binary Golay code, 12 bits of data is encoded into 23 bits codeword in such a 3
errors can be corrected. Let G = [I;B] be the 12x23 matrix, where I and B are the 12x12
identity matrix and matrix over GF. Any linear code C with this generator matrix G is
called the binary Golay code (G23).

In addition, Golay Code plays a vital role in different applications like coded excitation
for a laser and ultrasound imaging due to the complete side lobe nullification property of
complementary Golay pair. All these applications need generation of Golay sequence,
which is fed as trigger to the laser modules. However, for generating Golay Code, an
automatic pattern generator is used, which is of very high cost. Golay decoder is used
extensively in communication links for forward error correction. Therefore, a high speed
and high throughput hardware for decoder could be useful in communication links for
forward error correction.

1
1.2 Need for Golay code:
In mathematics and electronics engineering, a binary Golay code is type of linear
Error-correcting code used in digital communications. The binary Golay code, along
with the ternary Golay code, has a particularly deep and interesting connection to the
theory of finite sporadic groups in mathematics. These codes are named in honor
of Marcel J. E. Golay whose 1949 paper introducing them has been called, by E. R.
Berlekamp, the "best single published page" in coding theory.
As Golay code has the ability of correcting up to 3 errors it can be used in areas where
the probability of errors is more. It is the only code which can correct up to 3 errors.

1.3 Different Golay codes:

There are different types of Golay codes. Some of them are

Binary Golay code
Extended Binary Golay code
Ternary Golay code

1.3.1 Binary Golay Code:

The binary form of the Golay code is one of the most important types of linear binary
block codes. It is of particular significance since it is one of only a few examples of a
nontrivial perfect code. A t-error-correcting code can correct a maximum of t errors. A
perfect t-error correcting code has the property that every word lies within a distance of t
to exactly one code word. Equivalently, the code has dmin = 2t + 1, and covering radius t,
where the covering radius r is the smallest number such that every word lies within a
distance of r to a codeword.

Two Golay codes do attain equality, making them perfect codes the (23, 12) binary code
with dmin = 7, and the (11, 6) ternary code with dmin = 5. Both codes have the largest
minimum distance for any known code with the same values of n and k. Only two other
codes achieve equality in the Hamming bound: the (2m 1 m) Hamming code with

2
dmin = 3, and the binary repetition code with two code words, one all 0s and one all
1s.Golay was in search of a perfect code when he noticed that

which indicated the possible existence of a (23, 12) perfect binary code that could correct
up to three errors. In 1949, Golay discovered such a perfect code, and it is the only one
known capable of correcting any combination of three or fewer random errors in a block
of 23 elements.

Table 1.1 codeword format of Golay code

1.3.2 Extended Binary Golay code:

Codes can be easily extended by adding an overall parity check to the end of each code
word. Let c be any (n, k) code whose minimum distance is odd. We can obtain a new (n +
1, k) code c 0 with the new minimum distance d 0 min = dmin + 1 by adding a 0 at the
end of each code word of even weight and a 1 at the end of each code word of odd
weight.

The (23, 12) Golay code can be extended by adding an overall parity check to each code
word to form the (24, 12) extended Golay code. This code can be generated by the 12 by
24 matrix G = [ I , B ] where I is the 12 by 12 identity matrix and B is the following
matrix:

3
Fig1.1 Matrix B used for Generator Matrix

This (24, 12) extended Golay code G has minimum distance dmin = 8 and has a code rate
of exactly R = 1 2 . The weight of every code word is a multiple of 4, and G is invariant
under a permutation of coordinates that interchanges the two halves of each code word.
Unlike the (23,12) code, the (24, 12) extended Golay code is not perfect, only quasi-
perfect, because all spheres of radius t are disjoint, but every vector is at most a distance
of t + 1 from some code vector. A quasi-perfect code is defined to be a code which for
some t has most vectors of weight t or less, a few of weight t + 1, and none of weight
greater than t + 1.

1.3.3 Ternary Golay code:

In addition to the binary Golay codes discussed previously, there are also ternary Golay
codes. The ternary (11, 6) Golay code is the only known perfect non binary code. The
(11, 6) Golay code over the Galois field with three elements GF(3) has minimum distance
of 5, and can correct up to two errors. As stated previously, like the (23, 12) binary Golay
code, the (11, 6) ternary code has the largest minimum distance dmin of any known code
with the same values of n and k. Also, like the (23, 12) binary code, the (11, 6) ternary
code can be extended by adding an overall parity check to form the extended (12, 6)
ternary Golay code. Like the extended (24, 12) code, the (12, 6) code is also unique.

4
1.4 Objectives:
To design a Golay encoder and decoder that can correct up to three errors.
Design a Golay decoder and encoder using verilog and Matlab
Compare the results of both decoders and encoders

Fig 1.2 Process of Encoding and Decoding the data

5
 CHAPTER 2

2.1 Generator matrix:

In coding theory, a generator matrix is a matrix whose rows form a basis for a linear
code. The code words are all of the linear combinations of the rows of this matrix, that is,
the linear code is the row space of its generator matrix. The generator polynomial g(x) of
C is a factor of x power(n) - 1 in GF(q)[x].The generator polynomial g(x) forms a kn
generator matrix G, that is

Fig 2.1 Generator polynomial represented in matrix form

The generator polynomial of (23, 12, 7) Golay code is:g(x)=x11+x9 +x7 +x6 +x5 +x +1

The degree of g(x) is r = 11, and the total entries of the1223generator matrix G are:

By using row operation in G, the systematic generatormatrix for this code is shown as
follows:

6
 Fig 2.2 Generator Matrix

P expresses parity check bits matrix, and Ik expresses identity matrix with k=12.This
generator matrix is used in the calculation of codeword.

2.2 Parity Check Matrix:

In coding theory, a parity-check matrix of a linear block code C is a matrix which

describes the linear relations that the components of a codeword must satisfy. It can be
used to decide whether a particular vector is a codeword and is also used in decoding
algorithms. The parity check polynomial kh(x) = h0 + h1x +..+ hk x power kwith the
degree of k=(n-r) is a factor of x^(n) 1, such that x^(n) 1=g(x)h(x). The (n-k)n parity
check matrix H is:

Fig 2.3 Parity check polynomial represented in matrix form

The parity check polynomial of (23, 12, 7) Golay code is h(x) = (x23 1) / g(x) = x12 +
x10 + x7 + x4 + x3 + x2 + x +1.The degree of h(x) is k=12, and the total entries of the 11
23 parity check matrix H is:

7
By using row operation in H, or transform [P | I k] into [I k | PT] from (4), where PT is
transpose matrix of P, is the systematic parity check matrix for this code is shown as
follows:

Fig 2.4 parity check Matrix

P expresses parity check bits matrix, and Ik expressesidentity matrix with k=12.This
Parity check matrix is used in the calculation of syndrome which determines the errors in
received codeword.

8
2.3 INTRODUCTION TO VERILOG:
Verilog is a portmanteau of the words "verification" and "logic"Verilog, standardized
as IEEE 1364, is a hardware description language (HDL) used to
model electronic systems. It is most commonly used in the design and verification
of digital circuits at the register-transfer level of abstraction. It is also used in the
verification of analog circuits and mixed-signal circuits, as well as in the design of
genetic circuits. Some of the softwares like Modelsim can be used for the debugging

Hardware description languages such as Verilog differ from software programming

languages because they include ways of describing the propagation time and signal
strengths (sensitivity). There are two types of assignment operators; a blocking
assignment (=), and a non-blocking (<=) assignment. The non-blocking assignment
allows designers to describe a state-machine update without needing to declare and use
temporary storage variables. Since these concepts are part of Verilog language semantics,
designers could quickly write descriptions of large circuits in a relatively compact and
concise form. At the time of Verilog introduction (1984), Verilog represented a
tremendous productivity improvement for circuit designers who were already using
graphical schematic capture software and specially written software programs to
document and simulate electronic circuits.

Syntactic differences include required bit-widths for variable declarations, Demarcation

of procedural blocks (Verilog uses begin/end instead of curly braces {} and many other
minor differences. Verilog requires that variables be given a definite size . In C these
sizes are assumed from the type of the variable (for instance an integer type may be 8
bits).

A Verilog design consists of a hierarchy of modules. Modules encapsulate Design

hierarchy, and communicate with other modules through a set of declared input, output,
and bidirectional ports. Internally, a module can contain any combination of the
following: net/variable declarations (wire, reg, integer, etc.), Concurrent and sequential
statement blocks, and instances of other modules (sub-hierarchies). Sequential statements
are placed inside a begin/end block and executed in sequential order within the block.

9
However, the blocks themselves are executed concurrently, making Verilog a dataflow
language.

2.3.1 VERILOG HISTORY:

Verilog was one of the first modernhardware description languages tobe invented.It
was created by PrabhuGoel and Phil Moorby between late1983 and early 1984. The
wording for this process was "Automated IntegratedDesign Systems" (later renamed
to Gateway Design Automation in 1985) as ahardwaremodeling language. Gateway
Design Automation was purchasedby Cadence Design Systems in 1990

2.3.2 TYPES OF VERILOG

With the increasing success of VHDL at the time, Cadence decided to make the language
available for open standardization. Some types of verilog are shown,

Verilog-95

Verilog 2001

Verilog 2005

System Verilog

2.3.3 SIMULATION AND DEBUGGING OF VERILOG CODE:

Essential to HDL design is the ability to simulate HDL programs. Simulation allow an
HDL description of a design (called a model) to pass design verification, an important
milestone that validates the design's intended function (specification) against the code
implementation in the HDL description. It also permits architectural exploration. The
engineer can experiment with design choices by writing multiple variations of a base
design, then comparing their behavior in simulation. Thus, simulation is critical for
successful HDL design.

10
 To simulate an HDL model, an engineer writes a top-level simulation environment
(called a test bench). At minimum, a testbench contains an instantiation of the
model(called the device under test or DUT), pin/signal declarations for the model's I/O,
and clock waveform. The test bench code is event driven: the engineer writes HDL
statements to implement the (test bench-generated) reset-signal, to model interface
transactions (such as a hostbus read/write), and to monitor the DUT's output. An HDL
simulator the program that executes the test bench maintains the simulator clock,
which is the master reference for all events in the test bench simulation. Events occur
only at the instants dictated by the test bench HDL (such as a reset-toggle coded into the
test bench),or in reaction (by the model) to stimulus and triggering events. Modern HDL
simulators have full-featured graphical user interfaces, complete with a suite of debug
tools.

These allow the user to stop and restart the simulation at any time, insert simulator
breakpoints (independent of the HDL code), and monitor or modify any element in the
HDL model hierarchy. Modern simulators can also link the HDL environment to user-
compiled libraries, through a defined PLI/VHPI interface. Linking is system-
dependent(Win32/Linux/SPARC), as the HDL simulator and user libraries are compiled
and linked outside the HDL environment.

Design verification is often the most time-consuming portion of the design process, due
to the disconnection between a device's functional specification, the designer's
interpretation of the specification, and the imprecision [citation needed] of the HDL
language. The majority of the initial test/debug cycle is conducted in the HDL simulator
environment, as the early stage of the design is subject to frequent and major circuit
changes. An HDL description can also be prototyped and tested in hardware
programmable logic devices are often used for this purpose. Hardware prototyping is
comparatively more expensive than HDL simulation, but offers a real-world view of the
design. Prototyping is the best way to check interfacing against other hardware devices
and hardware prototypes. Even those running on slow FPGAs offer much shorter
simulation times than pure HDL simulation.

11
2.3.4 ABSTRACTION LEVELS IN VERILOG:

Abstraction is defined as the hiding of information that is too detailed. It is therefore

necessary to differentiate between essential and non-essential information. Information
that is not important for the current view of the problem will be left out from the
description. Abstraction levels are characterized by the kind of information that is
common to all models of this level. A model is said to be of a certain abstraction level if
every module has the same degree of abstraction.

Fig 2.5 Abstraction levels in Verilog

2.3.5 BEHAVIOURAL LEVEL:

This level describes a system by concurrent algorithms (Behavioral). Each algorithm
itself is sequential, that means it consists of a set of instructions that are executed one
after the other. Functions, Tasks and Always blocks are the main elements. There is no
regard to the structural realization of the design.

2.3.6 REGISTER TRANSFER LEVEL

Designs using the Register-Transfer Level specify the characteristics of a circuit by
operations and the transfer of data between the registers. An explicit clock is used.

12
RTLdesign contains exact timing bounds: operations are scheduled to occur at certain
times. Modern RTL code definition is "Any code that is synthesizable is called RTL
code".

2.3.7 GATE LEVEL

Within the logic level the characteristics of a system are described by logical links and
their timing properties. All signals are discrete signals. They can only have definite
logical values (`0', `1', `X', `Z`). The usable operations are predefined logic primitives
(AND, OR, NOT etc gates). Using gate level modeling might not be a good idea for any
level of logic design. Gate level code is generated by tools like synthesis tools and this
net list is used for gate level simulation and for backend.

2.3.8 TESTBENCHES FOR SIMULATION:

To simulate an HDL model, an engineer writes a top-level simulation environment

(called a test bench). At minimum, a testbench contains an instantiation of the
model(called the device under test or DUT), pin/signal declarations for the model's I/O,
and clock waveform. The test bench code is event driven: the engineer writes HDL
statements to implement the (test bench-generated) reset-signal, to model interface
transactions (such as a hostbus read/write), and to monitor the DUT's output. An HDL
simulator the program that executes the test bench maintains the simulator clock,
which is the master reference for all events in the test bench simulation. Events occur
only at the instants dictated by the test bench HDL (such as a reset-toggle coded into the
test bench),or in reaction (by the model) to stimulus and triggering events. Modern HDL
simulators have full-featured graphical user interfaces, complete with a suite of debug
tools.

These allow the user to stop and restart the simulation at any time, insert simulator
breakpoints (independent of the HDL code), and monitor or modify any element in the
HDL model hierarchy. Modern simulators can also link the HDL environment to user-
compiled libraries, through a defined PLI/VHPI interface. Linking is system-

13
dependent(Win32/Linux/SPARC), as the HDL simulator and user libraries are compiled
and linked outside the HDL environment.

2.4 INTRODUCTION TO MODELSIM:

Modelsim is a multi-language HDL simulation environment by Mentor Graphics for

simulation of HDL languages such as VHDL, Verilog and SystemC, and includes a built-
in C debugger. Modelsim can be used independently, or in conjunction with Altera
Quartus or Xilinx ISE. Simulation is performed using the graphical user interface (GUI),
or automatically using scripts.

The Modelsim debug environments broad set of intuitive capabilities for Verilog,
VHDL, and SystemC make it the choice for ASIC and FPGA design. Modelsim eases the
process of finding design defects with an intelligently engineered debug environment.
The Modelsim debug environment efficiently displays design data for analysis and debug
of all languages.

Modelsim allows many debug and analysis capabilities to be employed post-simulation

on saved results, as well as during live simulation runs. For example, the coverage viewer
analyzes and annotates source code with code coverage results, including FSM state and
transition, statement, expression, branch, and toggle coverage.Signal values can be
annotated in the source window and viewed in the waveform viewer, easing debug
navigation with hyperlinked navigation between objects and its declaration and between
visited files.

Race conditions, delta, and event activity can be analyzed in the list and wave windows.
User-defined enumeration values can be easily defined for quicker understanding of
simulation results. For improved debug productivity, Modelsim also has graphical and
textual dataflow capabilities.

2.4.1 FEATURES OF MODELSIM:

Unified mixed language simulation engine for ease of use and performance

14
 Native support of Verilog, SystemVerilog for design, VHDL, and SystemC for
effective verification of sophisticated design environments
Fast time-to-debug, easy to use, multi-language debug environment
Advanced code coverage and analysis tools for fast time to coverage closure
Interactive and Post-Sim Debug available so same debug environment used for
both

Powerful Waveform compare for easy analysis of differences and bugs

Unified Coverage Database with complete interactive and HTML reporting and
processing for understanding and debugging coverage throughout your project
Coupled with HDL Designer and HDL Author for complete design creation,
project management and visualization capabilities

2.5 INTRODUCTION TO MATLAB:

Millions of engineers and scientists worldwide use MATLAB to analyze and design the
systems and products transforming our world. The matrix-based MATLAB language is
the world's most natural way to express computational mathematics. Built-in graphics
make it easy to visualize and gain insights from data. The desktop environment invites
experimentation, exploration, and discovery. These MATLAB tools and capabilities are
all rigorously tested and designed to work together.

MATLAB helps you take your ideas beyond the desktop. You can run your analyses on
larger data sets, and scale up to clusters and clouds. MATLAB code can be integrated
with other languages, enabling you to deploy algorithms and applications within web,
enterprise, and production systems.

2.5.1 FEATURES OF MATLAB:

Matlab is an interactive system for doing numerical computations.

A numerical analyst called Cleve Moler wrote the first version of Matlab in the 1970s.
It has since evolved into a successful commercial software package.

15
 Matlab relieves you of a lot of the mundane tasks associated with solving problems
numerically. This allows you to spend more time thinking, and encourages you to
experiment.
Matlab makes use of highly respected algorithms and hence you can be confident about
your results.
Powerful operations can be performed using just one or two commands.

You can build up your own set of functions for a particular application.

Excellent graphics facilities are available, and the pictures can be inserted into LATEX
and Word documents

2.6 Introduction to Xilinx:

Xilinx ISE (Integrated Synthesis Environment) is a software tool produced by Xilinx for
synthesis and analysis of HDL designs, enabling the developer to synthesize ("compile")
their designs, perform timing analysis, examine RTL diagrams, simulate a design's
reaction to different stimuli, and configure the target device with the programmer.

Xilinx ISE is a design environment for FPGA products from Xilinx, and is tightly-
coupled to the architecture of such chips, and cannot be used with FPGA products from
other vendors. The Xilinx ISE is primarily used for circuit synthesis and design, while
ISIM or the Modelsim logic simulator is used for system-level testing. Other components
shipped with the Xilinx ISE include the Embedded Development Kit (EDK), a Software
Development Kit (SDK) and Chip Scope Pro.

The primary user interface of the ISE is the Project Navigator, which includes the design
hierarchy (Sources), a source code editor (Workplace), an output console (Transcript),
and a processes tree (Processes). The Design hierarchy consists of design files (modules),
whose dependencies are interpreted by the ISE and displayed as a tree structure.For
single-chip designs there may be one main module, with other modules included by the
main module, similar to the main() subroutine in C++ programs. Design constraints are

specified in modules, which include pin configuration and mapping.

16
The Processes hierarchy describes the operations that the ISE will perform on the
currently active module.The hierarchy includes compilation functions, their dependency
functions, and other utilities. The window also denotes issues or errors that arise with
each function.The Transcript window provides status of currently running operations, and
informs engineers on design issues. Such issues may be filtered to show Warnings,
Errors, or both.

17
 CHAPTER 3
3.1 GOLAY ENCODER:
An (n, k) linear cyclic code C is said to be cyclic if for every codeword

, there is also a code word ,

the codeword c' is a right cyclic shift of the codeword c , it follows that all n of the
distinct cyclic shifts of c must also be codewords in C. The vector form of c can be
expressed as polynomial form

All the code polynomials in C , there is an unique monic generator polynomial

with minimal degree r < n. Every code polynomial c(x) in

C is a multiple of g(x) , and can be expressed uniquely as c(x) = m(x)g(x), where

is a message polynomial which coefficients are from the vector form. The codeword of
systematic form can be obtained in matrix form by c=mGS. From this, it is clearly shows
that the message bits always occupy the lowest 12 coordinates of each codeword.

In this case the codeword can be generated using XOR gates. Depending on the generator
matrix equations are written and the 12 message bits are encoded in to 23 bits.

3.2 CODEWORD GENERATION:

c[22] = xor (m[11],m[10],m[9],m[8],m[7],m[4],m[1]);

c[21] = xor (m[10],m[9],m[8],m[7],m[6],m[3],m[0]);
c[20] = xor (m[11],m[10],m[6],m[5],m[4],m[2],m[1]);
c[19] = xor (m[10],m[9],m[5],m[4],m[3],m[1],m[0]);
c[18] = xor (m[11],m[10],m[7],m[3],m[2],m[1],m[0]);
c[17] = xor (m[11],m[8],m[7],m[6],m[4],m[2],m[0]);
c[16] = xor (m[11],m[9],m[8],m[6],m[5],m[4],m[3]);

18
c[15]= xor (m[10],m[8],m[7],m[5],m[4],m[3],m[2]);
c[14]= xor (m[9],m[7],m[6],m[4],m[3],m[2],m[1]);
c[13]= xor (m[8],m[6],m[5],m[3],m[2],m[1],m[0]);
c[12]= xor (m[11],m[10],m[9],m[8],m[5],m[2],m[0]);
c[11]=m[11];
c[10]=m[10];
c[9]=m[9];
c[8]=m[8];
c[7]=m[7];
c[6]=m[6];
c[5]=m[5];
c[4]=m[4];
c[3]=m[3];
c[2]=m[2];
c[1]=m[1];
c[0]=m[0];

Fig 3.1 Block Diagram of Golay Encoder

19
3.3 GOLAY DECODER:

Fig 3.2 Block Diagram of Golay Decoder

If the codeword c is transmitted through a noisy channel, and if the vector r is received,
then r = c + e where e is an error pattern induced by the channel, that can be expressed as

error polynomial l Golay decoder is used to decode the

data that is received. It removes the parity bits that are added and then gives the message
bits for us.

3.3.1 PROCEDURE FOR DECODING:

First of all syndromes for single errors are computed and stored in arrays. Then
syndrome is calculated for the received codeword. Now the syndrome computed is
compared with the syndromes stored in arrays and if it is not present then syndrome is
compared by performing EXOR between any 2 or 3 syndromes stored in arrays. Then the
corresponding error patterns are added and the resultant error is added to the received
codeword.

20
Table 3.1 List of Syndromes Computed

Syndromes Error patterns

01011100011 00000000000000000000001
10111000110 00000000000000000000010
00101101111 00000000000000000000100
01011011110 00000000000000000001000
10110111100 00000000000000000010000
00110011011 00000000000000000100000
01100110110 00000000000000001000000
11001101100 00000000000000010000000
11000111011 00000000000000100000000
11010010101 00000000000001000000000
11111001001 00000000000010000000000
10101110001 00000000000100000000000
00000000001 00000000001000000000000
00000000010 00000000010000000000000
00000000100 00000000100000000000000
00000001000 00000001000000000000000
00000010000 00000010000000000000000
00000100000 00000100000000000000000
00001000000 00001000000000000000000
00010000000 00010000000000000000000
00100000000 00100000000000000000000
01000000000 01000000000000000000000
10000000000 10000000000000000000000

21
3.4 SYNDROME COMPUTATION:
The polynomial product r(x)h(x) modulo (xn1) is a polynomial of the form

where s(x)=r(x)h(x) is to be called syndrome polynomial. The vector form of s(x) can be
expressed as

And s can be computed from s = [rHT]. Where HT is transpose matrix of H. If during the
data transmission, no error occurs, the received codeword r is equal to the original
transmitted codeword c, then the syndrome vector s=rHT =(c+e)HT =(c+0)HT =cHT =0.
If errors occur in the received codeword, then the s=rHT=(cHT+eHT) =(0+eHT) 0.
Compare with s and the position of the column of the H, one can find out the error
position of the received codeword and correct these error bits under error correcting
capability.

3.4.1 EQUATIONS TO COMPUTE SYNDROME

s[10] = xor(r[22],r[11],r[10],r[9],r[8],r[7],r[4],r[1]);
s[9] = xor(r[21],r[10],r[9],r[8],r[7],r[6],r[3],r[0]);
s[8] = xor(r[20],r[11],r[10],r[6],r[5],r[4],r[2],r[1]);
s[7] = xor(r[19],r[10],r[9],r[5],r[4],r[3],r[1],r[0]);
s[6] = xor(r[18],r[11],r[10],r[7],r[3],r[2],r[1],r[0]);
s[5] = xor(r[17],r[11],r[4],r[9],r[8],r[7],r[6],r[2],r[0]);
s[4] = xor(r[16],r[11],r[3],r[8],r[6],r[5],r[4]);
s[3] = xor(r[15],r[9],r[10],r[7],r[8],r[5],r[4],r[3],r[2]);
s[2] = xor(r[14],r[7],r[6],r[1],r[4],r[3],r[2]);
s[1] = xor(r[13],r[9],r[8],r[5],r[6],r[3],r[2],r[1],r[0]);
s[0] = xor(r[12],r[10],r[11],r[5],r[8],r[2],r[0]);
Here r represents the received codeword and the digit in the bracket indicates the
position of the bit.

22
 CHAPTER 4

4.1 RESULTS OF ENCODER USING MODELSIM:

Message bits are 100000000000, Encoded data is 10101110001100000000000

Message bits are 000000000001, Encoded data is 01011100011000000000001

23
4.2 RESULTS OF ENCODER USING MATLAB:

Message bits are 100000000000, Encoded data is 10101110001100000000000

Message bits are 000000000001, Encoded data is 01011100011000000000001

24
4.3 SYNTHESIS REPORTS OF ENCODER

Top Level Output File Name : maj_gol.ngc

Primitive and Black Box Usage:

------------------------------
# BELS : 16
# LUT2 :5
# LUT6 : 11
# IO Buffers : 35
# IBUF : 12
# OBUF : 23

Device utilization summary:

---------------------------

Selected Device: 6slx45csg484-3

Slice Logic Utilization:

Number of Slice LUTs: 16 out of 27288 0%
Number used as Logic: 16 out of 27288 0%

Slice Logic Distribution:

Number of LUT Flip Flop pairs used: 16
Number with an unused Flip Flop: 16 out of 16 100%
Number with an unused LUT: 0 out of 16 0%
Number of fully used LUT-FF pairs: 0 out of 16 0%
Number of unique control sets: 0

IO Utilization:
Number of IOs: 35
Number of bonded IOBs: 35 out of 320 10%

25
4.3.1 RTL SCHEMATIC:

4.3.2 TECHNOLOGY SCHEMATIC:

26
4.4 RESULTS OF DECODER USING MODELSIM:

Received Codeword is 01000000011000000000001

Correct Codeword is 01011100011000000000001

Received Codeword is 10101110001100000000111

Correct Codeword is 10101110001100000000000

27
4.5 RESULTS OF DECODER USING MATLAB:

Received Codeword is 01000000011000000000001

Correct Codeword is 01011100011000000000001

Received Codeword is 10101110001100000000111

Correct Codeword is 10101110001100000000000

28
 CHAPTER 5

5.1 CONCLUSION:

A powerful weight decoder is developed to correct up to three errors in the (23, 12, 7)
Golay code. This decoding algorithm is based on the fact that it makes use of the
properties of cyclic codes and calculates the weight of the syndrome. Decoder is
developed using verilog and Matlab. The results of both the decoders are compared and
data which is corrupted is given as input to the decoder. It finds the position of the errors
in corrupted data and corrects the errors present in it.
An encoder is developed using verilog, Matlab and synthesized using Xilinx ISE.
The output of the encoder consists of 23 bits with last 12 bits as message bits and
remaining 11 bits as parity bits. The results of encoders developed using Matlab and
verilog are compared.

5.2 FUTURE SCOPE:

Coding applications have grown rapidly in the past several years. The area of applied
mathematics includes the study and discovery of various coding schemes that are used to
correct the errors that are introduced during data transmission. There are various types of
errors and a number of techniques for correction of these errors under Hamming metric
for both binary and non binary cases. Out of all these techniques Golay decoder is for
error detection and correction up to 3 errors. This Golay code is used in NASA deep
space mission because transmission of color image requires large bandwidth. As large
data is transmitted Golay code will be effective for encoding and decoding the data. This
can be further synthesized and can be installed at different places where the transmission
or reception of large data is carried out.

29
BIBILIOGRAPHY:
[1] M. J. E. Golay, Notes on digital coding, Proc. IRE, vol. 37, p. 657, Jun. 1949.
[2] X.-H. Peng and P. G. Farrell, On construction of the (24, 12, 8) Golay codes,
IEEE Trans. Inf. Theory, vol. 52, no. 8, pp. 36693675, Aug. 2006.
[3] B. Honary and G. Markarian, New simple encoder and trellis decoder for Golay
codes, Electron. Lett., vol. 29, no. 25, pp. 21702171, Dec. 1993.
[4] B. K. Classon, Method, system, apparatus, and phone for error control of Golay
encoded data signals, U.S. Patent 6 199 189, Mar. 6, 2001.
[5] M.-I. Weng and L.-N. Lee, Weighted erasure codec for the (24, 12) extended
Golay code, U.S. Patent 4 397 022, Aug. 2, 1983.
[6] S.-Y. Su and P.-C. Li, Photoacoustic signal generation with Golay coded
excitation, in Proc. IEEE Ultrason. Symp. (IUS), Oct. 2010, pp. 21512154.
[7] M. Spachmann, Automatic generation of parallel CRC circuits, IEEEDes. Test.
Comput., vol. 18, no. 3, pp. 108114, May/Jun. 2001.
[8] G. Campobello, G. Patane, and M. Russo, Parallel CRC realization, IEEE
Trans. Comput., vol. 52, no. 10, pp. 13121319, Oct. 2003.
[9] R. Nair, G. Ryan, and F. Farzaneh, A symbol based algorithm for hardware
implementation of cyclic redundancy check (CRC), in Proc.VHDL Int. Users
Forum, Oct. 1997, pp. 8287. J. Sel. Areas Commun., vol. 6, no. 3, pp. 558565,
Apr. 1988.
[10] J. Snyders and Y. Beery, Maximum likelihood soft decoding of binary block
codes and decoders for the Golay codes, IEEE Trans. Inf. Theory, vol. 35, no. 5, pp.
963975, Sep. 1989.
[11] I. S. Reed, X. Yin, T. K. Truong, and J. K. Holmes, Decoding the (24, 12, 8)
Golay code, IEE Proc. E Comput. Digit. Techn., vol. 137, no. 3, pp. 202206, May
1990. pp. 692695, May 1990.
[12] A. Vardy and Y. Beery, More efficient soft decoding of the Golay codes, IEEE
Trans. Inf. Theory, vol. 37, no. 3, pp. 667672, May 1991.
[13] W. Cao, High-speed parallel VLSI-architecture for the (24, 12) Golay decoder
with Optimized permutation decoding, in Proc. IEEE Int. Symp.Circuits Syst.
(ISCAS), Connecting World, vol. 4. May 1996, pp. 6164.

30
[14] W. Cao, High-speed parallel hard and soft-decision Golay decoder: Algorithm
and VLSI-architecture, in Proc. IEEE Int. Conf. Acoust.,Speech, Signal Process.
(ICASSP)., vol. 6. May 1996, pp. 32953297.
[15] G. Solomon, Golay encoding/decoding via BCH-hamming, Comput.Math.
Appl., vol. 39, no. 11, pp. 103108, Jun. 2000.
[16] M.-H. Jing, Y.-C.Su, J.-H.Chen, Z.-H. Chen, and Y. Chang, High-speed low-
complexity Golay decoder based on syndrome-weight determination, in Proc. 7th
Int. Conf. Inf., Commun., SignalProcess. (ICICS), Dec. 2009, pp. 14.
[17] T.-C. Lin, H.-C.Chang, H.-P.Lee, and T.-K. Truong, On the decoding of the (24,
12, 8) Golay code, Inf. Sci., vol. 180, no. 23, pp. 47294736, Dec. 2010.
[18] P. Adde, D. G. Toro, and C. Jego, Design of an efficient maximum likelihood
soft decoder for systematic short block codes, IEEE Trans.Signal Process., vol. 60.

31
APPENDIX-A

A.1 VERILOG CODE FOR ENCODER:

Module golay_enc(m,c);
input [11:0] m;
output [22:0] c;
assign c[22]=m[11]^m[10]^m[9]^m[8]^m[7]^m[4]^m[1];
assign c[21]=m[10]^m[9]^m[8]^m[7]^m[6]^m[3]^m[0];
assign c[20]=m[11]^m[10]^m[6]^m[5]^m[4]^m[2]^m[1];
assign c[19]=m[10]^m[9]^m[5]^m[4]^m[3]^m[1]^m[0];
assign c[18]=m[11]^m[10]^m[7]^m[3]^m[2]^m[1]^m[0];
assign c[17]=m[11]^m[8]^m[7]^m[6]^m[4]^m[2]^m[0];
assign c[16]=m[11]^m[9]^m[8]^m[6]^m[5]^m[4]^m[3];
assign c[15]=m[10]^m[8]^m[7]^m[5]^m[4]^m[3]^m[2];
assign c[14]=m[9]^m[7]^m[6]^m[4]^m[3]^m[2]^m[1];
assign c[13]=m[8]^m[6]^m[5]^m[3]^m[2]^m[1]^m[0];
assign c[12]=m[11]^m[10]^m[9]^m[8]^m[5]^m[2]^m[0];
assign c[11]=m[11];
assign c[10]=m[10];
assign c[9]=m[9];
assign c[8]=m[8];
assign c[7]=m[7];
assign c[6]=m[6];
assign c[5]=m[5];
assign c[4]=m[4];
assign c[3]=m[3];
assign c[2]=m[2];
assign c[1]=m[1];
assign c[0]=m[0];
endmodule

32
A.2 VERILOG CODE FOR DECODER:
module dec_golay1(r,s,c);
input[22:0] r;
integer i=0,j=0,l=0,n=0;
output[10:0] s;
output [22:0] c;
reg[22:0] c,u;
integer k=0;
reg[10:0] x;
wire [22:0] e[22:0];
wire [10:0] m[22:0];
assign e[0]=23'b00000000000000000000001;
assign e[1]=23'b00000000000000000000010;
assign e[2]=23'b00000000000000000000100;
assign e[3]=23'b00000000000000000001000;
assign e[4]=23'b00000000000000000010000;
assign e[5]=23'b00000000000000000100000;
assign e[6]=23'b00000000000000001000000;
assign e[7]=23'b00000000000000010000000;
assign e[8]=23'b00000000000000100000000;
assign e[9]=23'b00000000000001000000000;
assign e[10]=23'b00000000000010000000000;
assign e[11]=23'b00000000000100000000000;
assign e[12]=23'b00000000001000000000000;
assign e[13]=23'b00000000010000000000000;
assign e[14]=23'b00000000100000000000000;
assign e[15]=23'b00000001000000000000000;
assign e[16]=23'b00000010000000000000000;
assign e[17]=23'b00000100000000000000000;
assign e[18]=23'b00001000000000000000000;
assign e[19]=23'b00010000000000000000000;

33
assign e[20]=23'b00100000000000000000000;
assign e[21]=23'b01000000000000000000000;
assign e[22]=23'b10000000000000000000000;
assign m[0]=11'b01011100011;
assign m[1]=11'b10111000110;
assign m[2]=11'b00101101111;
assign m[3]=11'b01011011110;
assign m[4]=11'b10110111100;
assign m[5]=11'b00110011011;
assign m[6]=11'b01100110110;
assign m[7]=11'b11001101100;
assign m[8]=11'b11000111011;
assign m[9]=11'b11010010101;
assign m[10]=11'b11111001001;
assign m[11]=11'b10101110001;
assign m[12]=11'b00000000001;
assign m[13]=11'b00000000010;
assign m[14]=11'b00000000100;
assign m[15]=11'b00000001000;
assign m[16]=11'b00000010000;
assign m[17]=11'b00000100000;
assign m[18]=11'b00001000000;
assign m[19]=11'b00010000000;
assign m[20]=11'b00100000000;
assign m[21]=11'b01000000000;
assign m[22]=11'b10000000000;

assign s[10]=r[22]^r[11]^r[10]^r[9]^r[8]^r[7]^r[4]^r[1];
assign s[9]=r[21]^r[10]^r[9]^r[8]^r[7]^r[6]^r[3]^r[0];
assign s[8]=r[20]^r[11]^r[10]^r[6]^r[5]^r[4]^r[2]^r[1];

34
assign s[7]=r[19]^r[10]^r[9]^r[5]^r[4]^r[3]^r[1]^r[0];
assign s[6]=r[18]^r[11]^r[10]^r[7]^r[3]^r[2]^r[1]^r[0];
assign s[5]=r[17]^r[11]^r[4]^r[9]^r[8]^r[7]^r[6]^r[2]^r[0];
assign s[4]=r[16]^r[11]^r[3]^r[8]^r[6]^r[5]^r[4];
assign s[3]=r[15]^r[9]^r[10]^r[7]^r[8]^r[5]^r[4]^r[3]^r[2];
assign s[2]=r[14]^r[7]^r[6]^r[1]^r[4]^r[3]^r[2];
assign s[1]=r[13]^r[9]^r[8]^r[5]^r[6]^r[3]^r[2]^r[1]^r[0];
assign s[0]=r[12]^r[10]^r[11]^r[5]^r[8]^r[2]^r[0];
always@(*)
begin
if(s==0)
c<=r;
else
begin
x=s;
while(x!=0)
begin
if(x[0]&1==1)
k=k+1;
x=x>>1;
end
if((k<3)|(k==3))
begin
u={13'b0000000000000,s[10:0]};
c=r^(u<<12);
end
else
begin
u<=23'b00000000000000000000000;
if(s== 11'b01011100011) c=r^(23'b00000000000000000000001);
else if (s==11'b10111000110) c=r^(23'b00000000000000000000010);

35
else if (s==11'b00101101111) c=r^(23'b00000000000000000000100);
else if (s==11'b01011011110) c=r^(23'b00000000000000000001000);
else if (s==11'b10110111100) c=r^(23'b00000000000000000010000);
else if (s==11'b00110011011) c=r^(23'b00000000000000000100000);
else if(s==11'b01100110110) c=r^(23'b00000000000000001000000);
else if(s==11'b11001101100) c=r^(23'b00000000000000010000000);
else if(s==11'b11000111011) c=r^(23'b00000000000000100000000);
else if(s==11'b11010010101) c=r^(23'b00000000000001000000000);
else if(s==11'b11111001001) c=r^(23'b00000000000010000000000);
else if(s==11'b10101110001) c=r^(23'b00000000000100000000000);
else
begin
for(i=0;((i<23)&&(l!=1));i=i+1)
begin
for(j=0;((j<23)&&(l!=1));j=j+1)
begin
if(s==(m[i]^m[j]))
begin
c=r^e[i]^e[j];
l=1;
end
else
begin
for(n=0;((n<23)&&(l!=1));n=n+1)
begin
if(s==(m[i]^m[j]^m[n]))
begin
l=1;
c=r^e[i]^e[j]^e[n];
end
end

36
end
end
end

end
end
end
end
endmodule

37
A.3 MATLAB CODE FOR ENCODER:
clc
clear all
m=zeros(1,12);
for i=1:12
m(i)=input('enter message bit');
end
g=[1 0 1 0 1 1 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0;
1 1 1 1 1 0 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0;
1 1 0 1 0 0 1 0 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0;
1 1 0 0 0 1 1 1 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0;
1 1 0 0 1 1 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0;
0 1 1 0 0 1 1 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0;
0 0 1 1 0 0 1 1 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0;
1 0 1 1 0 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0;
0 1 0 1 1 0 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0;
0 0 1 0 1 1 0 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 0;
1 0 1 1 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0;
0 1 0 1 1 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 1]
c=m*g;
for i=1:23
if (mod(c(i),2))
c(i)=1;
else
c(i)=0;
end
end
disp(c);

38
A.4 MATLAB CODE FOR DECODER:
clc;
clearall;
r=zeros(1,23);
c=zeros(1,23);
for i=1:23
r(i)=input ('enter binar data');
end
disp(r);
s(1)=xor(xor(xor(r(1),r(12)),xor(r(13),r(14))),xor(xor(r(15),r(16)),xor(r(19),r(22))));
s(2)=xor(xor(xor(r(2),r(13)),xor(r(14),r(15))),xor(xor(r(16),r(17)),xor(r(20),r(23))));
s(3)=xor(xor(xor(r(3),r(12)),xor(r(13),r(17))),xor(xor(r(18),r(19)),xor(r(21),r(22))));
s(4)=xor(xor(xor(r(4),r(13)),xor(r(14),r(18))),xor(xor(r(19),r(20)),xor(r(22),r(23))));
s(5)=xor(xor(xor(r(23-18),r(23-11)),xor(r(23-10),r(23-7))),xor(xor(r(20),r(23-
2)),xor(r(23-1),r(23-0))));
s(6)=xor(xor(xor(r(23-17),r(23-11)),xor(r(23-4),r(23-9))),xor(xor(r(23-8),r(23-
7)),xor(r(23-6),xor(r(23-2),r(23-0)))));
s(7)=xor(r(23-16),xor(r(23-11),xor(r(23-3),xor(r(23-8),xor(r(23-6),xor(r(23-5),r(23-
4)))))));
s(8)=xor(r(23-15),xor(r(23-9),xor(r(23-10),xor(r(23-7),xor(r(23-8),xor(r(23-5),xor(r(23-
4),xor(r(23-3),r(23-2)))))))));
s(9)=xor(r(23-14),xor(r(23-7),xor(r(23-6),xor(r(23-1),xor(r(23-4),xor(r(23-3),r(23-
2)))))));
s(10)=xor(r(23-13),xor(r(23-9),xor(r(23-8),xor(r(23-5),xor(r(23-6),xor(r(23-3),xor(r(23-
2),xor(r(23-1),r(23-0)))))))));
s(11)=xor(r(23-12),xor(r(23-10),xor(r(23-11),xor(r(23-5),xor(r(23-8),xor(r(23-2),r(23-
0)))))));
disp(s);
h=[1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 1 0 0 1 0;
0 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 1 0 0 1;
0 0 1 0 0 0 0 0 0 0 0 1 1 0 0 0 1 1 1 0 1 1 0;

39
 0 0 0 1 0 0 0 0 0 0 0 0 1 1 0 0 0 1 1 1 0 1 1;
0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 1 0 0 0 1 1 1 1;
0 0 0 0 0 1 0 0 0 0 0 1 0 1 1 1 1 0 1 0 1 0 1;
0 0 0 0 0 0 1 0 0 0 0 1 0 0 1 0 1 1 1 1 0 0 0;
0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 1 1 1 1 0 0;
0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 1 1 1 1 0;
0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 1 1 0 1 1 1 1;
0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 0 1 0 0 1 0 1]

e=eye(23);
for i=1:23
if(s==transpose(h(:,i)))
c=xor(r,transpose(e(:,i)))
end
end
for i=1:23
for j=1:23
if(s==(xor(transpose(h(:,i)),transpose(h(:,j)))))
c=xor(r,xor(transpose(e(:,i)),transpose(e(:,j))));
end
for k=1:23
if(s==(xor(transpose(h(:,i)),xor(transpose(h(:,j)),transpose(h(:,k))))))
c=xor(r,xor(transpose(e(:,i)),xor(transpose(e(:,j)),transpose(e(:,k)))));
break;
end
end
end
end
disp('c value is');
disp(c);

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41