DIGITAL BAS ICS

Introduction

Digital techniques are now well established in the world of broadcasting. This is due to
the fact that though the digital system seems more complex, however, it has many
advantages, such as higher accuracy, stability, flexibility etc. Therefore, in spite of their
complexity and higher costs, digital circuits are being used for great variety of
operations. Secondly with the easy availability of digital circuits in I.C. forms, extreme
large digital circuits can be reliably built in small volumes at relatively low cost.

In broadcasting, digital techniques are being used in tape recorders, mixers, switchers,
signal processors, level control, reverberation generators, remote control of air-
conditioning plants, automation in recording, studio-transmitter links, control and tuning
of transmitter etc.

Analogue and Digital Signals

A continuous signal is known as analogue signal. It has many continuous values. On

the other hand, a digital signal has discrete values either it is available or not available.
The input to and output from a microphone, the output of a loudspeaker, a singer singing
a song etc. are examples of continuous signals. A switch is being switched ON and
OFF; the output available is a digital signal. This has been shown in fig. 1

Fig. 1 Analogue and Digital Signals

So what do we find in the above figure? The digital signal has got only two states High
and Low or ON and OFF or 1 and 0. 1 may be 5V, 10V or 12V etc. In the same way 0
may be 0V, 0.2V or 0.5V etc. The states of digital signal give an idea of a new number
system, which is known as Binary Number System.
Induction Course (General)

Binary Number System

We all are aware of decimal number system where basic digits are from 0 9 (total ten
digits and hence the name). All the numbers have been written with the help of these
ten digits. In the binary system we have only two basic digits i.e. 0 and 1. All the
numbers of binary system are written with the help of these two digits as given below :

Decimal Number Binary Number

0 0
1 1
2 10
3 11
4 100
5 101
6 110
7 111
8 1000
9 1001
10 1010
11 1011
12 1100
13 1101
14 1110
15 1111
16 10000
17 10001
18 10010
19 10011
20 10100

It is interesting to note that all the binary numbers are inside the decimal numbers. Take
out those decimal numbers which contains digits 0 and 1 only. This will result in binary
number e.g. 0, 1, 10, 11, 100, 101, 110, 111 .

Base

The number of digits or basic symbols in a number system is known as its base. The
decimal system has a base of 10 because it uses 10 digits. Binary has a base of 2, octal
has a base of 8 and hexadecimal a base of 16.

Bit

Bit is an abbreviated form of binary digit. Instead of saying that 10110 has five binary
digits, we can say that it has 5 bits.

Hexadecimal Number System

It is a number system with a base of 16. This system has 16 digits as follow
0, 1, 2, 3, 4, 5, 6, 7, 8, A, B, C, D, E, F

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Octal Number System

It is a number system with a base of 8. It has the following 8 digits.

0, 1, 2, 3, 4, 5, 6, 7

Binary to Decimal Conversion

We can express any decimal integer (a whole number) in units, tens, hundreds,
thousands and so on. For instance decimal number 3056 may be written as

3856 = 3000 + 800 + 50 + 6

In power of 10, this becomes

3856 = 3(10)3 + 8(10) 2 + 5(10) 1 + 6(10) o

Here each digit position has a weight or value. The sum of all the digits multiplied by
their weights gives the total amount being represented.

Binary Weight

In a similar way we can rewrite any binary number in terms of weights. For example
binary number 111 becomes

111 = 100 + 10 + 1
In decimal it is 7 = 4+2+1
7 = 1(2)2 + 1(2)1 + 1(2)o
= 1(4) + 1(2) +1

Procedure for Binary to decimal conversion

i) Write the binary number

ii) Directly under the binary number write 1, 2, 4, 6, 8, 16 working from right to
left.
iii) If a zero appears in a digit position, delete/cross out weight for that position.
iv) Add the remaining weights to obtain the decimal equivalent.

Example

1. Convert binary number 101 into equivalent decimal number

Step I) : 101
Step ii) : 421
Step iii) : 401
Step iv) : 4+1=5

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2. Convert binary number 10101 into equivalent decimal number

Step I) : 1 0 1 0 1
Step ii) : 16 8 4 2 1
Step iii) : 16 0 4 0 1
Step iv) : 16 + 0 + 4 + 0 + 1 = 21

Conversion of binary fractions

What is the decimal equivalent of 0.101. In this case, the weight of digit positions to the
right of the binary point are given by ½, ¼, 1/8, 1/16, 1/32

In power of 2, the weights are

2-1, 2-2, 2-3, 2-4

or in decimal form
0.5, 0.25, 0.125, 0.0625

Hence the decimal equivalent for the binary fraction 0.101 can be calculated as follow

0.1 0 1
0.5 + 0 + 0.125 = 0.625

3. What is the decimal equivalent of binary fraction 0.1101 ?

0.1 1 0 1
0.5 + 0.25 + 0.125 + 0.0625 = 0.8125

Hence for conversion of binary number into decimal number you should remember the
following :

23 22 21 20 o 2-1 2-2 2-3

Binary point

Decimal to Binary Conversion

Double Dabble

This is a very popular way to convert decimal numbers to binary numbers. In this
method you progressively divide the decimal number by 2, writing down the remainder
after each division. The remainders, taken in reverse order is the required binary
number. Let us convert decimal number 13 into equivalent binary number

Step 1 Divide 13 by 2,

2) 13 ( 6 ------ Quotient is 6
12
01 ---------- remainder = 1

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Step 2
2) 6 ( 3 ------ Quotient is 3
6
0 ---------- remainder = 0
Step 3
2) 3 ( 1 ------ Quotient is 1
2
1 ---------- remainder = 1

Step 4
2) 1 ( 0 ------ Quotient is 0
0
1 ---------- remainder = 1

In final division, 2 does not divide into 1, therefore, the quotient is 0 with a
remainder of 1. Hence binary equivalent of 13 = 1101.

Binary Addition

0+0 = 0 0 plus 0 equals 0

0+1 = 1 0 plus 1 equals 1
1+0 = 1 1 plus 0 equals 1
1+1 = 10 1 plus 1 equals 0 with a carry of 1

Example

Add binary number

1 0 1 0 to 1011
Binary Decimal
1010 10
+ 1011 + 11
10101 21
Binary multiplication

0 x0 = 0
0x1 = 0
1x0 = 0
1x1 = 1
Example

Multiply
1 0 1 by 1 1 0
Binary Decimal
101 - 5
x 110 - x 6
000 30
101x
101xx
11110

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Induction Course (General)

Logic Gates

Logic gate is somewhat similar to normal gate. When a gate is opened something is
allowed to pass and when it is closed nothing is allowed to pass through. But logical
gate things logically and then acts. It works with certain conditions. When all the
conditions are fulfilled input is allowed to pass as output.

A logic gate is a digital circuit with one or more inputs, but only one output. The output is
high only for certain combinations of the input signals.

We have different types of gates such as AND gate, OR gate, NOT gate etc. These can
be designed with the help of switches, diodes, transistors and ICs. Let us discuss these
gates one by one.

AND Gate

The AND Gate has two or more inputs but only one output. When all the inputs are high
(1), the output is high (1) otherwise it is low (0). This gate can be implemented with
simple switches as shown in Fig. 2.

Fig. 2 AND gate drawn with simple switches A and B

In the above figure switches A and B are connected in series with the supply. When
both the switches are ON (i.e. 1 or High), the bulb is ON (1 or High). If any of the
switches is OFF (0 or Low), the bulb is OFF (0 or Low). Hence the combination of
switches A and B is known as AND gate. The symbol of AND gate is shown in fig. 3.

Fig. 3 Symbol of AND gate

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Truth Table

A truth table gives details of various combinations of inputs and corresponding outputs.
The truth table of AND gate is given below :

Truth Table of AND Gate

I/P O/P
A B Y
0 0 0
0 1 0
1 0 0
1 1 1

0 = LOW/OFF 1= HIGH/ON

AND Gate can also be implemented with diodes as shown in Fig. 4.

Fig. 4 And gate drawn with diodes

When either A or B input is low (0), D1 or D2 is forward biased and output Y is low(0).
When both inputs A and B are high (1) together, the output Y is High (1).

In the same way AND Gate can also be designed with the combinations of Diodes and
transistors or only transistors. The AND gate designed in IC form is shown in Fig. 5.

Fig. 5 Quad 2-input TTL AND gates

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This gate works on the logic of 'this and that' hence the name is AND gate.

OR Gate

This gate has two or more inputs and one output. When any or all the inputs are high (1)
the output is high (1). Fig. 6 and 7 show the OR gate designed with the help of switches
and diodes respectively.

Fig. 6 OR gates drawn with switches Fig. 7 OR gate drawn with diodes

In figure 6 bulb starts glowing when switch A or B is ON (1 or High). In fig. 7 output Y is

High (1) when either input A or B is high (1) making D1 or D2 to conduct. Symbol of OR
Gate is shown in fig. 8. Fig. 9 shows OR gates in IC form.

Fig. 8 Symbol of OR gate

Truth Table
I/P O/P
A B C
0 0 0
0 1 1
1 0 1
1 1 1

Fig. 9 Quad 2-input TTL OR gates

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This gate works on the logic of 'This or that', hence the name is OR gate

NOT Gate

The NOT gate has one input and one output. When the input is High (1), the out is low
(O) and vice versa. Fig. 10 shows this gate designed with a switch.

Fig. 10 NOT gate drawn with a switch Fig. 11 NOT gate drawn with a transister

When the switch is ON (1 or High) the bulb is shorted and hence it does not glow (OFF
or 0 or LOW). When switch is OFF (open or 0) the bulb is ON (1 or High).

In Fig. (11) the NOT gate has been drawn with a transistor. When the input A is high (1)
the transistor is forward biased and so it conducts making Y low (0). When the input A is
low (0), the transistor is cut off and hence the output Y is high (1). Since the NOT gate
inverts the sense of the output with respect to input, it is also called as an inverter.
Fig. 13 shows NOT gates in IC form.

Symbol of NOT gate

Fig. 12 Symbol of NOT gate

Truth Table
A T
0 1
1 0

Fig. 13 TTL NOT gates (Hex inverters)

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This gate works on the logic of 'negative', hence the name is NOT gate.

NAND Gate

A NAND gate has two or more inputs and a single output. It is a combination of an AND
gate and a NOT gate. The output of a NAND gate assumes the 0 state if and only if all
the inputs assume the 1 state. Fig. 14 shows the NAND gate designed with the help of
switches. Symbol of NAND gate is given in fig.15. Fig. 16 shows NAND gates in IC form.

Fig. 14 NAND gate drawn with switches

Fig. 15 Symbol of NAND gate

Truth Table
I/P O/P
A B Y
0 0 1
0 1 1
1 0 1
1 1 0

Fig. 16 Quad 2-input NAND gates

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NOR Gate

A NOR gate has two or more inputs and a single output. It is a combination of an OR
gate followed by a NOT gate. The output of a NOR gate assumes the 1 state if and
only if all the inputs assume the 0 state. Fig. 17 shows the NOR gate designed with the
help of switches. Symbol of NOR gate is given in fig. 18. Fig. 19 shows NOR gates in IC
form.

Fig. 17 NOR gate drawn with switches

Fig. 18 Symbol of NOR gate

Truth Table
I/P O/P
A B Y
0 0 1
0 1 0
1 0 0
1 1 0

Fig. 19 Quad 2-input NOR gates

NAND and NOR gates are known as 'Universal Gates' as any gate or logical circuit can
be implemented with them.

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Exclusive OR Gate

EX-OR gate has two or more inputs and one output. It has high output only when odd
number of inputs are high.

Symbols of Ex-OR gate

Fig. 20 Symbol of EX-OR gate

Truth Table
I/P O/P
A B Y
0 0 0
0 1 1
1 0 1
1 1 0

Figure 21 shows how to build an EX-OR Gate with the help of AND, OR and NOT Gates.

Fig. 21 Implementation of EX-OR gate with AND, OR and NOT gates

The opposite of Ex-OR gate is Ex-NOR gate.

Flip-Flops
A flip-flop (FF) is a bistable electric circuit that has two stable states. The flip-flop also
has memory unlike gates described in previous paragraphs, since its output will remain
as set until something is done to change it. FF has two outputs, defined as Q and Q.Q
and Q are complementary.

i) R.S. Flip-flop : The basic R-S flip-flop with NOR gates is shown below along with
truth table.

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Truth Table (with NOR gates)

R S Qn Qn
0 0 Qn-1 Qn-1
0 1 1 (Set) 0
1 0 0 (Reset) 1
1 1 * *

Truth Table (with NAND gates)

R S Qn Qn
1 1 Qn-1 Qn-1
0 1 1 (Set) 0
1 0 0 (Reset) 1
0 0 * *
*Forbidden

Fig. 22 RS flip-flop drawn with NOR and NAND gates and its symbol

ii) Clocked RS Flip-Flop : In the RS FF any change in input information at R and

S is transmitted immediately to the output at Q and Q according to the truth table.
Addition of two AND gates at the R and S inputs results in enabling/disabling the
FF. This flip-flop is called a clocked RS flip-flop. The R and S inputs are
transmitted to the output only when clock pulse is present.

Logic diagram and truth table are given below :-

Truth Table
CLK R S Qn
0 0 0 Qn-1
0 0 1 Qn-1
0 1 0 Qn-1
0 1 1 Qn-1
1 0 0 Qn-1
1 0 1 1
1 1 0 0
1 1 1 *

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Fig. 23 Logic diagram

iii) D Flip-Flop : The RS flip-flop has two data inputs R and S. To store a high bit,
we need a high S; to store a low bit, we need a high R. Generation of two
signals to drive has disadvantages in many applications. Furthermore,
something forbidden condition of both R and S high may occur in advertently.
These problems are avoided in D flip-flop, which needs only a single data input.

Logic diagram, symbol and truth table of D-FF are shown below :-

Fig. 24 Logic diagram, symbol and truth table of D Flip-Flop

iv) Edge Triggered D Flip-Flop

In edge-triggered D FF, an RC circuit, having much smaller time constant than

the clock pulse width, is introduced at the clock input. This produces narrow
positive and negative spikes at the leading and trailing edges of clock pulse. The
FF can be triggered at the positive or negative edge of the pulse.

PRESET and CLEAR inputs can also be provided in the flip-flop. A high
PRESET forces Q to 1; a high CLEAR resets Q to 0.

Logic diagram and symbols of these FFs are given below :

Fig. 25 Logic diagram and symbols of edge triggered D Flip-Flop

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v) J.K.Flip-Flop

Among the other flip flops J-K-flip flops are mostly used in counters. Fig. 26 shows a
typical J.K.Flip flop.

C CLK J K Qn
J S Q X 0 0 Q n-1 Last
CLK State
0 1 0

K R Q 1 0 1

1 1 Qn Toggle)

(a) J K Flip Flop (b) Truth Table

Fig. 26 J-K Flip-Flop

When J and K both are low, both AND gates are disabled. Therefore clock pulses have
no effect. As shown when J-K=0, Q retains its last value.

When J=0, K =1, the upper gate is disabled so the flip flop cannot be set. The only
possibility is reset. When Q is high, the lower gate passes a RESET trigger as soon as
the next positive clock edge arrives.

Similarly J=1, K=0, means that the next positive clock edge sets the flip flop. (unless Q is
already high).

When J=1, K =1, it is possible to set or RESET the flip-flop. If Q = 1, the lower gate
passes a reset trigger, and Q=0, the upper gate passes a set trigger on the next positive
clock edge, either way, Q changes to the complement of the last state. Therefore
J=K=1, means the flip-flop will toggle on the next positive clock edge.

Propagation delay prevents the JK flip flop from racing. Racing is phenomenon of
toggling more than once during a positive clock edge. This can be explained as follows :
The outputs change after the positive clock edge has struck. But, by then, the new Q
and Q values are too late to coincide with the positive spikes driving the AND gates.
For instance, if tp = 20 ns, the outputs change approximately 20 ns after the leading
edge of the clock. If the clock spikes are narrower than 20 ns, the returning Q and Q
arrive too late to cause false triggering.

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Counter
A counter is probably one of the most useful and versatile subsystem in a digital system.
A counter driven by a clock can be used to count the number of clock cycles. Since the
clock pulses occur at known intervals, the counter can be used as an instrument for
measuring time and therefore period of frequency. There are basically two different
types of counters asynchronous or ripple and synhronous counter.

Asynchronous (Ripple) Counter

A binary ripple counter can be constructed using clocked JK flip-flop, as shown in fig. 27.
All the J and K inputs are tied to +Vcc. The system clock drives flip flop A. The output of
A drives flip flop B and the output of B drives flip flop C. This means each flip flop will
change state (toggle) with a negative transition of its clock input.

When the output of a flip flop is used as the clock input for the next flip flop, we call the
counters a ripple counter, or asynchronous counter. As the output of previous stage
acts as a clock input to the next stage, the overall propagation delay time is the sum of
the individual delays.

Fig. 27 Asynchronous Counter

A binary ripple counter counts in a straight binary sequence. So counter having n flip
flops will have 2n output conditions. The largest binary number that can be represented
by n cascade flip flops has a decimal equivalent of 2n-1. The modules of a counter is
the total number of states through which the counter can progress. A three flip flop
counter is often referred to as a modules 8 ( or Mod-8) counter since it has eight
states.

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A Mod-5 (divide-by-5) binary counter

The counter is shown in fig. 28. During up count when the counter reaches number 5
(Binary 101) the output of the NAND gate goes to 0 and all the flip flops are reset. Thus
it counts from 0 to 4 only. However a glitch will appear, as shown in the figure,
immediately after 5th count.

Fig. 28 A divide-by-5 (MOD-5) binary counter

Up-Down Counter

Fig. 29 3-bit binary up-down counter

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Synchronous Counters

The ripple counter is the simplest to build, but there is a limit to its highest operating
frequency. It is due to the accumulated propagation delay of the clock from flip flop to
flip flop. Further more, there is a possibility of glitches occurring at the output of
decoding gates used with a ripple counter. Both these problems can be overcome by
the use of a synchronous or parallel counter. The main difference here is that every flip
flop is triggered in synchronism with the clock.

Synchronous Up-Down Counter

A synchronous 4-bit up-down counter is shown in fig. 30. To operate in the counter up
mode, the system clock is applied at the count-up input, while the count-down input is
held low. To operate in the count down mode, the system clock is applied at the count
down input while holding the count up input low. All the J-K inputs are kept at high state.

Fig. 30 Synchronous, 4-bit up-down counter

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Registers
A register is a group of flip-flops that can be used to store a binary number. There must
be one flip flop for each bit in the binary number. For instance, a register used to store
an 8-bit binary number must have eight flip-flops.

There are two ways to shift data into a register (serial or parallel) and similarly two ways
to shift the data out of the register. This leads to the construction of few basic register
types

a) Serial in serial out.

b) Serial in parallel out
c) Parallel in serial out
d) Parallel in parallel out

a) Serial in serial out registers

The flip-flops used to construct registers are usually either J-K or D types.

The important point to note is that the J-K or D inputs must be controlled to provide the
correct input data. The input logic levels may be changing while the clock is high (or
low), but they must be steady from just before until just after the clock transition.

a b c d
Time

Clock 1
0
J Q
Input J 1
Data 0
K Q
K 1
Clock
(Shift) 0

Q 1
0

(a) (b)

Fig. 31 Serial in Serial out

The waveform in figure 31 illustrate these ideas. At time a, Q is reset low (a 0 is shifted
into the flip flop). At time b, Q does not change since the flip-flop had a 0 in it and
another 0 is shifted in. At time c, the flip flop is set (a1 is shifted into it). At time d
another 0 is shifted into the flip flop. In essence, we have shifted 4 data bits into this flip
flop in a time sequence; a 0 at time a, another 0 at time b, a 1 at time c, and a 0 at time
d. Clearly, K = J and J = K from above. Therefore, instead of J, K flip flop a D type flip
flop may be used for resisters.

A 4 bit serial input shift register is shown in figure 32.

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Serial
Input D Q D R D S D T

Clock
(a)

a b c d
Time

Clock 1
0

D 1
0

Q 1 0
0

R 1
1
0
S 1 0
0
T 1
0
0
(b)

Fig. 32 Serial in Serial out Registers

In a similar way other types of registers may be discussed.

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