A B C D E

1 1

LCFC Confidential
ACLU9 M/B Schematics Document
2

Intel BayTrail M-Processor with DDRIIIL + NV (N15V-GM/N15S-GT) GPU 2

2013-12-22
3

REV:0.2 3

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 Cover Page
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
ACLU9
Date: Monday, December 23, 2013 Sheet 1 of 59
A B C D E
 A B C D E

LCFC confidential File Name : ACLU9

NV (N15V-GM/N15S-GT)
GB2B-64 Package PCI-Express Memory BUS (DDR3L)
Page 18~28 PCIe Port5 Dual Channel DDR3L-SO-DIMM
2x Gen2 Page 14

VRAM 256/128*16 1.35V DDR3L 1333 MT/s

UP TO 8G
DDR3L*8 4GB/2GB/1GB
1
Page 19~28 1

USB 3.0 1x USB Left 3.0 Conn

HDMI
HDMI Conn. USB 2.0 1x USB 3.0 Port0
Page 34
USB 2.0 Port0 Page 41

CRT
VGA Conn. Baytrail M (4.5W) USB 2.0 1x USB Left 2.0 Conn
Page 36
USB 2.0 Port3 Page 41
eDP Conn
USB 2.0 1x to Camera
to USB Port Int. Camera
USB2.0 Port2
eDP x2 Lane
Int. MIC Conn. USB Right
USB2.0 1x
USB2.0 Hub Port1
2
Page 33 2

USB2.0 1x Cardreader Realtek

USB 2.0 1x USB Hub SD/MMC Conn.
SATA HDD SATA Gen2 RTS5170USB2.0 Hub Port3
Page 42 SATA Port0 USB Board
BGA-1170
USB2.0 1x Touch Screen
SATA ODD SATA Gen1 25mm*27mm
Page 42 SATA Port1
reserved
USB 2.0 Port2 Page 33
Page 16
USB2.0 1x
USB 2.0 Port1
NGFF Card
LAN Realtek PCIe 1x WLAN&BT
PCIe Port0
RJ45 Conn. PCIe 1x Page 40
RTL8111GUL (1G) USB2.0 Hub Port4
Page 38
RTL8106EUL (10M/100M)
Page 37 PCIe Port1
HD Audio SPI BUS SPI ROM
Page 4~12
8MB Page 07 Sub-board ( for 14")
POWER BOARD
3 3

Codec SPK Conn.

Conexant CX20752 Page 43
Page 43 USB Board
EC
ITE IT8586E-LQFP
Page 44
Sub-board ( for 15")
HP&Mic Combo Conn.
POWER BOARD
USB Board
Touch Pad Int.KBD Thermal Sensor
Page 45 Page 45 NCT7718W USB Board
Page 39

ODD Board
4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 Block Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
ACLU9
Date: Monday, December 23, 2013 Sheet 2 of 59
A B C D E
 A B C D E

Voltage Rails ( O --> Means ON , X --> Means OFF )

+5VS
SIGNAL
Power Plane +3VS STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
+1.5VS
+3VALW_SOC Full ON HIGH HIGH HIGH HIGH ON ON ON ON
+1.05VS
B+ +3VALW +1.0VALW +1.35V
+0.68VS S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
+3VL +5VALW +1.8VALW
1
CPU_CORE 1
S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
State GFX_CORE
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF

S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF

S0 O O O O O
S3 O O O O X
USB Port Table BOM Structure Table
S5 S4/AC Only O O O X X USB 2.0 USB 3.0 Port
3 External BOM Structure BTO Item
USB Port
AOAC@ AOAC support part
0 USB Port (Left Side) OPT@ GPU Part
S5 S4 O X X X X XHCI UMA@ UMA SKU ID part
Battery only 1 1 USB Port (Right Side)
14@ For 14" part
S5 S4 EHCI1
2
USB Port (Left Side) 15@ For 15" part
AC & Battery X X X X X 3 USB HUB 100M@ 100M LAN part
2 2

don't exist N15SGT@ N15SGT Part

N15VGM@ N15GSM Part
SIGNAL GIGA@ GIGA LAN Part
STATE SLP_S1# SLP_S3# SLP_S4# +VALW +VALW_PCH +V +VS Clock
GC6@ GPU GC6 Part
Full ON HIGH HIGH HIGH ON ON ON ON ON TS@ Touch Screen part
1 Camera GPU VRAM RANKA PART
S1(Power On Suspend) ON
USB HUB RANKA@
LOW HIGH HIGH ON ON ON LOW 2 Cardreader
RANKB@ GPU VRAM RANKB PART
ON
3 BT(WLAN) Connector
S3 (Suspend to RAM) LOW LOW HIGH ON ON OFF OFF ME@
4 TOUCH PANEL COST DOWN
S4 (Suspend to Disk) LOW LOW LOW ON ON OFF OFF OFF
CD@
@ Not stuff
S5 (Soft OFF) LOW LOW LOW ON ON OFF OFF OFF

SMBUS Control Table PCIE PORT LIST H4T@ Hynix VRAM Part
M4T@ Micron VRAM Part
WLAN Thermal PCH TP Port Device
3
SOURCE VGA BATT IT8586E SODIMM WiMAX Sensor Module charger S4T@@ Samsung VRAM Part 3
1 Discrete GPU
2 Discrete GPU
EC_SMB_CK1 IT8586E V 3 WLAN
EC_SMB_DA1 +3VALW X V +3VALW X X X X X V
4 LAN
5
EC_SMB_CK2 IT8586E V V
X X X V X X X 6
EC_SMB_DA2 +3VS +3VGS +3VS +3VS 7
8
PCH_SMB_CLK PCH
PCH_SMB_DATA +3VALW_PCH X X X V V X V X X
+3VS +3VS +3VALW_PCH

EC SM Bus1 address EC SM Bus2 address PCH SM Bus address

Device Address
Device Device Address DDR DIMMA 1001 000Xb
4 4
Smart Battery 0001 011X b Thermal Sensor EMC1403-2 1001_100xb
Charger need to update VGA 0x9E Wlan Rsvd
PCH 0x96 TP need to update

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 Notes List

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
ACLU9
Date: Monday, December 23, 2013 Sheet 3 of 59
A B C D E
 5 4 3 2 1

Port
UC1C
Port 0 DDI PROCESSOR Pin Names HDMI* Mapping
AV3 AG3
DDI0_TXP_0 HDMI_TX2+
{34} HDMI_TX2+ HDMI_TX2+ CPU_EDP_TX0+
DDI0_TXP_0 V1P0Sx DDI1_TXP_0 CPU_EDP_TX0+ {33} DDI0_TXN_0 HDMI_TX2-
HDMI D2 {34} HDMI_TX2- HDMI_TX2- AV2 V1P0Sx AG1 CPU_EDP_TX0-
DDI0_TXN_0 V1P0Sx DDI1_TXN_0 CPU_EDP_TX0- {33}
{34} HDMI_TX1+ HDMI_TX1+ AT2 V1P0Sx AF3 CPU_EDP_TX1+
CPU_EDP_TX1+ {33} EDP DDI0_TXP_1 HDMI_TX1+
HDMI_TX1- AT3 DDI0_TXP_1 V1P0Sx V1P0Sx DDI1_TXP_1 AF2 CPU_EDP_TX1-
HDMI D1 {34} HDMI_TX1-
AR3 DDI0_TXN_1 V1P0Sx DDI1_TXN_1 AD3
CPU_EDP_TX1- {33} DDI0_TXN_1 HDMI_TX1-
{34} HDMI_TX0+ HDMI_TX0+ V1P0Sx
HDMI_TX0- AR1 DDI0_TXP_2 V1P0Sx V1P0Sx DDI1_TXP_2 AD2 DDI0_TXP_2 HDMI_TX0+
HDMI D0 {34} HDMI_TX0-
AP3 DDI0_TXN_2 V1P0Sx DDI1_TXN_2 AC3 DDI0_TXN_2 HDMI_TX0-
{34} HDMI_CLK+ HDMI_CLK+ V1P0Sx
HDMI_CLK- AP2 DDI0_TXP_3 V1P0Sx DDI1_TXP_3 AC1
HDMI CLK {34} HDMI_CLK- DDI0_TXN_3 V1P0Sx
V1P0Sx
DDI1_TXN_3
DDI0_TXP_3 HDMI_CLK+
V1P0Sx
DDI0_TXP_3 HDMI_CLK-
AL3 AK3 CPU_EDP_AUX
AL1 DDI0_AUXP V1P0Sx V1P0Sx DDI1_AUXP AK2 CPU_EDP_AUX# CPU_EDP_AUX {33} DDI0_HPD HDMI_HPD
DDI0_AUXN V1P0Sx V1P0Sx DDI1_AUXN CPU_EDP_AUX# {33} DDI0_DDCDATA DDPB_DAT
{34} HDMI_HPD D27 K30 EDP_HPD DDI0_DDCCLK DDPB_CLK
DDI0_HPD V1P8S V1P8S DDI1_HPD
C26 P30 DDI1_DDCDATA DDI1_DDCDATA {12} Port
{34} DDPB_DATA DDI0_DDCDATA V1P8S DDI1_DDCDATA
C28 V1P8S G30 1 @ TP11
{34} DDPB_CLK DDI0_DDCCLK V1P8S V1P8S DDI1_DDCCLK Port 1 DDI PROCESSOR Pin Names EDP* Mapping
B28 N30 PCH_LCD_VDDEN_Q
DDI1_TXP_0 CPU_EDP_TX0+
D D
C27 DDI0_VDDEN V1P8S V1P8S DDI1_VDDEN J30 PCH_BKLT_EN_Q DDI1_TXN_0 CPU_EDP_TX0-
DDI0_RCOMP_N B26 DDI0_BKLTEN V1P8S V1P8S DDI1_BKLTEN M30 PCH_BKLT_CTRL_Q DDI1_TXP_1 CPU_EDP_TX1+
DDI0_BKLTCTL V1P8S V1P8S DDI1_BKLTCTL DDI1_TXN_1 CPU_EDP_TX1-
1

RC1 DDI0_RCOMP_N AK13 AH14 DDI1_AUXP CPU_EDP_AUX

402_0402_1% DDI0_RCOMP_P AK12 DDI0_RCOMP V1P0Sx RESERVED_AH14 AH13 DDI1_AUXN CPU_EDP_AUX#
AM14 DDI0_RCOMP_P V1P0Sx RESERVED_AH13 AF14
RESERVED_AM14 RESERVED_AF14
DDI1_HPD EDP_HPD
AM13 AF13
2

DDI0_RCOMP_P AM3 RESERVED_AM13 RESERVED_AF13 AH3

AM2 VSS_AM3 RESERVED_VSS0 RESERVED_VSS2 VSS_AH3 AH2
VSS_AM2 RESERVED_VSS1 RESERVED_VSS3 VSS_AH2
BA3 CRT_R
VGA_RED CRT_R {36}
AY2 CRT_B
VGA_BLUE CRT_B {36}
BA1 CRT_G
VGA_GREEN AW1 CRT_G {36}
CRT_IREF
VGA_IREF AY3
VGA_IRTN
BD2 VGA_HS
VGA_HSYNC VGA_HS {36}
VVGA_GPIO BF2 VGA_VS
VVGA_GPIO VGA_VSYNC VGA_VS {36} +3VS
BC1 VGA_DDC_CLK VGA_DDC_CLK {36}
VVGA_GPIO VGA_DDCCLK BC2 VGA_DDC_DAT
VGA_DDCDATA VGA_DDC_DAT {36}
VVGA_GPIO
T2 T7
T3 RESERVED_T2 RESERVED_T7 T9
AB3 RESERVED_T3 RESERVED_T9 AB13 RPC16
AB2 RESERVED_AB3 RESERVED_AB13 AB12 VGA_DDC_CLK 3 2
Y3 RESERVED_AB2 RESERVED_AB12 Y12 VGA_DDC_DAT 4 1
Y2 RESERVED_Y3 RESERVED_Y12 Y13 2.2K_0404_4P2R_5%
W3 RESERVED_Y2 RESERVED_Y13 V10
W1 RESERVED_W3 RESERVED_V10 V9 CRT_R RC5 2 1 150_0402_1%
V2 RESERVED_W1 RESERVED_V9 T12
V3 RESERVED_V2 RESERVED_T12 T10 CRT_B RC6 2 1 150_0402_1%
R3 RESERVED_V3 RESERVED_T10 V14
R1 RESERVED_R3 RESERVED_V14 V13 CRT_G RC7 2 1 150_0402_1%
AD6 RESERVED_R1 RESERVED_V13 T14
AD4 RESERVED_AD6 RESERVED_T14 T13
AB9 RESERVED_AD4 RESERVED_T13 T6
AB7 RESERVED_AB9 RESERVED_T6 T4 CRT_IREF RC4 1 2 357_0402_1%
Y4 RESERVED_AB7 RESERVED_T4 P14
Y6 RESERVED_Y4 RESERVED_P14
V4 RESERVED_Y6 need to change 357 1%
V6 RESERVED_V4 K34
GPIO_NC13 A29 RESERVED_V6 V1P8S RESERVED_K34 D32
C {12} GPIO_NC13 C29 GPIO_S0_NC13 RESERVED_A29 RESERVED_D32 GPIO_S0_NC26 N32 C
AB14 GPIO_S0_NC14_C29 RESERVED_C29 RESERVED_N32 GPIO_S0_NC25 J34
B30 RESERVED_AB14 RESERVED_J34 GPIO_S0_NC24 K28
C30 GPIO_S0_NC12 V1P8S RESERVED_K28 GPIO_S0_NC23 F28 XDP
RESERVED_C30 RESERVED_F28 GPIO_S0_NC22 F32
change dual mos to one mos RESERVED_F32 GPIO_S0_NC21
GPIO_S0_NC20
D34
RESERVED_D34 J28
RESERVED_J28 GPIO_S0_NC18 D28
RESERVED_D28 GPIO_S0_NC17 M32
RESERVED_M32 GPIO_S0_NC16 F34
RESERVED_F34 GPIO_S0_NC15
BAY-TRAIL-M-SOC_FCBGA1170 3 OF 13 REV = 1.15 ?
@

R4602 change from 10K to 1K,

as Vienna
+3VALW +3VS +1.8VS

2
R4602
3
4

1K_0402_1%
RPC24
10K_0404_4P2R_5%

1
2
1

EDP_HPD
PCH_ENVDD {33}
D2 3

QC1B
5 G2 PJT138K_SOT363-6

1
D
QC3 2
CPU_EDP_HPD {33}
4 S2

G
D1 6

QC1A S 2N7002KW_SOT323-3

1
PCH_LCD_VDDEN_Q 2 G1 PJT138K_SOT363-6
0604 R4603
100K_0402_5%
1 S1

2
B B

EDP_HPD
+1.8VALW +3VS +3VALW +3VS
4
3

1
1

RC972
RPC25 RC973
10K_0404_4P2R_5% 10K_0402_5% 10K_0402_5%
1
2

2
2

PCH_ENBKL {33} PCH_EDP_PWM {33}

D2 3

D2 3

QC2B QC198B
5 G2 PJT138K_SOT363-6 5 G2 PJT138K_SOT363-6
4 S2

4 S2
D1 6

D1 6

QC2A QC198A
PCH_BKLT_EN_Q 2 G1 PJT138K_SOT363-6 PCH_BKLT_CTRL_Q 2 G1 PJT138K_SOT363-6
1 S1

1 S1

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/03/26 Deciphered Date 2013/02/01 SOC (DDI,EDP)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
ACLU9
Date: Monday, December 23, 2013 Sheet 4 of 59
5 4 3 2 1
 5 4 3 2 1

DDRA_DQ[63:0] {14}

DDRA_MA[15:0] {14}

DDRA_DQS[7:0] {14}

DDRA_DQS#[7:0] {14}

DDRA_DM[7:0] {14}

UC1A
UC1B
DDRA_MA0 K45 M36 DDRA_DQ0
DDRA_MA1 H47 DRAM0_MA_00 DRAM0_DQ_00 J36 DDRA_DQ1 AY45 BG38
DDRA_MA2 L41 DRAM0_MA_11 DRAM0_DQ_11 P40 DDRA_DQ2 BB47 DRAM1_MA_00 DRAM1_DQ_00 BC40
DDRA_MA3 H44 DRAM0_MA_22 DRAM0_DQ_22 M40 DDRA_DQ3 AW41 DRAM1_MA_11 DRAM1_DQ_11 BA42
DDRA_MA4 H50 DRAM0_MA_33 DRAM0_DQ_33 P36 DDRA_DQ4 BB44 DRAM1_MA_22 DRAM1_DQ_22 BD42
D
DDRA_MA5 G53 DRAM0_MA_44 DRAM0_DQ_44 N36 DDRA_DQ5
Group 0 BB50 DRAM1_MA_33 DRAM1_DQ_33 BC38 D

DDRA_MA6 H49 DRAM0_MA_55 DRAM0_DQ_55 K40 DDRA_DQ6 BC53 DRAM1_MA_44 DRAM1_DQ_44 BD36
DDRA_MA7 D50 DRAM0_MA_66 DRAM0_DQ_66 K42 DDRA_DQ7 BB49 DRAM1_MA_55 DRAM1_DQ_55 BF42
DDRA_MA8 G52 DRAM0_MA_77 DRAM0_DQ_77 B32 DDRA_DQ8 BF50 DRAM1_MA_66 DRAM1_DQ_66 BC44
DDRA_MA9 E52 DRAM0_MA_88 DRAM0_DQ_88 C32 DDRA_DQ9 BC52 DRAM1_MA_77 DRAM1_DQ_77 BH32
DDRA_MA10 K48 DRAM0_MA_99 DRAM0_DQ09_C32 C36 DDRA_DQ10 BE52 DRAM1_MA_88 DRAM1_DQ_88 BG32
DDRA_MA11 E51 DRAM0_MA_1010 DRAM0_DQ_1010 A37 DDRA_DQ11 AY48 DRAM1_MA_99 DRAM1_DQ_99 BG36
DDRA_MA12 F47 DRAM0_MA_1111 DRAM0_DQ_1111 C33 DDRA_DQ12 BE51 DRAM1_MA_1010 DRAM1_DQ_1010 BJ37
DDRA_MA13 J51 DRAM0_MA_1212 DRAM0_DQ_1212 A33 DDRA_DQ13
Group 1 BD47 DRAM1_MA_1111 DRAM1_DQ_1111 BG33
DDRA_MA14 B49 DRAM0_MA_1313 DRAM0_DQ_1313 C37 DDRA_DQ14 BA51 DRAM1_MA_1212 DRAM1_DQ_1212 BJ33
DDRA_MA15 B50 DRAM0_MA_1414 DRAM0_DQ_1414 B38 DDRA_DQ15 BH49 DRAM1_MA_1313 DRAM1_DQ_1313 BG37
DRAM0_MA_1515 DRAM0_DQ_1515 F36 DDRA_DQ24 BH50 DRAM1_MA_1414 DRAM1_DQ_1414 BH38
DDRA_DM0 G36 DRAM0_DQ_1616 G38 DDRA_DQ25 DRAM1_MA_1515 DRAM1_DQ_1515 AU36
DDRA_DM1 B36 DRAM0_DM_00 DRAM0_DQ_1717 F42 DDRA_DQ26 BD38 DRAM1_DQ_1616 AT36
DDRA_DM3 F38 DRAM0_DM_11 DRAM0_DQ_1818 J42 DDRA_DQ27 BH36 DRAM1_DM_00 DRAM1_DQ_1717 AV40
Swap Group 2 to Group 3 DRAM0_DM_22 DRAM0_DQ_1919 DRAM1_DM_11 DRAM1_DQ_1818
DDRA_DM2 B42 G40 DDRA_DQ28 Group 3 BC36 AT40
DDRA_DM4 P51 DRAM0_DM_33 DRAM0_DQ_2020 C38 DDRA_DQ29 BH42 DRAM1_DM_22 DRAM1_DQ_1919 BA36
DDRA_DM6 V42 DRAM0_DM_44 DRAM0_DQ_2121 G44 DDRA_DQ30 AT51 DRAM1_DM_33 DRAM1_DQ_2020 AV36
DDRA_DM7 Y50 DRAM0_DM_55 DRAM0_DQ_2222 D42 DDRA_DQ31 AM42 DRAM1_DM_44 DRAM1_DQ_2121 AY42
Swap Group to 6\7\5 DRAM0_DM_66 DRAM0_DQ_2323 DRAM1_DM_55 DRAM1_DQ_2222
DDRA_DM5 Y52 A41 DDRA_DQ16 Swap Group 2 to Group 3 AK50 AY40
DRAM0_DM_77 DRAM0_DQ_2424 C41 DDRA_DQ17 AK52 DRAM1_DM_66 DRAM1_DQ_2323 BJ41
M45 DRAM0_DQ_2525 A45 DDRA_DQ18 DRAM1_DM_77 DRAM1_DQ_2424 BG41
{14} DDRA_RAS# M44 DRAM0_RAS DRAM0_DQ_2626 B46 AV45 DRAM1_DQ_2525 BJ45
DDRA_DQ19
{14} DDRA_CAS# H51 DRAM0_CAS DRAM0_DQ_2727 C40 AV44 DRAM1_RAS DRAM1_DQ_2626 BH46
DDRA_DQ20 Group 2
{14} DDRA_WE# DRAM0_WE DRAM0_DQ_2828 B40 DDRA_DQ21 BB51 DRAM1_CAS DRAM1_DQ_2727 BG40
K47 DRAM0_DQ_2929 B48 DDRA_DQ22 DRAM1_WE DRAM1_DQ_2828 BH40
{14} DDRA_BS0# K44 DRAM0_BS_00 DRAM0_DQ_3030 B47 AY47 DRAM1_DQ_2929 BH48
DDRA_DQ23
{14} DDRA_BS1# D52 DRAM0_BS_11 DRAM0_DQ_3131 K52 AY44 DRAM1_BS_00 DRAM1_DQ_3030 BH47
DDRA_DQ32
{14} DDRA_BS2# DRAM0_BS_22 DRAM0_DQ_3232 K51 BF52 DRAM1_BS_11 DRAM1_DQ_3131 AY52
DDRA_DQ33
P44 DRAM0_DQ_3333 T52 DDRA_DQ34 DRAM1_BS_22 DRAM1_DQ_3232 AY51
{14} DDRA_CS0# DRAM0_CS_0 DRAM0_DQ_3434 T51 AT44 DRAM1_DQ_3333 AP52
DDRA_DQ35
P45 DRAM0_DQ_3535 L51 DDRA_DQ36 DRAM1_CS_0 DRAM1_DQ_3434 AP51
{14} DDRA_CS1# DRAM0_CS_2 DRAM0_DQ_3636 L53 DDRA_DQ37
Group 4 AT45 DRAM1_DQ_3535 AW51
DRAM0_DQ_3737 R51 DDRA_DQ38 DRAM1_CS_2 DRAM1_DQ_3636 AW53
C47 DRAM0_DQ_3838 R53 DDRA_DQ39 DRAM1_DQ_3737 AR51
{14} DDRA_CKE0 D48 DRAM0_CKE_00 DRAM0_DQ_3939 T47 BG47 DRAM1_DQ_3838 AR53
DDRA_DQ48
F44 RESERVED_D48 DRAM0_DQ_4040 T45 DDRA_DQ49 BE46 DRAM1_CKE_00 DRAM1_DQ_3939 AP47
{14} DDRA_CKE1 E46 DRAM0_CKE_22 DRAM0_DQ_4141 Y40 BD44 RESERVED_BE46 DRAM1_DQ_4040 AP45
C DDRA_DQ50 C
RESERVED_E46 DRAM0_DQ_4242 V41 DDRA_DQ51 BF48 DRAM1_CKE_22 DRAM1_DQ_4141 AK40
T41 DRAM0_DQ_4343 T48 DDRA_DQ52
Group 6 RESERVED_BF48 DRAM1_DQ_4242 AM41
{14} DDRA_ODT0 DRAM0_ODT_0 DRAM0_DQ_4444 T50 AP41 DRAM1_DQ_4343 AP48
DDRA_DQ53
P42 DRAM0_DQ_4545 Y42 DDRA_DQ54 DRAM1_ODT_0 DRAM1_DQ_4444 AP50
{14} DDRA_ODT1 DRAM0_ODT_2 DRAM0_DQ_4646 AB40 AT42 DRAM1_DQ_4545 AK42
DDRA_DQ55
DRAM0_DQ_4747 V45 DDRA_DQ56 DRAM1_ODT_2 DRAM1_DQ_4646 AH40
M50 DRAM0_DQ_4848 V47 DDRA_DQ57 DRAM1_DQ_4747 AM45
{14} DDRA_CLK0 DRAM0_CKP_0 DRAM0_DQ_4949 Swap Group to 6\7\5 DRAM1_DQ_4848
M48 AD48 DDRA_DQ58 AV50 AM47
{14} DDRA_CLK0# DRAM0_CKN_0 DRAM0_DQ_5050 AD50 AV48 DRAM1_CKP_0 DRAM1_DQ_4949 AF48
DDRA_DQ59
DRAM0_DQ_5151 V48 DDRA_DQ60 DRAM1_CKN_0 DRAM1_DQ_5050 AF50
P50 DRAM0_DQ_5252 V50 DDRA_DQ61
Group 7 DRAM1_DQ_5151 AM48
{14} DDRA_CLK1 P48 DRAM0_CKP_2 DRAM0_DQ_5353 AB44 DDRA_DQ62 DRAM1_DQ_5252 AM50
{14} DDRA_CLK1# DRAM0_CKN_2 DRAM0_DQ_5454 Y45 AT50 DRAM1_DQ_5353 AH44
DDRA_DQ63
DRAM0_DQ_5555 V52 DDRA_DQ40 AT48 DRAM1_CKP_2 DRAM1_DQ_5454 AK45
DRAM0_DQ_5656 W51 DDRA_DQ41 DRAM1_CKN_2 DRAM1_DQ_5555 AM52
P41 DRAM0_DQ_5757 AC53 DDRA_DQ42 DRAM1_DQ_5656 AL51
{14} DDRA_DRAMRST# DRAM0_DRAMRST DRAM0_DQ_5858 AC51 DDRA_DQ43 DRAM1_DQ_5757 AG53
DRAM0_DQ_5959 W53 DDRA_DQ44 AT41 DRAM1_DQ_5858 AG51
DRAM0_DQ_6060 Y51 DDRA_DQ45
Group 5 DRAM1_DRAMRST DRAM1_DQ_5959 AL53
DRAM_VREF AF44 DRAM0_DQ_6161 AD52 DDRA_DQ46 DRAM1_DQ_6060 AK51
DRAM_VREF DRAM0_DQ_6262 AD51 DDRA_DQ47 DRAM1_DQ_6161 AF52
DRAM0_DQ_6363 DRAM1_DQ_6262 AF51
J38 DDRA_DQS0 DRAM1_DQ_6363
100K_0402_1% 2 RC19 1 ICLK_DRAM_TERMN_0 AH42 ICLK_DRAM_TERM_1 DRAM0_DQSP_00 K38 DDRA_DQS#0 BF40
100K_0402_1% 2 RC20 1 ICLK_DRAM_TERMN_1 AF42 ICLK_DRAM_TERMN DRAM0_DQSN_00 C35 DDRA_DQS1 DRAM1_DQSP_00 BD40
ICLK_DRAM_TERMN_AF42 DRAM0_DQSP_11 B34 DDRA_DQS#1 DRAM1_DQSN_00 BG35
DRAM0_DQSN_11 D40 DDRA_DQS3 DRAM1_DQSP_11 BH34
DDR_PWROK AD42 DRAM0_DQSP_22 F40 DDRA_DQS#3 DRAM1_DQSN_11 BA38
DRAM_VDD_S4_PWROK DRAM0_DQSN_22 Swap Group 2 to Group 3 DRAM1_DQSP_22
DDR_CORE_PWROK AB42 B44 DDRA_DQS2 AY38
DRAM_CORE_PWROK DRAM0_DQSP_33 C43 DDRA_DQS#2 DRAM1_DQSN_22 BH44
DRAM0_DQSN_33 N53 DDRA_DQS4 DRAM1_DQSP_33 BG43
SM_RCOMP_0 AD44 DRAM0_DQSP_44 M52 DDRA_DQS#4 DRAM1_DQSN_33 AU53
SM_RCOMP_1 AF45 DRAM_RCOMP_00 DRAM0_DQSN_44 T42 DDRA_DQS6 DRAM1_DQSP_44 AV52
SM_RCOMP_2 AD45 DRAM_RCOMP_11 DRAM0_DQSP_55 T44 DDRA_DQS#6 DRAM1_DQSN_44 AP42
DRAM_RCOMP_22 DRAM0_DQSN_55 Y47 DDRA_DQS7 DRAM1_DQSP_55 AP44
DRAM0_DQSP_66 Y48 DDRA_DQS#7 DRAM1_DQSN_55 AK47
AF40 DRAM0_DQSN_66 AB52 DDRA_DQS5 DRAM1_DQSP_66 AK48
B
AF41 RESERVED_AF40 DRAM0_DQSP_77 AA51
Swap Group to 6\7\5 DRAM1_DQSN_66 AH52 B
DDRA_DQS#5
AD40 RESERVED_AF41 DRAM0_DQSN_77 DRAM1_DQSP_77 AJ51
AD41 RESERVED_AD40 DRAM1_DQSN_77
RESERVED_AD41
1 OF 13
2 OF 13
BAY-TRAIL-M-SOC_FCBGA1170 REV = 1.15 ?
@ BAY-TRAIL-M-SOC_FCBGA1170 REV = 1.15 ?
+3VALW +1.35V @

4
3
RPC13 +3VALW
10K_0404_4P2R_5% +1.35V
1
2

4
3
+1.35V
RC23 RPC14
SM_RCOMP_2 1 2 DDR_PWROK 10K_0404_4P2R_5%

SM_RCOMP_1 0_0402_5%

1
2
1

1 RC103
RC24 SM_RCOMP_0 1 2 DDR_CORE_PWROK
3

4.7K_0402_1% QC5B D CC1

5 .1U_0402_10V6-K 0_0402_5%
2

G 2
1
2

RC25 RC26 RC27 2N7002KDWH_SOT363-6

23.2_0402_1% 29.4_0402_1% 162_0402_1% S CC18
4

3
RC28 QC16B D .1U_0402_10V6-K
6

1 2 0_0402_5% DRAM_VREF QC5A D 5 2

1

{44,55} VDDQ_PGOOD 2 G
G 2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6 S

4
1

6
1 1 S QC16A D
1

RC29 {7,44} SYS_PWROK 2

4.7K_0402_1% CC2 CC3 1 G
.1U_0402_10V6-K .1U_0402_10V6-K 2N7002KDWH_SOT363-6
A 2 2 CC19 S A
2

1
.1U_0402_10V6-K
2
DDR3 Compensation Signal
WIDTH:20MIL
SPACING: 25MIL
Length: 500Mil

Security Classification LC Future Center Secret Data Title

Issued Date 2013/03/26 Deciphered Date 2013/02/01 SOC (DDR3L)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
C 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
ACLU9
Date: Monday, December 23, 2013 Sheet 5 of 59
5 4 3 2 1
 5 4 3 2 1
+1.8VS

? Net name changed to same as ACLU1

UC1D VLV_M_D
OPT@ RPC1
SATA_PTX_DRX_P0 BF6 AY7 PCIE_CTX_GRX_P0 .1U_0402_10V6-K 2 1 CC4
{42} SATA_PTX_DRX_P0 BG7 SATA_TXP_0 PCIE_TXP_0 AY6 2 1 CC5 PCIE_CTX_C_GRX_P0 {19} 1 8
SATA_PTX_DRX_N0 PCIE_CTX_GRX_N0 .1U_0402_10V6-K LAN_CLKREQ#_Q
{42} SATA_PTX_DRX_N0 SATA_TXN_0 PCIE_TXN_0 PCIE_CTX_C_GRX_N0 {19}
HDD GPU_CLKREQ#_Q 2 7
SATA_PRX_DTX_P0 AU16 AT14 PCIE_CRX_GTX_P0 OPT@ PCIE_CRX_GTX_P0 {19} PCIE_CLKREQ_2# 3 6
{42} SATA_PRX_DTX_P0 AV16 SATA_RXP_0 PCIE_RXP_0 AT13
SATA_PRX_DTX_N0 PCIE_CRX_GTX_N0 PCIE_CRX_GTX_N0 {19} WLAN_CLKREQ#_Q 4 5
{42} SATA_PRX_DTX_N0 SATA_RXN_0 PCIE_RXN_0 OPT@ dGPU
D {42}
{42}
SATA_PTX_DRX_P1
SATA_PTX_DRX_N1
SATA_PTX_DRX_P1
SATA_PTX_DRX_N1
BD10
BF10 SATA_TXP1
SATA_TXN_1
PCIE_TXP_1
PCIE_TXN_1
AV6
AV4
PCIE_CTX_GRX_P1
PCIE_CTX_GRX_N1
.1U_0402_10V6-K
.1U_0402_10V6-K
2
2
1 CC6
1 CC7 PCIE_CTX_C_GRX_P1
PCIE_CTX_C_GRX_N1
{19}
{19}
10K_0804_8P4R_5%

+3VS
D
ODD SATA_PRX_DTX_P1 AY16 AT10 PCIE_CRX_GTX_P1 OPT@ PCIE_CRX_GTX_P1 {19}
{42} SATA_PRX_DTX_P1 BA16 SATA_RXP_1 PCIE_RXP_1 AT9
SATA_PRX_DTX_N1 PCIE_CRX_GTX_N1 PCIE_CRX_GTX_N1 {19}
{42} SATA_PRX_DTX_N1 SATA_RXN_1 PCIE_RXN_1 2 1 10K_0402_5%
LAN_CLKREQ# RC968
BB10 AT7 PCIE_PTX_DRX_P4 .1U_0402_10V6-K 2 1 CC104 WLAN_CLKREQ#RC969 2 1 10K_0402_5%
BC10 ICLK_SATA_TERMP RESERVED_VSS4 PCIE_TXP_2 AT6 2 1 CC103 PCIE_PTX_C_DRX_P4 {40}
PCIE_PTX_DRX_N4 .1U_0402_10V6-K
ICLK_SATA_TERMN RESERVED_VSS5 PCIE_TXN_2 PCIE_PTX_C_DRX_N4 {40}
CRB USE SATA_GP0 WLAN
SOC_SCI# RC32 1 2 0_0402_5% BA12 AP12 PCIE_PRX_DTX_P4
need check with BIOS ODD_DETECT#_SOC AY14 SATA_GP0 V1P8S PCIE_RXP_2 AP10 PCIE_PRX_DTX_N4
PCIE_PRX_DTX_P4 {40}
SATA_GP1 PCIE_RXN_2 PCIE_PRX_DTX_N4 {40}
only GPIO_S0_SC[0..7] can make SCI ODD_DA#_SOC AY12 V1P8S
SATA_LED V1P8S AP6 PCIE_PTX_DRX_P3 .1U_0402_10V6-K 2 1 CC105
AU18 PCIE_TXP_3 AP4 2 1 CC106 PCIE_PTX_C_DRX_P3 {37}
SATA_RCOMP_DP PCIE_PTX_DRX_N3 .1U_0402_10V6-K +1.8VS
AT18 SATA_RCOMP_P_AU18 PCIE_TXN_3 PCIE_PTX_C_DRX_N3 {37}
SATA_RCOMP_DN
SATA_RCOMP_N_AT18 AP9 PCIE_PRX_DTX_P3
PCIE_RXP_3 PCIE_PRX_DTX_P3 {37} LAN

1
AP7 PCIE_PRX_DTX_N3
PCIE_RXN_3 PCIE_PRX_DTX_N3 {37}
AT22 RC958
MMC1_CLK BB7 2.2K_0402_5%
AV20 RESERVED_VSS7 VSS_BB7 BB5
AU22 MMC1_D0 RESERVED_VSS6 VSS_BB5

2 2
AV22 MMC1_D1 BG3 GPU_CLKREQ#_Q PCIE_RCOMP_DP
AT20 MMC1_D2 V1P8S PCIE_CLKREQ_0 BD7 PCIE_CLKREQ_2#

B
MMC1_D3 PCIE_CLKREQ_1

2
AY24 V1P8S BG5 WLAN_CLKREQ#_Q
AU26 MMC1_D4 V1P8S PCIE_CLKREQ_2 BE3 LAN_CLKREQ#_Q RC31 LAN_CLKREQ#_Q 1 3

E
MMC1_D5 PCIE_CLKREQ_3 LAN_CLKREQ# {37}
AT26 V1P8S BD5

C
MMC1_D6 SD3_WP_BD5 402_0402_1% QC6
AU20
MMC1_D7 AP14 PCIE_RCOMP_DP MMBT3904WH_SOT323-3

1
AV26 PCIE_RCOMP_P_AP14_AP14 AP13 PCIE_RCOMP_DN PCIE_RCOMP_DN
BA24 MMC1_CMD PCIE_RCOMP_N_AP13_AP13
MMC1_RST BB4
RC35 1 2 49.9_0402_1% SDMMC1_RCOMP AY18 RESERVED_BB4 BB3 +1.8VS
MMC1_RCOMP RESERVED_BB3 AV10
C RESERVED_AV10
RESERVED_AV9
AV9 0607
C

1
SATA_RCOMP_DP BA18
AY20 SD2_CLK RC959
BD20 SD2_D0 BF20 HDA_RCOMP 1 RC36 2 49.9_0402_1% 2.2K_0402_5%
SD2_D1 HDA_LPE_RCOMP
1

BA20 VAUD BG22 HDA_RST_AUDIO#_R 1 RC37 2 33_0402_5%

BD18 SD2_D2 HDA_RST BH20 1 2 HDA_RST_AUDIO# {43}
RC30 VAUD HDA_SYNC_AUDIO_R RC38 33_0402_5%

2 2
BC18 SD2_D3_CD HDA_SYNC BJ21 1 2 HDA_SYNC_AUDIO {43}
402_0402_1% VAUD HDA_BITCLK_AUDIO_R RC39 33_0402_5%
SD2_CMD HDA_CLK BG20 1 2 HDA_BITCLK_AUDIO {43}
VAUD HDA_SDOUT_AUDIO_R RC40 33_0402_5%

B
VAUD HDA_SDO BG19 HDA_SDOUT_AUDIO {43}
2

HDA_SDI0 BG21 HDA_SDIN0 {43} 1 3

SATA_RCOMP_DN VAUD WLAN_CLKREQ#_Q

E
HDA_SDI1 WLAN_CLKREQ# {40}
AY26 VAUD BH18

C
AT28 SD3_CLK GPIO_S0_SC_14 HDA_DOCKRST BG18 QC7
BD26 SD3_D0 GPIO_S0_SC_15 HDA_DOCKEN MMBT3904WH_SOT323-3
AU28 SD3_D1 BF28
BA26 SD3_D2 LPE_I2S2_CLK BA30 I2S_2_FS
BC24 SD3_D3 LPE_I2S2_FRM BC30 I2S_2_FS {12}
I2S_2_TXD
AV28 SD3_CD# LPE_I2S2_DATAOUT BD28 I2S_2_TXD {12}
+1.8VS
BF22 SD3_CMD LPE_I2S2_DATAIN +1.0VS
BD22 SD3_1P8EN P34
SD3_PWREN RESERVED_P34

1
N34
RC43 1 2 49.9_0402_1% SDMMC3_RCOMP BF26 RESERVED_N34 RC42 RC960
SD3_RCOMP AK9 2.2K_0402_5%
RESERVED_AK9 73.2_0402_1%
AK7 @ OPT@
RESERVED_AK7

2 2
C24 CPU_PROCHOT#_R 1 RC44 2 0_0402_5%
V1P0_S3 PROCHOT H_PROCHOT# {44,51,52}

B
BAY-TRAIL-M-SOC_FCBGA1170 4 OF 13 REV = 1.15 ? GPU_CLKREQ#_Q 1 3

E
GPU_CLKREQ# {19}
OPT@

C
@ QC199
MMBT3904WH_SOT323-3

change mos to 3904

B B
+1.8VS

+3VALW_R

+1.8VS +1.8VS

2
1
RC95
RC967 10K_0402_5%
3
4

2.2K_0402_5% @

2
RPC9

1
G
2.2K_0404_4P2R_5%

1
G2 5

SOC_SCI# EC_SCI# {44}

2
1

D
ODD_DA#_SOC 4 S2 D2 3
ODD_DA# {42} QC13
@ PJA138K_SOT23-3
QC17B
2

PJT138K_SOT363-6
G1

ODD_DETECT#_SOC 1 S1 D1 6
ODD_DETECT# {42}
@
A +3VS QC17A
PJT138K_SOT363-6
A
@
RC957 1 2 10K_0402_5% ODD_DETECT# Title
RC965 1 2 10K_0402_5% ODD_DA# Security Classification LC Future Center Secret Data
@
Issued Date 2013/03/26 Deciphered Date 2013/02/01 SOC (PCIE&HDA&SATA&STRAPS)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
ACLU9
Date: Monday, December 23, 2013 Sheet 6 of 59

5 4 3 2 1
 5 4 3 2 1

XTAL25_IN

XTAL25_OUT
?
UC1E
RTC_X1

RTC_X2
VLV_M_D
+1.8VS
XTAL25_IN AH12 AU34 1 @ TP9
RC92 1 2 10M_0402_5% RC93 1 2 1M_0402_5% XTAL25_OUT AH10 ICLK_OSCIN SIO_UART1_RXD AV34 1 @ TP10
ICLK_OSCOUT SIO_UART1_TXD BA34 1 @ TP1
AD9 SIO_UART1_RTS AY34 1 @ TP3 PMC_RSTBTN# 1 RC73 2 10K_0402_5%
RESERVED_AD9 SIO_UART1_CTS
YC2 RC70 1 2 4.02K_0402_1% ICLK_ICOMP AD14 BF34 PMC_SUSCLK @ 1 RC83 2 10K_0402_5%
YC1 1 2 RC62 1 2 47.5_0402_1% ICLK_RCOMP AD13 ICLK_ICOMP SIO_UART2_RXD BD34
1 4 ICLK_RCOMP SIO_UART2_TXD BD32 EC_RSMRST# 2 RC930 1 100K_0402_5%
32.768KHZ_12.5PF_200458-PG14 OSC1 GND2 AD10 SIO_UART2_RTS BF32
2 2 RESERVED_AD10 SIO_UART2_CTS
D CC11 1 2 3 AD12 +3VALW_R +1.8VALW EC_RSMRST# CC113 1 20.01U_0402_25V7K D
18P_0402_50V8J CC12 GND1 OSC2 RESERVED_AD12 @
1
18P_0402_50V8J CC13 CLK_PCIE_GPU# AF6
1 1 {19} CLK_PCIE_GPU# PCIE_CLKN_00
10P_0402_50V8-J CC14 CLK_PCIE_GPU AF4 D26 SUSPWRDNACK
{19} CLK_PCIE_GPU PCIE_CLKP_00 V1P8A PMC_SUSPWRDNACK

2
2 25MHZ_10PF_7V25000014 G24 PMC_SUSCLK
1,Space 15MIL 10P_0402_50V8-J 2 AF9 V1P8A PMC_SUSCLK0_G24 F18 PMC_SLP_S0IX# 1 TP4 0604 RC60 RC61
PCIE_CLKN_11 PMC_SLP_S0IX

2
2,No trace under crystal AF7 V1P8A F22 PMC_SLP_S4# @ 10K_0402_5% 2.2K_0402_5%
PCIE_CLKP_11 PMC_SLP_S4

G
V1P8A D22 PMC_SLP_S3# @ for ACINneed check with power team
CRYSTAL 3,place on oppsosit side of MCP for temp influence V1P8A PMC_SLP_S3 J20 GPIO_S514_J20 1 RC71 2 10K_0402_5% +1.8VALW

1
GPIO_S514_J20

1
CLK_PCIE_WLAN# AK4 GPIO_S5_14 V1P8A D20 PMC_ACIN PMC_ACIN RC69 1 @ 2
{40} CLK_PCIE_WLAN# PCIE_CLKN_22 PMC_ACPRESENT AC_PRESENT {44}
AK6 V1P8A F26 0_0402_5%

D
CLK_PCIE_WLAN PMC_PCIE_WAKE#
{40} CLK_PCIE_WLAN PCIE_CLKP_22 PMC_WAKE_PCIE_0
V1P8A K26 PMC_BATLOW# 1 RC72 2 10K_0402_5% +1.8VALW @
PMC_BATLOW

2
+1.8VALW CLK_PCIE_LAN# AM4 V1P8A J26 PMC_PWRBTN#
{37} CLK_PCIE_LAN# PCIE_CLKN_33 PMC_PWRBTN QC203
CLK_PCIE_LAN AM6 V1P8A BG9 PMC_RSTBTN# RC63
{37} CLK_PCIE_LAN PCIE_CLKP_33 PMC_RSTBTN PJA138K_SOT23-3
Internal 20K(H) V1P8S F20 PMC_PLTRST# 10K_0402_5%
PMC_PLTRST

1
RC82 1 2 0_0402_5% +1.8VALW_SPI AM10 V1P8A J24 @ D QC9
AM9 RESERVED_AM10 GPIO_S5_17 V1P8A GPIO_S517_J24 G18 1 @ TP5 2 0605
ACIN# {44,53}

1
+1.8VALW_SPI RESERVED_AM9 V1P8A PMC_SUS_STAT G
RPC15
S 2N7002KW_SOT323-3

3
1 8 SPI_WP# C11 RTC_RST#
2 7 SPI_HOLD# BH7 ILB_RTC_TEST
3 6 PCH_SPI_CS0# BH5 PMC_PLT_CLK_00
4 5 BH4 PMC_PLT_CLK_11
BH8 PMC_PLT_CLK_22 B10 EC_RSMRST#
PMC_PLT_CLK_33 PMC_RSMRST EC_RSMRST# {44}
2.2K_0804_8P4R_5% BH6 VRTC B7 SYS_PWROK SYS_PWROK {5,44}
BJ9 PMC_PLT_CLK_44 VRTC PMC_CORE_PWROK
change 3.3K to 2.2K 4R8P PMC_PLT_CLK_55
SRTC_RST# C12
+1.8VALW_SPI ILB_RTC_RST C9 RTC_X1
UC2 D14 ILB_RTC_X1 A9 RTC_X2
50mA TAP_TCK ILB_RTC_X2
RC85 PCH_SPI_CS0# 1 8 G12 B8 BVCCRTC_EXTPAD CC17 1 2 .1U_0402_10V6-K
PCH_SPI_SO_R 1 2 PCH_SPI_SO 2 CS# VCC 7 SPI_HOLD# F14 TAP_TRST ILB_RTC_EXTPAD
SO(IO1) HOLD#(IO3) 1 TAP_TMS
22_0402_5% SPI_WP# 3 6 PCH_SPI_CLK F12
4 WP#(IO2) SCLK 5 PCH_SPI_SI CC8 G16 TAP_TDI
VSS SI(IO0) D18 TAP_TDO
2
.1U_0402_10V6-K XDP TAP_PRDY
F16 B24 CPU_SVID_ALRT#_R 1 RC78 2 20_0402_1% CPU_SVID_ALERT# {59}
GD25LQ64CVIGR_TSOP8 AT34 TAP_PREQ V1P0S SVID_ALERT A25 CPU_SVID_DAT_R 1 RC79 2 16.9_0402_1%
RESERVED SVID_DATA CPU_SVID_DAT {59}
0605 V1P0S C25 CPU_SVID_CLK_R 1 RC80 2 0_0402_5%
C SPI ROM PCH_SPI_CS0# RC81 1 2 22_0402_5%PCH_SPI_CS0#_R C23 V1P0S SVID_CLK CPU_SVID_CLK {59} C

C21 PCU_SPI_CS_00 V1P8A

PCH_SPI_SO_R B22 PCU_SPI_CS_11 V1P8A AU32
PCH_SPI_SI RC84 1 2 22_0402_5%PCH_SPI_SI_R A21 PCU_SPI_MISO V1P8A SIO_PWM_00 AT32
PCU_SPI_MOSI SIO_PWM_11 need check power part if RES is staffed
VCCRTC PCH_SPI_CLK RC88 1 2 22_0402_5%PCH_SPI_CLK_R C22 V1P8A
PCU_SPI_CLK V1P8A

SRTC_RST# RC89 1 2 20K_0402_1% SOC_KBRST# B18

B16 GPIO_S5_0 V1P8A K24
C18 GPIO_S5_1 V1P8A V1P8A GPIO_S5_22 N24
RTC_RST# RC90 1 2 20K_0402_1% A17 GPIO_S5_2 V1P8A V1P8A GPIO_S5_23 M20
SOC_LID_OUT# C17 GPIO_S5_3 V1P8A V1P8A GPIO_S5_24 J18
C16 GPIO_S5_4 V1P8A V1P8A GPIO_S5_25 M18
B14 GPIO_S5_5 V1P8A V1P8A GPIO_S5_26 K18
GPIO_S5_6 GPIO_S5_27
1U_0402_6.3V6K

1U_0402_6.3V6K

JME1 1 1 SOC_SMI# C15 V1P8A V1P8A K20

GPIO_S5_7 GPIO_S5_28
1

1
CC10

SHORT PADS JCMOS1 V1P8A V1P8A M22

GPIO_S5_29
CC9

@ SHORT PADS V1P8A M24

@ V1P8A GPIO_S5_30 +1.8VALW +3VALW
2

2 2 C13
JCMOS/JCMOS1 GPIO_S5_8
Place under Bottom A13 V1P8A
C19 GPIO_S5_9 V1P8A AV32
GPIO_S5_10 V1P8A V1P8S SIO_SPI_CS BA28
RTCRST#
V1P8S SIO_SPI_MISO

1
Space 15Mil AY28
RC91 1 2 49.9_0402_1% GPIO_RCOMP18 N26 V1P8S SIO_SPI_MOSI AY30 RC927 RC793
GPIO_RCOMP V1P8S SIO_SPI_CLK 10K_0402_5% 10K_0402_5%
RTC RST#

2
BAY-TRAIL-M-SOC_FCBGA1170 5 OF 13 REV = 1.15 ?

2
G
The ALT_GPIO_SMI.CORE_GPIO_SMI_STS@ [31:24] & ALT_GPIO_SMI.CORE_GPIO_SMI _EN[15:8] register bits correspond
to GPIO_S0_SC[7:0]. ALT_GPIO_SMI.SUS_GPIO_SMI_STS[23:16] & ALT_GPIO_SMI.SUS_GPIO_SMI_EN[7:0] correspond

1
PMC_PCIE_WAKE# PCIE_WAKE# {37,40,44}
to GPIO_S5[7:0].

D
+3VALW +3VS
QC168
PJA138K_SOT23-3
3
4

B RPC17 B
10K_0404_4P2R_5% +1.8VALW
+3VALW_R
2
1

PLT_RST# {19,37,40,44}

2
D2 3

RC75 RC74
2

QC15B 10K_0402_5% 10K_0402_5%

2
5 G2 PJT138K_SOT363-6 RC104

G
100K_0402_5%

1
3
4 S2

1
SUSPWRDNACK
SUSWARN# {44}
1
D1 6

D
QC15A @
PMC_PLTRST# 2 G1 PJT138K_SOT363-6 QC10
PJA138K_SOT23-3
1 S1

+1.8VALW +1.8VALW +3VALW_R +1.8VALW +3VALW

+1.8VALW +3VALW_R +1.8VALW +1.8VALW +3VALW_R

+1.8VALW

3
4

2
3
4
RPC2 RC933

1
10K_0404_4P2R_5% RPC3 10K_0402_5%
3
4

3
4

@ 10K_0404_4P2R_5% RC932
3
4

3
4

2
0605 RPC6 RPC7 QC11A 2.2K_0402_5% @

2
1

1
G
0603 RPC4 RPC5 @

G1
2.2K_0404_4P2R_5% 10K_0404_4P2R_5%

2
1
10K_0404_4P2R_5% 10K_0404_4P2R_5%

2
2

1
PMC_SLP_S3# 1 S1 D1 6 PMC_SUSCLK
PM_SLP_S3# {44} SUSCLK {40}
2
1

2
1

D
G1

G1
2
1

2
1

A @ A
SOC_SMI# 1 S1 D1 6 SOC_KBRST# 1 S1 D1 6 KBRST# {44} PJT138K_SOT363-6
EC_SMI# {44} QC200
PJA138K_SOT23-3

G2 5
QC14A QC12A
G2 5

G2 5

0801 EC_INT_SERIRQ need change to level shift QC11B

PJT138K_SOT363-6 PJT138K_SOT363-6 PMC_SLP_S4# 4 S2 D2 3 Bay trail plaform susclk is 1.8VSA level, NGFF card need 3.3V
PM_SLP_S4# {44}
SOC_LID_OUT# 4 S2 D2 3 EC_LID_OUT# {44} PMC_PWRBTN# 4 S2 D2 3 PBTN_OUT# {44} PJT138K_SOT363-6

Security Classification LC Future Center Secret Data Title

QC14B QC12B
PJT138K_SOT363-6 PJT138K_SOT363-6 Issued Date 2013/03/26 Deciphered Date 2013/02/01 SOC (RTC&SPI&PM)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
ACLU9
Date: Thursday, December 26, 2013 Sheet 7 of 59
5 4 3 2 1

0801 EC_INT_SERIRQ need change to level shift

 5 4 3 2 1

? +3VS
UC1F VLV_M_D +1.8VS

G2 M10
GPIO_S5_31 V1P8A RESERVED_M10 M9 +3VS
RESERVED_M9

1
+1.8VS

2
PCH_CMOS_ON#_Q M3 P7 RC971
ODD_EN L1 GPIO_S5_32 V1P8A RESERVED_P7 P6 RC956 2.2K_0402_5%
{42} ODD_EN GPIO_S5_33 RESERVED_P6
K2 V1P8A 10K_0402_5% OPT@
GPIO_S5_34

1
K3 V1P8A OPT@

2
GPIO_S5_35

2
M2 V1P8A M7 RC970

1
GPIO_S5_36 RESERVED_M7

G
N3 V1P8A M12 USB3_P1_REXT 1 RC110 2 1.24K_0402_1% RC948 2.2K_0402_5%
P2 GPIO_S5_37 V1P8A USB3_REXT0 OPT@
10K_0402_5%
GPIO_S5_38

1
L3 V1P8A P10 OPT@ PXS_PWREN_SOC
PXS_PWREN {21,58}

2
GPIO_S5_39 RESERVED_P10

2
V1P8A P12

D
1
RESERVED_P12

G
M4
RESERVED_M4 QC8

1
D PCB_ID0 J3 M6 PXS_RST#_SOC D
GPIO_S5_40 RESERVED_M6 PXS_RST# {19} PJA138K_SOT23-3
PCB_ID1 P3 V1P8A

D
PCB_ID2 H3 GPIO_S5_41 V1P8A D4 USB30_RX_P1
USB30_RX_P1 {41} OPT@
PCB_ID3 B12 GPIO_S5_42 V1P8A USB3_RXP0 E3 USB30_RX_N1
GPIO_S5_43 V1P8A USB3_RXN0 USB30_RX_N1 {41} QC4
LEFT USB (3.0)

1
K6 USB30_TX_P1 PJA138K_SOT23-3 D
USB3_TXP0 USB30_TX_P1 {41}
USB20_P1 M16 K7 USB30_TX_N1 OPT@ RC170 1 @ 2 2 QC201
{41} USB20_P1 USB_DP0 USB3_TXN0 USB30_TX_N1 {41} {44} VGA_GATE#
USB20_N1 K16 0_0402_5% G 2N7002KW_SOT323-3
LEFT USB (3.0) {41} USB20_N1 USB_DN0
1
{45} USB20_P0 USB20_P0 J14 CC107 @ S

3
USB20_N0 G14 USB_DP1 .1U_0402_10V6-K
RIGHT USB (2.0) {45} USB20_N0 USB_DN1 @
USB20_P2 K12 2
{41} USB20_P2 USB_DP2
USB20_N2 J12
LEFT USB (2.0) {41} USB20_N2 USB_DN2
{16} USB20_P3 USB20_P3 K10 H8
USB20_N3 H10 USB_DP3 RESERVED_H8 H7
USB Hub {16} USB20_N3 USB_DN3 RESERVED_H7

ICLK_USB_TERMN_0 D10 H5
ICLK_USB_TERMN_1 F10 ICLK_USB_TERMN_D10 ICLK_USB_TERM_1 RESERVED_H5 H4 +3VS +3VS +3VS
ICLK_USB_TERMN RESERVED_H4

USB_OC0# C20
{41} USB_OC0# USB_OC_00

2
USB_OC1# B20 V1P8A
{45} USB_OC1# USB_OC_11 V1P8A RC115 RC116 RC112
10K_0402_5% 10K_0402_5% 10K_0402_5%
@
USB_RCOMP USBRBIAS D6 BD12 PXS_RST#_SOC

1
RC113 1 2 45.3_0402_1% C7 USB_RCOMPO V1P8S GPIO_S0_SC_55 BC12 GPIO_S0_SC_56
Width 20Mil USB_RCOMPI GPIO_S0_SC_56 GPIO_S0_SC_56 {12} PCH_WLAN_OFF# {40} PCH_BT_OFF# {40} CMOS_ON# {33}
Space 15Mil V1P8S BD14 VGA_PWRGD_SOC
V1P8S GPIO_S0_SC_57 BC14 GPIO52_SOC
Length 500Mil USB_PLL_MON M13 V1P8S GPIO_S0_SC_58 BF14 GPIO53_SOC
USB_PLL_MON V1P8S GPIO_S0_SC_59 BD16 PXS_PWREN_SOC
GPIO_S0_SC_60

D2 3
BC16

D1 6
V1P8S QC19A QC18
V1P8S GPIO_S0_SC_61 QC19B 1
B4 PCH_WLAN_OFF#_Q 2 G1 PCH_BT_OFF#_Q 5 G2 PJT138K_SOT363-6 D
B5 USB_HSIC0_DATA BH12 PCH_CMOS_ON#_Q 2
C USB_HSIC0_STROBE ILB_8254_SPKR PCH_BEEP {43} C
V1P8S G

1 S1

4 S2
S
E2 @
USB_HSIC1_DATA PJT138K_SOT363-6 3
D2
USB_HSIC1_STROBE BH22 PJA138K_SOT23-3
V1P8S SIO_I2C0_DATA BG23
RC114 1 2 45.3_0402_1% USB_HSIC_RCOMP A7 V1P8S SIO_I2C0_CLK
USB_HSIC_RCOMP
BG24
V1P8S SIO_I2C1_DATA BH24
RC117 1 2 49.9_0402_1% RCOMP_LPC_HVT BF18 V1P8S SIO_I2C1_CLK
BH16 LPC_RCOMP VLPC
{44} LPC_AD0 ILB_LPC_AD_00
BJ17 VLPC BG25
{44} LPC_AD1 ILB_LPC_AD_11 SIO_I2C2_DATA
BJ13 VLPC V1P8S BJ25
{44} LPC_AD2 ILB_LPC_AD_22 SIO_I2C2_CLK
BG14 VLPC V1P8S
{44} LPC_AD3 ILB_LPC_AD_33
BG17 VLPC
{44} LPC_FRAME# ILB_LPC_FRAME
RC118 1 2 22_0402_5% PCH_PCI_CLK_R BG15 VLPC BG26
{44} CLK_PCI_EC ILB_LPC_CLK_00 SIO_I2C3_DATA
BH14 VLPC V1P8S BH26
BG16 ILB_LPC_CLK_11 VLPC V1P8S SIO_I2C3_CLK +1.8VS +1.8VS
SOC_SERIRQ RC119 1 2 0_0402_5% BG13 ILB_LPC_CLKRUN VLPC +1.8VS
ILB_LPC_SERIRQ V1P8S BF27
V1P8S SIO_I2C4_DATA BG27
V1P8S SIO_I2C4_CLK

3
4
1
BH28 RPC8
PCH_SMB_DATA BG12 V1P8S SIO_I2C5_DATA BG28 RC966
PCU_SMB_DATA V1P8S SIO_I2C5_CLK 2.2K_0404_4P2R_5%
PCH_SMB_CLK BH10 V1P8S 2.2K_0402_5% GC6@
PCU_SMB_CLK

2
PCH_SMB_ALERT# BG11 V1P8S @

2
1
PCU_SMB_ALERT V1P8S

2
BJ29

G1
2
SIO_I2C6_DATA

G
V1P8S BG29
V1P8S SIO_I2C6_CLK GPIO52_SOC 1 S1 D1 6
GPIO52 {19}

1
6 OF 13 VGA_PWRGD_SOC
VGA_PWRGD {22,44}
BH30

D
PCH_WLAN_OFF#_Q
V1P8S GPIO_S0_SC_092 BG30 PCH_BT_OFF#_Q
BAY-TRAIL-M-SOC_FCBGA1170 GPIO_S0_SC_093 ? QC21A

G2 5
V1P8S
REV = 1.15 QC204 PJT138K_SOT363-6
@ PJA138K_SOT23-3 GC6@
B B
@ GPIO53_SOC 4 S2 D2 3
GPIO53 {19}
PCB_ID0 PCB_ID1 PCB_ID2 PCB_ID3 Description
Reserve for GPU
+1.8VS QC21B
0 Reserve Reserve UMA SKU PJT138K_SOT363-6
RC120 1 210K_0402_5% PCH_SMB_ALERT# GC6@

1 Reserve Reserve GPU SKU

+1.8VALW
RPC18
4 1 USB_OC0# 0 Reserve Reserve 14 panel
3 2 USB_OC1#
10K_0404_4P2R_5% +1.8VS +1.8VS +3VS
+3VS RC964 1 2 10K_0402_5% ODD_EN 1 Reserve Reserve 15 panel
@

+1.8VALW CC108
4 1 RPC19 GPIO52 PCH_PCI_CLK_R 1 2

3
4

3
4
3 2 GPIO53
10K_0404_4P2R_5% 10P_0402_50V8-J RPC22 RPC23
GC6@ @ 2.2K_0404_4P2R_5% 2.2K_0404_4P2R_5%

2
2
1

2
1
+1.8VS +3VS +1.8VS

G1
2

2
2.2K_0402_5%

2.2K_0402_5%

2.2K_0402_5%

2.2K_0402_5%

OPT@ 15@ @ @ PCH_SMB_CLK 1 S1 D1 6

RC54

RC55

RC944

RC945

SMB_CLK_S3 {14,40}
2

2
1

RC105 1 2 1K_0402_1% ICLK_USB_TERMN_0 RC96 RC97 RC98 QC20A

RC106 1 2 1K_0402_1% ICLK_USB_TERMN_1 0_0402_5% 0_0402_5% 10K_0402_5% PJT138K_SOT363-6

G2 5
RC108 1 @ 2 0_0402_5% USB_PLL_MON
PCB_ID0
1

PCB_ID1 UC3
A PCB_ID2 1 6 PCH_SMB_DATA 4 S2 D2 3 A
VCCA VCCB SMB_DATA_S3 {14,40}
PCB_ID3
Reserve for NV GPU 2 5
0610 GND EO
QC20B
2

RC954 1 @ 2 10K_0402_5% GPIO52 SOC_SERIRQ 3 4

2.2K_0402_5%

2.2K_0402_5%

2.2K_0402_5%

2.2K_0402_5%

A4 B4 SERIRQ {44} PJT138K_SOT363-6

UMA@ 14@ @ @
RC57

RC56

RC946

RC947

1 1
RC955 1 @ 2 10K_0402_5% GPIO53
CC15 CC16 EMC
G2129TL1U_SC70-6
.1U_0402_10V6-K .1U_0402_10V6-K
1

RC17 2 @ 1 100K_0402_5% PXS_PWREN 2 2

Security Classification LC Future Center Secret Data Title

RC18 1 @ 2 10K_0402_5% PXS_RST#
Issued Date 2013/03/26 Deciphered Date 2013/02/01 SOC (USB&LPC&SMB)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
SERIRQ level shift need IC, not MOS for frequence AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
PCB ID DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
ACLU9
Date: Monday, December 23, 2013 Sheet 8 of 59
5 4 3 2 1
 5 4 3 2 1

?
UC1G VLV_M_D +1.35V
+CPU_CORE
VCC_SENSE P28 BD49
{59} VCC_SENSE VCC_AXG_SENSE BB8 CORE_VCC_SENSE_P28 DRAM_VDD_S4_BD49 BD52
2 RC131 1 100_0402_1% {59} VCC_AXG_SENSE N28 UNCORE_VNN_SENSE DRAM_VDD_S4_BD52 BD53
VCC_SENSE VSS_SENSE
{59} VSS_SENSE CORE_VSS_SENSE_N28 DRAM_VDD_S4_BD53 BF44
+GFX_CORE +1.35V +1.35V DRAM_VDD_S4_BF44 BG51
DRAM_VDD_S4_BG51 BJ48
1 RC129 2 DRAM_VDD_S4_CLK AD38 DRAM_VDD_S4_BJ48 C51
2 RC130 1 100_0402_1% VCC_AXG_SENSE 0_0603_5% AF38 DRAM_VDD_S4_AD38 DRAM_VDD_S4_C51 D44
A48 DRAM_VDD_S4_AF38 DRAM_VDD_S4_D44 F49
AK38 DRAM_VDD_S4 DRAM_VDD_S4_F49 F52
AM38 DRAM_VDD_S4_AK38 DRAM_VDD_S4_F52 F53
AV41 DRAM_VDD_S4_AM38 DRAM_VDD_S4_F53 H46
D
2 RC132 1 100_0402_1% VSS_SENSE AV42 DRAM_VDD_S4_AV41 DRAM_VDD_S4_H46 M41 D

BB46 DRAM_VDD_S4_AV42 DRAM_VDD_S4_M41 M42

DRAM_VDD_S4_BB46 DRAM_VDD_S4_M42 V38
+CPU_CORE DRAM_VDD_S4_V38 Y38
DRAM_VDD_S4_Y38
AA27
AA29 CORE_VCC_S0IX_AA27
AA30 CORE_VCC_S0IX_AA29 +GFX_CORE
AC27 CORE_VCC_S0IX_AA30
AC29 CORE_VCC_S0IX_AC27 AA24
AC30 CORE_VCC_S0IX_AC29 UNCORE_VNN_S3_AA24 AC22
AD27 CORE_VCC_S0IX_AC30 UNCORE_VNN_S3_AC22 AC24
AD29 CORE_VCC_S0IX_AD27 UNCORE_VNN_S3_AC24 AD22
AD30 CORE_VCC_S0IX_AD29 UNCORE_VNN_S3_AD22 AD24
AF27 CORE_VCC_S0IX_AD30 UNCORE_VNN_S3_AD24 AF22
AF29 CORE_VCC_S0IX_AF27 UNCORE_VNN_S3_AF22 AF24
AG27 CORE_VCC_S0IX_AF29 UNCORE_VNN_S3_AF24 AG22
AG29 CORE_VCC_S0IX_AG27 UNCORE_VNN_S3_AG22 AG24
AG30 CORE_VCC_S0IX_AG29 UNCORE_VNN_S3_AG24 AJ22
P26 CORE_VCC_S0IX_AG30 UNCORE_VNN_S3_AJ22 AJ24
P27 CORE_VCC_S0IX_P26 UNCORE_VNN_S3_AJ24 AK22
U27 CORE_VCC_S0IX_P27 UNCORE_VNN_S3_AK22 AK24
U29 CORE_VCC_S0IX_U27 UNCORE_VNN_S3_AK24 AK25
V27 CORE_VCC_S0IX_U29 UNCORE_VNN_S3_AK25 AK27
V29 CORE_VCC_S0IX_V27 UNCORE_VNN_S3_AK27 AK29
V30 CORE_VCC_S0IX_V29 UNCORE_VNN_S3_AK29 AK30
Y27 CORE_VCC_S0IX_V30 UNCORE_VNN_S3_AK30 AK32
Y29 CORE_VCC_S0IX_Y27 UNCORE_VNN_S3_AK32 AM22
Y30 CORE_VCC_S0IX_Y29 UNCORE_VNN_S3_AM22
CORE_VCC_S0IX_Y30

AF30 AA22
TP_CORE_V1P05_S4 TP2_CORE_VCC_S0IX

BAY-TRAIL-M-SOC_FCBGA1170 7 OF 13 ?
REV = 1.15
@
C C

0402 10uF SE00000UD8J CAD NOTE:FOR PIN AD38 AND AF38

0402 4.7uF SE00000SO0J DRAM_VDD_S4_CLK

+CPU_CORE 0402 2.2uF SE00000888J 1 1

0402 1uF SE000000K0J CC20
.1U_0402_10V6-K
CC21
1U_0402_6.3V6K
12 A 2
CD@
2
1 1 1 1 1
CC22 Vienna is 0402 1uF SE000000K0J
10U_0603_6.3V6M CC23 CC24 CC25 CC26
4.7U_0402_6.3V6M 4.7U_0402_6.3V6M 2.2U_0402_6.3V6M 2.2U_0402_6.3V6M
2 2 CD@ 2 2 2
+1.35V

1.25 A
+CPU_CORE 1 1 1 1 1 1 1 1
CC32 CC31 CC30 CC33 CC34
CC27 CC28 CC29 2.2U_0402_6.3V6M 33P_0402_50V8J .1U_0402_10V6-K .1U_0402_10V6-K 33P_0402_50V8J
2.2U_0402_6.3V6M 2.2U_0402_6.3V6M 2.2U_0402_6.3V6M @ @
B 2 2 2 2 2 2 2 2 B
33P_0402_50V8J

CD@
1 1 1 1
CC109

CC35 CC36 CC37

22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
CD@ CD@
2 2 2 2 For RF For RF

@ For RF request

+GFX_CORE
33P_0402_50V8J

1 1 1 1
CC38

CC40 CC39 CC110

1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K
CD@
2 2 2 2

@
For RF request
+GFX_CORE
14 A
2 1 2
CC41 CC42 CC43
10U_0603_6.3V6M 1U_0402_6.3V6K 10U_0603_6.3V6M
A CD@ A
1 2 1

Vienna is 0402 10uF SE00000UD8J

Security Classification LC Future Center Secret Data Title

Issued Date 2013/03/26 Deciphered Date 2013/02/01 SOC (Power)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
C 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
ACLU9
Date: Monday, December 23, 2013 Sheet 9 of 59
5 4 3 2 1
 5 4 3 2 1

+1.0VS_SOC +1.35VS_SOC
? +1.5VS_HDA_S3
UC1H VLV_M_D
+1.8VS_UNCORE_S3
V32 AD36
VGA_V1P0_S3 BJ6 SVID_V1P0_S3_V32 DRAM_V1P35_S0IX_F1_AD36 AM32 +3.3VS_SOC
AD35 VGA_V1P0_S3_BJ6 HDA_LPE_V1P5V1P8_S3_AM32 AM30
AF35 DRAM_V1P0_S0IX_AD35 UNCORE_V1P8_S3_AM30 AN32 +1.8VALW_SOC
AF36 DRAM_V1P0_S0IX_AF35 UNCORE_V1P8_S3_AN32 AM27
AA36 DRAM_V1P0_S0IX_AF36 LPC_V1P8V3P3_S3_AM27 U24 +3.3VALW_USB/PCU_G3
AJ36 DRAM_V1P0_S0IX_AA36 UNCORE_V1P8_G3_U24 N18
AK35 DRAM_V1P0_S0IX_AJ36 USB_V3P3_G3_N18 P18
AK36 DRAM_V1P0_S0IX_AK35 USB_V3P3_G3_P18 U38
Y35 DRAM_V1P0_S0IX_AK36 UNCORE_V1P8_S3_U38 AN24
Y36 DRAM_V1P0_S0IX_Y35 VGA_V3P3_S3_AN24 V25
AK19 DRAM_V1P0_S0IX_Y36 PCU_V1P8_G3_V25 N22 VSS_AD
AK21 DDI_V1P0_S0IX_AK19 PCU_V3P3_G3_N22 AN27 +1.0VALW_UNCORE_G3 0531 Change to UNCORE_V1P0_G3
AJ18 DDI_V1P0_S0IX_AK21 SD3_V1P8V3P3_S3_AN27 AD16 VSS_AD
AM16 DDI_V1P0_S0IX_AJ18 VSS_AD16 AD18 VSS_AD
U22 DDI_V1P0_S0IX_AM16 +1.0VALW_UNCORE_G3 VSS_AD18 V18 +1.0VALW_UNCORE_G3 VCCRTC
D V22 UNCORE_V1P0_G3_U22 +1.0VALW_UNCORE_G3 USB_HSIC_V1P2_G3_V18 AA18 D
+1.0VS_SOC AN29 UNCORE_V1P0_G3_V22 UNCORE_V1P0_S0IX_AN30 UNCORE_V1P8_G3_AA18 P22
+1.0VS_SOC AN30 VIS_V1P0_S0IX_AN29 UNCORE_V1P0_S0IX_AN29 RTC_VCC_P22 N20
AF16 VIS_V1P0_S0IX_AN30 USB_V1P8_G3_N20 U25
AF18 UNCORE_V1P0_S3_AF16 PMU_V1P8_G3_U25 AF33 +1.05VS
Y18 UNCORE_V1P0_S3_AF18 CORE_V1P05_S3_AF33 AG33
G1 UNCORE_V1P0_S3_Y18 CORE_V1P05_S3_AG33 AG35
AM21 UNCORE_V1P0_S3_G1 CORE_V1P05_S3_AG35 U33
AN21 PCIE_V1P0_S3_AM21 CORE_V1P05_S3_U33 U35
PCIE_V1P0_S3_AN21 CORE_V1P05_S3_U35 V33
+1.05VS AN18 CORE_V1P05_S3_V33 A3
AN19 PCIE_GBE_SATA_V1P0_S3_AN18 VSS_A3_A3 A49
+1.05VS_CORE_S3 AA33 SATA_V1P0_S3_AN19 VSS_A49_A49 A5
AF21 CORE_V1P05_S3_AA33 VSS_A5_A5 A51
AG21 UNCORE_V1P0_S0IX_AF21 VSS_A51_A51 A52
+1.0VS_SOC V24 UNCORE_V1P0_S0IX_AG21 UNCORE_V1P0_S0IX_V24 VSS_A52_A52 A6
+1.0VS_SOC Y22 VIS_V1P0_S0IX_V24 UNCORE_V1P0_S0IX_Y22 VSS_A6_A6 B2
+1.0VS_SOC Y24 VIS_V1P0_S0IX_Y22 UNCORE_V1P0_S0IX_Y24 VSS_B2_B2 B52
M14 VIS_V1P0_S0IX_Y24 VSS_B52_B52 B53
U18 USB_V1P0_S3_M14 VSS_B53_B53 BE1
U19 USB_V1P0_S3_U18 VSS_BE1_BE1 BE53
AN25 USB_V1P0_S3_U19 VSS_BE53_BE53 BG1
+1.0VALW_UNCORE_G3 Y19 GPIO_V1P0_S3_AN25 +1.0VALW_UNCORE_G3 VSS_BG1_BG1 BG53
C3 USB3_V1P0_G3_Y19 +1.0VALW_UNCORE_G3 VSS_BG53_BG53 BH1
C5 USB3_V1P0_G3_C3 VSS_BH1_BH1 BH2
B6 UNCORE_V1P0_G3_C5 VSS_BH2_BH2 BH52
UNCORE_V1P0_G3_B6 CORE_V1P05_S3_AC32 VSS_BH52_BH52
1.05VS +1.05VS_CORE_S3 AC32
CORE_V1P0_S3_AC32 CORE_V1P05_S3_Y32 VSS_BH53_BH53
BH53
+1.05VS_CORE_S3 Y32 BJ2
U36 CORE_V1P0_S3_Y32 VSS_BJ2_BJ2 BJ3
AA25 UNCORE_V1P35_S0IX_F4_U36 VSS_BJ3_BJ3 BJ5
AG32 UNCORE_V1P35_S0IX_F5_AA25 VSS_BJ5_BJ5 BJ49
V36 UNCORE_V1P35_S0IX_F2_AG32 VSS_BJ49_BJ49 BJ51
+1.35VS_SOC VGA_V1P35_S3 BD1 UNCORE_V1P35_S0IX_F3_V36 VSS_BJ51_BJ51 BJ52
AF19 VGA_V1P35_S3_F1_BD1 VSS_BJ52_BJ52 C1
AG19 UNCORE_V1P35_S0IX_F6 VSS_C1_C1 C53
AJ19 UNCORE_V1P35_S0IX_F1_AG19 VSS_C53_C53 E1
ICLK_V1P35_S3_F1_AJ19 VSS_E1_E1 E53 +1.0VS_SOC
ICLK_V1P35_S3 VSS_E53_E53 F1
ICLK_V1P35_S3 AG18 RESERVED_F1 AK18
AN16 ICLK_V1P35_S3_F2 PCIE_V1P0_S3_AK18 AM18
U16 VSSA_AN16 PCIE_V1P0_S3_AM18
USB_VSSA_U16
BAY-TRAIL-M-SOC_FCBGA1170 8 OF 13 ?
REV = 1.15
@

C +1.0VS +1.0VS_SOC C

PJ1
1.9 A+850 mA +1.0VS_SOC
+1.05VS
CAD NOTE:FOR CAD NOTE:FOR CAD NOTE:FOR CAD NOTE:FOR CAD NOTE:FOR
1U_0402_6.3V6K

1U_0402_6.3V6K

PJ_43x79_6 PIN AD35 AF35 PIN AF36 PINS AJ36 AK35 PINS AA36 Y35 PINS AK21 RC300 1 2 0_0402_5% VGA_V1P0_S3 1.0 A
AK36 Y36

1U_0402_6.3V6K
1 1 1 1 1 1 1
CC46 CC47 CC49 CC50 CC51 CC52 CC53 1
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1 CAD NOTE:FOR CC114 1 1
CD@ CD@ CC48 PIN BJ6 10U_0603_6.3V6M CC54 CC55
2 2 2 2 2 2 2 1U_0402_6.3V6K 1U_0402_6.3V6K
2
@ 2 2 2

+1.35VS_SOC 0603

RC301 1 2 0_0603_5% VGA_V1P35_S3

+3VS +3.3VS_SOC

CC115
CAD NOTE:FOR CAD NOTE:FOR
CAD NOTE:FOR CAD NOTE:FOR CAD NOTE:FOR CAD NOTE:FOR
22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

@
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
PINS AK19 PINS AJ18 PINS AM16 PINS AF21 AND AG21 PIN U18 U19
PINS V24 Y22 Y24 +1.5VS +1.5VS_HDA_S3

CC101
CAD NOTE:FOR

10U_0603_6.3V6M
1 PIN BD1
1 1 8 mA+25 mA
CC60 +1.35VS_SOC_VGA RC135 1 2 0_0603_5%
1
CC56
1
CC57
1
CC58
1
CC59
1
CC61
1
CC62
1
CC63
1
CC64 .1U_0402_10V6-K RC136 1 2 0_0603_5% 10 mA CAD NOTE:FOR
2 2
CD@ CD@
2 1 1 PIN AM27
RC974 1 2 0_0603_5% @ 1 CC116 CC66
2 2 2 2 2 2 2 2 CC65 10U_0603_6.3V6M
1U_0402_6.3V6K
@ @ @ @
1U_0402_6.3V6K CD@
2 2
2

CAD NOTE:FOR CAD NOTE:FOR CAD NOTE:FOR CAD NOTE:FOR

CAD NOTE:FOR
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

0.01U_0402_25V7K

1U_0402_6.3V6K

1U_0402_6.3V6K

PIN AM16 PIN AF16 AF18 PIN Y18 G1 CAD NOTE:FOR PIN AN18 PIN V23 CAD NOTE:FOR
PIN AN25 PIN AK18 AM18
1 1 1 1 2 1 1 1 1
CC67 CC68 CC69 CC70 CC71 CC72 CC73 CC74 CC75
CD@ 1U_0402_6.3V6K 1U_0402_6.3V6K
CD@ +1.8VS +1.8VS_UNCORE_S3
2 2 2 2 1 2 2 2 2
@ @ @
RC137 1 2 0_0603_5% 10 mA
+1.35VS_SOC ICLK_V1P35_S3
CAD NOTE:FOR CAD NOTE:FOR CAD NOTE:FOR CAD NOTE:FOR
1 PIN U38 1 PIN AM30 AN32 1 PIN AM30 AN32 1 PIN AM30 AN32
RC302 1 2 0_0402_5% ICLK_V1P35_S3 CC76 CC77 CC78 CC79
1 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K
CAD NOTE:FOR CC111 @ @
PIN AG18 1U_0402_6.3V6K 2 2 2 2

B B
+1.8VALW +1.8VALW_SOC

RC138 1 2 0_0603_5% 65 mA
CAD NOTE:FOR
1 1 PIN AA18
CC80 CC81
1U_0402_6.3V6K 1U_0402_6.3V6K
CD@
+1.0VALW +1.0VALW_UNCORE_G3 2 2
325 mA +1.0VALW_UNCORE_G3
1 RC139 2 0_0603_5%

CAD NOTE:FOR
CAD NOTE:FOR 1 PIN V18
PINS Y19 AND C3 CC86
1 1 1 1 2
CC82 CC83 CC84 CC85 CC87 1U_0402_6.3V6K
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 0.01U_0402_25V7K VSS_AD
CD@ CD@ CD@ 2
2 2 2 2 1 0531 1.2VS VCCRTC
BAY TRAIL no use

0603 1
CC112
.1U_0402_10V6-K
2

+1.35VS +1.35VS_SOC
375 mA+45 mA
1 RC140 2 0_0603_5%

CAD NOTE:FOR
0611 CAD NOTE:FOR CAD NOTE:FOR CAD NOTE:FOR CAD NOTE:FOR PIN AD36 CAD NOTE:FOR CAD NOTE:FOR +3VALW_SOC +3.3VALW_USB/PCU_G3
1 PIN V36 1 PIN AD36 PIN
1 AJ19 1 PIN AA25 1 1 PIN AG19 1 PIN AF19
CC89 CC90 CC91 CC92 CC102 CC94 CC95
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K RC141 1 2 0_0603_5% 50 mA
CD@ CD@
2 2 2 2 2 2 2
CAD NOTE:FOR
PIN N18 P18
1 1
CC96 CC97
1U_0402_6.3V6K .1U_0402_10V6-K
A CD@ A
CAD NOTE:FOR CAD NOTE:FOR CAD NOTE:FOR 2 2
PIN AA25 PIN U36 PIN AG32
1 1 1 1 1
CC98 CC99 CC100 CC88 CC93
10U_0603_6.3V6M 22U_0805_6.3V6M 1U_0402_6.3V6K 1U_0402_6.3V6K
CD@ CD@ 1U_0402_6.3V6K CD@
2 2 2 2 CD@ 2

Security Classification LC Future Center Secret Data Title

Issued Date 2013/03/26 Deciphered Date 2013/02/01 SOC (Power2)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
ACLU9
Date: Monday, December 23, 2013 Sheet 10 of 59
5 4 3 2 1
 5 4 3 2 1

? ?
? UC1J VLV_M_D UC1K VLV_M_D
UC1I VLV_M_D
AG38 AH47 AT24 AY36
A11 AC36 AH4 VSS71 VSS106 AH48 AT27 VSS141 VSS176 AY4
A15 VSS1 VSS36 AC38 AH41 VSS72 VSS107 AH50 AT30 VSS142 VSS177 AY50
A19 VSS2 VSS37 AD19 AH45 VSS73 VSS108 AH51 AT35 VSS143 VSS178 AY9
A23 VSS3 VSS38 AD21 AH7 VSS74 VSS109 AH6 AT38 VSS144 VSS179 BA14
A27 VSS4 VSS39 AD25 AH9 VSS75 VSS110 AM44 AT4 VSS145 VSS180 BA19
A31 VSS5 VSS40 AD32 AJ1 VSS76 VSS111 AM51 AT47 VSS146 VSS181 BA22
A35 VSS6 VSS41 AD33 AJ16 VSS77 VSS112 AM7 AT52 VSS147 VSS182 BA27
A39 VSS7 VSS42 AD47 AJ21 VSS78 VSS113 AN1 AU1 VSS148 VSS183 BA32
A43 VSS8 VSS43 AD7 AJ25 VSS79 VSS114 AN11 AU24 VSS149 VSS184 BA35
D
A47 VSS9 VSS44 AE1 AJ27 VSS80 VSS115 AN12 AU3 VSS150 VSS185 BA40 D

AA1 VSS10 VSS45 AE11 AJ29 VSS81 VSS116 AN14 AU30 VSS151 VSS186 BA53
AA16 VSS11 VSS46 AE12 AJ3 VSS82 VSS117 AN22 AU38 VSS152 VSS187 BB19
AA19 VSS12 VSS47 AE14 AJ30 VSS83 VSS118 AN3 AU51 VSS153 VSS188 BB27
AA21 VSS13 VSS48 AE3 AJ32 VSS84 VSS119 AN33 AV12 VSS154 VSS189 BB35
AA3 VSS14 VSS49 AE4 AJ33 VSS85 VSS120 AN35 AV13 VSS155 VSS190 BC20
AA32 VSS15 VSS50 AE40 AJ35 VSS86 VSS121 AN36 AV14 VSS156 VSS191 BC22
AA35 VSS16 VSS51 AE42 AJ38 VSS87 VSS122 AN38 AV18 VSS157 VSS192 BC26
AA38 VSS17 VSS52 AE43 AJ53 VSS88 VSS123 AN40 AV19 VSS158 VSS193 BC28
AA53 VSS18 VSS53 AE45 AK10 VSS89 VSS124 AN42 AV24 VSS159 VSS194 BC32
AB10 VSS19 VSS54 AE46 AK14 VSS90 VSS125 AN43 AV27 VSS160 VSS195 BC34
AB4 VSS20 VSS55 AE48 AK16 VSS91 VSS126 AN45 AV30 VSS161 VSS196 BC42
AB41 VSS21 VSS56 AE50 AK33 VSS92 VSS127 AN46 AV35 VSS162 VSS197 BD19
AB45 VSS22 VSS57 AE51 AK41 VSS93 VSS128 AN48 AV38 VSS163 VSS198 BD24
AB47 VSS23 VSS58 AE53 AK44 VSS94 VSS129 AN49 AV47 VSS164 VSS199 BD27
AB48 VSS24 VSS59 AE6 AM12 VSS95 VSS130 AN5 AV51 VSS165 VSS200 BD30
AB50 VSS25 VSS60 AE8 AM19 VSS96 VSS131 AN51 AV7 VSS166 VSS201 BD35
AB51 VSS26 VSS61 AE9 AM24 VSS97 VSS132 AN53 AW13 VSS167 VSS202 BE19
AB6 VSS27 VSS62 AF10 AM25 VSS98 VSS133 AN6 AW19 VSS168 VSS203 BE2
AC16 VSS28 VSS63 AF12 AM29 VSS99 VSS134 AN8 AW27 VSS169 VSS204 BE35
AC18 VSS29 VSS64 AF25 AM33 VSS100 VSS135 AN9 AW3 VSS170 VSS205 BE8
AC19 VSS30 VSS65 AF32 AM35 VSS101 VSS136 AP40 AW35 VSS171 VSS206 BF12
AC21 VSS31 VSS66 AF47 AM36 VSS102 VSS137 AT12 AY10 VSS172 VSS207 BF16
AC25 VSS32 VSS67 AG16 AM40 VSS103 VSS138 AT16 AY22 VSS173 VSS208 BF24
AC33 VSS33 VSS68 AG25 M28 VSS104 VSS139 AT19 AY32 VSS174 VSS209 BF38
AC35 VSS34 VSS69 AG36 VSS105 VSS140 VSS175 VSS210
VSS35 VSS70
BAY-TRAIL-M-SOC_FCBGA1170 BAY-TRAIL-M-SOC_FCBGA1170
BAY-TRAIL-M-SOC_FCBGA1170 REV = 1.15 10 OF 13 ? REV = 1.15 11 OF 13 ?
REV = 1.15 9 OF 13 ? @ @
@
?
UC1L VLV_M_D
?
BF30 E8 UC1M VLV_M_D
BF36 VSS211 VSS246 F19
C BF4 VSS212 VSS247 F2 K9 U3 C
BG31 VSS213 VSS248 F24 L13 VSS281 VSS316 U30
BG34 VSS214 VSS249 F27 L19 VSS282 VSS317 U32
BG39 VSS215 VSS250 F30 L27 VSS283 VSS318 U40
BG42 VSS216 VSS251 F35 L35 VSS284 VSS319 U42
BG45 VSS217 VSS252 F5 M19 VSS285 VSS320 U43
BG49 VSS218 VSS253 F7 M26 VSS286 VSS321 U45
BJ11 VSS219 VSS254 G10 M27 VSS287 VSS322 U46
BJ15 VSS220 VSS255 G20 M34 VSS288 VSS323 U48
BJ19 VSS221 VSS256 G22 M35 VSS289 VSS324 U49
BJ23 VSS222 VSS257 G26 M38 VSS290 VSS325 U5
BJ27 VSS223 VSS258 G28 M47 VSS291 VSS326 U51
BJ31 VSS224 VSS259 G32 M51 VSS292 VSS327 U53
BJ35 VSS225 VSS260 G34 N1 VSS293 VSS328 U6
BJ39 VSS226 VSS261 G42 N16 VSS294 VSS329 U8
BJ43 VSS227 VSS262 H19 N38 VSS295 VSS330 U9
BJ47 VSS228 VSS263 H27 N51 VSS296 VSS331 V12
BJ7 VSS229 VSS264 H35 P13 VSS297 VSS332 V16
C14 VSS230 VSS265 J1 P16 VSS298 VSS333 V19
C31 VSS231 VSS266 J16 P19 VSS299 VSS334 V21
C34 VSS232 VSS267 J19 P20 VSS300 VSS335 V35
C39 VSS233 VSS268 J22 P24 VSS301 VSS336 V40
C42 VSS234 VSS269 J27 P32 VSS302 VSS337 V44
C45 VSS235 VSS270 J32 P35 VSS303 VSS338 V51
C49 VSS236 VSS271 J35 P38 VSS304 VSS339 V7
D12 VSS237 VSS272 J40 P4 VSS305 VSS340 Y10
D16 VSS238 VSS273 J53 P47 VSS306 VSS341 Y14
D24 VSS239 VSS274 K14 P52 VSS307 VSS342 Y16
D30 VSS240 VSS275 K22 P9 VSS308 VSS343 Y21
D36 VSS241 VSS276 K32 T40 VSS309 VSS344 Y25
D38 VSS242 VSS277 K36 U1 VSS310 VSS345 Y33
E19 VSS243 VSS278 K4 U11 VSS311 VSS346 Y41
E35 VSS244 VSS279 K50 U12 VSS312 VSS347 Y44
VSS245 VSS280 U14 VSS313 VSS348 Y7
U21 VSS314 VSS349 Y9
BAY-TRAIL-M-SOC_FCBGA1170 VSS315 VSS350
REV = 1.15 12 OF 13 ?
@ BAY-TRAIL-M-SOC_FCBGA1170
B B
REV = 1.15 13 OF 13 ?
@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/03/26 Deciphered Date 2013/02/01 SOC (VSS)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
C 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
ACLU9
Date: Monday, December 23, 2013 Sheet 11 of 59
5 4 3 2 1
 5 4 3 2 1

D D

GPIO_NC13 MDSI_DDCDATA(Checklist repuest 10K pull down)

Hardware STRAPS GPIO_S0_SC_56 GPIO_S0_SC_56(Internal Pull-up) GPIO_S0_SC_56:
(Follow up CRB& VIENNA) I2S_2_FS
I2S_2_TXD
GPIO_S0_SC[063] (Internal Pull-up)
GPIO_S0_SC[065](Internal Pull-up)
A16 Top Swap
+1.8VS PCH_HDMI_DDC_DAT DDI1_DDCDATA 0=Top address bit is unchanged
DDI0_DDCDATA DDI0_DDCDATA
1=Top address bit is inverted
GPIO_S0_SC[063]
Multiplexed with Hardware Straps Pin LPE_I2S2_FRM
BIOS Boot selection
2

2
RC936 RC938 RC45 RC46 RC47
2.2K_0402_5% 10K_0402_1% 10K_0402_1% 10K_0402_1% 10K_0402_1% 0=LPC
@
@ @ @ 1=SPI
1

1
C C
GPIO_S0_SC[065]
GPIO_NC13

GPIO_S0_SC_56
GPIO_NC13 {4}
Multiplexed with LPE_I2S2_DATAOUT
GPIO_S0_SC_56 {8}
I2S_2_FS
Security Flash Descriptors
I2S_2_FS {6}
I2S_2_TXD
I2S_2_TXD {6}
0=Override
1=Normal Operation
DDI1_DDCDATA
DDI1_DDCDATA {4} DDI0_DDCDATA:
DDI0 strap
2

RC963 RC941 RC943 RC942

0=DDI0 not detected
10K_0402_1% 10K_0402_1% 2.2K_0402_5% 10K_0402_1%
@ @ @ 1=DDI0 detected
DDI1_DDCDATA:
1

B DDI1 strap B

0=DDI1 not detected

I2S_2_TXD
0606 1=DDI1 detected

2
RC961
4.7K_0402_5%
1
1

ME2 @
1

D QC202 RC962
2 1 2
PCH_ME_PROTECT {44}
2

G
JUMP_43X39 0_0402_5%
2

S 2N7002KW_SOT323-3
3

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 SOC (STRAPS & OTHERS)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
ACLU9
Date: Monday, December 23, 2013 Sheet 12 of 59
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 MCP (OTHER)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
ACLU9
Date: Monday, December 23, 2013 Sheet 13 of 59
5 4 3 2 1
 5 4 3 2 1

DDR Mapping table DDR3 SO-DIMM A

DDRA_DQ[0..63] {5}
DDRA_DQ0---DQ0
DDRA_DQ1---DQ1 +1.35V +1.35V
DDRA_DQS[0..7] {5}
DDRA_DQ6---DQ2
DDRA_DQ3---DQ3 DDRA_DQS#[0..7] {5}
DDRA_DQ4---DQ4 3A@1.5V DDRA_MA[0..15] {5}
DDRA_DQ5---DQ5 For RF request
JDDR1
DDRA_DQ7---DQ6 DDRA_DM[7:0] {5}
DDR_DQ 1 2
D DDRA_DQ2---DQ7 3 VREF_DQ VSS_2 4 DDRA_DQ4 D
VSS_1 DQ4

.1U_0402_10V6-K

33P_0402_50V8J

33P_0402_50V8J

33P_0402_50V8J
DDRA_DQ9----DQ8 DDRA_DQ0 5 6 DDRA_DQ5
DDRA_DQ1 7 DQ0 DQ5 8
DDRA_DQ13---DQ9 1 DQ1 VSS_4 1 1 1

CD4

CD5

CD6
CD3 9 10 DDRA_DQS#0 @ @ @
DDRA_DQ10---DQ10 DDRA_DM0 11 VSS_3 DQS0# 12 DDRA_DQS0
DDRA_DQ11---DQ11 13 DM0 DQS0 14
2 DDRA_DQ6 15 VSS_5 VSS_6 16 DDRA_DQ7 2 2 2
DDRA_DQ12---DQ12 DQ2 DQ6
DDRA_DQ8----DQ13 DDRA_DQ3 17 18 DDRA_DQ2
19 DQ3 DQ7 20
DDRA_DQ15---DQ14 DDRA_DQ9 21 VSS_7 VSS_8 22 DDRA_DQ12
DDRA_DQ14---DQ15 DDRA_DQ13 23 DQ8 DQ12 24 DDRA_DQ8
25 DQ9 DQ13 26
DDRA_DQ16---DQ16 VSS_9 VSS_10
DDRA_DQ17---DQ17 DDRA_DQS#1 27 28 DDRA_DM1
DDRA_DQS1 29 DQS1# DM1 30
DDRA_DQ18---DQ18 31 DQS1 RESET# 32
DDRA_DRAMRST# {5} OSCON (220uF_6.3V_4.2L_ESR17m)*1=(SF000002Y00)
DDRA_DQ19---DQ19 DDRA_DQ10 33 VSS_11 VSS_12 34 DDRA_DQ15
DDRA_DQ11 35 DQ10 DQ14 36 DDRA_DQ14
DDRA_DQ20---DQ20 DQ11 DQ15
DDRA_DQ21---DQ21 37 38
DDRA_DQ16 39 VSS_13 VSS_14 40 DDRA_DQ20
DDRA_DQ23---DQ22 DQ16 DQ20 Layout Note:
DDRA_DQ17 41 42 DDRA_DQ21
DDRA_DQ22---DQ23 43 DQ17 DQ21 44 Place near DIMM (10uF_0603_6.3V)*8
DDRA_DQS#2 45 VSS_15 VSS_16 46 DDRA_DM2
DDRA_DQ28---DQ24 DQS2# DM2 (0.1uF_402_10V)*4
DDRA_DQ25---DQ25 DDRA_DQS2 47 48
49 DQS2 VSS_18 50 DDRA_DQ23
DDRA_DQ26---DQ26 DDRA_DQ18 51 VSS_17 DQ22 52 DDRA_DQ22
DDRA_DQ27---DQ27 DDRA_DQ19 53 DQ18 DQ23 54
55 DQ19 VSS_20 56 DDRA_DQ24
DDRA_DQ24---DQ28 VSS_19 DQ28
DDRA_DQ29---DQ29 DDRA_DQ28 57 58 DDRA_DQ29 +1.35V
DDRA_DQ25 59 DQ24 DQ29 60
DDRA_DQ30---DQ30 61 DQ25 VSS_22 62 DDRA_DQS#3
DDRA_DQ31---DQ31 DDRA_DM3 63 VSS_21 DQS3# 64 DDRA_DQS3
DM3 DQS3

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K
DDRA_DQ32---DQ32 65 66 1
C DDRA_DQ26 67 VSS_23 VSS_24 68 DDRA_DQ30 CD7 1 CD8 1 CD9 1 CD10 CD11 CD12 CD13 CD14 CD15 CD16 CD17 CD18 C
DDRA_DQ36---DQ33 DQ26 DQ30 1 1 1 1 1 1 1 1 1
DDRA_DQ27 69 70 DDRA_DQ31 + CD19
DDRA_DQ35---DQ34 71 DQ27 DQ31 72 220U_6.3V_M
DDRA_DQ34---DQ35 VSS_25 VSS_26
DDRA_DQ37---DQ36 2 2 2 2 2 2 2 2 2 2 2 2 2
@
DDRA_DQ33---DQ37 {5} DDRA_CKE0 DDRA_CKE0 73 74 DDRA_CKE1
CKE0 CKE1 DDRA_CKE1 {5}
75 76
DDRA_DQ38---DQ38 77 VDD_1 VDD_2 78 DDRA_MA15 @ @
DDRA_DQ39---DQ39 DDRA_BS2# 79 NC_1 A15 80 DDRA_MA14
{5} DDRA_BS2# BA2 A14
DDRA_DQ40---DQ40 81 82
DDRA_MA12 83 VDD_3 VDD_4 84 DDRA_MA11
DDRA_DQ45---DQ41 A12/BC# A11
DDRA_MA9 85 86 DDRA_MA7
DDRA_DQ42---DQ42 87 A9 A7 88
DDRA_DQ43---DQ43 DDRA_MA8 89 VDD_5 VDD_6 90 DDRA_MA6
DDRA_MA5 91 A8 A6 92 DDRA_MA4 +1.35V +1.35V
DDRA_DQ44---DQ44 A5 A4
DDRA_DQ41---DQ45 93 94
DDRA_MA3 95 VDD_7 VDD_8 96 DDRA_MA2
DDRA_DQ47---DQ46 DDRA_MA1 97 A3 A2 98 DDRA_MA0
DDRA_DQ46---DQ47 99 A1 A0 100
VDD_9 VDD_10

1
DDRA_DQ48---DQ48 {5} DDRA_CLK0 DDRA_CLK0 101 102 DDRA_CLK1
CK0 CK1 DDRA_CLK1 {5}
DDRA_DQ49---DQ49 {5} DDRA_CLK0# DDRA_CLK0# 103 104 DDRA_CLK1# RD1 RD3
CK0# CK1# DDRA_CLK1# {5}
105 106 4.7K_0402_1% 4.7K_0402_1%
DDRA_DQ50---DQ50 DDRA_MA10 107 VDD_11 VDD_12 108 DDRA_BS1#
DDRA_DQ51---DQ51 A10/AP BA1 DDRA_BS1# {5}
{5} DDRA_BS0# DDRA_BS0# 109 110 DDRA_RAS#
DDRA_RAS# {5}

2
111 BA0 RAS# 112
DDRA_DQ52---DQ52 VDD_13 VDD_14
DDRA_DQ53---DQ53 {5} DDRA_WE# DDRA_WE# 113 114 DDRA_CS0#
WE# S0# DDRA_CS0# {5}
{5} DDRA_CAS# DDRA_CAS# 115 116 DDRA_ODT0 RD5 RD6
DDRA_DQ55---DQ54 CAS# ODT0 DDRA_ODT0 {5}
117 118 1 2 DDR_DQ 1 2 DDR_CA
DDRA_DQ54---DQ55 DDRA_MA13 119 VDD_15 VDD_16 120 DDRA_ODT1
A13 ODT1 DDRA_ODT1 {5}
DDRA_DQ56---DQ56 {5} DDRA_CS1# DDRA_CS1# 121 122 0_0402_5% 0_0402_5%
123 S1# NC_2 124
DDRA_DQ61---DQ57 VDD_17 VDD_18

1
125 126 DDR_CA
B DDRA_DQ58---DQ58 127 TEST VREF_CA 128 RD2 RD4 B
VSS_27 VSS_28
.1U_0402_10V6-K

DDRA_DQ59---DQ59 DDRA_DQ32 129 130 DDRA_DQ37 4.7K_0402_1% 4.7K_0402_1%

DDRA_DQ36 131 DQ32 DQ36 132 DDRA_DQ33
DDRA_DQ60---DQ60 DQ33 DQ37 1
CD21

DDRA_DQ57---DQ61 133 134

2
DDRA_DQS#4 135 VSS_29 VSS_30 136 DDRA_DM4
DDRA_DQ63---DQ62 DDRA_DQS4 137 DQS4# DM4 138
DDRA_DQ62---DQ63 139 DQS4 VSS_32 140 DDRA_DQ38 2
DDRA_DQ35 141 VSS_31 DQ38 142 DDRA_DQ39
DDRA_DQ34 143 DQ34 DQ39 144
145 DQ35 VSS_34 146 DDRA_DQ44
DDRA_DQ40 147 VSS_33 DQ44 148 DDRA_DQ41
DDRA_DQ45 149 DQ40 DQ45 150
151 DQ41 VSS_35 152 DDRA_DQS#5
DDRA_DM5 153 VSS_36 DQS5# 154 DDRA_DQS5
DM5 DQS5 Layout Note:
155 156
DDRA_DQ42 157 VSS_37 VSS_38 158 DDRA_DQ47 Place near DIMM
DDRA_DQ43 159 DQ42 DQ46 160 DDRA_DQ46
161 DQ43 DQ47 162 +1.35V
DDRA_DQ48 163 VSS_39 VSS_40 164 DDRA_DQ52
DDRA_DQ49 165 DQ48 DQ52 166 DDRA_DQ53 +0.675VS
167 DQ49 DQ53 168
VSS_41 VSS_42

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K
DDRA_DQS#6 169 170 DDRA_DM6
5V
DQS6# DM6 @0. 7

CD64

CD65
171 172
.65A
DDRA_DQS6 CD68 1 CD69 1 CD66 1 CD67 1
RD10 1 2 0_0402_5% SA0 173 DQS6 VSS_44 174 0 DDRA_DQ55
VSS_43 DQ54

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

10U_0603_6.3V6M

10U_0603_6.3V6M

33P_0402_50V8J
RD11 1 2 0_0402_5% SA1 DDRA_DQ50 175 176 DDRA_DQ54
DDRA_DQ51 177 DQ50 DQ55 178 CD24 1 CD25 CD26
DQ51 VSS_46 2 2 2 2 1 1 1 1 1 1

CD70
179 180 DDRA_DQ60 CD23
DDRA_DQ56 181 VSS_45 DQ60 182 DDRA_DQ57 1U_0402_6.3V6K
DDRA_DQ61 183 DQ56 DQ61 184
185 DQ57 VSS_48 186 DDRA_DQS#7 @ @ @ @ 2 2 2 2 2 2 2
DDRA_DM7 187 VSS_47 DQS7# 188 DDRA_DQS7
189 DM7 DQS7 190
A DDRA_DQ58 191 VSS_49 VSS_50 192 DDRA_DQ63 @ @ @ @ @ A
DQ58 DQ62 cost down bom to change 0.1uF
DDRA_DQ59 193 194 DDRA_DQ62 For RF request
195 DQ59 DQ63 196
SA0 197 VSS_51 VSS_52 198
199 SA0 EVENT# 200
+3VS VDDSPD SDA SMB_DATA_S3 {8,40}
SA1 201 202
SA1 SCL SMB_CLK_S3 {8,40}
1 1 203 204 +0.675VS
VTT_1 VTT_2
Security Classification LC Future Center Secret Data Title
CD27 CD28 205 206
2.2U_0603_6.3V6K .1U_0402_10V6-K 207 GND1 GND2 208
2 2 BOSS1 BOSS2 Issued Date 2013/08/08 Deciphered Date 2013/08/05 DDRIII SO-DIMM A
@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
LCN_DAN06-K4406-0103 Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
ME@ Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
ACLU9
Date: Monday, December 23, 2013 Sheet 14 of 59
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 DDRIII SO-DIMM B

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
ACLU9
Date: Monday, December 23, 2013 Sheet 15 of 59
5 4 3 2 1
 5 4 3 2 1

+3VS

1 2
U1 RH20 0_0603_5% +5VALW
+3VALW_SOC +VDD
0604
1 @ 2 V5
HUB_USB20_N0 1 28 +VDD 1 2 RH2 0_0603_5%
HUB_USB20_P0 2 DM0 V33 27 V5 @ RH1 0_0603_5%
HUB_USB20_N1 3 DP0 V5 26 SDA_HUB 1 TP6 @
HUB_USB20_P1 4 DM1 PWREN1#/SDA 25 HUB_USB_OC1#
D DP1 GL850G OVCUR1#/SMC ** External regulator modeRH1RH2 D
+AVDD 5 24
HUB_USB20_N2 6 AVDD QFN28 OVCUR2#/SMD 23 PGANG Internal regulator modeRH1RH2
DM2 PGANG LB1
HUB_USB20_P2 7 22 PSELF
RREF_HUB 8 DP2 PSELF 21 1 2+VDD
RREF DVDD 1
+AVDD 9 20 UPB100505T-121Y-N_2P CH1
XTAL12_IN 10 AVDD1 OVCUR3# 19 .1U_0402_10V6-K
XTAL12_OUT 11 X1 OVCUR4# 18 TEST/SCL 1 TP7 @
HUB_USB20_N3 12 X2 TEST/SCL 17 RESET# 2
HUB_USB20_P3 13 DM3 RESET# 16 HUB_USB20_P4 +VDD +AVDD +AVDD
+AVDD 14 DP3 DP4 15 HUB_USB20_N4 2 RH3 1 @
AVDD2 DM4 10M_0402_5%

XTAL12_IN

XTAL12_OUT
LB2
YH1 0604
29 1 2
PAD

.1U_0402_10V6-K

.1U_0402_10V6-K

1U_0402_6.3V6K

1U_0402_6.3V6K

.1U_0402_10V6-K
UPB100505T-121Y-N_2P
1 3 1 1 1 1 1 1 1
OSC1 OSC2

CH4

CH5

CH6

CH7

CH8
2 4 CH2 CH3
GL850G-OHY31_QFN28_5X5 GND1 GND2 10U_0603_6.3V6M .1U_0402_10V6-K
0805 change 1 1 2 2 2 2 2 2 2
CH9 CH10
20P_0402_50V8 12MHZ_10PF_7V12000008 20P_0402_50V8
2 2
As close to GL850G
CH2 close to PIN28
C CH3 PIN5 CH4/CH5 PIN9 CH6/CH15 PIN14 C
As close to GL850G

1 2 +5VALW +VDD
RH4 0_0402_5%

CM1 @
{8} USB20_N3 USB20_N3 1 2 HUB_USB20_N0

1
Vienna change to 619 ohm for Eye Diagram test
RH6 RH7
{8} USB20_P3 USB20_P3 4 3 HUB_USB20_P0 10K_0402_5% 10K_0402_5%
@
RH9
DLP11SN900HL2L_4P

2
1 2 RREF_HUB 1 2
RH8 0_0402_5% RESET#
680_0402_1%

1U_0402_6.3V6K

47K_0402_5%
1
B 1 B

CH11

RH10
0605 PGANG 1 RH11 2 Individual Mode
2 @ 100K_0402_5%

2
+VDD
HUB_USB20_N1 {33}
HUB_USB20_P1 {33} Camera
PSELF 1 RH12 2 Self-power
HUB_USB20_N2 {45}
10K_0402_5%
HUB_USB20_P2 {45} Card reader
HUB_USB20_N3
HUB_USB20_P3
{40}
{40}
BT +VDD

HUB_USB20_N4 {33}
HUB_USB20_P4 {33} Touch panel RH628
HUB_USB_OC1# 1 2
@ 10K_0402_5%

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/03/26 Deciphered Date 2013/02/01 USB Hub GL850G-OHY31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
ACLU9
Date: Monday, December 23, 2013 Sheet 16 of 59
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 Blank

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
ACLU9
Date: Monday, December 23, 2013 Sheet 17 of 59
5 4 3 2 1
 5 4 3 2 1

N15x GPIO
Performance Mode P0 TDP at Tj = 102 C* (DDR3)
GPIO I/O ACTIVE Function Description
FBVDDQ PCI Express I/O and Other
GPU Mem NVCLK FBVDD (GPU+Mem) (1.05V) PLLVDD
GPIO0 OUT - FB Enable for GC6 2.0 (4) (1,5) /MCLK NVVDD (1.35V) (1.35V) (6) (1.05V) (3.3V)
Products (W) (W) (MHz) (V) (A) (W) (A) (W) (A) (W) (mA) (W) (mA) (W) (mA) (W)
D GPIO1 OUT N/A D

N14X
GPIO2 OUT N/A 128bit TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
2GB
DDR3
GPIO3 OUT N/A

GPIO4 OUT N/A

GPIO5 OUT N/A GPU power sequencing---3V3_MAIN_EN

GPIO6 IN - GPU wake signal for GC6 2.0

GPIO7 OUT N/A

GPIO8 I/O - System side PCIe reset Monitor

GPIO9 I/O N/A 2.2K Pull-up

N15x Multi-level Straps
GPIO10 OUT N/A

GPIO11 OUT - GPU Core VDD PWM control signal

GPIO12 IN AC Power Detect Input (10K pull High)

Physical Logical Logical Logical Logical
GPIO13 OUT - Phase Shedding Strapping pin Power Rail Strapping Bit3 Strapping Bit2 Strapping Bit1 Strapping Bit0
C ROM_SCLK +3VGS SOR3_EXPOSED SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED C
GPIO14 IN N/A
ROM_SI +3VGS RAM_CFG[3] RAM_CFG[2] RAM_CFG[1] RAM_CFG[0]
GPIO15 IN N/A ROM_SO +3VGS DEVID_SEL PCIE_CFG SMB_ALT_ADDR VGA_DEVICE
STRAP0 +3VGS Reserved(keep pull-up and pull-down footprint and stuff 50Kohm pull-up)
GPIO16 N/A
STRAP1 +3VGS
GPIO17 IN N/A STRAP2 +3VGS
Reserved(keep pull-up and pull-down footprint and not stuff by default)
STRAP3 +3VGS
GPIO18 IN N/A
STRAP4 +3VGS
GPIO19 IN N/A

GPIO20 N/A SMBUS_ALT_ADDR

GPIO21 OUT GPU PCIe self-reset control 0 0x9E (Default)

OVERT OUT Active Low Thermal Catastrophic Over Temperature 1 0x9C (Multi-GPU usage)

N15V-GM Power Sequence

B
N15x Binary Straps B

+3VG_AON Other Power rail

+VGA_CORE
+3VG_AON
Physical
tNVVDD >0 Power Rail Strap Mapping
+1.35VGS Strapping pin
Tpower-off <10ms ROM_SCLK +3VGS SMB_ALT_ADDR
tFBVDDQ >0
ROM_SI +3VGS SUB_VENDOR
+1.05VS_VGA
ROM_SO +3VGS VGA_DEVICE
tPEX_VDD >0
STRAP0 +3VGS RAM_CFG[0]
1.all GPU power rails should be turned off within 10ms STRAP1 +3VGS RAM_CFG[1]
1. all power rail ramp up time should be larger than 40us 2. Optimus system VDD33 avoids drop down earlier than NVDD and FBVDDQ
STRAP2 +3VGS RAM_CFG[2]
STRAP3 +3VGS RAM_CFG[3]
STRAP4 +3VGS PCIE_MAX_SPEED
N15S-GT Power Sequence

+3VG_AON

+VGA_CORE
A A

tNVVDD >0
+1.05VS_VGA

+1.35VGS
tPEX_VDD >0
Security Classification LC Future Center Secret Data Title

1. all power rail ramp up time should be larger than 40us Issued Date 2013/08/08 Deciphered Date 2013/08/05 VGA Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
C 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
ACLU9
Date: Monday, December 23, 2013 Sheet 18 of 59
5 4 3 2 1
 5 4 3 2 1

RV1 1 GC6@ 2 0_0402_5% FB_GC6_EN_R

{8} GPIO52
RV2 1 GC6@ 2 0_0402_5% GPU_EVENT#
{8} GPIO53

{6} PCIE_CRX_GTX_N[0..1]

{6} PCIE_CRX_GTX_P[0..1]

{6} PCIE_CTX_C_GRX_N[0..1]
UV1A
{6} PCIE_CTX_C_GRX_P[0..1]
+3VGS
Part 1 of 6 1 RV175 2 0_0402_5%
H_THRMTRIP#
PCIE_CTX_C_GRX_P0 AG6 C6 FB_GC6_EN @
D PEX_RX0 GPIO0 FB_GC6_EN {23} D

.1U_0402_10V6-K
+3VG_AON +3VG_AON PCIE_CTX_C_GRX_N0 AG7 B2
PEX_RX0_N GPIO1

1
PCIE_CTX_C_GRX_P1 AF7 D6 1
PCIE_CTX_C_GRX_N1 AE7 PEX_RX1 GPIO2 C7 RV4
AE9 PEX_RX1_N GPIO3 F9 10K_0402_5% CV1
2

AF9 PEX_RX2 GPIO4 A3 3VGS_PWR_EN @ @

PEX_RX2_N GPIO5 3VGS_PWR_EN {21,58}

3
RV3 RV5 AG9 A4 GPU_EVENT#_R D 2

2
PEX_RX3 GPIO6

5
2.2K_0402_5% 2.2K_0402_5% AG10 B6 5

G
OPT@ OPT@ AF10 PEX_RX3_N GPIO7 E9 SYS_PEX_RST_MON# G
AE10 NC81 GPIO8 F8 VGA_ALERT#
A6 Symbol update to OVER QV2B
1

NC82 GPIO9

6
AE12 C5 D S 2N7002KDWH_SOT363-6

4
VGA_SMB_CK2 4
S
3 AF12 NC83 GPIO10 E7 NVVDD PWM_VID DV1 OVERT# 2 @
EC_SMB_CK2 {39,44} NC84 GPIO11 NVVDD PWM_VID {58}

D
AG12 D7 VGA_AC_DET_R 2 1 G
NC85 GPIO12 VGA_AC_DET {44}
AG13 B4 PSI_VGA_R OPT@ QV2A

GPIO
QV1B AF13 NC86 GPIO13 B3 RB751V-40_SOD323-2 S 2N7002KDWH_SOT363-6

1
2N7002KDWH_SOT363-6 AE13 NC87 GPIO14 C3 @
NC88 GPIO15 2 RV6
2

OPT@ AE15 D5 1 PSI_VGA

G

NC1 GPIO16 PSI_VGA {58}

1
RV7 2 @ 1 0_0402_5% AF15 D4 N15SGT@ 0_0402_5% D
NC2 GPIO17

.1U_0402_10V6-K
AG15 C2 PLT_RST_VGA# 1 RV8 2 0_0402_5% 2 1
AG16 NC3 GPIO18 F7 @ G
NC4 GPIO19

.1U_0402_10V6-K
VGA_SMB_DA2 1 6 AF16 E6 QV3 CV2
S

EC_SMB_DA2 {39,44} NC5 GPIO20

D

AE16 C4 GPU_PEX_RST_HOLD# S 2N7002KW_SOT323-3 @

3
AE18 NC6 GPIO21 @ 2
NC7 1
QV1A AF18 A6 OVERT# CV3
2N7002KDWH_SOT363-6 AG18 NC8 OVERT AB6
OPT@ AG19 NC9 NC33 @
RV9 2 @ 1 0_0402_5% AF19 NC10 2
PU AT EC SIDE, +3VS AND 4.7K
AE19 NC11 PLT_RST_VGA# 1 RV174 2 0_0402_5%
NC12

.1U_0402_10V6-K
AE21 AG3
+3VS AF21 NC13 NC97 AF4 OPT@
NC14 NC98 1
AG21 AF3 CV218
NC15 NC99

2
AG22

G
+3VGARST RV10 2 @ 1 0_0402_5% NC16 @ +3VG_AON +3VG_AON
2
+3VG_AON PCIE_CRX_GTX_P0 CV10 OPT@ 1 2 .1U_0402_10V6-K PCIE_CRX_C_GTX_P0 AC9 AE3

DACs
PCIE_CRX_GTX_N0 CV13 OPT@ 1 2 .1U_0402_10V6-K PCIE_CRX_C_GTX_N0 AB9 PEX_TX0 NC100 AE4 OVERT# 3 1
PEX_TX0_N NC101 WRST# {44}

D
RV12 2 OPT@1 0_0402_5% PCIE_CRX_GTX_P1 CV8 OPT@ 1 2 .1U_0402_10V6-K PCIE_CRX_C_GTX_P1 AB10
PCIE_CRX_GTX_N1 CV9 OPT@ 1 2 .1U_0402_10V6-K PCIE_CRX_C_GTX_N1 AC10 PEX_TX1
PEX_TX1_N QV23

2
PCI EXPRESS

.1U_0402_10V6-K
C AD11 1 C
AC11 PEX_TX2 W5 2N7002KW_SOT323-3 RV13
1 PEX_TX2_N NC102
AC12 AE2 OPT@ 10K_0402_5% CV12
PEX_TX3 NC103

2
CV11 AB12 AF2 @ @

G
.1U_0402_10V6-K AB13 PEX_TX3_N NC104 2

1
2 OPT@ AC13 NC89
AD14 NC90
AC14 NC91 GPU_EVENT#_R 3 1 GPU_EVENT#
NC92
5

D
UV2 AC15
PLT_RST# 2 AB15 NC93 QV4
P

{7,37,40,44} PLT_RST# B NC94

4 SYS_PEX_RST_MON# AB16 B7 VGA_CRT_CLK 2N7002KW_SOT323-3
1 Y AC16 NC95 I2CA_SCL A7 VGA_CRT_DATA @
{8} PXS_RST# Connect to CPU GPIO
G

A NC96 I2CA_SDA
2

AD17 I2C,if not use, can be soft grounded

RV14 AC17 NC17 C9 I2CB_SCL 1 2 RV15
and delete pull up resistor ---colin
3

74LVC1G08GW_SOT353-1-5 10K_0402_5% AC18 NC18 I2CB_SCL C8 I2CB_SDA GC6@ 0_0402_5%

NC19 I2CB_SDA

I2C
OPT@ OPT@ AB18
AB19 NC20 A9 I2CC_SCL
1

AC19 NC21 I2CC_SCL B9 I2CC_SDA

AD20 NC22 I2CC_SDA
AC20 NC23 D9 VGA_SMB_CK2 +3VG_AON +3VG_AON
AC21 NC24 I2CS_SCL D8 VGA_SMB_DA2
NC25 I2CS_SDA Internal Thermal Sensor
AB21
1 2 RV16 AD23 NC26
@ 0_0402_5% AE23 NC27 VGA_CRT_DATA RV17 1 2 3VGS_PWR_EN RV18 2 1
AF24 NC28 60mA OPT@ 2.2K_0402_5% OPT@ 10K_0402_5%
AE24 NC29 L6 +PLLVDD VGA_CRT_CLK RV19 1 2 OVERT# RV20 1 2
AG24 NC30 CORE_PLLVDD M6 OPT@ 2.2K_0402_5% OPT@ 10K_0402_5%
AG25 NC31 SP_PLLVDD I2CB_SCL RV22 1 2 VGA_ALERT# RV23 1 2
NC32 N6
45mA 1 2 RV24 +SP_PLLVDD OPT@ 2.2K_0402_5% OPT@ 10K_0402_5%
VID_PLLVDD @ 0_0402_5% I2CB_SDA RV25 1 2 VGA_AC_DET_R RV26 1 2
45mA OPT@ 2.2K_0402_5% OPT@ 100K_0402_5%
+3VGS +3VG_AON {7} CLK_PCIE_GPU CLK_PCIE_GPU AE8 I2CC_SCL RV28 1 2 PSI_VGA RV29 1 2
CLK_PCIE_GPU# AD8 PEX_REFCLK OPT@ 2.2K_0402_5% OPT@ 10K_0402_5%
{7} CLK_PCIE_GPU# PEX_REFCLK_N
CLK_REQ_GPU# AC6 I2CC_SDA RV30 1 2 GPU_PEX_RST_HOLD# RV31 1 2
PEX_CLKREQ_N OPT@ 2.2K_0402_5% OPT@ 10K_0402_5%
1 2 RV32 PEX_TSTCLK_OUT AF22 XTALOUT RV33 1 2

CLK
Differential signal @ 200_0402_1% PEX_TSTCLK_OUT# AE22 PEX_TSTCLK C11 XTAL_IN @ 10K_0402_5%
PEX_TSTCLK_N XTAL_IN
2

B10 XTAL_OUT
B
RV180 RV37 XTAL_OUT B
10K_0402_5% 10K_0402_5% PLT_RST_VGA# AC7 A10 XTALSSIN 1 OPT@ 2 RV34 10K_0402_5%
GC6@ @ 1 2 RV35 PEX_TERMP AF25 PEX_RST_N XTAL_SSIN C10 XTALOUT 1 OPT@ 2 RV36 10K_0402_5%
DV6 PEX_TERMP XTAL_OUTBUFF Under GPU(below 150mils)
OPT@ 2.49K_0402_1% 180ohms (ESR=0.2) Bead
1

GPU_PEX_RST_HOLD# 2
1 PLT_RST_VGA# N15S-GT-S-A2_FCBGA595 +SP_PLLVDD 1 2 LV1 +1.05VGS
SYS_PEX_RST_MON# 3 OPT@ PBY160808T-181Y-N_2P

22U_0805_6.3V6M
4.7U_0402_6.3V6M
0.1U_0402_10V7K

0.1U_0402_10V7K
150mA 1
CV15
1
CV16
1
CV17
1
CV18 OPT@
BAT54AWT1G_SOT323-3
GC6@
2 2 2 2
OPT@ OPT@ OPT@ OPT@
1 2 RV39
N15VGM@ 0_0402_5%

1 2 RV38
change to BAT54A for cost down OPT@ 10M_0402_5%
YV1
Under GPU Near GPU 30ohms (ESR=0.05) Bead
+3VG_AON +3VG_AON XTAL_IN 1 4
OSC1 GND2 +PLLVDD 1 2 LV2 +1.05VGS
2 3 XTAL_OUT
GND1 OSC2

10P_0402_50V8J

10P_0402_50V8J
1 1 PBY160808T-300Y-N_2P
2

1 1 OPT@
RV40 RV41 CV19 CV20 CV21 CV22
10K_0402_5% 10K_0402_5% OPT@ 27MHZ_10PF_7V27000050 OPT@ 0.1U_0402_10V7K 22U_0805_6.3V6M
@ @ OPT@ 2 2 OPT@
OPT@
2 2
1

+3VG_AON +3VG_AON
.1U_0402_10V6-K

.1U_0402_10V6-K

1 1
CV23 CV24
@ @
2

2
2

A
2 RV44 2 RV45 A
G

10K_0402_5% 10K_0402_5%
OPT@ @
1

{6} GPU_CLKREQ# 1 3 CLK_REQ_GPU# FB_GC6_EN_R 1 3 FB_GC6_EN

D

QV5 QV6
2

2N7002KW_SOT323-3 2N7002KW_SOT323-3
@ RV46 @ RV47
10K_0402_5% 10K_0402_5%
@
Connect to CPU GPIO GC6@ Title
1 2 RV48 1 2 RV49 Security Classification LC Future Center Secret Data
1

OPT@
0_0402_5% GC6@ 0_0402_5%
Issued Date 2013/08/08 Deciphered Date 2013/08/05 N15X_PCIE/ DAC/ GPIO
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
ACLU9
Date: Monday, December 23, 2013 Sheet 19 of 59
5 4 3 2 1
 5 4 3 2 1

D D

UV1C

Part 3 of 6 F11
AC3 NC50 AD10
AC4 NC105 NC51 AD7
Y4 NC106 NC52
Y3 NC107 V5
B19 Symbol update to FBA_CMD32
AA3 NC108 FERMI_RSVD1 V6
AA2 NC109 FERMI_RSVD2 G1
AB1 NC110 NC56 G2
NC111 NC57

NC
AA1 G3
AA4 NC112 NC58 G4
AA5 NC113 NC59 G5
NC114 NC60 G6
NC61 G7
AB5 NC62 V1
AB4 NC115 NC63 V2
AB3 NC116 NC64 W1
AB2 NC117 NC65 W2
AD3 NC118 NC66 W3
AD2 NC119 NC67 W4
AE1 NC120 NC68
AD1 NC121
AD4 NC122
AD5 NC123
NC124 D11 2 1 RV50
BUFRST_N @ 10K_0402_5%

LVDS/TMDS
T2
T3 NC125 D10
T1 NC126 PGOOD
R1 NC127 E10
R2 NC128 NC71

GENERAL
R3 NC129 F10
N2 NC130 NC72
N3 NC131 Symbol update to GPIO8
NC132 D1 STRAP0
STRAP0 D2 STRAP0 {28}
C STRAP1 C
V3 STRAP1 E4 STRAP1 {28}
STRAP2
V4 NC133 STRAP2 E3 STRAP3 STRAP2 {28}
U3 NC134 STRAP3 D3 STRAP3 {28}
STRAP4
U4 NC135 STRAP4 C1 STRAP4 {28}
T4 NC136 NC73
T5 NC137
R4 NC138 F6 1 2 RV51
R5 NC139 MULTI_STRAP_REF0_GND F4 N15SGT@ 40.2K_0402_1%
NC140 MULTI_STRAP_REF1_GNDMLS_REF1 F5
MULTI_STRAP_REF2_GND
N1
M1 NC34
M2 NC35 F12
M3 NC36 THERMDP
K2 NC37 E12
K3 NC38 THERMDN
K1 NC39
J1 NC40
NC41

M4 F2 VCCSENSE_VGA VCCSENSE_VGA
NC42 VDD_SENSE {58}
M5
L3 NC43
NC44 trace width: 16mils
L4
K4 NC45 differential voltage sensing.
NC46
differential signal routing.
K5
J4 NC47 F1 VSSSENSE_VGA
NC48 GND_SENSE VSSSENSE_VGA {58}

J5
N4 NC49
N5 NC141
NC142
TEST
P3 AD9 TESTMODE 1 OPT@ 2 RV52
P4 NC143 TESTMODE AE5 @ 1 10K_0402_5%
B NC144 JTAG_TCK AE6 1 TV1 B
@
JTAG_TDI AF6 1 TV2
@
J2 JTAG_TDO AD6 1 TV3
@
J3 NC145 JTAG_TMS AG4 1TV4 2 RV53
NC146 JTAG_TRST_N OPT@ 10K_0402_5%

H3
H4 NC147
NC148 SERIAL
D12 @ 1
ROM_CS_N B12 TV5
ROM_SI
ROM_SI A12 ROM_SI {28}
ROM_SO
ROM_SO C12 ROM_SO {28}
ROM_SCLK
ROM_SCLK ROM_SCLK {28}

N15S-GT-S-A2_FCBGA595
OPT@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 N15X_LVDS/ HDMI/ THERM

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
C 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
ACLU9
Date: Monday, December 23, 2013 Sheet 20 of 59
5 4 3 2 1
 5 4 3 2 1

UV1D
Near GPU
+1.35VGS Near GPU Under GPU(below 150mils)
2000mA +1.05VGS
3.5A Part 4 of 6
B26 AA10 For RF
C25 FBVDDQ_01 PEX_IOVDDQ_1 AA12

22U_0805_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

33P_0402_50V8J
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
0.1U_0402_10V7K

0.1U_0402_10V7K
4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
FBVDDQ_02 PEX_IOVDDQ_2

CV33

N15VGM@CV34

N15VGM@CV35

N15VGM@CV36

CV37

N15VGM@CV38

CV39

N15VGM@CV40

N15VGM@CV41

N15VGM@CV42

CV215
E23 AA13

1U_0603_25V6M

1U_0603_25V6M
FBVDDQ_03 PEX_IOVDDQ_3 1 1 1 1 1 1 2 2 2 2 1

CV25

CV26

CV27

CV28

CV29

CV30

CV31

CV32
1 2 1 1 1 1 1 1 E26 AA16
F14 FBVDDQ_04 PEX_IOVDDQ_4 AA18
F21 FBVDDQ_05 PEX_IOVDDQ_5 AA19
G13 FBVDDQ_06 PEX_IOVDDQ_6 AA20 2 2 2 2 2 2 1 1 1 1 2
2 1 2 2 2 2 2 2 G14 FBVDDQ_07 PEX_IOVDDQ_7 AA21 OPT@ OPT@ @
FBVDDQ_08 PEX_IOVDDQ_8 OPT@
OPT@ OPT@ OPT@ OPT@ OPT@ OPT@ OPT@ OPT@ G15 AB22
G16 FBVDDQ_09 PEX_IOVDDQ_9 AC23
D FBVDDQ_10 PEX_IOVDDQ_10 Under GPU(below 150mils) +1.05VGS PEX_IOVVDD/Q Decouling D
G18 AD24
G19 FBVDDQ_11 PEX_IOVDDQ_11 AE25
G20 FBVDDQ_12 PEX_IOVDDQ_12 AF26

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
FBVDDQ_13 PEX_IOVDDQ_13 1 1 1 1 MLCC N15V-GM N15S-GT

CV43

N15VGM@CV44

N15VGM@CV45

N15VGM@CV46
G21 AF27
L22 FBVDDQ_14 PEX_IOVDDQ_14
Symbol update to FBVDDQ_AON L24 FBVDDQ_19
H24/H26/J21/K21 L26 FBVDDQ_20 AA22 2 2 2 2
Under Near +3VG_AON
1.0uF 4 1
M21 FBVDDQ_21 PEX_IOVDD_1 AB23
N21 FBVDDQ_22 PEX_IOVDD_2 AC24 OPT@

.1U_0402_10V6-K

1U_0402_6.3V6K

4.7U_0603_6.3V6K
FBVDDQ_23 PEX_IOVDD_3 4.7uF 2 1

CV47

CV48

CV49
R21 AD25 1 1 1

POWER
T21 FBVDDQ_24 PEX_IOVDD_4 AE26
V21 FBVDDQ_25 PEX_IOVDD_5 AE27
W21 FBVDDQ_26 PEX_IOVDD_6 10uF 4 1
FBVDDQ_27 2 2 2
Symbol update to 3V3_AON OPT@ OPT@ OPT@
H24 22uF 4 1
H26 FBVDDQ_AON_1 +3VG_AON
J21 FBVDDQ_AON_2 G10
FBVDDQ_AON_3 3V3_AON_1 Place near balls(Under GPU) Place near GPU
K21 G12
FBVDDQ_AON_4 3V3_AON_2 +3VGS
RV54
V7 G8 +VDD33 1 2
NC149 3V3_MAIN_1 G9

.1U_0402_10V6-K

.1U_0402_10V6-K

1U_0402_6.3V6K

4.7U_0603_6.3V6K
3V3_MAIN_2

CV50

CV51

CV52

CV53
+1.35VGS 1 1 1 1 0_0603_5%
W7
AA6 NC150
NC151 Change RV9 to 0ohm jump
W6 D22 1 2 RV55
Y6 NC152 FB_CAL_VDDQ OPT@ 40.2_0402_1% 2 2 2 2
NC153 OPT@ OPT@ OPT@ OPT@
C24 1 2 RV56
FB_CAL_GND OPT@ 42.2_0402_1%

M7 B25 1 2 RV57 CALIBRATION PIN DDR3

N7 NC154 FB_CAL_TERM OPT@ 51.1_0402_1%
T6 NC155
P6 NC156 FB_CAL_x_PD_VDDQ 40.2Ohm
NC157
Place near balls
C C
FB_CAL_x_PU_GND 42.2Ohm
T7 +3VG_AON
R7 NC158
NC159 Under GPU(below 150mils) FB_CAL_xTERM_GND 51.1Ohm
U6
R6 NC160 AA8

.1U_0402_10V6-K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
NC161 PEX_PLL_HVDD_1

CV55

CV56

CV57
AA9 1 1 1
PEX_PLL_HVDD_2
AB8
PEX_SVDD_3V3
2 2 2
J7 OPT@ OPT@ OPT@ +1.05VGS
NC76 120mA 120ohm (ESR=0.18) Bead
K7
K6 NC77 AA14 +PEX_PLLVDD 2 @ 1 LV3
NC78 PEX_PLLVDD_1

1U_0603_25V6M
H6 AA15 HCB1608KF-121T30_0603

.1U_0402_10V6-K

4.7U_0805_25V6-K
NC79 PEX_PLLVDD_2

CV58

CV59

CV60
J6 1 1 1
NC80
2 1 RV62
OPT@ 0_0603_5%
2 2 2
OPT@ OPT@ OPT@
N15S-GT-S-A2_FCBGA595
OPT@
Place near balls
+3.3VS TO +3VG_AON

+3VS +3VG_AON

+5VALW
3 1
S

D
1

QV11 OPT@
1

B B
RV63 OPT@
G

1 1 1
2

47K_0402_5% @ LP2301ALT1G_SOT23-3 CV62 RV64 CV63

CV61 0.01U_0402_25V7K 470_0603_5% 10U_0603_6.3V6M +1.35V +1.35VGS
.1U_0402_10V6-K @ @ OPT@ +1.35V TO +1.35VGS AON6414AL_DFN8-5
2

2 2 2
2

PXS_PWREN# 1 2 RV65 1
10K_0402_5% 2
OPT@ 1 5 3
1

220U_B2_2.5VM_R15M
QV12 D OPT@ CV67 CV68 CV69 CV70
1

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

.1U_0402_10V6-K
OPT@ CV64 QV13 D CV65 CV66 1
{8,58} PXS_PWREN

1
G .1U_0402_10V6-K PXS_PWREN# 2 1 1 QV14 OPT@ 1 1 1

4
2 G + RV67
1

S 2N7002KW_SOT323-3 470_0603_5%
3

@ S 2N7002KW_SOT323-3 @
3

2 2 2 2 2 2

OPT@

OPT@

OPT@

OPT@
@

@
RV66 OPT@

2
100K_0402_5%
2

+20VSB

1
+5VALW D
1 OPT@2 RV68 FBVDDQ_PWR_EN# 2 QV15
100K_0402_5% G 2N7002KW_SOT323-3
@

1
+3VG_AON +3VGS S
1

3
RV69

1
D CV71 RV70
+3.3VS TO +3VGS 1 2 FBVDDQ_PWR_EN# 2 QV17 0.01U_0402_25V7K 124K_0402_1%
G 2N7002KW_SOT323-3 OPT@ OPT@
OPT@ 2

2
RV171 1 2 47K_0402_5% S

3
0_0603_5% OPT@
N15VGM@

1
D
+5VALW 2 QV18
{23} FBVDDQ_PWR_EN
S

3 1 G 2N7002KW_SOT323-3
QV16 GC6@ OPT@
1

3
1

RV71 GC6@
G

1 1 1
2

A 47K_0402_5% @ CV73 RV72 CV74 A

CV72 LP2301ALT1G_SOT23-3 0.01U_0402_25V7K 470_0603_5% 10U_0603_6.3V6M
.1U_0402_10V6-K @ @ GC6@
2

2 2 2
2

DGPU_PWR_EN# 1 RV73 2
10K_0402_5%
GC6@ 1
1

QV19 D GC6@
1

2 GC6@ CV75 QV20 D

{19,58} 3VGS_PWR_EN .1U_0402_10V6-K 2
G DGPU_PWR_EN#
2 G
Security Classification LC Future Center Secret Data Title
1

S 2N7002KW_SOT323-3
3

@ S 2N7002KW_SOT323-3
Issued Date 2013/08/08 Deciphered Date 2013/08/05 N15X_Power
3

RV74 GC6@
100K_0402_5% THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
2

C 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
ACLU9
Date: Monday, December 23, 2013 Sheet 21 of 59
5 4 3 2 1
 5 4 3 2 1

D D

UV1E
UV1F
A2 Part 5 of 6 K11 +VGA_CORE +VGA_CORE
A26 GND_001 GND_057 K13 Part 6 of 6
AB11 GND_002 GND_058 K15
AB14 GND_003 GND_059 K17 K10 V18
AB17 GND_004 GND_060 L10 K12 VDD_001 VDD_041 V16
AB20 GND_005 GND_061 L12 +VGA_CORE K14 VDD_002 VDD_040 V14
AB24 GND_006 GND_062 L14 K16 VDD_003 VDD_039 V12
GND_007 GND_063 Under GPU VDD_004 VDD_038
AC2 L16 K18 V10
AC22 GND_008 GND_064 L18 L11 VDD_005 VDD_037 U17
GND_009 GND_065 VDD_006 VDD_036

POWER
AC26 L2 L13 U15
AC5 GND_010 GND_066 L23 L15 VDD_007 VDD_035 U13

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
AC8 GND_011 GND_067 L25 L17 VDD_008 VDD_034 U11
AD12 GND_012 GND_068 L5 M10 VDD_009 VDD_033 T18
GND_013 GND_069 1 1 1 1 1 1 1 1 1 1 1 1 1 VDD_010 VDD_032

CV76

CV77

CV78

CV79

CV80

CV81

CV82

CV83

CV84

CV85

CV86

CV87

CV88
AD13 M11 M12 T16
AD15 GND_014 GND_070 M13 M14 VDD_011 VDD_031 T14
AD16 GND_015 GND_071 M15 M16 VDD_012 VDD_030 T12
AD18 GND_016 GND_072 M17 2 2 2 2 2 2 2 2 2 2 2 2 2 M18 VDD_013 VDD_029 T10
AD19 GND_017 GND_073 N10 N11 VDD_014 VDD_028 R17
AD21 GND_018 GND_074 N12 OPT@ OPT@ OPT@ OPT@ OPT@ OPT@ OPT@ OPT@ OPT@ OPT@ @ @ @ N13 VDD_015 VDD_027 R15
AD22 GND_019 GND_075 N14 N15 VDD_016 VDD_026 R13
AE11 GND_020 GND_076 N16 N17 VDD_017 VDD_025 R11
AE14 GND_021 GND_077 N18 P10 VDD_018 VDD_024 P18
AE17 GND_022 GND_078 P11 P12 VDD_019 VDD_023 P16
GND_023 GND_079 For RF VDD_020 VDD_022
AE20 P13 P14

33P_0402_50V8J
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
GND_024 GND_080 VDD_021

CV89

CV90

CV91

CV92

CV213
AF1 P15 1 1 1 1 1
AF11 GND_025 GND_081 P17
GND

AF14 GND_026 GND_082 P2

AF17 GND_027 GND_083 P23
C AF20 GND_028 GND_084 P26 2 2 2 2 2 C
AF23 GND_029 GND_085 P5 OPT@ OPT@ OPT@ OPT@ @
AF5 GND_030 GND_086 R10
AF8 GND_031 GND_087 R12
AG2 GND_032 GND_088 R14
AG26 GND_033 GND_089 R16 N15S-GT-S-A2_FCBGA595
B1 GND_034 GND_090 R18

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
GND_035 GND_091 OPT@
B11 T11
B14 GND_036 GND_092 T13
GND_037 GND_093 1 1 1 1 1 1 1 1 1 1

CV93

CV94

CV95

CV96

CV97

CV98

CV99

CV100

CV101

CV102
B17 T15
B20 GND_038 GND_094 T17
B23 GND_039 GND_095 U10
B27 GND_040 GND_096 U12 2 2 2 2 2 2 2 2 2 2
B5 GND_041 GND_097 U14
B8 GND_042 GND_098 U16 OPT@ OPT@ OPT@ OPT@ OPT@ @ @ @ @ @
E11 GND_043 GND_099 U18
E14 GND_044 GND_100 U2
E17 GND_045 GND_101 U23
E2 GND_046 GND_102 U26
22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
GND_047 GND_103 For RF
E20 U5

33P_0402_50V8J
GND_048 GND_104
CV103

CV104

CV105

CV214
E22 V11 1 1 1 1
E25 GND_049 GND_105 V13
E5 GND_050 GND_106 V15
E8 GND_051 GND_107 V17
H2 GND_052 GND_108 Y2 2 2 2 2
H23 GND_053 GND_109 Y23 OPT@ OPT@ OPT@ @
H25 GND_054 GND_110 Y26
H5 GND_055 GND_111 Y5
GND_056 GND_112

Near GPU
AA7
GND_113 AB7
GND_114

N15S-GT-S-A2_FCBGA595
B B
OPT@

+3VGS

2
RV176
10K_0402_5%
OPT@

1
+VGA_CORE +3VG_AON DV5
+5VALW 2
{57} +1.05VGS_PWRGD 1
VGA_PWRGD {8,44}
1

2 1 3
RV173 +5VALW
2

470_0603_5% RV179 10K_0402_5%

RV178 BAT54AWT1G_SOT323-3
1

RV172 @ OPT@ D
47K_0402_5% 1 2 2 QV25 OPT@
1 2

@ G 2N7002KW_SOT323-3
D OPT@
1

2 QV22 47K_0402_5% S
3

G OPT@
1

D
2 QV21 @ S
3

{57,58} EN_VGA G 2N7002KW_SOT323-3 +1.35VGS

1

C
@ S RV177 1 OPT@2 2 QV24
3

2N7002KW_SOT323-3 2.2K_0402_5% B MMBT3904WH_SOT323-3

CV219

.1U_0402_10V6-K

E
3

1 OPT@
A A

2
@

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 N15X_+VGA CORE, GND

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
C 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
ACLU9
Date: Monday, December 23, 2013 Sheet 22 of 59
5 4 3 2 1
 5 4 3 2 1

FBA_D[0..63]
{24,25,26,27} FBA_D[0..63]

{24,25,26,27} FBA_DQM[7..0]
{24,25,26,27} FBA_DQS[7..0]
{24,25,26,27} FBA_DQS#[7..0]

{24,25,26,27} FBA_CMD[30..0]

UV1B
D D
Only Dual Rank need Termination CMD mapping mod Mode E
Part 2 of 6
Rank0 Rank1
FBA_D0 E18 C27 FBA_ODT_L +1.35VGS
F18 FBA_D00 FBA_CMD00 C26 FBA_ODT_L {24,26}
FBA_D1 FBA_CS1#_L Address 0..31 32..63 0..31 32..63
E16 FBA_D01 FBA_CMD01 E24 FBA_CS1#_L {26}
FBA_D2 FBA_CS0#_L
F17 FBA_D02 FBA_CMD02 F24 FBA_CS0#_L {24}
FBA_D3 FBA_CKE_L FBx_CMD0 ODT_L ODT_L
D20 FBA_D03 FBA_CMD03 D27 FBA_CKE_L {24,26}
FBA_D4 FBA_CMD4
FBA_D5 D21 FBA_D04 FBA_CMD04 D26 FBA_CMD5
FBA_D05 FBA_CMD05 FBx_CMD1 CS1#_L
FBA_D6 F20 F25 FBA_CMD6 FBA_CMD4 RV75 1 2 100_0402_5%

0.1U_0402_10V7K
FBA_D06 FBA_CMD06

CV106
FBA_D7 E21 F26 FBA_CMD7 RV76 1 2 100_0402_5% 1 FBx_CMD2 CS0#_L
FBA_D8 E15 FBA_D07 FBA_CMD07 F23 FBA_CMD8 OPT@
FBA_D9 D15 FBA_D08 FBA_CMD08 G22 FBA_CMD9 FBA_CMD5 RV77 1 OPT@ 2 100_0402_5%
FBA_D09 FBA_CMD09 FBx_CMD3 CKE_L CKE_L
FBA_D10 F15 G23 FBA_CMD10 RV78 1 2 100_0402_5%
FBA_D11 F13 FBA_D10 FBA_CMD10 G24 FBA_RAS# 2
FBA_D11 FBA_CMD11 FBA_RAS# {24,25,26,27} OPT@ FBx_CMD4 A9 A9 A11 A11
FBA_D12 C13 F27 FBA_CMD12 FBA_CMD6 RV79 1 OPT@ 2 100_0402_5%
FBA_D13 B13 FBA_D12 FBA_CMD12 G25 FBA_CMD13 RV80 1 2 100_0402_5%
FBA_D13 FBA_CMD13
@ FBx_CMD5 A6 A6 A7 A7
FBA_D14 E13 G27 FBA_CMD14 OPT@
FBA_D15 D13 FBA_D14 FBA_CMD14 G26 FBA_CAS# FBA_CMD7 1 2 100_0402_5%
FBA_D15 FBA_CMD15 FBA_CAS# {24,25,26,27}
RV81 OPT@ FBx_CMD6 A3 A3 BA1 BA1
FBA_D16 B15 M24 FBA_ODT_H RV82 1 2 100_0402_5%

0.1U_0402_10V7K
FBA_D16 FBA_CMD16 FBA_ODT_H {25,27}

CV107
FBA_D17 C16 M23 FBA_CS1#_H OPT@ 1 FBx_CMD7 A0 A0 A12 A12
A13 FBA_D17 FBA_CMD17 K24 FBA_CS1#_H {27}
FBA_D18 FBA_CS0#_H FBA_CMD8 RV83 1 OPT@ 2 100_0402_5%
A15 FBA_D18 FBA_CMD18 K23 FBA_CS0#_H {25}
FBA_D19 FBA_CKE_H RV84 1 2 100_0402_5% FBx_CMD8 A8 A8 A8 A8
FBA_D20 B18 FBA_D19 FBA_CMD19 M27 FBA_RST# FBA_CKE_H {25,27}
FBA_RST# {24,25,26,27} OPT@
FBA_D21 A18 FBA_D20 FBA_CMD20 M26 FBA_CMD21 FBA_CMD9 RV85 1 OPT@ 2 100_0402_5% 2
FBA_D21 FBA_CMD21 FBx_CMD9 A12 A12 A0 A0
FBA_D22 A19 M25 FBA_CMD22 RV86 1 2 100_0402_5%
FBA_D23 C19 FBA_D22 FBA_CMD22 K26 FBA_CMD23
FBA_D23 FBA_CMD23
OPT@ @ FBx_CMD10 A1 A1 A2 A2
FBA_D24 B24 K22 FBA_CMD24 FBA_CMD10 RV87 1 OPT@ 2 100_0402_5%
FBA_D25 C23 FBA_D24 FBA_CMD24 J23 FBA_CMD25 RV88 1 2 100_0402_5%
FBA_D25 FBA_CMD25 FBx_CMD11 RAS# RAS# RAS# RAS#
FBA_D26 A25 J25 FBA_CMD26 OPT@
FBA_D27 A24 FBA_D26 FBA_CMD26 J24 FBA_CMD27 FBA_RAS# RV89 1 OPT@ 2 100_0402_5%
FBA_D27 FBA_CMD27 FBx_CMD12 A13 A13 A14 A14
FBA_D28 A21 K27 FBA_CMD28 RV90 1 2 100_0402_5%

0.1U_0402_10V7K
FBA_D28 FBA_CMD28

CV108
FBA_D29 B21 K25 FBA_CMD29 OPT@ 1 FBx_CMD13 BA1 BA1 A3 A3
FBA_D30 C20 FBA_D29 FBA_CMD29 J27 FBA_CMD30 FBA_CMD12 RV91 1 OPT@ 2 100_0402_5%
FBA_D31 C21 FBA_D30 FBA_CMD30 J26 RV92 1 2 100_0402_5%
FBA_D31 FBA_CMD31 FBx_CMD14 A14 A14 A13 A13
C
FBA_D32
FBA_D33
R22
R24 FBA_D32 FBA_CMD32
B19
Symbol update to +1.35VGS
FBA_CMD34/35 FBA_CMD13
OPT@
RV93 1 OPT@ 2 100_0402_5% 2
FBx_CMD15 CAS# CAS# CAS# CAS# C
FBA_D33

INTERFACE A
FBA_D34 T22 F22 RV121 2 @ 1 60.4_0402_1% RV94 1 2 100_0402_5%
FBA_D35 R23 FBA_D34 FBA_CMD34 J22 RV122 2 1 60.4_0402_1%
FBA_D35 FBA_CMD35
OPT@ @ FBx_CMD16 ODT_H ODT_H
FBA_D36 N25 @ FBA_CMD14 RV95 1 OPT@ 2 100_0402_5%
FBA_D37 N26 FBA_D36 D19 FBA_DQM0 RV96 1 2 100_0402_5% FBx_CMD17 CS1#_H

MEMORY
FBA_D38 N23 FBA_D37 FBA_DQM0 D14 FBA_DQM1 OPT@
FBA_D39 N24 FBA_D38 FBA_DQM1 C17 FBA_DQM2 FBA_CAS# RV97 1 OPT@ 2 100_0402_5%
30ohms (ESR=0.01) Bead FBA_D39 FBA_DQM2 FBx_CMD18 CS0#_H
FBA_D40 V23 C22 FBA_DQM3 RV98 1 2 100_0402_5%

0.1U_0402_10V7K
FBA_D40 FBA_DQM3

CV109
FBA_D41 V22 P24 FBA_DQM4 OPT@ 1 FBx_CMD19 CKE_H CKE_H
+1.05VGS +FB_PLLAVDD FBA_D42 T23 FBA_D41 FBA_DQM4 W24 FBA_DQM5 FBA_CMD21 RV99 1 OPT@ 2 100_0402_5%
FBA_D43 U22 FBA_D42 FBA_DQM5 AA25 FBA_DQM6 RV100 1 2 100_0402_5%
200mA FBA_D43 FBA_DQM6 FBx_CMD20 RST RST RST RST
FBA_D44 Y24 U25 FBA_DQM7 OPT@
1 2 LV4 FBA_D45 AA24 FBA_D44 FBA_DQM7 FBA_CMD22 RV101 1 OPT@ 2 100_0402_5% 2
FBA_D45 FBx_CMD21 A7 A7 A6 A6
HCB1608KF-300T60_2P FBA_D46 Y22 F19 FBA_DQS#0 RV102 1 2 100_0402_5%
FBA_D47 AA23 FBA_D46 FBA_DQS_RN0 C14 FBA_DQS#1 @
OPT@ FBA_D47 FBA_DQS_RN1
OPT@ FBx_CMD22 A4 A4 A5 A5
FBA_D48 AD27 A16 FBA_DQS#2 FBA_CMD23 RV103 1 OPT@ 2 100_0402_5%
FBA_D49 AB25 FBA_D48 FBA_DQS_RN2 A22 FBA_DQS#3 RV104 1 2 100_0402_5%
Place close to BGA FBx_CMD23 A11 A11 A9 A9
FBA_D50 AD26 FBA_D49 FBA_DQS_RN3 P25 FBA_DQS#4 OPT@
FBA_D51 AC25 FBA_D50 FBA_DQS_RN4 W22 FBA_DQS#5 FBA_CMD24 RV105 1 OPT@ 2 100_0402_5%
FBA_D51 FBA_DQS_RN5 FBx_CMD24 A2 A2 A1 A1
FBA_D52 AA27 AB27 FBA_DQS#6 RV106 1 2 100_0402_5%

0.1U_0402_10V7K
FBA_D52 FBA_DQS_RN6

CV110
Place close to BGA Place close to ball FBA_D53 AA26 T27 FBA_DQS#7 OPT@ 1 FBx_CMD25 A10 A10 WE# WE#
FBA_D54 W26 FBA_D53 FBA_DQS_RN7 FBA_CMD25 RV107 1 OPT@ 2 100_0402_5%
FBA_D55 Y25 FBA_D54 E19 FBA_DQS0 RV108 1 2 100_0402_5%
+FB_PLLAVDD FBA_D55 FBA_DQS_WP0 FBx_CMD26 A5 A5 A4 A4
R26 C15
22U_0805_6.3V6M

FBA_D56 FBA_DQS1
1U_0402_6.3V6K

0.1U_0402_10V7K

OPT@
FBA_D56 FBA_DQS_WP1 2
CV111

CV112

CV113

1 1 1 FBA_D57 T25 B16 FBA_DQS2 FBA_CMD26 RV109 1 OPT@ 2 100_0402_5% FBx_CMD27 BA2 BA2
FBA_D58 N27 FBA_D57 FBA_DQS_WP2 B22 FBA_DQS3 RV110 1 2 100_0402_5%
FBA_D59 R27 FBA_D58 FBA_DQS_WP3 R25 FBA_DQS4
FBA_D59 FBA_DQS_WP4
OPT@ @ FBx_CMD28 WE# WE# A10 A10
FBA_D60 V26 W23 FBA_DQS5 FBA_CMD27 RV111 1 OPT@ 2 100_0402_5%
2 2 2 FBA_D61 V27 FBA_D60 FBA_DQS_WP5 AB26 FBA_DQS6 RV112 1 2 100_0402_5%
FBA_D61 FBA_DQS_WP6 FBx_CMD29 BA0 BA0 BA0 BA0
FBA_D62 W27 T26 FBA_DQS7 OPT@
OPT@ OPT@ OPT@ FBA_D63 W25 FBA_D62 FBA_DQS_WP7 FBA_CMD28 RV113 1 OPT@ 2 100_0402_5%
FBA_D63 FBx_CMD30 BA2 BA2
D24 FBA_CLK0 RV114 1 2 100_0402_5%

0.1U_0402_10V7K
FBA_CLK0 FBA_CLK0 {24,26}

CV114
F16 D25 FBA_CLK0# OPT@ 1
P22 FB_PLLAVDD_1 FBA_CLK0_N FBA_CLK0# {24,26}
FBA_CMD29 RV115 1 OPT@ 2 100_0402_5%
FB_PLLAVDD_2 N22 FBA_CLK1 RV116 1 2 100_0402_5%
D23 FBA_CLK1 M22 FBA_CLK1 {25,27}
FBA_CLK1# OPT@
FB_VREF FBA_CLK1_N FBA_CLK1# {25,27} 2
+FB_PLLAVDD FBA_CMD30 RV117 1 OPT@ 2 100_0402_5%
Place close to ball D18 RV118 1 2 100_0402_5%
B
1 2 CV115 H22 FBA_WCK01 C18 @
B
OPT@
OPT@ 0.1U_0402_10V7K FB_DLLAVDD FBA_WCK01_N D17 OPT@
FB_GC6_EN RV119 1 @ 2 0_0402_5% FB_CLAMP F3 FBA_WCK23 D16
RV120 1 OPT@ 2 10K_0402_5% FB_CLAMP FBA_WCK23_N T24
FBA_WCK45 U24
FBA_WCK45_N V24
FBA_WCK67 V25
FBA_WCK67_N

N15S-GT-S-A2_FCBGA595
OPT@

DV4 GC6@
{19} FB_GC6_EN FB_GC6_ENRV123 1 2 0_0402_5% GC6_EN 2
1
3 FBVDDQ_PWR_EN {21}
1

RV124 1 2 BAV70W-7-F_SOT323-3
+3VGS RV125
10K_0402_5%
200K_0402_5%
OPT@ GC6@
1 2 RV126
2

{57,58} DGPU_PWROK
0_0402_5%
A N15VGM@ A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 N15X_MEM Interface

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
C 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
ACLU9
Date: Monday, December 23, 2013 Sheet 23 of 59
5 4 3 2 1
 5 4 3 2 1

at least 16 mils width(optimal)

20 mils spacing to other signals /planes FBA_D[0..63] {23,25,26,27}
+1.35VGS
D FBA_CMD[30..0] {23,25,26,27} D
1

RANKA@
FBA_DQM[7..0] {23,25,26,27}
RV128
1.33K_0402_1% UV6 UV5
FBA_DQS[7..0] {23,25,26,27}
2

+FBA_VREFCA0 +FBA_VREFCA0 M8 E3 FBA_D5 +FBA_VREFCA0 M8 E3 FBA_D11

+FBA_VREFCA0 {26} H1 VREFCA DQL0 F7 H1 VREFCA DQL0 F7 FBA_DQS#[7..0] {23,25,26,27}
+FBA_VREFDQ0 FBA_D1 +FBA_VREFDQ0 FBA_D13
VREFDQ DQL1 VREFDQ DQL1
1

1 F2 FBA_D7 F2 FBA_D8
RANKA@ CV116 FBA_CMD7 N3 DQL2 F8 FBA_D0 FBA_CMD7 N3 DQL2 F8 FBA_D15
RV127 .01U_0402_16V7-K FBA_CMD10 P7 A0
A1
DQL3
DQL4
H3 FBA_D4 Group0 FBA_CMD10 P7 A0
A1
DQL3
DQL4
H3 FBA_D10 Group1 CMD mapping mod Mode E
1.33K_0402_1% RANKA@ FBA_CMD24 P3 H8 FBA_D3 FBA_CMD24 P3 H8 FBA_D14
2 FBA_CMD6 N2 A2 DQL5 G2 FBA_D6 FBA_CMD6 N2 A2 DQL5 G2 FBA_D9 Rank0 Rank1
2

FBA_CMD22 P8 A3 DQL6 H7 FBA_D2 FBA_CMD22 P8 A3 DQL6 H7 FBA_D12

FBA_CMD26 P2 A4 DQL7 FBA_CMD26 P2 A4 DQL7 Address
A5 A5 0..31 32..63 0..31 32..63
FBA_CMD5 R8 FBA_CMD5 R8
FBA_CMD21 R2 A6 D7 FBA_D31 FBA_CMD21 R2 A6 D7 FBA_D17
A7 DQU0 A7 DQU0 FBx_CMD0 ODT_L ODT_L
FBA_CMD8 T8 C3 FBA_D25 FBA_CMD8 T8 C3 FBA_D22
FBA_CMD4 R3 A8 DQU1 C8 FBA_D30 FBA_CMD4 R3 A8 DQU1 C8 FBA_D16
A9 DQU2 A9 DQU2 FBx_CMD1 CS1#_L
FBA_CMD25 L7 C2 FBA_D24 FBA_CMD25 L7 C2 FBA_D23 Group2
FBA_CMD23 R7 A10/AP DQU3 A7 FBA_D29 FBA_CMD23 R7 A10/AP DQU3 A7 FBA_D19
+1.35VGS
A11 DQU4 Group3 A11 DQU4 FBx_CMD2 CS0#_L
FBA_CMD9 N7 A2 FBA_D27 FBA_CMD9 N7 A2 FBA_D21
FBA_CMD12 T3 A12/BC DQU5 B8 FBA_D28 FBA_CMD12 T3 A12/BC DQU5 B8 FBA_D18
A13 DQU6 A13 DQU6 FBx_CMD3 CKE_L CKE_L
1

FBA_CMD14 T7 A3 FBA_D26 FBA_CMD14 T7 A3 FBA_D20

A14 DQU7 A14 DQU7
RANKA@ FBx_CMD4 A9 A9 A11 A11
RV167 +1.35VGS +1.35VGS
1.33K_0402_1% FBx_CMD5 A6 A6 A7 A7
FBA_CMD29 M2 B2 FBA_CMD29 M2 B2
2

+FBA_VREFDQ0 FBA_CMD13 N8 BA0 VDD_1 D9 FBA_CMD13 N8 BA0 VDD_1 D9

+FBA_VREFDQ0 {26} BA1 VDD_2 BA1 VDD_2 FBx_CMD6 A3 A3 BA1 BA1
FBA_CMD27 M3 G7 FBA_CMD27 M3 G7
BA2 VDD_3 BA2 VDD_3
1

1 K2 K2 FBx_CMD7 A0 A0 A12 A12

RANKA@ CV216 VDD_4 K8 VDD_4 K8
.01U_0402_16V7-K VDD_5 N1 VDD_5 N1
RV168
VDD_6 VDD_6 FBx_CMD8 A8 A8 A8 A8
1.33K_0402_1% RANKA@ FBA_CLK0 J7 N9 FBA_CLK0 J7 N9
2 {23,26} FBA_CLK0 FBA_CLK0# K7 CK VDD_7 R1 FBA_CLK0# K7 CK VDD_7 R1 FBx_CMD9 A12 A12 A0 A0
2

{23,26} FBA_CLK0# K9 CK VDD_8 R9 K9 CK VDD_8 R9

FBA_CKE_L FBA_CKE_L
{23,26} FBA_CKE_L CKE VDD_9 CKE VDD_9
FBx_CMD10 A1 A1 A2 A2
C C
FBA_ODT_L K1 A1 FBA_ODT_L K1 A1 FBx_CMD11 RAS# RAS# RAS# RAS#
{23,26} FBA_ODT_L FBA_CS0#_L L2 ODT VDDQ_1 A8 FBA_CS0#_L L2 ODT VDDQ_1 A8
{23} FBA_CS0#_L J3 CS VDDQ_2 C1 J3 CS VDDQ_2 C1
FBA_RAS# FBA_RAS# FBx_CMD12 A13 A13 A14 A14
{23,25,26,27} FBA_RAS# K3 RAS VDDQ_3 C9 K3 RAS VDDQ_3 C9
FBA_CAS# FBA_CAS#
{23,25,26,27} FBA_CAS# L3 CAS VDDQ_4 D2 L3 CAS VDDQ_4 D2
FBA_CMD28 FBA_CMD28 FBx_CMD13 BA1 BA1 A3 A3
WE VDDQ_5 E9 WE VDDQ_5 E9
VDDQ_6 F1 VDDQ_6 F1
VDDQ_7 VDDQ_7 FBx_CMD14 A14 A14 A13 A13
FBA_DQS0 F3 H2 FBA_DQS1 F3 H2
FBA_CLK0 FBA_DQS3 C7 DQSL VDDQ_8 H9 FBA_DQS2 C7 DQSL VDDQ_8 H9
DQSU VDDQ_9 DQSU VDDQ_9 FBx_CMD15 CAS# CAS# CAS# CAS#
FBx_CMD16 ODT_H ODT_H
1

FBA_DQM0 E7 A9 FBA_DQM1 E7 A9
FBA_DQM3 D3 DML VSS_1 B3 FBA_DQM2 D3 DML VSS_1 B3
RV129
DMU VSS_2 DMU VSS_2 FBx_CMD17 CS1#_H
162_0402_1% E1 E1
VSS_3 G8 VSS_3 G8
RANKA@
VSS_4 VSS_4 FBx_CMD18 CS0#_H
FBA_DQS#0 G3 J2 FBA_DQS#1 G3 J2
2

FBA_DQS#3 B7 DQSL VSS_5 J8 FBA_DQS#2 B7 DQSL VSS_5 J8

DQSU VSS_6 DQSU VSS_6 FBx_CMD19 CKE_H CKE_H
FBA_CLK0# M1 M1
VSS_7 M9 VSS_7 M9
VSS_8 VSS_8 FBx_CMD20 RST RST RST RST
P1 P1
FBA_RST# T2 VSS_9 P9 FBA_RST# T2 VSS_9 P9
{23,25,26,27} FBA_RST# RESET VSS_10 RESET VSS_10 FBx_CMD21 A7 A7 A6 A6
T1 T1
1 2 RV130 L8 VSS_11 T9 L8 VSS_11 T9
ZQ VSS_12 ZQ VSS_12 FBx_CMD22 A4 A4 A5 A5
243_0402_1%
RANKA@ FBx_CMD23 A11 A11 A9 A9

1
J1 B1 J1 B1
NC1 VSSQ_1 NC1 VSSQ_1
1

L1 B9 RV132 L1 B9 FBx_CMD24 A2 A2 A1 A1
RV131 J9 NC2 VSSQ_2 D1 243_0402_1% J9 NC2 VSSQ_2 D1
FBA_ODT_L L9 NC3 VSSQ_3 D8 L9 NC3 VSSQ_3 D8
10K_0402_5%
NC4 VSSQ_4
RANKA@
NC4 VSSQ_4 FBx_CMD25 A10 A10 WE# WE#
RANKA@ M7 E2 M7 E2

2
NC5 VSSQ_5 E8 NC5 VSSQ_5 E8 FBx_CMD26 A5 A5 A4 A4
2

FBA_CKE_L VSSQ_6 F9 VSSQ_6 F9

VSSQ_7 G1 VSSQ_7 G1
VSSQ_8 VSSQ_8 FBx_CMD27 BA2 BA2
G9 G9
VSSQ_9 VSSQ_9
1

FBx_CMD28 WE# WE# A10 A10

RV133 RV134 96-BALL 96-BALL
B
10K_0402_5% 10K_0402_5% SDRAM DDR3 SDRAM DDR3 FBx_CMD29 BA0 BA0 BA0 BA0 B
RANKA@ RANKA@ K4W4G1646B-HC11_FBGA96 K4W4G1646B-HC11_FBGA96
@ @ FBx_CMD30 BA2 BA2
2

+1.35VGS UV6 SIDE +1.35VGS +1.35VGS UV5 SIDE +1.35VGS

For RF
1U_0603_25V6M

1U_0603_25V6M

1U_0603_25V6M

1U_0603_25V6M

1U_0603_25V6M

1U_0603_25V6M

1U_0603_25V6M

1U_0603_25V6M
33P_0402_50V8J

33P_0402_50V8J
0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K
CV117

CV118

CV119

CV120

CV121

CV122

CV127

CV129

CV130

CV131

CV132

CV133

CV134

CV139
1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 2 2 2 2
For RF
RANKA@ RANKA@ RANKA@ RANKA@ RANKA@ RANKA@ @ RANKA@ RANKA@ RANKA@ RANKA@ RANKA@ RANKA@ @

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 DDR3 VRAM Rank0_L

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
C 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
ACLU9
Date: Monday, December 23, 2013 Sheet 24 of 59
5 4 3 2 1
 5 4 3 2 1

at least 16 mils width(optimal)

20 mils spacing to other signals /planes

+1.35VGS
1

D FBA_D[0..63] {23,24,26,27} D
RANKA@
RV135
1.33K_0402_1%
FBA_CMD[30..0] {23,24,26,27}
UV8 UV7
2

+FBA_VREFCA1
+FBA_VREFCA1 {27} M8 E3 M8 E3 FBA_DQM[7..0] {23,24,26,27}
+FBA_VREFCA1 FBA_D34 +FBA_VREFCA1 FBA_D44
VREFCA DQL0 VREFCA DQL0
1

1 +FBA_VREFDQ1 H1 F7 FBA_D38 +FBA_VREFDQ1 H1 F7 FBA_D43

VREFDQ DQL1 F2 VREFDQ DQL1 F2 FBA_DQS[7..0] {23,24,26,27}
RANKA@ CV141 FBA_D35 FBA_D45
RV136 .01U_0402_16V7-K FBA_CMD7 N3 DQL2 F8 FBA_D39 FBA_CMD7 N3 DQL2 F8 FBA_D40
A0 DQL3 A0 DQL3 Group5 FBA_DQS#[7..0] {23,24,26,27}
1.33K_0402_1% RANKA@ FBA_CMD10 P7 H3 FBA_D32 Group4 FBA_CMD10 P7 H3 FBA_D47
2 FBA_CMD24 P3 A1 DQL4 H8 FBA_D36 FBA_CMD24 P3 A1 DQL4 H8 FBA_D42
2

FBA_CMD6 N2 A2 DQL5 G2 FBA_D33 FBA_CMD6 N2 A2 DQL5 G2 FBA_D46

FBA_CMD22 P8 A3 DQL6 H7 FBA_D37 FBA_CMD22 P8 A3 DQL6 H7 FBA_D41
FBA_CMD26 P2 A4 DQL7 FBA_CMD26 P2 A4 DQL7
FBA_CMD5 R8 A5 FBA_CMD5 R8 A5
FBA_CMD21 R2 A6 D7 FBA_D59 FBA_CMD21 R2 A6 D7 FBA_D52
FBA_CMD8 T8 A7
A8
DQU0
DQU1
C3 FBA_D62 FBA_CMD8 T8 A7
A8
DQU0
DQU1
C3 FBA_D50 CMD mapping mod Mode E
FBA_CMD4 R3 C8 FBA_D58 FBA_CMD4 R3 C8 FBA_D55
FBA_CMD25 L7 A9 DQU2 C2 FBA_D63 FBA_CMD25 L7 A9 DQU2 C2 FBA_D51
+1.35VGS
A10/AP DQU3 A10/AP DQU3 Rank0 Rank1
FBA_CMD23 R7 A7 FBA_D57 Group7 FBA_CMD23 R7 A7 FBA_D53 Group6
FBA_CMD9 N7 A11 DQU4 A2 FBA_D60 FBA_CMD9 N7 A11 DQU4 A2 FBA_D48 Address 0..31 32..63 0..31 32..63
A12/BC DQU5 A12/BC DQU5
1

FBA_CMD12 T3 B8 FBA_D56 FBA_CMD12 T3 B8 FBA_D54

FBA_CMD14 T7 A13 DQU6 A3 FBA_D61 FBA_CMD14 T7 A13 DQU6 A3 FBA_D49
RANKA@
A14 DQU7 A14 DQU7 FBx_CMD0 ODT_L ODT_L
RV169
1.33K_0402_1% +1.35VGS +1.35VGS FBx_CMD1 CS1#_L
2

+FBA_VREFDQ1 FBA_CMD29 M2 B2 FBA_CMD29 M2 B2 FBx_CMD2 CS0#_L

+FBA_VREFDQ1 {27} N8 BA0 VDD_1 D9 N8 BA0 VDD_1 D9
FBA_CMD13 FBA_CMD13
BA1 VDD_2 BA1 VDD_2
1

1 FBA_CMD27 M3 G7 FBA_CMD27 M3 G7 FBx_CMD3 CKE_L CKE_L

RANKA@ CV217 BA2 VDD_3 K2 BA2 VDD_3 K2
.01U_0402_16V7-K VDD_4 K8 VDD_4 K8
RV170
VDD_5 VDD_5 FBx_CMD4 A9 A9 A11 A11
1.33K_0402_1% RANKA@ N1 N1
2 FBA_CLK1 J7 VDD_6 N9 FBA_CLK1 J7 VDD_6 N9 FBx_CMD5 A6 A6 A7 A7
2

{23,27} FBA_CLK1 K7 CK VDD_7 R1 CK VDD_7

FBA_CLK1# FBA_CLK1# K7 R1
{23,27} FBA_CLK1# FBA_CKE_H K9 CK VDD_8 R9 FBA_CKE_H K9 CK VDD_8 R9
{23,27} FBA_CKE_H CKE VDD_9 CKE VDD_9 FBx_CMD6 A3 A3 BA1 BA1
FBx_CMD7 A0 A0 A12 A12
C FBA_ODT_H K1 A1 FBA_ODT_H K1 A1 C
{23,27} FBA_ODT_H L2 ODT VDDQ_1 A8 L2 ODT VDDQ_1 A8
FBA_CS0#_H FBA_CS0#_H FBx_CMD8 A8 A8 A8 A8
{23} FBA_CS0#_H FBA_RAS# J3 CS VDDQ_2 C1 FBA_RAS# J3 CS VDDQ_2 C1
{23,24,26,27} FBA_RAS# K3 RAS VDDQ_3 C9 K3 RAS VDDQ_3 C9
FBA_CAS# FBA_CAS# FBx_CMD9 A12 A12 A0 A0
{23,24,26,27} FBA_CAS# L3 CAS VDDQ_4 D2 L3 CAS VDDQ_4 D2
FBA_CMD28 FBA_CMD28
FBA_CLK1 WE VDDQ_5 E9 WE VDDQ_5 E9
VDDQ_6 VDDQ_6 FBx_CMD10 A1 A1 A2 A2
F1 F1
FBA_DQS4 F3 VDDQ_7 H2 FBA_DQS5 F3 VDDQ_7 H2
DQSL VDDQ_8 DQSL VDDQ_8 FBx_CMD11 RAS# RAS# RAS# RAS#
1

FBA_DQS7 C7 H9 FBA_DQS6 C7 H9
DQSU VDDQ_9 DQSU VDDQ_9
RV137 FBx_CMD12 A13 A13 A14 A14
162_0402_1%
FBA_DQM4 E7 A9 FBA_DQM5 E7 A9 FBx_CMD13 BA1 BA1 A3 A3
RANKA@ FBA_DQM7 D3 DML VSS_1 B3 FBA_DQM6 D3 DML VSS_1 B3
2

DMU VSS_2 E1 DMU VSS_2 E1

VSS_3 VSS_3 FBx_CMD14 A14 A14 A13 A13
FBA_CLK1# G8 G8
FBA_DQS#4 G3 VSS_4 J2 FBA_DQS#5 G3 VSS_4 J2
DQSL VSS_5 DQSL VSS_5 FBx_CMD15 CAS# CAS# CAS# CAS#
FBA_DQS#7 B7 J8 FBA_DQS#6 B7 J8
DQSU VSS_6 M1 DQSU VSS_6 M1
VSS_7 VSS_7 FBx_CMD16 ODT_H ODT_H
M9 M9
VSS_8 P1 VSS_8 P1
VSS_9 VSS_9 FBx_CMD17 CS1#_H
FBA_RST# T2 P9 FBA_RST# T2 P9
{23,24,26,27} FBA_RST# RESET VSS_10 T1 RESET VSS_10 T1
VSS_11 VSS_11 FBx_CMD18 CS0#_H
L8 T9 L8 T9
FBA_CKE_H ZQ VSS_12 ZQ VSS_12
FBx_CMD19 CKE_H CKE_H

1
J1 B1 J1 B1 FBx_CMD20 RST RST RST RST
NC1 VSSQ_1 NC1 VSSQ_1
1

FBA_ODT_H L1 B9 RV141 L1 B9
J9 NC2 VSSQ_2 D1 J9 NC2 VSSQ_2 D1
RV140
NC3 VSSQ_3
243_0402_1%
NC3 VSSQ_3 FBx_CMD21 A7 A7 A6 A6
243_0402_1% L9 D8 RANKA@ L9 D8
M7 NC4 VSSQ_4 E2 M7 NC4 VSSQ_4 E2
RANKA@ FBx_CMD22 A4 A4 A5 A5

2
NC5 VSSQ_5 NC5 VSSQ_5
1

E8 E8
2

VSSQ_6 F9 VSSQ_6 F9
RV138 RV139
VSSQ_7 VSSQ_7 FBx_CMD23 A11 A11 A9 A9
10K_0402_5% 10K_0402_5% G1 G1
VSSQ_8 G9 VSSQ_8 G9
RANKA@ RANKA@
VSSQ_9 VSSQ_9 FBx_CMD24 A2 A2 A1 A1
2

96-BALL 96-BALL FBx_CMD25 A10 A10 WE# WE#

SDRAM DDR3 SDRAM DDR3
B
K4W4G1646B-HC11_FBGA96 K4W4G1646B-HC11_FBGA96 FBx_CMD26 A5 A5 A4 A4 B
@ @
FBx_CMD27 BA2 BA2
FBx_CMD28 WE# WE# A10 A10
FBx_CMD29 BA0 BA0 BA0 BA0
FBx_CMD30 BA2 BA2

+1.35VGS UV8 SIDE +1.35VGS +1.35VGS UV7 SIDE +1.35VGS

For RF For RF
1U_0603_25V6M

1U_0603_25V6M

1U_0603_25V6M

1U_0603_25V6M

1U_0603_25V6M

1U_0603_25V6M

1U_0603_25V6M

1U_0603_25V6M
33P_0402_50V8J

33P_0402_50V8J
0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K
CV142

CV143

CV144

CV145

CV146

CV147

CV152

CV154

CV155

CV156

CV157

CV158

CV159

CV164
1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 2 2 2 2

RANKA@ RANKA@ RANKA@ RANKA@ RANKA@ RANKA@ RANKA@ RANKA@ RANKA@ RANKA@ RANKA@ RANKA@
@ @

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 DDR3 VRAM Rank0_H

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
C 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
ACLU9
Date: Monday, December 23, 2013 Sheet 25 of 59
5 4 3 2 1
 5 4 3 2 1

FBA_D[0..63] {23,24,25,27}

FBA_CMD[30..0] {23,24,25,27}

FBA_DQM[7..0] {23,24,25,27}

FBA_DQS[7..0] {23,24,25,27}

D FBA_DQS#[7..0] {23,24,25,27} D

UV9 UV10

+FBA_VREFCA0 M8 E3 FBA_D1 +FBA_VREFCA0 M8 E3 FBA_D13

{24} +FBA_VREFCA0 H1 VREFCA DQL0 F7 H1 VREFCA DQL0 F7
+FBA_VREFDQ0 FBA_D5 +FBA_VREFDQ0 FBA_D11
{24} +FBA_VREFDQ0 VREFDQ DQL1 F2 VREFDQ DQL1 F2
at least 16 mils width(optimal) FBA_D0 FBA_D15
FBA_CMD9 N3 DQL2 F8 FBA_D7 FBA_CMD9 N3 DQL2 F8 FBA_D8
20 mils spacing to other signals /planes A0 DQL3 A0 DQL3 Group1
FBA_CMD24 P7 H3 FBA_D2 Group0 FBA_CMD24 P7 H3 FBA_D12
FBA_CMD10 P3 A1 DQL4 H8 FBA_D6 FBA_CMD10 P3 A1 DQL4 H8 FBA_D9
FBA_CMD13 N2 A2 DQL5 G2 FBA_D3 FBA_CMD13 N2 A2 DQL5 G2 FBA_D14
FBA_CMD26 P8 A3 DQL6 H7 FBA_D4 FBA_CMD26 P8 A3 DQL6 H7 FBA_D10
FBA_CMD22 P2 A4 DQL7 FBA_CMD22 P2 A4 DQL7
FBA_CMD21 R8 A5 FBA_CMD21 R8 A5
FBA_CMD5 R2 A6 D7 FBA_D25 FBA_CMD5 R2 A6 D7 FBA_D22
FBA_CMD8 T8 A7 DQU0 C3 FBA_D31 FBA_CMD8 T8 A7 DQU0 C3 FBA_D17
FBA_CMD23 R3 A8 DQU1 C8 FBA_D24 FBA_CMD23 R3 A8 DQU1 C8 FBA_D23
FBA_CMD28 L7 A9 DQU2 C2 FBA_D30 FBA_CMD28 L7 A9 DQU2 C2 FBA_D16
A10/AP DQU3 A10/AP DQU3 Group2
FBA_CMD4 R7 A7 FBA_D26 Group3 FBA_CMD4 R7 A7 FBA_D20
FBA_CMD7 N7 A11 DQU4 A2 FBA_D28 FBA_CMD7 N7 A11 DQU4 A2 FBA_D18
FBA_CMD14 T3 A12/BC DQU5 B8 FBA_D27 FBA_CMD14 T3 A12/BC DQU5 B8 FBA_D21
FBA_CMD12 T7 A13 DQU6 A3 FBA_D29 FBA_CMD12 T7 A13 DQU6 A3 FBA_D19
A14 DQU7 A14 DQU7 CMD mapping mod Mode E
+1.35VGS +1.35VGS
Rank0 Rank1
FBA_CMD29 M2 B2 FBA_CMD29 M2 B2
FBA_CMD6 N8 BA0 VDD_1 D9 FBA_CMD6 N8 BA0 VDD_1 D9
BA1 VDD_2 BA1 VDD_2
Address 0..31 32..63 0..31 32..63
FBA_CMD30 M3 G7 FBA_CMD30 M3 G7
BA2 VDD_3 K2 BA2 VDD_3 K2
VDD_4 VDD_4 FBx_CMD0 ODT_L ODT_L
K8 K8
VDD_5 N1 VDD_5 N1
VDD_6 VDD_6 FBx_CMD1 CS1#_L
FBA_CLK0 J7 N9 FBA_CLK0 J7 N9
{23,24} FBA_CLK0 K7 CK VDD_7 R1 K7 CK VDD_7 R1
FBA_CLK0# FBA_CLK0# FBx_CMD2 CS0#_L
{23,24} FBA_CLK0# FBA_CKE_L K9 CK VDD_8 R9 FBA_CKE_L K9 CK VDD_8 R9
{23,24} FBA_CKE_L CKE VDD_9 CKE VDD_9
FBx_CMD3 CKE_L CKE_L
C FBA_ODT_L K1 A1 FBA_ODT_L K1 A1 FBx_CMD4 A9 A9 A11 A11 C
{23,24} FBA_ODT_L L2 ODT VDDQ_1 A8 L2 ODT VDDQ_1 A8
FBA_CS1#_L FBA_CS1#_L
{23} FBA_CS1#_L FBA_RAS# J3 CS VDDQ_2 C1 FBA_RAS# J3 CS VDDQ_2 C1
{23,24,25,27} FBA_RAS# RAS VDDQ_3 RAS VDDQ_3 FBx_CMD5 A6 A6 A7 A7
FBA_CAS# K3 C9 FBA_CAS# K3 C9
{23,24,25,27} FBA_CAS# L3 CAS VDDQ_4 D2 L3 CAS VDDQ_4 D2
FBA_CMD25 FBA_CMD25 FBx_CMD6 A3 A3 BA1 BA1
WE VDDQ_5 E9 WE VDDQ_5 E9
VDDQ_6 F1 VDDQ_6 F1
VDDQ_7 VDDQ_7 FBx_CMD7 A0 A0 A12 A12
FBA_DQS0 F3 H2 FBA_DQS1 F3 H2
FBA_DQS3 C7 DQSL VDDQ_8 H9 FBA_DQS2 C7 DQSL VDDQ_8 H9
DQSU VDDQ_9 DQSU VDDQ_9 FBx_CMD8 A8 A8 A8 A8
FBx_CMD9 A12 A12 A0 A0
FBA_DQM0 E7 A9 FBA_DQM1 E7 A9
FBA_DQM3 D3 DML VSS_1 B3 FBA_DQM2 D3 DML VSS_1 B3
DMU VSS_2 DMU VSS_2 FBx_CMD10 A1 A1 A2 A2
E1 E1
VSS_3 G8 VSS_3 G8
VSS_4 VSS_4 FBx_CMD11 RAS# RAS# RAS# RAS#
FBA_DQS#0 G3 J2 FBA_DQS#1 G3 J2
FBA_DQS#3 B7 DQSL VSS_5 J8 FBA_DQS#2 B7 DQSL VSS_5 J8
DQSU VSS_6 DQSU VSS_6 FBx_CMD12 A13 A13 A14 A14
M1 M1
VSS_7 M9 VSS_7 M9
VSS_8 VSS_8 FBx_CMD13 BA1 BA1 A3 A3
P1 P1
FBA_RST# T2 VSS_9 P9 FBA_RST# T2 VSS_9 P9
{23,24,25,27} FBA_RST# RESET VSS_10 RESET VSS_10 FBx_CMD14 A14 A14 A13 A13
T1 T1
1 2 RV142 L8 VSS_11 T9 L8 VSS_11 T9
ZQ VSS_12 ZQ VSS_12 FBx_CMD15 CAS# CAS# CAS# CAS#
243_0402_1%
RANKB@ FBx_CMD16 ODT_H ODT_H

1
J1 B1 J1 B1
L1 NC1 VSSQ_1 B9 L1 NC1 VSSQ_1 B9
NC2 VSSQ_2
RV143
NC2 VSSQ_2 FBx_CMD17 CS1#_H
J9 D1 243_0402_1% J9 D1
L9 NC3 VSSQ_3 D8 L9 NC3 VSSQ_3 D8
NC4 VSSQ_4
RANKB@
NC4 VSSQ_4 FBx_CMD18 CS0#_H
M7 E2 M7 E2

2
NC5 VSSQ_5 E8 NC5 VSSQ_5 E8
VSSQ_6 VSSQ_6 FBx_CMD19 CKE_H CKE_H
F9 F9
VSSQ_7 G1 VSSQ_7 G1
VSSQ_8 VSSQ_8 FBx_CMD20 RST RST RST RST
G9 G9
VSSQ_9 VSSQ_9
FBx_CMD21 A7 A7 A6 A6
96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 FBx_CMD22 A4 A4 A5 A5
K4W4G1646B-HC11_FBGA96 K4W4G1646B-HC11_FBGA96
B B
@ @ FBx_CMD23 A11 A11 A9 A9
FBx_CMD24 A2 A2 A1 A1
FBx_CMD25 A10 A10 WE# WE#
FBx_CMD26 A5 A5 A4 A4
FBx_CMD27 BA2 BA2
FBx_CMD28 WE# WE# A10 A10
FBx_CMD29 BA0 BA0 BA0 BA0
FBx_CMD30 BA2 BA2

+1.35VGS UV4 SIDE +1.35VGS +1.35VGS UV3 SIDE +1.35VGS

For RF For RF
1U_0603_25V6M

1U_0603_25V6M

1U_0603_25V6M

1U_0603_25V6M

1U_0603_25V6M

1U_0603_25V6M

1U_0603_25V6M

1U_0603_25V6M
33P_0402_50V8J

33P_0402_50V8J
0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K
CV166

CV167

CV168

CV169

CV170

CV171

CV176

CV178

CV179

CV180

CV181

CV182

CV183

CV188
1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 2 2 2 2

RANKB@ RANKB@ RANKB@ RANKB@ RANKB@ RANKB@ @ RANKB@ RANKB@ RANKB@ RANKB@ RANKB@ RANKB@ @

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 DDR3 VRAM Rank1_L

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
C 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
ACLU9
Date: Monday, December 23, 2013 Sheet 26 of 59
5 4 3 2 1
 5 4 3 2 1

FBA_D[0..63] {23,24,25,26}

FBA_CMD[30..0] {23,24,25,26}

FBA_DQM[7..0] {23,24,25,26}

FBA_DQS[7..0] {23,24,25,26}
D D
FBA_DQS#[7..0] {23,24,25,26}
UV11 UV12

+FBA_VREFCA1 M8 E3 FBA_D38 +FBA_VREFCA1 M8 E3 FBA_D43

{25} +FBA_VREFCA1 H1 VREFCA DQL0 F7 H1 VREFCA DQL0 F7
at least 16 mils width(optimal) +FBA_VREFDQ1 FBA_D34 +FBA_VREFDQ1 FBA_D44
{25} +FBA_VREFDQ1 VREFDQ DQL1 F2 VREFDQ DQL1 F2
FBA_D39 FBA_D40
20 mils spacing to other signals /planes FBA_CMD9 N3 DQL2 F8 FBA_D35 FBA_CMD9 N3 DQL2 F8 FBA_D45
FBA_CMD24 P7 A0 DQL3 H3 FBA_D37 FBA_CMD24 P7 A0 DQL3 H3 FBA_D41
A1 DQL4 Group4 A1 DQL4 Group5
FBA_CMD10 P3 H8 FBA_D33 FBA_CMD10 P3 H8 FBA_D46
FBA_CMD13 N2 A2 DQL5 G2 FBA_D36 FBA_CMD13 N2 A2 DQL5 G2 FBA_D42
FBA_CMD26 P8 A3 DQL6 H7 FBA_D32 FBA_CMD26 P8 A3 DQL6 H7 FBA_D47
FBA_CMD22 P2 A4 DQL7 FBA_CMD22 P2 A4 DQL7
FBA_CMD21 R8 A5 FBA_CMD21 R8 A5
FBA_CMD5 R2 A6 D7 FBA_D62 FBA_CMD5 R2 A6 D7 FBA_D50
FBA_CMD8 T8 A7 DQU0 C3 FBA_D59 FBA_CMD8 T8 A7 DQU0 C3 FBA_D52
FBA_CMD23 R3 A8 DQU1 C8 FBA_D63 FBA_CMD23 R3 A8 DQU1 C8 FBA_D51
FBA_CMD28 L7 A9 DQU2 C2 FBA_D58 FBA_CMD28 L7 A9 DQU2 C2 FBA_D55
A10/AP DQU3 Group7 A10/AP DQU3
FBA_CMD4 R7 A7 FBA_D61 FBA_CMD4 R7 A7 FBA_D49 Group6
FBA_CMD7 N7 A11 DQU4 A2 FBA_D56 FBA_CMD7 N7 A11 DQU4 A2 FBA_D54
FBA_CMD14 T3 A12/BC
A13
DQU5
DQU6
B8 FBA_D60 FBA_CMD14 T3 A12/BC
A13
DQU5
DQU6
B8 FBA_D48 CMD mapping mod Mode E
FBA_CMD12 T7 A3 FBA_D57 FBA_CMD12 T7 A3 FBA_D53
A14 DQU7 A14 DQU7
Rank0 Rank1
+1.35VGS +1.35VGS
Address 0..31 32..63 0..31 32..63
FBA_CMD29 M2 B2 FBA_CMD29 M2 B2
FBA_CMD6 N8 BA0 VDD_1 D9 FBA_CMD6 N8 BA0 VDD_1 D9
BA1 VDD_2 BA1 VDD_2 FBx_CMD0 ODT_L ODT_L
FBA_CMD30 M3 G7 FBA_CMD30 M3 G7
BA2 VDD_3 K2 BA2 VDD_3 K2
VDD_4 VDD_4 FBx_CMD1 CS1#_L
K8 K8
VDD_5 N1 VDD_5 N1
VDD_6 VDD_6 FBx_CMD2 CS0#_L
FBA_CLK1 J7 N9 FBA_CLK1 J7 N9
{23,25} FBA_CLK1 K7 CK VDD_7 R1 CK VDD_7
FBA_CLK1# FBA_CLK1# K7 R1 FBx_CMD3 CKE_L CKE_L
{23,25} FBA_CLK1# K9 CK VDD_8 R9 CK VDD_8
FBA_CKE_H FBA_CKE_H K9 R9
{23,25} FBA_CKE_H CKE VDD_9 CKE VDD_9
FBx_CMD4 A9 A9 A11 A11
FBA_ODT_H K1 A1 FBA_ODT_H K1 A1 FBx_CMD5 A6 A6 A7 A7
{23,25} FBA_ODT_H L2 ODT VDDQ_1 A8 L2 ODT VDDQ_1 A8
C FBA_CS1#_H FBA_CS1#_H C
{23} FBA_CS1#_H J3 CS VDDQ_2 C1 J3 CS VDDQ_2 C1
FBA_RAS# FBA_RAS# FBx_CMD6 A3 A3 BA1 BA1
{23,24,25,26} FBA_RAS# FBA_CAS# K3 RAS VDDQ_3 C9 FBA_CAS# K3 RAS VDDQ_3 C9
{23,24,25,26} FBA_CAS# L3 CAS VDDQ_4 D2 L3 CAS VDDQ_4 D2
FBA_CMD25 FBA_CMD25 FBx_CMD7 A0 A0 A12 A12
WE VDDQ_5 E9 WE VDDQ_5 E9
VDDQ_6 F1 VDDQ_6 F1
VDDQ_7 VDDQ_7 FBx_CMD8 A8 A8 A8 A8
FBA_DQS4 F3 H2 FBA_DQS5 F3 H2
FBA_DQS7 C7 DQSL VDDQ_8 H9 FBA_DQS6 C7 DQSL VDDQ_8 H9
DQSU VDDQ_9 DQSU VDDQ_9 FBx_CMD9 A12 A12 A0 A0
FBx_CMD10 A1 A1 A2 A2
FBA_DQM4 E7 A9 FBA_DQM5 E7 A9
FBA_DQM7 D3 DML VSS_1 B3 FBA_DQM6 D3 DML VSS_1 B3
DMU VSS_2 DMU VSS_2 FBx_CMD11 RAS# RAS# RAS# RAS#
E1 E1
VSS_3 G8 VSS_3 G8
VSS_4 VSS_4 FBx_CMD12 A13 A13 A14 A14
FBA_DQS#4 G3 J2 FBA_DQS#5 G3 J2
FBA_DQS#7 B7 DQSL VSS_5 J8 FBA_DQS#6 B7 DQSL VSS_5 J8
DQSU VSS_6 DQSU VSS_6 FBx_CMD13 BA1 BA1 A3 A3
M1 M1
VSS_7 M9 VSS_7 M9
VSS_8 VSS_8 FBx_CMD14 A14 A14 A13 A13
P1 P1
FBA_RST# T2 VSS_9 P9 FBA_RST# T2 VSS_9 P9
{23,24,25,26} FBA_RST# RESET VSS_10 RESET VSS_10 FBx_CMD15 CAS# CAS# CAS# CAS#
T1 T1
L8 VSS_11 T9 L8 VSS_11 T9
ZQ VSS_12 ZQ VSS_12 FBx_CMD16 ODT_H ODT_H
FBx_CMD17 CS1#_H

1
J1 B1 J1 B1
NC1 VSSQ_1 NC1 VSSQ_1
1

L1 B9 RV145 L1 B9 FBx_CMD18 CS0#_H

RV144 J9 NC2 VSSQ_2 D1 243_0402_1% J9 NC2 VSSQ_2 D1
L9 NC3 VSSQ_3 D8 L9 NC3 VSSQ_3 D8
243_0402_1%
NC4 VSSQ_4
RANKB@
NC4 VSSQ_4 FBx_CMD19 CKE_H CKE_H
RANKB@ M7 E2 M7 E2

2
NC5 VSSQ_5 E8 NC5 VSSQ_5 E8 FBx_CMD20 RST RST RST RST
2

VSSQ_6 F9 VSSQ_6 F9
VSSQ_7 G1 VSSQ_7 G1
VSSQ_8 VSSQ_8 FBx_CMD21 A7 A7 A6 A6
G9 G9
VSSQ_9 VSSQ_9
FBx_CMD22 A4 A4 A5 A5
96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 FBx_CMD23 A11 A11 A9 A9
K4W4G1646B-HC11_FBGA96 K4W4G1646B-HC11_FBGA96
B @ @ FBx_CMD24 A2 A2 A1 A1 B

FBx_CMD25 A10 A10 WE# WE#

FBx_CMD26 A5 A5 A4 A4
FBx_CMD27 BA2 BA2
FBx_CMD28 WE# WE# A10 A10
FBx_CMD29 BA0 BA0 BA0 BA0
FBx_CMD30 BA2 BA2

+1.35VGS UV6 SIDE +1.35VGS +1.35VGS UV5 SIDE +1.35VGS

For RF For RF
1U_0603_25V6M

1U_0603_25V6M

1U_0603_25V6M

1U_0603_25V6M

1U_0603_25V6M

1U_0603_25V6M

1U_0603_25V6M

1U_0603_25V6M
33P_0402_50V8J

33P_0402_50V8J
0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K
CV190

CV191

CV192

CV193

CV194

CV195

CV200

CV202

CV203

CV204

CV205

CV206

CV207

CV212
1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 2 2 2 2

RANKB@ RANKB@ RANKB@ RANKB@ RANKB@ RANKB@ RANKB@ RANKB@ RANKB@ RANKB@ RANKB@ RANKB@
@ @

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 DDR3 VRAM Rank1_H

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
C 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
ACLU9
Date: Monday, December 23, 2013 Sheet 27 of 59
5 4 3 2 1
 5 4 3 2 1

+3VG_AON Physical Logical Logical Logical Logical

Strapping pin Power Rail Strapping Bit3 Strapping Bit2 Strapping Bit1 Strapping Bit0
D D
ROM_SCLK +3VGS SOR3_EXPOSED SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED
ROM_SI +3VGS RAM_CFG[3] RAM_CFG[2] RAM_CFG[1] RAM_CFG[0]
ROM_SO +3VGS DEVID_SEL PCIE_CFG SMB_ALT_ADDR VGA_DEVICE

2
RV146 RV147 RV148 RV149 RV150 STRAP0 +3VGS Reserved(keep pull-up and pull-down footprint and stuff 50Kohm pull-up)
49.9K_0402_1% 4.99K_0402_1% 24.9K_0402_1% 4.99K_0402_1% 45.3K_0402_1%
N15SGT@ @ @ @ @ STRAP1 +3VGS

1
STRAP2 +3VGS
{20} STRAP0 STRAP0 Reserved(keep pull-up and pull-down footprint and not stuff by default)
STRAP1 STRAP3 +3VGS
{20} STRAP1
{20} STRAP2 STRAP2
STRAP3 STRAP4 +3VGS
{20} STRAP3
STRAP4
{20} STRAP4

DEVID_SEL
2

2
Pull-up to
RV151 RV152 RV153 RV154 RV155 Resistor Values +3VGS Pull-down to Gnd
45.3K_0402_1% 4.99K_0402_1% 15K_0402_1% 4.99K_0402_1% 10K_0402_1% 0 (Default)
@ @ @ @ OPT@ 4.99K 1000 0000
SD03449918J
1

1
10K 1001 0001 1
15K 1010 0010
20K 1011 0011 PCIE_CFG
24.9K 1100 0100
SD03424928J 0 (Default)
30.1K 1101 0101
SD03430128J
34.8K 1110 0110 1
SD03434828J
+3VGS 45.3K 1111 0111
C SD03445328J C

SMBUS_ALT_ADDR
0 0x9E (Default)
2

2 Physical
RV156 RV157 RV158
Strapping pin Power Rail Strap Mapping
4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 1 0x9C (Multi-GPU usage)
@ @ @ ROM_SCLK +3VGS SMB_ALT_ADDR
1

ROM_SI +3VGS SUB_VENDOR

ROM_SO +3VGS VGA_DEVICE VGA_DEVICE
ROM_SI
{20} ROM_SI
{20} ROM_SO ROM_SO STRAP0 +3VGS RAM_CFG[0] 0 3D Device (Class Code 302h)
ROM_SCLK
{20} ROM_SCLK
STRAP1 +3VGS RAM_CFG[1]
1 VGA Device (Default)
2

STRAP2 +3VGS RAM_CFG[2]

RV159 RV160 RV161
X76 10K_0402_1% 10K_0402_1% 10K_0402_1% STRAP3 +3VGS RAM_CFG[3]
OPT@ OPT@ OPT@
STRAP4 +3VGS PCIE_MAX_SPEED
1

X76

GPU FB Memory (DDR3) ROM_SI ROM_SO ROM_SCLK STRAP0 STRAP1 STRAP2 STRAP3 STRAP4
B H5TC4G63AFR-11C 0x3 B
Hynix
900MHz 256M x 16 PD 20K
MT41J256M16HA-093G:E 0x4
Micron
900MHz 256M x 16 PD 24.9K
N15S-GT
K4W4G1646D-BC1A 0x5
Samsung PD 4.99K PD 4.99K PU 49.9K Un-stuff Un-stuff Un-stuff Un-stuff
900MHz 256M x 16 PD 30.1K

GPU FB Memory (DDR3) STRAP3 STRAP2 STRAP1 STRAP0 STRAP4 ROM_SI ROM_SO ROM_SCLK
VRAM X76 VRAM P/N
H5TC4G63AFR-11C
Hynix PD 10K PU 10K PD 10K PD 10K
900MHz 256M x 16 0x4 X7604112001 SA00005SH40
Samsung
MT41J256M16HA-093G:E
Micron PU 10K PU 10K PD 10K PU 10K
900MHz 256M x 16 0xD
N15V-GM
H5TC2G63FFR-11C X7604012002 SA00005M120
Hynix PU 10K PU 10K PD 10K PD 10K PD 10K PD 10K PD 10K PD 10K Micron
900MHz 128M x 16 0xC
A MT41J128M16JT-093G A
Micron PD 10K PD 10K PD 10K PU 10K
900MHz 128M x 16 0x1 Hynix X7604012001 SA00005VS00
K4W2G1646Q-BC1A
Samsung PU 10K PU 10K PU 10K PD 10K
900MHz 128M x 16 0xE

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 N15X_MISC

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
C 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
ACLU9
Date: Monday, December 23, 2013 Sheet 28 of 59
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 Blank
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
ACLU9
Date: Monday, December 23, 2013 Sheet 29 of 59
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 Blank

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
ACLU9
Date: Monday, December 23, 2013 Sheet 30 of 59
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 Blank

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
ACLU9
Date: Monday, December 23, 2013 Sheet 31 of 59
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 Blank

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
ACLU9
Date: Monday, December 23, 2013 Sheet 32 of 59
5 4 3 2 1
 5 4 3 2 1

LCD POWER CIRCUIT CMOS Camera

+LCDVDD +5VALW +3VS
W=60mils +3VS Need short +3VS_CMOS_R
J1 @

1
1 2
1 2

1
R1 1
130_0603_1% R2 C1 JUMP_43X39
100K_0402_5% 4.7U_0603_6.3V6K +3VS_CMOS
@

2
2 LP2301ALT1G_SOT23-3

2
Q9 W=40 mils W=40mils
R4

3
S

D
D Q8B Q7 3 1 R3 1 2

.01U_0402_16V7-K
G
D 5 1 2 2 LP2301ALT1G_SOT23-3 0_0603_5% D

C6
G 220K_0402_1% @ 1 1
2N7002KDWH_SOT363-6 +LCDVDD +LCDVDD_CON C3 C4

G
1
D
1 1

2
S C5 .1U_0402_10V6-K 10U_0603_6.3V6M

4
C2 L1 W=60mils .1U_0402_10V6-K @
.1U_0402_10V6-K 2 1 @ 2 2
2 2 @
@2

C7

C8

C43
0_0805_5%

33P_0402_50V8J
.1U_0402_10V6-K
4.7U_0603_6.3V6K
6
Q8A D 1 1 1 R5 1 @ 2
1 2 0_0402_5% 2 {8} CMOS_ON#
R6 100K_0402_5%
{4} PCH_ENVDD G 1 1
C9 C10

1
S 2N7002KDWH_SOT363-6 2 2 2 0.01U_0402_25V7K .1U_0402_10V6-K
For EMI

@
R7 @ Close to R5 @
100K_0402_5% 2 2
@

2
+3VS
For RF
+3VS
EMI request

2
R8 R9
2

100K_0402_1% 100K_0402_1% DMIC_CLK DISPOFF# INVT_PWM

470P_0402_50V7K
R10

C11

C12

C13
PCH_ENBKL 1 2

470P_0402_50V7K
R11 @ 4.7K_0402_5% @ @

100P_0402_50V8J
1

1
0_0402_5% @ 1 1 1
1

EDP_AUX
R12 1 2 0_0402_5% DISPOFF# B+ +LEDVDD EDP_AUX#
{44} BKOFF# 2 2 2
2A 80 mil 2A 80 mil @ @ @

2
R14 1 2 0_0402_5% ENBKL 2 R17 1
{4} PCH_ENBKL ENBKL {44}

4.7U_0805_25V6-K

470P_0402_50V7K
0_0805_5% C14 C15 R13 R15
1

C C
1 1 100K_0402_1% 100K_0402_1%
R16
100K_0402_5% AO3401A_SOT23-3 @ @

1
2 2

D
Q33 3 1 @
2

EMI Request JEDP1

+LEDVDD
1
2 1
@

G
2
3 2
+3VS R179 1 @ 2 LEDVDD_EN# 4 3
B+ 4
100K_0402_5% CPU_EDP_TX0+ C19 1 2 .1U_0402_10V6-K EDP_TX0+ 5
{4} CPU_EDP_TX0+ 1 2 .1U_0402_10V6-K 6 5
CPU_EDP_TX0- C16 EDP_TX0-
{4} CPU_EDP_TX0- 6
2

1
7
R18 R180 CPU_EDP_TX1+ C17 1 2 .1U_0402_10V6-K EDP_TX1+ 8 7
{4} CPU_EDP_TX1+ 1 2 .1U_0402_10V6-K 9 8
1K_0402_5% 100K_0402_5% CPU_EDP_TX1- C18 EDP_TX1-
{4} CPU_EDP_TX1- 10 9
@ @
CPU_EDP_AUX C20 1 2 .1U_0402_10V6-K EDP_AUX 11 10
1

1 2
{4} CPU_EDP_AUX 1 2 .1U_0402_10V6-K 12 11
CPU_EDP_AUX# C21 EDP_AUX#
1 2 0_0402_5% {4} CPU_EDP_AUX# 13 12
R19 INVT_PWM Q34 D
{4} PCH_EDP_PWM 13
PCH_ENVDD R181 1 @ 2 2 DISPOFF# 14
0_0402_5% G 15 14
15
1

1 INVT_PWM 16
R20 C132 @ S 17 16
3

100K_0402_5% .1U_0402_10V6-K 2N7002KW_SOT323-3 +3VS 18 17

@ 19 18
2 1 2 {4} CPU_EDP_HPD 20 19
R21 @
2

0_0402_5% 21 20
1 +LCDVDD_CON 21
W=60mils 22
C22 23 22
Reserve for power consumption test +3VS 23
680P_0402_50V7K {43} DMIC_DATA
24
@ 2 25 24
{43} DMIC_CLK 25
26 31
27 26 G1 32
R182 1 2 0_0402_5% HUSB20_P1_R 28 27 G2 33
{16} HUB_USB20_P1 28 G3
B R183 1 2 0_0402_5% HUSB20_N1_R 29 34 B
{16} HUB_USB20_N1 30 29 G4 35
+3VS_CMOS 30 G5
2
Touch Screen .1U_0402_10V6-K C24
W=40mils ACES_50406-03071-001
ME@
R22 1 TS@ 2 C23 1 2 TS@ 0.047U_0402_16V7K
{44} EC_TS_ON# 1
100K_0402_5% @
+3VS_TS_R +3VS_TS

LP2301ALT1G_SOT23-3
EMI request
S

3 1
Q11 TS@ JTS1
1 1
C25 R28 2 @ 1 10K_0402_5% TS_RS 2 1
G
2

.1U_0402_10V6-K 3 2
@ R23 1 TS@ 2 0_0402_5% USB20_N4_CONN 4 3
2 {16} HUB_USB20_N4
R24 1 TS@ 2 0_0402_5% USB20_P4_CONN 5 4 7
{16} HUB_USB20_P4 6 5 GND1 8
6 GND2
ACES_87213-00601-P01
+3VS +3VS_TS_R +3VS_TS USB20_P4_CONN ME@
+3VS_TS
R25 1 TS@ 2 0_0402_5% R26 1 @ 2 0_0402_5% USB20_N4_CONN Touch Screen For EMI
3

+3VALW L12 @
HUB_USB20_P1 1 2 HUSB20_P1_R
R27 1 @ 2 0_0402_5% 1 2
1

@
D2 HUB_USB20_N1 4 3 HUSB20_N1_R
1

4 3
For EMI CMM21T-900M-N_4P
L13 @ D1
2

HUB_USB20_P4 1 2 USB20_P4_CONN AZC199-02S.R7G_SOT23-3

A 1 2 @
A
2

AZ5215-01F_DFN1006P2E2
HUB_USB20_N4 4 3 USB20_N4_CONN
1

4 3
CMM21T-900M-N_4P For EMI

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 eDP/ CMOS/Touch screen
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
ACLU9
Date: Monday, December 23, 2013 Sheet 33 of 59
5 4 3 2 1
 5 4 3 2 1

L2 @
HDMI_CLK-_C 1 2 HDMI_CLK-_CON 1 2
1 2 C26 3.3P_0402_50V8-C
@
HDMI_CLK+_C 4 3 HDMI_CLK+_CON 1 2
4 3 C27 3.3P_0402_50V8-C
HDMI2012F2SF-900T04_4P +1.8VS +1.8VS +5VS_HDMI

D L3 @ D
HDMI_TX0-_C 1 2 HDMI_TX0-_CON 1 2
1 2 C28 3.3P_0402_50V8-C RP10
@ RP9 2.2K_0404_4P2R_5%

3
4
HDMI_TX0+_C 4 3 HDMI_TX0+_CON 1 2 2.2K_0404_4P2R_5%
4 3

3
4
C29 3.3P_0402_50V8-C
HDMI2012F2SF-900T04_4P
D3

G2 5
L4 @ HDMI_DET 1 1 10 9 HDMI_DET

2
1
HDMI_TX1-_C 1 2 HDMI_TX1-_CON 1 2

2
1
1 2 2 2
C30 3.3P_0402_50V8-C {4} DDPB_CLK 4 S2 D2 3 HDMICLK_R HDMIDAT_R 9 8 HDMIDAT_R
@
HDMI_TX1+_C 4 3 HDMI_TX1+_CON 1 2 HDMICLK_R 4 4 7 7 HDMICLK_R
4 3 C31 3.3P_0402_50V8-C
Q3401B

2
HDMI2012F2SF-900T04_4P +5VS_HDMI 5 5 6 6 +5VS_HDMI
PJT138K_SOT363-6

G1
L5 @ 3 3
HDMI_TX2-_C 1 2 HDMI_TX2-_CON 1 2 {4} DDPB_DATA 1 S1 D1 6 HDMIDAT_R
1 2 C32 3.3P_0402_50V8-C 8
@
HDMI_TX2+_C 4 3 HDMI_TX2+_CON 1 2
4 3 C33 3.3P_0402_50V8-C Q3401A AZ1045-04F_DFN2510P10E-10-9
HDMI2012F2SF-900T04_4P PJT138K_SOT363-6
@

For EMC
For EMC

+1.8VS
C C
HDMI_CLK-_C R29 1 2 619_0402_1%
R4602 change from 10K to 1K,
HDMI_CLK+_C R30 1 2 619_0402_1% as Vienna +5VS
+5VS +5VS_HDMI_F +5VS_HDMI

2
HDMI_TX0-_C R31 1 2 619_0402_1% D5 @

2
R3405 D4 2 F1
HDMI_TX0+_C R32 1 2 619_0402_1% 1K_0402_1% 1 1 2
3
HDMI_TX1-_C R33 1 2 619_0402_1% @ RB491D_SOT23-3 0.5A_8V_KMC3S050RY

1
HDMI_TX1+_C R34 1 2 619_0402_1% BAT54S-7-F_SOT23-3
{4} HDMI_HPD

1
D4 LP2301ALT1G_SOT23-3
HDMI_TX2-_C R37 1 2 619_0402_1% 1
1 3 Q32 C34

S
1
HDMI_TX2+_C R38 1 2 619_0402_1% D .1U_0402_10V6-K
Q12 2
2N7002KW_SOT323-3 G 2

G
2
1

D Q13

2
+3VS 2 S
{46} SUSP

3
G 2N7002KW_SOT323-3 R41
100K_0402_5%
S JHDMI1
3

HDMI_DET 19

1
R42 1 @ 2 18 HP_DET
17 +5V
100K_0402_5% HDMIDAT_R 16 DDC/CEC_GND
HDMICLK_R 15 SDA
14 SCL
13 Reserved
HDMI_CLK- C35 2 1 .1U_0402_10V6-K HDMI_CLK-_C R43 2 @ 1 0_0402_5% HDMI_CLK-_CON 12 CEC 20
{4} HDMI_CLK- CK- GND1
11 21
B HDMI_CLK+ C36 2 1 .1U_0402_10V6-K HDMI_CLK+_C R44 2 @ 1 0_0402_5% HDMI_CLK+_CON 10 CK_shield GND2 B
{4} HDMI_CLK+ CK+
{4} HDMI_TX0- HDMI_TX0- C37 2 1 .1U_0402_10V6-K HDMI_TX0-_C R45 2 @ 1 0_0402_5% HDMI_TX0-_CON 9 22
8 D0- GND3 23
HDMI_TX0+ C38 2 1 .1U_0402_10V6-K HDMI_TX0+_C R46 2 @ 1 0_0402_5% HDMI_TX0+_CON 7 D0_shield GND4
{4} HDMI_TX0+ D0+
{4} HDMI_TX1- HDMI_TX1- C39 2 1 .1U_0402_10V6-K HDMI_TX1-_C R47 2 @ 1 0_0402_5% HDMI_TX1-_CON 6
5 D1-
HDMI_TX1+ C40 2 1 .1U_0402_10V6-K HDMI_TX1+_C R48 2 @ 1 0_0402_5% HDMI_TX1+_CON 4 D1_shield
{4} HDMI_TX1+ D1+
{4} HDMI_TX2- HDMI_TX2- C41 2 1 .1U_0402_10V6-K HDMI_TX2-_C R49 2 @ 1 0_0402_5% HDMI_TX2-_CON 3
2 D2-
HDMI_TX2+ C42 2 1 .1U_0402_10V6-K HDMI_TX2+_C R50 2 @ 1 0_0402_5% HDMI_TX2+_CON 1 D2_shield
{4} HDMI_TX2+ D2+
FOX_QJ111A1-RC0AH1-8H
ME@

Close to JHDMI1
D6 D7
HDMI_CLK+_CON 1 1 10 9 HDMI_CLK+_CON HDMI_TX1-_CON 1 1 10 9 HDMI_TX1-_CON

HDMI_CLK-_CON 2 2 9 8 HDMI_CLK-_CON HDMI_TX1+_CON 2 2 9 8 HDMI_TX1+_CON

HDMI_TX0+_CON 4 4 7 7 HDMI_TX0+_CON HDMI_TX2-_CON 4 4 7 7 HDMI_TX2-_CON

HDMI_TX0-_CON 5 5 6 6 HDMI_TX0-_CON HDMI_TX2+_CON 5 5 6 6 HDMI_TX2+_CON

A A
3 3 3 3

8 8

AZ1045-04F_DFN2510P10E-10-9 For EMC AZ1045-04F_DFN2510P10E-10-9

@ @ Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 HDMI_CONN

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
ACLU9
Date: Monday, December 23, 2013 Sheet 34 of 59
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 DP to CRT Converter(PS8613)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
ACLU9
Date: Monday, December 23, 2013 Sheet 35 of 59
5 4 3 2 1
 5 4 3 2 1

+3VS

+CRT_VCC_CON
CRT Connector

3
4
2
RPC10 +CRT_VCC_CON +5VS_HDMI

G
2.2K_0404_4P2R_5% +5VS RVG39 @
+CRT_VCC 1 2

2
1
VGA_DDC_CLK 1 6 CRT_DDC_CLK DVG1 0_0603_5%

S
{4} VGA_DDC_CLK

D
2 @ FVG1
Q31A 1 1 2 @ +CRT_VCC_CON

5
2N7002KDWH_SOT363-6 3

G
1
D RB491D_SOT23-3 0.5A_8V_KMC3S050RY D

1
CVG34
.1U_0402_10V6-K DVG2
W=40mils

1
VGA_DDC_DAT 4 3 CRT_DDC_DAT 2 @ AZ5425-01F_DFN1006P2E2

S
{4} VGA_DDC_DAT

D
2N7002KDWH_SOT363-6 Q31B @
1 1

2
@ C50 C485 @

2
100P_0402_50V8J 68P_0402_50V8J JCRT1
2 2 6
@ PAD TVG3 1 CRT_DET# 11
LVG6 1 2 LVG11 1 2 0_0603_5% CRT_R_CON 1
{4} CRT_R
BLM18BB470SN1D_2P~D 7 For EMC
CRT_DDC_DAT 12
LVG7 1 2 LVG12 1 2 0_0603_5% CRT_G_CON 2
{4} CRT_G
BLM18BB470SN1D_2P~D 8
HSYNC_CON 13
LVG8 1 2 LVG13 1 2 0_0603_5% CRT_B_CON 3
{4} CRT_B
BLM18BB470SN1D_2P~D 9

10P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J

22P_0402_50V8-J

22P_0402_50V8-J

22P_0402_50V8-J

10P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J
VSYNC_CON 14
2

1 1 1 1 1 1 4

1
CVG51

CVG52

CVG53
RVG25 RVG26 RVG27 10 G 16

CVG35

CVG36

CVG37

CVG38

CVG39

CVG40
150_0402_1% 150_0402_1% 150_0402_1% CRT_DDC_CLK 15 G 17
5

2
2 2 2 2 2 2
1
1

CVG41 SUYIN_070546HR015M25KZR
100P_0402_50V8J ME@
@ @ @ @
2
CLOSE TO CONN
C C

RVG21 1 2 0_0402_5% +3VS

+5VS

1
CVG49 RVG37 RVG40
1 2 @ 1 @ 2 1K_0402_1%
1K_0402_5% @
.1U_0402_10V6-K

2
5

1
P

OE#

VGA_HS 2 4 CRT_HSYNC RVG32 1 2 15_0402_5% CRT_HSYNC_R LVG9 1 2 0_0402_5% HSYNC_CON

{4} VGA_HS A Y
G

UVG3
74AHCT1G125GW_SOT353-5 1
3

@
LVG9/LVG10 SM01000LO00 Change to 0 ohm CVG42
@ 150P_0402_50V8-J
2

RVG22 1 2 0_0402_5% +3VS

B B
+5VS
1

CVG50 RVG38 RVG41

1 2 @ 1 @ 2 1K_0402_1%
1K_0402_5% @
.1U_0402_10V6-K
2
5

1
P

OE#

VGA_VS 2 4 CRT_VSYNC RVG33 1 2 15_0402_5% CRT_VSYNC_R LVG10 1 2 0_0402_5% VSYNC_CON

{4} VGA_VS A Y
G

UVG4 1
74AHCT1G125GW_SOT353-5
3

@ CVG45
@ 150P_0402_50V8-J
2

DVG3 DVG4
CRT_B_CON 1 1 10 9 CRT_B_CON VSYNC_CON 1 1 10 9 VSYNC_CON

CRT_G_CON 2 2 9 8 CRT_G_CON HSYNC_CON 2 2 9 8 HSYNC_CON

CRT_R_CON 4 4 7 7 CRT_R_CON CRT_DDC_CLK 4 4 7 7 CRT_DDC_CLK

CRT_DET# 5 5 6 6 CRT_DET# CRT_DDC_DAT 5 5 6 6 CRT_DDC_DAT

3 3 3 3
A A
8 8

AZ1045-04F_DFN2510P10E-10-9 AZ1045-04F_DFN2510P10E-10-9
@ @
For EMC
Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 CRT

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
ACLU9
Date: Monday, December 23, 2013 Sheet 36 of 59
5 4 3 2 1
 5 4 3 2 1

+3VALW TO +3VALW_LAN
+3VALW_LAN rising time (10%~90%):
+3VALW +3VALW_LAN 0.5ms
spec
100ms +3VALW_LAN +LAN_VDDREG
Need short
JL1 1 2 @ width : 40 mils 1
RL1
2
@
1 2
JUMP_43X79 0_0603_5%
D D
1 1
+3VALW LP2301ALT1G_SOT23-3 CL1 CL2

.1U_0402_10V6-K

.1U_0402_10V6-K
4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
1 1 1 1 4.7U_0603_6.3V6K .1U_0402_10V6-K

D
Q14 3 1 @ CL4 CL5 CL6 CL7

.1U_0402_10V6-K

.01U_0402_16V7-K
1
2 2
RL2 1 1
100K_0402_5% CL8 CL9 @ 2 @ 2 2 2

G
2
@
2

2 2
RL3 1 @ 2 @ @
{44} LAN_PWR_ON#
47K_0402_5%
Close to Pin11 Close to Pin32 Close to Pin11 Close to Pin32
+3VALW_LAN +3VS

+3VALW_LAN

2
RL4

G
2
10K_0402_5% QL1
RL5 @
10K_0402_5% UL1

1
@ LAN_CLKREQ#_R 1 3 @
LAN_CLKREQ# {6}

S
1

2N7002KW_SOT323-3
RL7 1 @ 2 0_0402_5% PCIE_WAKE#_R
{7,40,44} PCIE_WAKE#
{40,44} LAN_WAKE# RL6 1 2 0_0402_5%
33 2 1
C +3VALW_LAN 32 GND 16 CLK_PCIE_LAN# 0_0402_5% RL18 C
AVDD33_2 REFCLK_N CLK_PCIE_LAN# {7}
RL8 1 2 RSET 31 15 CLK_PCIE_LAN
30 RSET REFCLK_P 14 CLK_PCIE_LAN {7}
2.49K_0402_1% +LAN_VDD10 PCIE_PTX_C_DRX_N3
AVDD10 HSIN PCIE_PTX_C_DRX_N3 {6}
LAN_XTALO 29 13 PCIE_PTX_C_DRX_P3
CKXTAL2 HSIP PCIE_PTX_C_DRX_P3 {6}
LAN_XTALI 28 12 LAN_CLKREQ#_R
+3VS TL3 @ 1 27 CKXTAL1 CLKREQB 11 +3VALW_LAN
LAN_PWR_ON# RL121 @ 2 LAN_DISABLE# 26 LED0 AVDD33_1 10 LAN_MDI3-
LED1/GPIO MDIN3 LAN_MDI3- {38}
0_0402_5% TL4 @ 1 25 9 LAN_MDI3+
LED2 MDIP3 LAN_MDI3+ {38}
1

+LAN_REGOUT 24 8 +LAN_VDD10
RL9 +LAN_VDDREG 23 REGOUT AVDD10_2 7 LAN_MDI2-
VDDREG MDIN2 LAN_MDI2- {38}
1K_0402_1% +LAN_VDD10 22 6 LAN_MDI2+
DVDD10 MDIP2 LAN_MDI2+ {38}
PCIE_WAKE#_R 21 5 LAN_MDI1-
20 LANWAKEB MDIN1 4 LAN_MDI1- {38}
ISOLATE# LAN_MDI1+
2

ISOLATEB MDIP1 LAN_MDI1+ {38}

PLT_RST# 19 3 +LAN_VDD10
{7,19,40,44} PLT_RST# PERSTB AVDD10_1
{6} PCIE_PRX_DTX_N3 CL10 1 2 .1U_0402_10V6-K PCIE_PRX_C_DTX_N3 18 2 LAN_MDI0-
HSON MDIN0 LAN_MDI0- {38}
ISOLATE# RL10 1 @ 2 LAN_PWR_ON# {6} PCIE_PRX_DTX_P3 CL11 1 2 .1U_0402_10V6-K PCIE_PRX_C_DTX_P3 17 1 LAN_MDI0+
HSOP MDIP0 LAN_MDI0+ {38}
0_0402_5% CL10 close to Pin18
1

RL11 CL11 close to Pin17

15K_0402_5%
@
2

RTL8111GUL-CG_QFN32_4X4
GIGA@

B B

LAN_XTALI For RTL8111GUL/ RTL8106EUL (SWR mode)

+LAN_VDD10
YL1 LAN_XTALO

1 4
OSC1 GND2 +LAN_REGOUT LL1 1 2
2 3 2.2UH_NLC252018T-2R2J-N_5%
GND1 OSC2
1 1 1 1 1 1 1 1
1 1
CL12 CL13 CL15 CL16 CL17 CL18 CL19 CL20 CL21 CL22
10P_0402_50V8J 25MHZ_10PF_7V25000014 10P_0402_50V8J 4.7U_0603_6.3V6K .1U_0402_10V6-K .1U_0402_10V6-K .1U_0402_10V6-K .1U_0402_10V6-K .1U_0402_10V6-K 1U_0402_6.3V6K .1U_0402_10V6-K
2 2 2 2 2 2 2 @ 2 @
2 2 @

Close to Pin3, 8, 22, 30 Close to Pin22(Reserved)

Layout Note: LL1 must be
within 200mil to Pin24,
CL15,CL16 must be within
200mil to LL1
+LAN_REGOUT: Width =60mil
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 LAN_RTL8111GUL/RTL8106EUL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
ACLU9
Date: Monday, December 23, 2013 Sheet 37 of 59
5 4 3 2 1

 5 4 3 2 1

DL1/DL2
1'S PN:SC300003M00
TL1 GIGA@
24 1 MCT
D MCT1 TCT1 D
LAN_MDI0- 23 2 LAN_MDO0-
{37} LAN_MDI0- MX1+ TD1+
DL1
LAN_MDI2+ 9 3 LAN_MDI3+ LAN_MDI0+ 22 3 LAN_MDO0+
I/O4 I/O2 {37} LAN_MDI0+ MX1- TD1-

1
2
NC1 10 21 4 MCT RL17
4 NC5 MCT2 TCT2 20_0603_5%
NC2

1
+3VALW_LAN 5 11 LAN_MDI1- 20 5 LAN_MDO1-
VDD GND {37} LAN_MDI1- MX2+ TD2+ DL3

1
2
6 8 LAN_MDI1+ 19 6 LAN_MDO1+ BS4200N-C-LV_SMB-F2
NC3 NC4 {37} LAN_MDI1+ MX2- TD2-

2
LAN_MDI2- 7 1 LAN_MDI3- 18 7 MCT
I/O3 I/O1 MCT3 TCT3

2
AZ3033-04F_DFN2525P10E10 LAN_MDI2+ 17 8 LAN_MDO2+
{37} LAN_MDI2+ MX3+ TD3+
GIGA@
LAN_MDI2- 16 9 LAN_MDO2-
{37} LAN_MDI2- MX3- TD3-
Place Close to TL1
15 10 MCT
MCT4 TCT4
1 1
LAN_MDI3+ 14 11 LAN_MDO3+
{37} LAN_MDI3+ MX4+ TD4+
DL2 CL32 CL25

68P_0402_50V8J
LAN_MDI1+ 9 3 LAN_MDI0+ 1 LAN_MDI3- 13 12 LAN_MDO3- 0.022U_0603_50V7K 1000P_1206_2KV7-K
I/O4 I/O2 {37} LAN_MDI3- MX4- TD4- 2 2

CL24
2 @
NC1 10
C NC5 C
4 BOTHHAND GST5009 LF LAN
5 NC2 11 2
+3VALW_LAN VDD GND
6 8
NC3 NC4
LAN_MDI1- 7 1 LAN_MDI0-
I/O3 I/O1 CHASSIS1_GND
AZ3033-04F_DFN2525P10E10

Place Close to TL2

JRJ1 ME@
12
GND_4
11
GND_3
10
LAN_MDO0+ 1 GND_2
PR1+ 9
B B
LAN_MDO0- 2 GND_1
PR1-
LAN_MDO1+ 3
CL27 1 2 0_0603_5% PR2+ CHASSIS1_GND
LAN_MDO2+ 4
CL28 1 2 0_0603_5% PR3+
LAN_MDO2- 5
CL29 1 2 0_0603_5% PR3-
LAN_MDO1- 6
PR2-
LAN_MDO3+ 7
PR4+
CHASSIS1_GND LAN_MDO3- 8
Reserve for EMI go rural solution PR4-

SANTA_130460-3

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 LAN_Transformer

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
ACLU9
Date: Monday, December 23, 2013 Sheet 38 of 59
5 4 3 2 1
 5 4 3 2 1

D D

Close to U3901
SMSC thermal sensor REMOTE1+
Near GPU&VRAM
REMOTE+_R 1

1
C44
1 placed near DIMM C45
100P_0402_50V8J 2
C
Q15
2200P_0402_50V7K @ B MMBT3904W H_SOT323-3
+3VS 2 E @

3
2 REMOTE-_R U3901 REMOTE1-
1 8 EC_SMB_CK2
VDD SCL EC_SMB_CK2 {19,44}

1 REMOTE+_R 2 7 EC_SMB_DA2
D+ SDA EC_SMB_DA2 {19,44}
C47 REMOTE-_R 3 6
.1U_0402_10V6-K D- ALERT#
@ 2 R51 2 @ 1 4 5 REMOTE2+
Near CPU core
+3VS T_CRIT# GND
10K_0402_5% 1

1
NCT7718W _MSOP8 C46 C
100P_0402_50V8J 2 Q16
@ B MMBT3904W H_SOT323-3
2 E
Address 1001_100xb

3
REMOTE2-

REMOTE1+ R175 1 @ 2 0_0402_5%

REMOTE2+ R176 1 2 0_0402_5% REMOTE+_R Baytrail SOC use thermal sensor to read the thermal,
C REMOTE2- R177 1 2 0_0402_5% REMOTE-_R Baytrail don't has PECI signal C

REMOTE1- R178 1 @ 2 0_0402_5%

REMOTE+/-_R, REMOTE1+/-, REMOTE2+/-:

Trace width/space:10/10 mil
Trace length:<8"

FAN Conn
B B

+5VS
JFAN1
R52 1 2 +5VS_FAN 1
0_0603_5% 2 1
{44} EC_FAN_SPEED 2
1 1 {44} EC_FAN_PW M 3
C3901 4 3
C49 .1U_0402_10V6-K 5 4
10U_0805_10V6K @ 6 GND1
2 2 GND2
@
ACES_85205-04001
ME@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 Thermal sensor/FAN CONN

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
ACLU9
Date: Monday, December 23, 2013 Sheet 39 of 59

5 4 3 2 1
 A B C D E

Mini-Express Card(WLAN/WiMAX) +3VS_WLAN

+3VS Need short +3VS_WLAN JWLAN1

J2 @ 1 2
1 2 3 GND1 3.3VAUX1 4
1 2 {16} HUB_USB20_P3 5 USB_D+ 3.3VAUX2 6 1 @ T2
{16} HUB_USB20_N3 7 USB_D- LED#1
JUMP_43X79 8
GND2 NC
9 NC NC 10
+3VALW 11 NC NC 12
LP2301ALT1G_SOT23-3 13 14
NC NC 16 1
15 @ T3
3 1 AOAC@ 17 NC LED#2 18

D
Q17
1
19 MLDIR_SENSE GND16 1

.01U_0402_16V7-K
20
1 1 1 21 DP_ML3N DP_AUXN 22
C51 C52 C53 23 DP_ML3P DP_AUXP 24

G
2
.1U_0402_10V6-K @ .1U_0402_10V6-K 25 GND3 GND13 26
@ AOAC@ 27 DP_ML2N DP_ML1N 28
2 2 2 29 DP_ML2P DP_ML1P 30
R54 1 AOAC@ 2 31 GND4 GND14 32
{44} AOAC_ON# 33 DP_HPD DP_ML0N 34
1
100K_0402_5% C54 35 GND5 DP_ML0P 36
.1U_0402_10V6-K {6} PCIE_PTX_C_DRX_P4 37 PETP0 GND15 38 EC_TX_RSVD 1 2 0_0402_5% EC_TX_R
R62 @
{6} PCIE_PTX_C_DRX_N4 39 PETN0 RESERVED1 40 1 2 0_0402_5%
AOAC@ EC_RX_RSVD R63 @ BT_OFF#
2 41 GND6 RESERVED2 42
{6} PCIE_PRX_DTX_P4 43 PERP0 RESERVED3 44
{6} PCIE_PRX_DTX_N4 45 PERN0
47 GND7
COEX3
COEX2
46
48
Bay trail plaform susclk is 1.8V level, NGFF card need check whether OK
{7} CLK_PCIE_WLAN 49 REFCLKP0 COEX1 50 1 2 0_0402_5%
SUSCLK_R R55
{7} CLK_PCIE_WLAN# 51 REFCLKN0 SUSCLK 52 SUSCLK {7}
PLT_RST#
53 GND8 PERST0# 54 1 2 1K_0402_1% PLT_RST# {7,19,37,44}
WLAN_CLKREQ_Q# BT_OFF# R53
55 CLKREQ0# RESERVED/W_DISABLE#2 56 1 2 0_0402_5% PCH_BT_OFF# {8}
WLAN_OFF# R56
{7,37,44} PCIE_WAKE# 57 PEWAKE0# W_DISABLE#1 58 SMB_DATA_S3_R 1 2 0_0402_5% PCH_WLAN_OFF# {8}
R58 @
1 2 0_0402_5% 59 GND9 I2C_DATA 60 1 2 0_0402_5% SMB_DATA_S3 {8,14}
R57 @ SMB_CLK_S3_R R59 @
{37,44} LAN_WAKE# 61 PETP1 I2C_CLK 62 1 SMB_CLK_S3 {8,14}
@ T4
63 PETN1 I2C_ALERT# 64 EC_TX_R
65 GND10 RESERVED4 66
67 PERP1 PERST1# 68 +3VS_WLAN
69 PERN1 CLKREQ1# 70
71 GND11 PEWAKE1# 72
73 REFCLKP1 3.3VAUX4 74
+3VS 75 REFCLKN1 3.3VAUX5
+3VS_WLAN GND12
76 77 EC_TX_R R184 1 2 100_0402_1%
PEG1 PEG2 EC_TX {44}
2

JAE_SM3ZS067U410BAR1000 BT_OFF# R185 1 2 100_0402_1%

EC_RX {44}
2

R60 ME@
G

Q18 10K_0402_5%

1
AOAC@
R186
1

2
{6} WLAN_CLKREQ# AOAC@ 3 1 WLAN_CLKREQ_Q# 100K_0402_5% 2
S

2N7002KW_SOT323-3

2
R61 1 2 0_0402_5%

If support AOAC, NC R61;

if not support AOAC, stuff R61.

3 3

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 NGFF WLAN

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
ACLU9
Date: Monday, December 23, 2013 Sheet 40 of 59
A B C D E
 A B C D E

+USB_VCCA

LEFT SIDE USB3.0 PORT X2 C55 1 2

+
220U_6.3V_M
U2 +USB_VCCA C56 1 2
+5VALW @ 1U_0603_25V6M
1 8
GND VOUT3 C57 1 2
1 2 7 @ 470P_0402_50V7K 1
2.2U_0603_6.3V6K VIN1 VOUT2
C58 1 2 3 6
VIN2 VOUT1 JUSB1 ME@
{44,45} USB_ON# USB_ON# 4 5 USB_OC0# 1
EN/EN FLAG USB_OC0# {8} USB20_N2 R65 1 @ 2 0_0402_5% USB20_N2_R 2 VBUS
{8} USB20_N2 D-
1 USB20_P2 R64 1 @ 2 0_0402_5% USB20_P2_R 3
{8} USB20_P2 D+
AP2820CMMTR-G1_MSOP8 C61 4 5
1000P_0402_50V7K GND GND1 6
@ GND2 7
Low Active 2A 2 GND3 8
GND4
C-K_20267-5K11-02

USB20_P2_R
+USB_VCCA
USB20_N2_R

AZ5425-01F_DFN1006P2E2

AZ5425-01F_DFN1006P2E2

AZ5425-01F_DFN1006P2E2
1

1
D9 D10 D11

1
2 2

2
@ @ @

2
USB20_P1_R
L8 D12 @
USB20_P2 1 2 USB20_P2_R USB30_RX_R_N1 9 10 1 1USB30_RX_R_N1 USB20_N1_R
1 2

AZ5425-01F_DFN1006P2E2

AZ5425-01F_DFN1006P2E2
USB30_RX_R_P1 8 9 2 2 USB30_RX_R_P1

1
USB20_N2 4 3 USB20_N2_R D13 D14
4 3 USB30_TX_R_N1 7 7 4 4 USB30_TX_R_N1

1
CMM21T-900M-N_4P
USB30_TX_R_P1 6 6 5 5 USB30_TX_R_P1

3 3

2
8 @ @

2
AZ1045-04F_DFN2510P10E-10-9

3 3
L9 For EMC
USB30_RX_N1 3 4 USB30_RX_R_N1
3 4

USB30_RX_P1 2 1 USB30_RX_R_P1
2 1 +USB_VCCA
DLW 21SN900HQ2L_4P
C62 1 2
@ 1U_0603_25V6M
L10
USB30_TX_C_N1 3 4 USB30_TX_R_N1 C63 1 2
3 4 @ 470P_0402_50V7K

USB30_TX_C_P1 2 1 USB30_TX_R_P1
2 1 JUSB2 ME@
DLW 21SN900HQ2L_4P USB30_TX_P1 C64 1 2 .1U_0402_10V6-K USB30_TX_C_P1 R68 1 @ 2 0_0402_5% USB30_TX_R_P1 9
{8} USB30_TX_P1 StdA_SSTX+
1
L11 USB30_TX_N1 C65 1 2 .1U_0402_10V6-K USB30_TX_C_N1 R69 1 @ 2 0_0402_5% USB30_TX_R_N1 8 VBUS
{8} USB30_TX_N1 StdA_SSTX-
USB20_N1 1 2 USB20_N1_R USB20_P1 R70 1 @ 2 0_0402_5% USB20_P1_R 3
1 2 {8} USB20_P1 D+
7
USB20_N1 R71 1 @ 2 0_0402_5% USB20_N1_R 2 GND_DRAIN 10
{8} USB20_N1 D- GND_1
USB20_P1 4 3 USB20_P1_R USB30_RX_P1 R72 1 @ 2 0_0402_5% USB30_RX_R_P1 6 11
4 3 {8} USB30_RX_P1 StdA_SSRX+ GND_2
4 12
CMM21T-900M-N_4P USB30_RX_N1 R73 1 @ 2 0_0402_5% USB30_RX_R_N1 5 GND_5 GND_3 13
{8} USB30_RX_N1 StdA_SSRX- GND_4
SUYIN_020053GR009M2736L
4 4
For EMC

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 USB2.0/USB3.0 PORT (LEFT)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
ACLU9
Date: Monday, December 23, 2013 Sheet 41 of 59

A B C D E
 A B C D E F G H

SATA HDD Conn.

FOR 14"
SATA ODD Conn.
JHDD1 ME@

1
SATA_PTX_DRX_P0 C66 1 2 .01U_0402_16V7-K SATA_PTX_C_DRX_P0 2 GND_1
{6} SATA_PTX_DRX_P0 A+
SATA_PTX_DRX_N0 C67 1 2 .01U_0402_16V7-K SATA_PTX_C_DRX_N0 3
{6} SATA_PTX_DRX_N0 A-
4
1 SATA_PRX_DTX_N0 C68 1 2 .01U_0402_16V7-K SATA_PRX_C_DTX_N0 5 GND_2 1
{6} SATA_PRX_DTX_N0 SATA_PRX_DTX_P0 C69 1 2 .01U_0402_16V7-K SATA_PRX_C_DTX_P0 6 B- JODD1
{6} SATA_PRX_DTX_P0 7 B+ 1
GND_3 SATA_PTX_DRX_P1 14@ C70 1 2 .01U_0402_16V7-K SATA_PTX_C_DRX_P1_14 2 GND_1
{6} SATA_PTX_DRX_P1 RX+
SATA_PTX_DRX_N1 14@ C71 1 2 .01U_0402_16V7-K SATA_PTX_C_DRX_N1_14 3
{6} SATA_PTX_DRX_N1 RX-
8 4
9 V33_1 SATA_PRX_DTX_N1 14@ C72 1 2 .01U_0402_16V7-K SATA_PRX_C_DTX_N1_14 5 GND_2
10 V33_2 {6} SATA_PRX_DTX_N1 SATA_PRX_DTX_P1 14@ C73 1 2 .01U_0402_16V7-K SATA_PRX_C_DTX_P1_14 6 TX-
+5VS +5VS_HDD V33_3 {6} SATA_PRX_DTX_P1 TX+
Need short 11
12 GND_4
7
GND_3
J3 @ 13 GND_5 ODD_DETECT#_R 8
1 2 14 GND_6 9 DP
1 2 15 V5_1 +5V_ODD 10 +5V_1
JUMP_43X79 16 V5_2 ODD_DA#_R 11 +5V_2 14
17 V5_3 12 MD GND1 15
18 GND_7 13 GND_4 GND2
19 DAS/DSS GND_5
+5VS_HDD 20 GND_8 SUYIN_127382FB013S255ZL
21 V12_1 ME@
22 V12_2
V12_3
1 1 1 1 1
C74 C75 C77 C78 SUYIN_127043HR022M32QZR
1000P_0402_50V7K .1U_0402_10V6-K C76 10U_0805_10V6K 10U_0805_10V6K
1U_0402_6.3V6K @
2 2 2 2 2
@ @
FOR 15"
2 2

For EMC SATA ODD FFC Conn

JODD2
SATA_PTX_DRX_P1 15@ C79 1 2 .01U_0402_16V7-K SATA_PTX_C_DRX_P1_15 1
SATA_PTX_DRX_N1 15@ C80 1 2 .01U_0402_16V7-K SATA_PTX_C_DRX_N1_15 2 1
3 2
SATA_PRX_DTX_N1 15@ C81 1 2 .01U_0402_16V7-K SATA_PRX_C_DTX_N1_15 4 3
SATA_PRX_DTX_P1 15@ C82 1 2 .01U_0402_16V7-K SATA_PRX_C_DTX_P1_15 5 4
6 5
R74 1 2 0_0402_5% ODD_DETECT#_R 7 6
{6} ODD_DETECT# 8 7
+5V_ODD 9 8
9

2
ODD_DA#_R 10
10
Need Short R92
0_0402_5% 11
@ 12 GND_1
J4 GND_2

1
1 2 ACES_51524-01001-003
1 2 ME@
JUMP_43X79

+5VALW +5VS +5V_ODD

3
LP2301ALT1G_SOT23-3 3
S

3 1 Q19
.1U_0402_10V6-K

.01U_0402_16V7-K
1

+3VS
C83

C84

10U_0805_10V6K

.1U_0402_10V6-K
1 1
R75 R76
G

1 1
2

10K_0402_5% 10K_0402_5%
@
@

1
@2 @2
2

1
2 2
C86

R77
@
C85

ODD_EN# 1 2 R78 @ R79 10K_0402_5%

100K_0402_5% 1 470_0603_5% @
C87 @

2
.01U_0402_16V7-K
2

R80 1 @ 2 0_0402_5% ODD_DA#_R

2 {6} ODD_DA#
1 @ 1 2 0_0402_5%
R86 @
D Q20 1 {44} ODD_DA_EC#
2 PJA138K_SOT23-3 D Q21
{8} ODD_EN
G ODD_EN# 2 PJA138K_SOT23-3
S G
2

S @
R81 3
@ 3
100K_0402_5%
1

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 HDD/ODD CONN

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
ACLU9
Date: Monday, December 23, 2013 Sheet 42 of 59
A B C D E F G H
 5 4 3 2 1

<BOM Structure>
+1.5VS +3VS
+3VS
RA8 1 2 0_0402_5% RA3 1 @ 2 0_0603_5% RA1 1 2 0_0402_5%
RA2 1 2 0_0603_5% +3.3VD +3VS +3VALW

RA11 1 2 0_0402_5% DVDD_IO RA5 1 @ 2 0_0603_5% AVDD_HP RA4 1 2 0_0402_5%

+3VL

.1U_0402_10V6-K
@
+5VS RA6 1 @ 2 0_0402_5%
2
CA1 RA43 1 2 0_0603_5%
RA7 1 2 0_0603_5% +5VA
RA9 1 @ 2 0_0402_5%
D 1 D
RA10 1 2 0_0603_5% +5VD
Same as Vienna RA12 1 @ 2 0_0402_5%

Close to Pin7
+3VS RA13 1 @ 2 0_0402_5%

2
RA14 GND GNDA
10K_0402_5%

0606 Close to Pin3

1
CA2
{44} BEEP# 2 RA288 1 1 2 PC_BEEP
10K_0402_5% .1U_0402_10V6-K

4.7U_0603_6.3V6K
1

.1U_0402_10V6-K
C CA16 close to Pin18
{8} PCH_BEEP 2 RA289 1 2 QA1 2 1 CA17 close to Pin2
4.7K_0402_5% B MMBT3904WH_SOT323-3 Close to Pin27
E
3

CA4
1 2

.1U_0402_10V6-K

1U_0402_6.3V6K
CA3
0608

CA7

CA8
2 1

.1U_0402_10V6-K

2.2U_0603_6.3V6K
UA1
2 1

CA5

CA6
HDA_RST_AUDIO# 9 3 FILT_1.8V
+3.3VD

{6} HDA_RST_AUDIO# RESET# FILT_1.8V 7 DVDD_IO 1 2

VDD_IO 2 CD@
HDA_BITCLK_AUDIO 5 VDDO_3.3 18 +3.3VD 1 2
{6} HDA_BITCLK_AUDIO BIT_CLK DVDD_3.3
2

C HDA_SYNC_AUDIO 8 27 AVDD_3.3 C
RA15 {6} HDA_SYNC_AUDIO RA16 SYNC AVDD_3.3 29 VREF_1.65V
5.11K_0402_1% 33_0402_5% 1 2 SDATA_IN 6 VREF_1.65V 28 +5VA
{6} HDA_SDIN0 SDATA_IN AVDD_5V

.1U_0402_10V6-K

1U_0402_6.3V6K
HDA_SDOUT_AUDIO 4 MICBIASB
{6} HDA_SDOUT_AUDIO SDATA_OUT

CA10
CA9
CX20751-11Z 2 1
1

PC_BEEP 10 12 SPK_L+
RA17 1 2 JSENSE SPKR_MUTE# 39 PC_BEEP LEFT+ 14 SPK_L- DA2
{45} PLUG_IN SPKR_MUTE# LEFT-
39.2K_0402_1% BAT54AWT1G_SOT323-3

1
JSENSE 38 17 SPK_R+ 1 2
JSENSE RIGHT+

1
RA36 1 2 37 15 SPK_R- +5VA AVDD_HP

1LINE_B_R

1LINE_B_L
GPIO1/PORTC_R_MIC RIGHT-

.1U_0402_10V6-K

.1U_0402_10V6-K
20K_0402_1% RA42 RA41

CA11

CA12
36 35 0_0402_5% 0_0402_5% 2 2
33_0402_5% 1 RA18 2 DMIC_CLK_R 40 MUSIC_REQ/GPIO0/PORTC_L_MIC MICBIASC 34 MICBIASB @ @
{33} DMIC_CLK DMIC_CLK/MUSIC_REQ/GPIO0 MICBIASB
Close to Pin29
0_0402_5% 1 RA19 2 DMIC_DATA_R 1
{33} DMIC_DATA

2
DMIC_DAT/GPIO1 33 LINE_B_R
.1U_0402_10V6-K PORTB_R_LINE 32 LINE_B_L RA39 RA40 1 1
+5VD 1 2 11 PORTB_L_LINE 100_0402_1% 100_0402_1%
CA13 CLASS-D_REF 30 PORTD_A_MIC
PORTD_A_MIC

3K_0402_1%

3K_0402_1%
13 31 PORTD_B_MIC

2
LPWR_5.0 PORTD_B_MIC

1
+5VD DMIC_DATA_R 16
RPWR_5.0
100P_0402_50V8J

100P_0402_50V8J

RA37

RA38
4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

25 RING2_CONN 1 1 Close to Pin28 Close to Pin24

DMIC_CLK_R CA14 1 2 1U_0402_6.3V6K 19 HGNDA 26 RING3_CONN CA35 CA36
FLY_P HGNDB
.1U_0402_10V6-K

.1U_0402_10V6-K
CA18

CA19

20 4.7U_0603_6.3V6K 4.7U_0603_6.3V6K
FLY_N 24 AVDD_HP
1 1 2 2

2
CA17 1 2 2.2U_0603_6.3V6K 21 AVDD_HP 2 2
AVEE 23 HPOUT_R RA20 1 2 82.5_0402_1%
1 1 PORTA_R HP_OUTR {45}
CA15

CA16

41 22 HPOUT_L RA21 1 2 82.5_0402_1%

2 2 1 1 GND PORTA_L HP_OUTL {45}
CA51 CA52
2 2 Reserve DA2 to prevent RA22
@ @ CX20752-21Z_QFN40_5X5 cross-talk between PORTD_A_MIC 1 2 100_0402_1% CA20 1 2 2.2U_0603_6.3V6K
RING3_CONN {45}
PORTD_B_MIC 1 2 100_0402_1% CA21 1 2 2.2U_0603_6.3V6K
B HPOUT_R/L, if stuff DA2, RING2_CONN {45} B
RA37/RA38 need change to RA23
3K.
Close to Pin11,13,16
For EMI

+1.5VS +3VS

HDA_RST_AUDIO#
2

HDA_SYNC_AUDIO
RA825 RA826
10K_0402_5% 10K_0402_5% HDA_SDOUT_AUDIO JSPK1
15_0402_5% 1 @ 2 RA25 SPK_R+ RA26 1 2 BLM18PG221SN1D_2P SPK_R+_CONN 1
1
2

RA27 1 @ 2 HDA_BITCLK_AUDIO 15_0402_5% 1 @ 2 RA29 SPK_R- RA31 1 2 BLM18PG221SN1D_2P SPK_R-_CONN 2

1

2
G

27_0402_5% 15_0402_5% 1 @ 2 RA32 SPK_L+ RA30 1 2 BLM18PG221SN1D_2P SPK_L+_CONN 3

@ @ 3
HDA_SDIN0 15_0402_5% 1 @ 2 RA33 SPK_L- RA34 1 2 BLM18PG221SN1D_2P SPK_L-_CONN 4
4
3

HDA_RST_AUDIO# PCH_HDA_RST#_Q
CA22

CA23

CA24

CA25

CA26

5
S

GND1

1000P_0402_50V7K

1000P_0402_50V7K

1000P_0402_50V7K

1000P_0402_50V7K
22P_0402_50V8-J

22P_0402_50V8-J

22P_0402_50V8-J

33P_0402_50V8J

33P_0402_50V8J

6
GND2
220P_0402_50V7K

220P_0402_50V7K

220P_0402_50V7K

220P_0402_50V7K
CA27

CA28

CA29

CA30

CA31

CA32

CA33

CA34
QA198 1 1 1 1 1
2 2 2 2 1 1 1 1 ACES_88231-04001
PJA138K_SOT23-3 ME@
+3.3VD

@
0610 2 2 2 2 2
1 1 1 1 2 2 2 2
@

RA24 1 @ 2
1

0_0402_5% @ @ @ @
A RA28 A
47K_0402_5%
RB751V-40_SOD323-2 For EMI
PCH_HDA_RST#_Q DA3 1 2 @
2

SPKR_MUTE#
RB751V-40_SOD323-2
EC_MUTE# DA4 1 2 @ Title
{44} EC_MUTE# Security Classification LC Future Center Secret Data
Issued Date 2013/08/08 Deciphered Date 2013/08/05 Codec_CX20751
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
RA35 1 2 Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0_0402_5% Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
ACLU9
Date: Monday, December 23, 2013 Sheet 43 of 59
5 4 3 2 1
 5 4 3 2 1

For ESD For EMI RE1 1 @ 2 0_0603_5%

+3VL
PLT_RST# CLK_PCI RE2 1 @ 2 10_0402_5%

1 1 Close EC RE3 1 2 0_0603_5% +3VALW

CE1 CE2 +3VALW_EC
220P_0402_50V7K 10P_0402_50V8J CE3 +3VALW_R +3VALW_R
2 @ 2 1 2 VCOREVCC

.1U_0402_10V6-K +3VALW_R All capacitors close to EC LE1 1 2 HCB1608KF-181T20_2P

+3VALW_R
1 1
CE4

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K
1 1 1 1 1 1 .1U_0402_10V6-K CE5

1
+3VS +3VALW_EC CE6 CE7 CE8 CE9 CE10 CE11 1000P_0402_50V7K
RE4 1 @ 2 0_0402_5% LE2 1 2
2 HCB1608KF-181T20_2P EC_AGND 2 RE5
D VCCRTC D
@ 10K_0402_5%
2 2 2 2 2 2
RE6 1 2 0_0402_5% EC_AGND

2
LAN_WAKE# LAN_WAKE# {37,40}

minimum trace width 12 mil

114
121
127
Change RE6 to 0ohm jump

12

11

26
50
92

74
3
UE1 +3VS

VCORE

VSTBY1
VSTBY2
VSTBY3
VSTBY4
VSTBY5
VSTBY(PLL)
VBAT

VCC

AVCC
EC_FAN_SPEED RE10 1 2 10K_0402_5%

EC_FAN_PWM RE11 1 @ 2 10K_0402_5%

{19} WRST#
4 24 LPC_FRAME# RE7 1 2 10K_0402_5%
+3VALW_R {7} KBRST# 5 KBRST#/GPB6 PWM0/GPA0 25 PWR_LED# {45}
{8} SERIRQ 6 SERIRQ/GPM6 PWM1/GPA1 28 BATT_CHG_LED# {45} 1 2 100K_0402_5%
LPC_FRAME# ENBKL RE9 @
{8} LPC_FRAME# 7 LFRAME#/GPM5 PWM2/GPA2 29 BATT_LOW_LED# {45}
1 2 {8} LPC_AD3 8 LAD3/GPM3 PWM3/GPA3 30 BATT_LEN# {52}
DE1 @ PWM
{8} LPC_AD2 9 LAD2/GPM2 PWM4/GPA4 31 SYS_PWROK {5,7}
EC_FAN_PWM
{8} LPC_AD1 10 LAD1/GPM1 PWM5/GPA5 32 EC_FAN_PWM {39} +5VS +3VS
RB751V-40_SOD323-2 {8} LPC_AD0 1 2 0_0402_5% 13 LAD0/GPM0 PWM6/SSCK/GPA6 34 BEEP# {43}
RE53 CLK_PCI LPC ACLU9 NC
{8} CLK_PCI_EC LPCCLK/GPM4 PWM7/RIG1#/GPA7

2
RE8 1 2 100K_0402_5% WRST# 14 120 LAN_WAKE#
15 WRST# TMRI0/GPC4 124 SUSP# RE52 RE51
{7} EC_SMI# 16 ECSMI#/GPD4 TMRI1/GPC6 SUSP# {46,55,56,57}
1 EC_RX 0_0402_5% 0_0402_5%
{40} EC_RX 17 PWUREQ#/BBO/SMCLK2ALT/GPC7 66
EC_TX NTC_V {52} @
CE12 {40} EC_TX 22 LPCPD#/GPE6 ADC0/GPI0 67
PLT_RST# TURBO_V {52}

1
1U_0402_6.3V6K {7,19,37,40} PLT_RST# 23 LPCRST#/GPD2 ADC1/GPI1 68 BATT_TEMP
2 {6} EC_SCI# 1 PAD 126 ECSCI#/GPD3 ADC2/GPI2 69 BATT_TEMP {52,53} RPE3
@ ADC
IT1 GA20/GPB5 ADC3/GPI3 70 VR_IMVP_IMON {59} 2 3
TP_CLK
IT8586E/AX ADC4/GPI4
ADC5/DCD1#/GPI5
71
72
VR_CPU_PWROK
ADP_I {52,53}
{59}
TP_DATA 1 4
ADC6/DSR1#/GPI6 73 ADAPTER_ID {51,53}

{45} KSI[0..7]
KSI[0..7] KSI0
KSI1
58
59 KSI0/STB#
LQFP-128L ADC7/CTS1#/GPI7
78
EC_3VSPWREN {46} 2.2K_0404_4P2R_5%

KSI1/AFD# DAC2/TACH0B/GPJ2 SUSWARN# {7}

KSO[0..17] KSI2 60 79 +5VALW
{45} KSO[0..17] 61 KSI2/INIT# DAC3/TACH1B/GPJ3 80 MAINPWON {52} 1 2 0_0402_5%
C KSI3 DAC H_PROCHOT#_EC RE14 C
62 KSI3/SLIN# DAC4/DCD0#/GPJ4 81 PROCHOT# {52}
KSI4 ENBKL {33}
KSI5 63 KSI4 DAC5/RIG0#/GPJ5 USB_ON# RE15 1 2 100K_0402_5%
+3VALW_R KSI5 Change RE14 to 0ohm jump
KSI6 64 85
65 KSI6 PS2CLK0/TMB0/CEC/GPF0 86 VGA_PWRGD {8,22}
KSI7
36 KSI7 PS2DAT0/TMB1/GPF1 87 PBTN_OUT# {7}
KSO0 VR_+1.0VALW_PWRGD
RPE1 1 37 KSO0/PD0 GPF2 88 VR_+1.0VALW_PWRGD {57}
EC_SMB_CK1 PAD @ KSO1 Int. K/B PS2 ACLU9 NC
2 3 EC_SMB_CK1 EC_SMB_DA1 1 IT2 KSO2 38 KSO1/PD1 GPF3 89 TP_CLK
PAD @
1 4 EC_SMB_DA1 PAD 1 @
IT3
KSO3 39 KSO2/PD2 Matrix PS2CLK2/GPF4 90 TP_DATA
TP_CLK {45}
1 IT4 40 KSO3/PD3 PS2DAT2/GPF5 TP_DATA {45}
PAD @ KSO4
1 IT5 41 KSO4/PD4 96
PAD @ KSO5 EXTERNAL SERIAL FLASH +3VALW_R
2.2K_0404_4P2R_5% IT6 42 KSO5/PD5 GPH3/ID3 97 CAPS_LED# {45}
KSO6
KSO7 43 KSO6/PD6 GPH4/ID4 98 PCH_PWR_EN {46,52,56,57}
44 KSO7/PD7 GPH5/ID5 99 ACOFF {53}
KSO8 VR_+1.5VS_PWRGD
+3VS 1 45 KSO8/ACK# GPH6/ID6 VR_+1.5VS_PWRGD {46,56}
KSI7 PAD @ KSO9 SUSP# RE18 1 @ 2 100K_0402_5%
1 IT7 46 KSO9/BUSY 101
KSI6 PAD @ KSO10
RPE2 IT8 KSO10/PE NC1
2 3 EC_SMB_CK2
WRST# PAD 1 @
IT9
KSO11
KSO12
51
52 KSO11/ERR#
SPI Flash ROM
NC2
102
103 Bay trail Platform SPI is 1.8V level, for mirror, need to check whether ok with ITE SUSP# RE19 1 2 100K_0402_5%

1 4 EC_SMB_DA2 KSO13 53 KSO12/SLCT NC3 105 SYSON RE21 1 2 100K_0402_5%

KSO14 54 KSO13 NC4
For factory EC flash KSO14
KSO15 55 EC_3VSPWREN RE23 1 2 100K_0402_5%
2.2K_0404_4P2R_5% KSO16 56 KSO15 108 ACIN#
KSO17 57 KSO16/SMOSI/GPC3 AC_IN# 109 LID_SW# SYS_PWROK RE12 1 2 10K_0402_5%
KSO17/SMISO/GPC5 UART LID_SW# LID_SW# {45}

ON/OFF 110 82 VGA_GATE#

{45} ON/OFF PWRSW# EGAD/GPE1 VGA_GATE# {8}
{54} EC_ON EC_SMB_CK1
111
115 XLP_OUT SM Bus EGCS#/GPE2
83
84
VDDQ_PGOOD {5,55}
ADAPTER_ID_ON# {53}
Need confirm later
{52,53} EC_SMB_CK1 116 SMCLK1/GPC1 EGCLK/GPE3
to charge ,battery EC_SMB_DA1
{52,53} EC_SMB_DA1 117 SMDAT1/GPC2 77
GPIO RE26 2 1 0_0402_5%
118 SMCLK2/PECI/GPF6 GPJ1 100 EC_MUTE# {43} EC_ADAPTER {51}
GPG2
{37} LAN_PWR_ON# 94 SMDAT2/PECIRQT#/GPF7 SSCE0#/GPG2 106
to thermal sensor EC_SMB_CK2
{19,39} EC_SMB_CK2 95 CRX1/SIN1/SMCLK3/GPH1/ID1 SSCE1#/GPG0 104
EC_SMB_DA2 RE24 2 1 0_0402_5% SYSON
+3VL {19,39} EC_SMB_DA2 CTX1/SOUT1/GPH2/SMDAT3/ID2 DSR0#/GPG6 107 PCH_ME_PROTECT {12}
SYSON
DTR1#/SBUSY/GPG1/ID7 119 SYSON {55}
BKOFF#
CRX0/GPC0 BKOFF# {33}
RE27 1 2 0_0402_5% 112 CTX0/TMA0/GPB2
123
18 AOAC_ON# {40} EMC Request 1
125 VSTBY0 RI1#/GPD0 21 PM_SLP_S3# {7}
Change RE24 to 0ohm jump PM_SLP_S4# {7} RE29 1 2 0_0402_5%
B {59} EC_VR_ON GPE4 RI2#/GPD1 76 PCIE_WAKE# {7,37,40} B
WAKE UP NOVO# {45} @ CE13
TACH2/GPJ0 48 .1U_0402_10V6-K
TACH1A/TMA1/GPD7 47 EC_TS_ON# {33} 2
EC_FAN_SPEED EC_FAN_SPEED {39}
USB_ON# 33 TACH0A/GPD6 19 RE30 1 2 0_0402_5%
VGA_AC_DET
{41,45} USB_ON# 35 GINT/CTS0#/GPD5 L80HLAT/BAO/GPE0 20 VGA_AC_DET {19}
RTS1#/GPE5 GPIO L80LLAT/GPE7 NUM_LED# {45}
93
{7} EC_RSMRST# CLKRUN#/GPH0/ID0 ODD_DA_EC# {42}

2
{7} EC_LID_OUT# 128 CK32KE/GPJ7
+3VL {7} AC_PRESENT CK32K/GPJ6 Clock

VGA_AC_DET RE33 1 2 0_0402_5% Change RE30 to 0ohm jump

@ RE34 1 2 0_0402_5% H_PROCHOT# {6,51,52}
RE35 1 2 10K_0402_5% ON/OFF {59} VR_HOT# +5VS +3VS
AVSS

@
VSS1

VSS2
VSS3
VSS4
VSS5
VSS6

1
RE36 1 @ 2 10K_0402_5% BKOFF# QE1 D 1 RE37 1 2 0_0402_5%
IT8586E-AX_LQFP128_14X14 H_PROCHOT#_EC 2 CE14
1

27
49
91
113
122

75

RE38 1 2 10K_0402_5% LID_SW# G 47P_0402_50V8J RE39 1 @ 2 0_0402_5% J80P1

@ 1
2N7002KW_SOT323-3 S 2 EC_TX 2 1

3
EC_RX 3 2
RE40 1 2 10K_0402_5% BKOFF# 4 3
4

1
EC_AGND +3VL 5
RE41 6 GND1
100K_0402_5% GND2

for EC version update to EX, manual modify PN to FX

ACES_85205-04001

1
ME@

2
RE42
10K_0402_5%
+3VS

2
+3VL BATT_TEMP @ CE16 1 2 100P_0402_50V8J ACIN#
{7,53} ACIN#
CE21 .1U_0402_10V6-K

CE19 .1U_0402_10V6-K
+3VALW_R NOVO# ACIN# @ CE17 1 2 100P_0402_50V8J

1
1 1 D QE2
A GPG2 RE43 2 @ 1 10K_0402_5% +3VL ON/OFF @ CE18 1 2 1U_0402_6.3V6K 2 A
ACIN {53}
.01U_0402_16V7-K

G
C48

GPG2 RE44 2 @ 1 10K_0402_5%

2 2 2N7002KW_SOT323-3 S
1

3
GPG2 RE46 2 1 10K_0402_5% 1
CE20
when mirror, GPG2 pull high .1U_0402_10V6-K
@2
2
when no mirror, GPG2 pull low
Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 EC ITE8586LQFP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
C 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
ACLU9
Date: Monday, December 23, 2013 Sheet 44 of 49
5 4 3 2 1
 5 4 3 2 1

ON/OFF switch
+3VL +3VALW
K/B Connector +3VS 14" 15"
KB_1 KSI1_14 KSO0_15

2
KSI[0..7] KB_2 KSI7_14 KSI2_15
R82 R83
KSI[0..7] {44}
14" 15"

1
@ 100K_0402_5% 100K_0402_5% KSO[0..17] KB_3 KSI6_14 KSI3_15
KSO[0..17] {44} 1 2 @
PWR_CAPS_LED C133 100P_0402_50V8J JKB2 R84 R90
300_0402_5% 300_0402_5% KB_4 KSO9_14 KSO5_15

1
D15 PWR_NUM_LED C134 1 2 @ 100P_0402_50V8J 27 15@ JKB1
NOVO# 2 GND1 28 NUM_LED# 30 31 KB_5 KSI4_14 KSO1_15

2
{44} NOVO# 1 2 @ 1 2 @ 26 GND2 {44} NUM_LED# 29 30 GND1 32
CAPS_LED# C117 100P_0402_50V8J KSO16 C91 100P_0402_50V8J CAPS_LED# PWR_NUM_LED
1 {44} CAPS_LED# 25 26 28 29 GND2
NOVO_BTN# PWR_CAPS_LED CAPS_LED# KB_6 KSI5_14 KSI0_15
@ NUM_LED# C118 1 2 @ 100P_0402_50V8J KSO17 C88 1 2 @ 100P_0402_50V8J KSO15 24 25 PWR_CAPS_LED 27 28
ON/OFF R85 1 2 0_0402_5% 3 KSO10 23 24 KSO17 26 27
23 26 KB_7 KSO0_14 KSO2_15
D KSO2 C89 1 2 @ 100P_0402_50V8J KSO1 C90 1 2 @ 100P_0402_50V8J KSO11 22 KSO16 25 D
BAT54CW_SOT323-3 KSO14 21 22 KSO15 24 25
21 24
KB_8 KSI2_14 KSO4_15
KSO15 C92 1 2 @ 100P_0402_50V8J KSO7 C93 1 2 @ 100P_0402_50V8J KSO13 20 KSO10 23
KSO12 19 20 KSO11 22 23
19 22
KB_9 KSI3_14 KSO7_15
KSO6 C94 1 2 @ 100P_0402_50V8J KSI2 C95 1 2 @ 100P_0402_50V8J KSO3 18 KSO14 21
+3VALW +3VL KSO6 17 18 KSO13 20 21
17 20 KB_10 KSO5_14 KSO8_15
KSO8 C96 1 2 @ 100P_0402_50V8J KSO5 C97 1 2 @ 100P_0402_50V8J KSO8 16 KSO12 19
KSO7 15 16 KSO3 18 19
15 18 KB_11 KSO1_14 KSO6_15

2
KSO13 C98 1 2 @ 100P_0402_50V8J KSI3 C99 1 2 @ 100P_0402_50V8J KSO4 14 KSO6 17
R111 R114 KSO2 13 14 KSO8 16 17
13 16 KB_12 KSI0_14 KSO3_15
100K_0402_5% 100K_0402_5% KSO12 C100 1 2 @ 100P_0402_50V8J KSO14 C101 1 2 @ 100P_0402_50V8J KSI0 12 KSO7 15
@ KSO1 11 12 KSO4 14 15
11 14
KB_13 KSO2_14 KSO12_15
KSO11 C102 1 2 @ 100P_0402_50V8J KSI7 C103 1 2 @ 100P_0402_50V8J KSO5 10 KSO2 13

1
@ KSI3 9 10 KSI0 12 13
9 12
KB_14 KSO4_14 KSO13_15
ON/OFFBTN# R119 1 2 0_0402_5% ON/OFF KSO10 C104 1 2 @ 100P_0402_50V8J KSI6 C105 1 2 @ 100P_0402_50V8J KSI2 8 KSO1 11
ON/OFF {44} 7 8 10 11
KSO0 KSO5 KB_15 KSO7_14 KSO14_15
KSO3 C106 1 2 @ 100P_0402_50V8J KSI5 C107 1 2 @ 100P_0402_50V8J KSI5 6 7 KSI3 9 10
J5 1 2 KSI4 5 6 KSI2 8 9
5 8 KB_16 KSO8_14 KSO11_14
KSO4 C108 1 2 @ 100P_0402_50V8J KSI4 C109 1 2 @ 100P_0402_50V8J KSO9 4 KSO0 7
SHORT PADS KSI6 3 4 KSI5 6 7
3 6 KB_17 KSO6_14 KSO10_15
KSI0 C110 1 2 @ 100P_0402_50V8J KSO9 C111 1 2 @ 100P_0402_50V8J KSI7 2 KSI4 5
J6 1 2 KSI1 1 2 KSO9 4 5
1 4
KB_18 KSO3_14 KSO15_15
KSO0 C112 1 2 @ 100P_0402_50V8J KSI1 C113 1 2 @ 100P_0402_50V8J KSI6 3
SHORT PADS ACES_88514-02601-071 KSI7 2 3
2
KB_19 KSO12_14 KSO16_15
ME@ KSI1 1
1
KB_20 KSO13_14 KSO17_15
ACES_50504-3041-001
For EMC ME@ KB_21 KSO14_14 KB_LED_PWR_15
TP/B Connector
KB_22 KSO11_14 CAPS_LED#_15
KB_23 KSO10_14 VDD_15
KB_24 KSO15_14 NUM_LED#_15

+5VS TP_PWR TP_CLK

TP_DATA
C R160 1 @ 2 PWR/B Connector USB I/O Connector
C

2
+3VS 0_0402_5%
JTP1 DT1
R141 1 2 1
0_0402_5% TP_CLK 2 1
{44} TP_CLK 3 2
TP_DATA
.1U_0402_10V6-K

{44} TP_DATA 4 3
1 TP_P4
@1 @1 TP_P5 5 4
Right Side USB2.0 Port X 1 (USB/B)
100P_0402_50V8J

100P_0402_50V8J

TP_P6 6 5 7
6 GND1 8
2 GND2
C114

2 2
C115

C116

ACES_50503-0060N-001
ME@ @ AZC199-02S.R7G_SOT23-3 +3VL +5VALW U3 +USB_VCCB +USB_VCCB

1
For EMC 1 8 +3VS JUSB3
JPWRB1
1 2.2U_0603_6.3V6K GND VOUT3 18 20
NOVO_BTN# 2 1 C119 1 2 2 7 17 18 G2 19
TP_P4 ON/OFFBTN# 3 2 VIN1 VOUT2 16 17 G1
LID_SW# 4 3 3 6 R67 1 2 0_0402_5% USB20_P0_CONN 15 16
TP_LEFT Button TP_P5
TP_LEFT Button TP_P5 5 4 VIN2 VOUT1 {8} USB20_P0
R66 1 2 0_0402_5% USB20_N0_CONN 14 15
{8} USB20_N0

AZ5215-01F_DFN1006P2E2
6 5 7 USB_ON# 4 5 USB_OC1# 13 14
6 GND1 {41,44} USB_ON# EN/EN FLAG USB_OC1# {8} 13

1
8 12
GND2 {16} HUB_USB20_P2 11 12
D17 1

1
{16} HUB_USB20_N2 11
1

5
AZ5215-01F_DFN1006P2E2

AZ5215-01F_DFN1006P2E2
ACES_50503-0060N-001 AP2820CMMTR-G1_MSOP8 C120 10
SW1 SW2 ME@ 1000P_0402_50V7K 9 10
EVQPLHA15_4P

EVQPLHA15_4P
A1

GND1

A1

GND1
A

9
1

1
DT2 DT3 Low Active 2A @ 8
2 8

2
HP_OUTR 7
For 14" For 15"
1

1
{43} HP_OUTR 7
@ HP_OUTL 6
{43} HP_OUTL

2
6
GND2

GND2

5
LID_SW# {44} 4 5
RING2_CONN
1 VDD 1 VDD
B1

B1

{43} RING2_CONN 4
B

B
2

2
14@ 15@ 3
@ @ RING3_CONN 2 3
3

2
{43} RING3_CONN PLUG_IN 1 2
{43} PLUG_IN 1
2 CLK 2 CLK For EMC
ACES_50505-0184N-P01
TP_RIGHT Button TP_RIGHT Button ME@
TP_P6 TP_P6
3 DAT 3 DAT NOVO_BTN# ON/OFFBTN#

AZ5215-01F_DFN1006P2E2

AZ5215-01F_DFN1006P2E2
1

1
B B
AZ5215-01F_DFN1006P2E2

AZ5215-01F_DFN1006P2E2

L14
4 GND 4 GND SW3 SW4 D18 D19 USB20_P0 1 2 USB20_P0_CONN
EVQPLHA15_4P

EVQPLHA15_4P
A1

GND1

A1

GND1

1
A

1 2
1

DT4 DT5
1

USB20_N0 4 3 USB20_N0_CONN
5 TP-L 5 TP-L 4 3

2
GND2

GND2

@ @ CMM21T-900M-N_4P
B1

B1

2
B

B
2

14@ 15@
@ @
6 TP-R 6 TP-R
3

Change to same as ACLUA For 14" For 15"

LED

PWR_LED# LED1 1 2 14@ R142 1 2 1.5K_0402_5%

{44} PWR_LED# +5VALW
LTW-C193TS5

LED4 1 2 15@

LTW-C193TS5

BATT_LOW_LED# LED2 1 2 14@ R143 1 2 470_0402_5%

{44} BATT_LOW_LED# +3VALW
LTST-C193KFKT-LC

A A

LED5 1 2 15@

LTST-C193KFKT-LC

BATT_CHG_LED# LED3 1 2 14@ R144 1 2 1.5K_0402_5%

{44} BATT_CHG_LED# +5VALW
LTW-C193TS5
Security Classification LC Future Center Secret Data Title

LED6 1 2 15@
Issued Date 2013/08/08 Deciphered Date 2013/08/05 KBD/PWR/IO/LED/TP Conn.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
LTW-C193TS5 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
ACLU9
Date: Monday, December 23, 2013 Sheet 45 of 59
5 4 3 2 1
 A B C D E

+5VALW to +5VS AP4800BGM +3VALW to +3VS AP4800BGM

VGS=10V, ID=9A, Rds=18m ohm VGS=10V, ID=9A, Rds=18m ohm
VGS=+-25V VGS=+-25V
+3VALW +1.35VS_SOC_VGA

+5VALW +3VALW Q4607

+5VS +3VS
Q4601 Q4602
3 4
8 1 8 1 LX IN

1
4.7U_0603_6.3V6K
7 2 1 1 7 2 1 1 +5VALW +5VLP 2 R4606
6 3 6 3 GND

C4606
1 1

4.7U_0603_6.3V6K
C128 5 C125 C126 C129 5 C127 C130 1 5 16.5K_0402_1% 1

2
10U_0805_25V6K 10U_0805_25V6K 1U_0603_25V6M 10U_0805_25V6K 10U_0603_6.3V6M 1U_0603_25V6M EN FB CC117

C4608
1

1
@ AP4800BGM-HF_SO-8 2 2 @ AP4800BGM-HF_SO-8 2 2 SY8089AAAC_SOT23-5

4
@ @

4
@ @

2
2 R151 2 R152 @ R4605 @ R4604 .1U_0402_10V6-K
@ 470_0603_5% 470_0603_5% 100K_0402_5% 100K_0402_5% Vout=0.8(1+R4606/R4607) 2
@

1
R154
5VS_GATE_R 1 2 5VS_GATE 2 R155 1 +3VS_PWREN# R4608 R4607
+20VSB
82K_0402_1% 150K_0402_5% R158 VR_+1.05VS_PWRGD 1 2 24K_0402_1%
3VS_GATE_R 1 R156 2 3VS_GATE 2 1 +20VSB

1
1 D Q22 Q23 D 0_0402_5% 470K_0402_5% 0_0402_5%

2
3

1
C131 R165 2 SUSP 2 D Q24B .1U_0402_10V6-K

1
0.01U_0402_25V7K 820K_0402_5% G G 1 D Q24A Q25 D 5 C4607
EC_3VSPWREN {44}
@ C4605 R4601 2 +3VS_PWREN# 2 G @

2
2 S 2N7002KW_SOT323-3 @ S 2N7002KW_SOT323-3 0.01U_0402_25V7K 820K_0402_5% G G

3
1 @ S 2N7002KDWH_SOT363-6 1

4
2 S 2N7002KDWH_SOT363-6 @ S 2N7002KW_SOT323-3

3
AON6414AL
VDS=30V VGS=20V, ID=50A,
+1.0VALW
Rds=8mohm @ VGS=10V +1.0VS
+5VALW +5VLP +5VALW VGS(th)=2.5V Max
+3VALW +3VALW_SOC
1

1
J7 @
1 2 R162 R163 +0.675VS Q4606
1 2 1
R161 100K_0402_5% 100K_0402_5% AON6414AL_DFN8-5
100K_0402_5% @ C219
JUMP_43X79

1
1 .1U_0402_10V6-K
2

2
R159 2 2
@
PCH_PWR_EN#_R R164 1 2 100K_0402_5% PCH_PWR_EN# SUSP 47_0603_5% 5 3
{34} SUSP
LP2301ALT1G_SOT23-3 Id=3.2A @

2
1

3 1

D
Q27 D Q26

4
{44,52,56,57} PCH_PWR_EN PCH_PWR_EN 2

3
G 1 1 Q10A D D Q10B 5VS_GATE 2 1
C4601 C4602 2 5 SUSP R269 0_0402_5%

G
2
S 2N7002KW_SOT323-3 .1U_0402_10V6-K {44,55,56,57} SUSP#
0.01U_0402_25V7K G G 1
3
1

C446
1000P_0402_50V7K
@ @
2 2 2N7002KDWH_SOT363-6 S S 2N7002KDWH_SOT363-6

4
R166
100K_0402_5% PCH_PWR_EN#_R 2
2

1
C4603
.1U_0402_10V6-K
@
for 8s reset SOC off power 2

AON6414AL AON6414AL
VDS=30V VGS=20V, ID=50A, VDS=30V VGS=20V, ID=50A,
+1.35V +1.35VS
Rds=8mohm @ VGS=10V +1.8VALW
Rds=8mohm @ VGS=10V +1.8VS
VGS(th)=2.5V Max VGS(th)=2.5V Max
+5VALW +5VLP

+5VALW +5VLP

1
+20VSB Q28 +20VSB Q30
1 1
AON6414AL_DFN8-5 R892 @ R893 0601 ADD AON6414AL_DFN8-5

1
C214 100K_0402_5% 100K_0402_5% C216
1 .1U_0402_10V6-K R894 @ R895 1 .1U_0402_10V6-K
2

2
2 2 100K_0402_5% 100K_0402_5% 0601 ADD 2 2
@
2

2
@
R896 5 3 R898 5 3
100K_0402_5% +1.35VS_PWREN# 100K_0402_5%

2
+1.8VS_PWREN#
1

4
3

0601 ADD +1.35VS_PWREN 2 1 D 0601 ADD +1.8VS_PWREN 2 1

R289 0_0402_5% 5 Q170B R266 0_0402_5%
VR_+1.05VS_PWRGD {56}

3
Q163B G D 2N7002KDWH_SOT363-6
1 1
C484

C444
1000P_0402_50V7K

1000P_0402_50V7K
2N7002KDWH_SOT363-6 5
VR_+1.5VS_PWRGD {44,56}
6

2
2 2
D S G D Q170A
4

+1.35VS_PWREN# 2 R897 +1.8VS_PWREN# 2 R899

G Q163A 330K_0402_5% 2 S G 2N7002KDWH_SOT363-6 330K_0402_5% 2

4
2N7002KDWH_SOT363-6
S S
1

1
3 3

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 DC V TO VS INTERFACE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
ACLU9
Date: Monday, December 23, 2013 Sheet 46 of 59

4 4

A B C D E
 5 4 3 2 1

B2 A2
D
+3VLP PCH_PWR_EN# 1 D

Q26,+3VALW_SOC

V
V
AC A1
MODE VIN 3
VR_+1.0VALW_PWRGD

V V
A2 A4 B5

V
PU401 2

V
PU301 +3VALW_SOC

V
B+
+3VALW
BATT BATT V V

V V V
MODE B1
4
PCH_RSMRST#
EC
5 PBTN_OUT#

EC_ON SOC
A3 B4 other Device
PM_SLP_S3#
PM_SLP_S4# 6

V
PLTRST# 15

V
14
DDR_CORE_PWROK

V V
C C

B3 13
SYS_PWROK

V
ON/OFF V
NOVO

PXS_PWREN
(DIS)
Vb
+VGA_CORE

V
11 VR_REDY SYSON 7 +1.35V
PU909

V
PU501
DGPU_PWROK
PXS_PWREN
10 Va (DIS)

V
PU901 VR_ON Q4601 +1.35VGS

V
V

V
+CPU_CORE +5VS QV14
Q28

V
B Q4606 B

V
+1.35VS +1.05VGS

V
+1.0VS
SUSP# 9 PU702

V
VGA
PU602

V
V
PU603 +1.5VS
+1.05VS VR_+1.05VS_PWRGD +3VG_AON

V
QV11
V PU501
+0.675V VR_+1.5VS_PWRGD

12
V
EC_3VSPWREN Q30
V
Q4602
+1.8VS
+3VS

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 Power sequence Block

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
ACLU9
Date: Monday, December 23, 2013 Sheet 47 of 59
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 Virtual symbol

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
ACLU9
Date: Monday, December 23, 2013 Sheet 48 of 59
5 4 3 2 1
 5 4 3 2 1

NH1 NH3 NH4 NH5

HOLEA HOLEA HOLEA HOLEA

1
D D

pad_c2p3d2p3n pad_o2p3x2p8d2p3x2p8n pad_o2p3x2p8d2p3x2p8n pad_c2p3d2p3n

H1 H2 H3 H4 H5 H6 H11 H12
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA H7 H8 H9 H10 HOLEA HOLEA
HOLEA HOLEA HOLEA HOLEA
1

1
1

1
PAD_SHAPET5P0X6P0B7P0D2P3
pad_SHT7P0X7P05BR10P65X10P3D2P8 Pad_ct8p0b9p0d2p8 Pad_ct8p0b9p0d2p8 pad_shapet8p8x8p0cb9p0d2p8 pad_shapet8p8x8p0cb9p0d2p8 pad_ct6p0d4p3 Pad_ct6p0b8p0d4p6
PAD_CT6P5B5P0D4P0 PAD_CT6P5B5P0D4P0 PAD_CT6P5B5P0D4P0 PAD_CT6P5B5P0D4P0

C C

H13 H14 H15 H16 H17 H18 H19 H20 H22 H23 H21
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
1

1
CHASSIS1_GND
pad_cb8p0d7p0 pad_ct6p0shapeb8p0x6p75d2p3 PAD_CT6P0shapeb10p04x10p0d2p8 pad_ct6p0b7p0d2p3 pad_shapet6p8x8p0cb8p0d2p5 PAD_ShapeT5P0X6P0-D PAD_shapeT5P0X6P0-U pad_ct5p5b6p0d3p3 pad_ct3p8b6p0d3p3 pad_ct5p5b6p0d3p3
pad_ct5p5b8p0d2p5

B+

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6
GP1 GP2 GP3 GP4 GP5 GP6 GP7 GP8 1 1 1 1 1 1

C4901

C4902

C4903

C4904

C4905

C4906
PAD_RT2P65X2P2 PAD_RT2P65X2P2 PAD_RT2P65X2P2 PAD_RT2P65X2P2 PAD_RT2P65X2P2 PAD_RT2P65X2P2 PAD_RT2P65X2P2 PAD_RT2P65X2P2
@ @ @ @ @ @ @ @
2 2 2 2 2 2
1

1
B B
1

1
@ @ @ @ @ @

+VGA_CORE +3VS +3VALW +5VALW +3VALW

GP9 GP10 C137 1 2 .1U_0402_10V6-K

PAD_RT2P21X2P99 PAD_RT2P21X2P99 GP11 GP12 @
@ @ PAD_RT2P45X2P5 PAD_RT2P45X2P5 +3VS +GFX_CORE
1 1 1
1

@ @ C135 C136 C138

FFC CONN GROUND PAD
1

.1U_0402_10V6-K .1U_0402_10V6-K
1

@ @
1

2 2 2
.1U_0402_10V6-K C251 1 2 .1U_0402_10V6-K
@

+3VS +1.35V

C252 1 2 .1U_0402_10V6-K
A
PCB Fedical Mark PAD @ A
For EMC
FD1 FD2 FD3 FD4 FD5 FD6
Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 Hole

1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
ACLU9
Date: Monday, December 23, 2013 Sheet 49 of 59
5 4 3 2 1
 5 4 3 2 1

B+
+5VLP/ 100mA
Silergy
D
Silergy D
SY8208CQNC +5VALW/6A SY8032LDBC
Adaptor Converter DFN10_3X3 +1.0VALW/2.5A
FOR SYSTEM Switch Mode
EC_ON EN PGOOD ALW_PWRGD FOR VDDR
PAGE 39
SUSP# EN PGOOD

+3VLP/ 100mA
Silergy
SY8206BQNC ANPEC
Converter +3VALW/ 5A APL5930AQBI-TRG
EC_ON EN FOR SYSTEM PGOOD ALW_PWRGD
TDFN10_3X3 +1.5VSP/1A
PAGE 39 Switch Mode
FOR VDDR
SUSP# EN PGOOD

TI +1.35V/10A
TPS51716RUKR
SYSON S5 WQFN20_3X3 Silergy
C SUSP# S3 +0.675VS/2A C
TI Switch Mode SY8032ABC
FOR DDR PGOOD SOT23-6 +1.05VSP_VGA/2A
BQ24737RGRR Switch Mode
Battery Charger FOR VDDR
EN PGOOD
Switch Mode
PAGE 46 Onsemi
CPU Core/12A
NCP6132AMNR2G
Silergy
QFN60_7X7 SY8089AAC
Switch Mode GFX Core/14A
SMBus
VR_ON
EN FOR CPU Core PGOOD VGATE
SOT23-5 +1.8VALW/1A
PGOOD_NB Switch Mode
FOR VDDR
EN PGOOD

Battery Onsemi Silergy

B
Li-ion NCP81172MNTWG SY8032ABC B

4S1P/41WH QFN24_4X4 +VGA_CORE/31A SOT23-6 +1.05VS/2A

VIDs
Switch Mode Switch Mode
NVDD_PWR_EN EN FOR VDDR
FOR GPU VDDC PGOOD VGA_PWRGD EN PGOOD

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 Power Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
ACLU9
Date: Monday, December 23, 2013 Sheet 50 of 59
5 4 3 2 1
 5 4 3 2 1

+3VL
VCCRTC
VIN

2
RTC_VCC PD101
JDCIN1 PF101 PJ101 RB751V-40_SOD323-2
1 APDIN 1 2 APDIN1 2 1
1 2 2 1

1
2 3 7A_24VDC_429007.WRML @ JUMP_43X118
3

470P_0402_50V7K

470P_0402_50V7K
4
4

1000P_0402_50V7K

1000P_0402_50V7K
5 JRTC1
5 ADAPTER_ID {44,53} PR101 PD102

1
PC101

PC102

PC103

PC104
D ACES_50299-00501-003 2 1 1 2 BAT_D 2 1 D
ME@

2
1K_0603_5% RB751V-40_SOD323-2
@ @ FDK_ML1220-TT28 change to 1K SD01310018J

RTC_VCC 20MIL
+3VALW 20MIL
VCCRTC 20MIL
BAT_D 20MIL

{53} 737_ACP 737_ACN {53}

@
PC105 +1.05VS +1.05VS
2 1
C C

1
0.1U_0402_25V6 PC106

1
+5VALW 0.1U_0402_25V6 PR102 PR103
PC107 @ 10K_0402_5% 10K_0402_5%
PR104

1
2 1 @{6,44,52} H_PROCHOT#
PU101 @ 2 1 H_PROCHOT#

2
2

@ 0.1U_0402_25V6 10 9

2
PR105 CSN PROCHOT# 0_0402_5% @
0_0402_5% @ 1 8
CSP RESET PR106 @
2 7 1 2 +3VALW
1

PR107 VCC OVSET PR108 +3VALW

1
@ +3VALW 1 2 3 6 1 2 2.94K_0402_1%
ILIM UVSET
2

PC108 PC109 @

GND

1
0.1U_0402_25V6 35.7K_0402_1% 2 1 4 5 24K_0402_1% @ PR109 set OVP
EN TMER 10K_0402_1%
1

2
@ 0.1U_0402_25V6 PR110 @

11

2
1

1
@ 10K_0402_1%
1

PR113 RT9553AGQW_WDFN10_3X3 @

2
@ PR112 10K_0402_5% PR114
PR111 10K_0402_1% @ 124K_0402_1% UVP 9V

1
30K_0402_1% @
2

2
@ 375K for 15uS
2

+3VALW 124K for 5uS

1

PQ101 D
2
{44} EC_ADAPTER G

2N7002KW_SOT323-3 S 45W current limit 2.8A

3

65W current limit 3.6A

B @ B

New solution need verify in SDV

This solution will reverse in next phase

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 DCIN / RTC

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
ACLU9
Date: Monday, December 23, 2013 Sheet 51 of 59
5 4 3 2 1
 5 4 3 2 1

VMB2
VMB For KB930 --> Keep PU1 circuit
JBATT1 PF201 PL201 PH201 under CPU botten side :
1 8A_24V_F1206HI8000V024T C8BBPH403025-1TAPING_2P (Vth = 0.825V)
1 2 1 2 1 2 CPU thermal protection at 92+-3 degree C
2 3 EC_SMCA
BATT+ For KB9012 (Red square) --> Remove PU201 circuit, but keep PR206
3 4 EC_SMDA Recovery at 56 +-3 degree C
4 5 PH201, PR205,PR211,PQ201,PR208,PR212
5 6
6

1
7
7

1
100_0402_1%

100_0402_1%
8 PC201 PC202
GND1

PR201

PR202
9 1000P_0402_50V7K 0.01U_0402_25V7K

2
GND2
+5VLP
D SUYIN_200082GR007G232ZR
+3VL D

2
{44,53} ADP_I

2
PC203

1
0.1U_0402_25V6 PR203
@ 4.42K_0402_1% PR204 PR205

1
@ 13.7K_0402_1% 21.5K_0402_1%
+3VS @ @

1
PU201

2
EC_SMB_CK1 {44,53} 1 8 NTC_V_1
VCC TMSNS1

2
2 7 OTP_N_002 2 1
GND RHYST1
EC_SMB_DA1 {44,53}

1
PR206 3 6 Turbo_V_1 PR207
{6,44,51} H_PROCHOT# 100K_0402_1% OT1 TMSNS2
PR208 10K_0402_1% PH201
1 2 +3VALW @ 4 5 ADP_OCP_2 1 2 @

1
100K_0402_1% @ OT2 RHYST2 100K_0402_1%_NCP15WF104F03RC

2
0_0402_5%

10K_0402_1%

0_0402_5%
D G718TM1U_SOT23-8 PR209

2
PR210

PR211

PR212
PQ201 2ADP_OCP_1 57.6K_0402_1%

OTP_N_003
PR213 2N7002KW_SOT323-3 G @
BATT_TEMP_IN 1 2
10K_0402_5%
BATT_TEMP {44,53} A/D S

1
@ @
@ PR214
1 2
MAINPWON {44}
0_0402_5%

{44}

{44}
Turbo_V

NTC_V
PR215
1 2
{44} PROCHOT#
0_0402_5% @
3

C C
+3VALW
VMB2
+5VALW @
+3VALW +5VALW PR218
JBATT2 0_0402_5%
1 2 1 H_PROCHOT#
1

2
2 PD201 @
2

UVP_1
3 EC_SMCA AZC199-02S.R7G_SOT23-3 PR216 @ @
3 4 EC_SMDA PR217 PR219
4 10K_0402_1%
5 BATT_TEMP_IN VMB2 221K_0402_1% 430K_0402_1%
5 6
1

1
6

3
7 D PQ202B

1
7

499K_0402_1%
8 Reverse PD305 For EMI request @ 5 2N7002KDWH_SOT363-6
GND1

1
9 PR221 G @
GND2
1

PR220
1 2
PD202 @ S
1

4
SUYIN_200082GR007G232ZR 1.78M_0402_1%

2N7002KDWH_SOT363-6
@ @

1
PQ202A D

6
2

12.5V PU202B D 1 2 2 PQ205

1 PR222 2 5 2 VIN G 2N7002KW_SOT323-3

P
2

+_2

1M_0402_5%
AZ5215-01F_DFN1006P2E2 7 G PR353
O2

180K_0402_1%

PR352
20K_0402_1% 6 1M_0402_5% S

3
-_2

G
@ S @
@ @

1
1

1
220P_0402_50V7K

430K_0402_1%
PR223
PC204 AS393MTR-G1_SO8

4
PR224
0.1U_0402_25V6 @

2
1
PC205
2 @

2
@

B B
PR225
1 2
0_0603_5%
@ +VSBP
+5VALW PQ210
+3VALW +3VALW TP0610K-T1-E3_SOT23-3 @
PJ201
VMB2 JUMP_43X39
1

100K_0402_1%

PC206 3 1 1 2
100K_0402_1%

B+ 1 2 +20VSB
2

0.01U_0402_25V7K

0.22U_0603_25V7K
PR226

PR227
2
1

1
100K_0402_1%
@

2
PR228

PC207
PR229 PR230
280K_0402_1% 10M_0402_5% PC208
1

1 2 0.1U_0402_25V6
BATT_OUT {53}

1
PR231
2

2
10K_0402_1%
8

1 2 PU202A PR232
3

3 D PQ203B 1
VSBP_2 2 VSBP_3
P

+_1 1 5 2N7002KDWH_SOT363-6
2 O1 G 22K_0402_1%
-_1
1

@
1

PC209 PR233 AS393MTR-G1_SO8 S

4

0.1U_0402_25V6 49.9K_0402_1%
+3VALW @ PR234
2

1
0_0402_5% PQ204 D
2

1 2 VSBP_1 2
{54} ALW_PWRGD G
100K_0402_1%
2

100K_0402_1%

1
PR235 S 2N7002KW_SOT323-3
PR236

3
2 1 +3VL PR237 PC210
A 1 2 1U_0402_6.3V6K A
{44,46,56,57} PCH_PWR_EN
2
2N7002KDWH_SOT363-6

1K_0402_1% @
1
2

PR238 PQ203A
6

PR239 10K_0402_1% D
100K_0402_1% 1 2 2
{44} BATT_LEN# G
1

S Title
Security Classification LC Future Center Secret Data
1

Issued Date 2013/08/08 Deciphered Date 2013/08/05 BATTERY CONN/OTP

Use BATT_TEMP to implement BATT_OUT function, THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
New solution need verify in SDV,maybe can reverse in next phase DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
ACLU9
Date: Monday, December 23, 2013 Sheet 52 of 59
5 4 3 2 1
 5 4 3 2 1

B+ Charge Option() bit[8]=1

P2 P3
PQ301 PQ302
AO4407AL_SO8 SI4483ADY-T1-GE3_SO8 PR301 @
8 1 1 8 0.01_1206_1% PJ301
7 2 2 7 JUMP_43X118
6 3 3 6 1 4 1 2 PQ303
VIN 5 5 1 2 AO4407AL_SO8 BATT+
2 3 1 8

0.1U_0402_25V6
2 7

2
PC302
3 6
5

2200P_0402_50V7K
PC301 PC303 PC304

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
D D
PQ304 1 2 10U_0805_25V6K 10U_0805_25V6K

1
1

2
PC305

PC306

PC308

PC309
0.1U_0402_25V6
@ @

4
1
PR302 LTA044EUBFS8TL_UMT3F-3 100P_0402_50V8J DISCHG_G
3

2
200K_0402_5% PR303 @

1
PC307
200K_0402_1%
PR304
2

1
2 @ 1 2 VIN

2
1 P2_G2

2ACOFF-1
47K_0402_1%

1SS355_SOD323-2
{51} 737_ACP {51} 737_ACN
PR305

DISCHG_G-1
10K_0402_1%
1

2
PD301
P2-1 PR306

1
2 200K_0402_1%

1
PQ305
LTC015EUBFS8TL_UMT3F-3 PR307

1
P2_G1

20K_0402_1% PC310 PC311 PQ307B

P2 2 1 2 1 2N7002KDWH_SOT363-6
3

3
D PD302
2

0.1U_0402_25V6 0.1U_0402_25V6 5 PACIN_N 1 2 PACIN_P

2N7002KDWH_SOT363-6

G
6

PQ306A D PR309 PC312

1SS355_SOD323-2
6

2 PR308 D PQ308A 2 1 2 1 BQ24737_VDD S

4
G 68K_0402_1% 2 BATT_OUT {52} 10_1206_5%
G PC313 0.1U_0402_25V6 PC314

6
1M_0402_5%
S 1U_0603_25V6M 1U_0603_25V6M D
1

1
PR310
S 2N7002KDWH_SOT363-6 2 1 737_VCC 1 2 PC315 2 PACIN
1

0.1U_0402_25V6 G
VIN

2
P2-2

PD303 S PQ307A

1
2 RB751V-40_SOD323-2 AO4466L_SO8 2N7002KDWH_SOT363-6
2 1
3

5
6
7
8
PR311 D PQ306B PR312

20

14
2

3
PACIN 1 2 5 2N7002KDWH_SOT363-6 390K_0402_1% PQ311
G

ACP
VCC

ACN

CMPOUT

GND
PACIN_G

47K_0402_1%
1

C S PR313 PR314 PC316 C

4

1 2 737_ACDET 6 17 BST_CHG 1 2 2 1 4
59K_0402_1% ACDET BTST 2.2_0603_5%
PC317 0.047U_0603_16V7K
1 2 ACPRN 5 16
ACOK REGN

3
2
1
0.1U_0402_25V6 PR315 PU301
6

PR316 PQ309A D 1 2 737_SCL 9 18 DH_CHG PR318

{44,52} EC_SMB_CK1 SCL HIDRV
1 2 ACOFF-1 2 0_0402_5% 0.01_1206_1%
{44} ACOFF G
1
PR317
2 8
BQ24737RGRR_VQFN20_3P5X3P5
19 1
PL301
2 CHG 1 4
BATT+
0_0402_5% 737_SDA LX_CHG
{44,52} EC_SMB_DA1 SDA PHASE
S
1

0_0402_5% 4.7UH_PCMB063T-4R7MS_5.5A_20% 2 3

5
6
7
8

1
{44,52} ADP_I ADP_I 7 15
IOUT LODRV
1

PR319 2N7002KDWH_SOT363-6 PQ312 PR320

CMPIN
2

1M_0402_5% 4.7_1206_5%

SRN
BM#

SRP
ILIM 21

10U_0805_25V6K

10U_0805_25V6K
PC318 AO4466L_SO8
PAD @
100P_0402_50V8J
1

1
DL_CHG 4
2

11

10

SRN_1 12

SRP_1 13

PC319

PC320
1 6251_SN

2
BM#

PR321 @

3
2
1
3

PQ308B D 10K_0402_5% PC321

1

10_0603_5%
680P_0402_50V7K
6.8_0603_5%

BATT_OUT 5 1 2
+3VS
1

PR324
G @

2
PR322
PR323

2N7002KDWH_SOT363-6 S 2 1 737_ILIM
4

2
2

100K_0402_1% 1
316K_0402_1%

PR325
0_0402_5% PC322
2

@ 0.1U_0402_25V6
2
PR326

PC323 @
1

1 2 737_SRP

0.1U_0402_25V6
1

B B
737_SRN
2

+3VALW PC324
{44,52} BATT_TEMP 0.1U_0402_25V6
1

+3VALW VIN

BQ24737_VDD
1

PR327
750_0603_1% PR328 PR331

1
1M_0402_5% 1 2
ACIN {44}
PR329 PR330
2

47K_0402_1% 10K_0402_1% 10K_0402_1%

2

2
PACIN

1
PQ309B PR332
2

3
D PQ310A D 12K_0402_1%
PR333 2 ADAPTER_ID_ON#_G ACPRN 5
0_0402_5% G G

2
@
S 2N7002KDWH_SOT363-6 2N7002KDWH_SOT363-6 S
1

ADAPTER_ID {44,51}
1

3
680P_0402_50V7K

D
5 ADAPTER_ID_ON# {44}
1

PR334 G
1M_0402_5%
0.1U_0402_25V6

PD304
1
PC325

A AZ5425-01F_DFN1006P2E2 S PQ310B A
2

4
1

1
PC326

2N7002KDWH_SOT363-6
2

@ PR335
0_0402_5%
2

ACPRN 1 2 ACIN#
ACIN# {7,44}
@

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 CHARGER

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
C 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
ACLU9
Date: Monday, December 23, 2013 Sheet 53 of 59
5 4 3 2 1
 5 4 3 2 1

D D

B+ PU401
@
PJ401 1.5A
2 1 +3V_VIN 7 2 +3V_PWRGD
2 1 EN2 PG

1M_0402_5%
10U_0805_25V6K
0.1U_0402_25V6

SY8206BQNC_QFN10_3X3
1

1
+3VALW

PR401
PC403

PC401

PC402
JUMP_43X79 8 6 +3VBS 1 2
IN BS @ 4A

2
0.1U_0603_25V7-M PL401 PJ402

2
9 10 +3VLX 1 2 +3VALW_P 2 1
GND LX 2 1

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
2.2UH_PCMB063T-2R2MS_8A_20%
PR402 3V_GND

1
1 2 +3VALW_EN 1 4 +3VALW_P JUMP_43X79
{44} EC_ON EN1 OUT

PC404

PC405

PC406

PC407
PR403
0_0402_5% 100mA +3VLP 4.7_1206_5%

2
+3VALW_FB 3 5 @
FB LDO

1 2
4.7U_0603_6.3V6K
1

1
PC409
@ PC408 PR404 PC410
0.1U_0402_25V6 1M_0402_5% 1000P_0402_50V9-J
2

2
@
@ PTP401
2

PAD
3V_GND
3V_GND 3V_GND

PC411
PR405
1 2 1 2

PJ403 0.01U_0402_25V7K 1K_0402_1%

1 2
+3VL
C JUMPER +3VLP @ change 470P to 10nf for soft start time 2ms C
@ PJ404
2 1
2 1
3V_GND
JUMP_43X39

+3VALW

2
PR406
100K_0402_5%

PR407 @

1
+3V_PWRGD 1 2
ALW_PWRGD {52}
B+ PU402
0_0402_5% @
@
PJ405 2.5A PR408
2 1 +5V_VIN 8 2 +5V_PWRGD 1 2
2 1 IN PG
10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6

SY8208CQNC_QFN10_3X3
1

+5VALW
PC413

PC414

PC415 0_0402_5% @
PC412

JUMP_43X79 9 6 +5VBS 1 2
GND BS 3.3UH_PCMB063T-3R3MS_6.5A_20% 5A
2

PC416 0.1U_0603_25V7-M PL402 PJ406

1 2 +5VVCC 5 10 +5VLX 1 2 +5VALW_P 2 1
VCC LX 2 1

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
1
PR409 1U_0603_25V6M PR413

1
EC_ON 1 2 5V_GND +5VALW_EN 1 4 +5VALW_OUT1 2 +5VALW_P PR410 JUMP_43X79
EN OUT

PC417

PC418

PC419

PC420
0_0402_5% 4.7_1206_5%
B B
0_0402_5% 100mA @ @

2
+5VFB 3 7
+5VLP

2
FB LDO
1M_0402_5%

4.7U_0603_6.3V6K
1

1
1

PR411

PC422

PC423
@ PC421 1000P_0402_50V9-J
2

2
0.1U_0402_25V6 @
2

5V_GND

5V_GND 5V_GND

PC424 PR412
1 2 1 2

6800P_0402_25V7-K 1K_0402_1%
PJ407
1 2

JUMPER
@
6800pf soft start 2ms
5V_GND 47nf soft start 7ms

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 PWR_3VALW/5VALW

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
C 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
ACLU9
Date: Monday, December 23, 2013 Sheet 54 of 59
5 4 3 2 1
 A B C D

1k for 500K
12k for 670K
1 1

1
PC501 @
0.1U_0402_10V7K

2
1.35V_GND
PR501 0_0402_5%
+3VALW 1.35V_GND 1 2 SUSP# {44,46,56,57}

100K_0402_1%
@
2A

S3_1.35V
PJ501
2 1

PR503

133K_0402_1%
PR504 0_0402_5% 1.35V_B+
B+

1
2 1 2 1

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6
SYSON {44}

1
PR506

PC503
PR505

1
S5_1.35V

PC504

PC505
1K_0402_1% JUMP_43X79

2
2 1

2
{5,44} VDDQ_PGOOD

2
PC502 0.1U_0402_10V7K @
@

5
20

19

18

17

16
PU501

S3

S5
MODE

TRIP
PGOOD
21 PR507 PC506
PAD 0_0603_5% 0.1U_0603_25V7-M PQ501 @
1 15 1
BST_1.35V 2 2 1 4 PJ502
VTTSNS VBST AON7408L_DFN8-5 2 1
PR508 2 1
2

+1.35V
2A 2
VLDOIN DRVH
14 2 1 UG_1.35V JUMP_43X118 2

0_0402_5%
2A

3
2
1
PL501 PJ503
22U_0805_6.3V6M

22U_0805_6.3V6M

+0.675VSP 3 13 LX_1.35V 1 2 1.35V_L 2 1 DIS ------10A

+1.35V
1

VTT SW 2 1
PC507

PC508

TPS51716RUKR_WQFN20_3X3
0.68UH_PCMC063T-R68MN_15.5A_20% 1 JUMP_43X118 UMA-----6A

1
4 12 @
+5VALW
2

5
VTTGND V5IN AON7506_DFN PR509 + PC509

1
@ 4.7_1206_5% 330U_2.5V_M

VDDQSNS
5 11 PC510
VTTREF DRVL 1U_0603_25V6M PQ502 @ 2

2
REFIN
1

PGND
VREF

1.35V_SN
GND
+VTT_REFP PC511 LG_1.35V 4
1U_0402_6.3V6K
2

10

1
10K_0402_1%

DDR_VREF

3
2
1
PR510

@ 1.35V_GND PC512
2

PJ504 1000P_0402_50V9-J
REFIN

2
+0.675VSP 2 1 +0.675VS @
2 1 PC513
1

0.1U_0402_25V6
JUMP_43X79
1

1.35V_GND
1.35V_GND
1

+1.35VP
1

PR511
PC514 30.9K_0402_1%
Vout=1.367V
2

0.01U_0402_25V7K
Iocp min=23A
2

3 3

1.35V_GND 1.35V_GND

PJ4
1 2

JUMPER
@

1.35V_GND

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 1.35VS/+0.675VS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
ACLU9
Date: Monday, December 23, 2013 Sheet 55 of 59
A B C D
 A B C D

+1.8VALW _L

PU601
2A +1.8VALW
1UH_PH041H-1R0MS_3.8A_20%
PJ601 PL601 PJ602
+3VALW 2
2 1
1 1A +1.8VALW _VIN 4
IN LX
3 +1.8VALW _LX 1 2 2
2 1
1

JUMP_43X79 2 JUMP_43X79

68P_0402_50V8J
22U_0805_6.3V6M

22U_0805_6.3V6M
GND

1
@ @

4.7_1206_5%

1
5 1

PC601

PC602

PR601
FB EN

PC603
1 1

2
PR602

2
SY8089AAAC_SOT23-5 19.6K_0402_1%

22U_0805_6.3V6M

22U_0805_6.3V6M
2

1
FB=0.6Volt

PC604

PC605
@

2
1

2
PC606
680P_0402_50V7K

2
@

@
PR603
SUSP# 2 1 EN_+1.8VALW +1.8VALW _FB
{44,46,55,57} SUSP#
47K_0402_5%

1
1
PR606 PR605

1
2 1 PR604 PC607 10K_0402_1%
{44,46,52,57} PCH_PW R_EN
0_0402_5% 1M_0402_5% .1U_0402_10V6-K

2
2
+5VALW

+1.5VSP +1.5VS

1
2 PC608 500mA 2

1U_0603_25V6M

2
500mA PU602
PJ603 6 PJ604
2 1 5 VCNTL 3 2 1
+3VALW 2 1 9 VIN1 VOUT1 4 2 1
4.7U_0603_6.3V6K

VIN2 VOUT2
1

1
PR607
JUMP_43X39 VR_+1.05VS_PW RGD 1 2EN_1_5VSP 8 JUMP_43X39
PC609

EN

1
@ 7 2 PR608 @

GND
2

0_0402_5% POK FB 21.5K_0402_1% PC610 PC611

1
.1U_0402_10V6-K 220P_0402_50V7K 10U_0603_6.3V6M

2
PC612 APL5930KAI-TRG_SO8

1
@ @
2

1
PR610
PR617 100K_0402_5%

1
100K_0402_5% @
PR609

2
24K_0402_1%
VR_+1.5VS_PW RGD {44,46}
+3VALW +3VS

2
+3VALW
VFB=0.8V
1

PR616
100K_0402_5% +1.05VS_L
3 3

2A
2

{46} VR_+1.05VS_PW RGD

PU603
PJ605 PL602 PJ606
+3VALW 2
2 1
1 1A 1.05VMP_VIN 4
IN LX
3 1.05VMP_LX 1 2 2
2 1
1 +1.05VS
1UH_PH041H-1R0MS_3.8A_20%
JUMP_43X79 5 2 JUMP_43X79
22U_0805_6.3V6M

22U_0805_6.3V6M

PG GND
1

4.7_1206_5%
6 1
PC613

PC614

PR611
@ FB EN @
2

1
SY8032ABC_SOT23-6

68P_0402_50V8J
PR612

22U_0805_6.3V6M

22U_0805_6.3V6M
2

1
FB=0.6Volt 75K_0402_1%

PC615

PC616

PC617
@
1

2
PC618
680P_0402_50V7K
2

PR613
SUSP# 2 1 EN_1.05VMP 1.05VMP_FB
47K_0402_5% 1
1

PR615
1

PR614 PC619 100K_0402_1%

1M_0402_5% .1U_0402_10V6-K
2

4 @ 4
2

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 +1.05VS/+1.5VS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
ACLU9
Date: Monday, December 23, 2013 Sheet 56 of 59
A B C D
 5 4 3 2 1

+3VALW

2
PR701
100K_0402_5%

1
{44} VR_+1.0VALW_PWRGD

2.5A +1.0VALW

22U_0805_6.3V6M
@ PU701 1UH_PH041H-1R0MS_3.8A_20% @
PJ701 PL701 PJ702
2 1 +1.0VALW_PVIN 4 3 +1.0VALW_LX 1 2 +1.0VALW_L 2 1

0.1U_0402_25V6
+5VALW 2 1 IN LX 2 1

1
PC702
D D

PC701
5 2
PG GND

1
JUMP_43X79 JUMP_43X79

2
6 1 PR702
FB EN 4.7_1206_5%

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
@

1
@ PR703 SY8032ABC_SOT23-6 @

PC704

PC705

PC706
1 2 +1.0VALW_EN

1SNB_+1.0VALW
2
{44,46,55,56} SUSP# 0_0402_5%

2
2

1
47K_0402_5%
PR704

PR705
1 2 PC709
{44,46,52,56} PCH_PWR_EN
.1U_0402_10V6-K @

2
0_0402_5%
@ PC711

1
@ 680P_0402_50V7K

2
@

VFB=0.6V

68.1K_0402_1%
PR706
+1.0VALW_FB 1 2

1
PR707
100K_0402_1%
2 1 PC712
220P_0402_50V7K

2
C C

+3VS

2
PR708
10K_0402_5%
OPT@ +1.05VSP_VGA

{22} +1.05VGS_PWRGD 1 2.5A

PU702
@ @
PJ703 PL702 PJ709
+3VALW 2 1 1.05VGS_VIN 4 3 1.05VGS_LX 1 2 2 1 +1.05VGS
2 1 IN LX 1UH_PH041H-1R0MS_3.8A_20% 2 1
5 2
22U_0805_6.3V6M

22U_0805_6.3V6M

68P_0402_50V8J
JUMP_43X79 OPT@ JUMP_43X79
PG GND
1

4.7_1206_5%

1
PC713

PC714

PR710
6 1
FB EN

PC715
2

2
SY8032ABC_SOT23-6

1
75K_0402_1%

22U_0805_6.3V6M

22U_0805_6.3V6M
2

1
OPT@
PR711
OPT@ FB=0.6Volt

OPT@

PC716

PC717
OPT@ OPT@ @

2
PC718

2
PD701 680P_0402_50V7K

2
1 2 N15VGM@ @
B B

1 2 1.05VGS_EN 1.05VGS_FB
{23,58} DGPU_PWROK OPT@ OPT@

1
PR172 4.7K_0402_5%
1

N15VGM@ PR714
1

PR713 PC719 100K_0402_1%

1M_0402_5% .1U_0402_10V6-K OPT@
PR715 OPT@ @
2

2
2 1
2

{22,58} EN_VGA 0_0402_5%

N15SGT@

1.05VGS_EN 1.05VGS_EN {21}

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 +1.05VS/+1.05VS_VGA

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
C 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
ACLU9
Date: Monday, December 23, 2013 Sheet 57 of 59
5 4 3 2 1
 5 4 3 2 1

+3VGS

2
N15VGM@ PR9442
2 1 10K_0402_5%
{8,21} PXS_PWREN
PR9446 @ PD705
0_0402_5% RB751V-40_SOD323-2

1
OPT@
2 1 1 2 EN_VGA EN_VGA {22,57}
D {19,21} 3VGS_PWR_EN D
PR9445 N15SGT@

1
0_0402_5% PC1303
PR9443 PR9444 .1U_0402_10V6-K
100K_0402_5% 1 2 OPT@

2
@ OPT@
10K_0402_1%

2
+VGA_B+

{19} NVVDD PWM_VID NVVDD PWM_VID PJ710

2 1
2 1 B+
{19} PSI_VGA PSI_VGA

{20} VSSSENSE_VGA VSSSENSE_VGA JUMP_43X79

@

10U_0805_25V6K

10U_0805_25V6K
{20} VCCSENSE_VGA VCCSENSE_VGA

1
PC1295

PC1298
0.1U_0402_25V6
AON6414AL_DFN8-5

1
NVVDD PWM_VID
DGPU_PWROK

PC1255
{23,57} DGPU_PWROK

2
2
PQ991
N15S-GT use config-B 4
N15V-GM use config-D

PR9429 PC1300 OPT@ OPT@ OPT@

B D 0_0603_5% 0.22U_0603_16V7K

3
2
1
2
2 1BOOT1_2_VGA 1 2 PR9441
N15S-GT N15V-GM PR9430 OPT@ OPT@ 0_0402_5%
0_0402_5% 2 1 UGATE1_2_VGA OPT@ PL705 +VGA_CORE
OPT@ 0.24UH_PCME063T-R24MS1R145_35A_20%
R1 PR9440 20 27 reserve OPT@ 1 2

BOOT1_VGA
1
R2 PR9434 20 7.5

5
PQ992 OPT@

10P_0402_50V8J
1
@
R3 PR9436 2 0

1
AON6554_DFN
PC1261
PC1262
2700P_0402_50V7-K PR9435
R4 PR9437 18 6.2

2
1 2 GPU_VID 4.7_1206_5%

330U_D2_2V_Y

330U_D2_2V_Y
1 1
LGATE1_VGA 4 @
C R5 PR9431 0 1.74 + +
C

OPT@ PC1293

OPT@ PC1297
reserve follow

1SNUB1_VGA 2
C(nF) PC1277 2.7 5.6 NV suggestion
7.5K_0402_1% PR9440

1
2 2

PSI_VGA
PR9434 27K_0402_1% UGATE1_VGA OPT@

EN_VGA

3
2
1
VREF 1 2 2 1VIDBUF PR9438
N15VGM@ N15VGM@ 5.1K_0402_1%

1
@

PHASE1_VGA
PR9436

2
PR9431 N15VGM@ 0_0402_5% PC1296
PU909

1
1.74K_0402_1% PR9437 680P_0402_50V7K
N15VGM@

2
N15VGM@ 6.2K_0402_1% @

HG1

BST1
VIDBUF

VID

PSI

EN
2
1 2 1 2 reserve for future tune
PR9447
2 1 PC1294 1
PC1277 2N15VGM@ 7 24
0.01U_0603_50V7K REFIN PH1 PC1301
OPT@ 1 2 5600P_0402_25V7-K VREF 8 23 4.7U_0603_6.3V6K
100_0402_5% PR9439 VREF LG1
OPT@ PR9449 2 1OPT@ FS 9 22 1 2OPT@
0_0402_5% 39K_0402_1% FS PGND
VSSSENSE_VGA OPT@ 2 1 VSS_SEN 10 21 PVCC_VGA 1 2 0_0402_5%
+5VS
FBRTN PVCC PR9418
PC1270 FB_VGA 11 20
@
1

PC1269 47P_0402_50V8J PR9419 OPT@ PC1271 FB LG2 +VGA_B+

1000P_0402_50V7K 1 2FB1_VGA1 2 1 2 COMP_VGA 12 19

TALERT#
COMP PH2

PGOOD
PR9420 OPT@ 51_0402_1% 10P_0402_50V8J
2

TSNS

BST2
0_0402_5% OPT@ PR9421 OPT@ PC1272

GND

VCC

HG2
VCCSENSE_VGA OPT@ 2 1 VCC_SEN 1 2 1 2FB2_VGA1 PR9422 2
OPT@ OPT@

10U_0805_25V6K

10U_0805_25V6K
5
10K_0402_1% 100P_0402_50V8J 82K_0402_1% OPT@

0.1U_0402_25V6
AON6414AL_DFN8-5
25

13

14

15

16

17

18

1
PC1275

PC1276
OPT@ NCP81172MNTWG_QFN24_4X4

PC1273
PR9448
BOOT2_VGA PR9423

VCC_VGA

2
OPT@ PQ993
1 2 0_0402_5%
+VGA_CORE 2 1 4
UGATE2_VGA UGATE2_2_VGA
100_0402_5%

OPT@
DGPU_PWROK OPT@
OPT@ PR9425 OPT@
2

1
B
PC1299 100K_0402_1%_NCP15WF104F03RC 10K_0402_5% PR9424 PC1278 B

3
2
1
2 1 +3VS OPT@ OPT@
PH903

0_0603_5% 0.22U_0603_16V7K
.1U_0402_10V6-K @ 2 1OPT@ BOOT2_2_VGA 1 2
1

1
OPT@ OPT@ PL706

5.9K_0402_1%
+VGA_CORE
2 1 +5VS
PR9426
0.24UH_PCME063T-R24MS1R145_35A_20%
2

PR9427 OPT@ PHASE2_VGA 1 2

2.2_0402_5% OPT@

5
PQ994
VREFOPT@ 2

PC1279

1
AON6554_DFN
1U_0402_6.3V6K
1

OPT@ PR9428
4.7_1206_5%

330U_D2_2V_Y

330U_D2_2V_Y
1 1
LGATE2_VGA 4 @

OPT@
+ +

PC1280

PC1281
PR9432

1SNUB2_VGA 2
0_0402_5% @
2 1
OPT@ 2 2

3
2
1
2 1 +3VS

PR9433 OPT@
10K_0402_5% PC1282
680P_0402_50V7K

2
@

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
1

1
PC1287

PC1288

PC1289

PC1290

PC1291

PC1292
A A

2
@ @ OPT@ OPT@ OPT@ OPT@

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 PWR-VGA_CORE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
ACLU9
Date: Monday, December 23, 2013 Sheet 58 of 59
5 4 3 2 1
 5 4 3 2 1

B+ CPU_GFX_VIN
PJ_43x79_6
PJ901
3A
+1.0VS +3VALW +3VALW
1
+ PC904

68U_25V_M
1

1
@
PR901 PR902 PR903 2
10K_0402_5% 10K_0402_5% PR904 PC901
69.8_0402_1% CPU_GFX_VIN
GFX_CSCOMPA 1 2 GFX_DROOPA 1 2 +GFX_CORE
1.5A

2
PC902 806_0402_1% 1000P_0402_50V9-J
0.1U_0402_25V6
VR_HOT# 1 2 CPU_GFX_VIN
{44} VR_HOT# CORE_GND

1
1 PR905 2

1200P_0402_50V7-K
CPU_RDY PC907 PC903 PC908
D {44} VR_CPU_PWROK

680P_0402_50V7K
D

Thinking_ERTSM0B224J
0_0402_5%
PR907

10U_0805_25V6K

10U_0805_25V6K

0.1U_0402_25V6
75K_0402_1%
1 PR906 2 GFX_RDYA

2
1

1
PC905

PR908

PH901
0_0402_5% 1 2
CORE_GND

PC906
41.2K_0402_1% CLOSE to GFX inductor

2
PC909 PC910

1
1 PR909 2 1 2 1 2 @ PR910
1 2

5
10_0402_1% 330P_0402_50V8J 10P_0402_50V8J
165K_0402_1%
PC911 1 PR911 2 GFX_PH
PR912 PR913
1 2 1 2 1 2
CORE_GND 133K_0402_1% PQ901
1K_0402_1% 6.8K_0402_1% 2200P_0402_50V7K GFX_HG 4

16.5K_0402_1%
AON7408L_DFN8-5

1
PC912 +GFX_CORE

PR914
1000P_0402_50V7K
PR915
PL901 14A

3
2
1
{9} VCC_AXG_SENSE 1 2 GFX_PH 1 2

1
2
1

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
0_0402_5% PC913 PC914 AON7506_DFN @PR916
@PR916 0.47UH_PCMB063T-R47MS_18A_20%
1000P_0402_50V7K 0.047U_0402_25V7K 2.2_0603_5% 1 1
+5VALW

1
GFX_CSCOMPA

PC915

PC916

PC917

PC918
PR917 PR918

330U_D2_2V_Y
2

GFX_DROOPA

1
GFX_CSSUMA
+ +

PC919
1 2 1 2 GFX_PH PQ902 PC920

+GFX_CORE

2
2.94K_0402_1% 330U_2.5V_M

TSENSEA

2
0_0402_5% PC922 GFX_LG 4

1
2 2

CSP1A
1 2
CORE_GND CORE_GND
@PC921
@PC921
0.1U_0402_25V6 PR920 0.47U_0402_25V6K

2
PR919 14.7K_0402_1%

3
2
1
1 2 1 2

61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
+5VALW PU901
CORE_GND
2.2_0603_5%

PAD
VSNA
VSPA
DIFFA
TRBSTA#
FBA
COMPA
IOUTA
ILIMA
DROOPA
CSCOMPA
CSSUMA
CSREFA
CSP2A
CSP1A
TSNSA
PC923
2.2U_0603_6.3V6K PC924
1 2 1 45 PR921
CORE_GND 0.22U_0603_25V7K
2 VCC PWMA 44 1 2 1 2
PR922 GFX_RDYA 3 VDDBP BSTA 43 GFX_HG 2.2_0603_5%
1 2 4 VRDYA HGA 42 GFX_PH
{44} EC_VR_ON EN SWA
VR_SVID_DATA 5 41 GFX_LG
1

0_0402_5% VR_SVID_ALERT# 6 SDIO LGA 40 PR923

PC925 @ VR_SVID_CLK 7 ALERT# BST2 39 1 2
0.1U_0402_25V6
CORE_GND
1 PR924 2 8 SCLK HG2 38 PC926 +5VALW
2

1 PR925 2 30K_0402_1% 9 VBOOT NCP6132AMNR2G_QFN60_7X7 SW2 37 2.2U_0603_6.3V6K 0_0402_5%

10 ROSC LG2 36 1 2
CORE_GND 68K_0402_1% VRMP PVCC
+1.0VS +1.0VS +1.0VS CORE_GND 1 PR926 2 VR_HOT# 11 35
B+ VRHOT# PGND
1K_0402_1% CPU_RDY 12 34 CPU_LG
1

13 VRDY LG1 33 CPU_PH

VSN SW1
1

@ PC927 14 32 CPU_HG PC928

1

PC952 PR927 0.01U_0402_25V7K 15 VSP HG1 31 1 PR929 2 1 2

CSCOMP
2

C DIFF BST1 C

TRBST#
1U_0402_6.3V6K 69.8_0402_1% PR928 PR930 PC933

DROOP

CSSUM

DRVEN
CSREF
2

COMP

TSNS
69.8_0402_1% 69.8_0402_1% 0.1U_0402_25V6 2.2_0603_5% 0.22U_0603_25V7K

CSP3
CSP2
CSP1

PWM
IOUT
2

ILIM
FB
2

CORE_GND CORE_GND CORE_GND

2

16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
PR932
PR931
1 2 13K_0402_1%
{7} CPU_SVID_DAT 1 2
CORE_GND
PR933 PC929
14.3K_0402_1% CPU_DROOP

1 2 16.9_0402_1% CPU_TSENSE 2 1
{7} CPU_SVID_ALERT# CORE_GND CPU_GFX_VIN
PR934
0_0402_5% 0.1U_0402_25V6
1 2 1 2 CPU_PH
{7} CPU_SVID_CLK
20_0402_1% 2.94K_0402_1%
1.5A

2
1 PR936 2 +5VALW PR935
{9} VSS_SENSE
1

PC930
1

PR937

0_0402_5% PC931 0.047U_0402_25V7K

1
1000P_0402_50V7K +CPU_CORE
PR938 11.8K CPU_GFX_VIN 1
2

1 2
2

{9} VCC_SENSE

1
PC932 + PC934 PC935 PC936 PC937

10U_0805_25V6K

10U_0805_25V6K
68U_25V_M
0_0402_5% 1000P_0402_50V9-J
2

0.1U_0402_25V6
2

2
CORE_GND CPU_CSSUM 2

5
PC939
PR939 PC938 1 2 @
CPU_CSCOMP

1 2 1 2
1200P_0402_50V7-K
1K_0402_1% 10P_0402_50V8J PQ903
PR942 4
CPU_HG
PR940 PR941
PC940 PC941 2 1 PC942 1 2 CPU_PH AON7408L_DFN8-5 +CPU_CORE
1 2 1 2 1 2 1 2
680P_0402_50V7K 133K_0402_1%
PL902
12A
10_0402_1% 330P_0402_50V8J 5.9K_0402_1% 2200P_0402_50V7K

3
2
1
PR943 PR944 1 2
CPU_PH
1 2 1 2
{44} VR_IMVP_IMON

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
AON7506_DFN 0.47UH_PCMB063T-R47MS_18A_20%
0.1U_0402_25V6
1

1
75K_0402_1% 165K_0402_1% TSENSEA CPU_TSENSE 1 1
2

1
PC943

PC944

PC945

PC946

PC947
PR945 @PR946
@PR946

330U_D2_2V_Y
2.2_0603_5% + +

PC948
41.2K_0402_1% PH902 PQ904 PC949
1 2 330U_2.5V_M
100K_0402_1%_NCP15WF104F03RC

100K_0402_1%_NCP15WF104F03RC
1

2
CPU_LG 4
2

1 2
Thinking_ERTSM0B224J 2 2

CORE_GND CORE_GND @PC951

@PC951
0.47U_0402_25V6K

3
2
1

2
CLOSE to GFX inductor
8.25K_0402_1%

8.25K_0402_1%
1

1
J901
PR947

PH959

PR948

PH904
B 1 2 B

PR949 PC950
JUMPER
CPU_CSCOMP 1 2 CPU_DROOP 1 2 +CPU_CORE
2

2
910_0402_1% 1000P_0402_50V9-J
CORE_GND

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/09/03 Deciphered Date 2012/09/03 PWR_CPU_CORE/GFX_CORE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
ACLU9
Date: Monday, December 23, 2013 Sheet 59 of 59
5 4 3 2 1
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