EE370

Digital IC Design

L2: Simple Combinational Ckt.

Design

B. Mazhari
Dept. of EE, IIT Kanpur

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Design Example from everyday life

Design a travel plan for going from point A to B with quantitative

constraints of time and money and subjective constraint of
comfort

(i) Generate a tentative travel plan tp1

(i) Evaluate the solution against the constraints. If constraints

are not met then generate another solution by either
modifying the existing one or finding a completely new one.

Generate {tp1 , tp2 , tp3 ,......tp N }

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 Generate {tp1 , tp2 , tp3 ,......tp N }
An optimum solution will be obtained by searching a solution
space consisting of all possible travel plans between the two
destinations.

The generation of candidate solutions requires experience

which provides information on the existing possibilities and
imagination which conceives of new possibilities.

Because both experience and imagination are highly

subjective qualities and also because some of the constraints
such as comfort are also subjective, the solution to design
problems such as the one described here is not unique.

Ability to generate, evaluate and modify alternative solutions

rapidly is key to achieving an optimum solution within a given time
constraint
B. Mazhari, IITK
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As designs become complex, two things happen:

ability to generate and evaluate alternative solutions degrades

the number of possible solutions increases exponentially making

the search for an optimum increasingly difficult.

Travel between city

Hierarchical decomposition

Travel within city

To handle increased complexity, more design levels are required

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Combinational Circuit Design

Function : Y abc abc abc

a, b, and c are inputs and

y is the output.

Performance: delay d

Cwafer w
Area minimum C Die ~
0.85 A
wafer AIC d

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 Y abc abc abc

Decision: Full custom design or semicustom design

4: 1 MUX

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Design consists of several synthesis steps, each of
which involves transformation of behavioral
representation (functionality, performance) into a
structural representation.

Y abc abc abc

VDD

VIN VOUT

yx
GND
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Step-1: Logic Synthesis 1. Minimization
2. Technology mapping

ab
c 00
0
01
0
11
1
10
0
x x 1
0

1 1 1 1 1
Y ab c
-Algorithm is required whose complexity keeps pace with
increasing circuit complexity.

-Manual minimization is tedious, sub-optimal and also error prone

for complex designs.

- A CAD tool is essential

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Logic Synthesis

-Minimization
-Technology mapping

-map the minimized expression onto a network of gates

available in the chosen technology.

a
b
Y ab c ? c

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CMOS : elementary gates are NAND, NOR, NOT etc

-All the above designs have the same functionality but they would differ in
terms of area and delay

-It may be difficult to estimate these values at this stage

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A CAD tool called static timing analysis tool is required
toMazhari,
B. check IITK if delay constraints are satisfied 49
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-All the above designs have the same functionality but they would differ in
terms of area and delay
-It may be difficult to estimate these values at this stage

Two ways:
-take each one of the possible solutions and complete its design to the last
detail.

-choose one possibility based on some estimate of performance and area and
then carry out its detailed design.
B. Mazhari, IITK
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Logic Verification: Horizontal & Vertical

Horizontal : Check compliance with certain rules

Fan-in, Fan-out, floating inputs etc.

a
b

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Logic Verification: Vertical

Y abc abc abc

Desired Behavior
Specifications

Match?

Logic Synthesis

Extract Behavior

Gate netlist Structure

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Logic Simulation

1
0
1 0 1
0
1
1 0
i/p o/p

A CAD tool is required

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 Verification: Generic structure

Desired Behavior
Leveln

Match?

Synthesis

Extract Behavior

Leveln+1 Structure

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Next Phase : Circuit Design

Specifications

Logic verification Logic Synthesis

Gate netlist

Circuit Synthesis circuit verification

Transistor
Schematic

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Circuit Design -Choose a circuit style

CMOS Circuit Styles

Static Dynamic

Fully Complementary Pseudo NMOS Domino

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Circuit Design

-Size Transistors to meet delay specs.and minimize area

Sizing has to be done under uncertainty

A CAD tool: circuit simulator is required to verify performance and

functionality
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Circuit dependent custom sizing of transistors becomes
impossible with increased complexity
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Next Phase : Physical or Layout Design

A design is complete only when we have a

complete plan for its fabrication

Transistor
Schematic

Layout verification Layout Synthesis

Mask Layout

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Layout Design

VDD

VIN VOUT

GND

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Verification

-Design Rule Check (DRC)

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Verification
-Layout vs. Schematic check (LVS)

VDD

VIN VOUT

GND

Circuit simulation on the extracted schematic gives

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 Placement and Routing
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Design Flow

Front-end design

Physical design

Back end design

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 EE370

It is a course about design of digital Integrated

Circuits

The aim is to provide an introduction to all

important aspects of CMOS Digital Design

It is not about design of digital systems using digital

ICs, microprocessors, microcontrollers or DSP
processors etc
 EE370 is a Digital Circuits Design Course

Topics (tentative list)

Sequential circuit Design

RTL design
Operation and Model of MOS devices
Fabrication and Layout
Design of basic Gates
Flip Flops and Memories
Design Methodologies
Simulation Techniques
Static Timing analysis
Floorplanning
Testing

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 Books :
1. Digital Integrated Circuits : A Design Perspective by Jan M. Rabaey,
Prentice Hall
2. Sung-Mo (Steve) Kang, Yusuf Leblebici, and Chul Woo Kim. CMOS
Digital Integrated Circuits Analysis & Design, 4th edition, McGraw
Hill, 2014
3. Neil Weste, CMOS VLSI Design, Pearson, 2011.

Journals : 1. IEEE Journal of Solid state circuits

2. IEEE Trans. On Circuits and Systems
3. IEEE Transactions on Very Large Scale Integration
(VLSI) Systems
4. IEEE transactions on computer-aided design of
integrated circuits and systems

Software : layout tool : http://www.microwind.net/index.php

Circuit simulator : http://www.spectrum-soft.com/index.shtm
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 Grading (tentative, % allocation may be revised):

Tutorial + class Assessment 10%

Two Quizzes 20%

Mid-Sem 25%

End-Sem 45%

Instructor: B. Mazhari ( baquer@iitk.ac.in; Tel: 7924; Office :

WL123)

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