Beruflich Dokumente
Kultur Dokumente
67XXB
SWEPT FREQUENCY SYNTHESIZER
MAINTENANCE MANUAL
=V= = = = = =· = = = =A = = = = = = = = =- = = =:==:==:==:==
=:==:==:==:==:==:==:==:==4=9 = =A R
0J IS D RI V E M O R G N H IL L C A 95 0 37 2 80 9
.
TEL (408) 778-2000•TELEX 28 5 227 WILTRO N MH •FAX 4 08-778-0239
� "YQ"J:I..."l:"�():r-lr � ===:::==:==
PIN: 10370-10242
REVISION: A
PRINTED: FEBRUARY 1990
COPYRIGHT 1990 WILTRON CO.
WARRANTY
All WILTRON products are warranted against defects in materials and workmanship for one year
from the date of shipment, except for YIG-tuned oscillators, which are warranted for two years.
WILTRON's obligation covers repairing or replacing products which prove to be defective during
the warranty period. Buyers shall prepay transportation charges for equipment returned to
WILTRON for warranty repairs. Obligation is limited to the original purchaser. WILTRON is not
liable for consequental damages.
LIMITATION OF WARRANTY
The foregoing warranty does not apply to WILTRON connectors that have failed due to normal
wear. Also, the warranty does not apply to defects resulting from improper or inadequate main
tenance by the Buyer, unauthorized modification or misuse, or operation outside of the environmen
tal specifications of the product. No other warranty is expressed or implied, and the remedies
provided herein are the Buyer's sole and exclusive remedies.
IMPORTANT
Dear Customer:
To better serve you, WILTRON Company is now
mailing change pages directly to our manual
holders.
To receive future change pages, remove this page
from your manual, fill out, detach, and return the
self-addressed card below (no postage necessary,
when mailed in the United States).
T hank You,
WILTRON Company
Mail TODAY;
... no postage
ca
� required in
U.S.A.
VVXLTRON
MANUAL REGISTER
Fill In manual number and Rev.:
P/N 10370-10242, REV: A --
equipment/instruments.
_ I authorize purchase of
equipment/instruments. Please print.
Name ___________
Title -------
Address __________
__ Magazine advertisements
__ Direct mailings City -------
__ Personal recommendation
State _____ Zip _____
PIN: 00986-00001
REV:D MR-1084
I II II I No
Postage Stamp
Necessary
If Mailed in the
United States
WILTRON Company
490 Jarvis Drive
Morgan Hill, CA 95037-2809
USA
TABLE
OF
CONTENTS
4 SPECIAL OPTIONS
Section 4 is reserved for a listing and description of any special options that are provided with
your model 67XXB Swept Frequency Synthesizer.
5 PARTS LISTS
Section 5 contains parts lists for all major assemblies and printed circuit board assemblies of
the Series 67XXB Swept Frequency Synthesizer (including RF microwave deck components).
The parts lists for the major assemblies include photo and line art illustrations for ease of
component identification.
67XXBMM i/ii
SECTION I
GENERAL INFORMATION
CONTENTS
Paragraph Title Page
67XXBMM 1-1
.----�--- ,CJ
�-� �:::;i-
.
.
L. .
L
-
t.J•
L .�- 1 •
�----------- :
!1
·--�----- �<- �
1-2 67XXBMM
SECTION 1
GENERAL INFORMATION
67XXB MM 1-3
OPTIONS SECTION 1-GENERAL INFORMATION
The OM and MM provide coverage for all models in by 3 dB. This option is available for all models
the 67XXB series. Conversely, the T&Cs contain having an upper frequency of �20 GHz.
model-dependent information. Because of this
model dependency there are nineteen different Option 2B, 110 dB Step Attenuator. Each
T&Cs-one for each frequency model. synthesizer comes supplied with a 110 dB Step
Attenuator installed. Rated output power is reduced
Operating Manual (OM). The OM provides by 3 dB. This option is available for all models
general, installation, and operation information for having an upper frequency limit of 26.5 GHz.
all 67XXB models. The WILTRON part number for
the OM is 10370-10202. Option 2C, 110 dB Step Attenuator. Each
synthesizer comes supplied with a 110 dB Step
Test and Calibration Manual CT&C). The T&C Attenuator installed. Rated output power is reduced
supplies performance verification test procedures, by 4 dB. This option is available for all models
calibration and adjustment procedures, and test having an upper frequency limit of 40 GHz.
records for a specific 67XXB model. The WILTRON
part numbers for all T&Cs are listed in Table 1-2. Option 9K, K Connector. Each synthesizer comes
®
supplied with a rear panel K Connector RF Output
Maintenance Manual (MM). The WILTRON part instead of the type of connector that would normally
number for the MM is 10370-10242. be installed on the front panel. The front panel con
nector is deleted. Rated output power, flatness, and
Table 1-2. Test & Calibration Manual Part Numbers
SWR are slightly degraded.
67XXB Manual
Model Number(s) Part Number 1-7 LEVEL OF MAINTENANCE
67098 & 67098-40 10370-10204
67178 & 67178-20 10370-10206 Maintenance of the 67XXB synthesizer consists of:
67198 10370-10208 • troubleshooting the instrument to a replaceable
67218 & 67218-20 10370-10210 subassembly or RF component.
67228 & 67228-20 10370-10212 • repair by replacing the failed subassembly or RF
67288 & 67288-40 10370-10214 component.
67298 & 67298-20 10370-10216
The 67XXB synthesizer contains firmware that
67308 & 67308-40 10370-10218
generates hidden-key routines and error codes to
67368 10370-10220 aid in troubleshooting instrument failures to the
67378 & 67378-20 10370-10222 replaceable subassembly or RF component.
67408 10370-10224 Section 2- System Description and Troubleshooting
67458 10370-10226 contains lists of these maintenance-related hidden
67478 & 67478-20 1 0370-10228 key routines and error codes.
67538 & 67538-10 10370-10230
67598 & 67598-10 10370-10232 The 67XXB synthesizer may require calibration or
67608 10370-10240 adjustment after repair. Refer to Section 3 of the
67638 10370-10234 T&C manual for your specific 67XXB model for
67698 10370-10236 calibration/adjustment procedures.
67728 10370-10238
1-8 REPLACEABLE SUBASSEMBLIES
1-6 OPTIONS AND PARTS
The following standard instrument options are Table 1-3 is a partial listing of replaceable subas
available. semblies and RF components for the 67XXB series
of synthesizers. It lists those replaceable subas
Option 1, Rack Mount. A kit is available contain semblies and RF components that are presently
ing mounting brackets and chassis track slides. covered byh the WILTRON exchange assembly pro
gram (see paragraph 1-9).
Option 110 dB Step Attenuator. Each
2A,
synthesizer comes supplied with a 110 dB Step ®K Connector is a registered trademark of WILTRON Company
Attenuator installed. Rated output power is reduced
1-4 67XXBMM
SECTION 1-GENERAL INFORMATION EXCHANGE ASSEMBLY PROGRAM
Section 5-Parts Lists provides a complete parts Contact the WIL TRON Customer Service depart
breakdown for the 67XXB series of synthesizers. It ment at (408) 778-2000 for assistance with firmware
contains figures and parts lists for the main com problems or for firmware upgrade details.
ponents of each major 67XXB assembly. Parts lists
of all replaceable components for each PCB assemb 1-13 SCHEMATICS
ly (Al-A29) are also included.
The schematics in this manual are the most current
version in use at the time of publication. They may
1-9 EXCHANGE ASSEMBLY PROGRAM
not accurately reflect the circuitry in your par
WILTRON maintains an exchange assembly pro ticular 67XXB synthesizer. Contact the WILTRON
gram for selected synthesizer subassemblies and RF Customer Service department at (408) 778-2000 for
components (Table 1-3). If a malfunction occurs in assistance in resolving schematic differences.
one of these subassemblies or RF components, the
defective item can be exchanged. Upon request and The schematic conventions used in this manual are
typically within 24 hours, WILTRON will ship the described below.
exchange subassembly or RF component. The cus
• Signal flow is from left to right. All signals enter
tomer then has 30 days in which to return the defec
ing the PCB do so on the left of the page and
tive item. All exchange subassemblies or RF com
those exiting the PCB do so on the right of the
ponents are warranted for 90 days from the date of
page.
shipment or for the balance of the original equip
The arrow points of the signal flags indicate the
ment warranty-whichever is longer.
•
For more information on this program, contact your • The lettering in the signal flags indicate the
local sales representative or call the WILTRON Cus sheet and grid coordinates of the signal destina
tomer Service department at (408) 778-2000. tion (for outputs), or the point of signal origina
tion (for inputs). The sheet number is designated
first.
1-10 PREVENTIVE MAINTENANCE
• The arrow points on the end of connector lines
The rear panel fan on the 67XXB has a two-part air
indicate plugs. The arrow tails on the end of con
filter. The exterior filter element should be peri
nector lines indicate jacks.
odically checked and cleaned as needed. The
Signal lines are identified by a distinctive name,
interior honeycomb element should also be checked
•
The 67XXB synthesizer contains components that 1-14 RECOMMENDED TEST EQUIPMENT
can be damaged by static electricity. Figure 1-2 con
tains a list of precautions for handling static-sensi Table 1-4 provides a list of recommended test equip
ment for maintenance troubleshooting of the 67XXB
tive components. If followed, these precautions will
synthesizer.
minimize the possibilities of static-shock damage to
these components.
Contact the WILTRON Customer Service depart
ment at (408) 778-2000 for help regarding test
1-12 FIRMWARE
equipment compatibility.
The descriptions in this manual of synthesizer
circuitry operation, hidden-key routines, self test
routines, and error codes are based on using version
8.03 operating firmware. If your particular instru
ment contains an older version of firmware, these
descriptions may not accurately reflect its opera
tion. You may wish to upgrade your synthesizer's
operating firmware to the latest available version.
67XXBMM 15
-
STATIC-SENSITIVE COMPONENT HANDLING PRECAUTIONS SECTION 1-GENERAL INFORMATION
1. Do not touch exposed con 2. Do not slide static sensi , 3. Do not handle static sen
tacts on any static sensitive tive components across any sitive components in areas
component. surface. where the floor or work sur
face covering is capable of
generatng a static charge.
�
ATTENTION
Static Sensitive
Devtces
��es�1�1w�\·11
Statlo"s
Reusable Container
Oo Not Destroy
7. Handle PCBs only by 8. Lift and handle sold state 9. Transport and store PCBs
their edges. Do not handle devices by their bodies - and other static sensitive
by the edge connectors. never by their leads. devices in static-shielded con
tainers.
10. ADDITIONAL PRECAUTIONS:
• Keep workspaces clean and free of any objects cabable of holding
or storing an electric charge.
• Connect soldering tools to an earth ground.
• Use only special anti-static suction or wick-type desoldering tools.
1-6 67XXBMM
SECTION 1·GENERAL INFORMATION REPLACEABLE SUBASSEMBLIES AND PARTS
A20 VIG Driver PCB Assy ND34073 18 to 26.5 GHz Amplifier C20552
A21 VIG Driver PCB Assy ND34075 18 to 26.5 GHz Amplifier C18965
cabled D22166
RF Take-off D9970
SP4T, 40 GHz, Output PIN Switch, A31998
Coupler, 20 GHz D21450
cabled D19900
Coupler, 26.5 GHz D21451
. ..................... ........... ...
67XXBMM 1-7
RECOMMENDED TEST EQUIPMENT SECTION 1-GENERAL INFORMA T/ON
CRITICAL RECOMMENDED
INSTRUMENT SPECIFICATION MANUFACTURER/MODEL
Frequency Counter, Frequency: 0.01 to 60 GHz EIP Microwave, Inc., Model 578A, with
with Input Impedance: son External Mixers:
External Mixers Resolution: 1 Hz Option 91 (26.5 to 40 GHz)
Other: Ext Time Base Input Option 92 (40 to 60 GHz)
Power Meter, Power Range: -30 to +20 dBm Hewlett-P ackard, Model 436A, with
with Power Sensors:
Power Sensors HP 8484A (0.01 to 20 GHz)
HP 8485A (0.01 to 26.5 GHz)
HP R8486A (26.5 to 40 GHz)
Digital Voltmeter Resolution: 4-1//2 digits (to 20V) John Fluke, Inc., Model 8840A, with
DC Accuracy: 0.002% +2 counts Option 8840A-09 (True RMS AC)
DC Input Impedance: 1O Mn
AC Accuracy: 0.07% + 100 counts
(to 20 kHz)
AC Input Impedance: 1 Mn
1-8 67XXBMM
SECTION 2
SYSTEM DESCRIPTION AND TROUBLESHOOTING
CONTENTS
2-1 INTRODUCTION . .. .
.... ...... 2-11
6 7XXB MM 2-1
SECTION 2
SYSTEM DESCRIPTION AND TROUBLESHOOTING
CONTENTS (Continued)
2A-POWER SUPPLY
2A-1 POWER SUPPLY ASSEMBLIES: A22, A25, AND PART OF A2S PCBs ..... 2A-1
2B-DIGITAL CONTROL
2B-1 DIGITAL CONTROL ASSEMBLIES: A23, A24, and AS PCBs . ......... 2B-1
2B-6 AS SERIAL 1/0 PCB, DETAILED CIRCUIT DESCRIPTION ..... ...... 2B-4
6E-6.l Microprocessor Interface ..... ... .... .. . .. ......... 2B-4
6E-6.2 Clock Timer ............. ............... . .. .. 2B-4
6E-6.3 Shift Registers . . . .......... ........ . ......... 2B-4
6E-6.4 Multiplexers .... ..... ... . .............. ...... 2B-4
6E-6.5 Ground Return Multiplexer .......... .. ........ ... . 2B-5
6E-6.6 Serial Data Input .... . . . . ....... ........... . . .. 2B-5
6E-6.7 External Reference Detected Signal Input . . .............. 2B-5
6E-6.S Fine Loop Data (FLD 12) Latch ....... ... ........ . .. . 2B-5
2-2 67XXB MM
SECTION 2
SYSTEM DESCRIPTION AND TROUBLESHOOTING
(CONTENTS (Continued
2C-FRONT PANEL
67XXB MM 2-3
SECTION 2
SYSTEM DESCRIPTION AND TROUBLESHOOTING
CONTENTS (Continued)
2D-INPUTS/OUTPUTS
2E-REFERENCE LOOP
2-4 6 7XXB MM
SECTION 2
SYSTEM DESCRIPTION AND TROUBLESHOOTING
CONTENTS (Continued)
2F-COARSE LOOP
2G-FINE LOOP
2G-4 All FINE LOOP DIVIDER, DETAILED CIRCUIT DESCRIPTION ....... 2G-3
2G-4.1 10 MHz Input Circuit . . . . .... . . . . . . . . . . . . .. . . .... 2G-3
2G-4.2 200-3 21 MHz Fine Loop Input .. . ... . . . . . .. . .. . .. ... . 2G-3
2G-4.3 Serial Input Circuits .... ............... .. ...... .. 2G-3
2G-4.4 Counter Circuits ........... .. .. . . . . . . .. .. . . .... 2G-3
2G-4.5 Phase/Frequency Detector . . . . . .. .. . .. . .. .. . . . . . . . . . 2G-4
2G-4.6 Notch Filters ....... . . .. . . . . . . .. . .. . . . . . . . . . . . 2G-4
2G-5 FINE LOOP ASSEMBLIES, TROUBLESHOOTING ... .... .. . ... ... 2G-4
67XXB MM 2-5
SECTION 2
SYSTEM DESCRIPTION AND TROUBLESHOOTING
CONTENTS (Continued)
2H-YIG LOOP/FM
2-6 6 7XXB MM
SECTION 2
SYSTEM DESCRIPTION AND TROUBLESHOOTING
CONTENTS (Continued)
21-ANALOG INSTRUCTION
2J-YIG DRIVERS
67XXB MM 2-7
SECTION 2
SYSTEM DESCRIPTION AND TROUBLESHOOTING
CONTENTS (Continued)
2K-ALC/PULSE MODULATION
2-8 6 7XxB MM
SECTION 2
SYSTEM DESCRIPTION AND TROUBLESHOOTING
CONTENTS (Continued)
2M-MOTHERBOARDnNTERCONNECTIONS
6 7XXB MM 2-9/2- 10
SECTION 2
SYSTEM DESCRIPTION AND TROUBLESHOOTING
This section provides system and subsystem level The synthesizer contains 25-28 printed circuit
descriptions (circuit descriptions, schematics, and boards (PCBs), a front panel assembly, a rear panel
block diagrams) and maintenance troubleshooting assem bly, and a number of microwave com
information for all models of the synthesizer. The ponents/microcircuits (mounted on the RF
material is arranged as follows: microwave deck). The exact number of PCBs con
tained in the instrument varies, depending upon the
• System level theory of operation and block
number ofYIG Driver PCBs included for the specific
diagram
model. The layout of the instrument with covers
• System level maintenance troubleshooting removed is shown in Figures 5-3 and 5-4 of Sec
• Individual subsystem level circuit descriptions, tion 5-Parts Lists. The figures and parts lists con
block diagrams, and schematics tained in Section 5 for the major assemblies of the
• RF microwave deck configuration circuit descrip- synthesizer identify the main components of each
tions and block diagrams assembly.
Paragraph 2-6 and Tables 2-2 through 2-4 provide These PCBs supply regulated voltages to the syn
detailed system troubleshooting information. Table thesizer circuits. The subsystem consists of the A25
2-2 is a listing of all hidden-key routines, useful in Switching Power Supply PCB, A26 Line Filter PCB,
maintenance troubleshooting. Table 2-3 provides A22 Regulator PCB, and part of the A28 Mother
procedures for troubleshooting faults that do not board PCB. Refer to Section 2A-Power Supply for
cause error codes. Table 2-4 is a summary listing of circuit descriptions, block diagrams, PCB parts
error codes with their probable causes. locator diagrams, and schematics.
67XXBMM 2-11
SECTION 2-SYSTEM DESCRIPTION
CIRCUIT SUBSYSTEMS AND TROUBLESHOOTING
ler, are provided by the A24 GPIB PCB. Refer to • Fine Loop - provides the fine tuning frequencies
Section 2B-Digital Control for circuit descriptions, for the YIG Loop. It consists of the A9 Fine Loop
block diagrams, PCB parts locator diagrams, and Oscillator PCB and the All Fine Loop Divider
schematics. PCB. Refer to paragraph 2-4 for a functional over
view and to Section 2G-Fine Loop for circuit
descriptions, block diagrams, PCB parts locator
2-3.3 Front Panel Assembly (Al and A2
diagrams, and schematics.
PCBs)
• YIG Loop/FM - performs phase detection of the
This circuit subsystem interfaces the front panel YIG-tuned oscillator output frequency and
LCD displ ays, the LEDs, the k e y s , and the provides the correction voltages to fine tune and
DEC/INCR knob to the A23 Microprocessor PCB. It phase lock the YIG-tuned oscillator. This loop also
consists of the Al Front Panel PCB and the A2 Front includes circuitry for FM modulation of the YIG
Panel Control PCB. Refer to Section 2C-Front Panel tuned oscillator by external FM input signals. It
for circuit descriptions, block diagrams, PCB parts consists of the Al2 YIG Phase Detector PCB, the
locator diagrams, and schematics. Al6 FM PCB, the A30 Sampler/IF Amplifier Assy,
and the A31 Power Amplifier Assy. Refer to para
graph 2-4 for a functional overview and to Section
2-3.4 Inputs/Outputs (A27 PCB and p/o
2H-YIG Loop/FM for circuit descriptions, block
A29 PCB)
diagrams, PCB parts locator diagrams, and
The A27 Auxiliary 1/0 PCB and the A29 Rear Panel schematics.
Interface PCB contain the interface circuitry for
most of the front and rear panel input/output con
2-3.6 Analog Instruction (A17 PCB)
nectors, including the AUX 1/0 connector. Refer to
Section 2D-lnputs/Outputs for circuit descriptions, The Al 7 Analog Instruction PCB provides the analog
block diagrams, PCB parts locator diagrams, and sweep ramp and tuning voltages to coarse tune the
schematics. YIG-tuned oscillators. It also contains the digital
voltmeter (DVM) and power meter circuitry. The
DVM interfaces with the A23 Microprocessor and
2-3.5 Frequency Synthesis Subsystem-RF
the various analog circuits of the synthesizer. Refer
Casting (A3-A7, A9-A12, A16 PCBs and
to Section 21-Analog Instruction for circuit descrip
A30, A31 Assys)
tions, block diagrams, PCB parts locator diagrams,
This circuit subsystem provides the reference fre and schematics.
quencies and phase lock circuits for precise control
of the YIG-tuned oscillator frequencies. This subsys
2-3.7 YIG Drivers (A18-A21 PCBs)
tem is further divided into the four smaller subsys
tems described below. These PCBs provide the main tuning-current and
• Reference Loop - provides the overall reference bias voltages for the YIG-tuned oscillators. The
for the rest of the frequency synthesis subsystem. actual number of these PCBs depends on the fre
It consists of the 10 MHz Crystal Oscillator as quency coverage of the synthesizer model. Refer to
sembly, the A5 Reference Oscillator PCB, the A7 Section 2J-YIG Drivers for circuit descriptions,
Reference Divider PCB, and the AlO Reference block diagrams, PCB parts locator diagrams, and
Buffer PCB. Refer to paragraph 2-4 for a function schematics.
al overview and to Section 6G-Reference Loop for
circuit descriptions, block diagrams, PCB parts 2-3.8 ALC/Pulse Modulation (A13, A15
locator diagrams, and schematics. PCBs and p/o A29 PCB)
• Coarse Loop - provides the coarse tuning frequen
This subsystem provides level control of the RF out
cies for the YIG Loop. It consists of the A3 Coarse
put power, AM modulation, pulse modulation, and
Loop Mixer PCB, the A4 Coarse Loop Oscillator
multiplexing of the YIG-tuned oscillator RF outputs.
PCB, and the A6 Coarse Loop Divider PCB. Refer
It consists of the Al5 ALC PCB, the Al3 Pulse Gen
to paragraph 2-4 for a funtional overview and to
erator PCB, and part of the A29 Rear Panel Interface
Section 2F-Coarse Loop for circuit descriptions,
block diagrams, PCB parts locator diagrams, and
schematics.
2-12 67XXB MM
SECTION 2·SYSTEM DESCRIPTION
AND TROUBLESHOOTING FREQUENCY SYNTHESIS CIRCUITS, FUNCTIONAL DESCRIPTION
PCB. Refer to Section 2K-ALC/Pulse for circuit coverage (Figure 2-1). Only one YIG-tuned oscillator
descriptions, block diagrams, PCB parts locator is active at any given time. Refer to Table 2L-2 (in
diagrams, and schematics. Section 2L) for a listing of the frequency coverage
and RF microwave deck configuration of each syn
thesizer model.
2-3.9 RF Microwave Deck
connections for a description of the A28 PCB, a parts monics are used by the sampler circuits of the
locator diagram, schematics, and interconnection Sampler/IF Amplifier.
diagrams.
The other input to the Sampler/IF Amplifier is a
sample of RF output signal from the YIG-tuned
2-4 FREQUENCY SYNTHESIS CIB.CUITS,
oscillator. Mixing this RF output signal sample with
FUNCTIONAL DESCRIPTION
the adjacent coarse-loop harmonic produces a low
The frequency synthesis circuits provide phase-lock frequency difference signal which is the YIG IF sig
control for the synthesizer output frequency. These nal (20-32.1 MHz).
circuits, comprising four loops, are distributed over
11 PCBs and two assemblies. The overall block The synthesizer's microprocessor programs the
diagram of these circuits is shown in Figure 2-2. The coarse-loop oscillator's output frequency so that one
operation of the four loops, Reference, Coarse, Fine, of its harmonics will be within 20 to 32. 1 MHz of the
and YIG, is described briefly in paragraph 2-4. 1 desired YIG-tuned oscillator's output frequency. The
below. YIG Phase Detector compares the YIG IF signal to
a 20 to 32.1 MHz frequency reference signal that is
The four phase-lock loop subsystems, operating derived from the 200 to 321 MHz fine-loop oscillator
together, produce an accurately synthesized, low output. The YIG phase detector fine tunes the YIG
noise RF output signal. The output frequency is tuned oscillator via the YIG FM coil driver to
selectable in 1 kHz increments from 10 MHz to eliminate any frequency difference between the two
26.5 GHz, in 2 kHz increments from 26.5 to 40 GHz, signals. The resulting YIG-tuned oscillator output
and in 3 kHz increments from 40 to 60 GHz. The frequency is equal to the frequency of the selected
output signal is ultimately derived from a single coarse-loop harmonic plus 1/10 the frequency of the
precision 10 MHz internal reference. fine-loop signal.
YIG-tuned oscillator$ are used to produce the actual Phase locking the synthesizer's output frequency
RF output signal. Several YIG-tuned oscillators, over a broad frequency range is accomplished by
each tunable over a different frequency range, may programming the coarse-loop oscillator's output to
be installed to give the synthesizer broad frequency various frequencies that have harmonics close to the
67XXB MM 2-13
SECTION 2-SYSTEM DESCRIPTION
FREQUENCY SYNTHESIS CIRCUITS, FUNCTIONAL DESCRIPTION AND TROUBLESHOOT/NG
REFERENCE
BUFFER
·············
. . 440 • 490 MHz
L ��-T.� _ j
PULSE
GENERATOR
······-······
. .
.i . EXT AM :�--"•�•
ALC
.
.. ...........
Figure 2-2. Block Diagram of Frequency Synthesis, ALC, and Modulation Circuits
desired operating frequencies. Exact frequency resulting harmonic steps may be as large as 12.1
tuning for each desired operating frequency is ac MHz at high frequencies.
complished by programming of the fine-loop oscil
lator. (In each case, theYIG-tuned oscillator is first
tuned via its main tuning coil to· the approximate The YIG loop i s f i n e tuned by var y i ng the
desired operating frequency.) 20 to 32.1 MHz reference frequency signal applied
Table 2·1. Example of Coarse-Loop Tuning
The programming (tuning) range of the coarse-loop Rang� vs Ha rmonic Spacing
osc illator provides harmonics in the range of
;;?:1.98 GHz to ""40 GHz. The harmonic signal spacing Desired 1/2 Coarse- Harmonic
varies throughout this range from 1 MHz to VIG Freq Loop Freq Harmonic Freq
12 MHz. An example of this is shown in Table 2-1. In GHz In MHz Number In GHz
Thus, any YIG output frequency can be downcon 2.000 220 9 1.980
verted to a YIG IF signal between 20 to 32.1 MHz.
Since the coarse-loop output is synthesized, its fre 2.198 242 9 2.178
quency can be adjusted only in finite steps. The 2.220 220 10 2.200
2-14 67XXB M M
SECTION 2-SYSTEM DESCRIPTION
AND TROUBLESHOOT/NG FREQUENCY SYNTHESIS CIRCUITS, FUNCTIONAL DESCRIPTION
to the YIG loop phase detector. This signal is derived RF output frequencies of 0.01 to 2. 0 GHz (Band O)
by dividing the fine-loop oscillator signal by a factor are developed by downconverting the fundamental
of 10. By programming the fine-loop oscillator, this frequencies of 6.01 to 8.0 GHz, generated by the SIC
signal can be adjusted in 1 kHz increments over a Band YIG-tuned oscillator, using a 6.0 GHz local
20 to 32. 1 MHz range. The resolution of the fine-loop oscillator signal that is phase locked to the 500 MHz
oscillator (hence the resolution of the RF output signal) Reference Loop oscillator. Precise control of the
is 1 kHz, which is much finer resolution than is avail Band 0 frequencies to 1 kHz accuracy is ac
able from the coarse-loop alone. complished by phase-lock control of the 6. 01 to
8.0 GHz fundamental frequencies prior to downcon
NOTE verting.
Whenever the synthesizer is operating in
the phase-locked mode, the frequency of Frequency doubling of the fundamental frequencies
the YIG IF will always equal 1110 the fre of 13. 25 to 20 GHz, generated by the Ku-Band YIG
quency of the fine-loop oscillator. tuned oscillator, is used to produce the 26. 5 to
40 GHz frequency band (Band 5). Phase-lock control
of the 13. 25 to 20 GHz fundamental frequencies, ac
For applications requiring a resolution finer than
complished prior to their doubling, ensures precise
1 kHz, an external 20 to 32. 1 MHz synthesizer can
control of the Band 5 frequencies to 2 kHz accuracy.
be connected at the rear panel to substitute for the
internal fine-loop signal. The tuning resolution is
RF output frequencies of 40 to 60 GHz (Band 6) are
then determined by the resolution of the external
developed by tripling the fundamental frequencies of
synthesizer.
13.33 to 20 GHz generated by the Ku-Band YIG
tuned oscillator. Precise control of the Band 6 fre
The Coarse Loop and Fine Loop outputs are derived quencies to 3 kHz accuracy is accomplished by
from high-stability 10 MHz and 500 MHz signals phase-lock control of the 13 . 33 to 20 GHz fundamen
produced by the Reference Loop circuits. The tal frequencies prior to tripling.
500 MHz oscillator frequency of the Reference Loop
oscillator is precisely stabilized by locking it to the
internal or external 10 MHz frequency standard. 2-4.3 · FM !rlodulation
67XXB MM 2-15
SECTION 2-SYSTEM DESCRIPTION
ALC AND MODULATION CIRCUITS, FUNCTIONAL DESCRIPTION AND TROUBLESHOOTING
Broadband analog sweeps (�50 MHz wide) of the shaper/driver circuits located on the A29 PCB. The
YIG-tuned oscillator RF output are accomplished by resulting PIN driver current output causes the PIN
applying appropriate sweep ramp signals generated level control d i odes, loca ted in the Control
by the Al7 Analog Instruction PCB to the YIG-tuned Modulator, to adjust the RF output level accordingly.
oscillator's main tuning coil (via the appropriate Thus, the detected RF voltage will be set equal to
Al8-A21 YIG Driver PCB). The A23 Microprocessor the RF reference voltage.
controls the Al7 PCB to produce precisely controlled
start and stop frequencies. For those analog sweeps NOTE
that cross over one or more YIG-tuned oscillator The synthesizer uses two internal level
bands, the microprocessor controls the generation detection circuits. For frequencies <2
and timing of the ramp signals from the Al 7 PCB GHz, the level detector is part of the Down
and the selection of the appropriate Al8-A21 YIG Converter and the RF sample is amplified
Driver PCB(s) throughout the sweep. by the Al5 Band 0 Detector Preamplifier.
For frequencies �2 GHz, the level detector
2·5 ALC AND MODULATION CffiCUITS, is part of the main Directional Coupler
FUNCTIONAL DESCRIPTION and the RF sample is amplified by the Al5
Band 1-4 Detector Preamplifer.
The ALC and modulation circuits provide automatic
level control (ALC), AM modulation and pulse The RF level reference voltage is produced by sum
modulation of the synthesizer's RF output signal. ming a precision de reference voltage with the out
The ALC loop is comprised of circuits, located on the put from the Range and Level DACs, which are
Al5 ALC PCB and part of the A29 Rear Panel Inter controlled by the A23 Microprocessor. By setting the
face PCB, that interface with the Control Modulator output of these DACs to the appropriate voltage, the
and Directional Coupler/Level Detector components Microprocessor adjusts the RF output power to the
located on the RF microwave deck (Figure 2-1). AM level selected by the user. The desired output level
modulation circuits (located on the Al5 ALC PCB) may be set throughout a 12 dB range (standard)
are included in this loop. using either the front panel switches or the GPIB.
For those units with the 110 dB attenuator (Op
Pulse modulation of the synthesizer's RF output sig tions 2A , 2B, and 2C) the output level range is
nal is provided by circuits located on the Al3 Pulse 0--122 dB.
Generator PCB. These circuits interface directly
with the Control Modulator components located on
a. External Leveling
the RF microwave deck (Figure 2-1).
In the external leveling mode of operation, an
external detector is used to monitor the RF
The overall block diagram of the ALC and pulse
power output level of the synthesizer instead of
modulation circuits is shown in Figure 2-3
an internal level detector. The external detector
(page 2-20). The operation of these circuits is
RF signal is sent to the Al5 ALC PCB from the
described briefly in the paragraphs that follow.
front panel input via a preamplifier located on
the A2 Front Panel Control PCB. The ALC con
2-5.1 ALC Loop Operation trols the RF power output as previously
described.
The ALC circuitry located on the Al5 PCB controls
the RF power output level of the synthesizer as fol
lows. A portion of the RF output is detected and b. Power Sweep
coupled out of the Directional Coupler/Level Detec In this mode of operation, the A23 Microproces
tor as an input to the ALC loop. The detected RF sor controls the ALC circuitry to step the RF
sample is routed to the Al5 ALC PCB. The RF output signal through a range of output levels
sample is compared with a reference voltage that specified by the user. This feature can be used in
represents the desired RF power output level. If the conjunction with the sweep mode to produce a
two voltages do not match, an error correction signal set of identical frequency sweeps, each with a
is fed from the Al5 ALC PCB to the P IN different RF power output level.
2-16 67XXB MM
SECTION 2-SYSTEM DESCRIPTION
ANO TROUBLESHOOTING
67XXBMM
FRONT PANEL (2C, 20, 2M) REAR PANEL (20, 2M)
r-
�
BNC Connectors
··---------
, BNC Inputs Coaxlal Sl!Jlal Path BNC Outputs Power Input
[>
�f----�---i· -
: P/OA2PCB :
b. I
EXT LEVEL
L ___________i
I
• ToA15ALC PCB
(ViaA28 Motherboa rd PCB) RF INPUT 0 :(): • Not Used ,
:
!
A26
0 :():
LINE FILTER
I
•
ulse PULSE GATE/ • To A13Pulse Generator PCB PCB
PULSE/TRIG �-----+:():-+-------·ToA13P
'i'
0 S1 .. -·-··1--'
TRIGGER INPUT
:():
GeneratorPCB
10 MHz REF INPUT • To A7 Refe19nce Divider PCB T1
-+-----•• ToA16 FMPCB
�------+A 0
,
:():
;---·---------
EXT F M 'W' = • ToA16 FM Driver PCB (ViaA28 MB PCB) ! T��.:'s��:��R i
"
"" (Via A28 Motherboa rd PCB) FM INPUT
l _____ ______:
b, -----t:o
0
�f-- -+----- ••
ToA15ALC PCB HI RES INPUT :(): • To A1 2 VIG Phasa Del8ctor PCB
EXT AM .o_
0
(Via A28 Motherboard PCB)
:(): • ToA15ALCPCB (Via A28 MB PCB)
ur(@)�----+:():-+----�(
AM INPUT
r--0
MEMORY SEO INPUT
i
�! >--
HORJZ OUTPUT
�
______
f---0
:
� ><11�------'-------+-
POWER SENSOR GPIBConnector
.
-�:�
(Not Included
>-------+- � - - _-_-
--_ _ _ -- -_-_-
___ _ _+
_ -· �:::::
:. : �.
J
SECTION 2-SYSTEM DES CRIPTION
TYPICAL OVERALL BLOCK DIAGRAM AND TROUBLESHOOTING
Phaoe SOOMHz
Enor
e >+--•soo MHz m
10 llHz
Oownconv.ter
CRYSTAL B
OSCILLATOR
�-Oven)
500 MHz
COARSE
M COARSE LOOP
OSCILLATOR
LOOP LOOP
A3COARSE
MIXER
440·480 MHz 440·490MHz
(2F)
�"«-�"'=«':;r«-."""'""'""'"'*"'*"'"*"'"''"""""'"''""""'"'''''"''""'"""""'"'�'*'�i;::-...,.:"*'*=<��R«:"'*'
::."'-��"' ''*"'$'&»''"'"'""'""''"«�>='"'"'"'"'*'�"«i::»"<=�<«'-'''''''"'''"''''�''''''*''*'''*''''*'"*=,.._�,.11
__ __.,.,.�--":4-E-R�-�-CE--.
.. ::�E�g;.
AB S�IAL t,,���,:�:o:>.::::,:::::::,�::::,::::::::::::::: ::::::@
(Con'nued
onSheel2)
:: •.w::-;-;::�::::».;.�).;.�:s:,:;::<>;'$!���<x'STS'!Y.�'W$.��>;:...�<�.:>:;:-..;-."«.::::�:��;*'«'ef.�t.:@
2-18 67XXBMM
SECTION 2-SYSTEM DESCRIPTION
AND TROUBLESHOOTING
FREQUENCY
MODULATION
(2H)
A17ANALOG
INSTRUCTION
ANALOG
INSTRUCTION (21)
To Switched RIW
ToSa,,.....MJX
To RF OUTPUT MUX
67XXBMM
TYPICAL OVERALL BLOCK DIAGRAM
RFOUlPUT
PIN SWITCH llUX
� 211 .5 GHz Models
2-19
,----
1 EXTERNAL I
AM
I
I (FROM FRONT' 1
[ REAR PANEL)
-l
ALC SLOPE
FROM A29PCB
FROM MAIN
MICRO PROCESSOR:
PAO- PA2,
LPA 17
DO- D7
BAN D ODET
ALC
CONTROL
SERIAL DATA
FROM AB PCB
CONTROL
MODULATOR
DRIVER(S)
2-20 67XXB MM
SECTION 2·SYSTEM DESCRIPTION
AND TROUBLESHOOTING SYSTEM TROUBLESHOOTING
check out DACs prior to calibration. Refer to Section the RF ON/RF OFF key.
3 of the 67XXB Test and Calibration manual for your b. Press the LINE STANDBY/OPERATE key to turn
particular instrument model before attempting to the instrument on. After the displays blank and
use these codes for maintenance troubleshooting. the self test starts, release the RF ON/RF OFF
key.
NOTE
2-6.2 TROUBLESHOOTING FAULTS THAT
The master reset function overwrites all
DO NOT PRODUCE ERROR CODES
information stored in the non-volatile
Since the synthesizer must run a self test to RAM, including the nine stored front
generate error codes, faults that cause the instru panel setups with their default values.
ment to be non-operational do not produce error Whenever a master reset is performed,
codes. These faults generally are failure to power up the error code E23-10 may occur on self
properly, unexpected shutdown, and front panel lock test.
67XXB MM 2-21/2-22
SECTION 2-SYSTEM DESCRIPTION
AND TROUBLESHOOTING HIDDEN-KEY ROUTINES
cShlfb
TRIGGER
Code Function
000 Enables the security function that turns off the FREQUENCY and MODULATION displays. It is disabled
by a reset.
001 Enables the security function that turns off all of the front panel displays. It is disabled with a reset.
002 Enables the external high-resolution mode. It is turned off by a reset or <Shift> TRIGGER 003.
004 Makes the non-volatile RAM act like standard RAM on POWER OFF/ON. It is disabled with a master
reset (para 2-6.4).
008 Enables the entry or display of the instrument serial number in the FREQUENCY display window.
009 Enables the display of the current operating firmware and GPIB firmware version numbers in the
FREQUENCYdisplay window. Pressing the <Shift> key exits this function.
010 Enables the display of the Reference Loop frequency in the FREQUENCY display window and the
tuning voltage in the LEVEL display window.
011 Enables direct control of the Fine Loop. The frequency is displayed in the FREQUENCY display win-
dow and the tuning voltage is displayed in the LEVEL display window. Changes to the Fine Loop fre-
quency are made with DATA ENTRY keypad inputs.
012 Enables direct control of the Coarse Loop. The frequency is displayed in the FREQUENCY display win-
dow and the tuning voltage is displayed in the LEVEL display window. Changes to the Coarse Loop fre-
quency are made with DATA ENTRY keypad inputs.
013 Provides normal RESET key operation (resets with default power and RF on). This is the default setting.
014 Suppresses the output-power level when RESET key is pressed. The level-value is not reset. Pressing
LEVEL 1 or LEVEL 2 following a RESET returns output power to the value last set before the RESET
key was pressed.
015 Turns off the digital level-vs-frequency correction. This is the same as sending LCO over the GPIB.
Reset removes the condition.
016 Turns on the digital level-vs-frequency correction. This is the same as sending LC1 over the GPIB. This
is the default setting.
019 Executes the display test that is part of self test. The test turns on all the LEDs and all segments of the
LCD displays continuously. Unit must be turned off to terminate this test.
020 Executes the Microprocessor test that is part of self test. Displays any failures as error codes in the
FREQUENCY display window and outputs a pass/fail message thru the GPIB.
021 Executes the A17 DVM test that is part of self test. Displays any failures as error codes in the FAE-
QUENCY display window and outputs a pass/fail message thru the GPIB.
022 Executes the power supply and A22 voltage regulator test that is part of self test. Displays any failures
as error codes in the FREQUENCY display window and outputs a pass/fail message thru the GPIB.
023 Executes the AS serial 1/0 test that is part of self test. Displays any failures as error codes in the FAE-
QUENCY display window and outputs a pass/fail message thru the GPIB.
024 Executes the A 17 ramp generator test that is part of self test. Displays any failures as error codes in the
FREQUENCY display window and outputs a pass/fail message thru the GPIB.
025 Executes the A13 pulse generator test that is part of self test. Displays any failures as error codes in the
FREQUENCY display window and outputs a pass/fail message thru the GPIB.
026 Executes the A16 FM PCB test that is part of self test. Displays any failures as error codes in the FAE-
QUENCY display window and outputs a pass/fail message thru the GPIB.
67XXB MM 2-23
SECTION 2-SYSTEM DESCRIPTION
HIDDEN-KEY ROUTINES AND TROUBLESHOOTING
<Shift>
TRIGGER
Code Function
027 Executes the A17 Analog Instruction PCB test that is part of self test. Displays any failures as error
codes in the FREQUENCY display window and outputs a pass/fail message thru the GPIB.
028 Executes the A15 ALC PCB test that is part of self test. Displays any failures as error codes in the FRE-
QUENCY display window and outputs a pass/fail message thru the GPIB.
029 Executes the A15 leveling loop test that is part of self test. Displays any failures as error codes in the
FREQUENCY display window and outputs a pass/fail message thru the GPIB.
030 Executes the A15 ALC test that is part of self test. Displays any failures as error codes in the FRE-
QUENCY display window and outputs a pass/fail message thru the GPIB.
031 Executes the AS reference oscillator test that is part of self test. Displays any failures as error codes in
the FREQUENCY display window and outputs a pass/fail message thru the GPIB.
032 Executes the A9, A11 Fine Loop test that is part of self test. Displays any failures as error codes in the
FREQUENCY display window and outputs a pass/fail message thru the GPIB.
033 Executes the A3, A4, AS Coarse Loop test that is part of self test. Displays any failures as error codes in
the FREQUENCY display window and outputs a pass/fail message thru the GPIB.
034 Executes the A12, A16 VIG Loop test that is part of self test. Displays any failures as error codes in the
FREQUENCY display window and outputs a pass/fail message thru the GPIB.
035 Executes the A24 GPIB test that is part of self test. Displays any failures as error codes in the FRE-
QUENCY display window and outputs a pass/fail message thru the GPIB.
080 Unlocks the synthesizer. Mainly used for unlocked FM mode where it is possible to get up to a 25 MHz
deviation. It is disabled by reset or <Shift> TRIGGER 081.
081 Disables hidden-key routine 080. Resets the synthesizer to normal locking.
089 Enables access to hidden-key routines that have <Shift> TRIGGER codes from 300 to 599. These
routines are used for calibration or to check out the DACs to be calibrated. (Refer to the 67XXB Test
and Calibration manual, Section 3,Table 3-3 for a listing these hidden-key routines.)
101 Selects RF level to be on during frequency switching in the CW or step sweep modes (except
bandswitch points).
102 Selects RF level to be off during frequency switching in the CW or step sweep modes only. The RF is
blanked before starting a frequency change and enabled when the RF is within approximately 1 kHz of
the final frequency.
103 Turns RF on during sweep retrace.
104 Turns RF off during sweep retrace. Has no effect in manual or external sweep mode when the RF is al-
ways on.
105 Selects ac coupling for the front panel EXT AM input and the rear panel AM INPUT.
106 Selects de coupling for the front panel EXT AM input and the rear panel AM INPUT.
107 Turns RF on when a TTL-high signal is applied to the front panel PULSEffRIG TTL input or to the rear
panel PULSE/GATEffRIG INPUT when the INTERNAL (PULSE) key is activated.
108 Turns RF on when a TTL-low signal is applied to the front panel PULSEffRIG TTL input or to the rear
panel PULSE/GATEffRIG INPUT when the INTERNAL (PULSE) key is activated.
109 Selects a +SV output for the rear panel RETRACE BLANK OUTPUT and AUX 1/0 connector pin 6 and
the rear panel BANDSWITCH BLANK and Aux i/O connector pin 20.
110 Selects a -5V output for the rear panel RETRACE BLANK OUTPUT and AUX 1/0 connector pin 6 and
the rear panel BANDSWITCH BLANK and AUX 1/0 connector pin 20.
2-24 67XXB MM
SECTION 2·SYSTEM DESCRIPTION
AND TROUBLESHOOTING HIDDEN-KEY ROUTINES
cShlfb
TRIGGER
Code Function
303 Enables direct control of the A15 PCB ALC Level Range DAC. No calibration is performed.
305 Enables direct control of the A15 PCB External ALC Gain DAC. No calibration is performed.
306 Enables direct control and calibration of the A15 PCB %AM DAC (AM Sensitivity).
307 Enables direct control of the A16 PCB FM Sensitivity Cal DAC (FM Driver Output). No calibration is
performed.
308 Enables direct control and calibration of the A16 PCB FM Attn DAC (FM Input Sensitivity).
309 Enables direct control of the A15 PCB ALC Slope DAC. No calibration is performed.
310 Enables direct control of the A17 PCB Sweep Width DAC. No calibration is performed.
312 Enables direct control of the A17 PCB Sweep Time DAC. No calibration is performed.
313 Enables direct control of the A17 PCB Marker/Switch Point DAC. No calibration is performed.
314 Enables direct control of the A29 PCB CW Horiz DAC. No calibration is performed.
315 Enables direct control of the A29 PCB V/GHz Slope DAC. No calibration is performed.
316 Enables direct control of the A29 PCB V/GHz Offset DAC. No calibration is performed.
317 Enables direct control and calibration of the A16 PCB Phase Mod Cal DAC (FM Flatness).
319 Enables direct control of the A17 PCB Linearizer DAC. No calibration is performed.
341 Calibrates the FM meter when there is a 1V peak (0.707 Vrms) input.
343 Calibrates the AM meter when there is a 1V peak (0.707 Vrms) input.
391 Zeros out the frequency calibration for the C/S Band (2 to 8 GHz).
392 Zeros out the frequency calibration for the X Band (8 to 12.4 GHz).
393 Zeros out the frequency calibration for the Ku Band (12.4 to 20 GHz).
394 Zeros out the frequency calibration for the K Band (20 to 26.5 GHz).
395 Zeros out the A16 PCB FM Attn DAC (FM Input Sensitivity) calibration.
396 Zeros out the A15 PCB %AM DAC (AM Sensitivity) calibration.
67XXB MM 2-25
SECTION 2-SYSTEM DESCRIPTION
HIDDEN-KEY ROUTINES AND TROUBLESHOOT/NG
cShlft>
TRIGGER
Code Function
397 Generates memory checksum for the A23 PCB EEPROMs. Must be done anytime calibration of the in-
strument is performed to eliminate checksum errors.
399 Zeros out the frequency calibration for the Ka Band (26.5 to 40 GHz).
400 Automatically calibrates the A16 PCB FM Sensitivity Cal DAC (FM Driver Output) for all installed
frequency bands.
402 Calibrates the ALC bandwidth for each installed frequency band except for the Ka Band (26.5 to
40 GHz).
403 Automatically calibrates the analog sweep time, both the s1 second and > 1 second ranges.
404 Automatically calibrates the A16 PCB FM Sensitivity Cal DAC (FM Driver Output) for all installed
frequency bands.
405 Automatically calibrates the paths used by analog sweeps.
406 Automatically calibrates the pathes used by narrow band sweeps (analog sweeps of :550 MHz).
407 Calibrates the ALC slope for the <2 GHz (heterodyne band) and the � GHz frequency bands.
612 Sets the A17 DVM scale to 2. This makes the voltage range -20 to+20 Volts.
614 Sets the A17 DVM scale to 10. This makes the voltage range -100 to + 100 Volts.
2-26 67XXB MM
SECTION 2·SYSTEM DESCRIPTION
AND TROUBLESHOOT/NG HIDDEN·KEY ROUTINES
cShlfb
TRIGGER
Code Function
703 Enables control of the A1 7 analog ramp and set it to the end.
704 Enables control of the A1 7 analog ramp and set it to the beginning.
732 Displays the tuning range of the VIG Loop for the current band.
67XXB MM 2-27
SECTION 2-SYSTEM DESCRIPTION
HIDDEN-KEY ROUTINES AND TROUBLESHOOTING
cShlft>
TRIGGER
Code Function
791 Sweeps the A17 Tuning DAC in 100 step increments.
792 Sweeps the A17 Sweep Width DAC in 100 step increments.
793 Sweeps the A17 Tuning and Sweep Width DACs at the same time.
821 Stops the analog sweep at each dwell point. The microprocessor will stop the sweep just before it
locks. Pressing <Shift> allows the sweep to continue to the next dwell point.
2-28 67XXB MM
SECTION 2-SYSTEM DESCRIPTION
AND TROUBLESHOOTING TROUBLESHOOTING
Table 2-3. Troubleshooting Turn On, Unusual Shutdown, and Locked Up Front Panel Problems (1 of 2)
• If the +24V is present, check the A28J1 connection to the front panel casting. If this
connection is good, then there is an open in the cabling between the front panel casting
and the A 1 and A2 PCBs.
• If there is no +24V present at A22TP11, disconnect A28J3 and A28J1. If the +24V
appears, there is a short circuit in either the front panel casting PCBs or the 1o MHz
crystal oscillator.
• If the +24 V does not appear, the problem is with the Rear Panel line power transformer
(T1), A22VR1, or A28CR6-9.
Synthesizer does not When the LINE key is pressed, the STANDBY light should go off and the OPERATE light
power up, STANDBY should illuminate.
light is ON.
• If STANDBY goes off and the OPERATE light remains off, it indicates either that the
LINE switch is defective or that there is a short circuit on the +24V line following the
LINE switch.
• If the STANDBY light goes off and the OPERATE light illuminates as normal, you should
hear a click. This click means the A28K1 relay has energized. If A28K1 does not
energize, but the fan operates, then A28K1 is defective. If the fan does not operate,
the cabling from the front panel casting via A28J2 is most likely open.
Front panel LCDs Indicates one of the A25 power supply outputs is shorted to ground. The table below shows
and LEDs flash on the resistance to ground of A25 outputs with A25 installed. The cause of the short circuit
may be localized to the PCB or subsystem level by removing the PCBs until the short circuit
and off when LINE
goes away. (All readings taken between ground and the connector point on a 1 Kn scale.
is switched to Ohmmeter negative lead to ground, positive lead to test point.)
OPERATE.
Resistance
Connection .sQI1al toGround �
XA25P2-1 +5V 60Q Remove:A28J1, AB, A13, A15, A16,
A17, A23,A24, A28J19
XA25P2-29 JfJOV 14kn Remove:A22
XA25P2-25 -18V 3kn Remove:A22
XA25P2-23 +22V 143kn Remove:A18, A19, A20, A21,A22, A28J19, A2804
XA25P2-11 +18V 49on Remove:A22
XA25P2-15 -18V 3Bn Remove:A22
XA25P2-9 +9V 465n Remove:A6, A?, A 11, A12, A22
67XXBMM 2-29
SECTION 2·SYSTEM DESCRIPTION
TROUBLESHOOTING AND TROUBLESHOOTING
Table 2·3. Troubleshooting Turn On, Unusual Shutdown, and Locked Up Front Panel Problems (2 of2)
Synthesizer operates Indicates the 67XXB synthesizer has reached an excessive operating temperature.
for some time, then
shuts down •
If fan is still operating, clean air filter.
(OPERATE indicator
is on) . After a short •
If fan is not operating, the trouble could be A22VR1, the fan, or the fan circuitry. Refer
time, synthesizer to Section 2A-Power Supply for circuit descriptions, block diagrams, and schematics
to assist you in isolating the failure.
resumes normal
operation.
Front Panel Locks Up During normal operation when the synthesizer is turned on, the front panel LCD displays
or Unable to Control and LEDs will light in a random pattern for a few seconds and then blank while self test is
being performed. Upon completion of self test, the front panel will display the set-up that
Synthesizer via the
the synthesizer had when last powered down.
Front Panel
If the LCD numeric displays and the indicator LEDs never change from their initial random
pattern and/or if front panel control is lost, a problem in either the Digital Control subsystem
or the Operator 1/0 subsystem is indicated. Troubleshoot as follows:
During power up, monitor A28J1-3 and A28J1-4 (Mother board connector that connects to
the front panel casting) with an oscilloscope. You should observe a TIL serial data signal
on pin 3 and a TIL 400 kHz clock signal on pin 4 at intervals indicating that the front panel
is being written to by the AS Serial 1/0.
• If the data and clock signals are observed at A28J1 pins 3 and 4, then the malfunction
is most likely in the Front Panel A1 and A2 PCBs. Refer to Section 2C-Front Panel
for circuit descriptions, block diagrams, and schematics to assist you in isolating the
failure.
• If the data and clock signal are not observed at A28J1 pins 3 and 4, the problem lies
within the Digital Control Subsystem. Refer to Section 28-Digital Control for circiut
descriptions, block diagrams, and schematics to assist you in isolating the failure.
2-30 67XXBMM
SECTION 2-SYSTEM DEXCRIPTION
AND TROUBLESHOOTING ERROR CODES
E0-0 The microprocessor is unable to perform a self-test. This can be Refer to Section 2A-Power Supply
caused by either the DVM or the ±15V(G) supplies. This is a fatal f o r circuit descriptions, block
error, which means that normal operation is curtailed until the error diagrams, and schematics.
is corrected.
E0-1 The A17 Board is missing, or +1 OV Reference in A17 or A1 5 failed.
NOTE
E4-10 Phase-Lock Error - This test checks the A6 PCB for phase A3, A4, or A6 PCBs.
detector output. If this test passes, then the E4-13 test is run. H this
test fails, then the E4-11 and E4-12 tests are used to narrow the
problem area.
E4-11 Phase-Lock Negative Error - The 10 MHz reference for the A6 PCB Input Buffer or A 10 PCB
Coarse Loop Subsystem is missing. Reference Buffer.
E4-12 Phase-Lock Positive Error - The A6 Coarse Loop Divider PCB is A3 and A4 PCBs.
not receiving a signal from the A3 Coarse Loop Mixer PCB.
E4-13 VCO Tuning Voltage Error - The VCO tuning voltage is out of If the voltage value reveals that the
range indicating that the A4 Coarse Loop Oscillator needs to be sweep is at the end of its range
recalibrated. This is not a routine calibration. Contact the opposite from where it should be, the
WILTRON Customer Service Department at (408) 778-2000 for probable cause is the A4 PCB
assistance in this calibration. Tuning Amplifier.
NOTE
ES-0 1O MHz Crystal Oscillator Error - Test indicates whether the The 1O MHz Crystal Oscillator As-
1O MHz Crystal Oscillator oven is at operating temperature. If not, sembly.
the ES-series tests are bypassed until the Crystal Oscillator error
is corrected.
67XXB MM 2-31
SECTION 2-SYSTEM DESCRIPTION
ERROR CODES AND TROUBLESHOOT/NG
EB-10 Serial 1/0 Not Responding - Failure indicates that the AB Serial Refer to Section 2B-Digital Control
l/O PCB is not receiving information from the front panel. for c ircuit descriptions, block
diagrams, and schematics.
NOTE
E9-13 VCO Tuning Voltage Error - The VCO tuning voltage is out of Probable cause is the A9 PCB
range. Linearizer (Tuning Shaper) or
Shaper Amplifier.
2-32 67XXB MM
SECTION 2-SYSTEM DEXCR/PTION
AND TROUBLESHOOT/NG ERROR CODES
NOTE
E12-10 Phase Lock Error - The VIG Loop will not phase lock in any band. A 12, A16, A30 and/or A31 PCBs
If completed successfully, the E12-11 and E1 2-12 tests are (Probable cause is the Sampler of
bypassed. If only one oscillator is not locking, the FM-path error the A30 Sampler/IF Amplifier PCB.)
code for that oscillator is displayed.
E15-10 UNLEV ELED-Indicator-On Error - The front panel UNLEVELED A1SU41 or A1SU42
indicator is always on.
E15·11 UNLEVELED-Indicator-Off Error - The front panel UNLEVELED A 1SU12B, A15U41, or A 15U42
indicator will not come on.
E15-13 Phase Error, AM Peak Detector - The AM Peak Detector is A15U11B, A15U11C, A15U13B , or
inoperative. A15U1S
E15-14 Phase Error.AM Trough Detector - Failure indicates that the AM A1SU11A, A15U11 D, A1SU138, or
Trough Detector is inoperative. A15U1S
67XXB MM 2-33
SECTION 2-SYSTEM DESCRIPTION
ERROR CODES AND TROUBLESHOOT/NG
E15-23 Detector Path Error, Band O CW Either the Down Converter or the
Band 0 Preamplifier on the A1 5 PCB
is defective.
E15-24 Detector Path Error, Band 1-4 CW Either the Band 1-4 Level Detector
or Band i -4 Preamplifier on the A1 5
PCB is defective.
E15·25 Detector Path Error, Band 0 Sample/Hold - This test is bypassed This detector path, which is used
if the E15-23 test passes. d u r i n g p u l s e o p e r a t i o n s , is
defective.
E15-26 Detector Path Error, Band 1-4 Sample/Hold - This test is This detector path, which is used
bypassed if the E15-24 test passes. d u r i n g p u l s e o pe r a tio n s , i s
defective.
E15-30 Band O Pulse Error - This test is bypassed if the E 13-10 test Indicates that the A13 PCB pulse
passes. driver for Band 1, Band 1 Control
Modulator, or A 15 Sample/Hold
circu� is defective.
E15·31 Band 1-4 Pulse Error - This test is bypassed if the E13-10 test The A13 PCB pulse drivers, or the
passes. A 15 PCB Sample/Hold circuit is
defective.
2-34 67XXB MM
SECTION 2-SYSTEM DEXCRIPTION
AND TROUBLESHOOTING ERROR CODES
NOTE
E17-12 DVM Measurement Error, +20 Volt Range The 20V range of the D V M is
inoperative.
E17-13 DVM Measurement Error, 1 oo Volt Range The 1 OOV range of the DVM is
inoperative.
E17·22 DVM Error, Tune DAC -1 OV The Tune DAC +10V reference
supply or Tune DAC is defective.
67XXB MM 2-35
SECTION 2-SYSTEM DESCRIPTION
ERROR CODES AND TROUBLESHOOTING
E17-23 DVM Error, Tune DAG Sweep Linearity problem in the Tune DAG.
E17-24 DVM Error, Tune DAG Gain.. 4 The switch for gain=4 is defective:
A17U41A.
E17-30 Ramp Generator Error The integrator for the ramp gener
ator and its associated circuitry is not
operating properly.
E17-31 Sweep Time Error, Sweep Time DAC The DAG that controls the sweep
time is out of its specified limits.
E17-32 Retrace Time Error, Sweep Time DAG Error in retrace timing of the ramp.
E17-33 Range Error, Sweep Time Circuit Error in the > 1 second sweep-time
circuitry.
E17-40 Sweep Width DAC Error, OV S w e e p W i d t h D A G e r r o r at
maximum attenuation.
E17-41 Sweep Width DAC Error, Full-Scale, + 1OV Sweep Width DAG error at
full scale.
E17-42 Sweep Width DAG Error. -1 OV
E17-43 Sweep Width DAG Error, 1% Steps Sweep Width DAG linearity error.
E17-44 Sweep Width DAG Error, Gain 4 The Gain=4 switch is defective:
A17U36.
2-36 67XXB MM
SECTION 2·SYSTEM DEXCRIPTION
AND TROUBLESHOOTING ERROR CODES
NOTE
67XXBMM 2-37
SECTION 2-SYSTEM DESCRIPTION
ERROR CODES AND TROUBLESHOOTING
2-38 67XXB MM
SECTION 2·SYSTEM DEXCRIPTION
AND TROUBLESHOOTING ERROR CODES
E23-10 Non-volatile RAM for storing front panel setups has failed read- The front panel setups need to be
write testing. In addition, this error code may be generated by a reentered and stored in non-volatile
master reset of the 67XXB which overwrites all information stored RAM or A23 U25 needs to be
in the non-volatile RAM. replaced.
E23-21 1/0 Error - Indicates the 110 interrupt is inoperative. Replace A23U8.
67XXB MM 2-39
SECTION 2-SYSTEM DESCRIPTION
ERROR CODES AND TROUBLESHOOTING
Table 2-4. Summary ofError Codes with Probable Causes (10 of 10)
E29·11 V/GHz Slope Error The U13 V/GHz Slope DAG or Data
Latches US or U9.
2-40 67XXB MM
2A-POWER SUPPLY: A22, A25, A26, 2A-2 POWER SUPPLY ASSEMBLIES,
AND PART OF A28 PCBS OVERALL DESCRIPTION
�···��
Detailed Circuit Description
67XXB MM 2A-1
POWER SUPPLY ASSEMBLIES, DETAILED DESCRIPTION 2A POWER SUPPLY
2A-3 POWER SUPPLY ASSEMBLIES, 2A-3.2 A28 Motherboard PCB Power Supply
DETAILED DESCRIPTION Circuits, Detailed Circuit Description
During this description, refer to Figure 2A-1 and to The power supply circuits that are located on the
Figure 2A-12, which is a partial schematic of the A28 A28 Motherboard PCB are described below; refer to
Motherboard PCB (Sheet 1) . Figure 2A-12 during this description. (For further
information pertaining to the A28 Motherboard
PCB, refer to Section 2M-Motherboard/Interconnec
2A-3.1 AC Line and +24V Standby Power tion .)
Supply Circuits
2A-2 67XXB MM
2A POWER SUPPLY
I
PARTOF REAR PANEL j PARTOFA28 PCB
I
I
I
I
I
�-....,.. !>---D
! I
f:>----0
RECTIAER/
DOUBLER
! I
I
��p--o l
/ �,,_,...,..,.._�y i
I
24V BRIDGE
TR ANSFORMER RECTIAE
r;;·----
.PARTOF
!RF DECK
--·-·
I
j
04· I
' FAN
i70'C
oc
! THERMAL j FAN
j
SWITCH
CIRCUITS ..__-l--._-��4iil
! SWITCH .j
·
I I
' ! i
.J
100KHz -?j �------�1--
l_ __________
• Unregulated voltage
67XXBMM
POWER SUPPLY BLOCK DIAGRAM
I
I
I
I
I
I
I
I
+24V1 I
-------- ------------------------ ;_ :__ ==�! I
.
.
I.
����I !i_
.,
______________________________________ J
ASSEMBLY j
___ __ _i
2A-3/2A-4
2A POWER SUPPLY POWER SUPPLY ASSEMBLIES, DETAILED DESCRIPTION
2A-3.3 A25 Switching Power Supply PCB, voltage input and to the duty cycle of the output
Detailed Circuit Description waveform g e nerated by t h e pulse width
modulator circuit (explained below). This signal
During the following description, refer to the block
is the input to the driver transistors, Q4/Q5 that
diagram of the A25 Switching Power Supply PCB ,
control switching transistors Q6/Q7. The vol
Figure 2A-4. Refer also to the A25 PCB schematic
tages from these windings are rectified and
diagram, Figure 2A-8.
passed through inductors that function as in
tegrators/filters.
The A25 PCB contains the following circuits:
• ±165 Vdc Input Filter
SWITCHING
TRANSISTORS
PULSE WIDTH DRIVER COMPOSITE
+ 165V
JIE �
MODULATOR TRANSISTORS OUTPUT
n=--B>--
INPUT WAVEFORM
� � T1 �
+1 65V···· ···
OV ······
T1
........... .
······
tIL-B>--JI E-
·
OUTPUT
T1
-1 65 ·················· ···
V
� T1 � T1 =25-40% of T period
-165V
67XXB MM 2A-5
POWER SUPPLY ASSEMBLIES, DETAILED DESCRIPTION 2A POWER SUPPLY
The UF and DF outputs of U7 are combined at put is sensed by zener diodes CR2 and CR19 (via
the junction of R90, R91, and R85. When the Q12). Any overtemperature condition of the FET
PWM oscillator frequency is too high, the signal switching transistors is sensed by the circuit
consists primarily of a series of positive-going comprised of thermistor RTl, and transistors Ql
pulses. When it is too low, it consists primarily and Q2. This circuit switches state when an
of a series of negative-going pulses. The com overtemperature condition occurs.
bined UF/DF output signal is integrated and
then fed to the frequency determining network The inputs to the Shut Down Timer, U5, are the
of U4. This causes the PWM oscillator frequency common collector outputs of Ul, U2, Q3 and
to shift in the direction required to achieve phase Q12, which are part of the overvoltage and over
lock. current sense circuits described above. The heat
sensing switch, located on the microwave deck,
The U2 output of U7 is fed to the input of the is also connected to this line. If an overvoltage,
lock detector timer, U8, via the filter comprised overcurrent, or overtemperature condition is
of R93 and C67. When the PWM oscillator is sensed, this line goes low and causes U5 to
phase locked with the reference signal, the sig generate a pulse having a pulse width of ap
nal at this point is a static high. When not in proximately 1 second.
phase lock, the negative-going pulses, output by
U7, cause U8 to drive the L PS LOCK MON
The leading edge of the pulse from U5 causes the
output high (i.e., unlocked). This status line goes
Ve pin of Q4 to go to +12V and the INH pin to
to the DVM circuits located on the Al7 Analog
go low. This causes Q4 to turn off, which shuts
Instruction PCB.
down the FET switching transistors. The lagging
edge of the one second pulse causes the INH pin
d. Loop Control Amplifier of Q4 to return high, which causes the switching
The +5V D and +5V SENSE COMP outputs from power supply to soft-start.
the +5V rectifier/filter circuit form a composite
input to the Loop Control Amplifier, U3. (The If the overvoltage, overcurrent, or overtempera
+5V SENSE COMP signal contains the high fre ture condition that started the above cycle is still
quency components of the feedback information.) present, U5 generates another pulse and again
The other input to U3 is a +5V reference voltage causes the supply to shut down. This cycling
derived from the +lOV output of VR2. The out operation continues until the overvoltage or
put of U3 is the 0 to 12V control signal (Ve) to overcurrent condition is corrected or the unit is
U4. The action of U3 causes U4 to output the put in the (LINE) STANDBY condition.
correct duty cycle that maintains the +5V D out
put at precisely +5V.
The input to the soft start circuit is +12 Vdc from
the +12V regulator, VRl. At the instant the LINE
e. Shut Down Timer/Soft Start Circuits
switch is depressed, +12V is applied to the Ve
These circuits shut down the switching power pin of Q4 through C23 (via R51 and CR12, refer
supply when overvoltage, overcurrent, or over to Figure 2A-8, sheet 1). With the Ve pin at
temperature conditions occur. They also cause + 12V, the duty cycle of the PWM output pulse
the rectified outputs from the switching power train is at its minimum, thus causing the rec
supply to come on line at their minimum voltage tified outputs of the switching power supply to
levels (soft start). be at their minimum levels. As C23 charges, the
subsequently decreasing voltage at the Ve pin
Overcurrent conditions in the switching power causes the duty cycle of the output pulse train to
supply circuits are sensed by photo-couplers, Ul increase. This, in turn, causes the +5 VD supply
and U2. Zener diode CR8 is used to sense any output voltage to rise until it is regulated in the
overvoltage condition on the +5 VD output (via normal manner by the action of the loop control
Q3). Any overvoltage condition on the +22V out- amplifier.
2A-6 67XXB MM
2A POWER SUPPLY POWER SUPPLY ASSEMBLIES, DETAILED DESCRIPTION
f. Rectifier/Filter Circuits
Table 2A·2. A25 PCB Output Vol tages Distribution
___., T1 I� T1 j+
__fl__fl..= Vavg -------
av---------
Vavg
��
---
-- ---:-1 -y t
PARTOFT3
Figure 2A-3. Typical A25 PCB Rec tifier/Fil ter Circ uit
67XXBMM 2A-7
POWER SUPPLY ASSEMBLIES, TROUBLESHOOTING 2A POWER SUPPLY
configured as a negative series regulator, with the the ±15V A, ±15V G, ±15V LP, and ±15V FM power
-lOV output at the GND terminal. supply outputs. Regulators VR3-VR10 are fixed out
put integrated circuit types; see Fi gure 2A-6,
Operational amplifier UlB is the control amplifier Sheets 1 and 2. These circuits have built-in current
for the -18V supply. The ratio of resistors R12 and limiting and current foldback that limit the output
R13 sets the output voltage of this supply at -18V. current to approximately l. 5A.
Transistor Q3 functions as a level shifter that drives
Ql, which is the series pass transistor for the -18V e. Power Supply Monitor Circuit
supply (Q3 is required to prevent the output of UlB
All of the power supply voltages, except the +5V and
from approaching -18V).
+22V, are summed by operational amplifiers U2A
and U2B to produce the PS MON! and PS MON2
Transis tor Q2, in conjunction with R6 and R7,
outputs. These outputs are approximately OV when
provides current limiting for this circuit. Transistor
all of the power supply voltages are at their nominal
Q8 provides foldback limiting. During current limit
levels. If one of the power supplies has no output,
ing conditions, if the output voltage goes above ap
proximately -12V, QB conducts. This causes Q2 to
the effective weighting value of the input resistor
2A-8 67XXB MM
2A POWER SUPPLY
P1
+12V
FROM MICROWAVE
DECK OVERTEMP
SWITCH I SHUTDOWN
SENSE
I CIRCUITS
01-03, 012
I +12V
+5 VD SENSE I
TR
(FROM P2 CONNECTOR) I POWER SUPPLY as
I OVERTEMP
SHUTDOWN
TIMER OU SOFT START
I SENSE
us CAPACITOR
I +1 v
I
I REFERENCE
I VR2 VOLTAGE
I LOOP
I CONTROL
AMPLIAER
I
I
I PULSE
I WIDTH
I MODULATOR
U4
I
I
------
,_ _
_
_ _ ____
-pt Rt
100 KHz
I REPETmoN RATE
SYNC CIRCUITS
(FROM A11 PCB) I U6,U7
I 1-------,"'1 TR
+24V G '>!-------, UNLOCK
DETECT
ou·
(FROM A2S PCB) I TIMER
us
I
+12V
I VR1
LPSLOCKMON
(TO A29PCB)
�' ______:�-------------------------�
ALTER
+1ssv>J-l---------r-1�--+-�I'---
- �• +165V
:
I ------ --,
·
FROM A2S
LINE RECTIAER : I
I II
-1ssv>1, nl___ I
.__,:
CIRCUIT
, __ -�· -165V
-
I l_ ______ ....J
67XXBMM
A25 SWITCHING POWER SUPPLY BLOCK DIAGRAM
T]
•SY _IT.SYD
RECTIAER
I
TO ALL
SYTHESIZER
OVER CURRENT
I
SENSE I
I
I +22V
1---�To A18-A21
VIG DRIVER PCB
DRIVER
TR ANSISTORS
I---,-:�> +18V G*
I
·--+-I>_,. -18V G*
I
I
I
-21V I
----RECTIAER• --+-J>-+ ·21V*
I
I
I
I
-SOV I> -sov•
OVERCURRENT RECTIAER
SENSE I
·165V I
I
I
+9V
I
+9V LP
t----+� TO FINE LOOP,
RECTIAER
COURSE LOOP, ETC.
2A-9
TP1·13
2 4 6 8 10 12
1 3 5 7 9 11 13
00 °
A22 0
°
0 0
0
0
0
J1 J1
0
PZ.
@ @ @
(Front) 1 P2 49
� � � u � u u u �
�
u [) � � u � u u � u
RE
VII
r·1
:.._, LJ �
lJ � u [I
TEST POINTS
TP1 GND G
TP2 +22V
TP3 -15VFM A22
TP4 +15VFM REGULATOR
TPS -15VG INTERFACE
TP6 + 15VG (A22A1, A22A2)
TP7 -15VA
TPS +15VA
TP9 -15VLP
TP10 +15VLP
TP11 +24V1
TP12 -18V --- - --
TP13 -43V
HEAT SINK
ASSEMBLY
SIDE
VIEW
IEAR
r1Ew Thermal
Compound [ I I
� �\1 y
,
, A22A1
i
1 1; r
! standoff
r1t/ 1 �
l1I.·
/ ,
;; \ '
,�
·
- I I
Insulator
Transistor Insulator
2A-10 67XXBMM
0 1 2 3 4
�=�::;:;::.;;:;;.;.:;:.:.;.: ::;.:::::::
;
:- ;: «·:·":·::::»;;:;:: :;xi:11
::-,;.: ::::::::::�.;:;;;:;::;;;r,�w.::i:9-:::i:& : ;;::: ;:; q;
\!
: :
ili
P10 ,0..22.AI
A
+30V
I
pz_
I
:o I
-<'..'1
ii II..\
·.;R1 ,_o_u_T_____, ,, Pl
Zr
+ 24V SUPPLY
2 _H317
CRl<O
/l..O'J 31<0
�\
Sl'-f
ii
T �O/
:·:-: :·:-:·:·:·�:::::::=:=:·:·:·:·:·:·:.:-: ·:·=--·-: ;.:7:{.}z�;:·:·:·:·:·:·:·:·:·:·:-:·:·: :·:·:·:·:-:-:-:-:-:-:-:-:-:-:-:.,.:-.:
·
-IRv su:::r=_(
�_lc.s
-4.1
IW
B
l/R2.
35V
RIO OUT AD581
RIZ.
2. 1'51< 5.111<.
C7
Q:,
·01 G\JD
i'l\PSA
I"'
Gl8
\..\?$A"l2.
c
R\4
p3.t;,
� K
"'A
l.. �>pl/���-+���-4---<����-..i.--��_._��,i._��-
!f=·:·:-·: :-::- ·:-:-:w�:- - :-:-::x-:.;:::<
:
-
: =· -»� : :·
1<40 2.15
.Ol
RS Rl3 C8
::.R\4
75\<, 4.12.K
-" "''t i
l>l444�
- 2. IV
.... .p-��i
39
....
40 . ..3:i.- ::'<l<d�q �,,
:1
- Zl v � ��� -....+��R�/\r
" ... CR2
I ,;
I P/O A..2.ZAI
47 .s \,., ,.,.,.,.".,.,.,.,.,,,.,.,,,,,,"·"·'·"''"''"'" R "l 11-.141431>' T
-SOY
48
D -SOY
1BV G
+ 1evc:=.
+ .... ave,
+t8VC.
c�G:>
./R3
�
<:>'t-4-
t- IS'IG
Pl
I >J
Pl
_\..\�40 OUT 14
...i'·'-
11
IS
t- ISVG
Ct�l
12. � >--.-��--<t-
+ ��....�
c13 . ���-
1
T-15
f"
I
'50.J
'ZSV
I GI-JD '-----+ >'3
I
E I
- 18\IG
-z� /R4
11-1 our
-06/G
-Z.G:>
=>1 \>\
-18V6
�
' l.µ320T
C..14
'301/
8
\- 1'5
+iIC.IS2..7..
iz.z.
�
) Go 2.'0V
-+
Gl.lD
18V<:i
C�7
·JRS Sl-4
11-.l OUT
"I
F
... ZI Lµ340
T-IS
*'?
2Z
C•Co
CR�
-
SI-'t
P1 VR(O
OUT
f;::; >-l'l�-----41
11 ,,___,._
, 1_1J__, ' µ 3 1.0
0
�i ��;
c1e 1e, C\9
G
NOIES:
I.
RESISTANCES ARE
UNLESS OTHER"m:
CAPACITANCES /114
INDUCTANCES ARE
SHEETS OF llilS S
CONNECTIONS BEl
SHEET NUMBER Al
APPEAR INSIDE Tt
DESTINATION GAIC
+2"2V
H
SCHEMATIC SET I.
3. GROUND SYMBOU
CHASSIS GROUll
ISOLATED GROUll
67XXB MM
5 6 7 8 9
P2
-43V SUPPLY
-,'.. :J
43
r.,,
44
RIS R21 RZ2
IK
1.1<.'H-\
+ CIO +
µp5v04
04 C1I
R23 10 10
S. llK G:>3V <CBV
PIO t>,2.ZA\
R2.0
7.87K
IS i
+15VA
l9 2 I
,1
I
I
+ISV�
+15VA
6ND G
?f
6ND G
�
ct �e
19
- \",VA
I
�r-4- LS I
- 15VA
-1evc..
1 I
+
�
,5\/LP
.,. 1•:>'/L?
+ 15VLP
II I
GND G
9
GND G
� ',�
- 5\/LP
- 5-,
. �p
- 15 VLP
filID + 18V6
lllSE SPECIFIED, 4... TEST POINTS ARE DENOTED A S : QJ
Rf I N OHMS (0),
!ZiJ!>-1'OV6
5. TROUBLESHOOT I NG V OLTAGE AND POWER
MIE IN llK.ROFAAADS (µF),
IRE I N MICAOHENAIES (µH). LEVELS I NDICATED IN B OXES ARE lYl'tCAL
OR NOMINAL LEVELS.
llllCATE MATCHING
6. SUBASSEMBLY BORDERS ARE DENOTED 'LAST USED/NOT USED C OMPONEKTS ARE:
::::·:�:·:•:;;;:::i:::::--x-::m:�;: REFERENCE DESIGNATORS
! SCHEMATIC. THE
!ETWEEN MULTIPLE
AS:
01
NOT USED
Ill: rf7
UNDS=wwwww U2
2A-11/2A-12
0 1 2 3 4
P,2.
+9 v LP �-------------
7 ----------R_:_::_S2 � v.�9_o_.9_K _ �.-----�c�z_o__�
0.1
A +IS V LP 1g�0 >-
•
----R�Z:C:J( 49. '! K
R27
-,o;{-;: · ----------------------_::_:
r;;, 5.,_ !
- IS'¥ LP , 4i'. 3 K 10 K
- <t3 ·/ , �
�
'OOS >-------------------.::
---..::--!
- 18 v · ---- ------------------=-"'2\9 y,,,2.,_
--:;:c ,>-
+24 VO "13
'.:e ;>______ ______ ____________.::: 0 115 K
1 ·,
Viv
B
t-15 VA ·, �i_ >----- ----
c · ; . : ::
.;.;.;.·.··: :·:·. .; ;: .� : ��·�::;.;:::�;:::::;:�
. ·
· :::::;:·:·:···:-:· .-.·.- ·.·.·.·.·. .·.··:·:· :·:·:<·:·
�
:-:.:-:-;.:-:· :-��
:�: !\
A22A2.
c0R I
�
t IB V G !I 2·:;>>-<r----�--<1>---�2.0!!'<,� ,, � �IJ4n
nur
t c 22 T. ,5
27
D +ISVG c...2 ::,
2 z
I
\\I
=�v
Z5V
fl
iN ·"'dT
·IP.8
-1.<1 v G [I'_��- ,...
_ .. __-J-_
tit ll Livi 320
_
T.15
.o.�o
E
C..."2.'l
Z.2.
zsv
1
f,u C.Z.3
�! 5C
J
67XXB MM
6 6 7 8 9
PZ
I
I
• � 14'> p s MON I
I
I
I
R-:.2. b4. "! K C21 I
I
0.1
P,'33 '-4. 'J K I
R�E'J I
R34 45. .3k'.
IOK I
?.::0.S• 45.3K I
I
\:2.3" 121 K 7 5o PS MDN 2
R'37. 121 K
�18'4G-
CRIO
SI-4-
·
+15 VG
bN I) &
CRI\ -15 VG
51-4
C. RI?.
51.4
+IS VFM
3
� I
I
7
51-4
-8V G.
2A-13
TEST POINTS
. TP1 GND G
TP2
�� �
V
TP3 , IN 1 (OSC SIG)
TP4 PR IMARY DRIVE
TP5 PRIMARY+ 165V
TP6 PRIMARY -165V
TP1·6
(Front) P1 (Front) 1
A25
SWITCHING
POWER SUPPLY
--- - --
L5
TOP
C45
8 ([)
LQ
BOT L3
+
___.,,-0 3
29
�5P2) 30
2A-14 67XXBMM
0 1 2 3 4
R3
21
.5
+165V 22
R4 TP5 2W
54'l
A 02
6. 19K C6 C61 + CB
TP1
02 Tl 0 01 0.01 0.02 12
3KV 05
350V
2 04
17
-
6mH
GND G �1�8�� -+
+
29
30 C5 C60 C10
B 0.01 0.02 12
Rl 3KV 350V
01
6. 19K
L13 R7
-165V
54'l TP6
RB
P/0 A28
1
I( CR10 .5 , 2W
I
A2BJ20 16 PSO
c +22V
+12V
0
rn
n
""
�
C3
+12
D R45
1. 47K
�
Cl . 01
�
1N751A, 5.1V
SWITCHER LP IN
30PF C
SWITCHER LP OUT
VR2 1N4446
A0581 R54 °'::
+12V IN OUTo--.-�v1-
vv----.�'V'l'v--.--"l.l\A---! -��� CR13 !OOK'
CD GND +12V
E CD <J--+----'
9
GND D �1�0'--'>-<--+----..--_._---<>-..-�
TP3
TP2
�o
C27 C28
+5V
+
20K
RB1
1K
NOTES: 14
(i vcc
u 1'
A25 SWITCHING POWER SUPPLY SCHEMATIC NOTES: 01
R
UNLESS OTHERWISE SPECIFIED. U7
03 01•
RESISTANCES ARE IN OHMS. CAPACITANCES ARE IN v
U2•
t.1ICROFARAOS, ANO INDUCTANCES ARE IN MICROHENRIES 04
REF DESIGNATIONS PU 02•
(2/B9I MATCHING CONNECTIONS FOR SIGNAL FLAGS ARE LAST USED NOT USED 11 UF'
us OF·
PD
LOCATED BY SHEET NUMBER AND GRID COORDINATE Q6, Q7, Q10. Ql 1
Q12 CR17, lB. 20, 21 09
NC A OUT,
DENOTES TEST POINT CR34 C4, C7,
C70 C51, 62. 63 GNO
DENOTES +5V RETURN
R94 R2G 07
-
P2 R67, 6B. 69, 75 MC4
DENOTES ANALOG GROUND 1
-vCD DENOTES RELATIVE VOLTAGES
T3
L17
R76, 77, 78, 79
Li5
DENOTES ANALOG GROUND 2 TP6
-V � DENOTES RELATIVE VOLTAGES VR2
RT1
DENOTES OFF BOARD SUBASSEMBLY
T2 R28
1K
1N4446 R26
1K
2
+12Y CD
+ C1B + �C17
4.7
10
1
3
R33
261 1N4446
R29
1K
PRIMARY
DRIVE
PRIMARY
RETURN
+12v CD
12v CD +12Y<>-�o-----,
CD
�"'
14.7K
02
TR
RST
vcc
OB
OUT
�
03
1
+12YCD
1
CY U5
THR 7555 + 23
R51
?
DIS 147
GND
47
01 CR32
K�
SHUT DOWN 1N4446
CR34
7 CR12
+ C24 1N4446 1N4446
2. 2
+12Y
CD
+5Y
01
1+
+5Y
RBS 1-
3. 32K
05
�
+5Y 06
C16
OOOPF
o
R91
590 R83 2+
R90 ..-·vv,,----.
1.47K
1K + C14
fi
RB4
133
Tc +5Y Pl
w
OB
1
-? L l"S I- oc>< MON
165K YCC
03
OUT �=----------------:--
5
12V
�---::-1CY UB TEST
!OOOPF f---+--+--__,_-;;-:;-lTHR 7555
DIS
:4044
C67
I GND
2A-15/2A-16
0 1 2 3 4
- - .
1
3 A56
A 10
CR16
1N5360
25V
R57
10
B
L9
3 4
282
R71
61.9
c C53
CR29
L5
108
DRIVE
D PRIMARY
PRIMARY
RETURN
L7
3 4
740
E L?.
CA24
2 2
MR822 740
10T R65
121
CR25
7T
MR822
� 001
F 14
9 L3
_ - - - - -
CA26
3 4
7T
282
MR822
R64
61. 9
�
10T
CR27
001
G MR822
L11
MR822
17 2
CR30 168
4T R59
24.9
18
�
C35
001
H
4T
MR822
19
�
CR31
67XXB MM
5 6 7 8 9
L1 L4
2 ------
2
17.6 17.6 +5VD
R58
402
GND D
L16 L17 C31
plQD +5V COMP
fYY'
1.0mH ill64 L65
11 0. 1 SENSE
�,, �40pF
}"
240pf
0
L10 +22V
3 ------
4
+ C54 62 + C56 C58
7
50V �o63V � 1
� 0
~
1 GND G
2
L6
I
I
------
2
50V
47 19.6 + C40 +18V G
C41 R63
C38 � �O 63V � 1 20K
i
47 C42 -18VG
50V
¥
C39 .1
3
LB
----- -
4
�
2
ryy-,
150:2I
�
C45 +
353 150� I
C46 ¥
L5 2
.1
�
30
I
-sov
47 C49
150V
�
C47 +
� .1
L12 9
5 ------
6 +=
10
yy +9V LP
+Ji57
ryy-,
-Ji5550V
:¥ 168 L59
47
:J;
0
63V
.1
� Figure 2A-8. A25 Switching Power Supply PCB
Schematic Diagram (Sheet 2 of 2)
6700-D-31725-1 (Rev. F)
2A-17
A26 LINE FILTER PCB PARTS LOCATOR DIAGRAM 2A POWER SUPPLY
E3 E2 n -1 S1 3· F2 2 F1
0. 0 0 D 0
E1 T1-3 Tl-2 S1 2 S1- 1 F2 1
D o o
·C1 L1
C2
RV2
2A-18 67XXBMM
0 1 2 3 4
PART OF R E A R. PA N E L
A
R. T I
F l F" I
C:\
I A 5 2- '+A \ I O V '::J
2.A 2 2-0 V
F" L I
(
5 .n. , C O L D
L L SB
I 0
<
INPUT
P fl \/, F. R. N ""
E. 0
B
\ -:-
LI
�
vv
RT 2.
S .n,C O L D
,...__
51- 1
'
5 1 - 2.
SI
,
1 1 o v/
/22.()V
Sl-3
Tl- I
F
T J -2
.
T J -3
.,
67XXB MM
5 6 7 8 9
E. 1
. TQ A 2 B :r z t. - 3
_,_
C. I l,.) RV I
-- l uF I/ I SOV
't O O V ( RM S
E 2.
T O A 2 8 J" 2 b - I
--- c 2. V R V 2.
-- l uF v ISOV
'f O O V ( RMS
E3
,. T O A 2. B :f 2 E. - �
TO f\2 8 :f 2. 6 - 7
T O A '2. B J"2 b - b
2A-19
A28 MOTHERBOARD
(As viewed from top of instrum ent)
..
..
.. .
..
..
..
..
cJO
«
..
..
x
..
.
..
J2 i ::
.
-- i-....
- - � I ..
--
__
r9·� : ••
•
'----'
• 1-:-;t
• • i ::
• • I ::
• cl:
·�
04
·-
• '=
·-
«
..
..
�
i .:
.
•'>< •x :: 1
DO
• • .. ..
• •
.. aa ..
• • :: I
.. ..
.. ,
..
U1 ·.£)
• •
..
• •
..
« « ..
«
• • • • x
N
.. ..
x
• • • •
"
N
..
..
• <T • a> «
.. ..
•« x
..
;:;: :;;:
. "' . " ..
ox
.. ..
=� • ox
. . .. ..
• • • •
"' .. ..
• a.
CJ
..
• • • •
. '" DO
l
.. ..
• o ·-" • • •
..
;;:
..
• • • •
.
o -< 0/
><
..
- - -n-• ,.---... ..
- - - ,-. 1 .. ..
•
•
..
J5-u"
..
.. .. ..
- - ...r.....o
- - ... 1-4 .. .. ..
..
- - i_J-11 ..
J7 .
.. ..
--�
-<1-'! 0
"" a>
N
"'
N
.. .
J61.J «
-- .--
«
..
«
..
«
.. ..
>(
�
x
..
- - ---, �
.. x .. x
"" .. ..
Jff
u .. ..
.. ..
..
. .. ..
Jg _
..
• • • _,..
• • •
• • •
• •o
o <-1
• tr> • <t • :;(°
. .....
<(_
• x: • >( • «
• .x J19
• • . "' • J14 • • • • • • il lil l l l il
• • _!_I
• •
•
•
D D l!
' 11 1 1 1
I I I _!__! � � I_!_ l
• • • �- - - :r
J3 J4
_.,!�
- T.- r
1 1 ' ··
••
••
..
••
1
••
..
NOTES:
1 . Filtercons are designated as : Fan Power
••••••••• • Supply Components
Each signal path connection (As viewed from
has (typically) 1 500 pf capacitance bottom of instrument)
between it and chassis ground.
2. J1 -9, J1 4, J 1 9, J23-25, and J27 are
m ou nted on the bottom side of the A28 PCB.
A28 MOTHERBOARD PCB PARTS LOCATOR DIAGRAM 2A POWER SUPPLY
A28
MOTHERBOARD
¢--===-2i (Bottom Side)
1:::::::::11
J25
.. J26
..
.. • • ••••• I
.. I•
..
..
.. � F LI
:: �
..
•• • a• • •
..
.. <(
>( Kl
.. ::
.. •• •
..
..
..
.. • •• • •
..
•
v� � �
..
..
..
• •
..
..
�c;:;,� tti�::
.. ..:
•• N
••
:: <(
)(
..
..
..
..
')�·1R1 2
..:: , · �, a: .... _____,.. cs -�:;
••
:: �
• •
�
c: .....
/'
e
+ 04
R9
:: �
•• I
:: )( '+ • .
�
\
N 8
•
•• / �RB
,_ _,/
J23
2A-20 67XXB MM
0 1 2 3 4
A
Fl L I NE F I LTER A28J26
I
) 3I �
FU 4 A 58,
2A 5 8 ,
l lOV
fr
220V V
R
I NPUT . c;, o v
-v
�
/
PMS
POWE�
1 .. f
� av �
...... .
� r:i I
� QC>V
B , 1
�
) I
R: T 1
l' .O. , c:..o�
) I I
I
I
c
SI
I
1 1ov
)6 I
220V
CRI
MAB!
D
T l -2
P/0
REAR PANEL
1 I
& A26
---
E +24V G 2/A9 �-
( i=Rc::>,.,..., L- 1 N £ -.W ti?=.M )
::
F
::11 � I
� :::
p /Q A 2 2 A 1 @ I
�
A28XA22 A22P2 A22PI A22P2
'
A22PI ·
A2BXA22
•
;
: ·.\.•, �� 5
I I
1\.;:l.:. s
1
I
1 29 21
I I • I
V ·· : R
30 I
' CR9
..
<>- ---.---"-<. !: I I
2
F�e8�l
;. :!
+
1 30
•• 28 6 6
I I
<........ . . .J h...""
·"' ...····"" . .....
, ,,·,•, , ,N. .'• • .•.•.•.•.••
. .•,,·•,.... ,N.,,•,·,·,•,•)
··'""
· ···
··
""""
· """" ""
· ·
"""" "'
....
...
.......
:=�.•. ,· •,, ,
FAN D R I VER
1. .
l- �
I NPUT
Kl
. ...·.·.·•·•······· ··········
A C L I NE
POWER
RELAY
L I NE SW I TCH. FAN
ANO I N TERNAL 10 MHz
H
OSC I LLATOR DE T A I L
67XXBMM
5 6 7 8 9
CR•
RI
FL !
+ 165V
2. SIGllAL fl.AGS INDICATE 11.t.TaftllG
COllNEC110llS llETWUN llULTPl.E
SHEE'1S Of THIS 9CHEMATIC. 111E
SHEET NUlll!ll AND SOUllCE Oii
OESTWIATION GAii COOlTES
APPEAR INSIDE 111E FLAG:
lDINA
I2183 )
I IOOK 3. GROUND SYlllOl.S USED ON THIS ASSElBl LY
C3
C2 MR82•
4c r
�
r
0
g
CHASSIS GllOUlll:
ISOLA TED GllOUNDS:
I
4. SUBASSEllY
ll. llOllD£llS ARl DENO TED
!OOK
C•
AS:
R2
I 850
I
5. STATIC 9EH8l11YE COllPOllEN1I USED II
THIS ASSEIB.Y INCi.i.KiE:
-165V
4c +5V Q1,VR1
I. LAST USEMIOT USED COllPONENTS ARE:
2/60
Cl NONE
LINE TRISGER
FL1
CR12
m
R7
15K
Kl
M
+I Q4
2N3111l•
C7 CRl2
IN•••6
R12
1112
CR7
RV2
MR852
XA17
-<
�
2 60 +30V
I
2
+ I
C6 I
� P/0
REAR PANEL
...·.·""
.... ....
.. ..... . ""
······· ""
""'' ....."'
·.·.·"' . . .., '"""·>
·"'"'""
" ="""" P/0 A 1 F R ON T PANEL
:.,... . =
.,1'-" � .
�Y+•---� I STCllYI
STAIClll
I
A28JI A2PI A2ul ASP!
- - - �
1� ( i' ( 9 1 + 2•V I I 'l
,I :: I I
- A28J3
I
) i. )
9�
:
:
�
>--�--<
f.i. I ;f; I
6) 6
052
�
P/0 A2
�TERNAL
F RONT
D MHz
PANEL
SC P/ 0
CONTROL
CHASS I S
OSI
::-
..•.
- •2&13
•IPI
I
A28J2 A2P2 A2Jl
I
I +2•V6 I 5
I I
I •
( ( • 5 1
Figure 2A-12. A28 Motherboard PCB
) . )
I I
;f; Schematic Diagram (Partial)
6700-D-31828-3 (Rev. B)
2A-2 1J2A-22
28-DIGITAL CONTROL 2B-2 DIGITAL CONTROL ASSEMBLIES,
AS, A23, and A24 PCBs OVERALL DESCRIPTION
Table 2B-l. Digital Control Service Information controls all of the main synthesizer functions, either
directly or indirectly. The microprocessor on the A24
Documentation Reference Page
PCB, and other control circuits located throughout
.J J _._. the synthesizer, control specific functions that are
r r
""""""'"""·"'-"'"•""
"'"'"'-� '""°•"•'"•"•"•"" .w.w..
• w.,. - ·.
• . •. . • ·w
• . . . ·.•.-.w.w.·
.· • .w .m· ..
.m"'._._
OVERALL ASSEMBLY LEVEL under the overall control of the A23 PCB main
28-2 28-1
.................................................................... ·.. ····························· ····················
PCB LEVEL
.� ..?.�:.�.w. . . ?.�:.�.......
i
. .2: .. ... .. . . ..
General Circuit Description Para. 28-2 28-1 an S-bit data bus and a 3-bit PCB address bus. In
Detailed Circuit Description Para. 28-5 28-8 addition, there is one (or more) dedicated address
Block Diagram Fig. 28-4 28-1 1 lines from the A23 PCB to each of these PCBs
Parts Locator Diagram Fig. 28-5 28-12 (LPAlO, LPAll and LPA12-LPA22).
Schematic (Sheet 1 of 1) Fig. 28-6 28-13
67XXB MM 2B-1
A23 MICROPROCESSOR PCB, DETAILED DESCRIPTION 28 DIGrrAL CONTROL
sends interrupts and data to the A23 Microprocessor 2B-3.2 A23 PCB Memory
PCB, as required. It also transmits data from the
A23 PCB to the GPIB bus under control of the (A23) The A23 PCB memory is structured as follows.
main microprocessor. • 136 Kbyte of EPROM that is used to store the
main operating program of the synthesizer (i.e.,
The A23 PCB communicates with the A24 PCB in synthesizer firmware).
the n o r m a l manner v i a the ( p a r a l l e l ) main • 16 Kbyte of EEPROM (expandable to 64 K) that
microprocessor data bus. For quick response to ex is used to store calibration data. This EEPROM
ternal GPIB commands, the A24 GPIB PCB inter is electrically erasable and is programmed by the
faces with the A23 PCB using interrupts. When a main microprocessor during calibration. The
(external) GPIB controller sends a command to the reprogramming is enabled by jumper P2 (see note
synthesizer, the A24 PCB decodes the command and below).
sends an interrupt to the main microprocessor. This
• 8 Kbyte of non-volatile RAM that is used to store
interrupt has the highest priority of all main proces
front panel setups in the power-off condition. The
sor interrupts. When it is received, the main
battery for this RAM is part of the integrated
microprocessor processes the command from the
circuit structure of these chips and requires no
GPIB and performs the required task.
external charging circuitry.
• 16 Kbyte of general purpose scratch-pad RAM .
NOTE
DETAILED DESCRIPTION
Refer to the A23 PCB block diagram (Figure 2B-2) Jumper P2 must be in the NORMAL posi
and to the A23 PCB schematic diagram (Figure tion for normal operation. (Jumper P2 is
2B-6) during the following description . placed in the CAL position to allow data
to be written into the EEPROMs during
calibration of the synthesizer; refer to the
2B-3.1 Microprocessor Circuits 67XXB Test and Calibration Manual for
more information.)
The synthesizer main microprocessor, A23U9 is an
8088 16-bit microprocessor that operates at a 5 MHz
clock rate. Clock chip Ul, in conjunction with the
2B-3.3 PCB Address Bus Circuits
15 MHz crystal Yl, generates the 5 MHz clock sig
nal for U9. Timer U32 provides the power-up reset These circuits address all of the circuit functions
function for the microprocessor circuit. Flip-flops throughout the synthesizer. As shown in Figure
U2A and U2B generate two wait s t ates 2B-2, the internal address bus goes to the U14 port
(total "" 400 ns) whenever U9 addresses circuits lo latch. The Qo-Qa outputs of U14 are the PCB ad
cated on any other PCB. dress bus lines, PAO-PA3. (Note: PA3 is not present
ly used.) The Q4-Q7 outputs are decoded by U18 and
Both address and data information are multiplexed U19 to produce the dedicated address lines L PAlO,
on the U9 microprocessor bus. Buffer latches UlO L PAU and L PA12-L PA22. These dedicated ad
and U11 store address information from the dress lines are used in conjunction with the PCB
microprocessor bus. The UlO/Ull outputs, in con address lines PAO-PA2 to select specific circuit func
junction with the AD9 and A10-A15 outputs of U9, tions located on the AB, A15, Al6, Al 7, A24 and A29
produce the 19-bit internal address bus. This bus is PCBs.
used to address all memory locations and other con
troller functions on the A23 PCB. (It also contains
2B-3.4 Main Microprocessor Data Bus
the information to address all of the other PCBs
see below.) Data from the memory circuits are placed onto the
8-bit internal data bus, ID BUS, under control of the
NOTE main microprocessor. This bus goes to various A23
Switch SW! must be in the NORM posi controller circuits and to buffer-latch U16. The out
tion for normal operation of the syn puts of U16 are the DO-D7 lines of the (external)
thesizer. (Placing SW! in the SERV posi main microprocessor bus that transfers data to/from
tion will cause U9 to become inoperative.) the AS, A15, A16, Al 7, A24 and A29 PCBs.
2B-2 67XXB MM
2B DIGITAL CONTROL DIGITAL CONTROL SUBSYSTEM BLOCK DIAGRAM
8-BIT MAIN
MIC ROPROCESSOR DEDICATED ADDRESS
DATA BUS DO·D7 LINES LPA 15·LPA22
!j .J . . . . . . . . . . . . .;:;
. . REAR PANEL
..... ,, ,.,,,. P
G lt}· �8 �i�• �� ��1i������ RFACE
'-
tc:::: &.......---"""
rp:=:
LPA17
FUPC �
16
r- D..:..:
.__---=:
W E
: :..= IN
:..: L=L-".:... T
=----------�
I
L--. -----
�L:.;.:.:·:·:·t:.;.;.;.;.;.:.;·:·:·:·:·:·:·:·:·:·:·:�}�::::-:-.
____.......
LPA22
\
.
lr--- SERIAL 1/0 & CONTROL BUS
KBDINT
67XXBMM 2B-3
A24 GPIB PCB, DETAILED DESCRIPTION 28 DIGITAL CONTROL
Data from the A24 GPIB PCB, the AS Serial VO periods are used to trigger events (such as the
PCB, or the DVM circuits on the Al 7 PCB are sent microprocessor housekeeping routine) and to pro
to the A23 PCB via the main microprocessor data vide time for the phase-lock loops to achieve lock.
bus. This data is received by tri-state buffer Ul7 and During these waits, the microprocessor does other
transferred to U9 via the internal data bus. (non-related) tasks. At the end of a wait period, U7
sends an interrupt to the microprocessor via US; the
The inputs to tri-state buffer Ul5 form a start up microprocessor then services the next (related) task.
instruction for the main microprocessor. When the
synthesizer is turned on, this instruction is trans NOTE
ferred via Ul5, Ul7 and jumper block Jl to the U9 The microprocessor housekeeping routine
microprocessor bus. normally occurs every 50 ms. During this
routine, the microprocessor checks for
2B-3.5 Interrupt Control and Timing Circuits phase lock on each of the loops and
monitors such items as AM and FM status
The interrupt controller integrated circuit (U8) and the power meter input.
processes the interrupt signals from the DWELL
INT, GPIB INT, LFF INT and KBD INT inputs
2B-4 A24 GPIB PCB, DETAILED
and generates interrupts to U9, as required. These
DE SCRIPTION
interrupt signals are handled on a priority basis.
The L FF INT interrupt from the A24 GPIB PCB During the following description, refer to the the A24
has top priority; the KBD INT interrupt from the A2 PCB block diagram (Figure 2B-3) and to the A24
Front Panel Control has the lowest priority. PCB schematic diagram (Figure 2B-10).
The L FF INT (Low Fast Frequency) interrupt The A24 GPIB PCB controller consists of an 8085
from the A24 PCB occurs when a fast frequency microprocessor (Ul) and associated ROM and RAM.
stepping command is received from the GPIB inter These circuits perform all the necessary software
face. (The fast frequency stepping function is initial operations to interface the IEEE-488 (GPIB) instru
ized by storing up to 512 frequencies in RAM ment bus to the A23 PCB main microprocessor. The
memory.) Each time a group execute trigger (GET) A24 PCB also contains a GPIB controller integrated
command is received from the GPIB, the A24 PCB circuit (U7) that performs the actual GPIB interfac
sends an L FF interrupt to the A23 PCB. The ing and control operations under overall control of
microprocessor then commands the synthesizer cir microprocessor Ul.
cuits to go to the next frequency stored in memory.
This reduces the time required for the GPIB
Microprocessor Ul implements the following GPIB
microprocessor to process the frequency commands
subset functions: SHl, AHl, T6, L4, SRl, RLl, PPl,
and request service from the main microprocessor.
DCl, DTl, and C5. Also, the front panel GPIB status
LEDs (remote, SRQ, listen, talk, etc.) are controlled
A DWELL INT interrupt is generated by the Al 7
by the A23 PCB main microprocessor from informa
Analog Instruction PCB during analog sweep opera
tion supplied by Ul.
tions. This interrupt tells the microprocessor that a
(sweep) dwell has occurred and that it must now
perform either a bandswitch, retrace, or beginning 2B-4.1 A24 Microprocessor Circuits
of-new-sweep operation.
Microprocessor Ul is an 8-bit 8085 microprocessor
The LINE TRIG input from the A28 Motherboard that operates at a 6 MHz clock rate. The internal
power circuits and the EXT TRIG input from the clock generator circuits of Ul are controlled by the
6 MHz crystal, Yl.
rear panel BNC connector are multiplexed by the U3
priority encoder chip to produce a single interrupt
signal. This interrupt occurs when the synthesizer NOTE
is in sweep mode and set for line trigger or external Switch SWl must be in the NORM posi
trigger operation. tion for normal operation. (Switching
SWl to the SERV position causes Ul to
The U6 counter and U7 timer circuits provide timing perform special test functions.)
signals for wait periods controlled by U9. These wait
2B-4 67XXB MM
28 DIGITAL CONTROL
D �
Y1 (15 MHz)
r
-
.. CLOCK ...
CIRCUIT .. 8 BIT·.·. ADDRESS ·
LATCH
: :: '):>
--
, :,
..•.
U1 :
U10
WAIT STATE
- CIRCUIT � 8 BIT
3088
)
p1 U2A,U2B MICROPROCESSOR
DWELL INT
I
...
...
(FROM A17 PCB) .... ,
GPIB INT ...
i:.
3 BIT .. .::.:. .
...
::::
(FROM A24 PCB)
LFF INT ,_
. ....
. .. ADDRESS ::,:·: :::: ::;:...
... - . ..., . :.: :
... LATCH
.
...
I
(FROM A24 PCB) INTERRUPT
CONTROLLER -
KBD INT - ..... U9
...
(FROM A2 PCB) , ....
U11
,_...
- us
LINE TRIG
(FROM A28 PCB)
>-+ t '
+-- COUNTER
TRIGGER - -
EVENT
MUX TIMER
U7 U6A,U6B
EXT TRIG I
(FROM A27 PCB) , � U3
I
I
67XXBMM
A23 MICROPROCESSOR PCB BL OCK DIAGRAM
EPROM NON-VOL
EE PROM RAM
RAM
136K 16K 16K
BK
'r
P1
I
DATA BUS 1!18111!1 MICR
1118118 OPROCESSOR
�i
�� llliilllllliilll!11118118!111181188811i111111!18111111!1811111
�
OUTPUT ��������� - , DATA BUS
LATCH
I DO-D7
_I TO AS,A15,A16
U16 / PAO A17,A24,A29
J PCBs
1---•PA1
----)�
1
)jPA2
t-------��;PA3
ADDRESS
BUS
LATCH
-----71 LPA15 (A17 PCB)
DATA BUS 1 ...,._ -----7! LPA16 (A16 PCB)
: ,...:,:=:::::::::::::::=:,:::::=::::::::::
INPUT
I� -----7! LPA17 (A15 PCB)
::::::::::::·:·:-:
LATCH
U14 o----... -----7! LPA18 (A29 PCB)
U17
DEDICATED
ADDRESS
BUS
LATCH
-----7: LPA19 (A17 PCB)
U15
2B-5
A24 GPIB PCB, DETAILED DESCRIPTION 28 DIGIT AL CONTROL
The circuit functions on the A24 PCB are addressed The output of U12, pin 7 (via inverter U2C) is the
by the A23 PCB main microprocessor via the PCB GPIB INT (interrupt) signal. This signal and the
address bus lines PAO-PAl and the dedicated ad PCB address bus decoder, U4A, control the transfer
dress line, L PA21. When enabled by L PA21, the of data between Ul and the A23 (main) Microproces
address decoder, U4A, decodes the PCB address sor PCB.
lines. Only one output from U4A is active at any
time. These output signals are used by the main
microprocessor to select and control various A24 During fast frequency stepping operations (via the
PCB circuit functions. GPIB), L FF INT interrupts are generated by the
A24 PCB. Refer to the description contained in para
graph 2B-3.5, above. The L FF INT interrupts are
2B-4.3 Dedicated GPIB Controller and
generated by the logic circuits consisting of U3A,
Interface Circuits
U3B, U4B, U9, U13B, and U17C/U17D.
Integrated circuit U7, is a dedicated microproces
sor/controller for the GPIB. This device controls the
data transfer to/from the GPIB via bus transceivers When the synthesizer is turned on, the A23 PCB
U5 and U6. The bus transfer rate is approximately main microprocessor commands the A24 PCB to per
15 Kbytes/second. form a self test. Microprocessor Ul performs a self
test of the GPIB circuits and stores the results in a
The interface between Ul and U7 is via interrupts. buffer in RAM (Ull). When the main microprocessor
Controller U7 receives commands from the GPIB has completed its self test routines, it retrieves this
and sends them to a part of RAM (Ull) that is used information via the main microprocessor data bus.
as a buffer. Microprocessor Ul then decodes these
commands and sends command/data information to
another part of RAM that is used as an output buffer. Programmable interface chip U14 functions as a
This data is then sent, via the programmable inter parallel peripheral driver/receiver. It is intended for
face, U12, and the bus transceiver, U16, to the main future use. The L TEST input line is also not
microprocessor data bus lines (DO-D7). presently used.
2B-6 67XXB MM
28 DIGITAL CONTROL
Y1 (6MHz)
r01
r
INTEI
_... 8
...
BIT .,....
.·.· ·
A
���€� '' ' /'
r.,
jf:j EPROI
dl us
t 16K
I
M lcROP '.\'M: .ssoR
a
err
•• , "' • •
w,
'�·
h
,··
·
•
J,
U1
-----
(JUMPER
BLOCK) INTERNAL
j! l
ADDRESS t ' .
1 BUS (8-BIT) r
P1
I
PAo· e>---l
!
1----ti-i
PA1' ,>---t
ADDRESS
I DECODER
I
LPA21 (A24 PCB)• :::->---iE N
j U4A
._______.
I
I
I
I II �
GPIB'
CONT ��� i
::::::::::::::::\;}::·:-
GPIB
BUFFER ··.•
;
.•.• . .. .
.·.· ·
!Ill
:::::
! U5 7210 ··-:::f:�::::..::.:·:·:=: ) 1 _.·:::::::;:::�:::::: ::::::::: ::::.:.. "
I
._
GPIB
I PROCESSOR....,.IRlllillillll!IB11111��
I
GPIB j
DATA ·· j :\;';: :::::::;;:;:::·. GPIB
BUFFER
U7
BUS.
I DAT•
CONH
I us
LOGI
67XXB MM
A24 GPIB PCB BLOCK DIAGRAM
p2
}
I
K
OM RAM
:
�
9K
,....
I
.....
8255 24 BIT
U10 U11 PARALLEL '
- ,..
PARALLEL
INTERFACE
I
OUTPU,....
(SPARE)
- i )
,,...
I
U14
1, p1
I
t
I
FF INTERRUPT ! L FF INT
i;i
ERNAL ADDRESS BUS (16-BIT)
1---I---. (TO A23
�.
C��rnT
11&;;;:;;;:::::;:;::::::::::::::::::::::::::;;;;:�::::::::::�:::::::::::::::::::::::::::::::::::::::::::::::�:::::::::::::!S!::::::: �::$0:-
PCB)
I
U38,U9B
U13,U17C/D I
I
I
�-------• GPIB INT j
. (TO A23 PCB)
DATA BUS
OUTPUT
LATCH
U15
8255
PARALLEL
INTERFACE
DATA BUS
r llllill ,! DO·D7
U12
INPUT '-41111llll
1111i ...,; (TO/FROM A23 PCB)
LATCH
1TA I
llK>L 1--------------.. 0EN U16 I
GIC
2B-7
AB SERIAL 110 PCB, DETAILED CIRCUIT DESCRIPTION 28 DIGIT AL CONTROL
2B-5 AB SERIAL I/O PCB, DETAILED • The internal clock that is used to shift the data
CIRCUIT DESCRIPTION through the shift registers.
During the following description, refer to the AB • The strobe signal that is sent either to the A2
Serial 1/0 PCB block diagram (Figure 2B-4) and to Front Panel Control PCB or to the A14 PCB (not
the AB PCB schematic diagram (Figure 2B-6). presently used).
The AB PCB converts the B-bit parallel data from the Integrated circuit U7 is a multivibrator that
A23 PCB main microprocessor into a 16-bit serial operates at a frequency of approximately 600 kHz
format. It then transmits the resultant serial data (as determined by R6, R7, and C9). This circuit is
strings to either the A2, A6, All, or A13 PCB, as gated on/off by the state of flip flop U4B, which is
determined by prior commands issued by the A23 controlled by the main microprocessor via the strobe
PCB. Note that there is a separate serial data bus from UL The output of U7 is divided by two and by
from the AB PCB to each of these PCBs (Figure sixteen by counter UBA. The divide-by-two output
2B-4). The AB PCB also receives serial data from the (QA) is the (external) clock signal that goes to the
A2, A7 and A14 PCBs and converts it into a parallel clock multiplexer circuit, U12. This signal is in
data format. This data is sent to the A23 PCB via verted by U2C and is the internal clock signal that
the main microprocessor data bus. goes to the shift registers.
Tri-state gate U3A monitors the Q output of U4B, Data from the main microprocessor data bus lines,
which is in the high state whenever the AB PCB is DO-D7, is loaded into U9 and Ull by the strobe
processing data. When enabled by the strobe from signals from Ul. This requires two load operations
Ul, U3A passes the state of this output to the DO because the main microprocessor must put a new
line of the main microprocessor data bus. This line B-bit word on the data bus after each load. On the
is monitored by the main microprocessor to deter rising edge of each clock signal, the data in each
mine if the serial VO data circuits are busy. register is shifted 1 bit toward the QH output of U9.
2B- B 67XXB MM
28 DIGITAL CONTROL AB SERIAL 110 PCB, DETAILED CIRCUIT DESCRIPTION
microprocessor. Each of the five serial data buses d. Ground Return Multiplexer
include DATA, CLOCK, and RETURN lines. The All of the serial data and clock signals from the
serial data bus to the A2 Front Panel Control PCB
AS PCB go to destinations which have chassis
also includes the FP STRB line. The serial data bus mounted filtercons as an interconnection device.
to the A l3 Pulse Generator PCB includes a second Filtercons are 1t-filter networks that are used to
clock line, PLS TRG CLK. The lines that are in reduce crosstalk between the circuits in the RF
cluded in each serial data bus are shown in Figure casting, and to reduce overall signal radiation
2B-4. Only one serial data bus is active at any time. from the synthesizer. They are also used in the
signal and power supply lines of the phase lock
NOTE: and front panel circuits. For further information,
The serial data bus lines from the AB PCB refer to Section 2M-Motherboard/lnterconnec
to the A28XA14 connector Qabeled CNTR tions.
or FC) are not presently used.
Filtercons have approximately 1500 pF of capac
a. Serial Data Multiplexer Circuit itance to ground. Driving this capacitance with
The serial data from the QH output of U9 goes the serial data and clock (TI'L) signals causes
to the D input of analog multiplexer integrated high frequency ground currents that affect other
circuit U6. To transmit data to a specific PCB, circuits connected to the ground system and also
the main microprocessor first loads address in cause undesirable signal radiation.
formation for the selected PCB into multiplexer
control latch U5. This causes U6 to connect the Transformers Tl-T4 couple the high frequency
serial data to the serial data bus for the selected components of the TI'L signals to a separate
PCB. multiplexer circuit consisting of FET switches
Q2 thru Q 6. The inverted high frequency com
Note that the serial data bus select information ponents from the secondary windings of Tl-T4
from U5 is fed in parallel to multiplexers U6, are coupled back into the grounding system to
U12 and UlOA Therefore, only the DATA and oppose the currents caused by the filtercons.
CLOCK lines (and the strobe line-if used) for This reduces the overall ground current effects
the selected serial data bus are active). and improves the Electro-Magnetic Com
patibility (EMC) performance.
b. Clock Signal Multiplexer Circuit The FET switches connect the secondary wind
The clock signal from the QA output of USA goes ings of T1-T4 to the RETURN line of the selected
to the D input of analog multiplexer integrated serial data bus. These switches are controlled by
circuit U12. The serial data bus select informa the Q4·Qa outputs of data latch U5.
tion from U5 causes U12 to connect the clock
signal to the serial data bus for the selected
PCB. 2B-5.5 FLD12 Data Latch
67XXB MM 2B-9
DIGITAL CONTROL ASSEMBLIES, TROUBLESHOOTING 2B DIGITAL CONTROL
Microprocessor PCB. Upon servicing the interrupt, • The Clock control flip-flop U4A is triggered to
the main microprocessor programs the AS PCB as shift the single bit of data from the A2 PCB into
follows. Ull (and U9).
• The UlOB serial data input multiplexer is
programmed to switch the FP DATA line to the After the data has been shifted into U9, the main
SIN input of Ull. microprocessor interprets and processes the data
• The clock multiplexer, U 12, is programmed to word from the main microprocessor data bus.
route the serial data clock to the A2 PCB.
NOTE:
• The clock control flip-flop U4Ais triggered to shift
The CNTR OU T line (from the A14 PCB)
the data from the A2 PCB into Ull (and U9).
is not presently used.
After the data has been shifted into U9, the main
2B-6 DIGITAL CONTROL ASSEMBLIES,
microprocessor interprets a n d processes the
TROUBLESHOOTING
(keystroke) data from the main microprocessor data
bus lines (DO-D7). Refer to the troubleshooting information located in
the beginning of this section (Section 2-System
Description and Troubleshooting). This information
Whenever an external 10 MHz reference signal is
connected to the rear panel 10 MHz REF INPUT BNC
provides a list of error codes that may be displayed
2B-10 67XXB MM
28 D/GffAL CONTROL
P1
I
I D
I FLP
Q-
I FLIPFLOP
....
I
I U4
I
. ... '""
D7 MUX '""'·
I ,,. ,,
,_
DO-D7* CONTROL
LATCH
-
'""
DATA SIGNAL
>-+
us DATA
PAO*
PA1* >-+ ADDRESS
,.,,_·_
r"'W"
'
Q H�= T2
-
-
MUX
-
PA2*
LPA22*
>-+
>-+
DECODER
CIRCUIT i+ SHIFT
REGISTER
r us.-
U1 EN ....
r SIN us
:{):::
:
GROUND
-
-
....
CLOCK/
iH- TIMER RETURN
-
J
CIRCUIT MUX
Q
U4B,U7,8
+ .... _. Q2-Q6-
SHIFT
REGISTER ....
-
FPOUT i�
A2
EN
(FROM PCB)
-
SERIAL
U11
EXT REFDET
i� INPUT SIN
: j):·· -
CLOCK
(FROM A7 PCB) MUX MUX
-
T3
I�
-
CNTROUT
-
A14 PCB**) U10B CLOCK SIGNAL
--
( FROM
u12-
r
I : :::; : :::
, :)
STROBE
MUX
STROBE SIGNAL T4 -
-
--
U10A
t
*FROM A23 PCB
**NOT PRESENTLY USED
67XXB MM
AB SERIAL 110 PCB BLOCK DIAGRAM
� }
P1
I
I
T1 FLD 12
@ nDATA
'Fl RTN
f----- Fl CLK
SERIAL DATA BUS
TOA11 PCB
� }
FLO 12
Fl DATA
;@ I
:.@)
CL DATA
CL DATA
;.@
PG DATA
SERIAL DATA BUS
CLRTN
TOA6 PCB
;. @)
CN TR DATA
CLCLK
s }
-r@ I
FP DATA
FLRTN
I
;@ I
·�
CLRTN
�DATA
PGRTN
• @> PG RTN SERIAL DATA BUS
CNTR RTN TOA13PCB
• @l
PGCLK
g }
FP RTN PLS TRG CLK
•@ I
FLCLK I
CLCLK
cwmoATA
PGCLK
CNTR RTN
PLSTRG CLK SERIAL DATA BUS
FC CLK TO A14 PCB**
FC CLK
}
STARTFC
FP CLK
I
:FPDATA
I
I
I
2B-11
0
--IBID- I C16
(Front) 1 P1 20
NOTE:
Leading zeros on
component number
references may be
disregarded.
AB SERIAL 110 PCB PARTS LOCATOR 28 DIGITAL CONTROL
2B-12 67XXBMM
0 1 2 3 4
DO +sv
DI
A
D3
DZ
04
05
06
07
+sv 74HCl4
C4
B 16
c� QI
I
I
I
YI
10
2
F A 0 A
Y2
I
11
12 I 3 c u I Y3D-'�--+-----------------------------.,
p A I B
>" A 2
II
6 El
13: 4 ZA Y5Ll�-=--+---------4---------��-��---���---+-4--+-'
Y4 10
L PA 2 2
I E Y6 µ--9--+--�----4---�- --- ----------+--+-+---+---l
5 E2B Y7 NC
GNO
c
+5v +sv
::< 3
4,75"
Q 9
Q R5
8
D
NC
IK
13
74HCl4
R7
511
c 9
s6o
TIMER
T
PF
V 555 -:GUNTER
E U88QA 11
NC
13 I 0 9
'.:!B
74HCl4
:.::: 9 r.c
IJ IZ 74HCl4
·-------.-
1�
1 ESE QD e NC
G'<D
T
L2E
+ 15V ','4,.<:_' 1
4 74HC 393
r:-1 I•
---- ---- -----�
I ,, V+
22
F i2
T ' - SIB
'U
T z�'
I·::.:
;:,:- ,-u s= a
EXT�'""l1T
14� : I S 3Bl
�
3 15
-15V
�I
1.
LI
G
RESISTANCES ARE IN OHMS (Q),
1. UNLESS OTHERWISE SPECIFIED,
' ,:.i! � 'l v
o? --1
�
CAPACITANCES ARE IN MICROFARADS (µf),
� INDUCTANCES ARE IN MICROHENRIES (µH).
t-
SIGNAL PATH CONNECTION HAS 5. LAST USED/NOT USED COMPONENTS AJ
' ',I ' . (TYPICALLY) 1SOOpF CAPACITANCE
: R 1 1
:-41
l'.-1 BETWEEN IT AND CHASSIS GROUND. REFERENCE DESIGNATORS
H CI
l1
51,1 6 ISOLATED GROUND:
I
Q6
0. 4. STATIC SENSITNE COllPONEKTS USED IN R12
THIS ASSEMBLY INCLUDE: RN3
T4
01-06, U6, U7, U10, U12
U12
67XXB MM
5 8 7 8 9
I
-t5V
Pl
Tl I
R2
D2 03
I
,..:--
:....:c 1r4�0� FLD 12
4
--
QP:-NC 99 I
--
74H C 74 04
---- ----.
+5v CONTROL � .s +5v SERIAL DATA
:
I
:
h
?� \J
+5 v
t1 M U LT IPLE X ER :
Jl I D VCC I Q 2' I
3
___
.1.1 74HC374 t
' 1
\] :"RN"2' I
•
-i5v
• I
-'
v c6 o_i.z!S. -c."RoOf\i!S-Rtr
MULTIPLEXER
J;>o :o�
V\.:L" ;· • \J
D
vv
l'CJCLR 470 Pl
!:so uH�
I 7
> R5
R NI r--
- r-Ra.
_.!tlT'"t
<.._
_ s 2 ! "-"-7 FL RETURN
...J-�--� 3 e,
3 A/QA 4 ••• 7>
';"' 8/QB 200 ·�
a.c;ac 470
&4 P/QD
02 03
Otn
.
.
�1'-"--+--+-+-i-+--+--'
E/QE 6
RNI
F/QF u 9 '(IQ.4 L--f--+-+-+-1-- ---"'-'\v/l.v· /I.•�· 5 --- ----.
�
i- G/oG T2 470 I �&a
+-- 4
� H/QH
.
Jor:..S __ __,�2�" C NTR RETURN
le�', 8 ��1•7
k G2 410 ��u s
s_ --.--�
32
_§_NC RN I ·� PG RETURN
:l:���K GNO
.!.§.NC I O V••A.9
� -
�B DI D4
S4 7
___.
2 PG CLK
�c � -EN
S
512 ZO FC CLK
�D a.2-Nc V •. �
D
Ul 2 s6 11 ,- -�26
FP CLK
[£: J
8
i2,_ E 02
T3
03 57 Nc 2 1 >5 .6 4 >�
�F UI I r.....1',
��4 ��2 � : ->, :: � � :� ',
-='- G <RB 13 4.7K
v- ,
200 l\>N31-- -
�H -1 v; VoG sos - --'
'--�1�,
1 1
�SIN
� LD EN DI D4 AO SIA� NC Pl
I ----=::i] A I S Z Ai-:5:...----
.. ' = 29'-1 F P STR 8
-------
I
t-t>CLK
GND
•
--
L----'2=-tEN S3A.§_NC I
I 4A 7
--
RN3
I t?
< < 4.7K
I
DG509 I I
RS
. A � !. - >,_ -
200
- - _,
fISTERS
r'
2B-13
TESTPOINTS
TP1 GND G TP8 U28 EEPROM C
"
TP2 +5VD TP9 U24 EPROM C�
CAL TP3 U9 µPROC WR TP10 U25 RAM CS
NORMAL TP4 U9 µPROC RD TP11 U26 RAM CS
TPS U22 EPROM CS TP12 U29 RAM CS
rlrl
TP6 U23 EPROM CS TP13 U9 µPROC ALE
TP7 U27 EEPROM CS
P2 -w
Position
.. ··:::: ·: ::::::
Jl/P2
:-�===��===::
TP1 ·13
U. 0 9
�
--v
c
I\)
I\)
c
I\)
w
c
I\)
�
c
I\)
Ul WI]
€::v:i:�:::1
s::v:i:�:::1 �::v:i:1:::1
--v
WLi [£1[J
P0 1
(Front} 1 P1 49
NOTE:
Leading zeros on
component number
references may be
disregarded.
A23 MICROPROCESSOR PCB PARTS LOCATOR 2B DIGrrAL CONTROL
cs
s
A23
MICROPROCESSOR ·
NORM . SERV
07
2B-14 67XXB MM
0 1 2 3 4
B
I
! CLR
II
: +sv - us
' '
� ....,_
l_,_ _ 1 __:
4..,--c 1:- ;'-IL S 0 '+
!
_____ ______
• SV
W l l
I I I • C CD
i.-2 cJ Q � ·.NG-"
c : I
I
"" U 2. 5
1 2. H�
, ,-Ly
0. 1 v
! UQ 7'<LS78� ,K
I
I I
' t-
�--�
��R l/1 u 5 0
1 1 _______,_----+-+----t-'--+--��
"-<Y"A t--
1 ---------<r-+-�
7'-! L SO'+
I
I
I
- s v RCo
-r s v
Pi
D I .----+-._-'-' :::.i ! R O
1B I NT � l '-
7 -- --+---.....J �V.YI! K.
"t-------f----++---'-1LJ
4-"
� °' I R I I N A'-ZC,,
.---___,f-+-__. '-l , R Z
2'-"
0 C'OO � ".c.
DWE L L I N T I
.----+-+--"Z'--'-i
1 , R3 e s t � ... c_ !
GPI B - ------+--+---+-+--==-
' 't--
". "'
+-.:...
� Z ' � Lf
2"-l CSl. ..i..a .
3 i R�
..--+-+-+---+--+--'2"-'=-l DO I I
DD Z�·
I�
I NT
.---t-+-�
:2..:;
Lf:-1 1 R (D
.c.
2.5 1 R-1
LFF INT
D 3 ' 8 '-
1 7'+LS0'+ Z ·NR
RD
DDS�
4�
KB D _· _
t N T ,"' ...
:
! .__ _ ____._,_......_,
_ 3
D <;, lfr- "
D 7�
/\0 Z 7 AO
�cs
_
::_ , T C: R ::;: L J P T
E
c..., \·< I \I f R '-l B
,_._!'-"...............
-; BZS� / ................+-------------------------��
-+ '
._
I
I
F _: :.J E E P PI G G F R
' !1 J x
..J 3 I
i '/'-IL501
i • 'SV
CB
I
i- 5 V
I t �7 TI o�
� (D
ti
G
I
1 « 16·� I z.i.+
R5
101<
O(O 10
'>
'>
U CO A '.Y3-S- ..J._!_ G.O
CD
Q Z. - N c :J/ I 1 3 � 62
7'-!LS Q I .!:i.. N (. 0/2. 1 7 �
GI
�) ' li8 2. o e ca
15
W R 2.
. sv 0
�
I
Q
i
LI 7' I AIZJ
Al 20 A l
I '3 AO D3 5
0 4 Lj
D"" 3
/
/
· sv 9 zz
21_
C$
RD D � :a
/
/
WR '.) 7 I
--�...,-\Z..,.---' 62 5:.
2 3-
( ;. :,
H E \/ E N T
GNO D
t5\I
CD T 1 ME R L
67XXB MM
� I
,-1,
.s .
5 6 7 8 9
-::ro!� CZI RN I
+ 5Y
V iO K ,> � . JI
+ '=:> ,> ,>
,
Cl l
;>
:> � . '> '>
if---j ,, 5 Co 7 8
3 100
•
U20A Y O � --, 15
:J.
"' 10
.., V
� o '2. AO Alf 2. A '( I "'""'s
� ADO/
I
'
-- - -
vr---+----+-+----+-+----+-1---"2.3� - - -
Q I �/Al 8
� 2. �I 3 B yz. � / <t - - -
- - - 10
15
Q3�
� EN
...---
'1" 3 �7
v s - - - l '-1
Gl4 � 9e /
as � /
T
ID - - -
7 - -
13
1 1
12
/'-f L.. � 1 3� .
3
B
'- : D 7
- -
Q.7 �
QI<>
/
/ 8
AD7 0 r::-:1
I 10
JIO A7
� l1'-<\U L(.. b.-.. i-4L':i 01
- -
:;
- 73
'----,---,1 ¢ I D BUS
, C 2' 0 E S E L
C A L D ATA
, o
�� D A T,, S E /....
7-------+-"'""'.-----------------.-----__,
�1,.---------------t-----------------------+--�7 o�
llf,u A D D R bUS
...._
,
I
+ 5V � � Cl7
0. 1
z-'� WR
�I
- 4 L'? 0�IZ
4 l 5 + sv 3 DO
ZO;
::;io t.
F U
�
I
; us
/
------ --;�
- v
7 DZ QZ.
· z '.) I
13 I'.. V.r--1----------+--1--+-�
. ,.--7
. 3
' s D3 03 :::. v�--------...--+--1--+--o"- --Y
--++--.-
a-OC
::::' 3
!10 ri..., 0.1 ' Q'-1 �/
QS I 5 ' /r-lt-------.--i---;---i-- . .;.,�
·5
CIZ.
�
I '-I D 5
' 3 ()Lj ::>-;
-
�
-----
�
12 PR. t "7 0(., t--
/--l ----- t--- -
----1
--t-- -+
-t- --= �
I
� '
I'.. Qi<> �V
--7'-
-t-
D5
1 - OE HCT
"/
Q C<N 2.
0 e 7 � s ,, 3 z
8
CLR =<73
'-'
'>
',>> > >> >.(> .(>> ?> <
t
tOK
o� 1
+ SV :;H I v CJB
t '=>Y
2 IAI
� IYI :8
/
� I A.Z. I Y 2 I to
/
� I Y3 , ��/
/
\ ,A,3
/� I A'-4
/ 1 1 2A I 2Y I
1 '< '-1 I Z.
/
V"/?;
� 1?, 2 A'2.
2A3 2'f3 5
2 Y2
e
-, /
/
v::1t:
I
2A'f. 2 YL/>--3-��
�--+-----1r--.=
� 9'{]��� u 17
+SV --+- 1� C15
2 01 Q. I 10\7
-, \] ...,.
Y-4
HCT
� QO t-2- DO
----+-----� 2.'-!Ll '" Pi
DI ,_
'\.,,__.!:!5
.,__________�QI I I � RD
.SO I '-......2 DZ Q2 "" �---------------<I--- ·� "'AO
Q � � 1 1
. , z_ ) ?A l
� 03 I
� D4 Qi.4 IZ.
,. D5 Q5 � I 3
P A3
;:,A z..
+ ,--+�-"''" ·� D<D
�
Q<O� 1 .CCN --.-----l {--, C t !O
A l� D7 :;; 7 � II 20T n
'.../ 0.1
U l '-l
o
I l)E
D:>.-:-A l_ A\C H E S •5V � IAIAZ.I ! 'Y I @_/
l-IC
, 0T37"t ......,._ I Y2 1JSe._/ ::i TA R T
IY3 �· I N S T R U C T I O N --%
>--
_-52. I A4
I A3
l 'Y'< �· L i'-IC H
+sv ..J_!_ 'Z.A I 2 Y � I
•
�--•i C l '.::> --����
_....!.2
- 2ALI
��;�
A__/
r;�
ZY"l
-;±<: I E N U IS
t (o I
,_J4: 1'?.E N
"' '
l
C/> ., .. . ..,
,3
· ' ·
,,
2 ,,, · Z.
,, , 3
�
�
I
I
Figure 2B-8. A23 Microprocessor PCB
2)
U5 '°'--! EN I
�----=
Schematic Diagram (Sheet 1 of
P..7 I I E .)Cr'IO'-- 6700-D-3 1 723-3 (Rev. J)
HCT l 3 8
__!:1,-
': EN B
ENA
- ------- ---t-'
' 5
"'(]
�.l
v
I K
9
2B- 15/2B-16
0 1 2 3 4
B AO
Ar DO 11
2YO ,,______._4
A 2- DI
2. Y I
2. Y 2 A3 DZ
2. Y 3 A Ll D3
A5 D L/
C:ODE S E L A (O DS
A7 D CD
AB 07
A '?J
A IO
AIZ
Al I
c Al3
A r '-'
�---+---�....:::.;,,,.., OE L) 2- 2.
�---<0-=o.n � c
' v ;:> P
2.7 2- 5Co
( 2 7 5 1 2.)
D
ADDR BU S
I D BU�
E A 13
-\ . -4
DATA SCL
0, ,3 /'/ 7
' --0 0
AIS
/\ 1 '1
U2 1 5
'-0
n'-'=---+---+-....J
;:.
2- YO
UZLJ
n-----=-< B
/.'\lo
�
F CA c. DATA
CJia::>------------'-=<:J ENl zt,, N
C
--: Y L S · 3 ':!>
2 704-
('.
RD
'A R
G
� PR OM � �� · y :::
R .:. ' .
H
LE\
CONNECTIONS BETWEEN MULTIPLE
OR
SHEETS OF TlilS SCHEMATIC. TliE
SHEET NUMBER AND SOURCE OR 6. STJ
I 2/8 3)
DESTINATION GRID COORDINATES THI
APPEAR INSIDE TliE FLAG:
UI
67XXB MM
5 6 7 8 9
+ sv
J" I
RB ,-
IOK
-
----- ----- · E E P R O M -- · -- -�
�-------- ----------_.______:_ : .L.>
1 jc �" LJ
CL4
p 2.
-t '5V
�� :::> O
;:) /
NC_:j] jN ORM f\LI
:::i z
D3
:)'-l
:i s
D�
:::> 7
J2 3 UZ7 U2B
" U M P E R TA 3LE
\N S
2 75 1 2. \'-J I
--
VY '-4
W G:>
2 5 Z: S lo ,·J S
-- ·
I W IO
2 8 l:>'-/ w7
w 7)
t 5Y en � sv c�o
025 U29
R9
2b
+ SV
OK
01 � Co2(.,'-I
f l..j o 2 b4 14
0 5 I 2. 2. ':>
7
'----- q MA -------"
' ;
FOUND SYMBOLS USED ON nus ASSEMBLY 1, LAST USED/NOT USED COMPONENTS ARE:
'\}
CMEMATIC SET ARE DENOTED AS:
REFERENCE DESIG NATORS
SOL Al ED GROUNDS:
LAST USED NOT USED
(2)
Figure 2B·8. A23 Microprocessor PCB
EST POINTS ARE DENOTED AS: C35 CR1
CR2 P1
6700-D-31723-3 (Rev. J)
L1 W1
A NOMINAL LEVELS.
P3 W4
IATIC SENSnTVE COMPONENTS USED IN R11 W6
ltS ASSEMBLY INCLUDE: RN2 WS
U32 W10
�1-U13, U20, U21, U24-U27, U29, U30, Y1
W13 WU
Y1
2B- 17
����MAL
TEST POINTS
TP1 GND D TP8 FF I NT
TP2 +SV TP9 GPIB INT
TP3 U 1 4 RD TP1 0 U 1 4 CS
TP4 U 1 4 WR TP1 1 U 1 2 CS
TP5 U 1 0 CE TP1 2 LPA2 1
TP6
JJ!
U 1 1 CE IP1 3 UB CLK
TP7 U7 CE
Jumper _
,.,.,.,.,.,.,.,.,.,.,.,.,.,.,.,.,.,
Position
P3 P2 TP1·13
(Spare)
2 4 6 8 10 12
\ 1 3 5 7 9 11 13
--- IL._-
'
P02
__ -
__ j rn:0:%:3 ® C�§j::3
L----- u 1 4_---l
- ill[] �
:3
[ill]
-®D-
� i: m�
G1:0:�:3
[ill]
U12
l I U07
l -JlP
R06
[
$� � �
(Front) 1 P1 49
A24
GPIB
SERV
c:lll
SW1
NORM
SW01
U0 1
l
�
-R__,
N0"""
1 ____,
)
c
......
2B-18 67XXB MM
0 1 2 3 4
� 'J J I
+ 5 \;
�
-----�-=--=--=--=--=--=--=--=--=-llLJ7 �------.!i6cJ -
= -
--
-�
12
D 7
,
E P R OM
__
DG
A
fv1 1 C RO P P GC E SS O P
1 ,:,_
_,�
l :l
8
:'....J U � ('._ ·
u-- i_O._ __... 1 r--- __ __;c;
LJ
If- -
,----__:!-.!:J _
-
- _ IS
_ _ 3
- II '+
D <;
0'1-
03
�
( A l !'l
A 2. I':
-l'\O
��
_____
I
18
I 7
7 '-' L S 0
'A.<; �
_
' "'+ 6
A6 '+
"7 3
1'16 ZS
'Aci -,�
AIO 2 1
Al I ?':!
Al7 '
B A l :l zi:.
...
-
C I ( f... I
\ IK
+_
c Pl
15 �:> ., ,-�
,--�.t.i!...
+sv 7_l
L "- E S c T R E S E T IM
RST 7 5 RB
READY
.---K
k 7 R'>H ,.S
L � + SV
• AA
v v � RST .5.5 I K
U2
�'�
�OLD RE S ET 0 U T 2-_
'--"- J NT RI'\ CL K .22_
l PA
F
' + SY -r sv
U 7
+ S \I
Pl
D·_----- ---
;-<q"�:L.-
g: � �:? -�
�
_-_-_-_-_,.hi4�'.J r�
l :l
1,��
- -+ � �
�-�
�C. CD II 0087
!J
'' !_j
-;- : I :·
I 1
I
< IOK
R
:l
>
h3
1.;:,1<,
RS
IOK
�u P -
010�
___ 1-lh-----+
·
-
- -
:._
·. r,E 6
-
-1� ' 1,
-
__;5:L] .!.-
--
-
I i b:--
-- --
D I 0 't
D1 05
�
' '-4-
(--
: "'.'
�
-""' ·�
___
7
'"'' "-
-/
-_
__19 1
. ___ !.J'
.'g..
1;"
� 1 :·�- -' 11 I
---+---L�'- r rDS
G
D 103
g: g� ��·-
(--
� t4'��=========t::::::::±Jz�'9i.J gg�
- OJ0 2
'�
'r-z_�----+--1-''.;J
-" D I 0 I
- l -
�-'--'--
1-
'1 ' I tv
l�P_c_::..,...=_
' .. _.l
I1
i
-� sv
�������
� l·J 0
9 - -
· _ i- V -,-_-_----_J
,._;1�' �=-_O -_J
CR / ( R I
L TEST �i'\��7=-, ==
F :,=' ----= == = = ·-
==
=�=---------===+====
- - -
=�====�-- _ ·· A
'°·_ - -- -
G '
+sv
I�
4 (f . �
+5V I I
_:-
, v U "':> D
: l U2 12
----I-�13:'J� Z
__ I
+ "� V �� 34 '
L
H - + 5V 7
$. •J O •. 1 Z - (. · �
6ND D
GND
�, -.,rr-----+---
T�O .!_I-9
-l.! - 14 ;...i C To4
7 4 HCT
74 �7
6 7XXB MND D �
�;:;-
M
D
5 6 7 8 9
+sv � +sv
T2Bl
f t
rtfzel
RA M P2
Z-7 zb I
VPP VCC PGM A_ O_ VCC CS2 Vlh AO 4
-, 3
'+
, ...;
l O_ ;; _
-,<- [J A I
l
U14
AO 1 1 /'\O -5
·
.2.. A I D 0 ._
0-
1 1__-'
o-'o�..�oo_
'-' _� 00 u ,.. I '"'
-.:i
="----''-'--'- A 1 .• "'-' D
'"0
'-"' __,
- 3 � 4
..-< DO � A 2. 2. S,'.
01 DI I I A Z. ...._ D 1 --'3� ,_, c I I
� AZ. LJ I Q DI 1 2. 1 2. D I
._ _ _,"- A"-•2 "'-'"-'- : 3' 0A3 7, 'tO
�
DZ 0 2. 1 7> o z_
� I'\A ;'+
.1_ DZ 1 3
03 IS 0' 03 1 5 03
A > l-!-
A'+ W'-
7__�
6__.:A
1\ 3�1
__,_-'--.I
't
ll'-'=:...:
0 2.-
11'--D"'-='-
: -:3;-'
3-.-:;�;..;
n
� D 2.
2.
l D3
,-.j
D A 't � A'
DA S S �
04 J�
i A5 D'+ I !; l'\ 't l"l 't 1 "' D 't A S .__ c; __,f'\ �,.._.
s :'4 D '+ DA6 J
D5 17 I ? 05 """"-'-
o s--' z.
;:..:9 37 10
� A& l"I< ne. A b 1-�- i.+
,____,,A,_, �IC. I "'"'=��--. o s DA7
�
__)_ A 7 06 I A D6 I) ' Ie
0G A7 ? L-"" '-
5 --'
- -- '-'-
"'
[s-'"7·I 11'--,._
o1.._
c. __,""' ? "-' 0 c0 PBO
18
..-q II
l7 SPA R E
07 l q 07 07 1 '3 0 7 A ,1 '-" 0,,__,_
7 __,=- Z 7 -- 0 7 � 13
gl!I
A8 _ AB � z""-
u -'� PBI
� A9 A 3 '-=-"---
• 1
� -'�
A
A�' •
IO
P B '2. " ' I
'+
AIO AIO
Zi!
PB3
A
Al l OE OE
2(_ IS
2.2. A l l l-"-
2:-.
3--<.
fl,_,_
l_,_
ld P B '+ ,T ' "'
A I 2. Z7 1 2 1-.'=-
Z. -'-A,,_I-=-.
Z I P BS 7't 7
� Al3
� VV R
P S (;
I
� CE 2. 0 , CE L'-A�O--l-
AI
-+--�9'-l P e ? I7� 5 18
GNO GND 5 P C. O 1-.:; 10 ,
2.C
pC I
r--+---1--
- -==-1 J5 <: :i I -,
R£ SET" P C 2 11 7 n
PC3
5 , RD P C 't 1_,-.: 23
,-..- �
36 W R P C S \1 2!"-"
-
� (5
P U '-'-' .._,,,
r l'C. • 1 0 26
+ o; v - -
-- -- - GND 7 +s v
�+sv
-
-1lv_4___
L.l-w-J _:"?L.�
ID\
� I C. . �I A
"R'°�
VCL..Yo LL2._ 10 I I� 7 741... '5o 1
2.
GND
-r-. 5 IZ � EN I
yz�
1> 1 2 t � ""'cCL.f'; �
c.
<;
B l.Jl 3 YI l 4
y�JZ_
Z
-= D 6).
u� E:> "' U�B
: : i.-;
\ I
� �I p
I
IJUll y4iil..:
10 c \'3 U il D \ al2A y.;li!l;:;( ..__Ut>
._._+-1--1--"'=
-'- 7
•
74L.� O O
r? Y(4ii;c,; �Z.B
G,IJ0-1,µ,..: D
B I I oa
I
F F 1 rn
16 r4HCT74 I
9
U2
HJ)
.__
_ _ .. 74HC.T04 1
74+\C.TI ?B ' II
I
'--'--- (§) I
T
T
T ------------------- 1 � GP1 3
-+--r-1' T "lQ >JT
+5V
+sv
35 h6 q;
-�
R!:StT VCC CS
Lo
� EN I VUC CI S
PC't(llB), (INH.;.jPU J2_
ENc
S P(b ( �lKJ
-f-!,,!-(:
� RC
� WR U� 6 �
__'L AO �)2_..__-=-1 I A l
---8-- A l l S;___ _____
6 l A�
i..:.
..._
.; _.+-4---+--��H�L-T_Cl 4-_,4--j I Y I �� _
(JBF, PCS
1 2. _ I Y2. ��I
�- -- --- ---,
(osr) PO 1 0 l I y 3 '-'-'
1 _
'1,__ _ __ _ REFERENCE DESIGNATORS
l�'l I Y't 1-
_
00 � - - - - - :;.
8--J ..;.
' I�' ----� LAST USED NOT USED
DI l 't 11
P CO i-:..;--1--+---+------�;.-i 2AI �---� ClB NONE
� Dl.
OJ
O'I'
J C:.
PC ! W..:L_
I f,
-4--+--- --+--
-
PC Z i-:..:'--
- -
: -l--
� �� ' 2A2
1�
15
L---+------;;;-i 2 1\3
17
---+------�� 2 114
l Y I '--"-
7 ---
z vz �"--
zy 3 ._2___
i'.Y�...]__
CRl
J1
L1
05 GND P3
� 06
07
U I 2.
74HC. 12.44 �D RlO
RNl
SWl
I
T1'13
+SV
t 20
� 8 2. S S A U17
Y1
I vcc
Pl
�, ;P, I
4 18 z. I
PAO A l
1 7 Bl DO
Ulo S PA R E S
4 i'.
�·) I
� I\ I
.3 B 2. A C. 1;
2_ lb 4 I 3
�« PAZ A� !J L
I I S BBll\ IW s
't
PA3 fl '3
� PBS 40 l 't 6 l s
P l\'t E5 AS u '+
:!.'3 13 7 b
� P l'I' PAS B i. A6 L) S
F ll G 38 I i'. 8 7
Cl A7 O E>
--.--1..2. 1' 8 7 37 I I BS F 't
FA"J A S C\ L) 7
GND
� OE GND
II
�7 I
�o 74. 1-\C..T24-s.
N OT E S :
A24 GPIB SCHEMATIC NOTES: 3. TEST POINTS ARE DENOTED AS: @ Figure 2B-IO A24 GPIB PCB
1. UNLESS OTHERWISE SPECIFIED, 4. mouBLESH00 11NG VOLTAGE AND POWER
RESISTANCES ARE IN OHMS (Q), LEVELS INDICATED IN BOXES ARE TYPICAL
Schematic Diagram ( Sheet 1 of 1)
CAPACITANCES ARE IN MICROFARAD$ (µF), OR NOMINAL LEVELS. 6700-D-31724-3 (Rev, C)
5.
INDUCTANCES ARE IN MICROHENRIES (µH).
STATIC SENSITlVE COMPONENTS USED IN
2. GROUND SYMBOLS USED ON THIS ASSEMBLY THIS ASSEMBLY INCLUDE:
\]
SCHE MATIC SET ARE DENOTED AS:
U 1 , UJ, U!;-117, U1J).U12, U17, Y1
ISOLATED GROUNDS:
2B-19/2B-20
2C-FRONT PANEL: A1 and A2 PCBs 2C-2 FRONT PANEL ASSEMBLIES,
OVERALL DESCRIPTION
2C-1 FRONT PANEL ASSEMBLIES: PCBs are part of the Front Panel Assembly. These
Al AND A2 PCBS PCBs are mounted within the front panel casting
and are isolated from the internal synthesizer cir
This section contains service information for the Al cuits. This prevents the internal RF sources and
and A2 front panel PCB assemblies; see Table 2C-l microprocessor bus signals from interfering with
below. Refer also to the specific troubleshooting in sensitive external equipment. Refer to the front
formation in the beginning of this section (Section panel assembly photographs in Section 5-Parts
2-System Description and Troubleshooting). Lists.
Table 2C-l.
system that sends the operator input commands to
Front Panel Service Information
the A 23 Microprocessor PCB . (The main
Documentation Reference Page
T
microprocessor located on the A23 PCB controls the
--
overall operation of the synthesizer.) This subsystem
tion
also displays operating parameters and status infor
mation via the front panel displays and indicators
(Figure 2C-l). The subsystem is described in para
PCB LEVEL graphs 2C-2. l through 2C-4 below.
··································································· ................................. ....................
Detailed Circuit Description Para. 2C-4 2C-4 indicate the main operational parameters of the
Block Diagram Fig. 2C-1 2C-7
internal synthesizer circuits. They are controlled
Parts Locator Diagram Fig. 2C-4 2C-14
by the A23 PCB main microprocessor via driver
Schematic {Sheet 1 of 3) Fig. 2C-5 2C-15
circuits on the Al and A2 PCBs.
2C-16
.
{Sheet 2 of 3)
• Forty nine LED indicators. Indicate the status of
.
{Sheet 3 of 3) 2C-17
the operational functions controlled by the front
panel keys. All but two of these LEDs are control
led by the Al PCB driver circuits.
• Fifty one control keys. Allow the operator to con
trol the operation of the synthesizer. The digital
keycodes for these keys are generated by circuits
on the A2 PCB and sent to the A23 Microprocessor
PCB.
• LINE (power) switch. Controls the +24V that
operates the line switch relay (A28Kl) on the A28
Motherboard PCB. This switch also controls the
associated STANDBY and OPERATE LEDs.
• SINGLE SWEEP push button. Initiates a single
sweep in the EXT sweep trigger mode. It operates
in the same manner as any of the control keys.
67XXB MM 2C-l
A1 FRONT PANEL PCB, DETAILED CIRCUIT DESCRIPT ION 2C FRONT PANEL
The operation and functions of these displays and d. Knob Motor and EXT ALC Amplifier Cir
controls are described in the 67XXB Swept Frequen cuits
cy Synthesizer Operation Manual. The front panel DECREA SE/INCREASE knob is
used by the operator to modify operational data
The three liquid crystal displays are refreshed with parameters that have been previously entered.
a 150 Hz (approximate) backplane signal. Other This knob turns a motor that is used as a de
than this signal, the Al/A2 front panel circuits are generator. The output of the motor is a de voltage
normally in a static state. They become active only proportional to the speed and direction in which
when the main microprocessor writes to an LCD it is turned.
display or a LED data latch, or when a front panel
key is pressed by the operator. The A2 PCB contains the amplifier for the signal
generated by the knob motor. The output of this
amplifier goes to the DVM circuits on the Al 7
2C-2.2 A2 Front Panel Control PCB, General Analog Instruction PCB.
Description
The A2 PCB also contains the preamplifier cir
The A2 PCB contains the data interface and control cuit for the signal from the front panel EXT
circuit groups described below. LEVEL BNC connector. The output of this
amplifier goes to the Al5 ALC PCB.
The 5 1 front panel keys make up a keyboard nected to the A5 Reference Oscillator PCB, the
matrix. Whenever the operator presses a par A25 Power Supply PCB, the A29 Rear Panel In
ticular key, the keyboard encode circuits convert terface PCB, and the OPERAT E LED , DSl.
the x and y coordinates for that key into a 7-bit
(parallel) keycode signal. These circuits also 2C-3.2 Front Panel Keys
generate a KBD INT interrupt signal to the A23
PCB. When the A23 PCB services this interrupt The 5 1 front panel keys constitute an 8-bit by 8-bit
(via the AS PCB), the parallel keycode data is switch matrix. Each key of the matrix is a DPST
converted into serial format and sent to the momentary type switch (Figure 2C-3 , sheet 1). When
A23 PCB (via the AB PCB). a key is pressed, the x and y coordinate lines that
2C-2 67XXB MM
2C FRONT PANEL A2 FRONT PANEL CONTROL PCB, DETAILED CIRCUIT DESCRIPTION
are associated with that key are connected to protrude through the front panel. Integrated circuits
ground. U7-U10 and U12 are the LCD drivers that control
the numeric digits of the three displays.
The x coordinate lines (XO-X7), and y coordinate
lines, (YO-Y7), go to the keyboard encode circuits on The LCD drivers latch and decode the information
the A2 PCB (described below). The output of the from the internal S-bit bus (DO-D7) that comes from
encode circuits is converted to serial data format and the A2 Front Panel Control PCB. Each device is
then sent to the A23 Microprocessor PCB via the AS capable of controlling up to four 7-segment display
Serial 1/0 PCB. digits. Data lines DO-D3 contain the BCD code of the
character (0-9) to be displayed, and lines D4/D5 con
The SINGLE SWEEP push button (S54) is connected tain the address of the LCD digit.
to the X6 and Yl coordinate lines of the switch
matrix by diodes CRl and CR2, respectively. This LCD drivers U7-U9 control the nine digits of the
circuit performs the same function as the DPST FREQUENCY display (Figure 2C-3, sheet 3). LCD
function key switches described above. The x and y driver UlO controls the MODULATIONfTIME display
coordinates for this switch are processed in the same and U12 controls the LEVEL display. Each of these
manner described above. displays contain four digits (Figure 2C-3, sheet 4).
In addition to these driver circuits, the driver latches
on the A2 PCB control the non-numeric message
2C-3.3 LED Driver Circuits
characters of the three LCD displays (these circuits
Latches Ul-U6 drive 46 of the 49 front panel LED are described in the following paragraphs).
indicators (Figure 2C-3, sheet 2). Data from the
serial/parallel conversion circuits located on the A2 The OSC input (pin 36) of UlO is unconnected, which
PCB is sent to these latches via the internal 8-bit enables the internal 19 kHz oscillator. The OSC in
bus (D0-D7). This data is strobed into each latch by puts of drivers U7-U9 and U12 are grounded, which
a dedicated control strobe. These strobes are disables the internal oscillators of these devices. The
generated by the strobe decode circuits located on internal oscillator signal of UlO is internally divided
the A2 PCB. (The LED drive data is generated by by 12S to produce the BP signal at pin 5, which is
the A23 PCB and sent to the A2 PCB via the AS the backplane drive signal required by the LCDs.
PCB.) This signal is a 0 to 5V square wave with an ap
proximate frequency of 150 Hz.
NOTE:
The Q7 output of Ul controls the A2U26 The BP signal from UlO goes directly to the back
analog relay, that is part of the knob plane of the MODULATION/TIME display and to the
amplifier on the A2 PCB. (This output input of buffer amplifier UllA, which drives buffer
does not drive an LED indicator.) Relay amplifiers UllB-UllF. The combined outputs of
A2U26 is con trolled by the A23 UllB-UllF is the BP signal line that is the back
Microprocessor PCB and is used to con plane drive signal for the FREQUENCY and LEVEL
figure the amplifier input during the zero displays. This signal also goes to the display mes
ing processes. sage driver latches located on the A2 PCB.
67XXB MM 2C-3
A2 FRONT PANEL CONTROL PCB, DETAILED CIRCUIT DESCRIPTION 2C FRONT PANEL
2C-4 67XXB MM
2C FRONT PANEL FRONT PANEL ASSEMBLIES, TROUBLESHOOTING
Amplifier U27 has a gain of xlO. Diodes CR9 and meter is often used instead of the internal detector
CRlO limit the output of this amplifier to ap circuits of the synthesizer. This is done to eliminate
proximately ±BV. The output of U27 goes to the DVM uncertainties caused by long cables or the insertion
circuits on the Al 7 Analog Instruction PCB via the of an additional amplifier in the RF output path of
KNOB MON signal line. The output limiting the synthesizer.
provided by diodes CR9 and CRlO prevents over
loading of the Al7 PCB DVM circuits. The EXT LVL DET INPUT signal line and EXT
LVL DET REF line from the front panel EXT LEVEL
As part of the housekeeping routine that it performs BNC connector are connected directly to the A2 PCB
every 50 ms, the main microprocessor reads the via cable J6. Diodes CR4-CR7 limit the input signals
KNOB MON signal voltage via the DVM circuits. on these two lines to approximately ±5. 7V. Resistor
The value read is used to determine the necessary RB is the load for the external detector.
amount, and polarity, of change required for the
operational parameter currently open. (This is
Operational amplifier U28 is a unity gain, non-in
usually the last parameter entered by the operator.)
verting buffer for the detector input signal line; U29
is a differential amplifier/receiver that has a gain of
Since the Knob Amplifier is de coupled and of rela
x5. The output of this amplifier goes to the external
tively high gain, it is necessary for the main
ALC input circuits on the Al5 ALC PCB via the FP
microprocessor to periodically measure the de offset
ALC INPUT and FP ALC REF signal lines.
of this amplifier. During the knob amplifier zeroing
procedure, the KNOB AMP ZERO control line is set
Potentiometer Rl5 is used to adjust the input offset
high. This causes analog switch U26 to disconnect
of U29 to zero. This adjustment is performed during
the knob motor signal and to short the input of U27.
the calibration of the ALC circuits. For information
The main microprocessor reads the residual KNOB
regarding this adjustment, refer to the 67XXB Test
MON signal voltage via the DVM circuits and stores
and Calibration Manual.
this measurement value for use as the residual error
correction voltage.
2C-5 FRONT PANEL ASSEMBLIES,
When the microprocessor reads a voltage resulting TROUBLESHOOTING
from movement of the knob, it subtracts the residual
error correction value to determine the actual meas Refer to the troubleshooting information in the
urement value. This is especially important when beginning of this section (Section 2-System Descrip
the knob is turned very slowly, as the signal voltage tion and Trou bleshoo t i n g). This infor mation
produced is extremely small. This technique allows provides some common front panel trouble indica
the DECREASE/INCREASE knob to be used over a tions and procedures for locating the failed assembly.
wide range of rotational speeds.
2C-6 FRONT PANEL ASSEMBLIES,
2C-4.6 External Level Detector Preamplifier SERVICE SHEETS
The external ALC amplifier on the A2 PCB boosts Table 2C-l, on the first page of this section, refer
the external ALC signal to the propel' level for use ences the block diagrams, schematics, and parts
by the A15 ALC PCB. An external detector or power locator diagrams for the Al and A2 PCBs.
67XXB MM 2C-5/2C-6
2C FRONT PANEL
A1
s
DISPLAY DIGIT DISPLAY DIGIT DISPLAY DIGIT
DRIVERS DRIVER DRIVER
t
LED LATCH DRIVERS
LED'S (48)
LED DRIVER
NL E ELEDLED
'- �u- _ _ v
_ _ I
_ _ _ _ _ �__.� <)----�-
X-AXIS
STANDBY
[;]
LINE SWITCH
� - __ - -
O P ERAT E
����������� ���-
67XXB MM
FRONT PANEL BLOCK DIAGRAM
LPCB PARTOFA2FRONTPANELCONTROLPCB
}
A1 CONTROL I A2 CONTROL
STR�BES I STROBES
;
.: :, ...-----.
,,,,\
:
.·.
Ah I STRESS
\::::::::::::::::::::::::::: :':<::::::::: :::::::::::::::f::::::::::::: ::::
FP DATA
f DECODE SERIAU
CIRCUITS PARALLEL �� , FP STROBE TO AB PCB
_
I _:--< FP CLK c o N vE RTER
I __ _ _ _ _ _ _
�---------� I
IPARTOF FRONTPANEL I I
I I EXT ALC AMP
EXT LEVEL I
>1 >--� >------+-�I FP ALC INPUT
I (TO A15 PCB)@
I
I
I
KNOB M OTOR
I
I KNOB AMP
I
I �: '
�-i
�
!
KNOB MON
I >-------+-.;:>,(TO A15 PCB)
-- --- - Ir-- - - I
-----<. �-------- - L RF UNLEVELED
-- ------ ---+--< I 7
, !(FROM A1 PCB)
I PARALLEU I
SERIAL
CONVERTER 1---I--... FRONT PANEL OUT
KBD
JCTO AB PCB)
DECODE
CIRCUITS
IKBD INT
1------c:>, (TO A23 PCB)
..___
1
2C-7
�527
L::: :J 0 r=:::-p
CJ sO2e
EJEJ
P1
(From A2J1 P2 P3
via ribbon cables (From A2J2) (From
Via ribb
NOTE:
Leading zeros on
component number
references may be
disregarded.
A1FRONTPANELPCBPARTSLOCATOR 2C FRONTPANEL
NOTE:
U7, US, U10, U12,
P1 thru PS are mounted
on back side.
A1
FRONT PANEL
(Behind front casting;
POWER see removal procedure
Display in Section3)
0853
- - - - - - - -- - - - �c:n:;
i---------------1
=�I I U12 )
I l 05!!3
I . t=========�===j
6 - b.. --
2C-8 67XXBMM
0 1 2 3 4
X o., � "4 - I
1 ... P2 -lS
A �PLL- 5
� ,">- --=-- --�
12
/. <-
P4
/4 ...
-
,)-----<.-+-++-1--------------------------------------,
Pd (o
- P4 IG
SET :/
I
r-n
9 ti I I= I- FZ.I
.r-n
I
ANAIL6/'STEPI
SWEEP
r-n
I I NC.Ii: I DEC I::
511.E
r- l r-Tl
lsHrFTI
-
�;./
,_. � ...... - ,_. ....-
B swz. .,,,'-13 SW4
"lM/51
�
15-S-P SwE::P
DWE"� llHE
11=3-1=41 btc.RI w �
I11Jc.12:I
r--, r-'l r-ri .--
'---,_J
r-n r-11 r-h
.____ ...... �� '---'--'
-- '--- µ ->-' �
11 '>'N' '2. 'SV..I , '3 '5W'4 ".>IAo\5 SWl<O �l/v'.\I SvJB
� lt.r- •sl @] �
,---,
L--
- -n
r- r-h .--
.____,._. ,_. ,_. .______ ,_.
c Z.5 "9J..J -Lea SV..t Z7 -:,wze 'Sw29
l>-i A-l?,.:.E2�
�-"I
@] G
,--11 ,--h r=-n r=-
'SW 47
- ,_. �,_.
S\�148
-
�W.49
,_.
swso
-
D
PZ-IG
yo
s
,
YI
? -
'°1-24
YZ.
P4-8
Y3
?4- 7
Y"l
"4- 9
YS
PL.-1\
ye;
E
y7
... �2
,
- z.co
Cl21
""
µBDSOI
l
�
PS-I
-��-� v I ,
-·
- !D \SWEEP
y6 '354
SllJGLE
SUB Pj.,UEL
ASSE\.-\8l'i
F
., +5VD
'2. S4!0 s
lu>..iEI � P5-2.
c:.-i
I�z
• ..,.. ?'/ 3 '° 4
r�-' ;,_;i
�STA..�Dl3:;'.j
DIGGN..J�
:::; _
I :>SI D'S z.
\,,\V�3/'1.
�
f-\J4484
G
LAST USED
RS
UIZ.
R'-lCo
C.13
Li
0. I
SS4
tiSS3
H PS
CR-Z.
67XXB MM
5 6 7 8 9
SW I - 5.3
SW ITCH DETAIL
J CONNECTION DIA.Gelo..µ
A.l..l K�'>'S
NOTESo
l. <%21D MATCHING
U5£D
CON'<ECTIONS FOR SIGNAL FLAGS ARE
LOCATED BY SHEET NUMBER Ar-D GRID COORDINATE.
;; NOT
3. * DENOTES +5V RETURN.
2C-9
0 1 2 3 4
A
/
.. SVD
t
12\...l<O
I I I I
R\..JI ,> '21-llb
�no �2.W
R\..11 e1-J1
S
• , '<'WI F>l\.ll •
.
s '> �
3 2.
-z.zo Z20 22.0
4
2.20
5
2.2.0
5 <O ""
. .
-s·;
���---���--��--��� +-
'<"-13
��--<>--��__._���----- +SVD
� 2 z.J ,>
RW3
< 2.20 < 2.2.0 < 2.7..0
2 5
>
8
-
-:...�
-
"..
'.:. :
.::,
-
c�
c
�· -
,.._
-o
- I ::;;.
-t
- > > "'ws el.JS i2 WC:,
! I I I
I
;
'>'> Z.lO 2
; 3-i.:J.. ;;:> ws <NS . �Qt.JS ,; ;> R <0
K' IJ5 > ni
__
'3 4
\ 2. 2.0
B 2. 5 e:, 7
'> ::� '> -=.::.') .
Z'Z.0 2.0
> '2.?.0
- �;J
F
P2
DO
._]_;; I.
/� -
DI
c I
�
-- - -
:- :--
� l. :
/"'-c
D'I..
��
- "'
�
4
.
/"::;3
-
D3
/":..:..
::·�
I
�
"-
DS /['._:; ::
s 0
D-'
- -
DG!:>
.'�
/l'<.. i>
::s
- --
Dl
l ,, .:
Uo'D DR'J!'\ Z.
4
S'H!B
H
5 6 7 8 9
41
1 � DO-C7
r
• SVD
'..>· - 4
, n.. ot:- /:.,\.IP -z.e.12.0
'
I'..'DI 4 DI 01
l'..D 2. 7 "'
DZ O<.
l'.. D 3 5 D3 03 9
I'.. D<!. 13
D4 04
12.
'.. DS 14
DS 05
IS
"
11
� D <O
I'.. Dl 18 D<O Cl<> llO
;
Dl a,
19
II
..r:;,
-
t
U2.
GI.ID
\\
'(: '.)::isz�: DSZ7� DS2.�) '.)DSZ9\)'.)DS3���DS3���])532.\);')HDSE �33
� � -� � I <;<.JR,�I
'5.:I
20 i\JC.R/Dl:(l
DO 3
Ve.
2
i-e.wn:Pl ie.TE:PSIZ.I � E E e: e: J... ��
DO '.<o
'..DI 4
DI ;i, le;
'\.DZ. 7
DZ Qc. IQ
'\..D3 8 �
13
D Q?> 9
'\.04- <I
D4 Qc.
'\.OS id ·s
17
DS Q5 i(Q
f'"
'..D'O °"' G"
'\. Dl 18 19
D7 ,�,
Ii
>
/ D
GIJD
"4
+f
�4LS374- < RW<C > 12. \.,J(O 12.\..ll "2.IJC:O ;?.\--II RB
• sv .?,220
<.IJ<a '> ��'° > > z.:::;c '> 2-;_ I
C.8 s '-" 0 > 2.2.0
.?
•
,>
2.2?
>
2.ZO
>
>
>
I,,{
::;:1
4 7 I
�-�
'2.. 3 8
(.
!'..DO
�t> I
...£Q /(
3
"'
DCi
DI
·��
.,, ,
z.
s
� � � -� -�
�
Pw;:>,
� -� I" ;::-
R£CA.LLI
T
'\.DZ.
D�
� D4
l
B
13
DZ.
D3
:::i
03>
"'
"J
•'-
;-o.'\"l.32..<
<
��
>
�
= -
D4 04
,4
I'-- DS D:'> Sls :<:,i .Q c� :o:o.::>
I'.. D� t
'
D� -:;""
07
zyL:���
:9
.(!; 1::7 01
'I\ )
U\'.::>
�IJ
�
� S>JD
-- <;)' 74LS314
2C-10 67XXBMM
0 1 2
ICM7211AM
A 'A
37
38
�q,o,
�go
C.l� i'SV
iCM721\I
08 \A. 37 05 b..
D� . I lBo ID
·e " VG IB :,8 DSB
39 D<=t.::_
:::.
40 D"", "' " 1(. 39 DSC
1::; � '\.'-"'-=----=2-.'.I' 40 DSD
2. --s-� '
:E IE 2. DSE
- .:: ::;:;iF " !'-..DI
1i:: 4- DSF'
::nc::, "
�D2. '"'
iG 3 DSG
�
29
3'- � '.)\\ /,. " !'-.. DZ. 29 A.
2�
i Cl\ 0
i3Z ZA "= D<O
D3 -- """"' 7 ""-F>
::;1 3 ZB
8 I :::. --..,._ r'\. D :>;- 8 �C.
zc 8 D
2.� "3
9 :: I I ::; "
\.. D4 2� 9 D<O D
B - 10 DI\ E " �I
Pl
ZD
2.E 10 DG>E
\..� Cl\ "' " zr= IZ D<O i='
DS �2
-'..:! ::.z.
-------= ::;11 -:> "- DS
""\. 32. <:; '1 Dc<.G
DZ. Z
::; ::;t:.. '
'DG
'---=-
--'- --- 33
-_:'.;'j :) ·�e 31>. 13 DI!:>.
(S I 33
�cs 1 3B 14 D7B
:l ICC. "
C 1C..D '- c______ 34
3C. 15 DlC.
::1G:. " ::. s 2 3D 1<0 DlD
_::;:ic
'3E 17 DIE:
____,
5,_., ::·c;::. '
r-___ __
�
4D z3 ooo"
4� Z4 D85'
v DBF"
� F ZfO
.4G ZS D&:i'-
"
SP
D II
MAR
T M
w I I
-1N � If) '9 r-
ca<(
- -
U.
F z=
u
oOO
///
P l- 7
;:R:.a �w
--- · = ====
===
= ----= -----------
========== - --=====:J
========-
i='REG>
cS1 D
()ISP/;, - g.---------
'�9>i-=1 �
===��
{:,qo
�P 1�.,��- �-31 1 �Z2.�! =======
t=< !".Gl D1SP F ' P l -\ \
=====
== =========�
i=li?EGI Di'5P
=RE;'.;l Ci'5P DP 8
• F
>�- ===�==== ========
==�============= ==�
=========== ======= -
=:<EQ DISC DP7
- =�-:--= ===-==============�:_:___:::==============::..=
- - -·
67XXBMM
5 6 7 8 9
....
'-"M ICM7211AM
,.,
5
Cl�+oV
ve:.
V9 fA 37 DIA.
'
IB 38DIB '
39 DIC.
::
:;
'
'\ � D10.I 21
BO
I C..
ID 400\D
2 DIE
'\
'
'
- 1 .::
.. ' �DI 28 91 4 Dlt='
'
IG 3 DIG
\1=
:. '
' <O DZ.,,..,
2'l
' "\.DI. '\
7 D'2..e.
BL 7-l>o.
'
2.-
� '\. D� 3() 133 z.c 8 DZ.C..
. - 9 D2.0
� '\
D4 ?,I lO D'Z.li '
� r-.. DI ZE
� 12 DZ.� '
C'2.5
"2.-
"
02 2�
� ' C)S ::,1. II
"
� �A. 13 D::lt...
33
•
::. '\. )7 CSI 3- i.1. .031=1
�
'34 3C. '""o� ' '
I� 030
� '!,()
17 D3E '
CS?.
� 5
3S
19 05i:- '
� SP 3-
18 D:.G '\
� 3b
osc..
ZOD4"- '\
63 7t D4B'
A./>.
- LL..J'. di
'
ll. ..{ ro <!J u_ <1 ro \'.J IL 4:
Q99� <5' <!' <7' IO «l dl
uuooco DD D Cl OD �b ss
ro \!J
r- <ll
00 ��
ro \!7 LL <!_
19 WI
00 ��
1(1 w�� <t
4 c!l � LL 4 ltl <j LL � ID \!] u. -'.ID
3i m (fl (fl '° (\j"' NN
0 D. 00 OD Cl Q ao ao
: �l�
..,v '.l
�z ��
�- "'If)
�
� rn "' - �a fl:1l0 :&� �� (l)m @ It !I)r- I'r- 19r- I/)r- �� r-; r- r-- \l \.9 !:9 ��� �� \9 s �� In� ��I
(�a- � r- �I u:1 0-0-0-0-
_O'(]- Q'<l'O'
fj I/ f ////:;::::; // C/ I I
}',.: �tf1bd�
·
H
� '-�� a
.Ett�" WEE �1�'- 2frf !!
N�wl-�rr. -�������
"""
A r L- lln �
__
�� 1,9
w llJ
iS 00 g II' in �� �I� �
OD Q D�
co
5 DQ 0 D DO
r- r-
Do o o 0 5 .0 D Cl 0 0 li 0
I = i;::: � ;;.: rfl
! � 2; I �� �
.
// /
lo '''
/ // , ,, .
/ ', ' •
I
. I '' �
�
-
''\ '\
'\. l '\. 'r-..'
.
,.
'\.' r-.. ,J
2C-l112C-12
0 1 2 3 4
-+SV
i C M 7 2 \ I A I"\ + sv
C i t.
A �0 .t---!-
1
V- G
6
UIO
I A.
16 39
31
36
D I A.
DI B "
t!_
3
UI I
2. I C!. l:)
27 DI C
-
s 4
'\ DO
IC. �'
"
DI D
80
ID O
'
DIE
-
f'\ DI 18
I E. 2. ' 7
4-
SI <O
I F" DI F" " -
S BP 3E
I I D3E'- � ' "''
3F
19 031'"' -
N C. � osc 36 1 8 036'
7.0
�
' -
c 4A 'ZINC
G I.I D 46
t 4C E Nc
23
4 D Z4 N�
+ 5 V ITZZE>-- + S V 4 .c:
.l\ F.!:§_ NC.-
GND G
.q(j 25"
�
D
PZ -1�
HOD D I S P rn
H O O D I SP U.
µ O D Q 1 -;,p S
H O D D 1 SP r.;
H O D Dl '5 P �'
H O D D l '::>P t- z.
\.\OD D I SP I I 1
µoo D I SP i.u ) P:l - 5
P:,- 1 1
F
\JO C D I S P :C :: i
H O D DI S P 0/o
µoo D1 S P WI OTI-!
_, O D D IS D c; ;..- ::_
LVL DISP r1'
LVL DISP SE".TlJP
\.. V � Dt S D 6. E / T
L\t\.. !:)•SP E.X T
_v _ D , SP L EV EL
L V '- :>' S P I
G LV L D i S P SwP -..
"-V L '.:l ' S D 2.
LY - D 1 S P FOWE R
LVL D• S P OD 3
P4 - 13
LY L DP 2
PA-I
DISP
DP 1
P4-I
lvl D15p
L V L DI S P
P4 - 17
dB ) P'l - 19
P4- 2 1
LV l.. DI'S?
LV L DI S P ,Y
m
L V L 0 \ SP V I
67XXB MM
5 6 7 8 9
_,.,.
�C. I . I + sv
� 0 4049
� 1 V
G I ,!.,. 'e> 7 D I A
38 DIB
oo 27 eo
18
IC 39 DI C
'
40 D I C
-
f'-. t:> I 2.8 10
2. DI E
'
'\
T Po,-31iD BP
Bl
--<I
IE
II" Al
DIF '
'. D Z. Z9 82 1 6 I� D G '
2A � D 'Z
I>. '
-
I'.. 0 '3 30
S3
1 0 2. B '
--<
z.e
e D?.C. '
i'.. D 4 �I
DI
2C.
ZD
q 0'2,D '
-
2E
10 0 2. E. '
"-D'5 32. D Z 1 2. p;>j:"
Z I="
I I 0 2.C::. '
-
D"7
� CS. I
'3i
2-
1 3 0'3..
3;: 14 os e '
38
'I 1'5 0'3 C..
3C.
31 CS2. ICD 030 '\
'"°
11 D3 E: '
·"Ill! 3E
S B 1 q t>3F '\
P 3�
'
3G I P. �G
z.o
� osc. 4A Ne '
46 TI
IC r 9
35
<::. 14 1:> <4C B N c.
f"J N 1\J 4D n NC.
U12
4£ .li-
4 F � NC
� 4 (:,
?c:. '"
\.. ' " '' '
IC/"\/e l I A l't � " " '' '
" "" "
�fr
-
'
�I � N
v v w
� " LI. <{ fR � u.
�
D � � � o �a N
N
< IO <..': "- 4 Ill
-
u u
tl
� � �I�:�I � � � � � � � 1fi � � Iii ff! � rn � � ��I�
� (/ � � {
�
j':::f
�
.�
f=V/I;
Lr
;:.�f�f :�;,��L
flilT/ 'ff�
I --
I - C\J m <r 1(1 '9 r- <ll°' Q = � !!l :! � � c:: 2 - N l(l
�1
I DSS3 NN �� N
I Ul Ill D u w 0 \) w D'£
N N
m N
ftl I \J
-' l0
q a 0l o n 0 00
-
8o
- '" �
'\."
'" �
�
2C-13
P1 P2
( From A28J1 (From A28J2
via wire harness via wire harness
µ-•n�-.i!..\
'r. ·� � , ,.�
,.., .,.- [QLJ .������������������������-
rnLI •.-r-r �
��: : : : : : � � : � : :
�� �
.
E-:_ �-®frp
L __
1 ----$Ill�p�
7-J0- - �Q) -
"""'� [
J1 JS J2 J3
(To A1 P1 (To Knob Motor (To A1 P2 (To
via ribbon cable) via wire harness) via ribbon cable) via
NOTE:
Leading zeros on
component number
references may be
disregarded .
A2 FRONT PANEL CONTROL PCB PARTS LOCA TOR 2C FRONT PANEL
NOTE: A2
P1 , P2, and P4 FRONT PANEL CONTROL
are mounted (Behind front casting;
on back side. see removal procedure
in Section 3)
P4
(From A28J4
via wire harness
§�$
� · � =� �
<ao => $
FfI
J04
� ��@
I J4 JS
o A 1 P3 (To A 1 P4 EXT LEVEL Input
a ribbon cable) via ribbon cable) (Via wi,re harness
from front panel
BNC connector)
2C-14 67XXB MM
0 1 2 3 4
-.- s v 2
ce,
A � 0.1 ,4
UI
/41-K. 1<.A
.-- --
U30
- 4 1-1:::. 14 c
P l +5V 2
I C.. '3
F P D ATA
�0 .. 1 14
uz.
74 1-\ C I � w
I
G.\JD 9 l
CLR
7 3
B 1"
A
5 5
FP CLK
z s !5
e
+ C:N2
13
FD ST R e!
c
'-------------
+5V2
+ ?V2.
RN I Cl?
( L< P L )
I
J4-1
IOK
9
!OK
a 7
10\<. IOK
(0
l4 l(.p
UCO
74HC.l48
�
XO 0 N:>
J Z - IS I
D XI
x z. .J '-1 - !:> 2.
'
c
Al
X .3 J '-! -IZ. 3
J 4 - (o AZ (,,,
.X 4 4
XS J '-1 - 1 0 5
J L.1 - 4- 14 I
XG c;, GS
J4 - 3 7 t
X7
R t.J I s 4 3 2. El EO I SN C •
(4 P L )
+ 5V 10K. I O K.. \OK IOK.
4
5
E
+5V
-t-t:;;N 2
C I C,,
�- 1
Rl\J l. U'?i
74 1 K148
( 4 PL ) I OK I OK.. 10" \OK I'=>
9 8 --, G lO 9
YO 0 A
Y I I I I
I Z. 7
y z. 2. Al
'( 3 13
3
F '(4 I 4-
Ys l 5
3 �
Y <D 4
Y7 7
s 4 - 2 s
l< t...12 El EO
'.4 P'.... j
+SV IOK IOK IOK IOK
P l
II
G KEY NC
L l?F l l N L E VE L E D �I "' L 'lF U N L E V E L E D
+- 2 4 V I �9 I "' +- 2 4 V I
<'10 I
+ 1 5 VA .,. t- 1 5 V A LI
. I
+ S VD 8 "' t 5 V I
+I C l
- 1 5VA
G N D G
<'21
(I I
I
"' - I 5 V A
: .9 U H
� 10
�Ziv
L 2
P4
H �r111 ... t-5 v 2
+1 C 2
IO
GND G
l ,9 U H
JI 2
67XXB MM
+24 V G )5 I .,. +- 2 4 V G
J
5 6 7 8 9
--
----------
----.-.
------------------------------------ ..........�
.... . �� DO- D 7
L---1f!7.1� DO - D 7
f's= "C:ESl""'-lbTIOIJ')
Ll>.'>"T u'iEI) \..biu<c.D
...i � P3
c.Fll O
c;!, �
R2 3
P,f.J "'.:>
P4
L':>
j c:;,
.. 5V
C. I B . o . \
�
7
L R F U N L E V ELED � L R F UNL E V E L E D
74 HC7 4
+ 24 V G -+1. + 2 4 V G
JI �
+ 24 V I . I < +2 4 V I S PARE
2C-15
0 1 2 3 4
--
DO - D7 '
' 'II 'II
BP
:r 3 - <0
UI Z.
... 5v 2 �0 0. 1
A C.D4 05 4-B
r--.0 ._ 0 9
llo �
�
D Z.
DI
t'--.. D I I I
QZ S
QI
!'-.. DZ. 1 3
03 Q3 4
D3 1 5 0
2 DF
4 Q4 3 +SV2�0 0. 1
_J_Q STB I
___fl_ STB 2.
l'+ ::T B .3
COLl054B 1/o
Ul"3
�
�E
______!_ 5TB 4
� DI Q I lo
B � 02. QZ. 5
r2 � D3 Q.3 4-
�1
18
w �STBI
� D4
z. DF
5TB Z
STB 5
Q4 3
U l4
+svc
CD405L!-B / G:> �
o.i
VE
5TB 4-
� Pl Gil Co
FREQ. DIS.P D P '5TRB � QZ. s
7a
� 02.
4
I � D3
�
D4
Q3 3
QL+
�2�
........11 STBI
18 +sv2
c 2. DF
� ___lQ U\5
C l)Ll.D5Lt B
� 5T84
� STB 3
STB 'Z
DI QI
l'[)Lj. 9
� DZ.
1141
Ql.
le
s
I VE. 8 � 03
DlJ.
Q3 4
Ql4
3
�STBI
�
2. D F
�· STB 2
UI
cc
D STB 3
FREQ DISP M""6 $TR.B ..!!.::!:. I ST B 4 �
7 VE
'-Q.
I a
...__
:gD;
-
U'
H
5 6 7 8 9
J I
I 18
_,
FR E Q D l $ P D P I
/9
n; E.Q D l :S P DP 2.
1 0'
FR_ EQ D I S P DP 3
17 F;::_ b::i D I S P DP 4
I
I
I
I 14
FRIi=;Q DI 5>P DP 5
I S'
FR EQ D t SP DP �
12
FR Eq_ Dt5P DP 7
FR EQ O I SP DP 8
13
I
I
I
FREQ DISP - F
2. 1
FR EQ D l 5 P CW
7
FR EQ DISP .6.
�
FR EQ Dl5P SWEEP
zc
J3-8
F R EQ Dl'=:>P GH i!.
.J I- I I F REQ D15P F
J J -l3
F R E Q Dl!:>P MAR K E �
J3-f0
U l (o
+ sve �3 ./
F REQ 01$P E X T RE F
CD�B tlo � J2
I
I�
DO 9 01 QI "°
Qt. I i;;.
I
13 M MOD Dl':>F' F f-1
� D� QQC+3 �4
� DZ. OD Dt 5P A \-;\
18 M o o Dl 5 P E l< T
D�
DF
-----1. !:>TB I U l7
+ :sv e �24 ,/ I
ZI
' M O D Dl 5P S
�
I
__JQ
,_____l!. ST B Z. CDl4<>�e> l<o I
I
..__t.:I: STB 3 9 (o 19_,
M OD D I SP m
r-1
r-,.DLI-
......___..!_ STB 4 11 DZ. Q Z. 5
01 Gl l
zo, M O
VE I'.� D D l 5P �
13 Z2. M 00
D3 Q!> 14 01 5p K
r-.,.Oto
,D7 IS D'+ Q� � Z3
e
z OF
ST!i& I UIB
+5V 2,e5 0. /
MOD DI S P M
�
CDl+05'+ & I (o
� 5TB 2.
�1
.. 5Te 3 !'DO 9 D I QI "' J2-24
MOD O l :S P
I o H�
TB �- DI I I ·-i... �'"' J Z -Z':l
lvlOD Dl 5P /V
J3- IS'
D3 Q3 4
�
OD 0 1 � p
r VE. 8
�
� D'+ <¥� 3
2
DF +5V 2 �z�
�
J3-1�; M MOD D\ S P
Alvl
o/o
� STI!l I UI�
'O' .__.._@ STS Z coi+oO-i.+B l(o I J3
,__l'.± 5TB � QI
I
r-1 01 Iv\ OD O I S P
�
� STe>'+- DEN
II
s
r-.04- 9
� DZ. G)Z. �, DISP OVE R RAN G E
VE M oo
� D3 RAT E:
4- 7.
I
Q3 3 MOD D I SP
D'+ Q4 M OD D\ �P W t DT i-1
Plsoa
5
IB z DF
� 5TB Z
1
STB 3
5TB 4-
VE
r2 18
w
Figure 2C-5. A2 Front Panel Control PCB
Schematic Diagram (Sheet 2 of 3)
6700-D-31 702-3 (Rev. H)
2C-16 67XXB MM
0 1 2 3 4
00 - D? 1/f!>A
" ...
+SV��l
"" "'Ii
BP 1�
A �Jg054B j 1eo
<ri
I
QI
�DO � 01
�I D 3 D2 � z. 5
03 4 3
�
� Di.+ z. 4>4
_____JQ ST B I
DF
UZ. I
CD4051fB
+ 5 V2
l��
C2B
0. 1
�'y
R
- 7
?... O F
I O SIB
I
STB ?...
STe> 3
12�
�4051.f.B
UfZ
11o
QI
lv\OD LVL DI SP DP ST R B ..l..__ STB 4 � DI
E � DZ. Q2 �
v ...� 03
1 � Dlt
Q31"'-
G>i+ .3
c
iv
18
�5TBI
z OF
5T B
45TB3
Z
2.
UZ.3
CD4-05'+6
+�
V2
�
I�� 0.1
9 0 1 QI �
LVL
LVL
D I SP MSC::i oTRB
DI S P M$6 5TR8
!ill!:'
2. -,-:;z
J I-'+
� VEI $T B 4
·
,D*
"DE>
"' D'-
,07
1 1 DZ. Q2. Jl_
13 D3 Q 3
I � D4- QQ. i::
KNOB A IV'I P ZER.O '' la
2. DF
D
CSV 2
R2.0
K N OB AMP
c,� CRIO
_./
w·
� 1 0 STB I
STB Z.
"=>TB 3
7 5T0 4
''"� Ul&>
D
U Z.(o
.r
I N15SA
.RZ.
...
?
I N155A
I VE 8
I 1 00 1<.
062 00 "2. DC:oZ.00 � 'V
.-J:i...... .-J:i...... c�
+ 15\/
D./
J5 "1. I
E 2' 4 s
I OK
K NOB. MOTO R. IN PU/
'
1CR I R.5
I N156A 100
I ( 2. PL )
R 'Z.
1C
I
KNOB MOTOR INPUI 3 �--t-��������-+������--�--'=--i
REF·>,,.+-
R9
.t C'::>
0./
2.5SK
F
- ISV
+15\/
-t l '::>VD RZZ
4 �14
+ 1 5 V A
+ 5V 2
- 1 5V A
IIIIlD>--- + 1 5 V
!I2BD>-- + 5 V 2
IJZEID:--. - 1 5 V
RI
o. l l K
CRB
\Nl51A.
5. I V
EXT ALC AMP
H GND G - 15V
GND G
67XXB MM
5 6 7 8 9
"" "
MOD O I SP DP I
JZ- 10,
M O D D 1 5P DP Z.
JZ- 1 1,
MOD D1$P D P 3
Jt-1?.;
LVL DISP DP I
J4 -1Co.:
J4 -16,
L\J L Dt5P DP 2.
Jl.i- 13,.
L\J L OISP DP 3
J3- 3,. MOD D l 5P PULSE:
J 3 - Z,
MOD D I S P E'XT
Jl.l-Z5
JQ41A
LVL 0 1 � ? V (Z.)
L. V L 0 1 5 P OFF 5 E r
J3-Z3,. L V L Dl�P PW R
J3_7c;. LVL D I S P N O T CAL
J 3
�
' I I
l'Y L D\'5P !:::.
I
� Zl' LV L DISP
LVL a sp
EXT
#
�
I
+':>Y2
ii
UZ.'+
CD405L+B llD '
I
9
DI
I� I
i
zo, LVL D I S P -
I I DZ
r-..00
zz.· LVL. Dl�I"
Q I l ln
Q2. Is I
"02. ' "' D � G 3 "' z� LVL DISP
r-..0 1
l..
I !> D't �'+ ltlll· Z<P
+sv a
LVL
D I S� LE'Y E L
�
'-D.3
? DF
5TB I
5TB Z.
U2.5 �32�
CDL+OSL+B II.<:>
O. /
J4
1 STB .3 17
Q I (# L V L OISP dB
.
7 .ST B 4-
I
PZ Q Z !6
DI
l'.D4 9
....o�
l'.05 I I
13 0 3 G:31a 21,
1�; LVL D l 5P
LVL 'O l 'SP
rn
µ...
07 I� Z 3,
r vrc. 8 D "+ G '-1 3 LVL D1 5 P V(I)
�iY
��� '
t. STl3 Z
q. STB �
I STe 4
r2 ve e
·u PI 2
<-----+-�� K NO B MON
r----+
1�" GN D G
VNC� K EY
P
I ) GN D G
14
Rf7
w NC� KEY
100 3
I
FP ALC
� FP ALC
RIB
R.E I=
I N PUT
2C- 17/2C-18
20-INPUTS/OUTPUTS 2D-2 INPUTS/OUTPUTS ASSEMBLIES,
A27 AND P/O A29 PCBs OVERALL DESCRIPTION
For information pertaining to the rear panel input/ a. A27 Auxiliary 110 PCB
output signal lines not routed through-or processed The A27 Aux 110 PCB routes most of the 110
by-the A27/A29 PCBs, refer to Section 2M-Mother interface signals to/from the internal PCB as
board/Interconnections . For information pertaining semblies of the 67XXB to the appropriate rear
to the front panel input signal lines, refer to Sec panel connectors. Additionally, relay A27Kl
tion 2M and to Section 2C-Front Panel. generates the drive signal that is routed to the
rear panel PEN LIFT BNC connector. This signal
is used to interface with data plotters.
Table 2D-1. Inputs/Outputs Service Information
67XXB MM 2D-1
A27 AUXILIARY VO PCB, DETAILED CIRCUIT DESCRIPTION 2D INPUTS/OUTPUTS
2D-3 A27 AUXILIARY 1/0 PCB, DETAILED microprocessor data bus lines, DO-D7, into the
CIRCUIT DESCRIPTION various control latches and DACs throughout the
A29 PCB. This data controls the operation of the VO
Refer to the A27 PCB schematic, Figure 2D-4, during
interface and microwave component drive circuits
the following description.
located on this PCB.
Connector Jl is a 14-pin DIL connector that connects The A23 Microprocessor PCB reads the state of the
via a ribbon cable to 11 of the rear panel BNC con Ul outputs associated with these signals ap
nectors (see Figure 2D-4). The AUXILIARY 1/0 con proximately every 50 ms. It then initiates ap
nector, J2, is a 25-pin D-type connector. This connec propriate action, as required.
tor extends through, and mounts to, the rear panel.
NAND gates U2B and U2C comprise a latch that
Relay Kl provides the switch closure for the rear senses the state of the L RF UNLVLD signal. When
panel PEN LIFT BNC connector signal. It is control the output of U2C goes high, the A23 Microprocessor
led by the PEN LIFT RELAY DRI VE signal from the reads the associated Ul output and determines that
A29 Rear Panel Interface PCB to provide normally an unleveled condition has occurred. It then sends
open or normally closed operation during sweep the proper signals to U6 to reset U2B/U2C. (This
retrace. This mode of operation is set by the A23 operation is used during the automatic ALC loop
Microprocessor PCB in response to instructions gain calibration that is initiated via the front panel
entered via the front panel keys or by GPIB com EXT GAIN CAL key.)
mands. (Refer to the 67XXB Swept Frequency Syn
thesizer Operating Manual.) When the L MEM SEQ IN signal from the rear panel
goes low, the change in state is sensed by the A23
2D-4 A29 REAR PANEL INTERFACE PCB, Microprocessor PCB via Ul. It then sequences from
DETAILED CIRCUIT DESCRIPTION the current front panel setup to the next setup that
is stored in memory.
Refer to the overall block diagram of the A29 PCB
(Figure 2D-2) and to the A29 PCB schematic (Fig The L SWEEP DWELL IN signal from the rear
ure 2D-6) during the following description. panel is sensed in the same manner. When the syn
thesizer is in the sweep mode and this signal goes
low, the A23 Microprocessor PCB causes the sweep
2D-4.1 Digital Control Circuits
to dwell (stop and wait). The duration of the dwell
Decoder chips U6 and U7 decode the PAO-PA2, signal is monitored by the A23 microprocessor to
LPA18 and LPA20 address lines from the A23 sense ':.he length of the sweep dwell. (The L SWEEP
Microprocessor PCB. The outputs of these devices DWELL IN signal also goes to the Al7 Analog In
are strobe pulses t h a t load data from the struction PCB sweep ramp control circuits.)
2D-2 67XXB MM
2D INPUTS/OUTPUTS A29 REAR PANEL INTERFACE PCB, DETAILED CIRCUIT DESCRIPTION
2D-4.3 External Instrument Interface Circuits The Q5, Qs and Q1 outputs of U4 are used in con
junction with operational amplifier U5C to produce
The Qo and Qi outputs of data latch U4 are used to the SEQ SYNC signal. During retrace and band
generate t h e R E TRACE BLANK and BA N D switch blanking, the Q1 output of U4 goes high . This
SWITCH BLANK signals. Operational amplifiers causes the output U5C to go to a TI'L high level
U5A and U5B invert these U4 outputs to provide (==+5V) .
negative polarity versions of the retrace and
bandswitch blanking signals. Integrated circuit For sweep markers that were selected via the front
switch U36 is controlled by the Q2 output of U4 to panel keys as MARKER SELECT, INTENSITY, the
select either the positive or negative versions of both marker output signal from U4, Q5 drives the output
signals. The state of this signal is set by the A23 of U5C to --5V during the positive portion of the
Microprocessor PCB in response to instructions marker signal. For sweep markers that were
entered via the front panel keys or by GPIB com selected as MARKER SELECT, VIDEO (i.e., en
mands. The outputs of U36 are routed to the rear hanced markers), the Q6 output of U4 also goes high
panel RETRA CE BLANK OUTPUT and BAND during those particular marker periods. This drives
SWITCH BLANK OUTPUT BNC connectors via the the output of U5C to -lOV during the positive
A27 PCB. portion of the marker signal. The SEQ SYNC signal
is routed to the rear panel SEQ SYNC OUTPUT BNC
The Q4 output of U4 drives Q19 to produce the PEN connector via the A27 PCB.
LIFI' RELAY DRIVE signal. The Qa and Qs outputs
of U4 are used as the LOCK OUTPUT and MARKER The Qo and Qi outputs of data latch U8 are used as
outputs, respectively. These signals are routed to the the L ALT 1 and L ALT 2 outputs, respectively. These
rear panel PEN LIFT, LOCK OUTPUT and MARKER signals are routed to the A27 PCB and distributed
OUTPUT BNC connectors via the A27 PCB. to the rear panel AUX 1/0 connector as the L ALTER-
67XXB
REAR PANEL
{
-
? 11
c:"
,
INPUT/OUTPUT
SIGNALS FROM . .
OTHER PCB•' . .
-
·'
) INPUT/OUTPUT
BNC CONNECTORS
�
A29 REAR PANEL
r-
..
}
INTERFACE PCB � �
ADDRESS AND ;·� -� .
.
DRIVE SIGNALS
CONTROL DATA
. -i:-
�
TO MICROWAVE
(FROMA23
MICROPROCESSOR PCB)
. DECK COMPONENTS � II
�
r� :
INPUT/OUTPUT SIGNALS
FROM A15 AND A17
.
rlT.. (
PCB•, ETC.
. J1
A2.7 AUXILIARY
1/0 PCB
� - -
. .
. .
- J: --
AUX 1/0
1 1-- -
CONNECTOR
-
L SWP DWELL -- �
(TOA17 PCB)
, .....
-
L EXT SWP TRIG
(FROMA23
MICROPROCESSOR PCB)
67XXB MM 2D-3
INPUTS/OUTPUTS ASSEMBLIES, TROUBLESHOOTING 20 INPUTS/OUTPUTS
NATE 1 and L ALTERNATE EN signals. These sig Each of the drivers is identical except for the resis
nals are used with the WILTRON 660 series network tors determining the output current to the PIN
analyzers in the alternate sweep mode of operation. switch; therefore, only one driver circuit is described.
Refer to the PIN drive circuit for the 2-8 GHz pole
of the main RF output multiplex switch that is com
2D-4.4 lOV Horiz Output Signal Circuits prised of analog switch U26A and driver transistors
Q6 and U30B.
The data for DAC UlO is first latched onto control
latch US and data latch U9. This data is then strobed
into the internal latches of UlO. During the CW or When the Qo output of U31 is high, the contacts of
step sweep modes of operation, the output of DAC U26A are open and the switch driver is in the off
UlO (via UllA ) is switched to the input of buffer mode. In this condition, U30B is saturated. The cur
amplifier UllB by analog switch Ul2A. In the rent through R52 determines the current to the
analog sweep mode, the ramp signal from the Al 7 2 to S GHz pole of the main RF output multiplexing
Analog Instruction PCB is switched to the input of switch and turns it off. Transistor Q6 is turned off.
UllB by analog switch Ul2D. The output of UllB
is the signal that is routed to the rear panel HORIZ When the Qo output of U31 goes low, the contacts of
OUT BNC connector via the Al 7 PCB. U26A close. Transistor Q6 is turned on and supplies
current through R56 to the PIN switch, turning it
on. Transistor U30B is biased off.
2D-4.5 Step Attenuator and R elay Drivers
The step attenuator driver circuits are used only for 2D-4. 7 ALC Loop 110 Interface Circuits
those units equipped with Options 2A, 2B or 2C. The ALC Loop circuits located on the A29 PCB are
Refer to sheet 3 of Figure 2D-6. Data latch US con described in Section 2K-ALC I Pulse Modulation.
trols the driver circuits for the microwave deck step These circuits are shown as shaded areas in Fig
attenuator and spare relays. ure 2D-2. The set of schematic diagrams contained
in Figure 2D-6 includes these circuits (this is done
The data that control these circuits are latched from in order to maintain the continuity of the A29 PCB
the data bus into US. The dual open collector line service information presented in this manual). Note
drivers, U20 -U23, are used to drive the step at that the ALC loop circuitry is electrically separate
tenuator actuator coils. Inverters Ul 7C-Ul 7F in from that of the other A29 PCB 1/0 interface and
vert the signals to one input of each of the dual microwave drive circuitry. Each of these circuit
drivers. This configuration provides opposite drive groups has separate power supply and ground refer
signals to the ATTN and THRU coils of each at ences.
tenuator section. The output transistor of the dual
drivers are protected by the diodes on each output. 2D-5 INPUTS/OUTPUTS ASSEMBLIES,
TROUBLESHOOTING
Optional relay drivers U19 and U35 operate in the
Refer to the troubleshooting information located in
same manner as described above. The outputs of
the beginning of this section (Section 2-System
Ul9/U35 drive current driver transistors Ql, Q2,
Description and Troubleshooting). This information
Q13 and Ql4, which drive the (optional function)
provides a list of error codes that may be displayed
relays. The driver transistors are protected by the
as a result of failures in the input/output assemblies
diodes on each output.
and probable causes of the failures.
2D-4 67XXB MM
20 INPUTS/OUTPUTS
DATA
AND
CONTROL I-------+---�
LATCHES
INTERNAL DATA/
U8,U9 CONTROL BUS CWHORIZ
DAC
U10
-10V
- f--------!li---<I>-••-_.� •••••.
+10V RAMP?----------t.>.-t---1
�l� j /
·=
1!::1
(FROM A17 PCB)
D ������ � ��
:
2 P
� )::·::::::··.::-":' ::·:. "··,··:·:·:::'.'.'"":·::·:: : :: ::=. :=:= : :
":: :=
::;�;:;���
L PS LOCK MON
(FROM A25 PCB)
.o----
TRl-STATE
BUFFER
U1
·"{:j:: \ ;::l!;'::::::::•::::::;:;:•:;:,;:;:;:/='t:::-.1
:;:•:::::::::::::: ::::::::::::::::::•::::::::::::::•:::::::::::::::::::::::::::::::::::::::::::::
DATA
LATCH
U4
LXTAL OVEN
(FROM REF OSC ASSY)
DATA
LATCHES
ill!i!!!illiillll..i
U18, U24,
U31
L RF UNLEVELED >---
LATCH
U2
(FROM A25 PCB)
+10V
67XXB MM
A29 Rear Panel Interface PCB Block Diagram
�-------� L ALT 1*
· �-
-����-��-----� L ALT 2*
J -�:
: V/GHzOUT*
-
ALC SLOPE*
i--- --
RETRACEJ
RETRACE BLANK*
l
r;
}
SEQ SYNC*
10dB
ATTENUATOR
SWITCH DRIVER 40dB 1 TO STEP
CIRCUITS 20dB ATTENUTATOR ***
(8)
}
40dB2
2-8
PIN SWITCH
DRIVER 8 12.4 TO RF OUTPUT
}
•
8-12A Dft1
PIN SWITCH
:: ;: }
8 • 12A DR2 TO DPDT
DRIVER
CIRCUITS
12.4 • 20 DR (T2) PIN SWITCH ***
26.5-40 DR
(5)
)
12.4 • 20 DR (T4
TO CONTROL L DOUBLER/AMP SEL
--------�12.4 • 20 MODULATORS***
2-8
--------'�20-26.5 PIN SWITCH
8·12.4 TO SAMPLER
DRIVER
12A • 20 MULTIPLEXER ***
26.5. 40 CIRCUITS
20 -26.5
TO FREQ DOUBLER# (5)
}
DOWN CONV INPUT SW
L DOWN CONV SEL
* TO REAR PANEL VIA A27 PCB 0.1. 2
•• SHADED AREAS ARE ALC LOOP CIRCUITS PIN SWITCH
DRIVER 2-3.5 TO SWITCHED
(REFER TO SECTION 2K)
CIRCUITS 3.5. 6 FILTER***
***LOCATED ON MICROWAVE DECK
(4)
#OPTIONAL 6·8
2D-5
J1
Rear Panel
AUX 1/0
Connector
J2
( Receives ribbon
cable from
0 0
rear panel
BNC connectors)
J01
c;
J02
l
I
P1 Ribbon Cable
I
J I
......
-u
0
'
i
'
(ToA28J27) I I
I l K01
I
I I I
I I
I
:
!
\ \ i. W01
L
A27AUX110 PCB PARTS LOCATOR DIAGRAM
2D-6 67XXB MM
0 1 2 3 4
P1
LOCK OUTPUT
0
RETRACE BLANK
12
BAND SW BLANK
8
V/GHZ
7
1ov HORIZ OUT
B
5
S E Q SYNC
3
MARKER
2
L EXT SWP T R I G ) I
4 I
SWP DWELL INPUT
c
K1
15 1
>--������--�������---...�--;�
PEN L I FT
RELAY DRIVE
�
D
l--0---
--:-=-
13___,
rh I
L
E 1 I
L ALTERN ATE 1
6
L ALTERNATE EN
25
SPARE
SPARE 2
25
23
SPARE 3
24 I
SPARE 4
21
SPARE 5
F 22
SPARE 5
19
SPARE 7
20 I
SPARE 8
13
SPARE OUT
14
SPARE OUT 2
16
SPARE OUT 3
17 I 2
G +5V @
Wl
GND G
NOTES:
67XXBMM
5 6 7 8 9
J1
11
L MEM SEQ INPUT
I
2
I HORIZ OUT
I
1
I SEQ SYNC
I
�---.---1--+--f---+--+-·�----,-1-"8'-<\, MARKER
�--.�--+--l-----1---+--t--,:--4'--<:, SWEEP TRIGGER
I
.-�f----1�-+�-+�--+�-+-�-+-�+-�����--,,�6�,, SWP DWELL INPUT
l
1 5
1--�1------i�-t- ---+�-+�-t-�-!-�-t-������������ �-=--<_� PEN LIFT
J2
I 9
I LOCK OUTPUT
: S
I
RETRACE BLANKING
'-�������,:��1�4-,/, V/GHZ
L------------------ :----c
1 (
r
I
HORIZ OUT
I 3
I SEQ SYNC
�
·
5 MARKER
-------------
-·� --- -- - -
-
,
3
- -� 1� -.; SWEEP TRIGGER
1B
L SWP DWELL INPUT
7
L ALTERNATE
4
L ALTERNATE EN
24
SPARE
23
SPARE 2
22
SPARE 3
21
SPARE 4
9
1
SPARE 5
17
SPARE 6 1.·'.11 I �O RIGHI S Lf:GEND
15 CONT�ACT NO
SPARE 7
CO <:9C· 0'1 \10Rf;f\'J �ILL ':•' :.r;;
25
WIL TRGN _'ARV�S ·-
"""'
12
+SV
NOTE:
I 2 Ji TO REAR PANEL BNC CONNECTORS.
F
J2 TO REAR PANEL AUX I/0 CONNECTOR.
GND
2D-7
A29 REAR PANEL INTERFACE
(As viewed from bottom of instrument)
J10 J1 2
ATTENUATOR DRIVE J11 ATTENUATOR
( To Optional Attenuator) (Optional) (Optiona
\'S11 Ji;(/ I
2::y:2:1:::1 2::YXi:]
J1
J7
BAND0 and/or BAND1
P1 FILTER DRIVE
MOD DRVR
(ToA28J14 (Used in all units with
J2 Vii
via ribbon cable) a 2-8 GHz band)
BAND2
MOD DRVR To RF Deck J6 J9
J3 Control Modulators SWITCH DRIVE
BAND3 and/or BAND5 SAMI
(Used in all (Usec
MOD DRVR multi-band units)
J4
JS
BAND4
(Used in all units with
MOD DRVR
Frequency Doubler)
A29 REAR PANEL INTERFACE PCB PARTS LOCATOR 20 INPUTS/OUTPUTS
A29
REAR PANEL
INTERFACE
(Bottom Side)
�DRIVER
lal)
P2 P3
(ToA28J19 (ToA28J23
r ribbon cable) via ribbon cable)
20-8 67XXBMM
0 1 2 3 4
P2
DO ,1
I ,
)2 +5V@
/
Di
I
D2 )3
I /
1 RN1, 10K
i;
)4 /
/
D3
A I -------1
)5 +5v@
�--
D4
I
)6
/
D5
)7
I
I I II
,�(:':i
/
6
0 / I > > > > >
D7
>e I I < < ' ' I
P Ri. 100
9 3 3 �7-�8__,4 5
- 2-+_ ______--,- 02 18 DD /
L c + + -U
MEM SEQ IN r- �__,_6 -+ _ _,1Al !Yi
-..--+- ------- 0-4--1 16 01 /
_____
�- - -+-- -----+---...-+-+-
___,,
14 D2 /
__ _
R2. 100 06
I
'
II 1A3 1Y3
12 0
3/
/2 �1A4 1Y4
B
PS LOCK MON '
L XTAL OVEN
/
f-5
I
Pl
----,---
I
I �''' �'''
1N751A ·, o 1N751A
-i -- ------------------+------+----------
'--- -----
..___________
"--'f'l
--,
1
"------1l""2 A1
r---+---+--- -- -- ---,_,, 3__, 2A2
15
_--12A3
17- _,2A4
2Y1
2Y2
2Y3
2Y4
09
07
05
03
4
D /
D5 /
6
0 /
0
7
/
6 I 09 �1EN
' I
L RF UNLEVELED
/
08 �2EN U1
U2C
'
10 GND
I
�
I
I HCTOO O HCT244
+sv@
GNO G
� i 1 * RN2. \OK
-
05
-��. -:� !
-
----+---+--+--+---!f--- --c-
0 c--!6 I ;A:3 •Y3 �- �--C
["-,_�
f-"'-'-
---"VV'v---'-"-'-"-C-"----· -- - --+- ---+--+--- + -+--0-----__,_-+--t- - +--=0�0__, 1A4 ;Y4 , � __Q)__/ I'-�
�-../
'
- --+-·- --t---+---!f--+--<1 -- + --- + +---t- - 11
- -- -1 ---- -12A 1 2Y 1 �� '·,�
13
2A2 2Y2 ��
15 6
�
f----<'---"VV'v-��- - -- - ---- -+- ---+--+- ...--t--1---+---l--+- -t-- +- �--12A 3 2Y3� / �
----
'
0
<-----�·VV',�--------- ---+----+-n-..-n--+--+--n-+-->---+---+--+----+--1---1 2A4 2Y4 °3 7 o7 ' .
JEN *
n 7
-2k
2EN U3
� � � ill £ £ £ £
+5V@<J-..--- - � -.----1i �
1 16
I
0 1
i 1N751A x
8Lr\�\Y�Lf ,.1\Y*Y"Y *
� � ft, {';,
GNO
(O
'HCT2 44
r
P2 vcc
U6 �
I
HC 138
'..g/\g/\g/\g/\(Y 0 \(Y\gl
15
PAO
PA1
/10 1
)
<-- 1-1° 1-
<--� '1- -
--+
+-
-+-
+-+---0� � 8
01
-
- 02� A
T YO D�
Yl
>--
U� 14
>--
1--------------------l-t------------�
=----+--- --------
� 1�3-- -t- --
__ _
- ---
- ---------------+- -+-----------
- ---t-t- ----------- �
I
)12 3 Y2 D- -
PA2 c 1 2
E
Y3 D-- _ __-+------------ ---- --+--+- -- -------- --+--+--+-�
El 11
' I .___2§_
I 04 y 4 ,�,__ _ __--+------------------+-�
E2A 1�0 ---+----------------- �
/14 1 Y 5 C�>--'-
LPA20 .-,--1r---+--+-
I I
�
-+--+--u E 28
GNO
Y7 �NC
O9
y6 r,__ __--1
07
+5V@
� '
49
- 16
-
8
,- � ..,
VCC
I
I ��
U7
HCT138 ,, 15
0 YO __ ________
�
: A
I O� Yi o- �14 -'--- ------ -
13 -
03 B Y2 L;; >-- ,,---------
F
C 12 -
1 06 Y3 L� >-- -------
1
� El 1 1
� �____
I y4 o-
E2A 10
LPA18
/
�, 13 1- 05 D E2B Y5 L;� >--:-- ,,------- -
___
h_ 9
� l -------- - ------- --- --- --- -----+-
Y6 u_ 0 ___ ____
07
+5V@ Y �
3 7
-----
L2 L
-- ---!:;>
i
GND
I
15 I I +5V G) _____.08
GND D 2
16 1.9 � 100 �3
'
1 ! 2 2 �
17 J'; . 2
L1 ;
0
G
+5VO 10 1 w v A29 REAR PANEL IN.
+svQ)
Cl
+15VA
� +15VA
1 9
+ 1. UNLESS OTHERWIS
RESISTANCES ARE
CAPAC ITANC ES AR
VR1 INDUCTANCES ARE
21 1 L4 7905
'---.---...-----<1 IN OUTl>----<1---0 -5V
- 1 5VA 2. SIGNAL FLAGS IN
'- 22
� �-+---i> 47 CONNECTIONS BEC
� -1 5 V A C20 GND C19
2.2 SHEETS OF THIS
I
R21 0' 1 SHEET NUMBER AN
� +22V DESTINATION GRI
H +22V � 16.2
� +
APPEAR I NS IDE T
67XXBMM
LI t 8 7 8 9
.
........................................................................ . --i�
. .................... . 00-07
R3
34.BK
+15V @
14
P3
04 vcc
S1A I
05 I
S2A RB5
OB 11 RETRACE
S3A DA BLANK
S4A 100 I
R7
S1B I
34.BK S2B RB6 112 BANDSWITCH
DB BLANK
S3B 100
S4B n n
:JJ :JJ
A. A.
EN A. rn
AO ���
09 n n
A1 :JJ :JJ
rn rn
GND A. rn
vcc
03
-15V@ 1N752A X 4
+5V@ �-----.-i> +5V @
ABB
10K Cl19
20
vcc
2N4249
RB7 15
1K ""--------- --> PEN LIFT RELAY DRIVE
R15
30.1K R16
I
30.1K
>:c=---�..._-'\/\�---'--"5-4 SECl
�
SYNC
R17 100 I
TL 17
30 .1K +5V@<! 1 ) +5V@ REF DESIGNATIONS
LAST USED NOT USED
--� F
GNOD
U43 Cl29
Cl34 C6
CR60 C47
C59 R141-146
-15VA R134-R137
3/EO> ATTEN STAB R173
12/BO( LATCH 1 STAB VR1
12/EO? ID0-!07 STAB L4
P3
12/CO> WR1 STAB RN6
l5/DO( SHAPE DAC STAB J14
12/CO> RAMP OUT STAB
12/FO(
12/H ) :
V/GHz WIDTH DAC STAB
V/GHz OFFSET DAC STAB
i> SWITCH SEL STAB
l 4/EO> SAMPLER SEL STAB
� MOD SELECT CLK
If J13
+15VA <I f ! 2 ) +15VA
-15VA <I '! 4 ) -15VA
F
SPECIFIED. 3. GROUND SYMBOLS USED ON THIS ASSEMBLY I GATE
IN OHMS,
IN MICRDFARADS,
SCHEMATIC SET ARE DENOTED AS:
v
IN MICROHENRIES. � DENOTES DIGITAL GROUND
CATE MATCHING
N MULTIPLE
\'.?' DENOTES ANALOG GROUND
SCHEMATIC. THE
OURCE DR
4. SUBASSEMBLY BORDERS ARE NOTED
AS: Figure 2D-6. A29 Rear Panel Interface PCB
no COORDINATES
5. STATIC SENSITIVE COMPONENTS USED IN
Schematic Diagram (Sheet 1 of 5)
THE FLAG: l2/B3)
THIS ASSEMBLY INCLUDE: 6700-D-31829-3 (Rev. J)
ns NOT INSTALLED CR12,CR14,CR16,U5,U10-U16,U19-U23,
U25-U27.U39,U41. U4B
20-9
0 1 2 3 4
02 07 D2 Q2 06
"
D3 08 Q3 09
103
'---
D4 13 04 Q4 12
"
05 14 05 Q5 15
"
D6 17 06 Q6 16
I',
D7 Q7 19
11 07
"
LATCH 1 STRB 1/F8
18
UB
I"
EN HC374
>
t GND +5V@
B 110 cw HORIZ
t20 08
DAC
w 07 DOVCC VRF
IDO
06 Dl FBK 09
/ ID1
I/ ID2 05 D2 U10 _152
v ID3
I/ ID4
v ID5
04 D3
16 04
15 05 11
T° 1
02
DT1
'
I/ ID6 14 06 1�
- 01
v ID7 13 07 CR12 t
OT2 12 M80501l 03 + �
�BYT
02 Wl TL074 02
AG
c I/
WR1 STRB
� W2
�
RAM P OUT S TRB 1/F8 , XFR �
_
� C SL
GNO
� OAC1232
(-Pl-2
0 -10V RAMP
+5v@ - +5V@
D
l 0. 1
20 t20 08
V/GHz
I�
!
D
SLOPE DAC
07 DOVCC VRF
I
� DO 03
04 DO QO 02
05
IDO IDO
ID1"..v ID1 06 Dl FBK 09
� 01
vcc
i
r
� GND
110 17 - W2
XFR Ii
01� CSL
�
w ? GND
OAC1232
V/GHz WIDTH 1/F8 Iv
OAC STRB
( Pl -!
F +10V REF
+5V@ V/GHz
f20 08
OFFSET DAC
17 W2
°''� -
P3
R23. 100 I 1
L ALT 1
R22 100 6 L ALT 2
DAC A/DAC B
R89 100 SPARE OUT
R90, 100 S PARE OUT 2
R91. 100 S PARE OUT 3
-1ov REF
n n n
JJ JJ JJ
n n ,. ,. ,.
+15VA
JJ "' -..J ro
;i: ro
* * *
H CTOO
R41
01 16 48.7 1N751A 5
+15VA @
X
+15VA @
U12A
DG201
06 04
�
�:· ·9
U11B >-0_7 ��---+��--t������ ��--+-�'A' R21'5.�-+-� �- 1 -7--;10V HORIZ OUT
03 R24 05 + 100
5. 1lK 11 T L074 08
C9 CR13
-15VA @ 1N759A
-15VA @ 12V
:p 01
R138 -15VA 07
15 14 1N4446
5.11K ell 42.2K CR56
+24VG .001
�66 42.2K
07
�
U14
-n·,:v Rv30v--+���8'---7 V/GHz OUT
>--_ 0_6�����---�--... ��v
LF356 100
CR15
1N4749
-5V
Pl
A LC SLOPE
I
>'-'---�-'---�...__����-+�·��1�1�1'-4)
OB
F
-15VA
12
09 � 5/AO
u12c
DG201
n
13
V
10 �11 Figure 2D-6. A29 Rear Panel Interface PCB
20-10 67XXB MM
03
F 10 01
U17E
HC04 02
06
07
05
G
03
13 12 01
U 1 7F
HC04 02
06
07
05
67XXBMM
6 7 8 9
'*'"
CR18 Ol"n°""""" A.iHC.n<>rc R'fii�Y�""'
1N4446 Jj.-
J11
12
'If * I SPARE
CR19 RELAY
"" �
1N444B �
I
I 4
*
CR21
.,,..
CR22
/I.
J12
I 3
,.
.if.
CR23
10 dB THAU
40 dB 1 THAU
CR33
CR34
1N4446
CR37
CR3B
1N4446
CR39 CR40
1N4446
ATTEN SUPPL Y
I
20-11
0 1 2 3 4
PIN SWITCH DRIVERS
+15VACD
+15VA +15VACD +5vCD
U29. U30, U33, &
r
1
A +5VCD
U298
U34
02 U26C
DG201
SUBSTRATE
DG201
CA3183
U25A
U25C
- 5 V DG201
+5 vCD
IDO-
B ID7 20 -15VACD
DO
-5V
D2 09 -5V
Dl
D3 12 -5V
15
Q3
Q5 16 15VA 1 +15VACD
Q4
Q6 19 +15VA 1 +5v CD
Q7 +5vCD
+
E U34 E
SWITCH
U2BC
S L
DG201
14
STRB CA3183
c
13
-5V
D
-5V
+5vCD -5V
20
IDO 03 DO QO 02
ID1 04 05 +15VA 1
vcc SWITCHED SAMPLER DRIVERS
ID2 07 D1 01 06
ID3 08
D2 Q2 09 +15VA 1 +15VA CD
ID4 13
D3 Q3 RN3
D4 1
+s vCD
ID5 14
E
D5 U29E
ID6 17 D6 �I RN3
4. 7K CA3183 14 U258 LC
ID7 18 D7 DG201
U25D 5 13 6°7
U24 DG201
EN HC374
> ol--���� � ---=-
=--i_j
GND
10 U29A
CA3183
F
01
-5V
-5V
�
-5V
+15VACD
+15VA 1
+15VA CD +sv CD
+svCD
RN4 U33D 09
R44 CA3183
U27D
G
+15VA <}--'\/Vv-- � +15VACD 6 10 DG201
33 2 +�17 U27C
�.7K
DG201
�2 09
U33C
RJ5
-15VA �
33.2
2.2
../
-15VACD
C22
CA3183
-15VACD -5V
H
� ClB +
07
+ 1 5 VA G)
q
+ s v G)
U26A
DG20 1
m
32D
J6
( R F OUTPLJ • P1 r.J
�
SW• Tc.JI
�
R52
215
14 I
1
"\U X )
�5 SHIELD
SPARE GATES
(DG20 1 ) NC � K E Y
3
-5V 2-B SW D R I V E
4
8- 1 2 . 4 S W D R I VE ( 8 - 2 0#)
5
1 2 . 4-20 SW D R I VE (20-26 5)
-------'---"6-7 20-26 5 SW D R I V E (26 5-40)
I
+ 1 5 V A G) # f'.'\IJl.,.'"T I � C> \N I I).\
+ 1 5 V A G) + 5 V G)
FR.e:9 Do Ua. L-er;a
U34B U33B
CA3 1 8 3 CA3 1B3
U288 03 U28D
03
DG20 1 DG201
U34D
CA3183
....-
- 5 v <1-
R80 1 1
... -'\,I\/\ <.. t:>PDT PtN S.,.., 1 T<:l-f )
100 c..___;._c� 8 - 1 2 . 4 DR 1 (T 1 I
+ 1 5 V A G) + 1 5V A G)
+ s v G)
+ s v G) -' P
--'
l --=
' 1 44
'-
- - --' L D 0 U B L E R I A MP S EL
U30E
U30C CA3 1 B 3
07 030
CA3183
U26D 13 U32C
2N2222A
DG201 DG20 1 J14
R 1 59 I 2 DOWN C O N V
r-
..
�. /\
,'VV -<1
- -- -> INPUT S W I T CH
12 3
SHI ELD
S H I EL D
R60
215
J9
KEY
51 . 1 '---+----�-"-'--? - 5V
2-B S A M P L E R SW DR I V E
'-------t--�r---7 8 - 1 2 . 4 SAMPLER SW D R I V E
------- -----+--r::-7 12 4-20 SAMPLER S W D R I V E
-------+--..-0--7 2 0 - 2 6 . 5 SAMPLER S W D R I V E
S H I ELD
+ 5 V G) + 1 5 V A G) + s v G)
CONV SEL
U33E U30A O1
CA3183 CA3 1B3
KEY
13 U27A 16 --------____. . 0 1 - 2 F I LTER D R I V E
DG20 1 --------�-'---'> 2-3 . 5 F I LTER D R I V E
-------� --"--7 3 . 5- 6 F I L TER D R I V E
--------4 6 - 8 F I L T ER D R I V E
SHI ELD
20-12 67XXB MM
0 1 2 3 4
+ 1 5V A
R92
100-107 2/G9
1K
A
+ C23
�o
CR49
1N751
20
vcc
03 02
DO ClO
04 05
D1 Cl 1
07 06
D2 Cl 2
08 09
D3
13
D4 NC
B 14
D5
106 17
D6 NC
107 18
D7 NC
SELECT
MOD
1 / GB >
STAB
U37
HC374
+ 1 5VI
- 1 0 V REF 2/89
c
17 04
VCCVRE
1 00 14 03
DO RFA
13
D 1 U38
2 12 AD7528
D2
11 02
D3 OUTA
10
D4
09 19
D5 RFB NC
106 OB
D6
D 1 07 07
07
A /DAC 8 2/A9
06
SHAPE DAC 1 /F B
DAC DAC
STAB
+ 15VA
16
- 1 51
+ 1 0V REF
+ 1 5VA
�
10
+ 1 5V
+ C29
P1
C26 R104
p
9. 5 3 K
F
ALC C N TAL
I
- 1 5VA Tio
F
8
REF
7
�
ALC CNTRL
7
02 1 . 5K
+
14
-x
MC 1 495
+ 1 5 VA 20K 03 13 07
:&
C57
022
- 1 5VA
H
67XXB MM
5 6 7 8 9
VNlOK
Q24
Jl
I
s 2 . 0 1-B
F
PIN ORV
S H I ELD
iVA @ SHIELD
f
VNlOK
Q25
R99
)r
J2
25 I
D s 2 B- 1 2
F
P I N ORV
S H I ELD
Q2 1
2N2907 S H I ELD
1
VNlOK
Q26
J3
s I
2 1 2 . 4-20
F
P I N ORV
R l OO SHIELD
lK SHIELD
)
;
Q22
2N2222
VNlOK
Q27 J4
I
D I
)�
2 20-26 . 5
R101 P I N ORV
F
2 . 26K SHIELD
SHIELD
FD300
15VA
+ 1 5VA
R 1 67
4 . 99K
Q34
5vA + 1 5VA 2N3906
C53 - 1 5V A
OB + 1 5 VA 39pF
+ 1 5VA
R 1 69 CR60
U32B 1 1 . 5K
D G2 0 1
1 N 4 4 46
CR59
R161
1N4446
R l 10
R 1 63 J5
240 133K I 26 . 5-40
lW PIN ORV
~ '"' '
- 1 5VA
CR5B SHIEL D
- 1 5VA
R 1 62
Figure 2D-6. A29 Rear Panel Interface PCB
�
1 2 . lK
C34
Schematic Diagram (Sheet 5 of 5)
9pF
6700-0-31829-3 (Rev. J)
2D-13/2D-14
2E-REFERENCE LOOP: A5, A7, A10 2E-2 REFERENCE LOOP ASSEMBLIES,
PCBs AND CRYSTAL OSCILLATOR OVERALL DESCRIPTION
This section contains service information for the ref The function of the Reference Loop is to translate
erence loop assemblies listed in Table 2E-1 below. the frequency accuracy and stability of the 10 MHz
Refer also to the specific troubleshooting informa reference signal (from the internal crystal reference
tion for the reference loop in the error code table that or an external synthesized source) to the Coarse
is located in the front portion of Section 2-System Loop, the Fine Loop, the 0.01 to 2 GHz Down Con
Description and Troubleshooting. verter, and the Pulse Generator.
Table 2E-1. Reference Loop Service Information The Afj Reference Oscillator PCB contains a voltage
controlled, surface-acoustical-wave (SAW) oscillator
Documentation Reference Page
•••••••••••••••••••oo•••••••••••••••••••••••••••••••••••••••••••••• f l
""""""""""""""""""""""""" •••••oo•••••••••••••
that generates an output frequency of 500 MHz. This
500 MHz signal is buffered and fed to the A3 Coarse
OVERALL ASSEMBLY LEVEL
1
···································································· ································· ····················
67XXB MM 2E-l
AS REFERENCE OSCILLATOR,
DETAILED CIRCUrr DESCRIPTION 2E REFERENCE LOOP
The output of the phase/frequency detector is zero the DVM circuits located on the Al 7 Analog Instruc
when the Reference Loop oscillator is phase locked. tion PCB for monitoring by the A23 Microprocessor.
This output is also monitored by the A23
Microprocessor PCB (via the DVM circuits on the NOTE
Al 7 Analog Instruction PCB) to detect an unlocked Pressing <Shift> TRIGGER 010 displays
condition. An unlocked Reference Loop is shown (1) the RL TUNE voltage in the synthesizer's
as an error code (E5-10, E5-11 or E5-12) during self front panel LEVEL display window and
test, and (2) by the illumination of the NOT the Reference Loop frequency in the
0-LOCKED LED on the synthesizer's front panel. FREQUENCY display window. This may
be useful in troubleshooting reference
NOTE loop problems.
There are several reasons for the NOT
0-LOCKED LED to be illuminated. If it is
2E-3.2 Reference Loop Oscillator
illuminated when it should not be; i.e., in
the CW or Stepped Sweep modes of opera The voltage-controlled SAW oscillator, Yl, is tuned
tion, an instrument self test will indicate by the output of U2 to generate 500 MHz. The tuning
the area causing the unlocked condition. voltage range of +2V to +12V compensates for any
drift of the SAW oscillator output frequency due to
In addition to the phase lock monitor, the output of time and temperature. The output of Yl is fed in
the loop amplifier is monitored by the A23 parallel to buffer amplifiers U3, U4, and U5.
Microprocessor PCB via the DVM circuits on the Al 7
Analog Instruction PCB. This voltage may be dis
2E-3.3 Buffer Amplifiers
played on the synthesizer's front panel LEVEL DIS
PAY as a aid in troubleshooting. Buffer amplifiers U3, U4, and U5 isolate the RF
output connectors A5Jl, A5J2, and A5J3 and buffer
2E-3 A5 REFERENCE OSCILLATOR, the output of Yl. These amplifiers are all configured
DETAILED CIRCUIT DESCRIPTION the same, however, their biases are slightly different
to provide the necessary output signal levels.
Refer to the A5 PCB schematic diagram in Figure
2E-3 for the following discussion. The output of U4 is coupled to A5Jl by Cl9. This
500 MHz signal, at approximately 0 dBm, goes to the
2E-3.1 Loop Amplifier A 7 Reference Divider PCB. The output of U3 is
coupled to A5J2 by Cl8. This 500 MHz signal, at
The reference loop phase error signal from the A 7 approximately 8 dBm, goes to the A3 Coarse Loop
Reference Divider PCB is input at A5Pl, pin 6, and Mixer PCB. The output of U5 is coupled to A5J3 by
then goes to the unity gain differential amplifier, Ul. C20. This 500 MHz signal, at approxim ately
From the Ul output, the error signal goes to the 5.5 dBm, goes to the 0.01 to 2 GHz Down Converter
input of the Loop Amplifier, U2. The network com located on the RF microwave deck.
prised of Rll and C3 sets the basic reference loop
bandwidth to approximately 30 kHz. The output of The +lOV supply for Y l comes from on-board
U2 is the tuning control voltage for the Reference regulator VRl. This regulator helps isolate the SAW
Loop Oscillator. oscillator from the normal +15 VLP power supply
noise. The circuitry of Q2, Q3, and Q4 filters the
The output of the loop amplifier, U2, is clamped to input voltages (+15 VLP, -15 VLP, and +24 VG)
ensure that the reference loop oscillator, Yl, will not received from the A22 Regulator PCB, providing ap
generate frequencies outside of the desired operating proximately 20 dB rejection of noise and ripple from
frequency of 500 MHz. The circuit comprised of Ql, the power supplies.
CRl, CR4, RB, Rl2, and Rl3 clamps the most "nega
tive" output of U2 to +2V. The output range of U2 is
2E-4 A7 REFERENCE DIVIDER,
approximately +2V to +12V.
DETAILED CIRCUIT DESCRIPTION
The output of U2 is also coupled to pin 5 of connector Refer to the A7 PCB schematic diagram in Figure
A5Pl via the voltage divider/isolation network Rl6 2E-5 for the following discussion.
and Rl 7. This is the RL TUNE signal that goes to
2E-2 67XXB MM
A7 REFERENCE DIVIDER
2E REFERENCE LOOP DETAILED CIRCUIT DESCRIPTION
The 500 MHz output from A5Jl goes to an im If a 10 MHz signal is present at A7J4, it is input to
pedance matching network (Rl, R2, and R3). From buffer amplifier/squaring circuit Q4 where it is con
there it is input to buffer amplifier Ql and is coupled verted to a TTL-level square wave and output to
out by C3 to Ul, a divide-by-10 integrated circuit. U5-10. The output of Q4 also goes to CR5 and CR6,
The 50 MHz TTL output ofUl goes to the divide-by- a full-wave rectifier. The rectifier de output turns on
5 circuits, U3 and U4, and buffer amplifier Q7. Q7 Q5, pulling the collector to ground. This ground sig
isolates the RF connector A7J2, reserved for future nal to U5-12 disables U5D, causing its output at pin
use. 11 to go to a TTL high. U2C inverts the ground
signal from Q5 and applies a TTL high to U5-9
causing U5C to invert the 10 MHz input. FromU5-B,
2E-4.2 Divide-by-Five
the 10 MHz goes to U5-5 which also has a TTL high
U3, U4, and part of U2 comprise a divide-by-five on pin 4. The 10 MHz output at pin U5-6 is input to
circuit that drops the frequency from 50 MHz to U6.
10 MHz and outputs it to the U6 phase/frequency
detector circuit. The output of the divide-by-five cir The TTL high fromU2C also goes to connector A 7Pl,
cuit also goes to buffer amplifier Q3. The output of pin 3, then to the A8 Serial VO PCB via the A28
Q3 is coupled to RF connector A7J3 via C27. This Motherboard PCB. The A23 Microprocessor PCB
10 MHz signal, at approximately -2 dBm, goes to reads the signal during normal housekeeping
the AlO Reference Buffer PCB. The rest of the syn routines, then instructs the front panel to activate
thesizer uses this 10 MHz signal for reference. the EXT REF annunciator on the FREQUENCY dis
play via the AB Serial VO and A2 Front Panel Con
NOTE trol PCBs. The signal from U2C also turns on Q6.
This 10 MHz signal comes from the Since the collector of Q6 connects to the internal
500 MHz reference loop oscillator, not 10 MHz crystal oscillator via the A28 Motherboard
from the internal 10 MHz crystal oscil PCB, the line is pulled to ground, shutting off the
lator. When the reference loop oscillator is internal 10 MHz oscillator. This prevents spurious
unlocked, the 10 MHz reference for the responses.
synthesizer is off frequency by the same
percentage as the reference loop oscillator
2E-4.5 Phase/Frequency Detector
is from 500 MHz. When the unlocked ref
erence loop oscillator is 50 kHz high, the U5A andU6 compose a "D" flip-flop phase/frequency
10 MHz at A5J3 is 10 kHz high (50 detector. When the 10 MHz signals at U6-1 and
kHz/50). Although the Reference Loop is U6-13 are in phase, the rising edges transfer the +5V
unlocked, the Coarse, Fine, and YIG on pins 3 and 11 to output pins 5 and 9. Since pins
Loops still lock, but at a corresponding 1 and 2 ofU5A go high at the same time, U5A-3 goes
frequency offset. low and clearsU6A and U6B, setting their Q output
low again. This causes a pulse of approximately
20 ns (due to the propagation delay of U5A and U6)
2E-4.3 Internal 10 MHz Input Circuit
at pins 5 and 9 of U6.
The 10 MHz signal, from the internal crystal oscil
lator, is input via RF connector A7J5 to buffer When the 10 MHz clock at U6-1 is delayed by
amplifier/squaring circuit QB where it is converted 90 degrees (25 ns at 10 MHz), U5A-1 goes high
from a sine wave to a TTL level square wave. CR 7 25 ns after U5A-2. This results in a pulse of ap
acts as a switch for the bias current of QB, which is proximately 45 ns at U6-9 and a pulse of 20 ns at
furnished by R13. CRB prevents saturation of QS. U6-5. When the 10 MHz clock at U6-l is ahead by
The output ofQ8 goes to NAND gateU5D. Normally, 90 degrees, U6-5 has the 45 ns pulse and U6-9 has
U5-12 functions at a TTL high, so U5D inverts the the 20 ns pulse.
10 MHz input. FromU5-11, the 10 MHz output goes
to U5-4, which also has a TTL high on pin 5. The R23-C19 and R25-C20 integrate the outputs of U6,
10 MHz output at U5-6 is input to U6. which go to the differential receiver U7. If one of the
outputs of U6 has a wider pulse than the other, the
de voltage resulting from the integration of that
67XXB MM 2E-3
A10 REFERENCE BUFFER,
DETAILED CIRCUIT DESCRIPTION 2E REFERENCE LOOP
pulse will be higher than the de voltage resulting 2E-5.2 Buffer Amplifiers
from the narrow pulse. U7 amplifies this de voltage
Ql is configured as an emitter follower and biased
difference (the reference loop phase error) and out
by R3 and R4 for a collector current of approximately
puts it to A7Pl, pin 6. The error signal then goes to
5 mA R7, RS, R9, and RlO split the output signal
the A!5 Reference Oscillator PCB as the input to the
from Ql into four paths.
loop amplifier. Because the phase lock loop corrects
the frequency until there is zero phase difference,
Emitter follower Q2 receives its bias from the emit
the output from U7 is OV when the Reference Loop
ter ofQl. Its collector current is approximately 3 ma.
is phase locked. When the loop is unlocked, the
The output signal, which is coupled by C 7 to
phase detector has maximum output and the output
amplifierQ6, is amplified approximately three times
from U7 is approximately ±12V.
to overcome the losses from the splitter and emitter
followers. The amp lified signal, whose peak
The U7 output is also coupled to pin 5 of connector
amplitude is ==0.2V, is coupled to AlOJl by C9. The
A7Pl via the decoupling network R37, C22, and R39.
10 MHz signal, at approximately -2 dBm, goes to
This is the RL MON signal that goes to the DVM
the All Fine Loop Divider PCB. The other two buffer
-circuits located on the Al 7 Analog Instruction PCB.
amplifiers (consisting ofQ3, Q4, Q7, and Q8) operate
The A23 Microprocessor monitors this signal via the
the same as the first buffer amplifier. The 10 MHz
Al 7 PCB DVM circuit to determine if the Reference
signals at AlOJ2 and A10J3 go to the A6 Coarse Loop
Loop is locked.
Divider PCB and the Al3 Pulse Generator PCB
respectively.
The +5V supply for this PCB comes from the on
board regulator VRl. This regulator helps isolate the
Emitter follower Q5 applies its output signal to a
Reference Divider from both the 50 kHz switching
voltage divider consisting of L3, Q9, R38, Qll, and
signals and the normal noise and ripple on the
L4. The divider sets the collector current forQlO and
+9 VLP unregulated supply from the A25 Switching
Ql2 at approximately 10 mA. Q9 and Qll provide
Power Supply PCB.
temperature compensation for QlO and Ql2. CRl
and CR2 prevent QlO and Ql2 from becoming
2E-5 AlO REFERENCE BUFFER, saturated. CR3 and CR4 prevent damage toQlO and
DETAILED CIRCUIT DESCRIPTION Ql2 by clamping any signal inadvertently applied to
Refer to the AlO schematic diagram in Figure 2E-7 the AlOJ5 output. R39 provides the 50 ohm source
for the following discussion. impedance for the AlOJ5 output and current limits
any signal applied to AlOJ5.
2E-5.1 Input On-board regulator VRl provides the +5V power for
The 10 MHz signal input at RF connector Al0J4 the PCB. It receives its voltage from the A25 Switch
comes from the A7 Reference Divider PCB. It is ing Power Supply +9VLP unregulated supply.
buffered by Ql and then applied to the four output
buffer amplifier circuits. The buffer amplifier cir 2E·6 REFERENCE LOOP ASSEMBLIES,
cuits going to RF connectors AlOJl, AlOJ2, and TROUBLESHOOTING
Al0J3 are identical. The buffer amplifier circuit for
Refer to the troubleshooting information located in
RF connector AlOJ5 (rear panel output) provides
the beginning of this section (Section 2-System
additional isolation and protection from any signal
Description and Troubleshooting). This information
applied to the AlOJ5 output. This high isolation
. provides a list of error codes that may be displayed
prevents destination circuit signals from gomg to the
as a result of failures in the reference loop subsys
other circuits. For example, any 200 to 321 MHz
tem and probable causes of the failures.
signal that comes from the All Fine Loop Divider
PCB and goes back into AlOJl will be attenuated by
40 dB at the AlOJ2 and AlOJ3 outputs. This 2E-7 REFERENCE LOOP ASSEMBLIES,
prevents interaction of circuits requiring the SERVICE SHEETS
10 MHz reference signal and decreases the pos Table 2E-l (page 2E-l) presents the arrangements
sibility of spurious responses. of the block diagrams, schematics, and parts locator
diagrams for the A5, A7 and AlO PCBs.
2E-4 67XXB MM
2E REFERENCE LOOP
10 MHz
(FROM INTERNAL
CRYSTAL REFERENCE
OSCILLATOR)
67XXB MM
REFERENCE LOOP BLOCK DIAGRAM
10 MHz -2 dBm
(TO A6J2 CLDIVIDER)
10 MHz -2 dBm
(TO A13J1 PULSE
GENERATOR)
AL
PHASE
ERROR
--.;:> >---;;.o- 500 MHz 5.5 dBm
(TO DOWN CONVERTER)
500 MHzSdBm
(TO A3J2 - CLMIXER)
AL TUNE V
(TO A17 ANALOG
IN STRUCTION PCB)
2E-5
500 MHz 500 MHz
500 MHz =::t8 dBm =::+5.5 dBm
::::QdBm (ToA3J2) (To Down
(ToA7J1) CL Mixer) Converter)
J1 J2 J3
�
,--;
n I
I .
-
I I
+8
TP2
TP3 Reference Loop
+12V Tuning Voltage
+
( 12V to+12V)
TP5
+23V
TP4
-14V
P01
P1 11
T
( o A28XA5 via filtercons)
A5 REFERENCE OSCILLATOR PCB PARTS LOCATOR DIAGRAM 2E REFERENCE LOOP
AS
REFERENCE
OSCILLATOR
2E-6 67XXB MM
0 1 2 3 4
CRI +12v
Rli'..
A 2.'+.�K
RI:,
Z.2.Co�
A2.8'<A5 Pi
B
R7
3 3.1>,K
0? 2. 7
L.j
. -, Rt .,.2V-h> +t.2...V
RH f> ERRCIR_ � r+-"··· ,
REF 3.1 !;<.
c -14V
LOOP AMfLIFIER
CRZ.
AZ..8'f..A5 Pl IN'IDO':.
I():
I
.;o RIB
VR I
+IS°VI?--'-----< f-0-'-l>T'*"----t---• +ID V
LM 5 ! l
D i\::JJ CR"'> Rl9
iN'10C'.J Z.'13
RZ.O i
I
l.G9K i
I
LI i
I R"
�
E 0. 2.
lNZ.Z.18
1<
....-+
-- 12.V
+ Cl 3
A28XAr:; ?I
�c
L2
-•�VLP� ),_1_1 ·--�rn r.___--1�--
'l 7
G...,
F ZNZ. "lOS
kZ.'t
'«
rmns·
G AS REFERENCE OSCILLATOR SCHEMATIC NOTES:
N•-;T
1. UNLESS OTHERWISE SPECIFIED,
RESISTANCES ARE IN OHMS 11·1;,
'.._ u�::c
CAPACITANCES ARE IN MICROFARADS (µF),
"L/7
i L.j
INDUCTANCES ARE IN MICROHENRIES (µH).
c Z.'"'
2. FILTERCONS ARE USED BETWEEN THIS
c.2. us
PCB EDGE CONNECTOR AND THE A28
MOTHERBOARD CONNECTOR. EACH
V ;. I
10
SIGNAL PATH CONNECTION HAS G'-'
(TYPICALLY) 1500pF CAPACITANCE H'S
BETWEEN IT AND CHASSIS GROUND. f I
(I
3. GROUND SYMBOLS USED ON THIS ASSEMBLY
H SCHEMATIC SET ARE DENOTED AS: LG
� �-.s
CHASSIS GROUND: m
ISOLATED GROUND: '\7
v
.I
:s � RL TCJNE \'
+IOV "1.02.K
�
Rl7
f " +'.f-¢
(3
2. .2.0'h
RIS
z. '+. �
7
f-+_..._
....
0
� I +12v
r-::,".+,2
YI \10
B 5
SA.W '-'43
7 osc.
�o R�S
::.co
"''"'"' ·R4'.
-�-030_
:
_
________ z.
_
____
_ i""�_ _ �1, _t_--"1 gs . j 4--�
�0.1C2 f
L3
0.33
R25 R31 CIS CIB J2
500 MHl.
"'�
11\1\i 'VVV I ::::5.lBm
l""
I IOOPF TO J>\3:J2.
+ 12V Cl MIXE.R
/.3)(
-:::::: Y.lV
¢0.1( 2.2.
Rr 29 'oo�'
L't
0. 3.3
(2.E, R32. CIE. (19 J" I
SOG MHZ.
VV\i '\/VV I ::::QdE.n'
b lb IOOPF Ml>.R-2 TO A 7 Ji
+ IZV RU". DIV
75
� 6�13
'l °
LS
0.33
R27 R3:5 (17 C20 J3
500 MHt_
"�
VV'v '\/VV I ;::: 5.5d8rn.
IOO'!'F Ml>.R-3 TO oovn, co Nv.
1.31\
BUFrER s;/\GLS
2E-7
A7J5
500 MHz 50MHz 10 MHz 10 MHz 10 MHz
==0 dBm (ToA14- ==-2dBm (From Rear (From Internal
(ToA5J1) Not Used) (ToA10J4) Panel BNC) XTALRef.)
J1 J2 J3 J4 JS
TP2
10MHz
UI TTL pulses
\Jl.
®· u� ,
TP1-+--4--
50MHz
TTL pulses
'lJ
: ,TP 1
0
' .
�'�
TP3
100 ns TTL
\JP.\ 0 pulse width
b L 3. ·
0 GJO "'
v
1 P1 11
A7
REFERENCE
DIVIDER
2E-8 67XXB MM
0 1 2 3 4
+sv
A
\0 L.•
'-17
��.�
-t SY
c_11
o.�
0.
y I \7
¢
B :z_ ::<..J ?R
[@
2.1<-, :;- u 3 B Q ,_9
� _.__=
'< l
Tl
soo ,.,....,?..
-l'3
(_
r
.=ROH A.. � :-1
� o-:1a�.
R"Z..
"'-S
�� 787
+5V
2
D
:r '-I
E:..X T 10 l-H-lz_
(>ROM i>.EA.\:1. ..::.1'"-1 ::;c,
fi2
..1e; L B\..lL)
DA.�
..
� . .::,..:1::- '=>I
=<-10
0 L"<.
•-(7 ,�
---
E -tSV
C 2. I
+SV f-
'-I IG:> 0.1
3 PR Ve_
s
��.,
10 1-iHz 3"._;(o/;._ Q
cn<o'--1 A.'-.\
\\,.JT'�Qk\A.._ ) '-"'
xn.,_ RE"") A Q (DI-.)(_
z C.LR
'ciSllZ.
I
is
�
-r-�V
F .,.� "'=
n _n_rCI
_
8() '"'S l
10
o_/\j\j\_
::>R
II
:::;- J(of:,::;;
-.:,
;>I
3
JR\
L_..___--l · 1.1 OUT>--- - SV
G
.. >:.v ?\-\A.SE/ FRE:.OUE"-IC. �
DETECTOR
'
J
I
1. UNLESS Oll1ERWISE SP ECIFIED,
RESIS TANCES ARE IN OHMS (Q),
CAP,a.CITANCES ARE IN MICROFARADS (µF),
I INDUCTANCES ARE IN MICROHENRIES (µH).
'
-711< � �- �v
I
2. FIL TI:RCONS ARE USED BETWEEN Tl11S
H - �v;_P
PCB EDGE CONNECTOR AND THE A28
+SV
+5V
---+-•+SV
IS pi:-
R?.Co
ih :
10"" ��L 1JT10>-'HZ..
---+1
'-,,.-, ,...,_...,,,.==,--<- ih 01S i>..'e-1...E:
rj
-;. v
Q(o
Rz.7 2.1.J 3Co9'4
?Jj
T3
�---------------------r--r-t) OYHZ..
- "2. .:l 8H
'"<:'.
'.C8 -"'.O_:y)
.,-sv C?.7
0.01
Rl� R33
AZ.8><A..I
100
I
I
+SV C3Z.
0.1
�%�RL0
RZ.Llf-\J-i R37 I I
\!",. W.OZ\<- I
I
��9 ( 5
')<-,
c.n.
io.1 );)��-'--
C.Y
3. GROUND SYMBOLS USED ON llilS ASSEMBLY 7. LAST USEDmOT USED COMPONENTS ARE:
SCHEMATIC SET ARE DENOTED AS:
REFERENCE DESIGNATORS
CHA SSIS GROUND: r/7
F), ISOLATED GROUND: '\} LAST USED
C32
NOT USED
cs.a Figure 2E-5. A7 Reference Divider PCB
II. Q)
4. TEST POINTS ARE DENOTED AS: CR8
L3
C29
CR1·3
Schematic Diagram (Sheet 1 of 1)
5. TROUBLESHOOTING VOLTAGE AND POWER
LEVELS INDICATED IN BOXES ARE TYPICAL
P1 Q2 6700-D-31707-3 (Rev. F)
08 R8
OR NOMINAL LEVELS. R43
6. STATIC SENSITIVE COMPONENTS USED IN TP3
llilS ASSEMBLY INCLUDE: U7
VR1
CR7, CR8, 01, U2-04, U6, U7, VR1 2E-9
10MHz
10MHz 10MHz 10MHz 10MHz ... +10 dBm
-2dBm
... -2dBm
... ...-2dBm =-2dBm (To Rear Panel
(ToA11J2) (ToA6J2) (ToA13J1) (ToA7J3) BNC)
J1 J2 J3 J4 JS
TP1
<
::0
GNDG
0
...
1 P1 4
NOTE:
Leading zeros on
component number
references may be
disregarded.
A 10 REFERENCE BUFFER PCB PARTS LOCATOR DIAGRAM 2E REFERENCE LOOP
A10
REFERENCE
BUFFER
2E-10 67XXB MM
0 1 2 3 4
�I
c T"L.
51
J4
IOMHZ
-;;:::: -z. ae.rri 01
\. \I 51-H&LD
.
(FROM A7 J"3)
D p,-z.
51
------ -;- TL
�·
n)
I I
VFI, I
+-<3VLP :!>40T-t;:. �----- +S\I
..
10
?.I
'5." + C3
CZ.
141.w
F
+
Cl
.2:z. 10
o.1
c1e
Gt-JD G
l.O
i
NOTES:
A10 REFERENCE BUffEll SCHEllATIC NOTES:
'
TL..
1. UNLESS OlHERWISE SPECIFIED,
RESISTANCES ARE IN OHllS (O�
'=>I
CAPACITANCES ARE IN lllCROFARADS (µF), 8. PCB TRANSlllSSKlN UNE PATHS ARE
INDUCTANCES ARE IN lllCROHENRIES (µII). DENOTED AS: -cTI:J-
G 7. STATIC SENSITlVE COllPONENTS USED II
2. FILTERCONS ARE USED BElWEEN lHIS
PCB EDGE CONNECTOR AND lHE A28 lHIS ASSEllBLY INCLUDE:
llOlHERBOARD CONNECTOR. EACH CR1, CR2, Q6.Q8, YR1
SIGNAL PAlH CONNECTION HAS
(TYPICALLY) 1500pf CAPACITANCE • 8. LAST USEDINOT USED COllPONENTS ARE:
BEIWEEN IT AND CHASSIS GROUND. REFERENCE DESIGNATORS
3. GROUND SYMBOLS USED ON lHIS ASSEllBLY LAST USED NOT USED
SCHEllATIC SET ARE DENOTED AS: C22 NONE
CHASSIS GROUND: m CR4
ISOLATED GROUND: \J J5
L4
H
4. TEST POINTS ARE DENOTED AS: @ P1
012
5. TROUBLESHOOTING VOLTAGE AND POWER
R39
LEVELS INDICATED IN BOXES ARE TYPICAL
TP1
OR NOlllHAL LEVELS.
YR1
67XXBMM
6 • 7 8 9
+51/
�·' JI
. IOMl-IZ.
I ?<-Z. de.,...
(TO All.)2)
�
+SH
- ;-- -
IOM�z
� -;:::.-ZdSl"T"I
-
+SV
-
N.1
- 20
- --
--
--
� �
10 l"IHL
- Z. .dBm
(TO Al3JI)
�
--
--fr-
+ C.Z.I
ilO
Gl\O .
Zl..l�OCD
J�
C.22 R� ---1'--��
,.___._ �
0�1 -( l --� --- � T
( O
IC> Ml-IZ
� +10 dBf'V)
RE,.._R PANEL BNC)
2E-ll/2E-12
2F-COARSE LOOP 2F-2 COARSE LOOP ASSEMBLIES,
A3, A4, AND A6 PCBs OVERALL D ESCRIPTION
1
Table 2F-1. Coarse Loop Service Information mixed with a fixed 500 MHz reference signal from
the A5 Reference Oscillator PCB to produce the 10-
L.""''"'""'���w.J.-�
�:,�:���'"'"'"" ��"J'" p���-wl 60 MHz Coarse Loop IF signal. This IF signal is
· �1����·�t���tion...............................�;:����2····· ..·����........
passed through a 80 MHz low pass filter and then
OVERALL ASSEMBLY LEVEL
goes to a limiter/ amplifier that prevents amplitude
modulated noise from being translated into frequen
.. ..
..!.�.?.!:l.�!.��.h.�.?.�.i.��........ . .... ......................�.��.�..?.��.�............�Y:�........
PCB LEVEL
cy modulated phase noise errors in the following A6
PCB circuits.
· ·
· 'A'i'ca'; �;;Tc;�·P'-•ili;tPc·e-w ------�-�--------· ·---� �"'"'" The amplified and limited CL IF signal is then
Detailed Circuit Description Para. 2F·3 2F-2 divided by the A6 PCB divider circuits-either by
Parts Locator Diagram Fig. 2F-3 2F-1 O integer division-or by fractional division-if re
Schematic {Sheet 1 of 1 ) Fig. 2F·4 2F·1 1 quired. The output of these circuits is a 2 MHz signal
that contains the frequency and phase information
A4 Coarse Loop Oscillator of the CLO signal. This signal is fed to the A6
Detailed Circuit Description Para. 2F-4 2F-2
phase/frequency detector circuits.
Parts Locator Diagram Fig. 2F-5 2F-1 2
Schematic {Sheet 1 of 1 ) Fig. 2F·6 2F·1 3
The A6 PCB integer divider circuits provide only
A6 Coarse Loop Divider PCB 2 MHz frequency division steps of the C.L. IF signal
Detailed Circuit Description Para. 2F-5 2F-5 (which represents a 2 MHz resolution of the CLO
Block Diagram . Fig. 2F·2 2F·9 signal). At high YIG oscillator frequencies, Coarse
Parts Locator Diagram Fig. 2F-7 2F-14 loop division steps finer than 2 MHz are needed. The
Schematic {Sheet 1 of 2)
{Sheet 2 of 2)
.
Fig. 2F·8 2F-1 5
2F-1 6
A6 fractional divide circuits provide this capability.
67XXB MM 2F-l
A3 COARSE L OOP MIXER, DETAILED CIRCUIT DESCRIPTION 2F COARSE LOOP
2F-3 A8 COARSE LOOP MJXER, proximately 12 dB. For input signals > -6 dBm, Q4
DETAILED cmCUIT DESCRIPTION and Q5 have a gain of about 6 dB. This limiting
action prevents any AM component on the IF signal
Refer to the schematic of the A3 PCB, Figure 2F-4,
from causing an FM component in the phase detec
during the following description.
tor output signal (which would degrade the phase
noise performance of the oscillator).
2F-3.1 Local Oscillator (LO) Input
The output of Q5 goes to the input of emitter follower
The 500 MHz LO signal from the A5 Reference Os
Q6. The output of U6 is coupled to connector A3Jl
cillator PCB is input to A3J2 at an approximate level
by R34 and C21. (Resistor R34 provides the 50 Ohm
of +7 dBm. The LO signal goes through a 6 dB
source match for this output, and C21 blocks the de
attenuator consisting of Rll, R12, and R13. From
component on the Q6 emitter.) This signal goes to
the attenuator, the signal goes to amplifier Q2 where
connector A6Jl of the A6 Coarse Loop Divider PCB.
it is amplified back to a +7 dBm level. This attenua
tion/amplification process isolates the signal, thus
preventing it from reflecting back into the A5 Refer 2F-4 A4 COARSE LOOP OSCILLATOR,
ence Oscillator PCB. Capacitor C9 couples the signal DETAILED cmCUIT DESCRIPTION
from the collector of Q2 to the input of the double
Refer to the A4 PCB schematic in Figure 2F-6 during
balanced mixer, Ul.
the following description.
from reflecting back into the A4 coarse loop oscillator C3, and C4. This low pass filter reduces the 2 MHz
2F-2 67XXB MM
2F COARSE LOOP
>
CLDATA��li!I
(FROM A8 SERIAL VO PCB)
CL CLK
(FROM A8 SERIAL VO PCB)
").!;4.;i;;;M
ffJ fu
;::i;- :;: ::: :Jll JIB&liMJIB [' i!i':: :·:,:::: -;: :)_::;::j:::: : : : : : : :: :: :
>.;;�•
10 llHz-2 dBm
(FROM A10 REFERENCE
BUFFER PCB)
67XXBMM
COARSE LOOP BLOCK DIAGRAM
440-490 MHz
>i!���..e->-------' •OdBm(TOA3J3)
440-490 MHz
OdBm(TOA31
POWER AMP/llULTIPLIER)
��""""'"""'-'-,,,,_.,.--'-::-� CL TUNE V
(TO A17 ANALOG
INSTRUCTION PCB)
CL MON
(TO A17 PCB)
2F-3/2F-4
2F COARSE L OOP A6 COARSE L OOP DIVIDER PCB, DETAILED CIRCUIT DESCRIPTION
resistor R14 is used to adjust the operating point of Table 2F-2. Yl Tune Control Voltage Range
this circuit.
Tune Voltage Output Frequency
NOTE:
Pressing <Shift> TRIGGER 012 displays Once the data transfer is complete, the outputs of
the CL TUNE signal voltage on the front shift registers U2 and U5 remain stable until the
panel LEVEL display for troubleshooting A23 microprocessor sends new data. Each time the
and calibration. frequency of the coarse loop oscillator is changed, U2
and U5 receive new data to program the counters.
67XXB MM 2F-5
A6 COARSE L OOP DIVIDER PCB, DETA ILED CIRCUIT DESCRIPTION 2F COARSE LOOP
minated by R12 and coupled via CU to amplifier Ql, nal frequency (490 MHz) by two and effectively
which has a gain of approximately two. The output multiplies it by 82. This results in a harmonic
of Q l drives buffer gate UBB that produces an ECL comb signal output with a harmonic signal spac
compatible clock signal that drives the coarse loop ing of 82 MHz (in the vicinity of 20 GHz). This
divider counters (U4/U7) and the divide-by-two flip is inadequate, since harmonic comb signals must
flop, U9A have a spacing of :5:20 MHz ( minimumFine Loop
Frequency divided by 10) near the desired YIG
tune frequency. 1b solve this problem, fractional
2F-5.3 Course Loop Counter Chain Operation
division of the C.L. IF signal is performed by the
The coarse loop counter chain is implemented as a A6 counter circuits. This technique results in a
N+l counter circuit. In the integer count mode of coarse loop resolution of 200 kHz. Note that 200
operation, these circuits divide the CL IF signal by KHz divided by two and multiplied by 82 results
whole integer ratios only. In the fractional division in a 8.2 MHz harmonic comb spacing in the
mode, the count ratios include fractional (decimal) vicinity of 20 GHz. This is well within the
components, as described below. 12 MHz tuning range (20 to 32MHz) of the fine
loop oscillator/counter circuits.
a. Integer Division Mode of Operation
The main coarse loop counter circuits are com The mode of operation of counters U4/U7 is
prised of presetable up/ down hexadecimal modified by the fractional division count control
counters U4/U7 and J-K flip-flop, U9A Counters circuits to produce division ratios that contain
U4/U7 are controlled by the Q outputs of shift fractional components. These circuits are com
register U2 as modified by the 4-bit adder in prised of:
tegrated circuits, U3 and U6 . In the integer • Rate-multiplier integrated circuit UlO,
count mode of operation, these circuits divide the • Waveform control and synchronization circuit
2F-6 67XXB MM
2F COARSE LOOP A6 COARSE L OOP DIVIDER PCB, DETAILED CIRCUIT DESCRIPTION
2F-5.4 10 MHz Reference Input age at the input of U16. The output of U16 is the
(unfiltered) coarse loop phase error signal.
The 10 MHz signal from the AlO Reference Oscil
lator module is input at connector A6J2 with a level
of approximately -2 dBm. The signal goes to termi At zero phase difference, the output sensitivity (out
nation resistor R68 and to the emitter of transistor put pulse width versus phase difference) of the D
QS, which is configured as a temperature-compen type flip-flop phase detector circuit decreases. When
sating diode for transistor QS. Amplifier QS converts the phase detector operates in this region, this
the 10 MHz signal to TTL levels. Diode CR6 im decrease affects the loop gain and loop bandwidth.
proves the 10 MHz input signal rise time by prevent This can cause loop instability and poor phase noise
ing Q6 from becoming saturated. The output of Q6 performance of the loop. (This point of the phase
goes to U16, which is a presetable counter that is detector is also called the dead zone).
configured to divide-by-5. The output of U16 is the
2 MHz TTL-level signal that is the reference fre To reduce the dead zone, the A6 phase detector cir
quency input to the phase detector circuits. cuits are designed to function in an offset mode of
operation. The pulse width of the two input signals
to flip-flops U 1 4A and U14B are unequal: the
2F-5.5 Phase/Frequency Detector
10 MHz reference signal from U6 has a pulse width
The A6 phaseJfrequency detector circuits comprised of approximately 40 ns, and the F DIV signal from
of J-K flip-flops U14A /U14B, operational amplifier the coarse loop divider circuits (U7) has a pulse
U16, diodes CR2-CR5, and associated filter com width of approximately 20 ns. Also, resistor R38 is
ponents. Flip-flops U14A and U14B operate in the smaller than R39.
same manner as the phaselfrequency detector cir
cuits located on the A7 Reference Divider PCB (refer During phased locked operation, the loop amplifier
to the circuit description for these circuits located in on the A4 Coarse Loop Oscillator PCB forces the
Section 2E-Reference Loop) . However, the A6 phase output of U16 to be OV when the loop is phase locked.
detector circuits operate at 2 MHz (i.e., the Coarse To counteract the extra current through R38, the
Loop reference frequency) instead of 10 MHz. pulse output at U14B is therefore slightly wider than
that at U14A (this phase lock offset is approximately
When the loop is phase locked, the Q outputs of 5 degrees).
U14A and U14B consists of narrow ( 20 ns) pulses
=
67XXB MM 2F-7
COARSE LOOP ASSEMBLIES, TROUBLESHOOT/NG 2F COARSE LOOP
The first 200 KHz notch filter is comprised of Instruction DVM circuit. The A23 Microprocessor
Ul7B/Ul7A and associated components. This circuit monitors this point via the Al7 PCB DVM circuits
reduces the 200 KHz signal components of the coarse to determine if the Coarse Loop is phase locked or
loop phase error signal (thus reducing the amount of not.
these components that appear in the final RF output
signal). The output of this filter goes to the input of
2F-6 COARSE LOOP ASSEMBLIES,
the 400 KHz notch filter.
TROUBLESHOOTING
The 400 KHz notch filter is comprised ofU18B/Ul8A Refer to the troubleshooting information located in
and associated components. This circuit reduces the the beginning of this section (Section 2-System
400 KHz signal components of the coarse loop phase Description and Troubleshooting). This information
error signal. The output of this circuit goes to the provides a list of error codes that may be displayed
input of the second 200 KHz notch filter comprised as a result of failures in the coarse loop subsystem
of Ul9B/Ul9A and associated components. This cir and probable causes of the failures.
cuit is identical in operation to the first 200 KHz
notch filter.
2F·7 COARSE LOOP ASSEMBLIES,
The output of Ul9B is the filtered coarse loop error SERVICE SHEETS
signal, CL 0 ERR, that go to the A4 Coarse Loop
Oscillator PCB. The output of Ul9B is also fed Table 2F-l on the first page of this section the loca
through isolation network comprised ofR63/R64 and tion of the block diagrams, schematics, and parts
C50 to become the CL MON signal to the Al7 Analog locator diagrams for the A3, A4 and A6 PCBs.
2F-8 67XXB MM
2F COARSE LOOP
I RATE WAVEFORM
I
CL CLK U2,U5
1 �:
:::::::::::; ;:::::;:;:;:;:;:;:;::::;::;:;:::::::::::: ::::::�:::::::;:::::::::::::� :�::;,;:, MULTIPLIER CONTROL
(FROM AS and SYNC
..._ ___.
SERIAL L'O PCB)
___
I
U10 U11A, U11B
I
I
I
I .__ ------ --- ------- - _______ _J
F DIV (2 MHz)
; ------------------------ ------------------------
'
PHASE/FREQUENCY
1 DETECTOR CIRCUITS
PHASE/FREQUENCY
I DETECTOR CIRCUITS
I
U14A, U14B,
I U15A, U16
I
I
I +s (2 MHz)
10 MHz CO UNTER
(FROM A10 U13
REFERENCE
BUFFER PCB)
---------- -----· - ---- ------------------------------- �
67XXBMM
A6 COARSE LOOP DIVIDER PCB BLOCK DIAGRAM
I U3,U6 ..
U4,U7,U9B
I
i I
! I
L-------�------------------------------------------------'
Bl-PHASE
CLOCK
GEN/BUFFER - ---------------------------'
��--
CIRCUITS
U20D Q7,Q8
.-·-----------·------------------------------------------,
.
I
i ALTER CIRCUITS I
I 200 KHz 400 KHz 200 KHz j
·
-----+----!�
NOTCH FILTER NOTCH FILTER NOTCH FILTER t-----41>----1-�
CLO ERR
(TO A4 CL OSCILLATOR PCB)
U17A, U17B U18A,U18B U19A, U19B
DECOUPLER/
ALTER
CL MON
(TO A17 ANALOG INST PCB)
R63, R64,CSO
I
L--------------------------------------------------------·
2F-9
10-60 MHz 44�-490 MHz
,,._2 dBm 500 MHz -+3dBm
=t 7 dB (CL RF Output
(From A5�
(CL IF Output
J1
to A61
J ) 2) t A 4J2)
0
J2 J3
Shield tab
soldered to
U1 case
aooo
Pl
aooo
1 P1 4
(To A28X A3
via filtercons)
A3 COARSE LOOP MIXER PCB PARTS LOCA TOR 2F COARSE LOOP
el
I
2F-10 67XXB MM
0 1 2 3 4
+ISVLP
R7
61 '.l
B (4
I
('.I
R '+
6.l'lK
�
c:, R 'l
J3
.:::.1
. 3/Q.5
'1'to· 'I e.o M H z +-t-t-1�--Vl/'\r--..-� �"i517'1
IO(•pF
�-3dB"" 6 d E.
(CL RF INPt T) ATT[N
C (FROM A4J 2) R3 RS
CCi8.1 "Bl
I
I
9
RF BUF�ER
Lil
SRI I
F
\I
5.0C MH l
J2
�+7dFm
(CL LO 1NruT)
( F R C '�1 ;. S · � '
-:::: �...,,��=-=-
J
-�s� ..:�::::::::
I ;��
�2..1. C- I
I
I
_4
i
! I.)�
F:
_J
67XXB MM
�I 5 6 7 8 9
IF AMPLIFIER/LIMITER
R Z.I
IK
(.I 't
o.�
L't
150 nh 15.'fVJ Cl 7
11,
0.1 (20
RI�
<'t.13711.
Rl. 2.
8Z..5
RZ.3
,, .z.z. K.
�l<Z9
,11.ZZ.K
o .i:--h
(
I�
·,
i'1. �
.\iJ G'-
Cl5 2N5179
�.J-3
.001
JI
R34 laIL 10-'-<J MH-..
%-Zd!!>"'
Q.C>Ot
(CL IF ()LI TPUT)
(TO AG JI)
RI!'! R20
, 71.5 715
2F-11
440-490 MHz 440-490 MHz
""+3 dBm ""+3 dBm
(CLO VCO Output (CL RF Output
�
to A31 Power Amp/ to A3J3)
/
Multiplier
- -- J1 J2
-om=! 0
P01
P1 11
A4
COARSE LOOP
OSCILLATOR
2F-12 67XXBMM
0 1 2 3 4
.°?11=-R::-&�TIA.L
AMP\..l�IE°FZ-.
llo<.. +l�V
G
B
AZ5XA4 Pl
-j�IC 0.'I
Jfl�
< dJ
rk-rr-r
I I p, I
, L'Z...
LI
I
CL(/> E-��o><, 2< >I '--
� ----'\/\/\r-----'z"-1 B+ 10
RI
Ii".
I u I A '-'-1-----"�""'-' r r
C:L � ERl=<.oP, � < UJ l':Z
>-'------A'"'' ____ 3 ·r
..=., , 4 t-JE:S'::i'3Z SI. I 470 S(DO 12...'
I
m
C� C4
-1�
RE-F >1 ' "" RB
T�io
i�
l.�:>4-�
I I 1 o + V'
!�t"1
FA:SI r=L.../C.L 3
E'i..JABl...E- -=< ( >! � i..J C �
/f;
c
I
I -17\/(-3)•"'
-20V(-4) .
I
I
I
D
� -10. "3V �I
:::::-11.�v R1
+ 1i:::,\J 1...1'"" -�I< >I 10
::::: -13. rev ca
;f; I
1<:�4
51\
I
�13V
E
I i' F'.3
?
I;<.,
I
3
I (+13v') (+S.'":N/
I
-r�v(-'3 :,«•-� 3
I< >i ...._
...._
._ �- -15V (-3) * *
J;
_
-�IVb::!.', -'21V(-4)
F
I
I
)
-17\J(-3)�•
c::. ...n::::i "' .J.. ( -20\/' (-4)
I J? I
,[� s
(-17V) (-� )'*�
(-20V)(-4 ')
G
�;f;
-�1
I
-15 v LP� >1-!- N c UNLESS OTHERWISE SPECIFIED,
RESISTANCES ARE IN OHMS.
CAPACITANCES ARE IN MICROFARADS.
INDUCTANCES ARE IN MICROHENRIES.
•
FACTORY SELECTED VALUE, SEE TABLE .
67XXBM M
5 6 7 I
-16V(-3)• *
8 9
--Z.IV(-4)
CR"3
+13'1/
+13V FD�OO
RI� -l!V(-3)
LOOP
IOK
CRI
-wv(-+) QCo
l\..IL.l'Z.'2.� RL.iS�
11(, �
c..i:,
10
Rl'3 RI�
�UPLIFIE-P., 1'!..3K 1f
1'"0300
-�v
1':12 G.5 R4� -11v (-�)
30 i< R"iB
IOI<. ZN. 3904 1':20 -2.0V(-4)
1'-.9K
,'f
1.2.1 K .I (. 1\2.
1'"0300
Pl A'ZBXA4
I I
R15 I '=> .
cs. i
Rill
..,
) I>=---- CL TU)..]E- y
IOK IOK 1<
+13\1 +13\/
1'
+ISV(j)
�o+z ,..;+::..
1;; s'-v--=
s +1 �
- +,::J'=>'-"
. 't 'f 0 M H l.
't'-5 MH�
� \J
c 1o
r--t 1---___,l.o"-l +<::N
,QI
yI
M-IDCX:l
I 'f !10 M H l. "2..------=3::.i\Jc OUT
2. � 12,FOUT
0'5CILLAIOP.,
E:�I0"-1 RI"
l"AC:TOl'l'f' 'S&L.l.C:T" R.48
-3 l�."'1-K 3'3K
-4 1�.1 t\ 2.0K
l';E:-F DE''Sl�IJAllO>-l'°S
LA�I \.l-'::>e-D 1'.lOTl.l'SED
u�
c.7, C.9
G.7
c.l"?.4
u,,
YI
RL/8
C.Z.l 2F-6. A4 Coarse Loop Oscillator PCB
ITHE-4 VERSION TP!:>
Schematic Diagram (Sheet 1 of 1)
1£SE UNITS HAVE
6700-D-31914-3 & -4 (Rev. F)
SUPPLY. CONTACT
l INFORMATION.
2F-13
10-60 MHz 10 MHz
z-2 dBm z-2 dBm
(CL IF from A3J1 ) (From A1O2
J )
TP2 J1 J2
F DIV
P1 11
(To A28XA6 via filtercons ) TP4
0DET
NOTE:
Leading zeros on
component number
references may be
disregarded.
A6 COARSE LOOP DIVIDER PCB PARTS LOCATOR 2F COARSE LOOP
A6
COARSE LOOP
DIVIDER
0+
TP1
CLRTN
TP5
CL ERR
2F-14 67XXBMM
0 1 2 3 4
C3
A +SYD +5VD
�y
Cl c 2.
Pl
+5) D
l't
o.� �·'
IK
U I;._ 5
(:;, )'\\
3
CL DA.TA, B
-1
B
IK
4 PL
4.
CL Cl K
c
+Sv
[4 �
+sv
�D.I
CIC
:JI ""70
CL IF i.. K
-J
� UIO
,1)7 v
F
EN
?I
L3
�rs------
+9V LP +SY
�.
G
CL RTN
�10
+ Cl'l
7'+ I(, 7
+ SVA
+T css
\7 10 SPARES
711-HC/4
MCI0/05
UIE UIF
2. 13 14
�
L
___rr-rn ---�+SVC
+5VD
\}'��
V +S:A V
I[,
H \;)
6
I,
67XXBMM
I I 5 I ·& I 7 I 8 I 9
-4-SV'
CRI '
IN'!-'+%��
'L"3V +sv
o.�
C.4
,> ,> . > RN2.
,>
:·
•
.
' IK .
't l'L
�·,
� U ..
II
I CI
12. 14
DO G.O
�
DI G.I
·� ID
02 G.Z.
..- s
D� G.3 -
13 4
CO �
- tLK
� 10 s
• SI ;r a 1
- -1... sz.
�8
U3&
- I'+
�K o.�
MCIOl3&
MC.101!5
4.3V
+sv
C7
'>
:>
••
�
•• , ,>
,>
,>
. RN2.
. I K. ��71 1 " +SVA
(8
NC.* MC.10105
4 l'L
11
00
CI
U? QO -
l'i
4 3 N I
��
If.I 5
LI C.
G.I .la._ ,ei.. s
5 )us
01 2 7 2
'°
,. 0 f. G.Z. � J U91'1. Q
-
-
5 0.3
13
C L
G.�
K CO
.L-.
� ,>RS
:> Sii
'>R(,
,>S I I NC ..ic
�
KCLKR o....L ,>
R9
�511 r-i
� C\5
�ODol--
9 SI
-1... S2.
8
,> R3
.
511
. ·�
'\'
MCIOl35 I�
+sv MCIOl36 � 5 UZ.01'1. Z.
·�
RIS
B Z.. S MC.IOIO'l
-�
�RI
>I
"
Z.7 �,• 511
R7.3
< R.IB
511
+SV/'\
LA'<>T U:O!;.I> NO/ US!;;)
�R75 CRf. qz - 4-
,>3b5 Pl I Vf.?..Z. Ul2.
0.7 G.8
-+SV"' Z.N.330(, 2.N'.5�� LS , 1<.NZ CS::!.,,54
Rl'+
+:OVA.. AAA
Tf'5 Rt 1, 1'7-Zi.
�
7i:} .. � .. �
511 Q8 R11, 7Z
t
,1; 10 d uzo
r-----4 ....... R.7 8
3 PR
Q
5 II ?;<
-;:;- UllB Gl �·
'> R7 Co >1n1 � 511 C55
iJ UllA 13 > I (,Z. > 1£.Z. R.75
� ��tLK l�U...K .
2. IZ
K Q. f, Q .2.
�
\(..
Cl &NO c:.. '- '
'(1s7 \� 0 ....,
NOlE.S:
2F-15
0 1 2 3 4
+5VA.
+ s " "'
¢ DE.TEI
A �0.1C 2. 2.
1B I
�1!17
CR3
C2. 3
n
of.5V R. '3 .3
14.'+Z.K
+ ISV
�. I
+ S Y "-
C 2. I
B
r- ��---
.1
IL\
Z. M H l.
.3
_n_.J'L
'V C.C. 100 h.S
N C. 4- A
Ul 3
N C. 1 0 B +5'1 Jll..
+5 V A +SV"'-
+s v ""
S R 3 '+
NC 3 C aA NC '+.'l 2. K
R 2. 8 R30 II G. B9 N C.
R 3 2.
511
'+87
2..37 1<. 13
____. C L Q ( z N C. 10
I C.Ri+ CRS
c
2. M H � M BOSOI t-1\130501
JLn__
'+O ns
G.Ei
Z.N390'1
�
J"2. .01
GS
Z.N 3,0'+
D C ZO
10 M H 'l.
� - 2. d B m 2.00 K H Z N O TCH FI LTER Y.00 KHt, WOT C.H rl LT I
( FROM AIO JZ. ) R 2. �
51.1
+ I SV
4- IS V
"RS.'4
R4 7 100
100
E
( '+ 2. +
�
10
s
RS I R.52
3 3 Z. 332..
C �8 C. 33
( 3 z. Ll .J 1 2.00PF 1 2.00PF
F
1 2 DO P F I Z.O O PF
•i o
R5 3
R4Ei '"5
3 3 Z.
C'fO C'l l
[34 C35
C. 3 7 R4 8 R.5 0
3.831<.
1 2.00 P F I Z.O O P F
1 1. C! O P F I Z. O O P F 100
G
A. Z.8 XAG Pl - I SV -ISV
l )�
L "+
'
:
� +15V
I
+ i S"-J L P (
,
:
I.
I
!
�0
, l es t
:
I
...
. 1
I I
I
I I LS
H -15V LP ��
1' � - 1 5V
.¢,0.1
I
j lf7 lc.s z.
m
5 6 7 8 9
. CTOR R.'Kl
.3.01 1<.
R3' C 2. 6
I I<.. t I S \/ 1 2.0 PF
C Z.'+
���
Rl8 R .'U
b3,0'Pl' 2.0.S K 1 00
',
:
6
LT I 007
· 'C2'
1
i R 3 !l
2'+. � K
"o"'
R. 3 7 -151/
IK
J
. C.2. 7 C31
39 0 f'F
P l AZB X f>... G
I
'E. R 2 0 0 K. Hl NO T C H F I LT E R
'
I '
I
ls
t l S '\/
4- c.L
I
MON
I
I
P2
I
I
R61 1 1.j. I
RS9
� CL 0 ERR
RS 8
I
,8. 1
l
I
R. '- 5 I
205 3
RS� C '+ '+ C '+5
�o E R R REF
IK I ZOOPF 1 2.00PF
,8.1
RID B
l
I
I
R60 I
3 3 2.
rT
I
I
C 'H• cu R'- 2.
1
I
'
IZOOfF 1 2.00PF
100 � GND G
R5 7
3.0I K
-15V
S P A R. E S
�NC �NC
+sv +sv +sv
2F-16 67XXB MM
2G-FINE LOOP: A9 AND A1 1 PCBs 2G-2 FINE LOOP ASSEMBLIES,
OVERALL DESCRIPTION
P
· ·· · . ••· ·· . ·· · ·
··· ··· ····· ···· ··· ...·· ·· ·.... · ·· · ·· ·
•
·
67XXB MM 2G-1
A9 FINE L OOP OSCILLA TOR,
DETAILED CIRCUff DESCRIPTION 2G FINE LOOP
sor PCB via the Al 7 PCB's DVM circuits. This volt Reference voltages for the shaping diodes, CR5-
age may be displayed on the synthesizer's front CR10 are supplied by U2A and U2B; diode emitter
panel LEVEL display as an aid in troubleshooting. voltage is determined by the U2A and U2B output
resistors. As the input voltage at U3 pin 3 rises
A 20 to 32.1 MHz signal from an external syn above approximately 2V, CRlO starts conducting
thesizer or other signal source may be used in place and puts R31 in the circuit. The gain of U3 then goes
of the fine loop oscillator's signal when finer frequen from unity gain to approximately 1.25. When the
cy resolution is needed. The A9 Fine Loop Oscillator input on U3 pin 3 reaches approximately 2. 9V, CR9
PCB receives a Tl'L-level signal that disables the starts conducting. This adds the parallel value of
V CO to reduce the possibility of spurious responses R28 and R29 in parallel with R31, which increases
being generated. the gain of U3. This continues with each successive
breakpoint until CR5 conducts. When CR5 conducts,
2G-3 A9 FINE LOOP OSCILLATOR, the gain of U3 is at its maximum. The output of U3,
DETAILED CIRCUIT DESCRIPTION the tuning voltage, is applied to the VCO tuning
varactor diodes, CRll and CR12.
Refer to the A9 PCB schematic (Figure 61-3) for the
following discussion.
2G-3.3 Voltage-Controlled Oscillator
2G-3.1 Loop Amplifier The fine loop VCO consists of Ql, a low noise FET,
and a resonant circuit made up of the varactor
The phase error signal, FL 0 ERR, at A9Pl-6 is diodes, CRll and CR12, in conjunction with the
input to the loop amplifier, UlB via the unity gain printed circuit transmission lines. The VCO is tuned
differential receiver, UlA When J3 is between pins through the frequency range of 200 to 321 MHz by
1 and 2 ( the normal position), UlB has no de feed the tuning voltage output of U3. The ALC amplifier,
back and the ac feedback is via C7 and C31. This U4, controls the output power of the oscillator by
provides a loop bandwidth of approximately 2 kHz. controlling the collector current of Ql. The output of
With J3 between pins 2 and 3, the loop amplifier Ql is applied to the Q2 buffer amplifier, which
becomes a unity gain inverting amplifier to allow reduces loading on the resonator circuit. This in
testing of the V CO without the phase-lock loop. The creases the Q (quality) of the oscillator, resulting in
output of the loop amplifier goes to the shaping reduced phase noise. Q2's output is sent to the two
amplifier, U3, and to A9Pl-5 v ia the voltage output buffer amplifier circuits and to rectifier diode,
divider/isolation network (Rl3, Rl4 and R16). FL CR14. CR14 is the rectifier diode for the ALC loop of
TUNE, the voltage from the divider Rl3 and R16, is the VCO.
monitored by the A23 Microprocessor PCB via the
Al 7 PCB DVM circuit for troubleshooting purposes. When an external source is used to get finer frequen
cy resolution than is available with the synthesizer's
NOTE fine loop, the signal, L HI RES EN, at A9Pl-4 goes
Pressing <Shift> TRIGGER 0 1 1 allows in to a TTL low. This forces the output of U4 to its
dependent control of the fine loop VCO via maximum positive value, cutting off the Ql oscil
the All Fine Loop Divider PCB. The FRE lator. This reduces the possibility of spurious respon
QU ENCY display shows the frequency of ses due to the mixing of the signals from the
the oscillator. the LEVEL display shows synthesizer's fine loop and the external source in the
the tuning voltage. Al2 YIG Phase Detector PCB.
2G-2 67XXB MM
A 1 1 FINE L OOP DIVIDER,
2G FINE L OOP DETAILED CIRCUIT DESCRIPTION
2G-4 All FINE LOOP DIVIDER, FLO 12, also from the AS PCB, is the only All PCB
DETAILED CIRCUIT DESCRIPTION control signal that is not sent serially. It is normally
low and goes to a 'ITL high only at Fine Loop oscil
Refer to the All PCB schematic (Figure 61-5) for the
lator frequencies of 300 MHz or greater.
following discussion.
67XXB MM 2G-3
FINE LOOP ASS EMBLIES, TROU BLESHOOTING 2G FINE LOOP
provides one output pulse for every two output pul an ac signal to be injected for testing of the notch
ses from U3. If US is programmed to load a count of filters or for exercising the phase-lock loop.
one at every 100 kHz cycle, the input to Ul4 in
creases to 201 M Hz to provide 100 kHz at U9-5. If
2G-4.6 Notch Filters
U3 is programmed to load a count of one for each
100 kHz cycle, US must provide an additional 10 The fine loop phase information at the output of U2 1
counts. This requires the input to U l4 to increase to goes through the notch filters before being sent to
2 10 M Hz . By loading different counts into U3 and the A9 Fine Loop Oscillator PCB. When the divider
U S , the entire fre quency range (from 2 0 0 to is set for fractional division, there is a 10 kHz com
300 M Hz) can be covered in 1 M Hz steps. ponent and its related harmonics on the output of
U2 1. If left unfiltered, this causes 10, 20, 30, and
At 300 M Hz, the FLD 12 line goes to a TTL high. 40 kHz sidebands on the fine loop oscillator output
This causes U5 to output one pulse for every three signal and shows up in the final RF output signal.
input pulses which is essentially the 100 M Hz The notch filter circuits re duce these sideband
decade. The only difference in the programming for levels.
the Fine Loop counters, at 200 and 300 M Hz, is the
FLD 12 line. The input data to U3, US, Ul2 and U7 The All Fine Loop Divider PCB contains five active
is the same at 200 and 300 M Hz. Incrementing in twin-T notch filters. There are two each for 10 kHz,
10 kHz, 100 kHz, 1 M Hz and 10 M Hz steps is iden since this is the highest amplitude and can cause the
tical to when the frequency is at 200 M Hz. most spurious responses. There is one each for
20 kHz, 30 kHz and 40 kHz. These filters have a
The 100 kHz signal at U4-6 i s output via flip-flop U9 40 dB (typical) rejection at their notch frequency.
to the phase/frequency detector to be compared with
th e d i v i d e d 1 0 M H z refe r e n c e frequen cy. U 9 The output of U26 is the (filtered) fine loop phase
provides 2 clock cycles of delay and determines the error signal, FL 0 ERR, that is sent via AllPl-3 to
100 ns pulse width for the 100 kHz signal. The out the A9 Fine Loop Oscillator PCB to control the fine
put signal at U9-6 reloads the counters for the next loop oscillator's frequency. The output of U26 is also
1 0 0 kHz cycle, loads two counts into the Ul2 sent via the filtering an d isolation network (R46,
counter, and sets Ul3-5 low and U l3-9 high. C48, and R4 7) and connector AllP l-6 as the signal
FL M ON to the Al 7 Analog In struction PCB's DVM
circuit. The A23 Microprocessor monitors this signal
2G-4.5 Phase/Frequency Detector
via the Al 7 PC B's DVM to determine if the fine loop
The fine loop phase/frequency detector, U20 operates is phase-locked. When the fine loop is phase-locked,
the same as the reference loop phase/frequency this voltage is very close to OV.
detector on the A7 Reference Divider PCB (refer to
Section 2E-Reference Loop for a detailed circuit 2G-5 FINE LOOP ASSEMBLIES,
description). However, the fine loop phase/frequency TROUBLESHOOTING
detector operates at 100 kHz instead of 10 M Hz .
Refer to the troubleshooting information located in
The outputs of U20 are sent via the integrator filter the front portion of Section 2-System De scription
and Troubleshooting. This information provides a
networks, Rl3-C26 and Rl4-C27, to the differential
receiver, U21. The output of U2 1 is the (unfiltered) list of error codes th at may be displayed as a result
fine loop phase error signal. R20 provides a de offset of failures in the fine loop subsystem and probable
voltage for U2 1 which results in the phase/frequency causes of the failure s.
detector operating in an offset mode. This prevents
the phase/frequency detector from operating in the 2G-6 FINE LOOP ASSEMBLIES,
d e a d z o n e and d r a s t i c ally affecting the l o o p SERVICE SHEETS
dynamics. When the Fine Loop is phase-locked, the
Table 2G-l (page 2G-l) presents the arrangements
loop amplifier on the A9 Fine Loop Oscillator PCB
of the block diagrams, schematics, and parts locator
forces the output of U2 1 to be OV. This causes the
diagrams for the A9 and All PCBs.
output pulse on U20-9 to be wider than at U20-5,
thereby canceling the approximately three degrees
of offset provided by R20. Test point 4 at Rl 7 allows
2G-4 67XXB MM
2G FINE LOOP
FL DATA :
FL CLOCK
1 0MHz
-2dBm >-
(FROM A1 0J1)
L HI RES EN
(FROM A1 6
FM PCB)
67XXBMM
FINE L OOP BLOCK DIA GRAM
1 00 kHz
(TO A25
SWITCHING
POWER
SUPPLY PCB)
2G-5
200 321 MHz 200 321 MHz
• •
(FL RF to (FL RF to
A1 1 J1 ) A12J1)
J1 J2
TP9
-2.2V @ 200 MHz
+0. 7V @ 321 MHz
TP8
+3.0V @ 200 MHz
+9.0V @ 321 MHz
TP2
I
OV between TP6
TP1 and TP2 GND G
when <I> locked
TP1
P0 1
P1 11
(To A28XA9 via filtercons )
A9 FINE LOOP OSCILLA TOR PCB PARTS L OCA TOR DIAGRAM 2G FINE LOOP
2G-6 67XXB MM
0 1 2 3 4
+ 1 5V CD R�: R63
p l lK 5 1 1 + 1 sv CD
/'
A
R17
TUN ING SHAPER
TP4
1 . 47K CR5
01
RlB
FD300
�
- 15V CD
� o
CR6 l 5 . 3vl
� FD300 CR7
FD300 CRB
B
5 . 1 1K 90 . 9K 30 . l K 1 1 . BK 1 0 . 2K
CR10 3 . 0V 200 MHZ
CR4 R31 9 . 0V 32 1 MHZ
/'
1 N8:1.:'.:
10 5K FD300
+ I!
6. 2v TPB
J3 1 C30
I!
TPl
c
Pl lBOPF
RlO 2
J
T
7 RB
FL 0 ERR RE� 3 . 0 1 K + 1 5V CD
3 . 0lK
I ---"/v'·�---
. 22
foB
J CR3 3
,--
01
6
FL ERR NE5532
'
04
I _[
2 . 7V1!2 OMHZ
,
I
5 . 6Vl!32 1 MHZ
�
07
0
D
J NE5532
R13
lK
10 Rl
+ 15 VLP + 1 5V CD
33 Cl
I
'"
T
R14 C10 16
,
�o 1K 17
+_L,_
LOOP AMP
� R2 J
E �-�--t> + 15V @
33 +�2
/\,\,
o
i
Ti 7,
R3
C3 + 1 5V @
v
33
�o
�R,
+
-2 . 2V I! 200 MHZ
+0 . 7 I! 32 1 MHZ
..,._
R45
+ 1 5V @ TP9
36
.1
F
�
l_ UI
L HI RES EN 04
R4 LF356
CD
33�10-1--- --lt> - 15V R66 - 15
4 . 02K
- 1 5V LP C4T 2 . 9V ON
'1/
- 1 . 2V OFF
R5 7 R67 Ji32
�-�--<r>-----t> - 1 5V @
+
10 33 . 2K
� 1
G
C5�
'-J.....'
R6 NOTES:
+
- 1 5v @
\,- ---t> - 15V @
0
33 10--1..- UNLESS OTHERWISE SPECIFIED.
c 61 1 . RES ISTANCES ARE IN OHMS, CAPACI TANCES ARE IN
MICROFARADS. AND INDUCTANCES ARE IN MI CROHEN�IES 4 . FACTORY·
- + Rl 1* R19
l TP6 2. FILTERCON ARE USED BETWEEN THIS PCB EDGE CONNECTOR 5 . TEST POI
GND G AND THE A2B MOTHERBOARD CONNECTOR . EACH SIGNAL PATH
7
CONNECTION HAS (TYPICALLY) 1500pF CAPACITANCE BETWEEN 6 . TROUBLE!
IT AND CHASSIS GROUND BOXES AF
H
W >>---'---�-o 3. GROUND SYMBOLS USED ON THIS ASSEMBLY SCHEMATIC SET 7 . PCB TRA
ARE DENOTED AS B . STATIC
67XXB MM CHASSIS GROUND rh I NCLUDE:
I 6 a. 1
I
8 9
+ 15V @
C17
C12
10 o .� R43
5 . 1K
BUFFER AMP
C23 Ji
R50
200-321 MHZ
-5 dBm
27 FL RF TO A 1 1 J1)
R49
1K
"-
1BOPF
CR12
" ZCB04B
CH
� J310
�
R53
5 . 1K
R35
B U F F ER A M P
750 ALC AMP
C29
+ 1 5V @
C27 J2
'.�
1BOPF
@
R59
+15V
CR15
R61
7 1 . 51< CR14 �- '·-�
43
200-321 MHz
5dblll
M8D501
MBD501
CR1
- 1 5V @ � FL TUNE MON
FD300
1'
REF DESIGNATIONS
LAST USED NOT USED
C32 C16
ISOLATED GROUND CR1!5 CR2
J3 CR13
L4 J1, J2
-SELECTED COMPONENTS ARE DENOTED WITH AN ASTRISK Pt TP3
1911 R2 111 RbO • Q6 TP7 Figure 2G-4. A9 Fine Loop Oecillator PCB
(,) R67
Schematic Diagram (Sheet 1 of 1)
INTS ARE DENOTED AS: 'f' TP9
l.ESHOOTING VOLTAGE ANO POWER LEVELS INDICATED IN
U4
6700-D-31709-3 (Rev. L)
TYPICAL OR NORMAL LEVELS
MISSION LINE PATHS ARE OENOTED AS: TL
NSITIVE COMPONENTS USED IN THIS ASSY
CR 14, CR1!5, Q2-Q6, U3, U4
2G-7
·
10 MHz
... - 2d8m
(From A 1 OJ1 )
J2
P1 11
TP1
(To A28XA1 1 via filtercons)
FL RTN
NOTE:
Leading zeros on
component number
references may be
disregarded.
A 1 1 FINE LOOP DIVIDER PCB PARTS LOCA TOR DIA GRAM 2G FINE LOOP
TP2 TP4
A1 1
FINE LOOP
DIVIDER
2G-8 67XXB MM
0 1 2 3 4
FLD 12 -+-:-<( >
, s 51 +sv®
A 2 8 XAl l J P l
A �O. t Cl
Va
19
'I
C <- R o.
4
a.
A29 X A \ I Jl 5
a.,
I 6
Go
10
F L DA TA �<
I J; > 4
z
13
uz °"
o.
a, If
IZ
8 13
�
tf,,111)
1
7
B 74HC / 6 4
H"®cs
+S'V@
� R A C T I O N A L 7 CO N T RO L
o. �
c
�O.! Cl/-
'l
.�
v"'
3 /4
/6
11,,..
Ct.<! /)A II
4 15
06 ll
,q 5 2
a� c
" )· '1 {, N C.C
6lo CJ
A28 XA II Pl 8 o, 10
U ID II
I U IC. ·) 6 Q, a11
B o..
FL C L -< �< > .z s
I J; 74HCl'f
MC 7BO'S 74HC 1 64
"'"" £/Al
Et>tl U7
D I
LI VR / S/£
+ 9 VL P
�< > IN OUT <.ND
I J 6NtJ
74/l.7
B
+ s vD
I
8
L 4-
10 llD �O.! CN
-RT
Va
E C/ 3
co
�O.I Il l
81 :i i
4
112 :u
13
82 ::u
A.3 to
:i.
S3
/I f(
U//
lW
RS4 f<.'55
F RS � "'iy "2 7 "4 74U Z 8 3
l; 5 R5IO
v«
·�c. OU <;, 1 1
II
13
JI 741'150'l
<; N
200 - �2. I C.
�-s d B m
lvli-lZipooof'F RZ 13
1 0/1 1 D I V I DER
( FL RF F R O M I 54 ,"':>
G A 9.J I ) 117
N O T E S '.
'+ 6 '+ Alt flHE LOOP DIVIDER SCllEllATIC NOTES: I. FLTERCOHS Al
RB
PCB EDGE COi
1. UNI.ES$ OTHERWISE SPECIFIED,
Pl 4 6 '+ RESISTANCES ARE IN OHllS )0),
llOTHERBOARC
A 2 8 XA l l
RTN -;1<<--r �
I
SIGNAL PATH C
CAPACITANCES ARE IN lllCROFARADS ()lf),
(TYPICALLY) 15
11 INDUCTANCES ARE IN lllCR OHENRIES (µHJ. BETWEEN IT Al
FL
2. S1GHAL FLAGS INDICATE MATCHING 4. GROUND SYllll
H CONNECTIONS BETWEEN llUL TlPLE
SHEETS OF THIS SCliEllATIC. THE
SCIEIATIC SE
.
,.. I
t
A o,. .,
� ·� I 3
e.L e Q, ..!:->J[.
I vt
8
Ct.O
I U3 � ' 7d.4Sti
� -Lile
II
"
t:.L.
Go -NC
IZ
�>Z _L Ci.b
....,,. B >I U5
- ....'>
....!. 2
7 7./!J(,.
·�/ 14S;;"
/,All)
+�II@ '
.
c�� . " UV(!}
0. 1 C7 ...L
IP ()./ �· 11 I I I I +oi+- l
� "'
l'ie
� s ..._
!,.. ,. 7'fS l l Z.
.J..,. ,.
v...
100 K H l
l'lt
IO
15 . ., -':JI· G/41 . '\ " l'lr
II .r " " 3
:r Q
., Z/IC..
ll 2 ·�. B
/I
c � /Z .. . -
""
1.1'1 r-2<� V'I
/) 4 .,._,,SI/ --1.!. " B Q 7 z. " -A a DI V I D ED FL Rf
U.l(
I
CL
<!<A: ,..• 4'Alb �,_ ( IOO K H ! )
8
t:tO
I U8 'f'� . -
r" -ij
�> Z ..
4-Nb ..
:
· 7- 1fSl'fl •.
-
+-S
V@
+ 1 1 . ....,...
. ... .. ....,,.
... ...L. CIS +4"@
+rto@
--.
,.,.
�()./ r-.i
"?j' u t:I� �0:1
..L Cl1
•
10
JI �
8
Q.� . 14 �PA v"
,.
5
3
t:
6'. 6\rH( H1() JJ
l / 2. 3
J �
// j) � IZ t.JI
-� A
14.45 11
I l U3
�
�
__.!.;> Z
I
Cl
ao
I UIL � ' '' fip.!.Ne
I< A
C<.<c "-
ii
7 74S l '1 7
10 1451\'Z.
+IV@ fill
II
:r Q 'f
rt;:: ()/3
I /Z le. 8 � r;l-Hel
9 c�
'( I �
IS ARE USED BE1WEEN TllS L 1110U81.ESHOOTllG VOLTAGE AND POWER
CONIECTOR AND THE A2ll l.EVEUI lllOICAml IN BOXES ARE 1YPICAL
MAD COHNEClOR. EACH OR NOlllW. LEVELS.
illl CONNECTION HAS
I) 15Gll!Jf CAPACITAllCE 7. STATIC SEHSITIVE co.PONENl'S USED II Figure 2G-6. All Fine Loop Divider PCB
THIS ASSalY llt. lllCLll:lE
IT Nil OIASSIS GROUll>. Schematic Diagram (Sheet 1 of 2)
Cll1, Qt, US, US, 117-013, U11, ¥111
MlllOlS USED ON THIS ASSElY
lBl.
� SET ARE DENOTED AS:
6700-D-31711-3 (Rev. H)
&ROUND : m
I GROUM>5: \] ,
R-\A<OE- DE:Tege>l2,
A - SY(!) 16
Vu:.
u 19
I Q,- 3
-S VQ) A
108 5 NC.
7'fl S13 Z -t-SVQ)
14 (,, NC /{ 1 5
7
�
IOo
c zs
�O.I + S VQ)
RI/
B 0 2- I I<
Rl3
2 '1"3C)Oy 5 3
I 0 MH 2
? - 2- d B m
7« -S390 6
NC.
S. 3 H:.
� /000/>PCZ.6
c
RIZ
•0 I IC
3 RN
9
'::l 1 \J I D E D >"L 12.. i::
( ; OO k H z ) I /BC
Q
1 N
C.
S. 3 6 1<
9 CZ7
1000,Pf.
+o4
..ll.Ll
1 0 0 1<. H i_
_4o
K
f?3 t
1.81
RZ6
2.41::
J, b d .
C36 C. 3 7
ZZOOp F Z:i?OOpF
C3Z. I C33 R31J
F ZZoO,.F 2200 , ,.. 7 511
_
I Rzq
-1---+-<�7-< /, C/61(
R3S
'f. 53 1::. 1.
�7.87K. !<.J o
2ZoOpF zzoop;:
H
5 6 7 8 9
J
p I A 28 X A l l
--------------------------------------....+.:.
r--
7< i �>4- I 0 0 kHz REF
Rn RZO
+ s v0
l
s. tbK. (,04/C
1( 1 6 RI'
3. 161:.
!(ZI
7
7. Z3K
ezq
R24
C26 Si l
zzcof' F 220 0pF
�Z3
3. b/IC "1 < 5
C3o 1!3 / q , 5 3 1<
A 28XA: i
Pl I
RL/6 51
/(IJ 7 16
���--4-+--�A.Ar--..J\l\A,� �>-!-- F L MON
Cl/8 /K T
�·! rh
PZ 1
13 3I
Rfl/ 169
�
l >-t-- F L ,0' E R R
I
1<,IJ"/ 14 4 I
'<3b
7. 23 K � �>+- F L 0' E R R REF
N�SS32.
-IS Vz
et:.. NE.553 1.. CW C: llS
v /67 I J I
ztOOf'F ZW O!'F I I
'O C'II Rl/ 4
zzoo,, F 7 I
'()pi=' R39 I
I
N OT U SED
�NC
+S Y(i) + s va;;
2G-10 67XXB MM
2H-YIG LOOP/ FM MODULATION 2H-1.l YIG Loop/FM Subsystem Overall
SUBSYSTEM: A12 AND A16 PCBs Functional Description
- c
Amplifier assembly.
OVERALL ASSEMBLY LEVEL
---- ---�---
· -�����
�-� ;:�'.�� . ............. .. . . I �;������� . . ��.��. . . .
. . .. � ""'' -
The other input to the Sampler/IF Amplifier is a
sample of RF power from the YIG-tuned oscil
PCB LEVEL lator output. Sampling the oscillator's output
................. .......
.. .............................. ..............
....
....
.. ......
.. ,
.......
. ,,.... �-.
. .... .......... ........ __.
........""""
.. .......... ...
..
A12 VIG Phase Detector PCB signal at the rate of the adjacent coarse-loop
Detailed Circuit Description Para. 2H-2 2H-3 harmonic produces a low frequency difference
Block Diagram Fig. 2H-1 2H-9 signal which is the YIG IF signal (20-32.1 MHz).
Parts Locator Diagram Fig. 2H-3 2H-12
Schematic Diagram Fig. 2H-4 2H-13
The A23 Microprocessor programs the coarse
A16 FM PCB loop output frequency so that one of its har
Detailed Circuit Description Para. 2H-3 2H-4 monics will be within 20-32.1 MHz of the desired
Block Diagram Fig. 2H-2 2H-11 YIG operating frequency. The YIG Phase Detec
Parts Locator Diagram Fig. 2H-5 2H-14 tor compares the YIG IF signal to a 20-32.1 MHz
...
Schematic (Sheet 1 of 4) Fig. 2H-6 2H-15 frequency reference signal that is derived from
(Sheet 2 of 4) 2H-16 the 200-321 MHz output of the fine-loop oscil
(Sheet 3 of 4) 2H-17
lator. The YIG phase detector fine tunes the YIG
(Sheet 4 of 4) 2H-1 8
via the YIG FM coil driver to eliminate any fre
A30 Sampler/ quency difference between the two signals.
IF Amp Assembly
Detailed Circuit Description Para. 2H-5 2H-7 Phase-locking the YIG-tuned oscillator over a
Parts Locator Diagram Fig. 2H-7 2H-19 broad frequency range is accomplished b y
Schematic Diagram Fig. 2H-9 2H-21
programming the coarse loop to various frequen
cies that have harmonics close to the desired
A31 Multiplier/
Power Amp Assembly operating frequencies. Exact frequency tuning
Detailed Circuit Description Para. 2H-4 2H-7 for each desired operating frequency is ac
Parts Locator Diagram Fig. 2H-8 2H-20 complished by programming of the fine-loop os
Schematic Diagram Fig. 2H-10 2H-22 cillator. (In each case, the YIG-tuned oscillator
is first tuned via its main tuning coil to the
approximate desired operating frequency.)
67XXB MM 2H-1
YIG LOOP/FM SUB SYSTEM OVERALL FUNCTIONAL DESCRIPTION 2H YIG LOOP I FM
The programming (tuning) range of the coarse In the phase-locked mode of operation, the FM
loop oscillator provides harmonic signals in the circuits are configured to operate as follows:
range of 1.98 to"" 40 GHz. The harmonic signal
• The FM modulation signal is filtered, as DC
spacing varies throughout this range from
FM operation is not possible in this mode. The
1 MHz to 12 MHz. Thus, any YIG-tuned oscil
filter selection in this mode is normally under
lator output frequency can be down converted to
control of the A23 Microprocessor.
a YIG IF signal between 20-32.1 MHz. Since the
coarse-loop output is synthesized, its frequency • The FM Integrator circuit is not bypassed in
can be acljusted only in finite steps. The result this mode; therefore, the FM modulation sig
ing harmonic steps may be as large as 12.1 MHz nal from the amplifier/filter circuits is in
at high frequencies. tegrated. This circuit also amplifies the FM
modulation signal by a factor approximately
equal to the YIG loop gain factor and with the
The YIG loop is fine tuned by varying the 20-
same response characteristics (i.e., high gain
32.1 MHz reference frequency signal applied to
at low frequencies, decreasing gain as the
the YIG loop phase detector. This signal is
modulating frequency increases).
derived by dividing the fine-loop oscillator signal
by a factor of 10. By programming the fine-loop • The output of the integrator circuit is fed into
the A12 PCB's YIG phase-lock circuit to cancel
oscillator, this signal can be adjusted in 1 kHz
the correction error signal that is caused by
increments over a 20-32.1 MHz range. The
the frequency modulation of the RF output
resolution of the fine-loop oscillator (hence the
signal. Without this function, modulation fre
resolution of the RF output signal) is 1 kHz, which
quencies below the YIG loop bandwidth (ap
is much finer resolution than is available from the
proximately 10 kHz) would be removed by the
coarse-loop alone.
YIG phase-lock loop circuitry.
• The attenuated FM modulation signal is com
NOTE
bined with the YIG frequency error signal at
Whenever the syn thesizer is operating the input of the FM Deviation Limiter circuit.
in the phase-locked mode, the frequen The combined signal output from this circuit
cy of the YIG IF will always equal 1/ 10 then goes to the FM amplifier in the normal
the frequency of the fine-loop oscil manner (see below).
lator.
In the unlocked :node of operation, the FM cir
For applications requiring resolution finer than cuits are configured to operate as follows:
1 kHz, an external 20-32.1 MHz synthesizer can • The FM modulation signal is not filtered (i.e.,
be connected at the rear panel to substitute for DC FM operation is selected).
the internal fine-loop signal. The tuning resolu
• The FM Integrator circuit is bypassed in this
tion is then determined by the resolution of the
mode; therefore, the FM modulation signal
external syn thesizer.
from the amplifier/filter circuits is not in
tegrated.
b. FM Modulation Functions
In addition to the YIG loop's frequency phase In both FM operating modes, the output of the
lock control circuitry, the YIG loop contains the amplifier/filter circuits (U4) goes to the input of
FM modulation circuitry that allows the user to the FM attenuator circuit and the input of the
frequency modulate the RF output waveform. A FM peak detector circuit. The output from the
portion of this circuitry is also used for the nar FM attenuator circuit goes to the FM limiter, FM
row band sweep function (i.e., sweeps s;50 MHz). sensitivity circuits, and FM output amplifier.
The external FM signals from the front and rear The FM output from the A16 PCB is routed to
panel connectors are routed to input buffer the A18-A21 YIG driver PCB(s). The FM
amplifiers and combined. The output of the amplifier of the YIG driver board selected by the
input amplifier chain is fed to the input of the A23 Microprocessor drives the FM coil of the
filter networks. YIG-tuned oscillator assembly.
2H-2 67XXB MM
2H YIG LOOP/FM A 12 YIG PHASE DETECTOR PCB CIRCUIT DESCRIPTION
The field produced by the YIG-tuned oscillator's signal from Ul goes to U2, which is another divide
FM coil interacts with the magnetic field that by-10 counter. The 2-3.21 MHz TTL signal from U2
results from the current flow through the YIG is the frequency reference signal that is connected to
tuned oscillator's main tuning coil. The modula one input of the YIG phase/frequency detector circuit
tion of this magnetic field changes the frequency comprised of U4A and U4B.
of the YIG-tuned oscillator at the rate of the
modulating frequency. Maximum deviation in
the unlocked mode is ±25 MHz. 2H-2.3 Phase/Frequency Detector Circuit
67XXB MM 2H-3
A 12 YIG PHASE DETECTOR PCB CIRCUIT DESCRIPTION 2H YIGLOOP!FM
The 0 MOD and 0 MOD REF phase modulation troubleshooting purposes. These codes are listed in
signals from the A16 FM board are filtered by the Table 2-2 located in the front portion of Section 2-
RC filter networks comprised of R39, C26, R40 and System Description and Troubleshooting.
R38, C27, and R41. These filtered signals are com
bined with the YIG phase error signal that are input 2H·3 Al6 FM PCB CIRCUIT DESCRIPTION
to the phase detector, U6. During the FM modula
tion mode of operation, these signals change the The circuitry contained on the A16 FM PCB provides
offset of the phase detector at the FM modulation the following functions: YIG frequency/phase lock
rate. This cancels the error signal generated by the ing, FM modulation, and narrow band sweep opera
phase detector circuits in response to the FM tions. Refer to the overall block diagram of the A16
modulation. Without this canceling effect, the phase PCB, Figure 2H-2, and to the A16 PCB schematic
lock loop would remove any FM modulation applied diagram, Figure 2H-6.
to the RF output signal that is within the 10 kHz
YIG loop bandwidth. 2H·3.1 Digital Control
2H-4 67XXB MM
2H YIG LOOP/FM A 16 FM PCB CIRCUff DESCRIPTION
proximately ±40 MHz, which prevents saturation of to the filter circuits. It is inverting or non-inverting,
the circuits following U24. This improves response depending on the position of W5-W8 jumpers.
time and eliminates overdrive conditions.
Jumpers W5-W8 provide a means of changing the
From U24, the error signal goes to output amplifier polarity of the modulation signal. Normally, a nega
U25 and to the U20 FM Sensitivity Cal DAC. The tive going modulation signal causes the RF output
Cal DAC can adjust the sensitivity approximately frequency to increase. By removing W5 and W6 and
±10%. There are variations in YIG-tuned oscillator installing W7 and WS, the frequency will increase
sensitivities, and component variation in the FM with a positive input. From U4, the FM signal goes
driver circuits; the Cal DAC provides a means to to U28 FM peak detector and UlO FM Attenuator
compensate for these variations. The Cal DAC data DAC.
for each YIG-tuned oscillator driver is stored in
EEPROM on the A23 PCB. At the bandswitch points,
this data sets the DAC so that each YIG driver has 2H-3.4 FM Attenuator Circuits
the same sensitivity. This provides for a more con
stant loop gain. It is also a requirement for a These circuits include DAC UlO, buffer amplifier
calibrated FM and sweep width. Ull, and two 20 dB attenuators comprised of resis
tors R24-R27 and analog switches U12A-U12D.
Whenever the user enters a FM Sensitivity value via
2H-3.3 FM Input Amplifiers and Filters the front panel (or GPIB), the A23 Microprocessor
sets the DAC/attenuators accordingly. The at
The external FM modulation signals from the front
tenuator circuits provide a resolution control of ap
and rear panel connectors go to the input buffer
proximately 0.02 dB throughout a 90 dB dynamic
amplifiers UlA and UlB, respectively. Diodes CR1-
CR4 and resistors R2 and R5 provide overdrive range.
protection for UlA and UlB. Resistors Rl and R6
provide the terminations for the two external FM The two 20 dB attenuators are used to provide high
modulation signal inputs. values of attenuation, therefore allowing the DAC to
be used only for low attenuation values. This avoids
The outputs of UlA and UlB go to the input of AC feedthrough of the DAC at high frequencies.
differential receiver amplifier U2, which sums the
two external modulation signal inputs. The output Buffer amplifier U13B provides a high impedance
of U2 is applied to the inputs of the two filter net load to the attenuators. With UlO DAC set for 0 dB
works and to analog switch U3A attenuation and the 20 dB attenuators in the 0 dB
attenuation state, the signal at the output of U13B
In the unlocked FM mode of operation, the A23 will be 5V peak for a 1 V peak input signal. At 10 kHz
Microprocessor selects the DC FM path (U3A closed) peak deviation, this signal will be about 50 µV peak
and extends the FM deviation range from de to for a 1V peak input signal.
25 MHVV.
67XXB MM 2H-5
A 16 FM PCB CIRCUIT DESCRIPTION 2H YIGLOOP/FM
The FM integrator circuits amplify the FM modula rectified by CR27 and CR28 and go to comparator,
tion signal by a factor approximately equal to the U27 A. When U27 A switches states, a DC level is fed
YIG phase-lock loop gain factor and with the same back to U19B via CR26 which forces the YIG-tuned
response characteristics. This signal is inverted and oscillator to a higher frequency. Resistors RSO and
fed back to the A12 PCB. R77 set the comparison voltage of U27A to ap
proximately 1 volt; R79 is a positive feedback path
The signal from the FM attenuator goes to amplifier that provides hysteresis for this circuit.
U13A, which has a decreasing gain with increasing
frequency characteristic. From U13, the signal goes
2H·3.7 Notch Filter Circuits
to amplifier, U15. The input circuit of U15 includes
the limiting network comprised of CR13, CR14 and Operational amplifiers U32A and U32B are con
R33. This circuit provides overdrive protection in the figured as a notch filter with a center frequency of
event of sudden level changes, such as connecting 200 kHz (this is the frequency of the main fractional
and disconnecting the FM modulation signal source. division sidebands generated by the A6 Coarse Loop
Divider). Operational amplifiers U33A and U33B
From U15, the signal goes to the input of the Phase comprise a 100 kHz notch filter that reduce any
Modulation Sensitivity DAC, U20A The outputs of 100 kHz sidebands caused by the switching power
U15 and U20A are summed by R37 and R29 at the supply and 100 kHz reference frequency signals
input of U16. This provides adjustment of the fre generated by the All Fine Loop Divider. Operational
quency response of the signal generated by the FM amplifiers U34A and U34B comprise a 50 kHz notch
integrator so it can be matched to that of the phase filter that filter out any sidebands that are also
lock loop. The Phase Modulation Sensitivity DAC is caused by the 50 kHz switching frequency of the
adjusted during the FM flatness calibration proce power supply.
dure.
When changing the YIG-tuned oscillator's frequency
Amplifier U16 also has a decreasing gain with in output in large increments, the notch filters are by
creasing frequency characteristic. From U16, the passed via analog switch U22A to provide a faster
FM signal goes to amplifier Ul 7, which is also over lock time; when lock is obtained, U22A is opened.
drive protected by CR15-CR18. From Ul7, the FM The switching of U22A is controlled by the A23
signal goes to the phase modulation metering cir Microprocessor. When U22A is closed, the output of
cuits and to Al2 YIG phase detector. U34 is swamped by the low output impedance of
Ul9, and the signal from U19B is fed to the input of
the YIG loop amplifier.
2H·3.6 False Lock Detector
The YIG phase error signal from the Al2 PCB goes
2H-3.8 YIG Loop Amplifier
to differential receiver, U19B. From U19B, the error
signal goes to the input of the notch filter circuits. Operational amplifier U23 is the YIG loop amplifier.
Analog switch, U22A, is a bypass for the notch fil When the YIG loop is phase-locked, it has a loop
ters; when closed, it routes the error signal directly bandwidth of approximately 10 kHz. When the
to the input of the YIG Loop Amplifier (U23). notch filters are bypassed by analog switch U22A,
the loop bandwidth is approximately 50 kHz. When
The YIG phase error signal will contain high fre the YIG loop is unlocked (during switching in step
quency signals whenever a change in the YIG fre sweep, or in analog sweep mode) analog switch
quency causes a zero beat with the harmonic comb U18B is closed to prevent the output of U23 from
signal from the A31 Power Amplifier. Because of the limiting at ±15V. This provides faster locking when
very high gain of the A30 Sampler/IF Amplifier, any the YIG is within the capture range of the phase
noise at the zero beat will be amplified. It is possible detector.
for the YIG loop circuits to sense these signals as a
coherent IF signal and to falsely lock at that point. Whenever the loop is unlocked, analog switch U18C
is opened, which disconnects the output of U23. This
The output of U19B is amplified by U27B and only prevents the YIG FM coil from receiving an er
high frequency components of the signal are coupled roneous phase error voltage. When closed, U18C
by C32 to the doubling rectifiers, CR27 and CR28. connects the phase error signal from U23 to the
These high frequency components of the signal are input of the FM Deviation Limiter amplifier, U24.
2H-6 67XXB MM
2H YIG LOOP/FM A 16 FM PCB CIRCUIT DESCRIPTION
The processed phase error signal at the output of The output of U24 goes to the input of the FM Sen
U23 is connected to the divider/filter network com sitivity DAC, U20B. The outputs of U24 and U20B
prised of R74, R72 and C34. The YL TUNE MON are summed by R68 and R70 at the input of U25.
signal is picked off at the junction of R74/R72. This This provides an adjustment range of the FM sen
signal goes to the Al7 Analog Instruction PCB's sitivity of approximately 16%, with a 0.12% adjust
DVM circuit. The A23 Microprocessor monitors this ment resolution . The FM signal at the output of U25
signal via the DVM to determine if the YIG loop is has a nominal 4 MHzJVolt sensitivity
phase locked, and also when performing various Al7
Tune DAC adjustments. The amplitude of this 2H-4 A31 MULTIPLIER/POWER AMPLIFIER
monitor signal is approximately 5 MHzJV. ASSEMBLY cmcuIT DESCRIPTION
67XXB MM 2H-7
A30/A31 ASSEMBLIES CIRCUff DESCRIPTION 2H YIGLOOP/FM
Resistor Rl provides a DC return for the sampler Emitter follower QlO drives the output connector,
diodes and Cl and C2 couple the IF signal to the IF A30J5. Capacitor C36 couples the output signal from
preamplifier. Since the output impedance of the the emitter of QlO to R52 which provides the 50 ohm
sampler is very high, Ql FET amplifier presents a output impedance for A30J5.
high input impedance to the sampler to prevent ex
cessive loading. The output from the source of Q1
2H·6 YIG LOOP ASSEMBLIES,
goes to emitter follower Q2. Resistors R9 and
TROUBLESHOOTING
capacitor C6 increase the high frequency gain of this
stage to compensate for the loss in output of the
Refer to the troubleshooting information located in
sampler with increasing frequency. The overall gain
the front portion of Section 2-System Description
of the Ql-Q2 gain stage is about Xl.
and Troubleshooting. This information provides a
list of error codes that may be displayed as a result
The signal from Q2 goes to amplifier stages Q3 and of failures in the A12 YIG Phase Detector PCB and
Q4 which have an overall voltage gain of ap the A16 FM PCB and probable causes of the failures.
proximately 24 dB. The signal from Q4 goes to Q5,
which drives the 72 MHz Low Pass Filter.
2H-7 YIG LOOP ASSEMBLIES
SERVICE SHEETS
2H-5.3 72 MHz Low Pass Filter
Table 2H-1, on the first page of this section, lists the
Inductors Ll-L4 and C18-C22 comprise a 72 MHz
block diagrams, schematic diagrams, and parts
low pass filter. This filter removes any signals
locator diagrams for the A12 and A16 PCBs that are
caused by intermodulation products of the sampler,
contained in this section. It also lists the schematic
which are produced when harmonics of the RF sig
diagrams and parts locator drawings for the A30
nal mix with harmonics of the comb signal and
Multiplier/Power Amplifier and A31 Sampler/IF
produce image frequency signals.
Amplifier assemblies.
2H-8 67XXB MM
2H YIG LOOP/FM
20-32.1 MHz
YLO ERR
67XXB MM
YIG LOOP/FM OVERALL BLOCK DIAGRAM
FM COIL
L._ _________ _:
PIO CONTROL
MODULATOR(S)
'------
TUNE
FROM A17PCB
(:t.SOMHz)
�'"""�I--- FM SWEEP
(< SOMHz)
FROM A17PCB
2H-9/2H-10
2H YIG LOOP/FM
FPFM
F( RONT PANEL)
RPFM
(REAR PANEL) FM
ATTN
DAC
U10
_____--+
---+--------,_:,.,
CONTROL
LATCH _ _ _ : :.r::/:J: : · B _YTE_
11 B YT E 2
.
.__ __
DATA DO· 7
1,: li : ug L HI RES ENBL
::::::::::::::::::::::::::::,:;:;::':::::::::::::::::i<:::::::::::
c
:ii\�
::::::::::
..
x F TTE L
l,,:·.•
,
}
:·=<
J\,,:,:::::::::::::::::::::::,:>:':':':':':'i'i':'i':':':':':':�
;:::::::::::::::::::::::::: :: :::: :::::::: ::::::::::::::::::::::::
.--- - - - :.: &::,: : ;:o <: : : : : : : :o : : : : :�: : : :3:: :�: : �::: : ;: :·:'i' : :'': :'i':':'i'':::::: :: : .:
..
D ATA
:: ::: :: : : 1mi�: :!:. LATCH . NT R L L 1 0 A N A
PAO '>--�----, LATCH L X10 ATTEN B
PA1 >--- A
-- DDRESS us
PA2 DECODER>--- - -- • LFMENBL ..._____
YUi
ERR*'>---r----1�1
FROMA12 PCB 50/100 200 KHz 14------'
NOTCH/FILTERS
FALSE
LOCK
DETECTOR
U27
YIG
* PHASE ERROR
67XXB MM
A16 FM PCB Overall B lock Diagram
--
I 1------>..., FM LEVEL
FM PEAK
�--------------------------- � DETECTOR
_ U28 TO A17 PCB
40dB
ATTN
U12,U13
FM
l---+-���11NTEGRATOR
U13-U17
_
._. __.�1 PHASE
MOD
CAL
: f@t:".___u_2_0_..
DAC
PHASE MOD
PEAK
DETECTOR
U30
1-------� PHASE
MOD LEVEL
TO A17 PCB
, Q i�j �
OVER MOD
CUTOFF
U30
I!!.! i: .1
TO A12 PCB
__
:1
:'-------+---� L HI
RESOLUTION
FM
SENSITIVITY
I CAL DAC
U20
A18-A21 PCBs
YIG DRIVERS
I
I
I
I
I
°'-.:n------'
2H-ll
20·32.1 MHz
20. 32.1 MHz =-2 dBm
(External Synth. (IF from A30
Input from Rear Sampler/
Panel BNC IF Amp)
1 P1 11
A12
YIG
PHASE
DETECTOR
2H-12 67XXB MM
�sv
ft.1
� L2
47
10
4 5
C.I:.
R� �.01 'Ve 2. PE I
NC 3 PE.l .J I
� LLK E.lLO. B NC
LajBIA5
. v c 4c.LK IHH ELLO. ' NC
"'" �MS
V£f ITL VE£ SP8(,,80
12 13
'128 �2 Pl
1.,,
XA
RES
I
L HJ EN
--f""<(--t r3'+--- ------..--�+-���
if? EXTERNl'\L R23 +5V
S.llK
HIGH R.£.SOLUTIDN IN. C17
12.
AMPLI Fl ER
RIS
RIG,
o.� /3
3 01
D +sv
Q(D
VNIOK
10
20-32.1 M H: QA
5
7'fALS
IF TEST 1-")kT OB �NC
;;o.:.-2rJBrn
· l2
c QC -;.c.
D QD I(.,
CLR
20-32. I Mill
LOAD
%-2dbr.-: '--���-l----<f---':...r\j
(IF FROM A30 2 U3
3AMPLEll/IF AMP) "'
�'� ' ._
G_N_D___, 74519�
MIH.. J
T
7 710
1 2.0-3.ZI
�·'
NOTES:
A12 YIG PHASE DETECTOR SCHEMATIC NOTES:
67XXB MM
5
10
+sv
Pl
A28 XAl2
+ sv
+sv
R30
90.'JK
C23 R'tS
�>r+-YLs'
MON
t +ISV
+ SV LP � IKR2
4
R2B R32
1�.C..K
R25 /DO
4.B7K 4.B7K
7 C20 4
NC
.¢ 3�0pf
...!.!:.�.(;i; )�YL
b 6
1
I
.St!J..
�'--_.-'V'V\,oj..._ ¢'ERR(-)
;l �
___
�)�YL
•SV
-+----+---e----<1---....
rx..---.-.�----�._-Vv"v-i.-----'\/V"..-- - .. --�
pf
C21
D
3
i 3
�SE
R40 R41
'22. G. K
UENCY
2'2.C..K
ECTOR
R39
R38 2.74 K
(2)
5. TROUBLESHOOTING VOLTAGE AND POWER
Figure 2H-4. Al2 YIG Phase Detector PCB
LEVELS INDICATED IN BOXES ARE TYPICAL Schematic Diagram (Sheet 1 of 1)
OR NOMINAL LEVELS.
6700-D-31712-3 (Rev. E)
6. STATIC SENSITIVE COMPONENTS USED IN
TMIS ASSEMBLY INCLUDE:
2H-13
TEST POINTS
TP1 GND G TP7 <!> MOD
TP2 FM TP8 Not Use1
TP3 FM ATTEN DAC OUT TP9 GND G
TP4 ATTEN FM TP10 FM S EN
TPS GND G TP11 FM DEV
TP6 FALSE LOCK DET OUT TP12 FM(+)
All test point measurem ents are made
with reference to GND G (T P1 or T P9).
�o
I 2 3 4
- ---@D-
�
U10
s::y:��:::1 � s:�s�::i
�::y:o:�:::1 I:y:o:%:::1 €:Y:��::1
W5
W6 (Front) 1 P1
II r-
49
W1
W2
W7 W3
wa (Back) 2 (To A28XA1 6) 50 W4
A16 FM PCB PARTS LOCATOR 2H YIG LOOP/FM
)
ied
;I
'\
:NS DACOUT
:v LIMITER OUT
'
A16
FM
2
-
1 Q�
a + -1:.IBill--
2H-14 67XXB MM
INPUT 8vFF£R. � FILT€1i..
R'i
F P t M IN PU T �3'-+<J-..._
Pl
')..--/\/\
+'l.'+V
CR.1
F0300
NE5532 /.q61(
/01(
ft5V<J)
o�LI� .cl /(//
s. 361<
CR2
a.
Ft;,300
-ISV<J)
FP FM SHIELD -'l.SIV Ne55.34
wz
!<!Ob
+'l.'IV /OK
:A'3
RP FM INPUT 1. '16k::
C3
C/' 4-
Nc5:532
5/1F /(10
10/C
51.I
RP JCM SHIELD
FD?OO
J
WI
�sv
I
I i
! I 11"' tSV
Yo b ;5
v«:.
PA 0 --l
<:-+---+-
/1 ) 1
YI C I'
i zo
2
A
� 8 ,5 �uh-_
>'..----4-�3�
p ,,.._ I
2· - J'3 L >-'1-"
c..
' 3__�
__J
PA c.._ > ' C z�
'
__
I
I
, i'
DO '
/ 21
DI
D 2. )3
D3 )+
D'I )5
DS >�
Db )7
07 ")8
I
:;
I
R73
J..5 vi)
t �·JVVv I
'
,,..1()
Rt9
51./
G -t4.t;V
Ci?9
+ISV@
A16 Al SCHEI
l/\/7SOA
- '''"V
- c;;, (�_ _
I
,
- l Ull.ES S IJ
RESISTAN<
CAPACITAI
INDUCTANI
2. SIGNAL Fl
8NO 4
.
:Z(�·.- 1
I
2P
RZI
- t;.+v
'·17SOA
CA.)10
R2Z
SI./
CONNECTI
SHEETS O
SHEET NI.I
DESTINATI
APPUI! I�
*Cl/
,_' -ISV@
3. GROUND!
�<)
/()
SCHEllATI
+
A ISOLAffi
A
4. TEST PQl)j
67XXBMM
5 6 7 8 9
".'( .S
+IS VC!)
CRS
:s FD300
RIZ
!<. 10 5
C[.2 100 CR6 W7
PD 300
< + IS VC!) --� I I /:.
R /11 W5 2.
- /5 V(J)
z
CR7
F0300
I 1 1< 6 F/1
.3
" CR 6 WB F l1
F!l 3 0 0
!,U6
-!SVC!) -/S V@
8
�
S"V(J)
AT T E. N O A C I N STRB
AT T E. N 0 /'. C. O U T STR.B
FM .S EN S O�C. S T R B
r S VC!)
20
� L FM EN
JO O 3 ,'-" H l=" M E. N
DO
t.
Io/ 0/ QI
DO
IM. D7 QZ
ID /)3 ()J L .S � E E P E.N
I/)11. bV
ros
jH
G I/
1.3 Y L EN
Q"
QS
ID 7 D? Q?
U7 L YL EN
L FA ST L O O P E N
EN
C.Alt>
l. X I O l<\T T E N f"I
20 74 HC 3 7 4- l X I D A T T �N B
I D O - "I.D 7
Qo
1) 1 5
z
�
· «.
oz h L H I G H R E. <; E N
<?z����������������������������� Ff"IST � L /C L E N
0:3 r1�
04
Pl
05 15
(t(, /{, L D A C 1>. / D A C. B
01rl'-'-���-�
��� ����--J B Y T E 1 / L B Y T' E. 2.
J9 7'1HC 3 74
"
f + 1 5 VF/1
)
r/S V@
- 15 V@
/ j.) � T7F/V A
-t /S i./FM
R23
. . 8 7<:
�
F M
CR/I
Ci
lu 7a9 'J' ?SIA
/6
I DO -IC7 82
-1s v@ i!S"V@ 1>
// D f, Z O I
RF8
+ iS V <iJ
B� �le
4
85
19
zo
87
86
18 b 8 )!Tl
13
6 15
17
;:J I
S9
15
16 3 a
I
Durz
B "r T E 1 / L. B Y T l l'..
1-;s s
I
Z3 3
A U,
A T T E_ N 0 1\ C. i N S H . 5
3�
2 -1s v® 3
') I 0
'..).-
/\ T T >_ N D A C O ' J T '.:.T R I'..
I
,DAC / 206
cs
H YL EN
__,' / 4-
___8--;,
�· � ()--"9__�
, /J TE G R lf TO R.
22B
80. 6 /::
316 , {) /
H
. 01
/{3 7
Ctr;.
? 2/K 2 , 2. 6 /C
I B.
+IS J @ � + I S V@
C23
- 5 V @ � - I S Vr�
"'=-'
V2{)A
+ i 5 ' l\ C 752B
? rB 1----<l>--'--t
F t,!,
t- 1 � IJ_., LF3�
� /0
- 1 5 \ FM
�4C/
�
-, :.:- / (i;
·��
- C/9
10
5l.;
-I �l(f!_
5 6 7 8 9
q 8
b t. 2 0 1
U / 2.
I>
7 b
fl TTE/\/ ,"'/vi
- 15 11@
II
U/ 4-
b& 2.1) D
R.3 8
R4Z.
25. 7 t:
1?3'! Cl 7
czo R4/
¢ /'40i)
RZ'!
L F357
7. 5 1!
3 5 !0
2H-16 67XXB MM
0 1 2 3 4
IDO - I D 7
L Mc A ID A C B
FM /JAC. ST� B ----
A SENS
A /TEN FM �� I 7b
Z / "::.
IS
o
f-o.L.'.!.-
L. fltf EN'
L S#l£EP £>/
... ::;. ....
-ISV©
P i
4(,,
I
sw..... .li!E.F
B
,;.. s ....-p c
4 "
L Y l [. N [=:2£>
U/8
�����������������__£..
B -
c H YL EN �--���-:-:;;
n '!
e{?>-
1" * 5 0 '( ,.. £ ;/ ) -c r/- I
I
... *
I
z .) I
II
10:_,-
{, ....--....:
r�
;;.· . .s !/.<:
�
.. lf-
D CS"f :·:;5
IZt»J" F' ILdo,F
R 74-
I!<
7
/. 3: � r� i
�
C$'G
f�
R ?Z.
f. C� K � O. C
E 12"1!J� ��
---- ·--- -------· -··
q
--------·--t----+- -----------
P l
I /' 5 1
43
F I
I
4+
44. 1k
67XXB MM
5 6 7 8 9
-f lS V FM
,Q.50
3. 0�K
UIB
10
C-'< 1 9
201
C'-'1
;,,.; 75 : A
•
i
:) C::, 4- /7
U18 c. VR A v<L.
LSB
� + !S LI@ 3
8 1 RF-.
83 U 2 0 E
;
� BZ.
10
R 56 ,J
B5
5 <1
l 'if. c?.K i
q J '"A
86 "
7
A/a
"1513
"
C/221
F.0300 3 J . /k.
R6B
·2
Ct<ZZ FM
UIB
Xc> ZD/ 5E,;S ! Tl V ! T V Ll 4 C
,;;
D?Z3
/('6 5
F630o
CRZ4
F63 0o R 7!
I
!?FF
3. 83 1<
�
FM
- IS" V@ I
4
YL TUNE M ON
. C34
· O. i
SI!
€115
x ! IO CS/
C <; b C 4' 7
- 15" V@)
825
; zoo? �
2001, � l'/6'55 3 2
!ZO D p F
"
7
l/32
....,_�+ R/17
B
"" J
s
W *B
66 5
/< I I I
/ZOO_, .: 120JP':
4. Z Z /C
IZ�o?f'" IZOOp ;:
2H-17
Ff/,
IOI:.
F tV\ · l / "f
, ' t<'Z'1
111 - � .... �
( J 3 ')
/)/4".JIJb
/LO 74
7l07 '1
• "..' C:3 4-
*
'
.:1n•u ;;
CR3 �
/0
------�'-"-
WJ � ,
Tl. {) 74
()bt.OO -IS/I@
UZ ? .;
h Ftfl E H
+ 1 5 VFM
/(/61 IO'o:Z.
�/. ( !"/./
_b: J
{.+ 1s v, .:;. +- 1 5 11@
C + t:llo
G /6
i '
$ /�
�'""
</. (
5 6 7 8 9
� �€ r: �.J :::
c38
F, Oo
� , s v0
c<
CR33
P</O
/Ok
I
f:c 89
pl
I�
F/*1
-a
TL07 4- B
' '
3_'
!-(orJ
<
TL 0 74-
-1s v0
/tf0/11
_ '(' q z
, ,<
rl
() /E R .M OU C U T() i= !C
C,Ri: CJ
eR3 8
.'l) t.j..J ./- '
+1s v ® 1,;1N<J6
I�
A
7L074-
I
- 1s v@
1"' / q1; ,c
- S V@
- / 5 t/(j)
P i
I
41 I> ,.,,t>
I
� l'tfll> /Utr
2H-18 67XXB MM
2H YIG LOOP/FM
LO IN
J2 220 - 240 M Hz Comb
( From A31 J2)
�
:-:::::- 1
,- - - - - l- - L
I
- - - - .,
I I
I I
1 Samp ler 1- -W RF IN 20-:
1
1 Microcir cuit
Assembly*
1
t-
1 \_\ \_ I J 1 20-26.5 GHz
,., -1 7 dBm ( I F 01
I I
I I
(O utput o
,_ - - - - - - - - - - .J
O+
Cl4
67XXB MM
A30 SA MPL ER/IF AMPLIFIER PCB PARTS LOCATOR
A30
SAMPLER /
I F AMP
32. 1 MHz
... -2 dBm
ut to A1 2J4)
on opposite side)
JS
2H-19
J1
440 - 490 MHz
::= -3 dBm
(CL VTO from A4J1 )
A31
POWER AMP I
MULTIPLIER
2H-20 67XXB MM
0 1 2 3 4
J/
+ /SI/I
+ /11- V
+ I S I/
o
T/en
s
67XXB MM
I 6 6 1 8 9
'f'KE4MP
A30 SAMPlERllF AMPLIFIER SCHEMATIC NOTES:
CHASSIS GROUND: m
ISOLATED GROUND: \]
3. LAST USED/NOT USED COMPONENTS ARE:
c111-
�10 eB
JD
Cl/
REFERENCE DESIGNATORS
,6 /iJ
.. + .j.
'S
LAST USED NOT USED
RU
� ·�
C36 NONE
7.SK
CR4
JS
C.'1 z CIS L5
P1
¢ RIZ
8t!:
RVI
IK
IUZ RZB
�o, !<" l'l6 2/. 5
J'f.6
_,../!: VI r /J; VJ + 15 Vf - OS V/
+
� to C:Z"t
1?44
+
JO
CiJ4
QB
7. 5/C
�
QIO
Z.t\15 17'1 rtJs11.,
Clf.3
JS
2H-21
1.1
Z l'7
,;::::. �
11---i
:n
0- 1
..
))1---i===� .......-�9\
L- 1 TL I
q�r-P'_t_-=-
MHr · "? " � f"t
C L 'FT"C
Cb
¢ d l3rn
4 4 C - 4 'i C
=
FRO M A4 J I
.C..4
IOOO f"'\'.
12" 1
,::.. z
�8 1 0 . 1 p-1'
NOTES:
3.
REFERENCE DESIGNATORS
- DENOTES PRIMAR Y SIG�JAL PATH.
LAST USED HOT USED
TL DENOTES TRANSMISSION L I NE.
C26 NOHE
J2
03
R17
U1
VR1
H
L a I 6 7 8 9
POWER AM P
PR E - A M P
,.,,_ �
l " Z ''
n.7
.76'"
71!>7 10
L.. �
10
+ 1 ..;.v
2H-22 67XXB MM
21-ANALOG INSTRUCTION: A17 PCB 21-2 ANALOG INSTRUCTION ASSEI\ffiLY,
OVERALL DESCRIPTION
t
Table Analog Instruction Service Information
.S��:V;��
Analog Instruction PCB are as follows:
OVERALL ASSEMBLY LEVEL
• Microprocessor Bus Interface and Internal
Data Bus - Separate control lines and an inter
67 XXB MM 2I-l
A17 ANALOG INSTRUCT/ON, DETAILED DESCRIPTION 21 ANALOG INSTRUCT/ON
(4) Interfaces between the A23 Microprocessor The DVM and MUX control latch, Ul , controls the
PCB and various analog circuits. analog multiplexers U7, U9, and Ul3 and the DVM's
analog-to-digital converter (A DC), U3. The power
• Power Meter- U sed with a WILTRON 560 series
meter control latch, U40, is an S-bit, edge-triggered
detector (or equivalent), allows measurement of
latch with the outputs enabled at all times by the
an external RF source-or of the RF output of the
ground at pin 1 . The outputs change only on the
synthesizer.
low-to-high transition of the strobe applied to pin 11 .
The YIG driver select latch, U16, selects the YIG
21·3 Al 7 ANALOG INSTRUCTION, tuned oscillator to which the frequency instruction's
DETAILED CffiCUIT DESCRIPTION voltages are to be applied. This latch also supplies
Refer to the Al 7 PCB block diagram (Figure 21-3) two signals to the YIG Driver PCBs; L RF OFF,
and the Al 7 PCB schematic diagram (Figure 21-5) which turns off the YIG-tuned osc illator and
during the following discussion. CW FILTER, which switches a filter capacitor
across the YIG-tuned oscillator's main tuning coil for
CW operation and narrow band sweeps. In addition,
21-3.1 Microprocessor Bus Interface and U16 provides the range select signals for the DVM
Internal Data Bus circuit.
U3. The A23 Microprocessor PCB's address bus the outputs follow the inputs. The internal data bus
PAO-PA2, and dedicated address lines, LPA 15 an d IDO-ID7, provides isolation of the A23 Microproces�
LPA 19, are connected directly to address decoders, sor PCB's data bus, DO-D7, from the sensitive DACs
in the ramp generator and frequency instruction cir
Ul4 and Ul7.
cuits. The internal data bus is connected to S-bit
latches US and U11 and DACs U18, U24, U34, U3S,
The 3-to-S decoders, Ul4 and Ul 7, decode the PAO
PA2 address information. The LPA 15 signal enables and U42.
1 0 ms, Ul and U16 may then be written to by the latches are referenced to T ground and receive their
+5V power from the R57, C30, and Zener diode CR11
A23 Microprocessor PCB. This prevents the YIG
supply circuit. This further isolates the ramp gener
Driver select lines from going to a low state and
ator and frequency instruction circuits from the A23
turning on all the YIG-tuned oscillators at the same
Microprocessor PCB data bus and the 5V digital
time during power on. It also disables U3, the
power supply.
analog-to-digital converter, from accessing the A23
Microprocessor PCB data bus at the critical power
on condition.
21-2 67XXB MM
21 ANALOG INSTRUCTION A 17 ANALOG INSTRUCTION, DETAILED DESCRIPTION
21-3.2 Ramp Generator R22. This prevents the output of U19B from going
to the supply rails when not being used.
The Ramp Generator circuit consists of the Sweep
Time DAC, the Ramp Integrator, the Marker-Switch
The sweep ramp output of the Ramp Integrator goes
Point DAC, the Marker-Switch Point Comparator,
to U26, pin 2 as an input to the Marker-Switch Point
the Ramp Control Logic circuitry, and part of the
Comparator. It is also buffered and amplified by
Ramp Control Latch. The circuits, shown on sheet 2
U21, then applied to the Frequency Instruction cir
of the schematic set, are described in the following
cuits as a-lOV to +lOV t.F sweep ramp. In addition,
subgroups:
it is buffered and inverted by U22, then sent as a OV
• Ramp Integrator to + lOV ramp to the rear panel HORIZ OUTPUT
BNC connector via the A29 Rear Panel Interface
• Marker-Switch Point DAC
PCB.
• Marker-Switch Point Comparator
b. Marker-Switch Point DAC
• Ramp Control Logic
�
switch (U20), and their associated components. The
multiband units), or the top or bottom of the sweep
DAC U18 receives digital sweep time information
ramp. It outputs a voltage representing this infor
and utputs a voltage representing this sweep time
mation via U19A. The amplifier, U25, has a resistor,
via U19A. The range of the output voltage is OV to
R32, in its feedback path that calibrates its output
+lOV. A typical U19A output at a 30 ms sweep speed
to be within typically 3 mV at full scale. The U25
is approximately +SV. At a sweep speed of 999 ms,
output, which has a range of OV to -lOV, goes to the
this voltage approaches OV. When applied through a
Marker-Switch Point Comparator inputs, U26 pin 3
resistor, this voltage determines the charge rate of
and U27 pin 3.
the integrator capacitor.
c. Marker-Switch Point Comparator
The output of U19A goes to pin 3 of analog switch
U20A. This switch is closed for a forward ramp and
The Marker-Switch Point Comparator, in conjunc
open during a retrace or dwell. From pin 2 of U20A,
tion with the Marker-Switch Point DAC, provides a
the voltage is applied to the input of U19B thr01.�gh
logic signal to the Ramp Control Logic which starts
either R20 or R20 in series with R21, depending
the dwell. Dwell occurs at the top and bottom of the
upon the front panel sweep time setting. R21 is in
ramp, at each bandswitch point ( for multiband
�
series with R20 for sweep speed ranges of from
units), and at each selected marker.
greater than 1 second to 99 seconds. At sweep
speeds less than or equal to 1 seco�d, R21 is sho ed
The Marker-Switch Point Comparator consists of an
out by pins 10 and 11 of analog switch U20C. Dunng operational amplifier (U26), a voltage comparator
retrace of the ramp, a current through R19 and pins
(U27), and their associated components. The
6 and 7 of U20B from -lOV is summed in at the
amplifer, U26, provides precise comparison between
junction of R20 and R21. The A23 Microprocess?r
the OV to -lOV ramp output from the Ramp In
PCB, in conjunction with the Ramp Control Logic,
tegrator and the voltage from the Marker-Switch
determines the closing of U20B for the retrace-to
Point DAC. The swing of U26's output voltage from
discharge time. From the junction of R21 and pin 10
its pin 3 input voltage is limited to from +0.6V to
of U20C, the U19A output voltage/R19 current goes
-0.6V by CR4 and CR5. The output of U26 goes to
to the input of U19B. The U19B output charges the U27 pin 2 where it is compared with the voltage
.
integrator capacitor C14. Since U19B has a typical from the Marker-Switch Point DAC at U27 pin 3. As
.
gain of 200,000, this produces a very lmear ramp. the voltage input at U27 pin 2 becomes more posi
tive than the voltage at U27 pin 3, the output of U27
When the Ramp Generator is not being used, switch
is pulled to a TTL high by RNl. This logic signal goes
U20D pins 14 and 15 are closed, shunting C14 with
to the Ramp Control Logic to start the dwell.
67XXB MM 2I-3
A 17 ANALOG INSTRUCTION, DETAILED DESCRIPTION 21 ANALOG INSTRUCTION
d. Ramp Control Logic At the end of the dwell, the A23 Microprocessor PCB
sets the Marker-Switch Point DAC to the value for
The Ramp Control Logic circuitry determines when the next dwell. This value depends on the syn
the ramp is in the sweep, retrace, or dwell mode. The thesizer model, sweep width, and marker settings.
circuitry consists of a hex inverter (U4), quad NAND The CLR DWELL STRB is then applied to U5
gates (U5 and U23), a quad exclusive-OR gate (U6), pin 12, changing the state of flip-flop U5. Since the
and associated components. The signal from U27 or RETRACE signal at U4 pin 9 is low, the U5 output
L SWP DWELL from the rear panel BNC connector is routed via U23A, U4C, and U23B to the analog
determines the start of each dwell. All other control switch, U20A. The switch closes and the ramp starts
signals and timing are determined by the A23 toward-lOV. At this time, the L DWELL EN signal
Microprocessor PCB. L DWELL EN enables the is also set low to enable the next dwell from com
dwell signal from U27, CLR DWELL STRB ter parator, U27. When the ramp reaches the next
minates the dwell, and RETRACE determines if the dwell, the events of the dwell just described repeat.
ramp is sweeping or retracing.
If the next dwell is a bandswitch dwell, the A23
The following is a description of the ramp control Microprocessor PCB locks the YIG-tuned oscillator
logic and the A23 Microprocessor PCB actions that was sweeping and determines the error, if any.
during a sweep ramp cy cle. It then turns it off. After so doing, it:
• Turns on the next YIG-tuned oscillator.
During retrace (ramp discharge), the output of U27
is at a TTL high, RETRACE is high, L DWELL EN • Phase-locks it, and determines the frequency
is low, and the Marker-Switch Point DAC output is error, if any.
set to OV. As the ramp reaches OV, the output at U27
• Sets the Marker-Switch Point DAC for the next
switches to a TTL low. This transition causes the
dwell point.
outputs at U6 pin 8 and U5 pin 11 to go low. The
output of U5 is inverted by U4E and sent to the A23 • Clears the dwell and sends the ramp toward -lOV.
Mic roprocessor PCB as the interrupt signal,
DWELL INT. The output of U5 also goes to U23 If the next dwell is for a frequency marker within
pin 2. From U23 pin 3 it is inverted by U4C and the sweep range, the YIG-tuned oscillator's frequen
applied to U23 pin 4 and U23 pin 9. Since cy is not phase-locked as at other dwell points. If the
RETRACE is true, there is no change in the output VIDEO marker is selected, there is a 5V pulse from
at U23 pin 6 (switch U20A remains open), but the the A29 Rear Panel Interface PCB applied to the
output at U23 pin 8, which was low, is now high. rear panel MARKER OUTPUT BNC connector.
This opens analog switch U20B, supplying in
tegrator current for the retrace. The output of the During the top-of-the-ramp dwell prior to retrace
integrator is now at OV and remains there for the (ramp discharge), the ramp holds at -lOV for ap
duration of the bottom-of-the-ramp dwell. proximately 20 ms. The A23 Microprocessor PCB
phase-locks the RF signal, determines the frequency
The following is a description of the events during a error, and stores this error-value for later use. When
dwell. Approximately 100 µs after the dwell starts, this is accomplished, the A23 Microprocessor:
the A23 Microprocessor PCB acknowledges the dwell • Turns off the YIG-tuned oscillator.
interrupt by setting L DWELL EN high. Since U6 is
an exclusive-OR gate with open-collector outputs, • Sets the blanking and sequential sync signals on
the high L DWELL EN signal causes U6 pin 6 to go the A29 Rear Panel Interface PCB.
low (the condition that it was in prior to dwell start).
• Turns off the A15 ALC PCB.
During the approximately 20 ms of the dwell, the
A23 Microprocessor PCB phase-locks the RF at the
At the end of the top of the ramp dwell, the A23
new frequency and adds any correction value that
Microprocessor PCB sets the Marker-Switch Point
was calculated during retrace. It then turns the RF
DAC to OV ( the value of the next dwell) and sends a
on via the A15 ALC PCB and changes the state of
CLR DWELL STRB to U5 pin 12. This changes the
the blanking and sequential sync signals on the A29
state of flip-flop U5. Since the RETRACE signal to
Rear Panel Interface PCB.
U4 pin 9 is high, the output of U5 is routed via
U23A, U4C, and U23C to the analog switch, U20B.
21-4 67XXB MM
21 ANALOG INSTRUCTION A 17 ANALOG INSTRUCTION, DETAILED DESCRIPTION
The switch closes and the ramp starts toward OV • Analog Sweep Correction
(retrace). The L DWELL EN signal is also set low to
enable the next dwell from comparator, U27. During • Linearizer DAC
the ramp discharge (retrace) of approximately 30
ms, the A23 Microprocessor PCB calculates the er a. TuneDAC
rors for the correction of the frequency on the next
setup and prepares the phase-lock loops to lock at TheTune DAC circuit consists of a 16-bit DAC (U34),
the bottom of the sweep. an operational amplifier (U35), and their associated
components. The DAC, U34, receives digital tuning
information from the A23 Microprocessor and out
21-3.3 ±lOV Reference Supplies
puts a tuning voltage via U35. The DAC reference
Refer to sheet 2 of the schematic set during the voltage input, at pin 13, is supplied with either the
following discussion. There are four reference volt +lOV REF T or -lOV REF T supply through the
age supplies on the Al 7 PCB: analog switches, U33A and U33B, and the isolation
amplifier, U53. The output voltage from U35 is in
• +lOV REF T
verted from this input reference voltage.
• -lOV REF T
In CW mode, switch U33A is closed. Therefore, the
• +lOV REF 2
output of U35 is in the range of O to +lOV. This
• -lOV REF 2 output goes to the input of amplifier U37 via switch
U41B and resistor R51. This is a unity gain invert
The ±lOV REF T supplies provide the reference vol ing path, so the output of U37 goes from O to -lOV.
tages for the ramp generator and frequency instruc The analog switches, U41B and U33C, provide
tion circuits. They also supply +lOV REF T reference temperature drift compensation. The output of U37
voltage to the A18-A21 YIG Driver PCBs and a is the analog tuning voltage that is applied to the
+lOV REF reference voltage to the A29 Rear Panel YIG Driver PCBs. To allow for circuit tolerances, the
Interface PCB. The ±lOV REF 2 supplies produce actual voltage applied to the YIG Driver PCBs is
reference voltages for the DVM and the power meter approximately -lV at the low end and -9V at the
circuits. high end of the YIG-tuned oscillator's tuning range.
This -lV to -9V may vary as much as 10%, depend
Voltage regulator U30 is a precision lOV regulator ing on the YIG-tuned oscillator and its driver. How
used as a reference for U31. The amplifier, U31A, ever, a particular YIG driver/YIG-tuned oscillator for
buffers and filters the precision regulator output for a frequency band will be the same whether it is used
the lOV REF T reference voltage supply. The in a single- or multiple-band synthesizer.
amplifier, U31B, inverts the +lOV and filters it for
the -lOV REF T reference voltage supply. In the broadband sweep modes, it is necessary for
the DAC, U34, to offset a very high �F ramp voltage.
The ±lOV REF 2 reference voltage supplies, consist At this time, switch U41A closes and puts R52 in
ing of the U28 and U29 circuits, operate in an iden parallel with R51. This results in a gain of four for
tical manner to the ±lOV REF T reference voltage amplifier U37.
supplies.
The actual tuning voltages for each YIG Driver PCB
are stored as a DAC word in the synthesizer 's non
21-3.4 Frequency Instruction volatile memory at the time of frequency calibration.
The Frequency Instruction circuit provides the These calibration voltages are used in all of the A23
analog tuning voltages for the A18-A21 YIG Driver Microprocessor PCB calculations for analog sweep,
PCBs in both the CW and sweep modes. The Fre stepped sweep, and CW frequencies.
quency Instruction circuit consists of the Tune DAC,
Sweep Width DAC, and Linearizer DAC circuitry. b. Sweep Width DAC
The circuits, shown on sheet 3 of the schematic set,
are described in the following subgroups: The Sweep Width DAC circuit consists of a 16-bit
DAC (U38), an operational amplifier (U39), and
• Tune DAC
their associated components. The DAC U38 receives
• Sweep Width DAC digital sweep width information from the A23
67XXB MM 2I-5
A 17 ANALOG INSTRUCTION, DETAILED DESCRIPTION 21 ANALOG INSTRUCTION
Microprocessor PCB and outputs a �F ramp voltage When broadband analog sweeps are selected-such
via U39. The DAC reference input, at pin 13, is a as 2 to 20 GHz-the slope of the �F ramp is insuffi
-lOV-to-+lOV �F ramp from the Ramp Generator cient to cover the frequency range of each of the
circuit. The output �F ramp voltage from U39 is YIG-tuned oscillators. In this case, the gain of the
inverted from this input reference voltage. It goes to summing amplifier, U37, is switched to provide a
analog switch U36A. Switch U36A provides a gain gain of four for both the �F ramp voltage and the
of one while U36A together with switch U36B pro Tune DAC voltage. This allows the Sweep Width
vide a gain of four. This �F ramp voltage is then DAC to still attenuate the �F ramp from the Ramp
summed with the Tune DAC output voltage by the Generator circuit.
summing amplifier U37.
Figure 21-1 shows the relationship of the �F ramp,
When sweeping a single YIG-tuned oscillator, the Sweep Width DAC attenuation settings, and Tune
Sweep Width DAC attenuates the 20V peak-to-peak DAC voltage required for a typical broadband sweep.
ramp down to the 8V peak-to-peak swing required
for the YIG driver. Since this attenuated ramp goes The �F ramp from U39 is also applied to connector
from -4V to +4V, the Tune DAC sums a -5V offset Al 7Pl pin 63 which goes to the A16 FM PCB.
with the attenuated �F ramp, providing the neces During narrow band analog sweeps (sweep widths of
sary -lV to -9V tuning range for the YIG-tuned �50 MHz), the ramp is applied to the FM coil of the
oscillator. YIG-tuned oscillator instead of to the main tuning
coil. Under this condition, both analog switches,
1
20 GHz
I
12.4 GHz
I
·6.200V
-10.000V
I
l
DELTA-F RAMP INTO
_::'.J
SWEEP WIDTH DAC
-2.400V
-10.000
1.091V I 2.s32v l
DELTA·F RAMP OUT OF
lo.632V
SWEEP WIDTH DAC
3
SUMMNG AMP GAIN
4
FOR TUNE DAC
(0.6 2 X 4) -1.528 • -1.000V
OUTPUT TO
r--r.
3
VIG DRIVERS
!-4.384V I (0.667 X 4) · (2.917 X 4). -9.000V (1.091 X 4) + 4.6 6 . -9.000V (2.632 X 4) - 1.528 • -9.000V
7.460- (2.961 x 4)
5.968 -(2.961 X 4 ) • -5.876V
NOTES: 1. The tuning voltages, -1V & -9V, are typical tuning voltages for the yigs and will vary from one yig to another.
2. The voltages given are rounded ott to the nearest milllivolt.
3. The above figure is for a typical 6747A. Other models will vary as far as switchpoint voltages and dac settings.
4. These voltages and gain settings will also depend on the sweep width and center frequency settings.
21-6 67XXB MM
21 ANALOG INSTRUCT/ON A 17 ANALOG INSTRUCTION, DETAILED DESCRIPTION
67XXB MM 21-7
A 17 ANALOG INSTRUCTION, DETAILED DESCRIPTION 21 ANALOG INSTRUCTION
Reference Loop Measures the phase lock condition of the reference loop from A7.
Coarse Loop Measures the phase lock condition of the coarse loop from AS.
Fine Loop Measures the phase lock condition of the fine loop from A11.
Knob Measures the de voltage from the A2 PCB DECREASE/INCREASE knob cir-
cuit. (The control in located on the front panel. )
YIG Loop Measures the phase lock condition of the YIG loop from A 12.
PS1 Monitors the status of the regulated power supplies on the A22 Regulator
PS2 PCB.
Fine Loop Tune Measures the tuning voltage of the fine loop oscillator from A9.
Coarse Loop Tune Measures the tuning voltage of the coarse loop oscillator from A4.
Reference Loop Measures the tuning voltage of the reference loop oscillator from A5.
Tune
YIG Loop Tune Measures the YIG loop phase lock error from A 12. Used in Analog Sweep
mode.
Power Meter Measures the output of the A17 PCB's power meter circuit (Series 560
detector ) for display on the front panel LEVEL display.
Detector Thermistor Measures the thermistor voltage of the power meter head (Series 560 detec-
tor ) for temperature compensation.
Power Meter Offset Measures the calibration offset voltage of the power meter head (Series 560
detector ).
+10V T Measures the A17 PCB's reference voltage for self test purposes.
Tune Measures the A 17 PC B's Tune DAC output that goes to the YIG drivers.
Down Converter Measures the phase lock condition of the oscillator loop from the Down Con-
Loop verter.
FM Measures the FM deviation from A16 for display on the front panel
MODULATION/TIME display.
21-8 67XXB MM
21 ANALOG INSTRUCTION A 17 ANALOG INSTRUCTION, DETAILED DESCRIPTION
DAC changes at each bandswitch point. This auto or make conversion data available to the A23
matically compensates for the YIG-tuned oscillator Microprocessor PCB (read). The control signal, CE,
linearity in both the CW and sweep modes. enables U3 operation for the requested convert or
read operation. The control signal, AO, determines
if an 8-bit or 12-bit conversion is to be made. To
21·3.5 Digital Voltmeter (DVM)
improve accuracy, +lOV REF 2 is applied to REFl
The DV M circuit consists of a 12-bit analog-to-digital (U3 pin 10) rather than using the internal reference
converter (ADC), a 24-channel analog multiplexer of the ADC itself. This voltage is also applied to B/P
(MUX), and a sample/hold network. It has a +lOV to OFF (U3 pin 12) to allow the DV M to have a full
-lOV basic range and two auto ranges of ±20V and scale operating range of +lOV to -lOV.
±lOOV.
Switch U15 provides an additional two ranges for
As shown on sheet 1 of the schematic set, the various the DVM. When switch U15A is closed, the range of
analog inputs to the DVM are applied through the the DV M is +20V to -20V for all inputs except U13
8-to-1 multiplexers U7, U9, and U13. The A23 pin 4, which is +lOOV to -lOOV. When switches
Microprocessor addresses these MUXs via the DVM U15A and U15B are both closed, the range of the
and MUX control latch, Ul, to select which channel DV M is +lOOV to -lOOV.
is to be measured. Table 21-2 lists the DVM input
channels and their basic functions. The U13 pin 4 input is tied to TP2 through R15. This
provides an internal DV M for general test and
The output voltage from the selected MUX channel troubleshooting purposes. It has a range of +lOOV to
goes to the input of UlO, the sample and hold in -lOOV and is auto-ranging for maximum resolution.
tegrated circuit. Whenever an analog-to-digital con
version is not taking place, the analog signal input
21-3.6 Power Meter
to UlO charges CB and is output via UlO pin 5 as
the analog input to U3, the analog-to-digital con The power meter circuit, shown on sheet 4 of the
verter. During the convert mode (analog-to-digital schematic set, consists of a chopper amplifier, a
conversion) of U3, the STS line (U3 pin 28) goes programmable gain amplifier, a synchronous detec
high, is inverted by U4B, and is applied to UlO pin tor, and buffer amplifiers for temperature compen
8. This places UlO in the HOLD mode so that the sation and offset calibration of the detector head.
input to U3 will be stable during its conversion, even The chopper/synchronous detector system mini
though the input to UlO may be changing. mizes de offset and drift errors at low signal levels.
The front panel LEVEL display, which is the in
U3 is an analog-to-digital converter (ADC) connected dicator for the power meter, is enabled when the EXT
directly to the A23 Microprocessor bus. It has a built PWR MTR key is pressed. If there is no detector
in DAC that is compared with the input analog sig physically connected to the rear panel, or if there is
nal at pin 14. Using a successive approximation al no RF power applied to the detector, the display
gorithum in its built-in microprocessor, it adjusts the indicates LLL.
DAC until its output equals the analog input. It then
creates the digital word to be read by the A23 a. Input Chopper Amplifier
Microprocessor PCB. The A23 Microprocessor PCB
accesses the DVM at least once every 50 ms as a PWR HEAD DET, the de voltage from the detector,
function of its housekeeping routines. Additionally, is input to the power meter circuit at A17Pl pin 67.
when certain operations are in progress - such as It goes to the inputs of U47 via the contacts of the
during phase-locking - the microprocessor accesses quad-analog switch, U46 . When L SAMPLE 1 is
the DV M more frequently. true, the detector voltage is applied to U 47 pin 5 and
when L SAMPLE 2 is true, it is applied to U47 pin 3.
The operation of U3 ADC is controlled by the control The outputs of U47 are sent to the inputs of U48.
signals AO (U3 pin 4), R/C (U3 pin 5), and CE (U3 The amplifiers, U47 and U48A, are arranged as an
pin 6). AO and RIC are set by the A23 Microprocessor instrumentation amplifier. The amplifier, U48A, fol
PCB via latch Ul; CE is set by U14 which is also lows the input from U47B and inverts the input from
controlled by the A23 Microprocessor PCB. The con "G47A, resulting in a square wave output at U48A
trol signal R/C determines if U3 is to do a conversion pin 7. This chopping is done at a 10 Hz rate, control-
67XXB MM 21-9
A17 ANALOG INSTRUCTION,TROUBLESHOOTING 21 ANALOG INSTRUCTION
led b y the A23 Microprocessor PCB during during calibration of the detector head itself. The
housekeeping. output of U45C changes with the calibration resistor
value. This voltage change, V dBm, is sent to the
b. Programmable Gain Amplifier Al 7 PCB's DVM through U13 and is read by the A23
Microprocessor PCB. It is used so that, for a given
The programmable gain amplifier consists of power, the front panel LEVEL display is the same for
amplifiers U48B and U51A, each with a gain of from any compatible detector head.
1 to 100. The resultant overall gain of the program
mable gain amplifier ranges from 10,000, at low 21-4 ANALOG INSTRUCTION ASSEMBLY,
detector input signal levels, to 1 at high input signal TROUBLESHOOTING
levels. The A23 Microprocessor PCB uses the range
select analog switches to set the overall gain of the Refer to the troubleshooting information in the front
amplifier. The 10 Hz square wave output from U48A portion of Section 2-System Description and
is applied to U48B and amplified. It is then ac Troubleshooting. This information provides a list of
coupled to U51A, where it is again amplified and ac error codes that may be displayed as a result of
coupled out to the U50A and U50B analog switches. failures in the analog instruction subsystem and
probable causes of the failures.
c. Synchronous Detector
21-5 ANALOG INSTRUCTION ASSEMBLY,
The synchronous detector converts the amplified SERVICE SHEETS
10 Hz square wave back to a de voltage appropriate
Table 2I-l, on the first page of this section, presents
for the Al7 PCB's DVM circuit. When L SAMPLE 1
the arrangements of the block diagram, schematics,
is true, the amplified detector voltage is negative
and parts locater diagram for the Al7 Analog In
and is routed through U51B to the inverting input
struction PCB.
of U52B. When L SAMPLE 2 is true, the amplified
detector voltage is positive and is routed through
U52A to the non-inverting input of U52B. In both
cases, V DET, the output of U52B, is positive. V DET
is applied to the Al 7 PCB's DVM through analog
multiplexer U13. The A23 Microprocessor PCB
reads the detector output from the DVM and con
verts it to a logarithmic ( dB) scale for output to the
front panel LEVEL display.
2I-10 67XXB MM
21 ANALOG INSTRUCT/ON
00-7
PAO:'.:;
PA1; .
. .___
· · 1 !· · · ,: ·.
,,,,:,:,:,:,:,:,:,:,:,:,:i:::::::,..,
ADDRESS INTERNAL DAC
PA2:::- � DATA BUS LSB ;:;:;:;�:;:::;;
;;:;:�;:;:x:x@ :::;:�:::�:::<:;:,:;s::-�,�:::-� �';ix::i;S!'.ss�
.
DECODER
LPA15:;:- LAT CH LAT CH
.
LPA19; .. '-- - - _ __ ......1
__ _ _ _ _ .....,.
�
DVM
AND MUX
CONTROL
LATCH
l:o::::=::::::::::::::::
I
!:i:\:;:;:;:;:;:;@;:;:m;:;::<�:=:=:�;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:::;:;:;�:::=:�"�';:;�:::::;:i;:;:;:::;:;:;:;:;:;:;:;:;s;:;:�;:;:;:;:::::;�:�';s;��"''�
PS2::. ..
POWER METER
DETECTOR OFFSET :::->---lrM CONTROL LATCH
-rl l I I I I
LOWELL ;>------
67XXBMM
A17 ANALOG INSTRUCTION PCB BLOCK DIAGRAM
',
+/-10V
REFERENCE LBAND2
-10VT +10VT
! '
YIG
LBAND3
DRIVER
.....
SELECT
�
-----
LBAND4
LATCH
�
�
.....- HCWFILTER
L RF OFF
+10VREFERENCE
...!#:.�"::
"::
�f:W.$!'��� ..:::::s:::::t��::::�1l�-:;... TUNE
DAC
TUNE
.-----.
·10VT � TUNE TO
YIG DRIVERS
SWEEP
I
TIME I
DAC
HRETRACE
RAMP -10V
L DWELL ENABLE
CONTROL DWELL
L CLEAR DWELL LOGIC
®��x:�«:..--::�:::::;::s ��'i>...
MARKER
SWITCH
POINT �10V
MARKER-
SWITCH
z·10Y
POINT.
ll --.:
ll!Jlll�=�'� ::: : :::-.-.;:;.o:;::: :;w:m***.� DAC COMP
SWEEP
LINEARITY
WIDTH
DAC
DAC
21-11
TEST POINTS
TP1 GND G TP8 FM SW P
TP2 DVM EXT INPUT TP9 GND G
TP3 20V .1F TP10 V DET
TP4 TUNE DAC OUT TP11 V TH
TPS TUNE TP12 V dBm
TP6 SWIT CH POINT DET OUT TP13 Not Used
TP7 LINEARIZER DAG OUT
TP1-13
TP2, 10, 11, and 12 measurements are made with reference to GND G at T P1.
TP3-9 measurements are made with reference to GND G at TP9. 2 4 6 8 10 12
1 3 5 7 9 11 13
U24 U18 J
>-------<1
��::y:o:�:::1 �
��
��
,_____--
-----.=-r- �
�€::y:n:::1 rn � U
��::y:o:�:::1! �
1
27 U26
U
�€::y:o:t:::1 �€::m�:::1 �
1 �
U03
(Front) 1 P1 69
NOTE:
Leading zeros on
component number
references may be
disregarded.
A17 ANALOG INSTRUCTION PCB PARTS LOCATOR DIAGRAM 21 ANALOG INSTRUCTION
A17
ANALOG
INSTRUCTION
�
Ul
w
21-12 67XXB MM
0 1 2 3 4
+
svµ.,
+\OY REF 2_
, �
�5\J
+5V
v
A
V'o.1
80 �
CSI C52- U2..
r-----7 7i+i-!C. 373
Pl -:;.I 2-0 Zf)
:/ 2 �'°
"co
vc
I �
3
/ Q O z. I.DO
- DO
4- D I QI 5 :r.01
I
2
�
/ - ""---�
:;) I >-- " 01
"02 7 DZ.
' c
Q2. 9 ID:!> "'-
/ 0 "ID2 '\.
,3
� / 8 " " "' 03 13 D3
'- "' �
"' 84 13 04- 12.. :r:D4-"'
__ Q3
3
=-"-+ /
/
- �
i5IDS"-
�
!'\. DS 14 05
::)<.. Q4
r-- 0 / �
/ "'� 17 DCO I&> ::!Da "'-
:. :s "'::; ,__ -� .,__,____, Q5
7
�
�
8 � ....1_:C+---+
'\.. DI 18 C7
::: :D / ' --+---+-� Q�
B 0 / 6 19 ID/ '- �
'::: 7
�L�_�. --u-1---' j I
Cl 7 t--9-+--+---+--I-_.__
f <t-
____l__I_ EN
Q7
OUTC,TC
"
�
�
I u
l GD �
�
� 14-rLToZ(
8\J�;1 , ;1JY z
IL
t
pI
+\SV�A \1C
� 1
� L , _1<)'-: >----+------ '+-' 31
----------"'--' AJ -'--<
IV! - , _. Al �,_
, L
3L 5 52
c
_
33
', =-·"-i
G 53 AZ�>-+-- 1'.
7 54 t: ' 1 ,.._2-t--t---+-�
I
y � -·__.�l1=. \'"11:_;:--,1
,z 55
p e- I '.,,',,'._J r
'r=�'.D---+----'-l-'--11 s�
FM [l5 /, -J, I ��__.:7-+------------�10"'--l ;7 - 8 RCO
� ��
. 'v--
_,. /
,v/'\
>-"'3ccB"-+-------------'9� 55
-
+--.._,__
-+---+-
LJ >- __
?::OZ. 'V\ '.X'1 ; O «.
0.1%
l
U7
-IS<'G:JAW =.-6508
D
- '::!CA� IC
P, I
�3�S>'-+-------------''"'"-j S I A0f-<
>---
4�0---+-----------�5""- s 2. Je.__
A I
RIZ.
'°
Az.§__
909K�I0.18K<
C O<
7 54 t: N ,_2---+---+-+--�
�
RI
�
SS
1
1 50 I •
10 57
vv 0.1°/o
?cl S B I".:! K
O. I 0/o
E
i::0:0-1�/
��
RIO 8
v'
LE vc
()
, c.sro�
;_
� \Ol<
l :JISA
2 P',I�
� DC::iZOC
0 I
sc . .c�
v : SI
- ui°SB
�:i 52. A 1 �
A.0-
v DET /4lo�E�----------_::: • UI
D6 2.00
Az �
: � ��3
��-------- ----'6�53 7'+HC11 ::,a
� YC YO�
� Y3bi£
RI
;clB!">""\ �
,,_10-;RE'F I �
7 54
12 SS
EN 2.
�..J._ A 4
y I L�>-'1 "'---+--+--'
I0
yz. c-' >'-3
1 =-+-+-__J '
F NE � 11 SS 2 B
TU
Dcwr-1 ,
�
_j�l O SI C '--t---+----
c•NV£2.TGR tooPM0"1 )-"'o�l:�________
__
._gi_ EN\ YLt C�>-'-'-
___
--=
r-�._
D
"'-" 1 1---+--+--
Y<oo-9=---+--4---,1 I
l'"M_ MO\J 3 SB
l I
�---=3o.i /E U13 �__,__,--;_4'-::n-< ENZA y5,L}- h ,,..
1 0-- f----+--�
Dv t/ ENZB
::i ___J .jd_ SD Y7o-'-'----+-__J �------
�I _ S\i([_;:o,.W CGS08 �---
LPA IS �' ��
LPA I� I '-+
I
I:)
/
G
PP..0
i
���·
PA1 z.
r1
..1 r=�
PAZ.
)fil:
1-
A17 ANALOG INSTRUCTION SCHEMATIC NOTES:
I J
+SYD
REFERENCE DESIGNATORS 1. UNLESS OTHERWISE SPECIFIED,
01'
I? RESISTANCES ARE IN OHMS (rl),
GND D
LAST USED NOT USED
CAPACITANCES ARE IN MICROFARADS (µF).
+
C64 CRS
�I
INDUCTANCES ARE IN MICROHENRIES (µH).
CR21 CR9 4. TEST PO
2. SIGNAL FLAGS INDICATE MATCHING
>-"--++- ----------''-
,._____,.
,> 15 Y(j)
L2 R27
+ 5. TROUBLI
+IS\! 6 P1 CONNECTIONS BETWE�N MULTIPLE
2'-l
R49
Yti5YI
LEVELS
'P
SHEETS OF THIS SCHEMATIC. THE
I
01 R60
H
SHEET NUMBER AND SOURCE OR OR NOMI
R111 R78
W�o
j2/B3 )
/;·- 2-3 DESTINATION GRID COORDINATES
t
RN1 R104-107
www
6. STATICS
APPEAR INSIDE THE FLAG:
- -" TP12 TP13 THIS A�
+ 5V
DVM
t5V
LI U3 R Z.
IOOLJH
L S.c:..;...,, pu;: I
A057'+ 100 L SA_._,\ PU:: 'Z.
I X. e:,
�
vcc 7 L..
Cl C Z. L \OX B
10 L I OOX !:::>
0. 1
L IX A
'- I O X A
;a L.. I OO X A
I C.
B/ P
I Z.
OFF DAC. ��
--'"--' > HBB'-E-
... \
Z OY l-'--1- --- CAC _<::; e, N I SE·LC- 2-
1N1
--
veE 1 '�
' ___ _
c�
10 R5 JATA L ATCHES
A6 1 00
O
-VV'\r--1---
00
C4
:
+
� 5
TUNE DAC +/
L GA ! .°'J 5
L G A I N f',..
RETRACE
L DW E L LEi'o
c ��TEGRb.TOR O � r=
N E. D l>.C G b..l lJ 4
50
'- Y I Co ::>RV� 1 5EL
U l lo
z. __J
Q O r-
5
Q I r-� -I L. Y I G DRV� 3
_
SEL
D V M R AN G E S E L E C T -
Q 2. 1-
Q 3 9 _____
"'::-----__J I L 'f l G DR\/C\
�sv 0 4 1.1';
2. ;-
-15\/(D A Qs 1s ___ .2 \ '\: � -�=�
c�
I
l (o
RN \ Q G> :'.) � <::
10 7 19
L.. RF
IOK Q I
P l
CIO +
27�
=====----�1.0 i +5V
-----
ELS INDICATED
llOMINAL LEVEL';.
""'-'
UBLESHOOTING VOLTAGE AND POWER
BOXES ARE T'.'PICAL
� 1
+5V
'1
S P AR E.. 5
�(
Figure
Schematic Di
21-5. Al 7 Analog Instruction PCB
�;:���� et 1 of 4 )
NC � NC
NC
f1C SENSITIVE CO N ENTS USED IN
N( �
BLY INCL��
12
6 7 00-D- 3l 7 l 7
i ASSEM
U E. 1'.
.3 N L
�7R��:;; R9, R10, R12, R2S R29
u ' R82, R87, R108-Rl11, '
U6,U7 U9 u1 s. u1s.u22, 7'1LS I 36 7 7 't H c.T O O
LU1�. ,it,.·,�Li�;l. 21-13
0 1 2 3 4
L I NT EGRAIOR. OFI=
Rl1
1 0
A
DAC LSB � IBBLE Z.
II
R l9 n
! DO - I D7
IO K
7
B
RZO
3 z. -10\/ REF T©j 17. 8 1<.
'V'V'.---t>---..-
"'>-.:.__
__ ..._--+___:::
:..y-1 0
1 U2.0A I UZ.OB
1 D6 2.01 DG 201
- 1 5'/ T(j)
8
uz.c
SWEEP
T I M E DAC DGZ
DAC. I Z.08
�
L T � \ S SC Q> l°Z"
+IC
MK R I SW PT 01'\C. � T RB fi:•�M>-----1---l--�
RN I �
+ 5V
10K
D
�·
I
�--....----+�
R31
PI iOO CRc'o +5V
: N l $1A
U lf D
cw�
e
RETRPC.E rvei?l>-----.-���-+-�����-..-�9 14- �0 -1
e
1 4 1-l CT OO
E +SV
1 4 \..\C.TOO
F • 5'1 ± \Oy RC-F-E-R
'""
5
ONELL £"1\f �
3 <.o
L
74- L S 1
RN I +SV
IOK z.2.
C
I I
7
+
AD581
10
G
Pl i I
�
GND 6. I
'
IOK
0. 1 %
H
5 6 7 8 9
R Z IO
10 1";
0. 1 %
R.Z.I
8ZSK
1s
Pi
e o - 1ov
__l!_-o/,( I0 RAMP
I ,.____ _ 1 5V T(!) LT I COl
0
i1
I
:r.
ZQ C Cl�
R�O
ZK
-1•:JV T CR'+ I N444G:>
- I S\/ T Pl
I
15
DWELL I N T
+ I SV T ± 1 0 \/ REFERENCE
io
I
T
�4-'G.::...l4 + V
w
R8= I
+ Cl �
DAC 1'206 ._�iA> + I O V RE"° T
">'--<>-++--m<:�
J24
oi::;a. G:>I Z + IOV R E. F T
R'37
l OK
�1 0
+ C ZO
CZ� I
Pl
C G '1
.,_ (:---,
10
Q. 1%
iOK
TLOIZ. R I"" · ---- - IOV R�
'
Ro+Z.
RL\-5
IOK
0. 1 % '-����....fiTclO A + IOV RE� Z
..._����fA/,o c -1�� REF L
- 15V (j)
21-14 67XXB MM
0 1 2 3 4
3�
IJ 1 2 F
+ 1 5\I T
,1
I U fJ E- DAC +/- �· ----------------� 714 HCT04
A
.,. 1 o v P. E- F T
�-1
;
?V T®
•
, �3�A
DG>ZO \
'
� ,,A 1o !
-��201
�
�'t8i 1n-
�
::!:> __-
\""="'
U3�B
--t---
_, _.
-1ov
C"'-C l'SB
RE F "T
'-l lBB'-E- , [-
' 'J-
�
J =----------
2 0� p
�------------___.£.
..._
/"'�--------_J
I �"'
11? n
�10
+l C'Zi
V RS:: 'JC
�
14
l c2e
L'SBC> 1. I
B
2.00 PF
"'
L<SB RF'
LS B I n e, I
"'
T
L'S B Z Z. 3
�
'I BZ U34
L-? 63 Z. 4
8>?
� L'=>B4 I
B4
� l <D
u�� ._
2 ['-.._
B? !CWT 7
LS&<:::. '2.
-_;""��0oo1
f--=---i
I DO - I OI �-----..
'I "' �sBec 3
� 1
� L'S BI LI
B7
"' I DO 5
e,e, I OUT
IS
"' ID \ ((:;, 2
le:C
et')
"' :r:o z. 7
c < RSO
il
BIO
"' _L D 3 6 e,1 I
"' I D4- '3 51. 1
� ID'=:i 10 B IZ
<:,13
IDCQ ii
- 1 2.
I' - !�V T
"' IOI 1 2.
Bl4
�
MS6
L<::> B TUNE DAC
I�
Tw i'-l2 D A C 5TR B = � 2o MSB
U4FO
74 \-\(T04
D
L TLJ l. J E D i'>-C r.:it>-I LI L.. �
L 6A I W A I D
L GA I W B D
"""[Ye:6>-----t--l---I--�
''--���
E 2o v 6 F
SWEEP WIDTH
- 1 5V T
67XXB MM
5 6 7 8 9
+ I S V T (g)
LT \ 0 0 7
© -15VT©
30 . l l'., 0.1 1.
Z. 5 P P H
3 0 . I 1-', 1 2.S P PH , 10
����
R <::>2 0.1 %
_,. 1'5Y T©
I 0 1-'\JC. I % ___.__.,
2. 5 P l-' \-.\ DGZO I Pl - ca4
R54-
LT IOOl
\ OK_,_ O.I( RCo4
C.5 P \-' 1-\ 1 0 1-'-
RS5
3 0 .l t:,.l"f. :'.. R I :,
2.'0 P P\.-\ + I OV R E F T F 03 0 0
+ 1'5V T
RSI
511 CR1 2
R58 F D 300
CRl l 5. l l K
7528
8
Pl
'--�-+-���������������������--+����__
i t.03
_, F t-...11 'SVVF'
'--��-f����-l!.l!I028,"> + 5�P,
I
DA C
~
UN EAR I Z E R DAC TLJ>lEc PEF
21- 15
0 1 2 3 4
L I OC>X A
A L \ O X. A
L I "-. A.
L \ CO X. B
L I =><- B
L I X. B
u
DE-Tee.TOR A MP J 4"'A
�-Z O \
B
- I SY (i) 'O
F\14-
i4 l . 6K
Pi SO P PM
"lea<::.
10
I
PW� ...\ E� 1,;-1 I I I 0. / -;,
I
R.75
�- i i<,
O
c c�=:,
1. e K
SOPP M , O . / %
i
C�I
P\"l-Z.
+T
I
10
1 00
Cl"\ I O
:Fo 3CO 12,ta/
IM
!2,G:>0
(.,e, I -,
- 1 5V(i)B
Pv.JF'-, ...\ e t:.D TLOI Z
RE-F "T7
�
2.enrs
D -15\/(i)B R
1 . eK
:
c;:>,14 SOF>PM
Q. 1 o/o
\2;/�
I \--!---.-J'.J'��___...
FD'3C:::O
G40 I
C P, 15
FD·
I J4to5 u40C 100 + 10
�
+
U4laA
DG2.0I
L SAM Pc..E I , e,
L SA!'--1 P LE-
E
2. IT2M:;>
C4S , .0 1
I(
TEMP CO M P AM P
+ 1 '5 V(i)
F II
=='\.\...· ?�
1
,�E-A-�
4
-
n .
..\E>", M
i C I
.0 1
OFFSET AMP
G
R I O Z. 12
1 1/\ -, Q . f io
2.
4 ;:>, 1 0 � U4SC >-'-----'
10 , +
�=------..------<r----".;\/\;_-
__ L--,,2.
.3 .
iC
I L0/ 2.
P, 1 0 1
H IH
I '/,
. 01
, Q.
t
I
5 6 7 8 9
RANGE S E L EC T
U4'? '0
DG-Z.01
'----�
�-l----�--{ ()-'
P..ei ? fZ,f!><Q
��1-=-
5 ----�
RBO IK 1 10
I IK 14 1 <;:, 5DPP M SOPPM
50PP f--r--c.u_ CY-'�-- 0. / °f'o I 0. 1 °lo
�I .)-'-'
11 _ 0. 1 -;. \"SI
R8"Z.. \OK
__
\OK 50f'f>M
'::> DPf'M rr'0=-----_. 0. 1 °lo C.FI, 1 U:>
0, / 'l. 1 1--.ll o/A CP\11
'3. \ V FD3Qa
rz-ee CSI
�.Z.K I . a CRIB
TLO/"Z. \or-; 1 .0 FD300
-l'OVG:) C.
+ 1SV(i)
S Y N C H R O N OU S DET ECTOR
C.'°2
µ,'?z.
a.I
100
+ISVQ)C.
R l lO
Cl..> O +
10 �
I 10
- 1 sv , W
C� CR'ZI
PPM
1""·
50
0.1% io . I
c,, 1o<.,
1
c eo .
_, P, 1 I I
.I
+ IOK
4
SO PPM
0. 1 %
i
'-----fl OF V \h
21-16 67XXB MM
2J-YIG DRIVER SUBSYSTEM: 2J-2 YIG DRIVER PCBs, CffiCUIT
A18·A21 PCBs DESCRIPl'ION
A18-A21 PCBs:
......... ....... .. .. ...... ........ ... .............. ................ ................................. ....................
(Sheet 3 of 3) 2J-9
. . .
67XXBMM 2J-1
YIG DRIVER PCBs, CIRCUIT DESCRIPTION 2J YIG DRIVERS
whenever the H CW FILTER control line is in the When operating in the CW mode, or with sweep
high state. This feedback signal cancels the mag widths less than 50 MHz, control line H CW FILTER
netic coupling between the FM coil and the main is set to the high state. This opens analog switch
tuning coil. This produces a linear sweep for sweep U5A and closes switch U5D, connecting the filter
widths �50 MHz. network comprised of R36 and C23/24 into the feed
back path of control amplifier U6. It also connects
the feedback path from the output of Q5 (and the FM
2J-2.3 Main Tuning Coil Driver Circuits feedback signal from U4A) to the input of U6. The
feedback filter network reduces the overall
The TUNE output of the Al 7 Analog Instruction
bandwidth of the main tuning coil driver amplifier
PCB is either a de voltage that represents the tuning
from approximately 6 kHz to 30 Hz. This reduced
current needed for the selected YIG oscillator (CW
bandwidth improves the residual FM performance
mode) or a 0 to -lOV ramp signal (sweep mode). This
in the CW and narrow band sweep modes.
signal is input to the differential receiver amplifier
U4C. The output of U4C goes to the input of control
During fast broadband sweeps, analog switch U5A
amplifier U6 via analog switch U5C. Switch U5C is
is closed and U5D is open. This disconnects the feed
closed whenever the L YIG DRVR SEL input is in
back paths from the input of control amplifier U6,
the low state.
which provides wider driver circuit bandwidth. The
switching of the H CW FILTER control line is con
During 0.01 to 2 GHz operat ion, the A 2 3 trolled by the A23 Microprocessor PCB and is com
Microprocessor PCB sets the L DOWN CONV pletely automatic.
SELECT control line from the Al 7 PCB to the low
state. This closes analog switches U2A and U5B.
2J-2.4 Bias Supply Driver Circuits.
Switch U5B connects R91 in parallel with R45. This
shifts the YIG oscillator frequency to 6.01 GHz, Integrated switch U7 provides the switching logic for
which is the YIG operating frequency for the low end the YIG bias supply driver circuits. The Al8 PCB
of the band (i.e., 6.01 GHz - 6.00 GHz = .01 GHz). also includes driver circuits for the -5V YIG bias
supply and for the Frequency Downconverter as
The +V REF reference voltage from the Al 7 PCB is sembly. The A20 PCB YIG also includes driver cir
input to differential receiver U4D. The output of cuits for the Frequency Doubler assembly.
U4D (+lOV) is used as a reference for all of the
control drive signals developed by the YIG Driver Switch U7 is controlled by the L RF OFF and
L BAND SEL lines from the Al 7 PCB. When
PCB.
L RF OFF is high and L BAND SEL is low, +lOV
from the output of U4B is connected via U7 to the
The TUNE signal from U4C and the +lOV reference
input of USA This causes driver transistor Qll to
signal from U4D are summed at the input of control supply +15V bias to the YIG oscillator assembly.
amplifier U6. The output of U6 goes to the input of This also causes U9 to turn on the -5V YIG bias
driver amplifier Q4, which drives the main tuning driver, Ql3 (Al8 only).
coil drive amplifier composed of Q5 and Q7. This
amplifier furnishes the main tuning coil current for Switch U7 also connects +lOV to the input of U8B,
the associated YIG oscillator assembly. Resistor R29 which turns on driver transistor Ql2. This driver
senses the current through the main tuning coil; this circuit supplies +15V to the A31 Multiplier/Power
signal is fed back to the input of U6 by resistor R28. Amplifier assembly. This circuit is identical to the
driver circuits of the YIG bias supplies.
During fast sweeps-or stepping operations in the
GPIB mode-more main tuning coil driver voltage is When the RF OUTPUT is turned off via the front
required to speed up the current change in the main panel or a frequency is selected in another band, U7
tuning coil. The voltage switch circuit composed of connects OV to the inputs of the bias supply driver
Q6, QB and Q9 furnishes -43V to the main tuning circuits. This turns the driver circuits off, thereby
coil drive amplifier on demand. LED CR22 is used turning off the associated YIG oscillator.
in this circuit as a 1.2 V Zener diode. This switch
operates whenever the voltage drive signal to the The Al8 PCB also contains a driver circuit that
coil goes below approximately -12.5V. supplies +15V to the Frequency Downconverter as-
2J-2 67XXB MM
2J YIG DRIVERS YIG DRIVER PCBs TROUBLESHOOTING
sembly. When the synthesizer is operating in the 2J-3 YIG DRIVER PCBs
0 .01 to 2 GHz band, the A23 Microprocessor PCB TROUBLESHOOTING
sets control line L DOWN CONV SEL low (via the
Refer to the troubleshooting information located in
A29 Rear Panel Interface PCB). This causes analog
the beginning of this section (Section 2-System
switchU2A to connect +lOV to the input ofUlO. The
Description and Troubleshooting). This information
output of UlO turns on driver transistor Q16, which
provides a list of error codes that may be displayed
supplies +15V to the frequency downconverter as
as a result of failures in the RF microwave deck
sembly.
associated with the YIG Driver PCBs, A18-A21, and
probable causes of the failures.
The A20 YIG Driver PCB uses this same circuit
(with a different value for R85) to output +12V to the
Frequency Doubler (26.5 GHz to 40 GHz) or Fre 2J-4 YIG DRIVER PCBs SERVICE SHEETS
quency Tripler (40 GHz to 60 GHz) assemblies. Table 2J-1, at the front of this section, lists the block
Refer to Section 2L-RF Microwave Deck for further diagrams, schematic diagrams, and parts locator
information pertaining to these assemblies. diagrams for the A18-A21 PCBs that are contained
in this section.
67XXB MM 2J-3/2J-4
2J YIG DRIVERS
P2
Fil TERI AMP LIFIER
FM .>:------_J I
(FROM A16 PCB)
I
I
------- '
T U NE .>-----t----1 I
(FROM A17 PCB)
I
'
l BAND SELEC T ?.----..-<11 -------
+VR EF 1 ..;>r---t----.I
(FROM A17 PCB)
I u-------"
LDOWNCONVSEL�--e--t--n
_______ /
(FROM A29 PCB)
BIAS
SWITCH
LOGCI
U7
L R FOFF
(FROM A17 PCB)
:>.-:-t------1--.I POWER AMPLIFIER SUPPL
0
DOWNCONVI DOUBLER
AMP SUPPLY
67XXBMM
OVERALL YIG DRIVER PCB BLOCK DIAGRAM
P2
FM COIL
CURRENT
SENSE
MAIN COIL
r- I
A T..E
.B. .. ...±15�.. . -sv_tt_j
)
R29
__
CURRENT
VOLTAGE SENSE
SWITCH
06,08,09
-
+ 22� > ! ------�-!"__,
-17V -43V +15V
2J-5
LED CR22 TP1·13
W4 (Is used in circuit as __..._
2 4 6 8 10
RBO* ws C3* C2* R6* a 1.2V Zener diode)
1 3 5 7 9 1
:n:
00
"'"' TPO!
�:y:o:�::1m
A18
A19
A20
or
A21
PCB �
A18A1 J1
B�
�
w��1
W03
I
A19A1
A20A1 VIG DRIVER TRANSISTOR PCB
P02
or
A21A1 @ @) @
(Front) 1 P2 3S
HEAT SINK
(Back) 2 (To A28XA18, XA19, 4C
ASSEMBLY
XA20, or XA21)
(REAR VIEW)
0 � � u u I] � � �
�· � u � \] [I � u u �
0 � � IJ 0 � � l1 �
�-������I
NOTES: QS QS Q2 Q1 Q17 Q16 Q11 Q13 Q12
1. Leading zeros on component number references (Not Used)
may be disregarded.
2. All components denoted with an asterisk ( * ) on this A18A1, A19A1, A20A1, or A21A1 PCB
page are loaded according to the model type
frequency range; see the tables on each
schematic sheet for the appropriate values.
A1�A21 PCB PARTS LOCATOR DIAGRAM 2J YIG DRIVERS
A21 ---
18-26.5 GHz
A20 ---
12-20 GHz
�llll
A19 -/��,����:fl
8-12.4 GHz
����m����..!-C24* A1B -
i
R56* 2-8.4 GHz -
R46*
VIG
C27* DR IVERS
.RZC)
TESTPOINTS
TP1 FM COIL CIRCUITS
GND (GND F)
TP2 FM COIL ( +)
W1 TP3 FM COIL ( -)
W2 TP4 MAIN COIL ( +)
W3 TPS MAIN COIL ( -)
TP6 MAIN COIL CIRCUITS
GROUND (GND M)
TP7 +22V HEATER
TPB +1 2V/+15V AMP BIAS
TP9 +15V DOWN CONV/
+12V DOUBLER AMP
TP10 -5V BIAS
TP11 BIAS SENSE
_(RF DECK GROUND)
TP12 +15V BIAS
TP13 Not Used
TP2 and TP3 measurements are made
with reference to FM COIL CIRCUITS
GROUND (GND F) at TP1.
TP4 and TP5 measurements are made
with reference to MAIN COIL CIRCUITS
GROUND (GND M) at TPS.
TP7-12 measurements are made with
reference to BIAS SENSE
(RF DECK GROUND) at TP11.
2J-6 67XXBMM
0 1 2 3 4
F!Vl })RIVE.
A
p 2
I
5
+IS V FM
6
R7
311!
47
O.l
R3
c
IOI< CI
h
P2
FM
/(5 Rf.
(+-) -)iE' RB*
I z
>-'__,, l.>-----J\
FM REF z' r78k 4 5
I
I
D I
+/5V�;*
I
I
-IH(j)F
L S£Locr
D6 Z�O. I i \b
SllN(J �------- ------------�
P2
7 I
-15 V FM
b
F
6/V/J G
COMPONEW\ VALUES
,A SS Y lleS FP.eQ RANGE "'"* RB'Jic 8'11#.CZ!lc CJ
-4 Al8 2- 8 GHz 12.n / 87kIZ.4K /()()0 ff: 101
G Ai'! 0· 12.4 611J. 12.IK l.UK IZ .4;.( 6BOpF IC p
-5
• 6 ,q 20 12 4 - 20 bH> fl. 7K UJ7K 8.25.<;' /OOOfF 15 f
_7 AZ/ zo. 26. 5 /Z.7K 1.87K 1_:), 2 /\0 !000 rF 15 p
SPARE GHl
-5 AZ.I
18· 2f..5 &Ht.. 12.7 K l.87K I0.2K IOOOpt I Sp
IL./ K l.B/11. ll:•.,, I 'Ill/pt I Up
__:cL_L.ttl!;L___ � -. l!.l3rt?•.
NC.
NC.
H
67XXBMM
- 6 I 6 7 8 9
�2
f()
C.,,_ + P(o Az.8
/llOTHER
+
i � 7% 80/f<RO
Rl.3
4.flK Pl
12
1
C/f./
'"' ""'"
CR3
Cln
!NH�&
!NI#'
'
I
CA.� li'2
'"'�"
en
INl-#46
CA'
/Al�"' Pl
I
22 Ge
T/P/15
Rt 7
4-4t K.
� c:a· O
i/
C7 , .,
/()
.RIG.
ldO � Rl6
Ifb
-..�����
�������������������������-�
Cb
A18 YIG DRIVER SCHEMATIC NOTES:
COllPONEHTS USEO II
CONNECTlONS BETWEE N llUL TlPlE
SHEETS OF THIS satEllATIC. THE
8. STATIC SENSlllVE
2.J-7
0 1 2 3 4
c·�
01 YIG Tu:
TES T R2e
A
5.DIK
en*
o'
-1--ISVM
''":. ::,
IClD
l
B
'::620 I
b
c
----•-ISVQ)M
=<4z
�*I�
1 C21
�-�-�
847
,---Vv -!SV
R4 4
'
P2
I _ __,.,,..,,"_____ ___-'\,"-A---4
-4= ..,____..._
7. - 1K
IS �
I c z i -r'"'�
+vP::=r-1 �- b --< - ./'./'
10
L SB
l ��v"Ar---
\
;:ig I 'J(
E '.C0..201�
L
c���
DC SELE:Cf �f--+---- -----!'-- . 8
:<54
P2
I
�S'l
1<8 ')j(.
TtJtJE
1 :=. ""--� <-- -
<:-- n-- er-r----vv - -
":) -
R ".::.f,lf
' -'-1----�'\/\/\r-+---+-- --.i----_,..t----'
I � VJ2.
I
:< -=.:::,
C, IC c,...:.
lt..J9<'.0ZBJ !IV
f- i:::�, .,....,_Q:.'.l..
P5b
F 10>-<
: .: ""
P?
11
G
+1':::'VM
:�� I
•
+1SVG
?1
- l'::>VG
p- ·
�
2 2. I ·I
• -1'=V1V1 [ COM PONENI \i\LUES
-:::;t-D
--..i S
: IQ: l ® /::EJ?Y <:::ES FREQR�E PA<::>"*: ?.5<D* c.11 '* Cc7'1: R-LIG,*
-?. '
l
-4 A18 Z-E>Gr-1-z:. /(,')I< 21.L;K ZCC>pF- .01 8 4(,,4 /(
-? Al':l 8-1z. 4 C::ii-\a 2 (o. I t<. . 01
H
_,e, v
� ?t=-
.. - I B\;}\.\ -(,:, A.2.0 12..4-ZOGl-\a 14.:::,�
34.BK
,.., &�
390nF
z-1opi; 4700 pf
4CfCfK
4Z.lK
_..., AZ\ Z0.0-2"".5 C::lHa 30.q K 4/0p� 49CfK
I
151<. 4760 pf
I I0.2 K
-43'\/
� • -43VM -B
-9
A 2. I
AIB
18.0-2.b.5 GHr
2.-B6Hi! 105 .I(
33.2 K
27. 41(
470 pF
ZOO PF
4700pF
.016
499K.
4G.�i<
7 8 9
1 =·=· =��=:��=:::::.::::�'''�-:�-:-
-.;..
. ....... . ...... ��T*�'=-»-"
. � """'""",_..... ,
� 'A� IN CC " , t' ! �
i
I
----- --.-
----------- ------ 3 C::--4i
---+------+--
..••.. ..•..�
. � �
.. ·
.
f: I Y 6 k/.'..
.. .
l �
�/3t}
::-:::i
!::
�:IA.2Ci'1�Z_
''.�; �: �
-
-� -
'..
:::
••
·.j: �f§;
•
b
I
_,
�vvv.----..---��---+--+--� �
' 3L.- MA1N CC,L (-) :<
CR\I
I"': I 2_ ...
t
�·
,::p.,z L;::»;�=: :;:= �=;:.-: :-= �
:::;;::::�::-:::::::·=·= =·:·:·:·=·=·:· -f
= :-=·=·:·=·=·: :·=·:·:-:-:·:·:·=·:-=·=·:::·:-:-;,:· <·=···:·:···:·:··· ··:·=·:·:.:····-;.:-··:-:-:-=-=
\ W5'3':0P'J
·
24V
�w
:::zs
,?;,O pf' p I
25
::P 3
JJ'l750A
'-.7 v
F'.46
Sil
.f'
.541<
p .---
C30 ---<1-<
D Q")
i
O
MPSA.42
PC:,O
":3."'>rc, "'' R0\
3:::2
-4 � V M
-- ___..
_ __ __J
______________ ___
---�-{�Q>o TIClVM
�
� L
E::C."-JC:: '5E:LEC.T
Tl'SVM
-l'=>VM
c_ 2
'* t'i'- P,qJ
I( 39 p-f },)/).
K 3C/pf Ni). Figure 2J-3. A18-A21 YIG Driver PCB
i: 39pf NU Schematic Diagram (Sheet 2 of 3)
f\I Ll 6700-D-31718-4 thru -9 (Rev. P)
( 6'l3 I'�
( 68 p.P NU
I( 3qpF 105K
2J-8 67XXB MM
0 1 2 3 4
Pl
Z7
+ z.z v 28
.;i;O.
CB
I
R66
B � � '' '�
�\, ?-<,0. , '%1 JK_l!J1,
7 R?I
:J4 +15 VB
1''64 5
4. f1K
-2/61- >-- " '\/\. \r----'
�---·
'�/(1 C-!°Jo 14
TL014
L
R7Z.
/0/(
R6S v�
!OK 4 >IA
o. ! °lo
c ' 53�
CRZO,
7 >-IA
"1BD501
13 518
il SU)
II 538
JO 548
L RF OFF I
AO U7
lb
D BllN" St:-ll�C T Ill
z €/'/
DbSO'I
4Na V-
15 3
w -/5 VB
E
(/127
/nl3DSO/
F
P2 B
���-
�lc0.451 i!
DOUB I
511 'I
Df-, 2 !)0
___§_\:LE
G
� .15V8
R87
+15 VM CR28
R83
... �� /OOK M/3!)501
n.I
�
-15 VM � -/SvB 1?8!?;
R85'!11
1
-!If
.
H i 0
R64-
!OK
0./%
w
67XXBMM
5 6 7 8 9
PIO Al8
R6 7
MOT11EMOARD P/o RF COM? t>.,�'(S-
� ��:«�»::· -;::::.:�:::�·:f.;-:::�·:·:
p 2.. ��
* +zzv Ht:AT€1(
1K
-,,-
, -_-5 ________ _ _______..____;_
z'-"' I �.
:·:::.:-:-:·:-:·:<·:-:-:-:-:-:::::::-:::·:·:·:�-:-:-:=:-:::::-:;:·:::::..
J1>,1•,17,lf-to
YIG OSCILLATOR
BIAS SUPPLIES
--------•-------- ---
-,--5 V-B-- --+-----�
3 ' >----->
+IS V o/'lS
-...
R 73
"
1.q'I� I ,,,
--.A.Rf\7/'___
4 _____,
______________.,___-+-_____35-+-I '°' -5 V 6/A s
I
CJS
Of .,. /.0
I I - 7 T·
m
en
�:
*
·�
!
1apF
t:
�
; Iii V fj (1(3/ i
/N7S5 � f'IO
P1-q
I.�;
MOTHER.
BoARO
-Jo V8
I
P!-11
POWER AMP
SUPPLY
ST8568
CllJZ
}
,J!S,16 ' 17' !'I- 13 �� +IZV/+l�V
) ) (+ISV +12v
AMP f'ilf\�
Arn/ AZ.I)
A I B/Al'.l�
1.10
fOR
t FOR
(
;;;
�N CONVERTER
L>-----.1--+-> :1
ER /AMP +15
DoJ)Bf..E� A MP
BL v DOW/\/ LONV I
)------4
t!·,. J41 �!
PPLY
- J:i._
_, 1- 1 .;J_ v
-
·�:
.. , ,,,- -" ).
-
-- - ...,.,,. ,,,,
, ?6 , ,, -<
, ,,,., ,, .,-
.. ,. .._
-,.,..
,...
1>1'l
,
STJ350(;
CR33
RB<o
1-0
3W
-----------��--'
Figure 2J.s. Al8-A21 YIG Driver PCB
Schematic Diagram (Sheet 3 of 3)
6700-D-31718-4 thru -9 (Rev. P)
2J-9/2J-10
2K-ALC/PULSE MODULATION diagram and partial schematic diagrams for the A29
SUBSYSTEM: A15, A13, AND A29 PCBS Rear Panel Interface PCB are located in this section.
Refer to Section 2-Inputs/ Outputs for complete
schematics for this PCB.
I I
All major circuits of the ALC loop are controlled by
the synthesizer main microprocessor. When a RF
....•"""'"'"'"'""""""'"f'"
Documentation Reference Page
"""'""""""""""'"•"•"•"•'"•'"" ... ........ f
"""""'""""' "'""•""""""""
output power level is selected by the operator, the
··
0v0 raff o0;��ipiian
· ·
OVERALL ASSEMBLY LEVEL
P"ara: 2i<: r1
·· · ·· 1
·· ···· ·····-·····..--- ---·
· . · · ·
·
1 2i< 1
·· · ·
··
= ······· ·
main microprocessor sets the ALC level reference
voltage (on the A15 PCB) to a value equal to the
desired RF output voltage. The ALC reference volt
.. �!9.��..�.i.�W.��.................... ..................... ���:...?.���...............�.���.......
. age is compared to a sample of the RF output from
PCB LEVEL
''A1y:ffiuis E G"e�rP'ce.... ......
the Level Detector and an error signal is developed
· · · v___ ...................-.. ..... ... ......
_. ---�--�-----�.....-
67XXB MM 2K-1
A 15 ALC PCB FUNCTIONAL DESCRIPTION 2K ALC/ PULSE MODULATION
2K-2 A15 ALC PCB FUNCTIONAL The output of U9B is summed with the ALC refer
DESCRIPTION ence voltage (and the ALC SLOPE signal) before
being applied to the ALC Level and range DACs.
This maintains a constant-percentage AM signal
The major ALC circuits are located on the Al5 PCB;
these circuits are discussed in the following para
with a changing reference-level voltage.
graphs. Refer to the overall block diagram of the Al5
NOTE:
PCB (Figure 2K-2), and to the schematic diagram
(Figure 2K-S).
If the external AM input signal is 1 volt
peak, then the actual %AM equals the
2K-2.1 Microprocessor Control %AM level selected. If the input signal is
The ALC internal data bus is buffered from the main not 1 volt peak, then the modulation per
processor data bus by latch Ul. Whenever the ALC centage is something other than the %AM
level selected.
PCB is addressed via the L PAl 7 line, the data on
%AM DAC.
digital voltmeter to measure the voltages from the
ALC peak and trough detectors. It then calculates
the actual percentage of AM using the peak and
The output of USD goes to the 12-Bit Level DAC,
trough measurements.
Ul 7. The output of Ul 7 goes to the input of S-Bit
ALC Range DAC, Ul9A. The combination of these
two DACs provides a 1 million-bit resolution over 2K-2.4 ALC Slope Circuits
the typical 20 dB control range of the level loop. The
main microprocessor sets the output voltage level This circuit compensates for an increasing or
from the ALC DAC circuits equal to that of the decreasing output power-vs-frequency characteristic
desired RF output signal. of the microwave circuits. This correction is usually
for a decreasing-output vs increasing-frequency
characteristic caused by the level detectors (and op
2K-2.3 External AM Circuits tional step attenuator).
The external AM input signals from the front and
rear panel connectors go to Input Amplifiers U6A The V /GHz circuits on the A29 PCB provide an ALC
and U6D. The outputs of U6A/U6D are summed by Slope correction that has a linear voltage change for
amplifier U6B. The output of U6B is connected to a linear change in frequency. The output of these
the AM Peak Detector, the AM Trough Detector, and circuits is the ALC SLOPE signal that goes to the
the %AM DAC circuits. unity gain buffer amplifier, USA (on the Al5 PCB).
The main microprocessor adjusts the output of the The output from USA is fed to the ALC Range DAC,
%AM DAC, U9B to provide the necessary modula U9B. The data for setting this DAC is stored in the
tion signal voltage required for the %AM level EEPROM on the A23 PCB. This data is stored into
selected. (The operator selects the desired %AM the EEPROM by the main microprocessor during
level by using the front panel keys or via the GPI B.) calibration of the synthesizer.
2K-2 67XXB MM
2K ALC I P ULSE MODULA TION
, ----------------------------------------------------------------------------------
, ----
: BUFFER P/0 A15 PCB
' EXTERNAL I I AMP
AM I
I (FROM FRONT' 1
[ REAR PANEL)
_J ALC REF
RF LEVEL
SET CIRCUITS
ALC SLOPE
FROM A29 PCB
RANGE/LEVEL
DACS
-1 0V REFERENCE
SAMPLE I HOLD
ALC
SUMMING
NODE CIRCUIT
RF
DET
LEVEL
SHAPER
CIRCUITS
1 -4
>-!
FET SW-3
,
BAND DET
___
L-----------------------------------------------------------------------------------·
67XXB MM
OVERALL ALC LOOP BLOCK DIAGRAM
I
YIG
j
: OSCILLATOR(S)
I (BANDS 1 -4) -----
BANDS1-4 LEVEL
I CONTROL RF OUTPUT
DETECTOR(S)
TO ATTENUATOR*
MODULATOR(S) PIN SWITCH OR RF OUTPUT
1
1.
·
:
1.i
BANDS1 -4 DET
:1.i *OPTIONAL .
:1 .i ' MODELS WITH I
.01·2 GHz ONLY '
:1.i
:1 .i
:1 .i
1: .i
:j
1.
: ·-··- ·-·· -··-··- -- -·
;:: ::===========================1
-
:.... . -
!. PIO A29 ece :
·
I I
ALC I
CONTROL PIN PIN DRIVER(S
SHAPER
I .
L.. .··-·--··-··-··-··-··-··-··-··
: ·-··-··-··-··-··-··-··-··-·· j
1
I PIOA13 ece
I SERIAL DATA
SERIAUPARALLEL :I
CONVERTER
j FROM A8PCB C IRCUITS I
I
. .. CONTROL
I MODULATOR
' c I'
I
. • -1 1
PULSE
GENERATOR : DRIVER S)
l
j
-
EXTERNAL : !
···-·-··-------·· I PU LSE I!
I_INPUTS":_
J SAMPLE/HOLD
I i. _. �
________ ___________________
2K-3
A 15 ALC PCB FUNCTIONAL DESCR IPTION 2K AL CI PULSE MODULA TION
The EEPROM data includes ALC slope range set Table 2K-2. Relay Kl Operation
tings for the CW and stepped-sweep modes. Also FUNCTION K1 STATUS
included are two additional settings for the ALC
CW (no AM or Pulse modulation) CLOSED
Range DAC that are used only in the analog sweep
mode. One is for :5;2 GHz, and the other is for STEP I ANALOG SWEEP CLOSED
>2 GHz.
AM CLOSED
2K-2.6 External ALC Level Circuits switches Ql 7, Ql8, and Ql9. This circuit selects the
input to the Detector Shaper Circuits (U30, etc.).
In the external level mode, an external detector is
used to monitor the RF output of the synthesizer. The output of Ul9B also goes to the input of buffer
(The external detector goes to the front panel EXT amplifier U36. When an external detector is used,
LEVEL connector.) The signal from the EXT LEVEL FET switch Q19 is opened. The output of U36 is
connector goes to the x5 preamplifier located on the connected via FET switches Q32 and Q34, to the
A2 Front Panel Control PCB. input of the ALC Comparator circuit.
2K-4 67XXB MM
2K ALC I P ULSE MODULA TION
L INT LVL
PA1 "">---...-.
........_�.,-���, DATA L EXT PWR MTR
PAO
LATCH L BAND 1 - 4 DET
PA2 >--_.. L B AND O DET
"">---...-.
U4 L EXT DET
�==::::==:�
:::
LPA17
EXT LVL
1----+-----+-1
FP EXT LVL >-_.__..
AUTOPOLARITY
GAIN DAC
U22
U 1 9B
(FRONT PANEL
FROM VIA A2)
Q1 7
Q18
1- 4 >-_.__..
J1
BAND DET
(§'3 ,--------
Q20, 021 , Q26, and Q27
C
-------------.iSAMPL�HOLD ONTROL CKTS
�
SAMPLE/HOLD -
FROM A13 PCB
67XXB MM
A15 ALC PCB BLOCK DIAGRAM
BAND 1-4
• �
:::
DETECTOR
THERMISTOR ... -
.... ANALOG , ALC MON 1
:::
U14D
...
MUX
.... -
/
�
� U15
ALC MON 2
llii@
.AM DETZERO
IUX AO
IUX A1
.VL DIP
IUNLVLD LO
ALC REF
ALC
RANGE
L FXD GAIN
DAC DATA L EXT PWR MTR COMP
U19A
(8- BIT)
LATCH L EXT DET COMP
L PULSE COMP
L EXT DET PREAMPI';\
t-=-�--=--��----+--\!J
U3 E
1-=L� P�
� X�T� W M
R�
;..:. TR
.:__ �� P�
R�E�
A� __.<V
M�P--1_
,______.
l
DETECTOR
SHAPER
CIRCUITS GAINJCOMPENSATION
U30-U33 031/033 NETWORK
R159/C68-C70
)18
RF LVL
.><:>----..
032/Q34 UNLEVELED
2K-5
A 15 ALC PCB FUNCTIONAL DESCRIPTION 2K AL CI PULSE MODULA TION
2K-2.7 External ALC Gain Calibration initial measurement of the internal detector sig
nal as described above.
The input voltage at the EXT LEVEL input connector
varies over a large range. The main microprocessor
software includes a procedure for adjusting the ex 2K-2.8 Detector Shaper Circuit
ternal detector signal voltage to a level usable by the
The percentage of amplitude modulation of a RF
ALC loop. This calibration procedure is invoked from
signal is the ratio of the modulating voltage vs the
the front panel and is performed by the synthesizer
RF carrier voltage. The detector diodes that are part
main microprocessor. To initiate the calibration pro
of the microwave deck Level Detectors are square
cedure, either EXT DETECTOR or EXT POWER MTR
law devices. (The output voltage of these devices is
must first be selected by using the LEVELING key.
a function of the input power.) To maintain a con
When the EXT GAIN CAL key is pressed, the follow
stant %AM with changing RF power levels (and
ing occurs (EXT DETECTOR selected):
prevent the introduction of AM distortion), a linear
1. The output of the appropriate internal detector voltage-output versus RF-voltage-input response is
(Band 1-4 or Band O) is switched to the input of necessary.
the Detector Shaper circuits (U32) and the RF
output is leveled in the normal manner.
The selected detector signal goes to the input of the
2. The output of the Detector Shaper circuit (DET Detector Shaper circuits. These circuits compensate
SHAPER MONITOR) is read by the main for the square-law characteristic of the diodes in the
microprocessor via the voltmeter circuits located Level Detectors. The output signal produced by
on the Al7 PCB. these circuits has the correct linear-voltage-output
3. The xl External ALC amplifier is selected (U29) versus RF-voltage-input characteristic.
and the External ALC Range DAC is
programmed for minimum gain (high attenua The outputs of the detector preamplifiers go to the
tion). switching circuit consisting of FET switches Ql7,
The output of the ALC Range DAC (U19B) is Q18, and Q19. These switches select either one of
4.
the two Detector Preamplifier outputs, or the output
switched to the input to the Detector Shaper
from the ALC Range DAC as the input to the Detec
circuit. The main microprocessor steps the bits
tor Shaper circuits.
of the ALC Range DAC until the External ALC
signal value is equal to the value of the internal
detector signal that was read initially. The Detector Shaper circuits consist of operational
amplifiers U31/U32 and FETs U30NU30B. The cir
This completes the calibration of the External ALC cuit composed of FET U30B, potentiometer R203
signal path gain. This procedure guarantees that the and operational amplifier U31B provides tempera
RF power level sensed at the input of the external ture compensation for FET U30A. The circuit com
level detector is set equal to the power for which the posed of potentiometer R197 and U31B is used to
synthesizer is set in the INT leveling mode. adjust the AM linearity of the ALC loop. The output
of this circuit is switched to one input of the ALC
Comparator circuit via FET switches Q31 and Q33.
2K-6 67XXB MM
2K AL C/PULSE MODULATION A 15 ALC PCB FUNCTIONAL DESCRIPTION
Summing Node). The ALC loop error voltage is 2K-2.10 ALC Level Amplifier
zero when the ALC loop is balanced.
The first stage of the ALC level amplifier is opera
b. Sample/Hold Circuits tional amplifier U40, which drives output transis
tors Q28 and Q29. The output of these transistors is
The ALC loop error voltage is the input to the
the ALC CNTRL signal that goes to the PIN diode
Sample /Hold circuits. The ALC sample/hold cir
current driver circuits located on the A29 Rear Panel
cuit is composed of FET switches Q23 and Q24,
Interface PCB.
along with FETs Q22 and Q25. FETs Q22 and
Q25 are used as coupling diodes. The gate-to
drain capacitance ofQ24 is the holding capacitor The output of Q28 and Q29 is fed back through the
for this circuit. These circuits are used in the gain setting and frequency compensation networks
sample/hold mode only during the pulse modula to the input of U40 (sheet 5 of Figure 2K-8). The
tion modes. In all other modes, Q24 is on and overall ALC loop bandwidth is determined by the
Q23 is off. characteristics of the following: selected detector
preamplifier, shaper circuits, ALC level amplifier
gain/frequency compensation networks, and the A29
T h e operation of this circuit during the
PCB PIN shaper circuits. In a non-pulse mode, the
sample/hold mode is as follows.
loop bandwidth is typically 100 kHz. In the pulse
• During the ON portion of the RF output pulse, mode, the bandwidth is approximately 20 kHz. (This
the gate-to-drain capacita nce of Q24 is bandwidth also depends on the pulse width and
charged to the value of the ALC error voltage. repetition frequency of the pulse modulation signal.)
This voltage is the input to the ALC Level When externally leveled with a power meter, the
Amplifier (U40). loop bandwidth is approximately 0. 7 Hz. This nar
• During the OFF condition of the pulse, Q24 is row bandwidth compensates for the slow response of
off and Q23 is on. This effectively shorts the a power meter.
drain of Q24 to ground. The voltage level
stored on the gate-to-drain capacitance ofQ24
is the input to U40. This action prevents the
2K-2.11 Unleveled Logic Circuits
ALC loop from shifting the output level
during the OFF portion of the modulation
pulse waveform (which would cause distortion In normal operation, comparators U41 and U42
of the RF output pulse waveform). sense the ALC CNTRL output of the ALC Level
Amplifier. If the RF output is too high, or does not
reach the power level selected, then the ALC CNTRL
The drive signals for the sample/hold circuit are
signal goes outside of its normal -SY to OV operating
generated by the Sample/Hold Switch circuits
range. When this occurs, either U41 or U42 pulls the
composed of transistorsQ20, Q21, Q26 and Q27.
L UNLEVELED line low,. This does the following:
Transistors Q20 and Q21 function as a flip-flop
that is driven by the SAMPLFJHOLD signal • Turns on the front panel UNLEVELED indicator
from connector Jl. This signal is generated by LED.
the timing circuits located on the A13 Pulse Gen
• Signals the main microprocessor (via the A29
erator PCB. Transistors Q26 and Q27 produce
PCB) that the ALC loop is no longer controlling
the correct drive signals for the sampling cir
the RF output level.
cuits. These circuits are enabled on/off by the
H S/H EN control line (via gate U12A).
67XXB MM 2K-7
A 13 PULSE GENERA TOR PCB CIRCUIT DESCRIPTION 2K ALC! PULSE MODULA TION
2K-8 67XXB MM
2K ALC I PULSE MODULA TION A 13 PULSE GENERA TOR PCB CIRCUIT DESCRIPTION
In the external ttriggered mode, the external The output of the Pulse FF is routed via buffer
pulse source signal is synchronized with the in gate U26A to the rear panel PULSE SYNC OUT
ternal pulse generator clock circuits by flip-flop PUT connector. This output is also routed to the
U38A. The leading edge of the synchronized ex input of the Pulse Resolution generator circuits.
ternal pulse waveform (i.e., the output of U38A)
triggers the Gating Edge Flip-flop, U25B, to in The Pulse Resolution Generator circuits, com
itiate the generation of the modulation pulse posed of U28B, U29 and U30, function as a delay
waveform. The waveform pulse width is deter line with three outputs that are delayed by 25,
mined by the pulse width counter circuits in the 50, and 75 nanoseconds. The selection of these
normal manner. outputs, OR'ed together with the output of the
Pulse FF, provide 25 ns pulse width resolution
for all internally generated pulses from 25 ns to
In the delayed triggered mode, the desired trig 100 us pulse width.
ger delay is entered via the front panel DELAY
key. The Hold-Off Delay Flip-Flop (U38B), in
conjunction with the PRF counter circuits, 2K-3.2 Source/Mode Select Control Circuits
generate the desired delay between the leading In the internal pulse modulatwn mode, the pulse
edge of the external pulse source waveform and source select circuit (U24) connects the DIVIDED
the start of the modulating pulse. In this mode, PRF CLK signal to the pulse generator circuits. Also,
Pulse Start Flip-flop U27A is triggered to start the mode select circuit (U31) connects the output of
the generation of the modulating pulse the Pulse FF to the input to the pulse PIN driver
waveform (Figure 2K-6). circuits (via the 100 & 25 ns Pulse Resolution cir
cuits).
In the external gated mode, the DIVIDED PRF
CLK signal to the Pulse Source Select circuit is In the external pulse mode, the mode select circuit
gated on and off by the external pulse source (U31) connects the external pulse source signal
waveform by U2B and U14B. (from the front/rear panel input connectors) to the
input of the pulse modulation PIN driver circuits.
The RF output signal is thus modulated with the
NOTE:
external source waveform.
For proper operation, the period of the
external pulse source signal must be In the external triggered mode, the external pulse
greater than the sum of the pulse source signal is synchronized with the internal pulse
repetition rate period and pulse width generator clock circuits by flip-flop U38A . This
of the internal pulse waveform. The synchronized external pulse waveform is selected by
pulse width of the external pulse U24 to trigger the Gating Edge Flip-flop, U25B, to
source must also exceed that of the initiate the generation of the modulation pulse
internal pulse. waveform.
67XXB MM 2K-9
A29 REAR PANEL INTERFACE PCB CIRCUrrs DESCRIPTION 2K ALC I PULSE MODULA TION
The output of U31 also goes to the Pulse Mux circuit The data for V/GHZ DACs, U13 and Ul5 are latched
composed of gates U35A-U35D. These gates route onto control latches U8 and U9. The data is then
the pulse modulation signal to the proper PIN driver strobed from these latches into the internal latches
circuit for the band selected. The PIN drivers are of the DACs, as appropriate.
high-speed high-current driver circuits that control
the pulse PIN diodes located in the control The 0-lOV ramp signal from the Al 7 PCB is input
modulators. These circuits are composed as listed to the V/GHz Slope DAC, U13. The output of U13
below. (via UllD) is combined with the output to the V/GHz
• Band 1: Q3-Q7, and U36A, B and F Offset DAC Ul5 (via Ul6A) by operational amplifier
Ul4 to produce the V/GHz signal. This signal is
• Band 2: Q8-Ql2, and U36C, D and E
routed to the rear panel V/GHz connector (via the
• Band 3: Ql3-Ql7, and U37A, B and F A27 1/0 PCB).
• Band 4: QlS-Q22, and U37C, D and E
The outputs of DACs Ul3 and Ul5 are also com
bined with the + lOV REF voltage from the Al7 PCB
2K-3.4 A13 PCB Processor Interface
by operational amplifier Ul6B. The output of Ul6B
Circuits
is the ALC SLOPE control signal for the Al5 ALC
The synthesizer main microprocessor controls the PCB.
pulse generator to produce pulse modulation of the
RF output signal per the commands received from The output of DAC Ul5 provides the sweep-width
either the front panel or via the GPIB. It interfaces and detector characteristic offsets for the V/GHz and
with the Al3 pulse generator through the AS Serial ALC SLOPE signals. The offset signal from buffer
1/0 PCB. On the Al5 PCB, serial-parallel interface amplifier Ul6A is summed into the ramp signal from
circuits Ul0/Ul6 and U33/U34, convert the serial buffer amplifier UllD in the analog sweep mode; it
data received from the AS Serial 1/0 PCB into paral is also summed into the de level signal during CW
lel data that is stored in control latches. or stepped sweep modes.
The serial data is clocked into the Al3 PCB by two Analog switch Ul2B sets the gain of operational
clocks from the AS PCB: the Pulse Generator Clock, amplifier Ul4 for either a lV/GHz or a 0.5V/GHz
and the Pulse Trigger Clock. The instructions and output. This switch is controlled by the A23
data for the pulse generator circuits are clocked into Microprocessor PCB.
UlO and U16 via the Pulse Generator Clock; this
data is used to set the pulse frequency and pulse
width. The instructions/data that are clocked into 2K-4.2 ALC Control Signal Drive Circuits
U33 and U34 by the Pulse Trigger Clock are used to
select the operating mode and the appropriate pulse Refer to Figure 2K-4 and to sheet 5 of the A29 PCB
modulation PIN driver circuit. schematic diagram (Figure 2K-11). The Control
Modulator PIN driver circuits, located on the A29
PCB, are described below. All of these circuits
2K-4 A29 REAR PANEL INTERFACE PCB operate under the control of the A23 Microprocessor
CIRCUITS DESCRIPTION PCB.
The following circuit description applies only to the • PIN Shaper/Driver Circuit- The ALC CNTRL
portion of the A29 PCB that is part of the ALC power signal from the Al5 PCB is input to the circuit
level control subsystem. Refer to the block diagram composed of DAC U38B, analog multiplier chip
for these A29 circuits (Figure 2K-4) on the facing U40, operational amplifiers U42/U43, and tran
page. The parts locator diagram and schematic sistors Q23/Q2S. The gain of this circuit is non
diagrams for these circuits are located in Figures linear to compensate for the characteristics of the
2K-9 thru 2K-11. A complete set of schematic Control Modulator PIN diodes (i.e., it has a gain
diagrams for the A29 PCB are located in Sec characteristic that decreases logarithmically with
tion 2D-Inputs/Outputs. increasing input signal amplitude).
2K-10 67XXB MM
2K AL C I PULSE MODULA TION
,, -
10 MHz
- so
�
... PULSE Pl
-
CLOCK
-
CLOCK
1 MHz RE PETITION
-
DIVIDE SELECT
:;�,,__
I __.�
� SE
FREQU ENCY
10 MHz .. CIRCUITS 100 KHz CIRCUITS ..
-
COUNTER
I
I
FROM �
L---
U141
A10 PCB U4-U6 1 KHz U3, U15
-
I �
�D
;
� U11 -U13 ... ..
EXTERNAL
: :::.
I
:::
FF
.::: PULSE
I SYNC
I > U38A
I
SERIAL TO
I
::.'>-1--1.,.- w CIRCUITS
PARALLEL
I CONVERTER
SERIAL DATA
:jl�
AND
INSTRUCTIONS
FROM
I U10, U16,
U33, U34
I
..______.
PULSE
-
:::�:::::::::�:�=
AS PCB
WIDTH
I .. COUNTER
I
---+
U17 -U20
l_ D
,: ::.
PULSE
STOP FF
> 0
U27B
HOl
u
DEi
ns - >
I __...;(
100 AND 25
-
...
RESOLUTION RESOLUTION
..
-
GENERATOR SELECT
---+ CIRCUITS CIRCUITS
..
: ·: U2D, U28D, - U30
...
U29
,- -, -
I EXTERNAL I
I INPUTS
I
PULSE
I
EXTERNAL
PULSE INPUT
I "::>1--1� CIRCUITS
01,02
I
::·�:--� ---------------------------
·:::: :::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::�::::::::::::�:::�::::::::::;::�::::::::::::::::::::::::::::::�::::::::::::�::�:::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::;:;::::::::::::::::::::::::::::::::::::::::::::::::::::::�::::::::::::�:;::::::�::::::::::::::��::::::::::::::::::::
� - - -_J
67XXB MM
A13 PULSE GENERATOR PCB BLOCK DIAGRAM
+SV
�
v
I
ULSE D a �� I
IURCE
:LECT
PULSE
START FF
v I
·co
S,U2B, U27A
0 I
,__ AST
U24
-> CLR a I
PULSE
'
FF
I
I
: •:::.
��
U28A
PULSE SYNC
v CLR
a
TO REAR PANEL
'
I:'
I
+SV I
Lo GATING
a �
v
D
GATING
a,__
I
I
EDGE FF EDGE
CLEAR FF
I
U25B I
U25B
-
CLR I>
- I
I
I
I
I
I
I
C'-- I
LO-OFF
LAY FF
"388
:IDELAY
:I
U36,U32B
>I TO
I
SAMPLE/HOLD
A15 PCB
_3
MODE
SELECT v PULSE
*
I
CONTROL MODULATOR
-
CIRCUITS
�
r
MUX
I BAND 2 I ....1. TO BAND 2
CIRCUITS
I DRIVER I *
....,..
CONTROL MODULATOR
_.
U31 I
I BAND 3 I ....., TOBAND 3
U24,
I DRIVER I *
1
CONTROL MODULATOR
/1�l�: . U25A- D
I BAND4 I
I
....,. TOBAND4
I DRIVER I
J:::
<::;::::::: :::;:::::: :::::::::,;:::;::::::::::::::: ::·::::::::::::::::::::::::::: ::::::::::::�:,
: :
* ...-\ CONTROL MODULATOR
I
I
I
I
I
"SEE TEXT
2K-ll
ALC L OOP RF MICROWA VE DECK COMPONENTS 2K ALC I PULSE MODULATION
• Offset Current Source Circuit- This circuit is ator PCB is applied to the Pulse modulation PIN
composed of DAC U38A, U39B and transistors diodes. These PIN diodes provide the level control
Q20--Q22. It is used to adjust the operating point and modulation functions of the control modulators.
of the overall PIN Driver circuit to produce the
correct RF output levels throughout the output
2K-5.2 Switched F ilter Module
level range of the synthesizer.
• PIN Driver MUX Switch Circuit- The combined The switched filter is installed in models containing
output of the PIN Shaper/Driver and Offset Cur a 2 to 8 GHz YIG-tuned oscillator. This module
rent Source circuits is routed to FET switches provides rejection of the harmonics generated by the
Q24-Q27. Control latch U37 selects the ap 2 to 8 GHz oscillator. It also rejects harmonic signals
propriate FET switch as follows: generated by the 0.01 to 2 GHz down converter.
Q24: Bands 0 and 1 (.01-8 GHz)
Q25: Band 2 (8-12 GHz) 2K-5.3 Main Mux Switch
Q25: Band 3 (12.4-20 GHz)
The Main Mux switch multiplexes the various con
Q25: Band 2 (20-26.5 GHz)
trol modulator outputs into a common output port.
• Frequency Doubler PIN Driver Circuit- This cir This switch is not installed in units having only one
cuit is composed of operational amplifier U41, oscillator.
d r iver transistor Q32 and voltage limiters
Q33/Q34. This circuit amplifies the ALC CNTL
drive signal and provides a linear output to drive 2K-5.4 Directional Coupler
the PIN modulator diodes located in the Frequen The Directional Coupler transfers the modulated RF
cy Doubler/Amplifier/Modulator module on the signals to the synthesizer's R F OUTPUT. A portion
Microwave Deck. The voltage limiters clamp the of the RF output is detected, coupled out, and routed
output to protect the modulator. For further infor to the A15 ALC PCB for use in internal power level
mation, refer to Section 2L-RF Microwave Deck. ing. For further information, refer to Section 2L-RF
(Note: only certain models are equipped with a Microwave Deck.
Frequency Doubler module.)
2K-6 ALC I PULSE MODULATION
2K-5 ALC LOOP RF MICROWAVE DECK SUBSYSTEM SCHEMATICS
COMPONENTS
Figures 2K-5 thru 2K-8 provide schematics and
The following paragraphs briefly describe the parts locator diagrams for the A13 and A15 PCBs.
microwave components that are part of--0r interface Figure 2K-4 is the block diagram of the A29 PCB
with-the ALC loop. Depending on the model con circuits that are part of--0r interface with-the ALC
figuration, some of the components described may loop. A parts locator diagram and schematic
not be present. For further information pertaining diagrams for these circuits are located in Figures
to these components, refer to Section 2L-RF 2K-9 thru 2K-11. Schematic diagrams for the com
Microwave Deck. plete A29 PCB are located in Section 2D-In
puts/Outputs.
2K-5.1 Control Modulators
2K-7 ALC/PULSE MODULATION
The control modulators provide variable attenuation
SUBSYSTEM TROUBLESHOOTING
to control the RF power output of the YIG-tuned
oscillators. They also detect a portion of the RF input Refer to the troubleshooting information located in
from the YIG-tuned oscillators and couple it to the the front portion of Section 2-System Description
YIG Loop phase-lock circuitry (this RF sample is and Troubleshooting. This information provides a
detected prior to modulation). list of error codes that may be displayed as a result
of failures in the ALC/Pulse Modulation subsystem
The ALC CNTRL driver current from the A29 Rear cicuitry located on the Al3, A15 and A29 PCBs and
Panel Interface PCB is applied to the level control probable causes of the failures. Refer also to Section
PIN diodes (these PIN diodes also provide AM 2L-RF Microwave Deck for information pertaining
modulation of the RF output signal). The pulse to the microwave components located on the RF
modulation drive current from the A 13 Pulse Gener- microwave deck.
2K-12 67XXB MM
2K ALC I PULSE MODULA TION
0 - 1 0 V RAMP >------
FROM A 1 7 PCB
DATA
LATCH
FROM A23 PCB: ;:'>:::: :::-!
,,,,,,,,,,,:,:,:,.:,
DATA DO · D7
U9
V/GHz
SLOPE
DAC
ADDA
U1 3
LPA20 ">---I
ADDR ESS
t---�
DECODER/
PA2 '">----' V/GHz
CONTROL
.,,__
_ _,
LATCHES OFFSET
DAC
PA1
and
US, U7, US,
U37 U15
PAO "'>---I
DAC
I U38A
�-
I DAC
I U38B
PIN DRIVER/SHAPER C
DIVIDER SHAPER
NETWORKS CIRCUIT
U40, U42,
>----�t-----
U43, 028
ALC C NTRL
FROM A 1 5 PCB
67XXB MM
A29 REA R PANEL INTERFACE PCB BLOCK DIAGRAM
---·-1?-·
�-------� V/GHz
TO REAR PANEL
(VIA A27 PCB)
:CIRCUIT
'-+-----� .01 -8
PIN ORV
Q24
QRCUITS '-+-------�
8-1 2
PIN.ORV
Q25
1 2 .4-20
<-+-------0>-
PIN ORV
Q26
20-26.5
<-+------�
PIN ORV
SHAPER CIRCUIT
VOLTAGE
LIMITERS
Q33/Q34
._____________ 26.5-40
PIN ORV
2K- 13
TP8
SAM PLE I HOLD
(Sam e as J2 out)
TP2
\
SAMPLE I HOLD
(To A1 5 J1 )
r i
FP P LS. IN RP PLS IN
(From front (From rear
pane1 q pan BNCJ
2 J3 J4
P0 1
P1
(To A28XA 1 3 via filtercons)
TP3 TP4 TPS TP6 TP1 TP7
PRF CLK PW CLK PG RET GND G
A 13 PULSE GENERATOR PCB PARTS LOCATOR DIAGRAM 2K A L C I PULSE MODULA TION
A13
Control Modulator Drive Signals
PULSE
(To RF Deck)
GENERATO R
2K-14 67XXB MM
0 1 2 3 4
�sv
+ 5V
l(: (o �
+ S-/ ".) I I
I'
A v�
o,
rt'"
"" - Z d B m .I /)I/
< F R ON' AIO J 3 1
61VD
B B
71/ALS/6()
H I N T f' G E N
r5V
.,. . v Cl/
c /41 "
o�
.
q vcc
4:�
Cl! ? o, J
It
.,- 5 V Os 4
8
XA 2 8 A l 3 Pl A 0.: 4
s s
uqF c
I I o,
" •
/)
P& DA T/\ 3 ' '-
8
--+2< � Q,
I/
CUI
10
u 10 q. LO
I j; Q a.. 12
13
I 6ND U I/
D I I 7 6N{J
8
PG CLK
-
---t-1<� ) 41 7'1HC/6�
;!; fl{ ,,c fl/ lV/llS 160
IY
E C7 �a l
X A 2 8 Al3 q
I CtR a.
_,
+ 5VD �sv tla
�� � Cb A 4.
I � 68 CLR.
2.
+ 5 VD
¢ e.
B
I.J i b A
z 8
QH
6/JIJ un
7
F ?6 RE W/VI 71/HC /6 '1 3 >
i -J OI ; _ ::, :
A13 PULSE GENERATOR SCHEMATIC NOTES: S f' f\ R E S 71//.1( 16 '1
1. UNLESS OTHERWISE SPECIFIED, 5 . TEST POINTS ARE DENOTW AS: @ +sv
(µF), 6. TROUBLESHOOTING VOLTAGE AND POWER
RESISTANCES ARE IN OHMS (!l),
PW
+sv
CAPACITANCES ARE IN MICROFARAOS
+sv
LEVELS INDICATED IN BOXES ARE TYPICAL
INDUCTANCES ARE IN MICROHENRIES (µH).
OR NOMINAL LEVELS.
7 't A L">08
G SHEETS OF THIS SCHEMATIC. THE
THIS ASSEMBLY INCLUDE:
SHEET NUMBER AND SOURCE OR CR10, CR12-CR19, 07, 012, 017, 022,
U3, U4, U24, U29-U32, U35-U37
•
1 1
f / B3 ) N(
DESTINATION GRID COORDINATES
APPEAR INSIDE THE FLAG: 2
8. LAST USE�OT USED COMPONENTS ARE:
3. FilTERCONS ARE USED BETWEEN THIS
+s v
REFERENCE DESIGNATORS
PCB EDGE CONNECTOR ANO THE A28
MOTHERBOARD CONNECTOR. EACH LAST USED NOT LISED
SIGNAL PATH .CONNECTION HAS C58 C 18
(TYPICALLY) 1500pF CAPACITANCE
BETWEEN IT AND CHASSIS GROUND.
CR19 RB
DS2 U1
J9 U7
l6
4. GROUND SYMBOLS USED ON THIS ASSEMBLY
U23
SCHEMATIC SET ARE DENOTED AS:
m
P1
H CHASSIS GROUND: 025
ISOLATED GROUND: '\] R68
TP9
U38
VR1 . ',\j z._
67XXB MM
5 6 7 8 9
+5V
+5V
t
1I 16 C3 l
�0.I
-
" ' V,c
lu, � .Do
3
�,.!.�NC. ...2 fi 6,
!). ,_!.",,,c.
l.�3,vc � 8 &ei-J.3Ne z.
D, y...:._
�,.!!-Ne � c a,.i.£.ZNC. I
D,
h..!.'Nc .....:. D Q,._!.I NC. 15
D�
1q
�� � C t.,<1. lltr � 0--- Ds
� LD � c:..,
7... EIYP
-----� ._J1, D1 W �NC
II
� ENr A
r--(; 13
.-!.1> q () 8 '> 1 % �
c:
'1 0 . 9
0 7 STR.
t.NO
P R F C O U N T ER
� +SV
U D.
� !
11.<.
. �
....+-+-...-i........ 3 D1
.i �
L..,_! DL
�M; 3 1':c �..!! ;ve 3 Vu. 0.
• ..!.�NC. '-+--Hl--+-"-1
' D� y 1--'--+-�
A A
._�__.-'1"'1
5 D•
� 4 ..!!NC 4
6/s .J!NC +sv
1.,, .;
.e
s
8 �l--+....;.;/�'-1 Ds
'&. •
c �i.£,,, , "
t:. a..£! NC ..Jl. {),
, ,. -2..
0 �.LL. NC " b GIJ,.!!. ...c.. ,__ 2
15;._
;..;.; .:...j
z D?
�A
n
� cue. fl I P � �fl RIP
wpi'.Nc
1 U3
____
lD L il
�[z �t:t A
t ;,._";
€NP €1H' r-;;- e, Ut5
10 /()
�AIT 7
ov r
urz.
Ut'3 !<I
�t> -lllo II
U14
D 7 'iAL508
?'IFIL SOB
.
+---e
+SV
'
l /h
�
i1A
J!!Nc
a., ,,.!; ..vc
Oc Jl:.N<:-
G.., J..!... Nc
RIP �
8
�f-1< CLR
L()
�10 €'>If'
..____ £NT
U/8
,...t>
..!. t!>NO
6ND
7t{ftLS16'i! 711ALS l 6 D
��H._1 �__7¢8_4"-_L_"'_i_0c.,_1--1---�+-+-------�
/-
I PRF C.. L K
� l � I D E D PW C L K.
- -:'<1Ji l s oa
I 10 M H l
'----- � ll l V I O E D P R F CLK
+SY
IN / OD PW (LK
'kc
6'A j
+.ic (Lfl 2'5 n S ==< �s l..S B
61a
8'.
4
s 2? nS _, �,� \..1 SF.3
.._!_ " i=? 1J
� ..::.'.. \O J '-.. S
"
a. + I - 1 \..JT PLS
z
8 f)� �(),\11., Jc_ '
C U '\
I "'
Q,.,1-"'
.,.--- "':::C
: '-<. \ I:.... ._ t>t_'T" t:...._
a, 11
uzz. � IZ A. «. ----
Oc. ��
Qe, '5
8
(./N IJ Ull Figure 2K-6. A13 Pulse Generator PCB
��J52 NC
6/'/D ._ __;:.
Z .i
,------------'"'! G o. gNC
Qc. 13 NC
Schematic Diagram (Sheet 1 of 4)
6700-D-31913-3 (Rev. B)
7'1HC l6 '1 8 '>
_ _______
ij G'JD
Cl." - N C.
17
'V
2K- 15
0 1 2 3 4
+sv
b l \J I D E D PR F C LK i / '3 .D
t
�sv
t J.10
12. P l!.. \lo'
A
'3
r--t---t D
U38
G. � _.:_ �o
....._L /Cf
__.._.:.
4...i I ' 2
_!!_I>CLRB Q � l--l---+---'Y
'� /C3
11 3 j_?
..J.._
_,____ ,-
...._i!_ ZCo IY
v � 2CI
7�AL':.1"1 ._f_!_ Z e l
....+-
. -t--'- ''1 2C3
�---<1--1---11---+--'-/l
�l AS l
...1...
�"-+-"-_.__."-4 t. BS l
2t
B
Im
� sn
� srz
_
&All>
,a
�
._
_ _
_.._
l'Xlpf'
CIS
�
VVv
!l
..__.__ D
c
�zoo
d JZK. l!V�l/ilb
�
R
PW
PRF ( L IC I I �(.
D/VID/:D c '-IC ' I � (,
PW C U:: l / 'JO
25
D
ns R E SOLU T I O N GE N E RAT I O N + sv
1.,_ , -i-_
.1
7411lS86
v�· �0.1
_
'>------.---
'
'>-!-!------',
Cl'
14 <. 1 01) nS PW I %
/CO
U 30
p.---2.. IC I
__.± IC2
.----2- I C 3
� z c.. o
.::�
!-"----" 2. C f
E 1-----�'.=..2 z c z
+-"----'-. > . 2 c3
1c,----'-ll/
'- A S L
___!_ 74AL >02
F
8Sl
ST /
s rz
"'"'"
Rfs
�" '
lB
v 'l" S V
Z o �s lSd
14:lSIJ6
' ' / �ti
L
74 .0.. L S IS3
25 �s ,�€$ !Yls 8 /'11.:J
-/-
I
· k'
''
....s E.
F
F-''J / ") (,
T14
�0.1
J_ ( 2 1
o.
3
____!__ o.
I
610 4
o,
A s
I
6
QI)
":, E F /A L t)A r,q >------�z� a
(}F
10
II
U33
j!;_NC
�>
Qt.
G /J
1' 5 \/
QH +!>v
� • v 1
l I•
-- +s
''"'
� "'· �---------------- ··----
3
I A
UK QA
Q.
4
5
Q,
Fr:. R TN
0. ,_:.!
b
* NOIE
U9D
2 B /v"C
OF .,_!..: N C..
8-17 U 3 4
�--+�������----- G. 5 U S E. �
H PCS TRI& CLKT s:
5 / "'-'-
-X'l
�"' � N C.
6!,_!} N <!.
U3�
WI
�
II
U31
Z.cl
USE --\
w z.
v,
7
A �
' " ' ��--
:
.....
.� J
. f·r "'"'v·
5 6 7 8 9
L PRF CNTR LD
ff l N G E D G E F L I P FLOP
ti>V
�0.1_ C lfl
'"
� w I K.
� v
"
5
l> Q
> A Q
VZ5
3 'Ne
t!lR
PU LSE S TA R T
FL I P FLOP
P W C N TR
./ S V
0. 1
L LD
9
en
+SV
P U L SE
�
"' � /fl
Pl<
FLI P F L O P
D a
"'"
J5
,.,.. SI/
A a
D-'(,�
REAR P/\N E L
V2 8 SYNC
(FROM R N l)
__
©
P U L S E STOP
F LI p FL 0 p
10
fl :R. Q
'f
N
C
B o p-:8:...._ __J
UZ7
I/
____________
13 74AL'> 74
-1- S V
C2.0 L RF O N
-j i---•
0.1
L RF ON
16
+ SV
LEA D I N G T RA I L I N G
;:� U 3 1 E DGE DELAY E D GE DE L AY R\3
1 "'-
a:z.s
..-sv
icz
Z � 39�
f-'-7-f-+--+----q-'--4
R7 10 L
IC. 3 IY
RJ I
lOO
l Co ::;AMPLe / '-r " '- u
A15I1)
IQ.SK C.'$<0
---� Z1PF�
2-C I ( 7'0
Zc2
741>.L.'$02.
? >----=-----< P L S M 0 N
2. G 3 tr 1
J;
A SL Pl -
f'
ST!
s rz
L 3 1>-fJ D SEL
____i__i 11 1.--- -
H IWT PG EN
SEL
1 PLS
U.....
S /53 -
.__ 6 L ? /.. k ::> '!. P L S SE L
c,;.. 1-c -::i '- P L S
'_
L 2t.. >.. :c '-i P L S S E L
_ -
2K-16 67XXB MM
0 1 2 3 4
us I
- 5 1/
- SI/
D
-5
p:!---1.
+sv
,,,:�:c
E
z PL '5
J 3� . '-------
"'--'
-"' ! u_3_�_T1Dc18
�
____ __
_ _____
5EL ��
6EE NOTE 7)
-- .tiiS o z.
_ /, J V
-f 5 tl
! ll.
!< 3 (, R 3o
F )I. I Z61
-SV
/. zv
C 37
G
- 5V
67XXB MM
i • 7 8 9
-+511
-+511
� O.I C- 3 /
IO OOp F
RZI
03
2.
., 1. 1. V
� /i? / l
C2 9
¢ 0.I M � i) SOI
- 1. 7 1/·
L. 3
15 Jb
B A N D ..L PU L S E C ON T R O L '1 0 D ULAT O R
MOD D R I V E R lf!2 L/ OR I V £
- > II RZ5
·3�
(To BAN D I C ON T R O L
CZ.7
�-'
RI �
I. 7CK
- S il -r s v
0. 1
C3 5 C33
.. s v
{JI/.
� O.I - sv
R2g
IOOOpr �
GB
? ;V t// 1. 'l
� -1. 1v
R. 2 "!
3"
s C/ U tJ
MtUJ sOI
E
� ·'
pl
BA N D 2 PUL S E
. /5
MOD DRIVER J7
C. O N TR OL M O D tJ L A T O R
R33 D R IVE
!< 3 Z.
3 3.L (TO BAN D 2 L: G N T R O ;...
MO D tJ L AIOR )
56. Z.
SI. /
{38
IOOO;F
Figure 2K-6. A13 Pulse Generator PCB
Schematic Diagram (Sheet 3 of 4)
6700-D-31913-3 (Rev. B)
- 5 1/
2K-17/2K- 18
0 1 2 3 4
10
7'1AL.S o z
B
+5V
014-
ZN�I ZZ
_ 5v
D
5
+ 5V
J! s 7
F SI. /
_ 5V B
a 20
ktJ4 / Z Z
+ /. z v
C 53
0. /
G
- SV
67XXB MM
9
./8
(TO
MODULATOR)
B A J.J D 3 C O N T/i.O L
2 1/
cJZ;g
� I.
0. 1
C52. M81) 5 0 /
L6
R55 DA ! VE
a A N O 4 P U LS E
332 ( ro
"\OD DR I V E R
13/\N D 4 (.O,NTROL.
U I 'I
M 13 {J5ol
51. /
c55
Schematic Diagram (Sheet 4 of 4)
6700-D-31913-3 (Rev. B)
51/
0. /
2K-19
TEST POINTS
TP1 GND G TPS DET SHAPER IN PUT
TP2 BUFFERED AM INPUT TP9 DET SHAPER INPUT
TP3 ALC COMBINED LVL TP1 0 RF LVL
TP4 ALC REF TP1 1 ALC CNTRL
TP5 BAND 1 -4 PREAMP TP1 2 L RF UNLVLD
TP6 BAND 0 PREAMP TP13 Not Used @
@ @
TP7 EXT LVL DAG OUT
R209 R203 R197
All test point measureme nts are made ALC SHAPER ALC SHAPER ALC AM
with reference to GND G (TP 1 ) . TP1 ·13 ZERO ADJ TEMP COMP ADJ BANDWIDTH .
2 4 6 8 10 1 2
3 5 7 9 11 1 3
TP0 1
@
R77
(Front) 1 P1 49
J2 BAN
i ADJ A15
SAMPLE/HOLD ALC
(From A1 3J2)
J1
@
R107
BAND 1 -4 BAL
� D cj>BAL J3
MAX 1 I =>-MAX
I
NORM 2
3 I
=>-- NORM
MIN 4 I =>-MIN
P3
1r Jumper
In Position
Figure 2K·7. Al5 ALC PCB
Parts Locator Diagram
6700-0-31915-3 (Rev. K)
2K-20 67XXB MM
0 1 2 3 4
h
+SV
Pl
� 5 2..
Z :· 0. 1
�/ D O
I' /DI
I '�
I z 18
Do IA / ·)/
A
DI 2 4 I A :;_:
12
I � ;:.
/;y
3 / '/
DZ '" ' 1\3
+ 8
D3 IA 'i
5 II 'I
D 4- 2A I Zyl
� 13 7
3
DS ZA 2 2 Yl
D7
IS 5
-fS V
D "' 2/l 3 2Yj
EN•
8 17
U/
2 /l J z y .;
74HCTJ44 ih
B � "'+
!} --+------------------------l--'-1
Z'--I
I
�/--+
/ - -+-----------------------4-�
PA 0 / A
PA I B
/2
PA 2 3 c
ENZB
17 ··· · · -------
A M I N PU T NC
74HCTl38
c
-f 4. 4 V
R.3 l!S
FF AM TL0 74-
'"
CRZ-
2K
- 1 5 V®
IK
oc. i.oo
FD30o
Ui
R2
SHIEi.i )
&04-
I -4,4-1/ R. 4
FP ,.JM 5
iK
RP AM
- 4.-- ---'V I Z
E SHIEL C> f.""J J�---4�---- -1 V
I R
-'? P AM
{K.
Zit:.
!i?l3
+ 15 VA
(R l
17 4
\
/A/ 75/A
S. / V V,.,,: A
+ 4. 4 v 3
11,A
ourA z
F
U9
!Ok
19
R, a
Pl o::
I
Z•
- / S VA
� II)
· -----41�--_.,
10 �
CIO '
G AL C S L O PC: f-
('"'
3..,
2+
1 ___
�
I
I SLOPE
�
/;.
"":'e. 1-= --····
�YJ1-_I
10
Ci/ 3.
A15 ALC SCHEMATIC NOTES:
I '1 ,
__ .
_. 1. UNLESS OTHERWISE SPECIFED,
8
I RESISTANCES ARE IN OHMS (0),
6
CB CAPACITANCES ARE IN MICROFARADS (µF), 4.
I
INDUCTANCES ARE IN MICROHENRIES (µH).
I B3)
DESTINA T10N GRID COORDINATES
67XXB MM APPEAR INSIDE THE FLAG: 2 I
6.
5 6 7 8 9
rSV
Cl
�
t:-dl�
' !.Y T E I / L BY T E. 2.
DI Gi i
.JD O
L OA C A / 0 1', C: B
3 Vt.f.. t;>- 2
I
DO
'
QZ
1J) I 4 s
"
9 l E X T DET Pl<£AM P
8
DATA
7 "
L E" X T P W R. MT R
D3
r"\.
Q3
1tJ4 13 IZ
L E X T D E T C.O M f'
D¥
r"\.
()IJ
r-..
XDS /IJ 15
L P U LS E C O M P
'"
iiB
(> 5 ()5
ID f. 17
L F Jl. D G />\ 1 N
r"\.
/)' Cl•
16
U3
J(>7 If
D7 t',/7
74HC 3 H
/I
CINI:;
rM l !"
+
r��
" L 8AN O 0 D t. T
:Ibl 4 5
l.t,.
BA N D 1 - 'i D E T
2
I
:ItJD 3
/j() Qo
7
'
Qt L EXT DET
"-.
DI QI
"
t:?J L I NT LV L
:Zt> Z
:-... :Ji:, 3
DZ
'
-L E X.T P W R M T R LY L
•
D3
' Ib4 13 12
' Jl)S
o� 124
II/ 15
rLN � 74H�374
� t �V
�
C.3
I
Vu �
0. 1
ilO
' Ib o
M U X AO
3 /)D !90
I
*
Il:.I 4 5
bl 191
tt3 L A M D E T Z ERO
7 "
r"\. U!3 ,
bZ
M U N L E\I LD LED
I
r"\. [()+
D.3
H 5 / H EN
'IJ;S
13
,,,, JI.
, n•
""
()
�(,. �
/'I IS
()5
-1c.
Cll 51 6 1 L V L Ll \ P
17
' J/>7
°"
18 19
D1
II
� C,N{) 74JIC 3 74
()5
rEN
w
l!o
S/I D
} IOO-IOS
'I
...
W R I ST R B
2. /0E X f" R S T RB
Z /o E
A M LEV E L
Ul> 8 A l>I\
c.
Ti07/.
vd. � SlOf'e A
"
3. GROUND SYMBOLS USED ON llllS ASSEMBLY 7. 1110UBLESHOOTING VOLTAGE AND POWER
SCHEMATIC SET ARE DENOTED AS: LEVELS lllDICATED IN BOXES ARE TYPICAL
ISOLATED GROUND :
w w� OR NOlllNAL LEVELS.
�Rn (°§)R107 �R115 ©R158 U18, U20-022, U24, U26, U28, U29,
li12i, Rl28, �. 6700-D-31915-3 (Rev. K)
s �
U32-U39, U41·U44, U46, VR1
C/\3 1 8 3 S U BST f\l>.TE U 'l 5
5. FACTORY·SELECTED COllPONENTS ARE
DENOTED Willi AN ASTERISK
�- P\N
- IO V
C14', C15', C34', C35', R59'
RZCO
�O K
A
+l'�Y@
+ISV@ C. R 8 C. I'\")
t l \.l<N4<0 1 '-l'-l U �2.8
' U \',
C. R ll
B
! 'Ko l';
+ISV@
U1'3 B
DGZ.Oo
AM TH ROUGH D E l
81/N w ?
6AN t.) ! - 4
D
D ET S H A!'E 1' M O N
M U X AO
MUX A l
L D A C .'\ / D M B
R A NGE 01'( STR.B
By T E_ I I L BYT E z
W R I S T RB
x i:- R ST R B
IDO- ID7
E R�O
AM �'"'---"'\/''-
't . Z 2 K
3
R37 IllO
SLOPE Pl
2. K
S L O P E. B /'I MPY(o3 4 K P
___________
PEF E RENCE
R '+ 4
!OK
Jl�N�V(i) I A io U��- - - - - - - -1
.� 3 I
• I
<:.ei.4 I
-IS V@
3.3 pF .t' " S
G
LT I 0 0 7 :
E X T E R N A L A LC A M P I
I
P l - I S V<5)
45 I
rP "1 L C IN
R47
H
if> � l C.
+ Is
' CD
XEF ""
R 3 r)
-------'\1\1\,
K
�- --- ---
+ C 24
r i
• + 5VA
� 10
CRIS
' L S 7 K.
IN 751A
5 6 7 8 9
- IS V@
C. R l 3 CRI I
I N '< .. '< Go 1\.,1'-I� // J.
C R l '-1 Pl
I
g
i> A A LC /t10rJ I
�-------'--l 7 S3A A
1 3 S4
-+------+----ll---+-------_:_: z.� S 1 8
1
�-+--------�;;..; sze
------------
11
+IOV I< +----
538
�-�-1--�lccOc.. S llB l! l C. MON Z.
f-51/ Ell/
�---1---
Ao
�----'-1f,::..J A1 U IS
#AJ/> VG
IS 3
T EC T O R
c zo
R3 / T O. /
,,,, czz
w �
-/O o/ R
-/() o/ R IO
IO I::
-;;z �oY'
- /O V R
-JovR
rl07'f
R 3 1J
IOI/:.
-l>IOV
-t!OV R
A LC LEV EL DA C
ll{) S "I
"135
R E F E R E N C E S U PPLI E S
/()I<
+S"YA
RA N G E OA C
/7
N
....
L6o
,,.
I1>1 13
0/
14Z. ll. {)u1 2.
oz
71>3 //
D3
J/J Y IO
c+ U19
IbS 'I 05
u,' I
[) '
Jb7 7
t: x T <- Vi-
CR33
+sv
A
+
R E L �Y D R I V ER u1L/7�t�---__.��10�-J
N/C 7 NC B
9
.,
I K.
N/C. "I
N
/L �2.:..L�;..:
N ::-
[ -t
-<> -
3 N /C.
Kl
TF 2.. E. - 5 V
B en
BAN D 0 Z H 390�
D E T E C TO R PREAMP
c lt,3
7, /$/C
R 71P
4-9.7 t l SV@
C3/3
'"
t:t3 1
I "'
BANO 0 C£T OP3 7 /�
D +
+
R82
P ? '! -IS V@
D E T EC T O R P R EA M P
"
We
J 3 /0 J�!O
,f88
q,87K_
R 93
7-/SIC.
;::l<.y
.<!!Of.
G 4£', 7
-N5 V(£J
;j;
�I ��55 �-----------
-_
1�
__�0
_
1 _� �
41
B A N D 1 - 't le
k'10"!
~
H B A N D 1 - 'i
3.0 1 c
� '<IJ8
1 48.7
-15 v©
67XXB MM
5 6 7 8 9
!O
• CJ'j
i
0 O,fEAMP
� BAND
I 0 BAL
R 73
/IC
Cfl,I
. {)/
l:l''t§>
----
1 500 P F
. 01
Cl/IZ
BZO p l=' 3300pl" .9 0 . 9 n i
R84 -s I OO p F 270 pF '-10. Z
It:.
i /<100
?50
G i 'i
2N3.,04
/3ANb i- 4 Pf?EA MP
csz
0
/
�
1
BA t-tD
1-4 BAL
f
- -��---4
I
R/03
-+-
'
CS3 1K
. 0/
Q l lo
2rJ3' '/0 (.
Figure 2K-8. A15 ALC PCB
Schematic Diagram (Sheet 3 of 5)
6700-D-31915-3 (Rev. K)
2K-23
0 1 2 3 4
+ I SV c ':lZ. R Z.2.1
R Z ZO
2-IO • I
�u Z�.I
-15V
R 2.Z. 5
5
A R 2- l '.l
5.11 R 2.2.. I 5.11 11. ;
I 0 I ll 3
'-----1 C L N BOO�T Z. 511 '----� C l U 't 't
3 Jl-E.F REG 1-8_....__..._._
SUP OUT 7
.______--'"-J
L- .JR2\/Z\,'t----'=-l El' ll005T
-V R
(OMP
R 2 2. 3
L M 305 1>- H 2. . 3 7 K LM304
B
G. 1 7
VNIOK Rl31 U '+ 3 I
BMJ D 0
PK[ A M P �B�s»-------+--�5'-f-1 _,,_�D'-----t.._---<9'---'V'rv---.
3 5"3
R l �O
'+ 9 9 K
R l 3 2.
c IOK
0. 1 B
VNIOK t 15 V
BA.ND 1 - 'I � ------+---...--=s� .-..�
o_____________
P R E AN � R l 39
5\. I
G
4'1'1 K. RZ09
Ri37
D C.RZ. I
F 0 300
RI 3 8
ICOK
Cl. 1 9
VNIOK
E. )( L �2Zt8�G!>-----+----+--.---1l----<;5Tl
R l 'IO
T lV
R \ 45 G SI.I
E 'l'l� K
- ISV
+ I S \/
�i
R l 'll
1 5 '1 CR2S
i �. 3 K tlOV I OO IC
F 0 300
fJ
Rl'l 7:
IK
L &.I'l l) 0 2
RIH> FD�
D l::I
ec:>----+----=-t
I OO K
1,;
F 3 C. R
7 '+
FO ;
TLO
u.
BA N D '---·""-
---" --' I
t:> ET 7 15K 'HI
U3S �-----------'
L
/
s
/ - '-!
6
L EX T
G
CE: T + IO V
RISS 10
'>-'2-----�
A�-.---_, + _,. 2.
u �sc
...r
T L G 7 1t
I I
-IOV 3
LT 1 0 5 b
N \ <( MTR
- IO V
L l:. 1. T
I/(8
L I hJ T ,,
i_·v L
H l/C
,
1 2.
U 3 5 0>.'.l�'+----
T L 0 7 '+
+
5 6 7 8 9
-IOV
+ l ':> V@
R l 9 CO
I.ZIK
R. 2.0 0
11-2.2.8 3
3 1 f, IK
+ 'I
2 K. T L 0 7 2. �
i.01 C. 11 7 R201
R"7
- -� o v IK
C: S G
93
.
.,
'
Rl98
3 . 0:,7 K.
� ,I - IS@
R.l 3 't
.01
R\35 + I O V R.
5'2.S K RZOf, R Z. 0 1
I K
1 2. 7
L 'l
B . 2. U30 B
R.205
K
C R 2 Z.
µ. H
7
MB0 5-0 1
RZ.0 2.
+IOV IOK "
c:c;.z.
.0 0 1
-15V
�
S H l\ fi:. i'.
RZ.1 1
IK
l'f8 1"14'-l'H.,.
l >J �'"'
C3 2. R Z l 'l
�K. - IOV
IOO K
..
1 00 ? >='
RZ.b R. 1 5 2.
�300 IOK
EXT PW R M T R M O N
R 2. 7 + 1sv @
z co
RIS3
.G I b
VN IOIC
� si:.. : z..
70PF
s
G, Go,
R,1 58
R 2. 1 1:, <-t'i"IK
RISI
-1sv @
'+ . �'3 K
't . 3 3 K
CR35
I N 'f'l'lb
1'.2. 1 7
IOO K
Figure 2K-8. A15 ALC PCB
Schematic Diagram (Sheet 4 of 5)
6700-D-31915-3 (Rev. K)
2K-24 67XXB MM
0 1 2 3 4
CR33
+5V
A / "1 4446
+
0 R I V ER [!/ :!.J
1._ CR.16
R E L 1'.Y 7/ I�
C ---_.-�0 -..J
R57
N/C 7 NC B
9 I K.
N/C. 'I
N /L �2.:J_��NC:
3 :.-04- N /C.
Kl
T F 2. E. - 5 V
B en
Z N 390�
BAN D 0
D E T E C TO R PREAMP
�'3
c
7, /$/C
R7!0
�. 7 t lSV@
C38
'"
�!31
'°
I
13ANO 0 6t:: T OP3 7 /k.
D +
+ RfJZ
P ? "J
E B A N D 1-4
D E T EC T O R P R EA M P
aic
J,jJO
<::J</ <1?5 R 93
f l.6"11!
7. (5/t:.
.<'!06
4;, 7
+15v©
G
B A N D 1 - '+
�I
.'210 '7
��55 ___________-1_ _0
5_�_
__ �;::
� ...
1c
y
~
H B A N 0 1 - 'I
.3.01 1::
� f 08
1 48,7
-/5 V(i)
67XXB MM
5 6 7 8 9
R 70
750
O
i/
+ C3'1
B A-N6 0 PREA MP
<fJ BAND
0 BAL
R 73
I
C� I /IC
. 01
/<100
750
5
2'-134'04
G l '"I
8"'1ND 1- 4 P,t:(EAMP
/0
csz
I 1-4 BAJ..
� BAl'lD �
-+-��·-------�
I
'
Rt03
CS3 ,K
. 0/
2K-23
0 1 2 3 4
L F X D G l'. I N
L L < T 1-"v\ "" �\T P C llv\i'
L E_ X T D t:. 1 [ Qt,,\P
A L P U L S E. r c :'l1 r
LV L L I P
SP ARE S
+sv
+s v
ALC RE F :m R l 57
RF
D
LVL ' ·
- ------------------------------
+sv
----
+ISV
�' l
'5 . 1 1 1"'-
Rl84
2 '-'4
3o1 K
R 1 7 2.
y . 0 2 "' RISO Q2:
E H .S /h FN
7 87
K I 7 .3
R. I 8 I
7 4 A L 'S. 3 8 R 1 1 '.l
I K 7f3'1
R l 8 2..
0. 2. 1
020 Z N 3�06
0 1
2. N 3 '3 0 6
o" M P L E /HO LD
( FP f1 M 1'1 � J 2. )
F
R I 7Y Rl 75
l 1 '-+ � ; oo
R I!
33
R IB �
S I . I
C. 7 7
I
-15v
.
H U N L£ Y L D L E O o:zID-------.�
��"'------------------------------
7 'f A L S !. P
67XXB MM
5 6 7 8 9
+ 1 5 \/ @
DG2.0i�
U3BD
�
r- -- --
--l- --+-
- -- - 5 : 0-1_
1 ::,.,
--+-- _:_: 4 __�
�
-
U 3 BC � -1sv@
+ 1 sv ® 06 Z.O I
+C <> S E X T PWR M T R
1 0�
l-------!------1----'..: II
10 B
U38B
OGZOI
E 'X.. T D 'E.T
r.;
-0 I: 0-
1------1------'-
7
'
---
2 70 p l=
U 3 BA
OGZOI
P U L S E.
RIS � C 70
2 3
.-----'VV\,--_.--1 , O
1 9 . l:; K D . O O Z. 2.
CR"!>O + 1 sv 6)
C R Z.S I N 7 S i l'I
F D 3 00 R l l08
R l f:. 0 R I "\
z. 7 '+
3 U, K
R \ b't Pl
-ISV @ "l . 0 9 K
(). 2 8 R \ 7 0 : 4 'l
Z N 3 '30 '1 ALC C N T R I_
(58 100
0.2.4 4 7 PF
U 't R \ 1;5
'
2. N 'l 3 '3 Z.
.I 750
---�-...f----"o-+-. ��s-+------.--4--=2-:..i
:so
All C N T R. L RLt
us � ' " "'
3o t k. .I 7 50
R. 1 7 1
0. 2.5 CH.'l 100
2 N 'l 3 9Z. 2.N 3 90 t.
s f:. 2 3 0 RI G 7
s 1. 1 +7
T c::if.
10 12.IK
R \ f.9
1=
- ISV
5 pF'
+5 V i c 1 ro
10
-1sv @
0. 2. 1
2. N 330't R\ 5 1
S.llK + I SV +1sv@
-IOVR
Pl
1 i i\5
(\,"v---�
1 3 2- +1sv @ R l 93 7 ;"8
+I 0 V R ---'V'vv-� >-------------4 L !'. F J h LV L D
1 8 . 7 "' LM 3 1 1
R \ '3 2.
.___,__
_. ____• - l ">V @
R. 1 9 5
5I.I ¢ C108 1
- I SV @ LM31 1 - ISV
2K-25
A29 REAR PANEL INTERFACE
(As viewed from bottom of instrument)
J10 J
ATTEN UATOR DRIVE J11 ATTENUAT
( To Optional Attenuator) (Optional) (Opt
\ /
I I I I
1�1 1�1
il
P01
J1
BAND 0 and/or BAND 1
MOD DRVR
� P1
J7
FILTEA DRIVE
(To A28J 1 4 (Used in all units with
J2
via ribbon cable) a 2-8 GHz band)
BAND 2
MOD DRVR To RF Deck J6 J!
J3 Control Modulators SWITCH DRIVE S.
BAND 3 and/or BAND 5
( Used in all (l
MOD DRVR
m ulti-band units)
J4
JS
BAND 4
(Used i n all units
MOD DRVR
Frequency Doub
A29 REAR PANEL INTERFACE PCB PARTS LOCATOR DIAGRAM 2K ALC/ PULSE MODULATION
A29
REAR PANEL
INTERFACE
J12 (Bottom Side)
�TOR DRIVER
ptional)
I
P2 P3
(To A28J1 9 (To A28J23
via ribbon cable) via ribbon cable)
J9
SAMPLER SWITCH DRIVE
(Used in all multi-band units)
s with
J�ler)
2K-26 67XXB MM
0 1 2 3 4
C50
�
1/AB
�
00-07 +5v @
20 0 .1
jj
A " DO 03 vcc 02 D
01
DO GO
" 04
Dl Gl
05
" D2 07 06
" D3 OB D2 02
09
D3 03
" 04 13 D4
G4
12
" 05 14 D5 15
�
05
D6 17 16
D6 G6
" D7 18 19
11
D7 G7
LATCH 1 STRB l /FB >
UB
N
E HC374
B I
GND +5V @ c w H OR I Z D A C
110
� 1 00
f20 08
VCC VRF
07 09
/
DO FBK
101 06
/
T°
Dl � 52
102 05 UlO
/ D2
I03 04
/
D3 1
I04 16
D4
11
/ ID5 15
/ D5 02�
I06 14 DT1
/ D6 C A 1 2 '* �l l A 01
107 13
c / D7 1 2 MBD50 1 0 3v,
� BYT OT2 TLD74
[UTI)--··
Ii
02 W1 AG
WA l STAB
RAMP OUT STRB 1 1T8
�
17
W2
XFR
� CSL
� GND
O A C 1 232
Iv
f P l -2
O- lOV RAMP
I
�� V / GH z S L O P E D A C
D + 5v ®
o
+5v @
os
1
D f20 ,
!'-.. 100
VCC VCC VRF
DO 03 02 IOO 07 09
101"V
DO GO DO FBK
� Dl 04 05 IO! 06
1 02"/
Dl G1 D1 �10
� D2 07 06 I02 05 U13
!'-.. 103"/
02 02 02
D3 08 09 I03 04
104"/ 16 D3
D3 G3 BOpF
� 04 13 12 I04
!'-.. 105"/
04 G4 04
D5 14 15 105 15 11 13
1 0 6 "v
T
�
D5 G5 05 OT!
" D6 17 16 106 14
107"/
D6 G6 06 � 14
E 07 18 19 107 13 C A 1 4 '* -
+
"v
M8D5 0 1
19
07 G7 D7 1 2 1 2
>
11 BYT OT2 TL074
100-107 STAB 1/FB
-cJ2 W!
Ii
U9
N AG
E HC374 1 8-
GNO W2
I
110 �
01
- XFR
� � CSL
GND
OAC 1232
V/GHZ W IDTH v
OAC STAB 1 /FB
F { P!-1
+ l O V REF
V / GH z O F F S E T D A C
+5V@
f20 08
VCC VAF
07
1 00 FBK 09
I/
00
101 06
v �16
01
102 05 U15
v 04
02
103
/ 104 16 03 BOpF
v
04
G
I05 15
v
�
D5 1 1 T
106 14 OT!
/ 1 07 13
D6 CA 1 6 Ul6 A
01
/
D7 MBD50 1'*
''
�
1 9 BYT OT2
°'
'--02 Wl AG
V/GHz OFFSET 1 /F8
r-3
17
W2
XFA + '''''
STAB DAC
�
� GND
CSL
D A C 1 2 32
H
\..
67XXB MM
5 6 7 8 9
P3
,.._�------------------------------------..�------'-'�'-=�"lli'v--, 1�1:--7 L ALT 1
�--------------------------------------l-�o------"�'--*-"'""-/\/l,, 6----7 L ALT 2
- l\,--T-'
DAC A/DAC B
�----1----+---l---..--'-""-='.__._,"""-/\/l,,l\,-"--r--'"� SPARE OUT 1
._----+---+---l--1---..':�'--=-'=-=--"lli'v-"--.-'--"-7
,. SPARE OUT 2
SPARE OUT 3
- 10V REF
n
D
n n ,..
D D "
fl)
*
+ 15VA
HCTOO
R41
01 16 4B . 7 1N751A X 5
U 12A
+ 15VA @
+15VA @
06 04
�
�=·-�I
07
DG201
">'-
"'--
- --<---+---------..----J'\/V\�--+----
R25
� 10V HORIZ OUT
7
03 R24 100
5 . 1 1K OB
C9 CR13
� - 1 5VA @ 1N759A
- 15VA @ 12V
-01
-15VA 07
15 1N4446
4 2 . 2K
5 . 1 1K C11 CR56
+24VG . 00 1
R27 ��g 42 . 2K
� :
10K
R2B
10K R O
>-'-'
06'---------+-�vV'
Jv---+--� 8--7 V /GHz OUT
100 I
R36 CR 1 5
10K 1N4749
R37
10K
+ 1 5VA
R35
10K -5V
R34
215K 07
�
-·� 1 11
P1
- -'-�>---�----
">'-"'-- ------------+----lf-"-"
-7 ALC S LOPE
- 1 5VA
+5V @
09
12 "°"7
v UDG201
12C
13
10 �
-0
11
Figure 2K·IO. A29 Rear Panel Interface PCB
Schematic Diagram (Sheet 2 of 5)
6700-D-31829-3 (Rev. J)
SPARE GATES
2K-27
0 1 2 3 4
+ 1 5VA
;:,
"' lDO 03
04 DO
20 "",�
1N75 1
ClO 02
�o
� 101 Dl Cl l 05
vcc
� I07 D7 Cl7 �
SELECT 1/GB 11
STAB r 01 U37
HC374
MOD
GND
>
I 10
EN
+ 1 5VA @
'7
-10V REF 2/89
.>R9B : R99
B25 <, B25
c
17 1 04 1N4446
VCCVRE
['.__ IDO 1 4 DO RFA 03
['.__ ID1 1 3 D l U3B C24
� 1N4446• f O . l CR5 1 't Cl21
2N290
['.._ ID2 1 2 D2 AD752B CR50
"' ID3 1 1 D3 OUTA 02 �BPF 06 +
['.._ ID4 10 D4 �0_7__.__ --+-j Cl20
- 2N2222
"- I D5 09 D5 RFB � NC 05�L072..>-
['.__ ID6 OB D6
I D7 07 D7 ouTB f-1_.> R95 9 . 53K
DAC A /DAC B � 06 DAC
D
+15VA
'
� R93
51 1
� 25
•
�
05 1B
j r2B
'.> R 102 _i_:
3 . 01K 0 1
t CR52
1N755A
7 . 5V
Cl22
2N222
10
E
I
·
® <l- +
._Q£� OB 0 1
U39 A - 15VA
�
r·
� ��OO � U40 0 1 R 126 R 1 2B >
I > 1 . 5K
R 122 OB y 1 . 5K 02"-- .
+ 02 06 R107
�
,__1 -...
R 123 100 � X
C56
__ I� +U 43 LT1056 VY
vv
12 14 100 Cl23
100 R124 j - X MC1 495- V 4
- • y
1 1
I _ 0 2 2__
r- R_
l•l7_ L--1--+-+---"\f vv'"-___J 2N22 18
03 1 3 o7L_ > R 130
A v
+ 1 5VA 201<
fl
7 . 32K
100
j � i �� > > 3 2 ���22A R.133
�� �K
1
IR11B 1 . SK
"::��
�i
G
.vv
C57 4 R 106
I ...
51 . 1
-'1..,
- 15VA
I
'
H
5 6 7 8 9
VN10K
Q24 Jl
2 . 0 1-8
PIN ORV
I
SHIELD
s
VN10K
Q25
r J2
SHIELD
2 8-12
PIN ORV
I
SHIELD
0 s
l07
VN10K
Q26
r J3
SHIELD
2 1 2 . 4-20
PIN ORV
R 100
I
SHIELD
0 s
1K
!22 VN10K
Q27
r J4
SHIELD
2 20-26 . 5
PIN ORV
I
SHIELD
0 s I
SHIELD
FD300
R167
F + 1 5VA
4 . 99K Q34
+ 1 5VA 2N3906
C53 - 1 5VA
08 +15VA 39pF + 15VA
U32B R169 CR60
DG20 1 1 1 . 5K
1N4446
Rl 1 0 R 163
133K J5
240 26 . 5-40
1W '--�__.��---�
1 �����������1 ---=
2��
PIN ORV
-15VA SHIELD
SHIELD
- 15VA
R 162
1 2 . lK C34
Figure2K·ll. A29 Rear Panel Interface PCB
�
Schematic Diagram (Sheet 5 of 5)
9pF
6700-D-31829-3 (Rev. J)
2K-28 67XXB MM
2L-RF MICROWAVE DECK 2L·2 RF MICROWAVE DECK ASSEMBLY,
OVERALL DESCRIPTION
Circuit Description Para. 2L-6 2L-6 During the sweep mode in multiband models, fre
quency bandswitching occurs at specific switch
Block Diagram Fig. 2L-1 2L-6
points. The bandswitch points occur at 2.0 GHz,
8.0 GHz, 12.4 GHz, 18.0 GHz, and 26.5 GHz. At
euch bandswitch point, the YIG-tuned oscillator that
was being swept is phase-locked to determine the
frequency error, if any, and then turned off. The
67XXB MM 2L-1
RF MICROWAVE DECK ASSEMBLY,
OVERALL DESCRIPTION 2L RF MICROWAVE DECK
67098/67098-40 wmmrnim;m��m1�
61200161200-40 i�l%1tlttfilff&W&
67408
67458
67478/67478-20
67538/67538·10
67598/67598-10
67608
67638
67698
67728
YIG-tuned oscillator for the next frequency band to to reduce FM noise close to the carrier. In the
be swept is then turned on and phase-locked. sweep mode, the main tuning coil current tunes
the oscillator through the swept frequency range.
The RF components common to all frequency bands Phase-locking to fine adjust the oscillator's output
and found in all models are described in the follow frequency is only done at the bottom and top of
ing paragraphs. The RF components peculiar to the sweep ramp or on both sides of each band
specific frequency bands and/or are found only in switch point. FM is also obtained by introducing
certain models described in later paragraphs as part an externally applied control voltage into the
of the description of that particular frequency band. oscillator's FM tuning coil control path.
• Isolators - The isolators prevent the reflection of
Common RF components that make up the RF RF energy back into the YIG-tuned oscillators,
which can cause frequency pulling. They pass for
microwave deck are:
ward wave RF energy with only 0.5 to 1 dB of
• YIG-tuned Oscillators - The YIG-tuned oscil attenuation; however, they attenuate reflected RF
lators generate high-power RF output signals that
energy by 17 to 20 dB. Dual isolators attenuate
have low broadband noise and low spurious con reflected RF energy by up to 40 dB.
tent. The oscillators are driven by the FM and
• Control Modulators -The control modulators pro
main tuning coil currents and bias voltage from
vide variable attenuation to control the RF power
the YIG Driver PCBs. During the CW mode, the
output of the YIG-tuned oscillators. A portion of
main tuning coil current tunes the oscillator to
the RF input to the modulators is coupled out
within a few megahertz of the final output fre
prior to modulation for use by the YIG Loop
quency. The phase-lock circuitry of the YIG Loop
phase-lock circuitry. The level modulation driver
then fine adjusts the oscillator's FM tuning coil
current input is received from the A29 Rear Panel
current to make the output frequency exact and
2L-2 67XXB MM
2L RF MICROWAVE DECK FREQUENCY BANDS 2 THRU 4, CIRCUIT DESCRIPTION
Interface PCB where it is developed from the ALC 2L-3.1 Frequency Control and FM
control signal. Pulse modulation current i s Modulation
received from the A 1 3 Pulse Generator PCB. The
The appropriate YIG Driver PCB receives a de
control modulators output modulated RF signals.
tuning voltage (in CW mode) or a tuning ramp sweep
Amplifiers - The RF amplifiers are used to in
voltage (in sweep mode) along with a +lOV reference
•
causes the RF microwave deck frequency bands 2, 3, oscillator, the control modulator has two other in
or 4 to generate the requested RF signals as follows. puts - the ALC input and the pulse input. The ALC
input provides driver current to the PIN diodes that
control the power level of the RF output signals from
the YIG-t u n e d o s c i l l ator. This level control
modulator driver current is received from the A29
PCB, where it is derived from the A 15 PCB's ALC
control signal input. The PIN diodes controlling the
power level act as variable resistors. They have zero
67XXB MM 2L-3
FREQUENCY BANDS 0 AND 1, CIRCUIT DESCRIPTION 2L RF MICROWAVE DECK
ohms resistance at full drive current, reflecting all The directional coupler also has a built-in thermis
the RF back towards the YIG-tuned oscillator. tor which outputs a resistance representing the
Amplitude modulation of the RF output signal is coupler's temperature. This resistance is converted
accomplished by varying the ALC input driver cur to a voltage by the A15 PCB and monitored by the
rent with the external modulation signal. Al 7 PCB's DVM circuit. As the ambient temperature
changes, the A23 Microprocessor compensates for
the output level to provide a stable RF-output-vs
2L-3.3 Pulse Modulation
temperature.
The pulse input provides driver current to the PIN
diodes which control pulse modulation of the RF
2L·4 FREQUENCY BANDS 0 AND 1,
output signal. The pulse modulation driver current CIB.CUIT DESCRIPTION
is received from the A13 Pulse Generator PCB. The
PIN diodes controlling pulse modulation act as Since the RF microwave deck frequency band 0 (0.01
switches rather than variable resistors - they are to 2 GHz) and band 1 (2 to 8.4 GHz) RF signals are
either full-on or full-off. The level modulator PIN generated using the same YIG-tuned oscillator, their
diodes are isolated from the pulse modulation PIN circuit descriptions are combined. Refer to the block
diodes by a "T'' filter consisting of two capacitors and diagram in Figure 2L-2 for the following description.
an inductor. This prevents the high-speed video pul
ses for the pulse modulation PIN diodes from Selecting a frequency or band of frequencies to be
modulating the level control modulator PIN diodes. swept within the range of frequency band 1 causes
the YIG-tuned oscillator to generate 2 to 8.4 GHz RF
signals. Selecting a frequency or band of frequencies
to be swept within the range of frequency band O
2L-3.4 Output Control
The modulated RF output signal is sent through a causes the YIG-tuned oscillator to generate 6.01 to
low-pass tilter to the Main RF MUX PIN Switch. The 8.0 GHz RF signals. The 6.01 to 8.0 GHz RF signals
low-pass tilter provides bandpass filtering of the RF are then down converted to produce 0.01 to 2 GHz
signal to reduce harmonic emissions. The Main RF RF signals.
MUX PIN Switch multiplexes the various control
modulator outputs into a common output port. Drive The YIG-tuned oscillator's output RF signal is sent
current for the switch is received from the PIN through a 10 dB attenuator to the control modulator.
switch drivers located on the A29 PCB. The switch This control modulator operates the same as the
input ports supporting frequency bands 2 through 4 other control modulators; the only difference is that
(8 to 26.5 GHz) have additional high-pass filtering it has an additional RF output for the down con
for the video pulses from the control modulator. The verter. Refer to paragraphs 2L-3.1, 2L-3.2, and
Main RF MUX PIN Switch is not installed in units 2L-3.3 for descriptions of frequency and power level
having only one oscillator; a separate video filter is control and AM, FM, and pulse modulation opera
installed in these units. tion.
The modulated RF signal output from the Main RF The 0.01 to 2 GHz Down Converter contains a
MUX PIN Switch is sent to the Directional Coupler 6 GHz voltage-controlled oscillator (VCO) that is
for transfer to the RF OUTPUT connector. A portion phase-locked to the 500 MHz reference oscillator
of the RF output is detected and coupled out as an through a sampling phase detector. The 6 GHz
input to the ALC loop. The detected RF sample is VCO's phase-lock condition is monitored by the A23
routed to the A15 ALC PCB. In the ALC loop, the RF Microprocessor via the Al 7 PCB DVM circuit. The
sample is compared with a reference voltage that 6 GHz VCO is on at all times; however, the down
represents the desired RF power output level. If the converter amplifier is powered on by the A18 YIG
two voltages do not match, an error correction signal Driver PCB only when the 0.01 to 2 GHz band is
is fed from the A15 PCB to the PIN modulator driver selected. Additionally, when frequency band 0 is not
circuit on the A29 PCB. The resulting modulator selected, a PIN switch at the down converter RF
driver current to the control modulator causes the input is activated. This prevents the 6 GHz VCO
level control modulator diodes to adjust the RF signal fr o m leaking back through the control
power level output. modulator and showing up as a spur in the 3.5 to
2L-4 67XXB MM
2L RF MICROWAVE DECK FREQUENCY BAND 5, CIRCUIT DESCRIPTION
the switch is received from the PIN switch driver on tor. When operating in the frequency range of 2 to
the A29 PCB. 8.4 GHz, the portion of the RF output detected and
coupled out to the A15 ALC PCB provides an input
During frequency band 0 operation, the modulated to the ALC loop . Refer to paragraph 2L-3.5 for a
6.01 to 8.0 GHz RF signal output from the control description of power level detection and ALC loop
modulator is sent to the 0.01 to 2 GHz Down Con operation.
verter. The modulated 6.01 to 8.0 GHz RF signal is
then mixed with the 6.0 GHz VCO signal resulting 2L-5 FREQUENCY BAND 5, CffiCUIT
in a modulated 0.01 to 2 GHz RF signal. The resul DESCRIPTION
tant RF signal is sent through a 2 GHz Low-Pass
Filter, then amplified and output to the Switched Frequency band 5 (26.5 to 40 GHz) RF signals are
Filter. A portion of the RF output is detected and produced by frequency doubling the band 3 (12.4 to
coupled out as an input to the ALC loop. Refer to 20 GHz) YIG-tuned oscillator's RF signal output.
paragraph 21-3.5 for a description of power level Refer to the block diagram in Figure 2L-2 during the
detection and ALC loop operation. following description.
67XXB MM 2L-5
FREQUENCY BAND 6, CIRCUrr DESCRIPTION 2L RF MICROWAVE DECK
FM
DRIVER SAMPLER
INP UT
12.4 20 GHz
Lr
•
VIG
OSCI LLATOR
---t-=-FM_.,
= ., 13.33 - 20 GHz
RF INPUT r::l_.._40 - 60 GHz
�
VIG TUNE
DRIVER BIAS RF OUTPUT
DUAL
ISOLATOR
CONTROL
MODULATOR
TUNING
RAMP ALC PULSE
INPUT INPUT INPUT
2L-6 67XXB MM
2L RF MICROWAVE DECK RF MICROWAVE DECK ASSEMBLY, TROUBLESHOOT/NG
40 to 60 GHz. The modulated RF signal output from 2L-7 RF MICROWAVE DECK ASSEMBLY,
the frequency trip ler is sent via the W R - 19 TROUBLESHOOTING
waveguide to the RF OUTPUT connector. The fre
Refer to the troubleshooting information located in
quency tripler and RF OUTPUT connectors are both
the front portion of Section 2-System Description
WR-19 waveguides (UG-383/U flange).
and Troubleshooting. This information provides a
list of error codes that may be displayed as a result
An external power level detector must be used with
of failures of components on the RF microwave deck
the model 6772B synthesizer to obtain an RF sample
assembly and probable causes of the failures.
for the ALC loop. Refer to Section 2K-ALC/Pulse
Modulation for a description of external ALC level
ing. 2L-8 RF MICROWAVE DECK ASSEMBLY,
SERVICE SHEETS
67XXB MM 2L-7/2L-8
2L RF MICROWAVE DECK
SAMPLER
MUX
PIN SWITCH
DPDT ATI
I o PIN SWITCH
13.25 20 GHz•
P UL SE
SWITCH CONTROL
INPUT
�
VIG OSCILLATOR
18 - 26.5
FM Ill>
GHz
Tune
...
Bias
(Required
VIG OSCILLATOR with
12.4 - 20 GHz Frequency
FM ... Doubler) 1
Tune Ill>
1-1-��i----11....i �-----"���+---'r -...... ...,__-"'.'.,..1����
B ias l/
I
HIGH POWER
VIG OSCILLATOR AMPLIFIERS
I
FM
8·12.4 GHz
Ill> (Optional) I
Tune Ill>
...
........ .__
_.._ _
_ __ i-.--+---1-+---f ...... ....,.__�) __ ________
__
Bias l/
DOWN CONVERTER
...__.,__,
BAND •
INPUT
�
CONTROL
MODULATORS BAND 0 0.01 • 2 GHz
67XXBMM
RF MICROWAVE DECK BLOCK DIAGRAM
Ill
F��u�����:l s) R ����� MAIN
T
26.5GHzLPF
��������-+-��---. 20GHzLPF
\
I I
(-
ALC
INPUT I 8GHzLPF I
I I I
l':ll'''''''''''''l'''''''''''i''''''''''''''''''l'''''''''''''''''''i"'''''''''i '''''''' ''''''''m'''''l'''ll''''''''''''''''''''ll'''';;,,,,,,,,,,,,,,,, , 'ri''''''''r:t:
1
BAND 4 (18 • 26.5GHz)
�:!:
�1}::::::::::::::::::::::::::::::::::::::::::::::::::::::::::: : :::::::::::::::::::::;::::::::::::::::: :::;:::::::::::::::::::::-::":::":!:: : : ::,:::::::::-::;:::::::::::::::::;:;: :;::s�*:
I
I
I
BAND 3 (12A • 20GHz)
I
I
I
I
I
BAND 2 (8 12.4 GHz)
I
•
MAIN I
RF OUTPUT
MUXPIN
I
SWITCH I
26.5 GHz
Models I
26.5 GHz LPF 0 I
20GHzLPF
I DIRECTIONAL
110 dB
\ COUPLER
STEP
RF OUTPUT
SWITCHED ALTEA
ATTENUATOR
13 GHzLPF 0.01·40GHz
(Optional )
)
8 GHzLPF
0.01 • 8.0GHz
LEVEL
CONTROL
2L-9
PARTS LOCATOR DIAGRAM (CONNECTOR LISTING) 2L RF MICROWAVE DECK
2L-10 67XXB MM
2L RF MICROWAVE DECK
Thermal
Shutdown
Switch
Switched Filter
(All Models Having Band 1)
67XXBMM
PARTS LOCATOR DIAGRAM (TOP VIEW)
NOTES:
) )
1. This diagram reflects a typical 6759A
having 5 frequency bands
18-26.5 GHz Amplifier
r
Band O- .01 to 2 GHz
18 - 26.5 GHz Control Modulator
Ba003 Band4 Band 1 -2 to 8.4 GHz
1lator 18-26.5 GHz Dual Isolator
Band 2-8 to 12.4 GHz
18-26.5 GHz YIG Oscillator
Band 3-12 .4 to 20 GHz
Band 4- 18 to 26.5 GHz
}
2. Refer to Section 5 Parts Lists for specific
microcircuit and cable part number information.
2 - 8.4 GHz Control Modulator
2 - 8.4 GHz Amplifier
Band 1
�-- 1 O dB Attenuator
"
-i=-,
11------4 ---; -.. J""
:I-�,
·
,.
""._
" __ RF OUTPUT
_11-----_.-r..'.J Connector
2L-ll
Location of
Optional Attenuator
,... - -- - --,
I
1
I
I
I
I
I
I I
I I
I I
I
L ---- ---- -I jJ
-;-;
1,-r
1 1
L-I
I 1 I
I
RF OUTPUT-----
-rr·,
� � "--....1...--=
..
��r
1.=:=:::::::==� e �- - -tc::.
Level Detector
Location of LevE
.
in Instruments with Op
PARTS LOCATOR DIAGRAM (BOTTOM VIEW) 2L RF MICROWAVE DECK
A30
========��;;;r=���t:::==�;;;;;::;;;�(�·
0 0
I I
11
I I
I I
I I
'-�=--=-"
I\
\ �-;----'/
h t'-..r----
\ \
�l 0 l_ 'r---f.il'l
L-�
- - - - - ..J ,_ - - --- - -- J
2L-12 67XXBMM
2M-MOTHERBOARD/INTERCONNECTIONS A fifth method-rigid coaxial cable-is used to inter
A28 PCB, INTERCONNECTION CABLES connect the components located on the microwave
deck. Refer to Section 2L.
67XXBMM 2M-1
A28 MOTHERBOARD PCB TROUBLESHOOTING 2M MOTHERBOARD/INTERCONNECTIONS
Refer to the su mmary diagram located at the bottom Many of the synthesizer' s front and rear panel
of sheet 1 of the A28 PCB schematic set. This input/output signals are rou ted throu gh wi ring har
simplified schematic diagram shows the conne ction nesses and ribbon cables to connectors on the
of the +30V u nregulated de to the +24V regul ator Motherb oard where they are distribu ted to the
circui t located on the A22 PCB. I t also shows the variou s PCB circu its via Motherboard circui t paths.
distribu tion of the +24V regulated de to the 10 MH z Most signals that interface with A29 PCB circuits
Reference O scillator assembly, the LINE switch, the are also routed via Motherboard circuit paths/ con
LINE switch relay, and the de fan driver circuits. nectors and ribbon cables to the A29 PCB.
An overall block diagram and detailed descriptions 2M·3.4 RF Casting Coaxial Cables
of the operation of all synthesizer power su pply cir Figure 2M-4 shows the coaxial cable interconnec
cu its, including those located on the A28 Mother tions that are used to distribute RF signals between
b oard PCB, are contained in S ection 2A-Power the RF Casting PCBs, the RF Microwave D eck com
Supply. ponents, an d the synthesizer's front/rear panel R F
and pu lse connections.
2M-3.2 Filtercons
2M-3.5 RF Microwave Deck Interconnections
Filtercons are pi-fi lter circuit elements that are u sed The interconnections of the RF Microwave D eck
to connect all control signal and power supply circu it components are fu lly documented in S ection 2L.
paths from the A28 Mo therboard PCB to the A3-A13 Figure 2L -2, the parts locator diagram, shows the
PCBs, located in the RF Casting, and the Al/A2 semi-rigid coaxial interconnections between the R F
PCBs, mounted o n the front panel casting. The loca Microwave Deck components. In addition, i t shows
tions of the A3-A13 filtercon s are shown in Figur e the variou s wiring harnesses, ribbon cables, and
2M-5 (page 2M-6). A typical fi ltercon application is coaxial cab les connecting the RF Microwave D eck
shown in Figure 2M- 1. components to the A28 PCB, the A29 PCB, and the
PCBs located in the RF Casting.
SCHEMATICBEpe;sENIAJ!ON
I
-
PART OF AS I
SERIAL 110 PCB A11
! .:,�r.t:. !
I I
J.f.'�t�.
I
I
I
I SIGNAL �
DESIGNATOR l ·j �
FILTEBCON I
.·.··:�:�;:�;:�:;i:i:i:j;:�:····· SYMBOL I
Figure 2M-1. Typical Filtercon Connection Between Motherboard Circuit Path and PCB Input
2M-2 67XXB MM
2M MOTHERBOARD I INTERCONNECTIONS
.. ...
PCB INTERCONNECT
FRO
PANE
..
l ...
CONNECTIONS VIA ALTERCONS
WIRE\RIBBON CABLES
R
.. / ... A1 A2
10MHz
REF
osc
COAXIAL CABLES
Q R
Rf------1
OUT
67XXB MM
BLOCK DIAGRAM OF 67XXB INTERCONNECTS
REAR
PANEL
1 I
;R A26 .,.
,
- AC PWRIN
A22 A23, A24 A25 LINE
13 A15 -A21
PWR CPU/ PWR ALTER
lNG MICROWAVE DECK �
REG GPIB SUP PCB
> CONTROL PCBS
PCB PCB II
PCB
IR
•l '. •• •• .. 4 S1,
F1,F2,
.. '. •• �r •• T1
....
;R-
I
;R ,,..... ...
}----{
�
"".: I -'-<... ...
REAR PANEL
,,..... �
A28 MOTHERBOARD PCB .!>.../..
"".:
....
: BNC CONNECTORS
t
II
v R R
R
a ·� ,,. ••
1,
:r
It 11
� I R I R �D IR A'Z'l
. •r AUX 1/0 � AUX 1/0
A29 REAR PANEL INTERFACE PCB
...
I PCB
1R GPIB
" I ...
�
�
IR
,.....
., -'-<...
..
- POWER METER
v
MICROWAVE DECK I R
... DC
-
FAN
2M-3
FRONT PANEL RF CASTING MICI
XA3-XA14
10 MHz
REFERENCE I------'
OSCILLATOR
FM
INPUT
I
_____
_J
I .-------+t
DOWN SWITCH
CONVERTER# FILTER
1 I
.._
__
-- - - - -
....--....__...,
#Units with 0.01-2GHz only
I I
DIRECTIONAL MAIN
STEP
RF COUPLER/LEVEL MULTIPLEX
I I
ATTENUATOR*
OUTPUT DETECTOR SWITCH
·---�--+----
0ptional
1 _1 I
• ___________
- - - 1 _f_:=-_:=-_:=-_:=-...=-.... I
r-
I �----�---
.=- ..
.=- ..
.=- ..
------ �
.=- ...=-
.=- _:=- _
...._
__ _
__
_
__.
_
j
: CON
L _j LJ �==== == _J
:. J
FREQUENCY DOUBLER DOUBLER -
AMPLIFIER/MODULATOR l MULTIPLEX/SWITCH*'•_r-- _ .
L _________ ____
POWER
REGULATOR
J DIGITAL POWER
:ROWAVE DECK CONTROL �CONTROL SUPPLY REAR PANEL
XA23,
XA15 - XA21 XA22
XA24
SAMPLER
l/F
SAMPLER
MULTIPLEX
BAND 3 1-+-----1 SWITCH
POWER
AMPLIFIER
-1 AND41�-----<
���-B
� �---,.---�
tTROL MODULATORS OSCILLATORS
_______________ _J
2M-4 67XXBMM
2M MOTHERBOARD I INTERCONNECTIONS
A4 J2 A9
J1
J2
JJ2
J2
a
J3
...��
J2
-----·--- ·· · -· - - - · · - --··----·----· ·-----·--··---
PART OF J3
MICROWAVE DOWN
DECK CONVERTER*
*0.01 TO 2 GHz
MODELS ONLY
10MHz
REFERENCE
A31 POWER OSCILLATOR
-r
AM PLIFIER/
� ------------------------·-·------------
MULT PLIER
l ___ ____________
67XXB MM
RF CASTING COAXIAL
CABLE INTERCONNECT DIAGRAM
A 11 A13 A 14
J1
.. -+--�1'.J
�....- BAND 1
CONTROL
MODULATORS
J3
a
\l/F TEST PORT
J2 Hi--... HIGH
E:..2Jl...----....--....------t4 RES
J4 INPUT
Vl-n---... 10 MHz
--�....................IP-1 REF REAR
OUTPUT PANEL
]
lH fl---.-.r-o 10 MHz
..............,_�" REF
INPUT
1-----1 ...- ,
l30SAMPLER
_J SAMPLER � __ (IV )
MUTIPLEX
l/F AMP
I \ ...._ /
SWITC H I
L - - - - - _J VIG OSCILLATOR
2M-5
A28 MOTHERBOARD
(As viewed from top of instrument)
..
..
..
..
..
..
..
,:
::1
::!ct:>
•• x
..
j
••' <(
..
..
.1
6· '
•
..
..
'I
..
..
.. .. .. ..
.. .. .. ..
.. .. .. ..
.. .. .. ..
.. .. .. ..
.. .. .. ..
.. .. .. .. ..
.. .. .. .. ..
.
)(
.. .. .. ..
)(
.. .
.. .. ..
.. ..
.. .. .. ..
•• <I> .. .... .. ..
..
)(
• :: � .. - .. - .. ..
•• <( ..
:: ct :: ct .. .. "'
• .. :: x .. ..
.. .. .. •• N N
• .. .. .. •• N :: <(
•• <( ••
• <t .. .. ..
.. .. ..
Ii<
••x
..
..
..
..
..
..
:: >(
..
::
..
.. ..
.. .. .. ..
•• .. .. .. ..
• ..
'
.. ..
·• .. ..
• .. ..
.. ..
-- � .. •• .. .. .. ..
___ ,...
-- :t.14
J5 n.9
I ...
..
.
.. ..
..
..
..
--
__ _. .... .. .. .. ..
.. .. .. ..
-- 1.,J-9 .. .. .. ..
J7 :: .. .. ..
Cl) •• 0 ..
:: �
�
.. -
•• <(
•• x :: <C
•• N
:: ct
:: �
-- -,
--
re .. •• x •• x
.. .. .. :: >(
.. .. .. ..
Jit"U"' .. .. .. ..
.. .. .. ..
::n;;
-- _._,....
..
..
..
..
..
..
..
..
• J9 .. ..
•
•
,' ........�, ,
" "'
:� J19
•• J14
••
� ----
*1)'j
•••••••••
• ---
•• er=-=-, ' .........
'I
I I 1 I
/
/
JI 7
..
••
••
••
..
..
••
Fan Power
NOTES: Supply Components
1. Filtercons are designated as: (As viewed from
........ .<:. bottom of instrument)
Each signal path connection
has (typically) 1500 pF capacitance
sbetween it and chassis ground.
2. J1-9, J14, J19, J23-25, and J27 are
mounted on the bottom side of the A28 PCB.
A28 MOTHERBOARD PCB PARTS LOCATOR DIAGRAM 2M MOTHERBOARD I INTERCONNECTIONS
A28
MOTHERBOARD
.L --- _; .l.
'r----� (Bottom Side)
m:m::m
J25
..
J26
..
..
..
..
• •
I! •••••
I
..
:: � F LI
.. "'
.. N
•• <[ a•• •
.. •
)( Kl
.. ::
.. •••
..
..
..
.. • ••• •
..
v�� �
.. •
.. • •
..
..
..
.. �
•• N
•• <[
:: )(
..
..
..
..
..
J23
2M-6 67XXBMM
0 1 2 3 4
A
LINE FILTER I A211J26
I
� ) 3I
FL! 4A SB, l!OV
2A SB, 220V
INPUT
:: r
z
,,,
�
0
POWER
B 6 LI •'
) I
�------�1
51-J I
I
I
51-1 1 I
1 I
) I
c
SI
I
l!OV )6 I
220V
Tl-3
f I
D F2
2A SB
P/0
REAR PANEL
7 I
& A26
:• P/ 0 A22A 1 '-! @
� �:· � •l yS
A28XA22 •22P2 A22P1 A22PI
F A2BXA22
••
+30V
4---
1 --+---.-'--'-< ·· I
FRO � 5�l
e
& CR9
�� �·· � � �1�
:-:-:-:-:-:-:-:-:-:-:-:-:·:�� ;, .• · . ·:-:- .•.• ..· :. -:-·-:-.-:.--:-.:.:
. ·.·=·· ·:· · ··· ·· ··· ·
::: .
, . .· ·..· ··. .·.·,•,•,,· ·.· ..· ............· ·.·· ··''�• ................. . .:. ;:
FAN DRIVER
G P/0
REAR
INPUT
PANEL
Kl AC LINE .·.·�.--· :·.··:·
··
POWER
RELAY -l-
LINE SWITCH, FAN
ANO INTERNAL 10 MHz
H
OSCILLATOR DETAIL
67XXB MM
5 6 7 8 9
----e-(o
I l c1
.01 CRI CR2
I MR824 MR824
I +S65V
I FLI
C3 RI
I C2
850 IOOK
.01
� r
�
r
0
>
0
I
C4
I 050
R2
IOOK
I
-165V
� +5V
R8
Kl 1K
R7
15K
04
-1
2N3694
C7
�CR7
MR852
p
�--�----l---.,___--f2/GO +30V
w
A28.J24
) . ( ( 9 1 +24V1 I 6)
I I
6
J;
P/O A2
FRONT
PANEL
P/0
CONTROL
CHASSIS
A211J3
2M-7
A28 MOTHERBOARD CONNECTOR CROSS-REFERENCE 2M MOTHERBOARD I INTERCONNECTIONS
Table 2M-2. Connector Location Cross-Reference for A28 Motherboard Schematic Diagram
A28XA03 A1 A28J01 81
A28XA04 E.1 A28J02 C1
A28XA05 F1 A28J03 F1
A28XA06 C1 A28J04 03
A28XA06 P2 E1 A28J05 E3
A28XA07 P1 F1 A28J06 F3
A28XA08 81 A28J07 04
A28XA09 E4 A28J08 E4
A28XA10 G1 A28J09 E4
A28XA11 P1 01 A28J10 G4
A28XA11 P2 E2 A28J11 88
A28XA12 F1 A28J12 03
A28XA13 02 A28J13 E3
A28XA14 8,2 A28J14 F3
A28XA15 82 A28J15 G5
A28XA16 8,3 A28J16 G,6
A28XA17 8,4 A28J17 G6
,
A28XA18 ES A28J18 G?
A28XA19 E,6 A28J19 87
A28XA20 E,6 A28J20 0,8
A28XA21 E,7 A28J21 8,8
A28XA22 E,8 A28J22 C,8
A28XA23 8,6 A28J23 C,7
A28XA24 86 A28J24 07 (Sheet 1 of schematic)
A28XA25,P1 08 A28J25 8,7
A28XA25, E,8 A28J26 A ,4 (Sheet 1 of schematic)
A28J27 C8
,
• Sheet 2 of schematic, unless otherwise noted.
2M-8 67XXB MM
0 1 2 3 4
0
0
� -
50
0 TO FANT�
,____IQ p 0 v
,- -
•
- � , � �
D -"- i �
p
"(!!
� TO REA.A
""'- '"
�
�
�
0
�
CLP DIV
6
XA P2 Fl MON
". I � � al 1
1
=
0 ' I
�
FlP OSC
1-
1tGrw 0
,
XA9
CLP OSC
-
0
x�1 : 2 :� '; ; � '-'
X 4
� FLP Oli'
� I l� FP AM
t AM I
j � c::J
FL
� �
SHIELD
i "°
� �-00
0
0 �:fl.,'."..li'
iy ""' t;;
'tm�":".
- "==� �
J6 TO RUA >--
I
-iev
�-+--41-EJ<>_>j--' TUNE
-
11 C1-
FIES EN
� "fn '-+-+-+--------->++--H-+-- --�
TO
�
¥ �.
i G0 �10 MH:z
PN..
� TO INTEW A29P1
OSC +1V0 REF
��
, D
•
�7 Lf-Ou
�f-0 �-��W -!:i_�-111-rm111-q:+=�0-1 �
<V
YIG PHASE DET ""
REF osc REF OIV \f/ XA12
\
'45 �
=;�
1 ' '"
F 0 ,...L, 0 0
0 \¢" <--tfJ �� RE�BUF IC_>+---4
,,- l <>-19
- <>+------*'l-+l+--_.._o"""o'••' ,_
c ON"_,,,, 'V'-,.,._
E
sL---4++++-+++-�
� 0 I <> XAlO G.L!!lll).__ '' -
�!;; <>
- .._ 1-1
FAA O <>
L1'll!LE!"
G-- 1L.:1=�== =±====±�E= ===�
-
: ,.._,,- G-
Q ERA !•I
O O (}_
'-t--+-ir-t<-,,, +•"'V LP
1, _
I - 5V P
-
•gv LP J ..___
y """
... "°"
00 ""'
G
�RiiNE /
I
CS
1/
v 08
+30
V
+165 1/BB >--------------------- --------------------------
-165 v 1/88 >------------------------- --------------- -------
67XXBMM
5 6 7 8 9
!/El +24V G
TO REAR Pfrl...
ANALOG I�Lrs_A29P2
SPIB
PROCESSOR
llA.11 -- ,W<J. �
-
-- n• -- --
)
-- �
)
--
::
)
o- oon
o- ::
...
0 0
10
0 SAHPLEA/If
TOA30
13
-
( " 0
.
--""--€>
NC
--
� w-:>-ftl-�-
J25 1
1W C T '------
� J21
l
O I:!
0
r,1--<l �·�
" ' ��
1
0
�
0 0
c� 19
� +1.,y 1.
0 0
GEW �
0
• G-
-€>G--i - G� G-i -1!5V A
0 , 0 2'
1-0...... �
0
= 10 G--i+22V
-€> G TO A31
+15Y 6
I
-1!5V G
c ,__.,
G--i +2•V 6 POWER AMP
I
;l�
- - -
-·· .. J22
O"0 .. G-i� 11 1
- -
+5V 0
,_ -
30 + 5V LP
t-€>� -0 20
-
tr
I
""----€>
- - PS2 MON
,. .... w� ,.� I
�-€>
�" <O
<BO
c.lliL_-€>"�
..... .....
"40
E::£ CA'- Sl-PJTOOWN
TO POliiEA
::
FROM FIEAA PANEL
-tJ �� J27
INT A 29P3 I/O A27P1
=
NC
"
0 ·-
="� ��
0
o-
-
0
_o L ff'" OFF
F":iT �WP TR S
-
POlllE A SI.PPLY
-
L SWP OWEL ::
�
�rw
� �·- ....
- ..... 0
- - 1
,--I.�
XA25PI
=.-w
- -
TO A18P2
YTS nRVR 1 L
TO ,1,1gp2 TO A20P2 TO A21P2
-
-€> :
YIS OR\IA 1 YI6 DAYA 2 YIS DAYA 3 YIG OR\IR '4
�
�----�
1i!�70·� ,X41Jl. 1�
XA2 517
1M.6.Q 1
-
iili iii
FM• � - 26
�o
�� � '--�30 0
+1!5V FM -�+16!5V
0
i�
IH ! J9
� -1"'V i:-w.
,_ -�
o!W
TO
23 0
-16!5¥
0
-�
-=�
-,
..... XA22
RE6UUTOFI
A22P2
': o TLO« REF -it>
,... 10 0
':
�o�
NTEFl'"ACE
�-"---0 +30V 13--,
w�
- - 0
0
2 �
:: 0 : 0 >V
REF 0 0 0
TO REAR F'tt...
-
, ..v
N
19 -
- -
+t5V 6
,_
� POWER SUPPLY �
,_
o!w �
PWA MTR
X �2
-toiy r;:
0
� ...v
-
. p
1 ci-.
-••v
-
1lw�
7�
-<t3V -1!'iV
�
IP
�� :: :: G-
- -
l1w
mv ..illLA. -
m
-te �:;-- <'}---
27 -
-€> 0
w� ft>G- G-
..=lli'...A- -0
�
- -
--
tJ G�
-€> -€> G-- ft>G --€> "� !1 + 21 G- +iBV G �
G -€> G ft>G>---- -€> G>-- � � l---€l
OG�
TO
>---- �m� -1BV 6
-€> " OG OG __J
. i��
JOWN CONVERTER
+
-
-€> G
-€> (
+ �
OG
o,
�G
m'-4o:;i :;i
oOG
,
1
I
-
�
�
"
� � �---.0� � :
-
:;i
�:��
�� + 5V FM � '¢/
>i':mi':hl
�<
" + � � f jil+ � < > +
-2 v 0
f
�+
� :i::i:�
<
�� g f; �
� �I � �
�
:�
H
�
JI!
DClJBLEA/AMP '.!: 1
Jl5 ��
U;
! I;: '
Z<
¥�
1 1
G +
PS!�
\v -ft)G 00
�ft)
�:� �:� �:�.
>--
-=�:�
�-€>"
-
0
TO YIG 1
.. >--ft) � >-- "
TO YI6 2
G-
-
ft)�
>-- "
TO YI6 3
�-€> "
--€>� . -
TO YI& <t
2M-9/2M-10
SECTION 3
DISASSEMBLY AND REPAIR PROCEDURES
CONTENTS
Paragraph Title Page
67XXB MM 3-1/3-2
SECTION 3
DISASSEMBLY AND REPAIR
3·1 INTRODUCTION
2. Place the synthesizer on its handles so that
The disassembly procedures show how to gain access the rear panel faces up (Figure 3-1).
to major instrument parts for troubleshooting or 3. Remove the four feet.
maintenance.
4. Remove the cover.
n
fi
LIO �FEET
, ' �(4)'\:�v
L6742A001
67XXB MM 3-3
DISASSEMBLY PROCEDURES SECTION 3-DISASSEMBL Y AND REPAIR PROCEDURES
a. Removing the Front Panel Assembly b. Removing the Front Panel Casting
1. Remove the cover as described in paragraph 1. Remove the cover as described in paragraph
3-2.1. 3-2.1.
2. Remove the five mounting scr ews - three top, 2. Unplu g the Al3J3 cable and pu sh it through
two bottom (Figure 3-2). the grommet on the chassi s (Figure 3-3).
3. Pu ll the front panel assembly away from the 3. Turn the synthesi zer on its top.
casting.
4. Lift the cable shi eld from its mounti ng pins
4. Unplu g the three ribbon cables from the back ju st enough to remove A28J5 and A28J7
of the front panel assembly. (Figure 3-4).
Do not push directly on the LCD Displays 8. Remove the ei ght screws that secure the front
which are mou nted into the front panel panel casti ng to the side rails.
assembly; they may break.
PUSH
HOLE
LCD
DISPLAY
SIDE RAIL
SCREWS
PULL
HERE
MOUNTING--.......:::----
SCREWS
L6742A002
3-4 67XXBMM
SECTION �ISASSEMBL Y AND REPAIR PROCEDURES DISASSEMBL Y PROCEDURES
POWER SUPPLY
HOUSING UPPER
SIDE RAIL
MICROWAVE DECK
L6742A003
MICROWAVE DECK
SUPPORT SCREWS
CONNECTOR
J27
FRONT PANEL
J24
MOUNTING SCREW
® ®
HIGH VOLTAGE
© SHIELD
©
CONNECTORS
MOTHERBOARD
J25 L6742A004
0 ©
CJ
67XXB MM 3-5
DISASSEMBL Y PROCEDURES SECTION 3-DISASSEMBL Y AND REPAIR PROCEDURES
9. Remove the front mounting screw from the The rear panel is now sufficiently disassembled to
quartz oscillator housing (Figure 3-3). allow troubleshooting and maintenance.
�c.AiiTioN-i
L .J
• • • • • • • • • • • • b. Removing the Rear Panel Casting
Before sliding the front panel away
from the chassis, loosen the captive To completely disassemble the rear panel, perform
nuts on the A29 PCB (Figure 3-4). the following steps and then follow the instructions
in paragraph 3-2.3a.
10. Slide the front panel forward.
1. Remove the cover as described in paragraph
NOTE: 3-2 . 1 .
If the front panel is held too tightly 2. From the top of the synthesizer, remove the
by the side rails, loosen the screws cables from A13J4, A13J5, A12J2, A10J5, and
along the top rails. A7J4.
�c.AiiTioN-i
L .J
• • • • • • • • • • • •
3. Pass these cables through the grommet, to the
bottom of the motherboard (Figure 3-5).
When replacing the front panel, protect
4. Tum the synthesizer over so that the bottom
the cables so they are not pinched or cut.
is accessible.
Also, protect the RF OUTPUT connector.
5. Remove the cable an d the high voltage
shields.
3-2.3 Removing the Rear Panel
6. Unplug the A28J6, A28J8, and A28J9 cables
This procedure is divided into two parts: opening the from the motherboard.
rear panel to access internal components and remov
7. Follow the instructions in paragraph 3-2.3a to
ing the rear panel casting for replacement or main
complete the disassembly of the rear panel.
tenance.
NO TE:
a. Opening the Rear Panel This technique is also useful when
1. Remove the cover as described in paragraph replacing a single cable or a BNC
3-2. 1. from the rear panel.
Take care to protect the cables that face PCB at the bottom of the synthesizer, secure the
are still connected between the rear bottom of the RF microwave deck. The rear support
panel and the motherboard. pillow block has a lock/release pin that must be lifted
8. Remove the cable from J26 (on the top of the before rotating the deck to the side.
motherboard - not visible in Figure 3-4).
3-6 67XXB MM
3-DISASSEMBL Y AND REPAIR PROCEDURES DISASSEMBLY PROCEDURES
SIDE RAIL
� SCREWS
,_______
LOCK/RELEASE
PIN
MICROWAVE DECK
SUPPORT SCREWS
L6742A005
4. Lift. the lock/release pin. positioned over the nearby semi-rigid cables.
67XXB MM 3-7/3-8
SECTION 4
SPECIAL OPTIONS
CONTENTS
Paragraph Title Page
67XXBMM 4- 1/4-2
SECTION V
PARTS LISTS
CONTENTS
Paragraph Description Page
67XXB MM 5-1
Table 5·1. Vendor and Vendor FSCM Number Cross-Reference List
5-2 67XXB MM
SECTION V
PARTS LISTS
Parts may be ordered from your local WILTRON rep Common abbreviations used in the parts list descrip
resentative or directly from the facto:ry. tions are defined in Table 5-2.
67XXB MM 5-3
ORGANIZATION OF PARTS LISTS SECTION �PARTS LISTS
5-4 67XXB MM
SECTION �PARTS LISTS A 1 FRONT PANEL PCB
67XXB MM 5-5
A 1 FRONT PANEL PCB SECTION �PARTS LISTS
5-6 67XXBMM
SECTION 5-PARTS LISTS A1 FRONT PANEL PCB
67XXB MM 5-7
A1 FRONT PANEL PCB SECTION �ARTS LISTS
5-8 67XXB MM
SECTION 5-PARTS LISTS A2 FRONT PANEL CONTROL PCB
67XXB MM 5-9
A2 FRONTPANEL CONTROLPCB SECTION �ARTS LISTS
5-10 67XXB MM
SECTION �PARTS LISTS A2 FRONTPANEL CONTROLPCB
67XXB MM 5-11
A3 COARSE LOOP MIXER PCB SECTION 5-PARTS LISTS
5-12 67XXBMM
SECTION 5- PARTS LISTS A3 COARSE LOOP MIXER PCB
67XXB MM 5-13
A4 COARSE LOOP OSCILLATOR PCB SECTION �PARTS LISTS
R3 110-1K-1 RESISTOR,FXD,MF,1Kn,1%,0.2SW
5-14 67XXBMM
SECTION 5- PARTS LISTS A4 COARSE LOOP OSCILLATOR PCB
67XXB MM 5-15
A4 COARSE LOOP OSCILLATOR PCB SECTION �PARTS LISTS
5-16 67XXB MM
SECTION �PARTS LISTS A5 REFERENCE OSCILLATOR PCB
67XXBMM 5-17
AS REFERENCE OSCILLATOR PCB SECTION �ARTS LISTS
5-18 67XXBMM
SECTION �PARTS LISTS A5 REFERENCE OSCILLATOR PCB
67XXBMM 5-19
A6 COARSE LOOP DIVIDER PCB SECTION 5-PARTS LISTS
5-20 67XXBMM
SECTION 5-PARTS LISTS A6 COARSE LOOP DIVIDER PCB
R9 110-S11-1 RESISTOR,FXD,MF,S1m,1%,0.2SW
67XXBMM 5-21
A6 COARSE LOOP DIVIDER PCB SECTION 5-PARTS LISTS
5-22 67XXBMM
SECTION 5-PARTS LISTS A6 COARSE LOOP DIVIDER PCB
67XXBMM 5-23
A7 REFERENCE DIVIDER PCB SECTION 5-PARTS LISTS
5-24 67XXBMM
SECTION 5-PARTS LISTS A7 REFERENCE DIVIDER PCB
R9 110-316-1 1 RESISTOR,FXD,MF,316n,1%,0.25W
67XXBMM 5-25
Al REFERENCE DIVIDER PCB SECTION �PARTS LISTS
5-26 67XXBMM
SECTION �ARTS LISTS AB SERIAL 110 PCB
R7 110-511-1 2 RESISTOR,FXD,MF,51Hl,1%,0.25W
R9 110-200-1 RESISTOR,FXD,MF,200Q,1%,0.25W
67XXBMM 5-27
A9 FINE LOOP OSCILLATOR PCB SECTION 5-PARTS LISTS
C26 230-37 CAPACITOR,FXD,CER,0.1 µF,20%, 1 OOV APE 1 221 04M1 OOV MURATA/ERIE
5-28 67XXBMM
SECTION 5-PARTS LISTS A9 FINE LOOP OSCILLATOR PCB
67XXB MM 5-29
A9 FINE LOOP OSCILLATOR PCB SECTION 5-PARTS LISTS
5-30 67XXBMM
SECTION 5-PARTS LISTS A9 FINE LOOP OSCILLATOR PCB
67XXBMM 5-31
A 10 REFERENCE BUFFER PCB SECTION �ARTS LISTS
5-32 67XXBMM
SECTION �PARTS LISTS A 10 REFERENCE BUFFER PCB
R39 109-51-5 RESISTOR, FXD, MF,51 Q, 5%,0.12W CMF -50 DALE RESISTOR
67XXBMM 5-33
A 10 REFERENCE BUFFER PCB SECTION 5-PARTS LISTS
5-34 67XXBMM
SECTION �PARTS LISTS A 1 1 FINE LOOP DIVIDER PCB
C11 230-37 19 CAPACITOR,FXD,CER,0. 1 µ F,20%, 1 OOV RPE1 221 04M1 OOV MURATA/ERIE
C12 230-37 CAPACITOR,FXD,CER,0. 1 µF,20%, 1 00V RPE1 221 04M1 OOV MURATA/ERI E
C13 230-37 CAPACITOR,FXD,CER,0. 1 µF,20%, 1 OOV APE 1 221 04M1 OOV MURATA/ERIE
C14 230-37 CAPACITOR, FXD,CER,0.1 µF,20%, 1 00V RPE 1 221 04 M 1 00V MURATA/ERIE
C15 230-37 CAPACITOR,FXD,CER,0 . 1 µ F,20%, 1 00V RPE 1 221 04M1 00V MURATA/ERIE
C18 230-64 4 CAPACI TOR, FXD, 1 000pF,5% 200-1 00-N P0- 1 02J CENTRE ENG
C19 230-64 CAPACI TOR,FXD, 1 000pF,5% 200- 1 00-N P0- 1 02J CENTRE ENG
C20 230-52 1 CAPACITOR, F DX, 1 5pF,5% 1 50-1 00-N P0- 1 SOJ CENTRE ENG
C24 230-37 CAPACITOR, FXD,CER,0. 1 µ F,20%, 1 00V APE 1 221 04M1 OOV MURATA/ERIE
C26 230-64 CAPACITOR,FXD . . 1 OOOpF,5% 200-1 00-N P0- 1 02J CENTRE ENG
C27 230-64 CAPACITOR,FXD., 1 000pF,5% 200- 1 00-N P0- 1 02J CENTRE ENG
67XXBMM 5-35
A 1 1 FINE LOOP DIVIDER PCB SECTION 5-PARTS LISTS
C50 250-42 CAPACITOR, FXD ,TANT, 1 0µF, 1 0%,25V 1 960106X9025 KE3 SPRAGUE
5-36 67XXBMM
SECTION 5-PARTS LISTS A 1 1 FINE L OOP DIVIDER PCB
R53 1 1 0-3 1 .6-1 RESISTOR, FXD, MF,31 .6Q, 1 %,0.25W SMA-4 OR C4 CORN I N G
67XXBMM 5-37
A 1 1 FINE L OOP DIVIDER PCB SECTION �PARTS LISTS
5-38 67XXBMM
SECTION �PARTS LISTS A 12 YIG PHASE DETECTOR PCB
C3 230-64 6 CAPACITOR ,FXO, 1 000pF,5% 200-1 00-N P0- 1 02J CENTRE ENG
cs 230-37 7 CAPACITOR, FXO,CER,0. 1 µ F,20%, 1 00V RPE 1 221 04M1 00V MURATA/ERIE
C6 250-77 1 CAPACI TOR, FXO,CER,0 .0 1 µF, 1 0%, 1 V CK05 BX1 03K SPRAGUE
C10 230-37 CAPACI TOR, FXO,CER,0. 1 µ F,20% , 1 00V RPE 1 22 1 04M1 00V MU RATA/ERIE
C11 230-37 CAPACI TOR, FXO,CER,0. 1 µF,20% , 1 00V RPE1 221 04M1 OOV MURATA/ERIE
C12 230-64 CAPACITOR, FXO, 1 OOOpF,5% 200-1 00-NP0-1 02J CENTRE ENG
C13 230-64 CAPACITOR,FXO, 1 OOOpF,5% 200-1 00-N P0-1 02J CENTRE ENG
C16 230-64 CAPACITOR, FXO, 1 000pF,5% 200- 1 00-NP0-1 02J CENTRE ENG
C25 250-42 CAPAC ITOR, FXO,TANT, 1 0µF, 1 0%, 25V 1 9601 06X9025KE3 SPRAGUE
R4 1 09-1 00-5 1 RESI STOR, FXD,MF, 1 oon, 1 %,0. 1 2W CMF-50 DALE RESISTOR
67XXBMM 5-39
A 1 2 YIG PHASE DETECTOR PCB SECTION 5-PARTS LISTS
R33 1 1 0-1 00-1 RESISTOR, FXD,MF, 1 00Q, 1 %,0. 25W SMA-4 OR C4 CORNING
R37 1 1 0-16 .2-1 1 RESISTOR, FXD, MF, 1 6.2Q, 1 %, 0.25W SMA-4 OR C4 CORNING
5-40 67XXB MM
SECTION �PARTS LISTS A 13PULSE GENERATOR PCB
67XXB MM 5-41
A 13 PULSE GENERATOR PCB SECTION 5-PARTS LISTS
cso 230-64 CAPACITOR,FXD,, 1 OOOpF,5% 200- 1 00-N P0-1 02J CENTRE ENG
C51 230-37 CAPACITOR, FXD, CE R,0. 1 µF,20% , 1 00V RPE 1 22 1 04M100V MURATA/E R I E
C52 230-37 CAPACITOR, FXD,CER,0. 1 µF,20% , 1 00V RPE1 221 04M100V MU RATA/ERIE
C53 230-37 CAPAC ITOR,FXD,CER,0. 1 µF,20%, 1 OOV RPE1 22104M1 00V MU RATA/ERIE
C54 230-64 CAPACITOR,FXD,, 1 OOOpF,5% 200-1 00-N P0- 1 02J CENTRE ENG
C55 230-37 CAPACITOR,FXD,CER,0. 1 µF,20%, 1 OOV RPE1 221 04M1 OOV MURATA/ERIE
5-42 67XXBMM
SECTION 5-PARTS LISTS A 13 PULSE GENERATOR PCB
67XXB MM 5-43
A13PULSE GENERATORPCB SECTION �PARTS LISTS
5-44 67XXB MM
SECTION 5-PARTS LISTS A13PULSE GENERATOR PCB
67XXB MM 5-45
A 13 PULSE GENERA TOR PCB SECTION 5-PARTS LISTS
U29 54-324 1 TTL,,DUAL, DIGITAL DE LAY LINE DDU-4-5 1 25 DATA DELAY DEV
5-46 67XXBMM
SECTION 5-PARTS LISTS A15ALCPCB
cs 230-85 1 CAPACITOR,FXD,CER,0.33uF,10%
C42 230-47 CAPACI TOR,FXD,.01µ.F, 10% 200- 1OO-X7 R-103K CENTRE ENG
67XXBMM 5-47
A 15 ALC PCB SECTION �PARTS LISTS
C53 230-47 CAPACITOR,FX0, .01 µF,+/- 10% 200-1OO-X7R-1 03K CENTRE ENG
C59 250-42A CAPAC ITOR,FXO,TANT, 1 0µF, 1 0%, 25V 19601 06 X9025KA 1 SPRAGUE
5-48 67XXBMM
SECTION � PARTS LISTS A 15 ALC PCB
C88 230-47 CAPACITOR,FXD,.0 1 uF, 1 0% 200- 1 00-X? R-1 03K CENTRE ENG
C90 230-81 CAPAC ITOR,FXD,CE R.47PF,5% 1 50- 1 00-N P0-4?OJ CENTRE ENG
C95 250-42A CAPACITOR, FXD,TANT, 1 0µF, 1 0%, 25V 1 96D1 06X9025KA1 SPRAGUE
C96 250-42A CAPACITOR, FXD,TANT, 1 0µF, 1 0%, 25V 1 96D1 06X9025KA 1 SPRAGUE
CR1 1 0-FD300 13 DIODE RECTI FIE R,IN3595 1 N3595 SOLID STATE DEV
CR2 1 0-FD300 DIODE RECTIFI ER, IN 3595 1 N3595 SOLID STATE DEV
CR4 1 0-FD300 DIODE RECTI FIER,I N3595 1 N3595 SOLID STATE DEV
CR21 10-FD300 DIODE RECTIFI ER,I N3595 1 N3595 SOLID STATE DEV
CR25 1 0-FD300 DIODE RECTIFIE R,I N3595 1 N3595 SOLID STATE DEV
CR28 1 0-FD300 DIODE RECTI FI ER,I N3595 1 N3595 SOLID STATE DEV
CR31 1 0-FD300 DIODE RECTI FIER,I N3595 1 N3595 SOLID STATE DEV
67XXBMM 5-49
A 15 ALC PCB SECTION �PARTS LISTS
5-50 67XXB MM
SECTION �PARTS LISTS A 15 AL C PCB
67XXB MM 5-51
A 15 ALC PCB SECTION �PARTS LISTS
5-52 67XXBMM
SECTION 5-PARTS LISTS A 15 AL C PCB
67XXBMM 5-53
A 15 AL C PCB SECTION 5-PARTS LISTS
R171 1 1 0- 1 00-1 RESISTOR,F XD,MF, 1 00Q, 1 %,0. 25W SMA-4 OR C4 CORN ING
5-54 67XXBMM
SECTION 5-PARTS LISTS A 15 ALC PCB
67XXB MM 5-55
A15ALC PCB SECTION 5- PARTS LISTS
5-56 67XXBMM
SECTION 5-PARTS LISTS A 15 AL C PCB
U34 50-33 1 OP AMP,LT1 056, SIN GLE LT1 056CNB LINEAR TECH
67XXBMM 5-57
A 16 FM PCB SECTION 5-PARTS LISTS
C2 250-42 CAPACITOR, FXD ,TANT, 1 OµF, 1 0%, 25V 1 9601 06X9025KE3 SPRAGUE
C1 1 250-42 CAPACITOR, FXD ,TANT, 1 OµF, 1 0%, 25V 1 96D1 06X9025KE3 SPRAGUE
C13 250-42 CAPACITOR, FXD,TANT, 1 0µF, 1 0%, 25V 1 96D1 06X9025KE3 SPRAGUE
C19 250-42 CAPACITOR, FXD,TANT, 1 0µF, 1 0%, 25V 19601 06X9025 KE3 SPRAGUE
C24 250-42 CAPACITOR, FXD, TANT, 1 OµF, 1 0%, 25V 1 9601 06X9025KE3 SPRAGUE
C34 230-37 CAPACITOR,FXD,CER,0. 1 µF,20%, 1 OOV RPE1 221 04M1 OOV MU RATA/ERIE
C37 250-42 CAPACI TOR, FXD ,TANT, 1 0µF, 1 0%,25V 1 9601 06X9025 KE3 SPRAGUE
5-58 67XXB MM
SECTION �PARTS LISTS A 16 FM PCB
C40 250-42 CAPACITOR, FXD,TANT, 1 0µF, 1 0%, 25V 1 96D1 06X9025KE3 SPRAGUE
C43 250-42 CAPACI TOR, FXD ,TANT, 1 0µF, 1 0%,25V 1 96D1 06X9025KE3 SPRAGUE
C49 230-76 CAPACITOR, FXD,CER, 1 200PF, 1 % 200-1 00-NP0-1 22F CENTRE ENG
C50 230-76 CAPACITOR, FXD,CER, 1 200PF, 1 % 200-1 00-NP0-1 22F CENTRE ENG
C51 230-76 CAPACITOR, FXD,CER, 1 200PF, 1 % 200-1 00-NP0- 1 22F CENTRE ENG
C53 230-76 CAPAC ITOR,FXD,CER, 1 200PF, 1 % 200- 1 00-NP0- 1 22F CENTRE ENG
C58 223-600 1 CAPACITOR, FXD,CER, 1 500PF, 1 0% 200-1 OO-X7R-1 52K CENTRE ENG
CR7 1 0-FD300 DIODE RECTI FIER,I N3595 1 N3595 SOLID STATE DEV
CR23 1 0-FD300 DIODE RECTIF IER, IN3595 1 N 3595 SOLID STATE DEV
CR26 1 0-FD300 DIODE RECTI FIER,I N3595 1 N3595 SOLID STATE DEV
67XXBMM 5-59
A 16 FM PCB SECTION 5-PARTS LISTS
CR36 10-1 N4446 DIOD E.SWITC HI NG, 1 N4446 1 N4446 T+R FAIRCH I LD
5-60 67XXBMM
SECTION 5-PARTS LISTS A 16 FM PCB
R62 1 1 0-31 .6-1 2 RESISTOR, FXD, MF,31 .6.n, 1 %,0.25W SMA-4 OR C4 CORN I N G
67XXBMM 5-61
A 16 FM PCB SECTION 5-PARTS LISTS
R73 1 1 0-1 00-1 RESISTOR,FXD, MF, 1 oon, 1 %,0.25W SMA-4 OR C4 CORN ING
5-62 67XXBMM
SECTION �PARTS LISTS A 16 FM PCB
67XXB MM 5-63
A 1 6 FM PCB SECTION 5-PARTS LISTS
5-64 67XXBMM
SECTION �PARTS LISTS A 1 7 ANAL OG INSTRUCTION PCB
C30 250- 1 9 CAPACITOR, FXO, TANT, 1 µF,1 0%,35V 1 9601 05X9035HE3 SPRAGUE
C35 230-37 CAPACITOR,FXO,CER,0. 1 µF,20%, 1 00V RPE1 221 04M1 00V MU RATA/ER I E
C36 230-37 CAPACITOR,FXO , C ER,0 . 1 µF,20%, 1 OOV RPE 1 221 04 M 1 00V MU RATA/ER I E
C40 250-42 CAPACITOR,FXO, TANT, 1 0µF, 1 0%,25V 1 960 1 06X9025 KE3 SPRAGUE
C47 230-4 1 2 2 CAPACITOR, FXO,CER, 1 .0µF,20%, 1 0V 400- 1 00-60 1 - 1 OSM CENTRE ENG
C49 230-37 13 1 3 CAPACITOR,FXO,CER,0 . 1 µF,20%, 1 00V RPE1 221 04M1 OOV MU RATA/ERIE
C51 230-37 CAPACITOR, FXO,CER,0. 1 µF,20%, 1 OOV RPE1 221 04M1 OOV MU RATA/ER I E
C52 230-37 CAPACITOR, FXO,CER,0.1 µF,20%, 1 OOV R P E 1 221 04M1 OOV MU RATA/ER I E
C54 230-37 CAPACITOR,FXO,CER,0. 1 µF,20%, 1 OOV RPE1 221 04M1 00V MURATA/ER I E
67XXB MM 5-65
A 17 A NALOG INSTRUCT/ONPCB SECTION 5-PARTS LISTS
C64 250-42 CAPACITOR,FXD ,TANT, 10µF , 10% ,25V 196D 106X9025KE3, SPRAGUE
CR13 10-F D300 DIODE RECTI FI ER,I N3595 1N3595 SOLID STATE DEV
CR15 10-F D300 DIODE RECTI F I ER ,IN3595 1N3595 SOL I D STATE DEV
CR17 10-F D300 DIODE RECTIF IER,IN3595 1N3595 SOLID STATE DEV
CR18 10-FD300 DIODE RECTIF IER,I N3595 1N3595 SOLI D STATE DEV
5-66 67XXB MM
SECTION �PARTS LISTS A 1 7 ANALOG INSTRUCTION PCB
67XXB MM 5-67
A 17 ANALOG INSTRUCTION PCB SECTION 5-PARTS LISTS
5-68 67XXBMM
SECTION 5-PARTS LISTS A 1 7 ANALOG INSTRUCT/ON PCB
67XXBMM 5-69
A 1 7 ANALOG INSTRUCTION PCB SECTION 5-PARTS LISTS
U25 54-503 OP-AMP, LT1 007,SINGLE LT1 007CN8 LIN EAR TECH
U39 54-503 OP-AMP, LT1 007,SI NGLE LT1 007CN8 LINEAR TECH
5-70 67XXB MM
SECTION �PARTS LISTS A 18 2-8.4 GHz YIG DRIVER PCB
C15 250-77 CAPACI TOR,FXD,CER,0 .01 µF, 1 0%, 1 V CK05BX 1 03K SPRAGUE
C19 230-37 CAPACITOR,FXD,CER.0. 1 µF.20%, 1 00V RPE1 221 04M1 OOV MURATA/ERI E
C25 220- 1 30 1 CAPACI TOR, FXD,MICA, 1 30PF,5%,50V CD1 5FD1 3 1 J03 CORNELL DUBILIER
C27 230-48 1 CAPACI TOR,FXD, . 0 1 8µF, 1 0% 200-1 OO-X7A-1 83K CENTRE ENG
C28 230-37 CAPACI TOR,FXD,CER,0. 1 µF,20%, 1 OOV RPE 1 221 04M 1 00V MURATA/ERI E
C30 223- 1 00 1 CAPACI TOR, FXD,MICA, 1 00PF,5%,50V CD1 0FD1 0 1 J03 CORNELL DUBI LIER
C33 230-37 6 CAPAC ITOR,FXD,CER,0. 1 µF,20%, 1 OOV RPE1 221 04M1 00V MURATA/ERIE
C34 250-77 CAPACJTOR, F XD,C ER,0 .01 µF, 1 0%, 1 V C K05BX 1 03K SPRAGUE
C43 230-37 CAPACITOR, FXD,CER,0. 1µF,20%, 1 OOV R P E 1 221 04M 1 00V MURATA/ERI E
C45 230-37 CAPACITOR, FXD,CER,0.1 µF,20%, 1 OOV RPE 1 22 1 04M1 00V MURATA/ERI E
67XXB MM 5-71
A 18 2-8.4 GHz YIG DRIVER PCB SECTION 5-PARTS LISTS
CR1 5 1 0-FD300 DIODE RECTI FIER,I N3595 1 N3595 SOLID STATE DEV
5-72 67XXB MM
SECTION 5-PARTS LISTS A18 2-8.4 GHz YIG DRIVER PCB
R10 1 1 0-1 00-1 RESISTOR, FXD,MF, 1 oo.n, 1 %,0.25W SMA-4 OR C4 CORN ING
R16 1 1 0-1 00-1 RESISTOR, FXD, MF, 1 00.n, 1 %,0.25W SMA-4 OR C4 CORNIN G
R34 1 1 0-1 00-1 11 RESISTOR, FXD,MF, 1 00.n, 1 %,0.25W SMA-4 OR C4 CORN ING
67XXB MM 5-73
A 18 2-8.4 GHz YIG DRIVER PCB SECTION �PARTS LISTS
5-74 67XXBMM
SECTION �PARTS LISTS A 18 2-8.4 GHz YIG DRIVER PCB
67XXBMM 5-75
A19 2-12.4 GHz YIG DRIVER PCB SECTION 5-PARTS LISTS
5-76 67XXB MM
SECnON �PARTS LISTS At9 2·12.4 GHz YIG DRIVER PCB
CR13 10-FD300 3 DIODE RECTI FIER, I N3595 1 N3595 SOLID STATE DEV
CR2 1 1 0-1 N4446 DIOD E.SWITC HING, 1 N4446 1 N 4446 T+R FAIRCHILD
67XXB MM 5-77
A 19 2· 12.4 GHz YIG DRIVER PCB SECTION 5-PARTS LISTS
5-78 67XXB MM
SECTION 5-PARTS LISTS A19 2-12.4 GHz YIG DRIVER PCB
67XXB MM 5-79
A19 2·12.4 GHz YIG DRIVER PCB SECTION 5-PARTS LISTS
R9 1 NOT USED
U9 NOT USED
W4 NOT USED
5-80 67XXB MM
SECTION �PARTS LISTS A20 12-20 GHz YIG DRIVER PCB
67XXBMM 5-81
A20 12-20 GHz YIG DRIVER PCB SECTION 5-PARTS LISTS
R7 130-47-3 1 RESISTOR,FXD,WW,47n,5%,3.25W
5-82 67XXB MM
SECTION 5-PARTS LISTS A20 12·20 GHz YIG DRIVER PCB
67XXB MM 5-83
A20 12·20 GHz YIG DRIVER PCB SECTION �PARTS LISTS
5-84 67XXB MM
SECTION 5-PARTS LISTS A21 18-26.5 GHz YIG DRIVER PCB
67XXBMM 5-85
A21 18-26.5 GHz YIG DRIVER PCB SECTION 5-PARTS LISTS
R7 1 30-47-3 1 RESISTOR,FXD,WW,47il,5%,3.25W
5-86 67XXB MM
SECTION 5-PARTS LISTS A21 18·26.5 GHz YIG DRIVER PCB
67XXB MM 5-87
A2 1 18-26.5 GHz YIG DRIVER PCB SECTION 5-PARTS LISTS
5-88 67XXB MM
SECTION 5-PA RTS LISTS A22 REGULA TOR INTERFACE PCB
C30 250-19 1 CAPACITOR,FXD,TANT, 1µF,1 0%,35V 196D 105X9035 HE3 SPRA GUE
67XXB MM 5-89
A22 REGULATOR INTERFACE PCB SECTION 5-PARTS LISTS
5-90 67XXB MM
SECTION 5-PARTS LISTS A22 REGULATOR INTERFACE PCB
67XXBMM 5-91
A23 MICROPROCESSOR PCB SECTION �PARTS LISTS
5-92 67XXB MM
SECTION �PARTS LISTS A23 MICROPROCESSOR PCB
67XXBMM 5-93
A23 MICROPROCESSOR PCB SECTION 5-PARTS LISTS
5-94 67XXB MM
SECTION 5-PARTS LISTS A24 GPIB PCB
67XXB MM 5-95
A24 GPIB PCB SECTION 5-PARTS LISTS
5-96 67XXBMM
SECTION 5-PARTS LISTS A25 SWITCHING POWER SUPPLY PCB
C25 230-37 CAPACITOR, FXO, CER,O. 1µF,20%,1 OOV RPE122104M1 00V MURATA/ERIE
67XXB MM 5-97
A25 SWITCHING POWER SUPPLY PCB SECTION �PARTS LISTS
5-98 67XXB MM
SECTION �PARTS LISTS A25 SWITCHING POWER SUPPLY PCB
67XXB MM 5-99
A25 SWITCHING POWER SUPPLY PCB SECTION �PARTS LISTS
5- 100 67XXB MM
SECTION 5-PARTS LISTS A25 SWITCHING POWER SUPPLY PCB
67XXB MM 5- 1 0 1
A27 AUXILIARY VO PCB SECTION 5-PARTS LISTS
5-102 67XXB MM
SECTION �PARTS LISTS A28 MOTHERBOARD PCB
67XXB MM 5- 103
A28 MOTHERBOARD PCB SECTION 5-PARTS LISTS
R3 110-487-1 1 RESISTOR,FXD,MF,487n,1%,0.25W
5- 104 67XXB MM
SECTION �PARTS LISTS A29 REAR PANEL INTERFACE PCB
67XXB MM 5-105
A29 REAR PANEL INTERFACE PCB SECTION 5-PARTS LISTS
5-106 67XXB MM
SECTION 5-PARTS LISTS A29 REAR PANEL INTERFACE PCB
67XXB MM 5-107
A29 REAR PA NEL INTERFACE P CB SE CTION �ARTS LISTS
R14 1 1 0-1 00-1 RESISTOR, FXD, MF, 1 oon. 1 %,0.25W SMA-4 OR C4 CORNING
R20 1 1 0-1 00-1 RESISTOR, FXD,MF, 1 oon, 1 %,0.25W SMA-4 OR C4 CORN ING
R26 1 1 0-1 00-1 RESISTOR, FXD, MF, 1 00Q, 1 %,0.25W SMA-4 OR C4 CORN ING
R40 1 1 0-48 .7-1 RESISTOR, FXD , M F,48. ?n, 1 %,0.25W SMA-4 OR C4 CORNING
R49 1 1 0-1 33-1 4 RESI STOR, FXD,MF, 133n, 1 %,0.25W SMA-4 OR C4 CORNING
5-108 67XXB MM
SECTION 5-PARTS LISTS A29 REAR PANEL INTERFACE PCB
67XXB MM 5- 109
A29 REAR PANEL INTERFACE PCB SECTION �PARTS LISTS
R147 1 1 0-1 0K-1 RES ISTOR. FXD,MF, 1 0.0 Kil, 1 %,0. 25W
5-110 67XXB MM
SECTION 5-PARTS LISTS A29 REAR PANEL INTERFACE PCB
U10 54-501 3 D/A, MP1 232 MP1 232HN MICRO POWER SYS-
TEMS
U13 54-50 1 D/A, MP1 232 MP1 232HN MICRO POWER SYS-
TEMS
67XXB MM 5-1 1 1
A29 REAR PANEL INTERFACE PCB SECTION �ARTS LISTS
5 - 1 12 67XXB MM
SECTION �PARTS LISTS OPTIONS AND ACCESSORIES
.
' lOil 1-Rack Mount AB semblIV
Table 5 31 0IPt'
•
900-391 4 WASHER,#4
900-391 4 WASHER,#4
900-391 4 WASHER,#4
67XXB MM 5-113
OPTIONS AND ACCESSORIES SECTION �PARTS LISTS
5-114 67XXB MM
SECTION 5-PARTS LISTS
INDEX
WPN QTY DESCRIPTION
NO.
67XXB MM
MECHANICAL PARTS
5-115
MECHANICAL PARTS SECTION 5-PARTS LISTS
INDEX
WPN QTY DESCRIPTION
NO.
1 790-265 · g STANOOF�MALE/FEMALE
3 60-25 1 DC MOTOR
-·�
5-116 67XXB MM
SECTION �ARTS LISTS
INDEX INDEX
WPN QTY DESCRIPTION WPN QTY DESCRIPTION
NO. NO.
67XXB MM
MECHANICAL PARTS
r1 r1 n
0 0 0
· •••Ii •
•
0 "
-®
5-117
INDEX
WPN QTY DESCRIPTION
NO.
5-118 67XXB MM
SECTION �ARTS LISTS
NOTE: The A3 thru A13 PCBs are pull out assemblies with permanently attached cover plates and handles,
as shown below. These PCBs reside in the RF housing.
67XXB MM
MECHANICA L PARTS
5-119
INDEX
WPN QTY DESCRIPTION
NO.
5-120 67XXB MM
SECTION �ARTS LISTS
INDEX
WPN QTY DESCRIPTION
NO.
67XXB MM
MECHANICAL PARTS
...
5 ,._
___
& )......---
�I _I
'
TI
5-121
INDEX
WPN QTY DESCRI PTION
NO.
11 783-403 1 FILTER.FAN
12 785-882 4 STANDOFF, M/ F
;\\ E � M
�IPULSE
NPUT �
�����
OUTPUT � ��FINPUTH• 4'
\::!;/
NOTE: USE SLOW BLOW
FUSES ONLY.
�
2!J IAMNPUT @\;:�c f@'i VIGHz
� O UTPUT '@) OUTPUT
SEO
INPUT G OUTPUT SWITCH �
�MEMORY�RETRACE�BANO
BLANK G BLANK G �IEF� CAUIIQl!I
90-1 30V
1 80·260V
DO NOT OPERATE S0-400Hz
� MARKER
wrrn UNGROUNDED 'l20VA
POWER CORO
14
5-122 67XXB MM
SECTION S:-PARTS LISTS
©-
fJ 'IT
- I
-1 1
'1
1,
I'
1i 30
·I
;1
,1
01
,/
67XXB MM
MECHANICAL PARTS
5-123
MICROWA VE DECK A SSEMBLY SECTION �PARTS LISTS
INDEX INDEX
WPN QTY DESCRIPTION WPN QTY DESCRIPTION
NO. NO.
ND19072
. 8 TO 12.4 GHz RF AMP
C18965
. 18 TO 26.5 GHz RF AMP
5-124 67XXB MM
MICROWA VE DECK A SSEMBLY
13
TOP VIEW
BOTTOM VIEW
--
10 '
'
,,
'
I
,' I
,_,
;·
/
:. .,C- "-' I
'-· ·� .. '
C0
I
26 17
67XXB MM
SECTION 5-PARTS LISTS
"�
�;;::;;;::;
;;;: :;;;
;;;: ;;;;j .. ;y-..J
.
26
0 0
2 1
5-125/5-126