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Computer Architecture

l Topics:
l Processor Design
Where are we now?
l C-Programming
l A real computer language
l Data Representation
l Everything goes down to bits and bytes
l Machine representation Language
l Very limited programming model
l Digital Logic
l Transistors g Gates g Circuits
l Circuits g { Memory, Registers, and
Components}
l What are we going to do now.
Processor Design
l Figure out how a small subset of the
instruction set works in hardware
l Use Hardware blocks to describe data path

l Use control logic to ensure steps of the

instruction flows smoothly
Add instruction
l Type of add depends on where operands are
located
l add reg1, reg2
l Add contents of reg1 to reg2 and store result in reg2
l add $constant, reg2
l Add contents of memory immediately following the
instruction to reg 2 and store result in reg2
l add (effective-address), reg2
l Add contents of effective address to reg2 and store
result in reg2
l Effective address could be relative; relative + offset;
relative + offset, index; relative + offset, index*scaled
 Instruction Example
l Addition Instruction
Generic Form!

Encoded Representation!

addl %edx, %eax! 0 3 rA! rB!

l Add value in register %edx to that in register %eax

l Store result in register %eax
l Two-byte encoding
l First indicates instruction type
l Second gives source and destination registers
ADD-Add : note src, dst are
reversed in the intel manual

In assembly language add src, dst means src + dst dst

 Instruction Example in x86
l Addition Instruction
Generic Form!

Encoded Representation!

addl %edx, %eax! 0 3 C! 2!

l Opcode is 03 and src, dst are %edx, %eax

l from previous table (Table 2.2) code is C2
l So, 03 C2 means add addl
%edx, %eax
8(%ebp), %eax! 0 3 4 5

l 03 45
l means add 8(%ebp), %eax
addl $4, %eax! 0 5 000 4
l 05
l add $cons, %eax
 Arithmetic and Logical
Operations
Instruction Code! l The second byte will
Function Code!
vary based on type of
Subtract (rA from rB)! operands
subl rA, rB! 2 B rA! rB! l Set condition codes
as side effect
And!

andl rA, rB! 2 3 rA! rB!

Exclusive-Or! Lower 4 bits can vary depending upon the type

Of operand

xorl rA, rB! 3 3 rA! rB! 20 means 8 byte register transfer,

Lower 4 bits can vary

30 means 8 byte register transfer,

Subtract operation-
Instruction Set Reference
Single cycle stages
l Fetch Instruction (IF)
l Decode Instruction (ID)

l Execute Instruction (EX)

l Memory access (MEM)

l Write back (WB)

l Update Program Counter (PC)

Building Blocks
fun"

A"
l Combinational Logic A"
L"
l Compute Boolean B"
U"
A"
functions of inputs
MUX"
l Continuously respond to B" A

input changes 1

="
l Operate on data and S

implement control B

valA"

A"
srcA"
valW"
Register" W"

Storage Elements
dstW"
file"
l valB"

B"
srcB" Clock"
l Store bits
Clock!
l Addressable memories
l Non-addressable registers
Fetch Instruction
+"

A"
L"
U"
+4"

IR

PC

Fetch Instruction and increment Program counter

 Add instruction (add %edx,
%eax)
+"

%edx

IR
A"
Register file
L"
U"
%eax

l Op code determines type of operation

l 03 C2
l Operands are in registers
l They are fed to the adder (ALU)
l Result stored back in register
l Based On Instruction the signal to ALU can be +, -, * or /
 Add instruction (add $4,
%eax)
+!

IR
%eax

A"
Register file
L"
U"

l Op code is determines type of operation

l 03 05
l One Operand is a register, the other is part of the instruction
l %eax, immediate value
l They are fed to the adder (ALU)
l Result stored back in register
 mov instruction (mov 8(%ebp),
%eax)
Data

+" mem

IR
%ebp
address

A"
Register file
L"
U"
%eax

data

l Op code is determines type of operation R/W

l 8b 45
l Load word from memory onto register %eax
l Address is 8 + (%ebp)
 mov instruction (mov %eax,
8(%ebp))
Data

+" mem

IR
%ebp
address

A"
Register file
L"
U"
%eax

data

l Op code determines type of operation R/W

l 89 45
l Store word from register %eax onto memory
l Address is 8 + (%ebp)
SEQ Hardware PC!
newPC !

Structure
!! !
valE , valM

Write back! valM !

l State Data
Data !
Memory! memory
memory !
l Program counter register (PC) ! !
Addr, Data

l Condition code register (CC)

valE!
l Register File
l Memories ! CC CC! ALU
ALU !
Execute! Bch
l Access same memory space aluA!, a!luB!

l Data: for reading/writing program

data
!! !
valA , valB
l Instruction: for reading instructions
l Instruction Flow !! !
srcA , srcB
! ! !!
Decode! !! !
dstA , dstB A
RegisterM
Register
B

l Read instruction at address ! !

file
file
E

specified by PC , !! !!
icode! ifun
rA! , rB
valP !
valC !
l Process through stages
Instruction
Instruction ! PC
PC !
l Update program counter Fetch!
memory
memory ! increment
increment !

PC !
 newPC !
PC!

SEQ Stages
!! !
valE , valM

Write back! valM !

l Fetch Data
Data !
Memory! memory
memory !
l Read instruction from instruction ! !
Addr, Data

memory
!
Decode
valE
l
l Read program registers ! CC CC! ALU
ALU !
Execute! Bch

l Execute aluA!, a!luB!

l Compute value or address

l Memory !! !
valA , valB

l Read or write data !! !

Decode!
srcA , srcB
!! !
dstA , dstB ! ! !!
A B

Write Back RegisterM

Register
l ! !
file
file
E

l Write program registers , !! !!

icode!ifun
rA! , rB
valP !
!
PC
valC
l
Instruction
Instruction ! PC
PC !
l Update program counter Fetch!
memory
memory ! increment
increment !

PC !
Instruction Decoding
Optional! Optional!

5 0 rA" rB" D"

icode!
ifun!
rA!
rB!
valC!
l Instruction Format
l Instructionbyte icode:ifun
l Optional register byte rA:rB
l Optional constant word valC
 Executing Arith./Logical
OperationOPl rA, rB! 6 rA! rB! fn"

l Fetch l Memory
l Read 2 bytes l Do nothing
l Decode l Write back
l Read operand registers l Update register
l Execute l PC Update
l Perform operation l Increment PC by 2
l Set condition codes
 Stage Computation: Arith/
Log. Ops
OPl rA, rB!
icode:ifun M1[PC]! Read instruction byte!
rA:rB M1[PC+1]! Read register byte!
Fetch!
! !
valP PC+2! Compute next PC!
valA R[rA]! Read operand A!
Decode!
valB R[rB]! Read operand B!
valE valB OP valA! Perform ALU operation!
Execute!
Set CC! Set condition code register!
Memory! ! !
Write! R[rB] valE! Write back result!
back! ! !
PC update! PC valP! Update PC!

l Formulate instruction execution as sequence of

simple steps
l Use same general form for all instructions
 Executing popl
popl rA! 8 F rA! 8
l Fetch l Memory
l Read 2 bytes l Read from old stack pointer
l Decode l Write back
l Read stack pointer l Update stack pointer
l Execute l Write result to register
l Increment stack pointer by 4 l PC Update
l Increment PC by 2
POP Instruction
Stage Computation: popl
popl rA!
icode:ifun M1[PC]! Read instruction byte!
rA:rB M1[PC+1]! Read register byte!
Fetch!
! !
valP PC+2! Compute next PC!
valA %esp! Read stack pointer!
Decode!
valB %esp! Read stack pointer!
valE valB + 4! Increment stack pointer!
Execute!
Memory! valM M4[valA]! Read from stack !

Write! R[%esp] valE! Update stack pointer!

back! R[rA] valM! Write back result!
PC update! PC valP! Update PC!
l Use ALU to increment stack pointer
l Must update two registers
l Popped value
l New stack pointer
 Executing Jumps
jXX Dest! 7 fn" Dest"

fall thru:! XX XX Not taken!

target:! XX XX Taken!

l Fetch l Memory
l Read 5 bytes l Do nothing
l Increment PC by 5
l Write back
l Decode
l Do nothing
l Do nothing
l Execute l PC Update
l Determine whether to take l Set PC to Dest if branch
branch based on jump taken or to incremented PC if
condition and condition codes not branch
Stage Computation: Jumps
jXX Dest!
icode:ifun M1[PC]! Read instruction byte!

Fetch!
valC M4[PC+1]! Read destination address!
valP PC+5! Fall through address!

Decode!

Execute!
Bch Cond(CC,ifun)! Take branch?!
Memory! ! !
Write!
back! ! !
PC update! PC Bch ? valC : valP! Update PC!

l Compute both addresses

l Choose based on setting of condition codes and
branch condition
 Executing call
call Dest! E 8 Dest"

return:! XX XX

target:! XX XX

l Fetch l Memory
l Read 5 bytes l Write incremented PC to new
l Increment PC by 5 value of stack pointer
l Decode l Write back
l Read stack pointer l Update stack pointer
l Execute l PC Update
l Decrement stack pointer by 4 l Set PC to Dest
Stage Computation: call
call Dest!
icode:ifun M1[PC]! Read instruction byte!

Fetch!
valC M4[PC+1]! Read destination address !
valP PC+5! Compute return point!

Decode!
valB R[%esp]! Read stack pointer!
valE valB + 4! Decrement stack pointer!
Execute!

Memory! M4[valE] valP ! Write return value on stack !

Write! R[%esp] valE! Update stack pointer!
back! ! !
PC update! PC valC! Set PC to destination!

l Use ALU to decrement stack pointer

l Store incremented PC
Call Opcodes in X86
 Executing ret
ret! C 3

return:! XX XX

l Fetch l Memory
l Read 1 byte l Read return address from old
l Decode stack pointer
l Read stack pointer l Write back
l Execute l Update stack pointer
l Increment stack pointer by 4 l PC Update
l Set PC to return address
Stage Computation: ret
ret
icode:ifun M1[PC]! Read instruction byte!

Fetch!
! !

valA R[%esp]! Read operand stack pointer!

Decode!
valB R[%esp]! Read operand stack pointer!
valE valB + 4! Increment stack pointer!
Execute!

Memory! valM M4[valA] ! Read return address!

Write! R[%esp] valE! Update stack pointer!
back! ! !
PC update! PC valM! Set PC to return address!

l Use ALU to increment stack pointer

l Read return address from memory