EECS 240

Analog Integrated Circuits

Topic 4:
MOS Models for Analog Design

Bernhard E. Boser and Ali M. Niknejad

Department of Electrical Engineering and Computer Sciences

EECS 240 Topic 4: MOS Models for Design 2007 B. Boser & A. Niknejad
 MOSFET Models for Design
SPICE (BSIM)
For verification
Device variations
Process design (?)
Hand analysis
Square law model (good for intuition only)
Small-signal model
Challenge
Complexity / accuracy tradeoff
How can we accurately design when large signal models
suitable for hand analysis are off by 50% and more?

EECS 240 Topic 4: MOS Models for Design 2007 B. Boser & A. Niknejad
 More Square Law Model
In saturation:

Familiar but inadequate for short channel devices

do not use!
EECS 240 Topic 4: MOS Models for Design 2007 B. Boser & A. Niknejad
 Cox
Square law:

Extracted values
strong function of ID

Low ID
weak inversion
Large ID
mobility reduction

Do not use Cox for

design!
EECS 240 Topic 4: MOS Models for Design 2007 B. Boser & A. Niknejad
Threshold Voltage VTH
Strong function of L
Use long channel for VTH
matching

Process variations
Run-to-run ~100mV
How characterize?
Slow/nominal/fast
Both worst-case & optimistic

Good design insensitive to Vth, only depends on mismatch in

Vth (can be <1mV for good layout and large devices)

EECS 240 Topic 4: MOS Models for Design 2007 B. Boser & A. Niknejad
 Device Parameters for Design
Focus on metrics that we can directly use in design
Region: moderate inversion / saturation
Most common region of operation in analog circuits
XTR behaves like transconductor: voltage controlled current
source
Key design parameters
Large signal
Current ID power dissipation
Minimum VDS available signal swing
Small signal
Transconductance gm speed / voltage gain
Capacitances CGS, CGD, speed
Output impedance ro voltage gain

EECS 240 Topic 4: MOS Models for Design 2007 B. Boser & A. Niknejad
 Low Frequency Model
A Taylor series expansion of small signal current
gives (neglect higher order derivatives)

How do we determine the values of the derivatives?

EECS 240 Topic 4: MOS Models for Design 2007 B. Boser & A. Niknejad
 Weak Inversion gm
In weak inversion we have bipolar behavior

Good model if transistor is actually used in

weak inversion
EECS 240 Topic 4: MOS Models for Design 2007 B. Boser & A. Niknejad
 Transconductance

weak strong inversion

inversion

EECS 240 Topic 4: MOS Models for Design 2007 B. Boser & A. Niknejad
 Transconductance (cont)
The transconductance increases linearly with Vgs
VT but only as the square root of Ids. Compare this to
a BJT that has transconductance proportional to
current.
In fact, we have very similar forms for gm

Since Vdsat >> Vt, the BJT has larger

transconductance for equal current.
Why cant we make Vdsat ~ Vt ?

EECS 240 Topic 4: MOS Models for Design 2007 B. Boser & A. Niknejad
 Transconductor Efficiency

A good metric for a transistor is the transconductance

normalized to the DC current. Since the power dissipation is
determined by and large by the DC current, wed like to get the
most bang for the buck.
From this perspective, the weak and moderate inversion region
is the optimal place to operate.

EECS 240 Topic 4: MOS Models for Design 2007 B. Boser & A. Niknejad
 Efficiency gm/ID
High efficiency is
good for low power

Higher gm/ID at low

VGS
Approaches BJT for
VGS < VTH

gm/IC = 1/Vt ~ 40 V-1

NMOS / PMOS
about same

EECS 240 Topic 4: MOS Models for Design 2007 B. Boser & A. Niknejad
Efficiency as a Design Parameter

If gm/ID is such a good metric, why not use it

for design?

We can always determine its precise value

(from ID and gm), independent of short
channel effects and other complications.

The units (V-1) and physical interpretation are

a little unusual, but we can easily fix this

EECS 240 Topic 4: MOS Models for Design 2007 B. Boser & A. Niknejad
 Efficiency gm/ID
Lets define

e.g. V* = 200mV gm/ID = 10 V-1

Square-law devices: V* = VGS-VTH = Vdsat

EECS 240 Topic 4: MOS Models for Design 2007 B. Boser & A. Niknejad
 Output Resistance ro

Hopeless to model this with a simple equation

(e.g. gds = ID)

EECS 240 Topic 4: MOS Models for Design 2007 B. Boser & A. Niknejad
 Open-loop Gain av0

More useful than ro

Represents maximum attainable
gain from a transistor

Simulation Notes:
Bias current idc sets V*
Use feedback to find the correct
VGS while sweeping Vds
Use relatively small gain (100)
for fast DC convergence

EECS 240 Topic 4: MOS Models for Design 2007 B. Boser & A. Niknejad
 Gain, av0 = gm ro
L = 0.18m

Strong tradeoff:
av0 versus VDS range

Create such plots for

several device
length for design
reference

EECS 240 Topic 4: MOS Models for Design 2007 B. Boser & A. Niknejad
 Long Channel Gain
L = 0.35m

L av0

like long channel device

EECS 240 Topic 4: MOS Models for Design 2007 B. Boser & A. Niknejad
 Technology Trend
Short channel devices suffer from reduced per transistor gain

EECS 240 Topic 4: MOS Models for Design 2007 B. Boser & A. Niknejad
 Transistor Gain Detail
45.000

33.775
gmro

22.550

11.325

0.100

0.02 0.06 0.1 0.14 0.18 0.22 0.26 0.3 0.34 0.38 0.42 0.46 0.5

VDS [V]

For practical VDS the effect the short-channel gain penalty is less severe
(remember: worst case VDS is what matters!)

EECS 240 Topic 4: MOS Models for Design 2007 B. Boser & A. Niknejad
 Saturation Voltage vs V*
Saturation voltage Vsat
VDS for which channel pinches off at drain
Cannot be measured
Complex equations
V* = 2ID/gm
Measure (or simulate) easily
Complex equations

Long channel (square law) devices:

VGS VTH = Vdsat = Vov = V*
Significance:
Channel pinch-off
ID ~ V*2
ro large for VDS > V*
CGS, CGD change
V* = 2 ID / gm

Short channel devices:

All interpretations of V* are approximations
Except V* = 2 ID / gm (but V* Vdsat)

EECS 240 Topic 4: MOS Models for Design 2007 B. Boser & A. Niknejad
 NMOS/PMOS Small-Signal
AC Model

gmb vbs

Bulk usually connected to substrate for NMOS

EECS 240 Topic 4: MOS Models for Design 2007 B. Boser & A. Niknejad
 SPICE Charge Model
Charge conservation

MOSFET:
4 terminals: S, G, D, B
4 charges: QS + QG + QD + QB = 0 (3 free variables)
3 independent voltages: VGS, VDS, VSB
9 derivatives: Cij = dQi / dVj, e.g. CG,GS ~ CGS
Cij != Cji

Ref: HSPICE manual, Introduction to Transcapacitance, pp. 15:42, Metasoft, 1996.

EECS 240 Topic 4: MOS Models for Design 2007 B. Boser & A. Niknejad
 Small Signal Capacitances
Weak inversion Strong inversion Strong inversion
linear saturation

CGS Col CGC/2 + Col 2/3 CGC + Col

CGD Col CGC/2 + Col Col

CGB CGC // CCB 0 0

CSB CjSB CjsB + CCB/2 CjsB + 2/3 CCB

CDB CjDB CjDB + CCB/2 CjDB

EECS 240 Topic 4: MOS Models for Design 2007 B. Boser & A. Niknejad
 MOS Capacitance Example
W/L=100/0.5
Cox=0ox/tox=15fF/m2
Col=0.5fF/m->Covlap=50fF
Cgs,si=2/3CoxWL+Col=550fF
Cgd,si=Covlap=50fF

Cgs,triode=1/2CoxWL+Co=425fF
Cgd,triode=1/2CoxWL+Co=425fF

Cgs,wi=Covlap=50fF
Cgd,wi=Covlap=50fF Inaccurate, residual Cgs left

EECS 240 Topic 4: MOS Models for Design 2007 B. Boser & A. Niknejad
 Layout
HSPICE geo = 0 (default)

HSPICE geo = 3

EECS 240 Topic 4: MOS Models for Design 2007 B. Boser & A. Niknejad
 Extrinsic MOS Capacitances
Source/drain diffusion junction capacitance:

Example: W/L = 100/0.5, VSB = VDB = 0V, Ldiff = 1m

AS = AD = 100m2, PS = PD = 102m
Cjn = 85fF Cjswn = 50fF Cbc = 58fF

Strong Inversion
Saturation: Csb = 173fF Cdb = 135fF
Linear region: Csb = 164fF Cdb = 164fF

EECS 240 Topic 4: MOS Models for Design 2007 B. Boser & A. Niknejad
High Frequency Figures of Merit
Unity current-gain bandwidth

(Long channel model, Cgd=0)

For degenerate short channel device

EECS 240 Topic 4: MOS Models for Design 2007 B. Boser & A. Niknejad
 Efficiency gm/ID versus fT

Speed-Efficiency
Tradeoff
NMOS > PMOS

EECS 240 Topic 4: MOS Models for Design 2007 B. Boser & A. Niknejad
Weak Inversion Frequency Response
The gate channel capacitance capacitance in
weak inversion ~0:Cgs ~ Cgsol
fT~25Id/Cgsol
Expression for channel capacitance and fT

IM is the maximum achievable current in weak

inversion so the factor ( ) < 1

Ref: Tsividis, Operation and Modeling of the MOS Transistor

EECS 240 Topic 4: MOS Models for Design 2007 B. Boser & A. Niknejad
 Device Scaling

Short channel devices are significantly faster!

EECS 240 Topic 4: MOS Models for Design 2007 B. Boser & A. Niknejad
 Device Figure-of-Merit
400.00

300.05
fTgm/ID [GHz/V]

200.10

100.15

0.20
-0.1 -0.06 -0.02 0.02 0.06 0.1 0.13 0.17 0.2 0.23 0.27 0.3 0.33 0.430000000000001
VGS-VTH [V]

Peak performance for low VGS-VTH (implies low V*)

EECS 240 Topic 4: MOS Models for Design 2007 B. Boser & A. Niknejad
 Design Example
Example: Common-source amp
av0 > 70, fu = 100MHz for CL = 5pF

av0>70L=0.5m

Highgmeff:V*=100mV

EECS 240 Topic 4: MOS Models for Design 2007 B. Boser & A. Niknejad
 Device Sizing
Pick L 0.5m
Pick V* 100mV
Determine gm 3.14mS
ID = 0.5 gm V* 157A
W from graph
(generate with SPICE)
Current Density=0.8uA/square
Corresponds to W/
L=157/0.8=196.25
W=W/L*L=98um
Cgs=600fF,Cgd=50fF
Create such graphs for
several device lengths for
design reference

EECS 240 Topic 4: MOS Models for Design 2007 B. Boser & A. Niknejad
 Common Source Verification

Amplifier gain > 70

Amplifier unity gain frequency is dead on
Output range limited to 0.12 V 1.2 V to maintain gain
(about 1V swing, due to NMOS not limiting gain on high side)

EECS 240 Topic 4: MOS Models for Design 2007 B. Boser & A. Niknejad
 Common Source Verification

Vmin=0.12V

Amplifier gain > 70

Amplifier unity gain frequency is dead on
Output range limited to 0.12 V 1.2 V to maintain gain
(about 1V swing, due to NMOS not limiting gain on high side)

EECS 240 Topic 4: MOS Models for Design 2007 B. Boser & A. Niknejad
 Small Signal Design Summary
Determine gm (from design objectives)

Pick L
Short channel high fT
Long channel high ro, av0, better matching

Pick V* = 2ID/gm based on qualitative interpretation of V*

Small V* large signal swing, high current efficiency
High V* high fT
Also affects noise (see later)

Determine ID (from gm and V*)

Determine W (SPICE / plot) this takes care of short channel effects, etc.

Accurate for short channel devices key for design

EECS 240 Topic 4: MOS Models for Design 2007 B. Boser & A. Niknejad
 Device Sizing Chart

Generate these curves for a variety of Ls and device flavors

(HW1)(NMOS, PMOS, thin oxide, thick oxide, different VTH)

EECS 240 Topic 4: MOS Models for Design 2007 B. Boser & A. Niknejad
Device Parameter Summary
Device Parameter Circuit Implications
V* Current efficiency, gm/ID
Power dissipation (ID)
Speed (gm)
Cutoff frequency, fT phase margin, noise
Headroom, VDS,min
L Cutoff frequency, fT phase margin, noise
Intrinsic transistor gain (av0)
W Obtain from L, ID (complicated equations!)
Self loading (CGS, CDB, )

EECS 240 Topic 4: MOS Models for Design 2007 B. Boser & A. Niknejad
 Device Variations
Run-to-run parameter variations:
E.g. implant doses, layer thickness, dimensions
Affect VTH, , Cox, R,
How model in SPICE?
Nominal / slow / fast parameters (tt, ss, ff)
E.g. fast: low VTH, high , high Cox, low R
Combine with supply & temperature extremes
Pessimistic but numerically tractable
improves chances for working Silicon

EECS 240 Topic 4: MOS Models for Design 2007 B. Boser & A. Niknejad
EECS 240 Topic 4: MOS Models for Design 2007 B. Boser & A. Niknejad