CHAPTER 1

Outline:
1) Device structure and physical operation
2) Current and voltage characteristics
3) MOSFET circuit at DC
4) Biasing in MOS amplifiers circuits
5) Small signal operation and models.
6) MOSFET as an amplifier and as a switch
7) Single stage MOS amplifier
8) Spice MOSFET models and examples

There are two major types of three terminal semiconductor devices

1. Metal oxide semiconductor field effect transistor
2. Bipolar junction transistor.

The FET differs from BJT in the following ways

1. It is a unipolar device
2. It is simpler to fabricate
3. Occupies less space in integrated form (packaging density is high > 200 million)
4. It has higher input resistance.
5. It functions as a memory device.
6. It can be used as symmetrical bilateral switch.
7. No offset voltage at zero input, making excellent signal chooper.
The only disadvantage is it has smaller gain bandwidth product than BJT.

Device structure:

Figure: Cross sectional view of enhancement type NMOS transistor.

1
 The transistor is fabricated on a p type substrate, single crystal silicon wafer that
provides physical support to the device.
Two heavily doped n type regions indicated in figure as n+ source n+ drain.
A thin layer of SiO2 of thickness tox (typically 2.50nm) as excellent insultor is grown on
surface of substrate.
Metal is deposited on top of the oxide layer to form gate electrode.
Metal contacts are also made to source drain and substrate known as body.
MOSFET is also known as IGFET since the gate electrode is electrically insulted from
substrate.
The current will flow in longitudinal direction from drain to source in the region labeled
channel region This region has length L(0.1m-3 m) and a width W (0.2m-100
m)
MOSFET is a symmetrical device, its source and drain can be interchanged with no
change in device characteristics.

Types of MOSFETS:

1) P Channel MOSFET(PMOS)
2) N Channel MOSFET (NMOS)

MOSFETs are available in two basic forms:

1) Depletion type:

The transistor requires the gate source (VGS) to switch the device off. The
depletion mode MOSFET is equivalent to a normally closed switch.

2) Enhancement Type:

The transistor requires the gate source (VGS) to switch the device on. The
enhancement mode MOSFET is equivalent to a normally open switch.

2
Device operation:

With no bias voltage:

With no bias voltage to the gate, two back to back diodes exists in series between drain
and source. They prevent current conduction from drain to source when VDS is applied. The
path between drain and source has a very high resistance.

Creating a channel for current flow:

The source and drain are grounded and a positive voltage to the gate.
The positive voltage on the gate causes the free holes (which are positive charged) to be
repelled from the region of thee substrate under the gate. These holes are pushed down
wards into the substrate leaving behind a carrier depletion region as shown in the figure
below.

The positive gate voltage attracts electrons from N+ source and drain into the channel
region. When a sufficient number of electrons accumulate near the surface of the
substrate under the gate connecting the source and drain region as shown in the figure.
This MOSFET is called n channel MOSFET or alternatively NMOS transistor.
The induced n region thus forms a channel for current flow from drain to source.
The value of VGS at which a sufficient number of mobile electrons accumulate in the
channel region to form conducting channel is called the threshold voltage and is denoted
by Vt. The value of Vt is controlled during device fabrication and typically lies in the
range of 0.5V to 1.0V.

3
Applying a small VDS:
We now apply a small positive voltage VDS between drain and source as shown in the
figure

The voltage VDS causes current ID to flow through the induced n channel. Current is
carried by free electrons travelling from source to drain.
The magnitude of ID depends on the density of electrons in the channel, which in turn
depends on magnitude of VDS.
By convention, the direction of current flow is opposite to that of the flow of negative
charge thus the current in the channel ID will be from drain to source.
At VGS = Vt the current conducted is still negligibly small as VGS exceeds Vt more
electrons are attracted into the channel. The result is increased conductance or equivalently
reduced resistance, thus conductance of channel is proportional to the excess gate voltage (VGS
Vt) also known as effective voltage or overdrive voltage.
The figure shows the sketch of ID versus VDS characteristics for various values of VGS

4
Operation as VDS is increased:
As VDS is increased by keeping VGS constant as shown in figure. As we travel along the
channel from source to drain, the voltage (measured relative to the source) increases from 0 to
VDS. Thus the voltage between the gate and points along the channel decreases from VGS at the
source end to VGS VDS at the drain end.

Since the channel depth depends on this voltage we find that the channel is now no
longer of uniform depth. As VDS is increased, the channel becomes more tapered and its
resistance increases correspondingly.
When VDS is increased to the value that reduces the voltage between gate channel at
drain end to Vt i.e., VGD = Vt, VGS VDS = Vt, or VGS Vt = VDS. The channel depth decreases to
almost zero and the channel is said to be pinched off.
As the value reaches for VDS = VGS Vt, The drain current saturates and the MOSFET is
said to have entered the saturation region. VDSAT = VGS - Vt
The region of ID VDS characteristics obtained from VDS < VDSAT is called the triode
region.

5
 Increase in VDS causes the channel to
acquire a tapered shape. Eventually as VDS reaches
VGS Vt the channel is pinched off at the drain
end. Increasing VDS above VGS Vt has little effect
on the channel shape as shown in the figure

Derivation of the ID VDS relationship

The gate voltage VGS is applied between gate and source with VGS > Vt to induce a
channel. Assume that a voltage VDS is applied between drain and source.

The gate and the channel region form a parallel plate capacitor for which the oxide layer
serves as a dielectric.
If capacitance per unit gate area is denoted by Cox and thickness of oxide layer is tox then

Where is the permittivity of SiO2 ie.,

VGS > Vt to induce channel and VDS < VGS - Vt and the triode region of operation is assumed.
The gate and a channel region form a parallel plate capacitor with oxide layer as
dielectric. The capacitance of the strip is Cox * W * dx

6
 The find the charge stored on this strip of gate capacitance, we multiply capacitance by
effective voltage between gate and the channel at point x
[ ( ) ( )] ( )
Where negative sign accounts that dq is a negative charge.
The voltage VDS produce an electrified along the channel in the negative X direction.
( )
Hence ( )

The electric field causes the electrons dq to drift towards the drain a velocity dx/dt
( )
Ie., ( ) ( )

The resulting current I can be expressed as

( )

Substituting 1 and 2 in 3 we obtain

( )
( ) ( )

( ) ( ) ( )
Integrating on both sides x=0 to x=L and V(o) = 0 to V(L) = VDS

( ) ( ) ( ) ( )

Gives () ]

This is the expression for the ID - VDS characteristics in the triode region

When ( ) The MOSFET moves into saturation

Ie., ()

The process transconductance parameter is given as

Hence

{ () } ( ) for triode region

() ( ) for saturation region

Equation (4) and (5) we see that drain current is proportional to the ratio of the channel
width W and Channel length L

7
Characteristics of the P channel MOSFET
The Physical structure of P channel enhancement type MOSFET is as shown in the
figure

To induce a channel we apply a gate voltage i.e. more negative than Vt i.e. ()
To operate in triode region
()
i.e. the drain voltage must be higher than the gate voltage at least Vt . The current ID is given as
() ]

Where VGS, Vt, and VDS are negative and transconductance parameter is given by

is the mobility of holes in induced P channel

To operate in the saturation region, VDS must satisfy
()
The current ID is given by

()

Where VGS, Vt, and VDS are negative

Complementary MOS or CMOS:

8
 As the name implies, complementary MOS technology employs MOS transistor of both
polarities. At present time CMOS is most widely used of all IC technologies the figure below
shows cross sectional of a CMOS chip illustrating how the PMOS and NMOS transistors are
fabricated. While the NMOS transistors is implemented directly in the p type substrate, the
PMOS transistor is fabricated in specially created n region known as nwell

Current voltage characteristics:

Figure (a) below shows an n channel MOSFET with voltage VGS and VDS applied and
normal direction of current flows are indicated as shown

The iD VDS characteristics, which are family of curves each measured for different
value of VGS as shown in the figure (b)
The characteristics curve indicates three different regions The cutoff , Triode, and
Saturation. The saturation region is used if the FET operates as an amplifier. For operation as
switch the cutoff or triode regions are used.
The device is cut off when VGS < Vt. to operate FET in triode region we must first induce
a channel VGS > Vt and keep VDS small enough so that channel remains continues ie.,
VDS < VGS - Vt
In triode region iD VDS characteristics can be described by a relation

{ () }

Where is transconductance parameter

9
If is sufficiently small then neglecting last term we have

{ () }

The linear resistance RDS is given as

()

The ( ) voltage is also referred as overdrive voltage given as ()

To operate MOSFET as in the saturation region VGS > Vt and ()
In saturation region iD VDS characteristics can be described by a relation

()

Thus in saturation the MOSFET provides a drain current that is independent of the drain voltage
and is determined by the gate voltage according to the square law relationship.

The role of the substrate:

In most applications the sources terminal is connected to the substrate terminal and
therefore VSB = 0 and it has no effects
In integrated circuit substrate is connected to negative voltage, the depletion region around
channel increases, decreasing channel depth
Decreases in channel depth should be compensated by corresponding increases in Vt.

[ ] ( )

Where is threshold voltage for VSB = 0V

is the physical parameter
is the fabrication process parameter, given as

q is the electron charge

is the permittivity of silicon.
For PMOS

[ ]

Where is negative

10


From (1) it indicates that incremental change in VSB gives rise to incremental change in Vt
which in turn result in incremental change in ID even though VGS has been kept constant, Thus
body voltage controls ID a phenomenon known as the body effect.

Temperature effect

Both Vt and are temperature sensitivity.

The magnitude of Vt Decreases by about 2mv for every 10 C rise in temperature, the
decreases in Vt gives corresponding increases in drain current however, because
decreases with temperature and its effect is dominant one, the overall observed effect
temperature is a decreases in current.

Breakdown
As the voltage on drain is increased a value is reached at which the pn junction between
drain region and substrate suffers avalanche break down and results in rapid increases in current.
Another breakdown that occurs in modern devices is punch through. It occurs in devices with
relatively short channels. When drain voltage is increased to the point that the depletion region
surrounding the drain region extends through channel to the source. The drain current increases
rapidly.
When gate to source voltage exceeds 30V this is the breakdown of gate oxide and results
in permanent damage of devices.

Finite output resistance

W.K.T in saturation ID is independent of drain voltage VDS

() ( )

Defining output resistance

Thus a change in in drain to source voltage causes a zero change in ID

11
 Which means incremental resistance is infinity i.e. ideally in VDS has no effect on
channel shape but in practice increases in VDS beyond VDSat affects the channel length i.e.
channel pinch off point is moved slightly away from the drain towards source. This is as shown
in figure

The additional voltage acceralates the electrons that reaches drain end of the channel and
sweeps across the depletion region into the drain. This phenomenon is known as channel length
modulation
Hence the equation (1) can be written as

()

()

We assume is proportional to VDS

Where is a process technology parameter with the dimensions of m/v we obtain

()

Usually is denoted by

() ( )

Typically set id VDS characteristics is as shown in the figure

12
The straight lines are extrapolated they intercept on VDS axis at the point VDS = -VA, id = 0.

VA is process technology parameter and is proportional to channel length L hence

Defining output resistance

( )

Substituting (2) in (3)

()

Which can be written as

Or equivalently

Where ID is the drain current without channel length modulation taken into account

()

MOSFET circuit at DC

1) Design a circuit of figure so that the transistor operates at ID = 0.4mA and VD = 0.5V the
NMOS transistor has Vt = 0.7V , = 100A/V2, L = 1m and W = 32m neglect
channel length modulation

VD = 0.5V > VG i.e. transistor is in saturation

Hence

()

()

13
Thus
()

WKT VG = 0V

( )

2) Redesign the Circuit for the above example for the following case VDD = - VSS = 2.5V, Vt
= 1V , = 60A/V2, W/L = 120m / 3m ID = 0.3mA and VD = 0.4V.

()

( )

14
3) Design a circuit of figure so that the transistor operates at ID = 80A find the value required
for R and DC voltage VD. Let the NMOS transistor has Vt = 0.6V, = 200A/V2, L =
0.8m and W = 4m neglect channel length modulation.

VDG = 0V and VD = VG the FET is operating in saturation region

()

()

VG = VD = 1V

4) Redesign a circuit of figure to double the value of ID without change in VD. Give new values
for W/L and R
()

( )

5) Design a circuit of figure let voltage VD be applied to the gate of another transistor Q2 as
shown in the figure assume that Q2 is identical to Q1. Find the drain current and voltage of

15
 Q2., Given = 200A/V2, L = 0.8m, W = 4m and VOV = 0.4V. Neglect channel
length modulation.
()

6) Design a circuit of figure to establish a drain voltage of 0.1V. What is the effective
resistance between drain and source at this operating point let Vt = 1V, = 1mA/V2.

{ () }

{ }

7) If in the circuit the value of RD is double, find approximate value for ID and VD

RD value is doubled i.e. 2*RD = 12.4K*2 = 24.8K

VGS = 5V since VG is connected to VDD and VS is connected to ground.

{ () }

{ } ( )

16
 Comparing (1) & (2)

{ }

We know that

Hence we choose , only then the device remains in triode.

8) Analyze the circuit as shown in the figure to determine the voltage at all nodes and the

current through all branches. Let V1 = 1V and 1mA/V2. Neglect the channel length

modulation effect

Ans:

17
 ( )
( )

Also
Gate voltage is determined by the voltage divider formed by the two 10M resistor
Hence,

Assume the transistor is in saturation from figure we have

Thus is given by

()

18
 Solving quadratic equation we have

Greater than gate voltage doesnt make any physical sense hence

Thus the transistor is in saturation as assumed.

9) For the circuit shown what is the largest value that RD can have while transistor in the
saturation mode.
According to condition

If the device should remain in saturation means the

value of
Hence

We also have

10) Redesign the circuit for the following requirements VDD = 5V, ID = 0.32mA, VS = 1.6V, and
VD = 3.4V with 1a of current through the voltage .

()

19
 ()

11) Design the circuit of figure so that the transistor operates in saturation with ID = 0.5mA and

VD = 3V. let the enhancement type PMOS transistor have Vt = -1V and 1mA/V2

Neglect the channel length modulation. What is the largest value that RD can have while
maintaining saturation region.

Since the MOSFET is saturation we have

()

because the MOSFET used is PMOS

()

20
 A possible selection is = 2M and = 3M

Note:

Normally the resistance and will be in terms of M

( )

Substituting in equation (1) we have

( )

Compare (1) and (2) we have

We have

Saturation mode operation will be maintained up to the point

21
 ( )

If the device should remain in saturation means the value of

Hence

12) The NMOS and PMOS transistors in the circuit shown in figure are matched with

1mA/V2 and Vtn = Vtp = -1V. Assuming = 0 for both devices, find the drain current

iDN and iDP as well as the voltage Vo, for V1 = 0V, +2.5V, -2.5V.

22
Case1: V1 = 0V

Since the circuit is symmetrical which dictates VI = 0V. We note that QN and QP are
perfectly matched and are operating at equal voltage (2.5) which dictates that Vo = 0V Thus
QN and QP are operating at VDG = 0V and hence in saturation the drain current is given by

()

Case2: V1 = 2.5V

23
Transistor Q2 Will have VGS of zero thus will be cut off reducing the circuit as shown
We note that Vo will be negative and thus VGD will be greater than Vt, causing QN to operate
in triode region and hence

{ () }

{ ( ) ( )} ( )

Also we have

( )

Solving (1) and (2)

We have
ID = 0.244mA and V0 = -2.44V

Case3: V1 = - 2.5V

The situation for this case will be exact complement of the case 2 causing QP to operate in
triode region
We have
ID = 0.244mA and V0 = +2.44V

24
MOSFET as an amplifier and as a switch :
Large signal operation The transfer characteristics: (graphical derivation of transfer
characteristics)
The figure below shows the basic structure of the MOSFET commonly used MOSFET
amplifier, the common source circuit or ground source circuit

The basic control of the MOSFET is the change in V GS changes in VI as VGS = VI gives
rise to change in ID we are using a resistor RD to obtain an output voltage Vo
VDS = VDD RDID --------- (1)
The straight line characteristics shown in figure is known as load line obtained as
When VDS = 0V in equ (1)
RDID = VDD
ID = VDD / RD
When ID = 0V in equ (1)
VDS = VDD

For any given value VI < Vt the transistor will be cutoff as shown in the ID VDS curve
and find Vo form the point of intersection of this curve with load line.
The circuit works as follows when VI < Vt the transistor will be in cutoff. ID will be zero
and Vo = VDD operation is labeled as A

25
 As VI exceeds Vt , the transistor turns on ID increases and Vo decreases. Since Vo will
initially be high the transistors will be operating in saturation region. This corresponds to
points along the segment of the load line from A to B
At the Q point we have VGS = VIQ and has the coordinates V0Q = VDSQ and IDQ.
Saturation region continues until V0 decreases to the point that is below VI by Vt volts.
At this point VDS = VGS Vt the MOSFET enters to triode region. This indicated in
figure as point B ie., VOB = VIB Vt
For VI > VIB the transistor is driven deeper into triode region, the output voltage
decreases to zero, point C is obtained for VI = VDD
Transfer characteristics operation as an amplifier as shown in the figure

Operation as a Switch
When MOSFET is used as a switch it is operated at the extreme points of the transfer
characteristics curve

Specifically the device is turned off by keeping VI < Vt resulting some where in the
region X A as shown in the figure
The switch is turned on by applying a voltage close to VDD resulting in operation
close to point C with Vo very small.

26
Operation as a linear amplifier

To operate MOSFET as an amplifier we make use of the saturation mode segment of

the transfer curve.
The device is biased at a point located somewhere close to middle of the curve point
Q is called quiescent point
The voltage signal to be amplified Vi is then superimposed on the DC voltage, It is
shown in figure. It can be seen that the amplifier will be very linear, the output
voltage Vo will be larger by a factor equal to the voltage gain of the amplifier at Q

The voltage gain is equal to the slope of the transfer curve at the bias point.

Analytical Expression for the transfer characteristics

The transfer characteristics showing operation of an amplifier

27
Saturation region conditions

() ( )

( )
Substituting (1) in (2)

() ( )

Voltage gain

Differentiating we obtain

() ( )

Substitute VI = VIQ and VO = VOQ in equation (3) and utilizing equation (4) and
substituting () We obtain

[ ( )]

[ ( )]

[ ( )]

Dividing by VOV
[ ]

Form equation (4) we have

[ ]

[ ]

The end point of saturation is given as

VOB = VIB Vt

28
The triode region operation
Triode region conditions

We have

{ () } ( )

( )
Substituting (1) in (2)

[( ( )) ]

For a portion of segment where V0 is small

[( ( )) ]

[( ( )) ]

( )
[( ( )) ]

We Have

[( ( )) ]

Equation (3) can be written as

Usually
Hence

Voltage gain

29
Differentiating we obtain

() ( )

Substitute VI = VIQ and VO = VOQ in equation (3) and utilizing equation (4) and
substituting () We obtain

[ ( )]

[ ( )]

[ ( )]

Dividing by VOV
[ ]

Form equation (4) we have

[ ]

[ ]

30
Biasing in MOS amplifier circuit
1. Biasing by fixing VGS
The most straight forward approach to biasing a MOSFET is to fix its gate to source
voltage VGS to the value required to provide the desired ID

()

Biasing by fixing VGS is not a good technique

Vt, Cox, and W/L vary widely among devices
Vt and n depends on temperature

Observe that for fixed value VGS the resultant spread in value of current.

2. Biasing by fixing VG and connecting a resistance in the source

Fixing the DC voltage at the gate VG, and connecting a resistance in the source lead as
shown in the figure
VG = VGS + RSID

31
 Resistor RS provides negative feedback, which acts to stabilize the value of the bias
current ID. This gives it the name degeneration resistance.
The figure provides a graphical illustration of ID VGS characteristics. The intersection
of straight line with characteristics curve provides bias points.
Compared to fixed VGS, here the variability of ID decreases.
Two possible practical discrete implementation of the bias scheme are as shown in the
figure.

Problem
1. It is required to design the circuit of figure to establish a DC drain current ID = 0.5mA. The

MOSFET is specified to have Vt =1V and for simplicity. Neglect the

channel length modulation effect = 0 use power supply VDD =15V calculate the
percentage change in the value of ID obtained when the MOSFET is replaced with

another unit having the same but Vt = 1.5V

32
Solution:

Rule of thumb for designing this classical biasing

network
We choose RS and RD to provide 1/3 of the power
supply voltage VDD as a drop across
1) RD 2) The transistor VDS 3) RS

This choice makes VD= 10V and VS = 5V

33
 To determine VGS

()
()

To establish this voltage at the gate select RG1 M an RG2 M

Note: Normally the resistance and will be in terms of M

( )

Substituting in equation (1) we have

34
 ( )

Compare (1) and (2) we have

If the NMOS transistor is replaced with another having Vt = 1.5V the new value of ID can be

()

( )

We have
R
( )
Solving (1) and (2)
( )

( )

Substitute (4) in (1)

( )
( )

Thus change in iD is

35
 Hence % change in id is given as

2. Consider the MOSFET as shown in the figure when fixed VGS is used. Find the required
value of VGS to establish a DC bias current ID =0.5mA. Given the device parameters are Vt =

1V, and = 0. What is the percentage change in iD obtained when the

transistor is replaced with another having Vt = 1.5V.

Solution:

()
()

36
 If the MOS transistor is replaced then

()

Since VGS is fixed

We have

Hence % change in id is given as

3. Biasing using a drain to gate feedback resistor

A simple and effective discrete biasing arrangement utilizing a feedback resistor

connected between drain and gate is as shown in the figure

The large feedback resistance RG (usually in the M

range) forces the DC voltage at the gate to be equal to that
at the drain
Hence

( )

If id value changes for some reason, say increases then equation (1) indicates that V GS must
decreases. The decreases in VGS in turn causes a decrease in id.

37
Problem:
Consider the circuit as shown in the figure to operate at DC drain current of 0.5m Assume

VDD = 5V, , Vt = 1V and = 0 use a standard 5% resistance value for RD,

and give the actual value obtained for iD and VD.

Solution:
Here VGS and VDS are of same voltage

()

()
()

38
 an ar res s ance K

4. Biasing using a constant current source

The most effective scheme for biasing for a MOSFET amplifier is that using a constant
current source as shown in the figure

39
 Here RG establishes a DC ground at the gate and presents a large resistance to an input
signal source that can be capacitively coupled to the gate.

RD establishes an appropriate DC voltage at the drain ensuring that the transistor always
remain in saturation region

A circuit for implementing the constant current source I is shown in figure (b). The
heart of the circuit is transistor Q1 whose drain is shorted to gate thus operating point in
saturation region

( ) ()

Where = 0. The Drain current Q1 is supplied by VDD through resistor R

( )
( )

Where current through R is considered to be the reference current.

Transistors Q2 it has the same VGS as Q1 thus if we assume that it is operating in
saturation its drain current

( ) () ( )

Relating (1) and (2)

( )

( )
Thus this circuit is known as current mirror circuit.

Problem:

Using two transistor Q1 and Q2 having equal lengths but widths are related ( ) ,

design the circuit which is as shown in the figure to obtain I = 0.5mA. Let V DD = - VSS =5V,

( ) , Vt = 1V, and = 0. Find the required value of R. what is the voltage

at the gates Q1 and Q2 ? what is the lowest voltage allowed at the drain of Q2 while Q2
remains in the saturation region.

40
Solution:

( )

( )

( )

( )

()
()

( )

41
 ( )

Lowest voltage at Q2 such that Q2 remains in saturation

()

Small signal operation and models:

The linear amplification can be achieved by biasing the MOSFET to operate in the
saturation region and by keeping the input signal small.
The common source amplifier circuit is as shown in the figure

The MOS transistor is biased by applying a DC VGS. The

input signal to be amplified, VGS is as shown superimposed
on the DC bias voltage VGS.

The DC bias point

The DC bias current iD can be found by setting VGS to zero

()

The DC bias voltage at the drain is given by

42
 To ensure saturation
()
The signal current in the drain terminal consider VGS applied, Hence total
instantaneous gate to source voltage.

Resulting in

[ ( )]

[ () ]

() [ ] ()

First term is DC bias current

Third term represents a current component that is directly proportional to input signal.
Second term is a current component that is proportional to square of input signal and
is undesirable because it represents nonlinear distortion. To reduce nonlinear
distortion the input signal should be kept small so that

[ ] ()

()

Hence neglecting second term

Where
()
Transconductance parameter

( )]
In terms of overdrive voltage

43
 Figure below shows the graphical interpretation of small signal operation of the
enhancement MOSFET amplifier

The voltage gain

Total instantaneous drain voltage VD

( )

Thus the signal component of the drain voltage

Hence

The minus sign indicates that the output signal Vd is 1800 out of phase with respect
to input signal Vgs illustrated as shown in the figure

44
Small signal equivalent model:
FET behaves as a voltage controlled current source. It accepts VGS between gate and
source and provides current
id = gm VGS
Input and output resistance are very high ideally infinite

Exact model
The previous model assumes id is independent of VDS which is not true, because of the
effect of channel length modulation
This was modeled by finite resistance r0 between drain and source in parallel to
con rolle curren source yp cally of he or er of K o K

45
Whose value given as
ro = | VA|/iD
Where

Transconductance gm
Note:
Transconductance is the properly of certain electronics components.
It is the ratio of the current change at the output port to the voltage change at the
input
We have

gm is proportional to

To obtain larger transconductance, the device must be short and wide

gm is also proportional to VOV.

Another usefull expression of gm

( )

We have

()

46
 ()

()

() ( )

Substitute (2) in (1)

( )

This expression shows that

For a given MOSFET, gm is proportional to the square root of the DC bias current

At a given bias current, gm is proportional to

Yet another usefull expression may be obtained as

()

( )
()
Substitute (3) in (1)

( ( ))
()

47
The T equivalent model
The T model can be developed through a simple transformation of the previous
model
The figure below shows the circuit without ro

In figure (b) we have added a second gmVGS current source in series with the
original controlled source without using any change in circuit .

The newly crea e po n X s jo ne o he er nal as shown n he f gure The

ga e curren oesn change an re a ns zero

48
 A controlled current source gmVGS connected across its control voltage VGS, we can
replace this controlled source by a resistance ass shown in the figure

Here we observe ig is still zero

id = gmVGS
and

Including ro we have circuit as shown below

Equivalent T model is also referred as hybrid - o el
Modeling the body effect

When source and substrate are not shorted and substrate is tied to most
negative supply in the circuit. The body effect comes into effect and substrate
acts like second gate.
The signal VDS gives rise to a drain current component, written as gmbVbs where
gmb is body transconductance given as

VGS VDS = constant

Where

49
 Where lies in the range 0.1- 0.3
Small signal equivalent circuit model of a MOSFET in which source is not
connect to the body.

The common source (CS) amplifier:

A common source amplifier has source terminal connected between the input and
output. Input is applied between gate and source terminals.
The constant current source biasing is used

Where CS is the bypass capacitor

CC1 is the coupling capacitor.

50
 The signal to be amplified Vsig with an internal resistance is connected to the gate
through CC1.
The voltage signal resulting at the drain is coupled to the load resistance RL via.,
another coupling capacitor CC2.
The AC equivalent circuit can be obtained by replacing the MOSFET with its small
signal hybrid model and writing the remaining components between the respective
terminal of the MOSFET as shown

At the input ig = 0, Rin = RG

To voltage gain
( )
Overall gain

( )

To determine the amplifier output resistance Rout we set Vsig to zero ie., Replace with
short circuit
Rout = r0||RD

51
The common source amplifier with a source resistance
Generally a common source amplifier will have a source resistance to improve the
stability of the bias point but the resistance also causes negative feedback and hence the
voltage gain will be lesser when compared to CS amplifier without source resistance.

The CS amplifier with source the replacement of transistor by its T- equivalent model

52
 Here we w ll be neglec ng he channel leng h o ula on, s nce ro woul
complaint the analysis
Hence
Rin = Ri = RG

Thus we can use the value of RS to control the magnitude of VGS and thus ensure VGS
does not become too large and cause nonlinear distortion
The current id is given as

Thus including RS reduce by factor

The output voltage is given as

If RL

A ng res s ance RS re uce he ga n by a fac or ( gm Rs) this factor is called

amount of feedback
Because of its action in reducing gain RS is called source degeneration resistance.

53
The common gate amplifier:
By establishing a signal ground on the MOSFET gate terminal, a circuit
configuration named common gate (CG) or grounded amplifier is obtained.

The input signal is applied to the source and output is taken at the drain, with gate
forming a common terminal between the input and output ports which is ass shown in
figure

The small signal equivalent model of the CG amplifier is as shown in figure we have
selec e T e u valen o el for analys s of he c rcu

54
 The channel leng h o ula on s no cons ere e , we have no nclu e r0 nclu ng
ro woul co pl ca e he analys s

To keep loss in the signal strength small

The current ii is given by

Drain current

Output voltage is given by

Overall voltage gain

Finally output resistance is given as

Rout = r0=RD
Observations:
Unlike CS amplifier, which is inverting the CG amplifier is non inverting
While CS amplifier has high input resistance, the input resistance of CG
amplifier is low
The overall gain of amplifier is smaller by a factor .

55
Common drain or source follower:
By establishing a signal ground on the MOSFET drain terminal and using it as a
terminal to the input port between drain and gate, and the output port source and drain.
The figure below shows a common drain amplifier. Since the drain is to function as
signal ground, there is no need of resistor RD and it has eliminated.

The input signal is applied between gate and source through coupling capacitor CC1
and output signal at the MOSFET source is coupled at capacitor CC2 to a load resistor RL.

The small signal equivalent model of the CD amplifier is as shown in figure we have
selected T e u valen o el for analys s

56
 Rin = Ri = RG

Usually

Applying voltage divider rule

Voltage gain Av

Open circuit gain

If ro >> 1/ gm then AV0 becomes nearly unity thus voltage at the source follows that at the
gate giving the name source follower.
If ro>>RL

Overall gain is given as

57
 CHAPTER 2
SINGLE STAGE IC AMPLIFIER

Outline:
1) IC Design philosophy.
2) Comparison of MOSFET and BJT
3) Current source, Current mirrors and Current steering circuits.
4) High frequency response - General considerations.

IC design philosophy
IC fabrication technology poses constraints on and provides opportunities to the circuit
designers.
The chip area consideration dictate that large and even moderate value of resistors are to
be avoided.
Large capacitors for signal coupling and bypass are not to be used except as component
external to the IC chip. Even then, the number of such capacitors has to be minimum,
otherwise the number of pin terminals and hence its cost increases.
In IC design technology one should strive to realize as many as functions required using
MOS transistors only and when needed small MOS capacitors
MOS transistors can be sized i.e. their W and L values can be selected to fit wide range
of requirements.
CMOS process technologies capable of producing devices with 0.1m minimum
channel length small devices need to operate with DC voltage of 1V. While lower
voltage operation can help to reduce power dissipation but it poses lot of challenges to
circuit designers.
The MOS amplifier circuit will be designed almost entirely using MOSFETS of both
polarities i.e. NMOS and PMOS. They are readily available in CMOS process
technology.
CMOS is currently the most widely used IC technology for both analog and digital as
well as combined analog and digital applications.
Bipolar circuit can be combined with CMOS in innovative and exciting ways.

1
MOSFET Scaling

G E Moore predicted that the number of transistors in integrated circuit double after two
years.
The only way to accommodate a large number of transistors in given silicon area is to
reduce the size of the transistors.
The process of reducing vertical and horizontal dimensions of the MOSFET is called
Scaling.
Thus the scaled device is obtained by simply dividing the key dimensions of MOSFET
such as channel length (L), width (W), oxide thickness (tOX) and junction depth (Xj) by
scaling factor S as shown in the figure.

(a)Long channel MOSFET (b) Scaling of MOSFET with scaling factor s

There are mainly two types of scaling they are

1) Constant field Scaling
2) Constant voltage scaling.

2
1) Constant field scaling
In constant field scaling the MOSFET dimensions as well as supply voltages are
scaled by the same scaling factor s
The scaling of supply voltage and terminal voltages maintain same electric field such
scaling is also called as full scaling.
The constant field scaling offers benefits such as increased component density,
increased speed decreased cost.
MOSFET Current before scaling is given as

[ ]

After scaling of device the drain current becomes

[ ]

Hence the drain current decreases by scaling factor s

Before scaling the delay is given by

o Where C is total capacitance.

o V is the supply voltage and I is the current.
After scaling the delay is given as

( )( )

2) Constant voltage scaling

In constant voltage scaling the geometrical dimensions of the MOSFET are scaled by
scaling factor s while the supply voltages are kept constant.
In addition to this the doping densities are increased by factor of s 2 to maintain
charge and electric field relationship known as partial scaling.
Let CGS be the total gate oxide capacitance before scaling and given by

3
 The total gate capacitance after scaling is given as

Thus total capacitance decreases by a factors

MOSFET Current before scaling is given as

[ ]

After scaling of device the drain current becomes

[ ]

Hence the drain current increases by scaling factor s

Before scaling the delay is given by

o Where C is total capacitance.

o V is the supply voltage and I is the current.
After scaling the capacitance decreases by factor s where as the current increases
by factor s. Since delay is directly proportional to capacitance and inversely
proportional to current we conclude that the delay decreases by a factor of s2.

Short channel effects

We have seen that to achieve a higher integration density and performance, channel lengths
of MOSFETs have been continuously reduced however, in short channel effects such benefits
are obtained at the cost of increased short channel effects, such as
1) Drain induced barrier lowering
2) Punch through effect
3) Threshold effect
4) Gate tunneling currents
5) Hot carrier effects

4
Drain induced barrier lowering (IDBL)

A MOSFET is considered a short channel device when its channel length is of the order
of the depletion widths of the source and drain.
In a long channel MOSFET when gate voltage is sufficiently smaller than threshold
voltage, electrons from the source region are prevented from entering into the channel
due to the potential barrier of the source channel junction.
However, in short channel devices, the barrier is lowered by the drain electric field,
which eventually allows electron flow into the channel. This flow of electrons gives rise
to drain current, which in turn gives rise to sub-threshold leakage current and static
leakage power.
In short channel devices, DIBL effect is controlled by increasing the channel doping
however, such increased doping will degrade carrier mobility and hence the drain current.

Punch through
In short channel devices, the channel lengths are of the order of source/drain depletion
region thickness. When drain voltage is increased, the drain depletion region touches the
source depletion region. This condition is known as the punch through effect, in which
gate losses control of the channel and the drain current increases sharply.
The punch through effect is reduced by using thin gate oxide and high channel doping.

Threshold voltage roll-off

For the MOSFETS threshold voltage expression is derived with the assumption that the
depletion bulk charge in the channel region is due to gate voltage. This assumption is
valid only for long channel devices as the contribution of source/drain depletion charge
to channel depletion charge is negligible.
However as channel lengths are reduced, the contribution of source/drain depletion
charge increases hence the expression for threshold voltage predicts higher threshold
voltage than the actual value.
In short channel devices, as channel lengths are reduced the contribution of source/drain
depletion charge to the total charge in the channel increases and hence the threshold
value decreases as shown in the figure

5
 The reduction in threshold voltage eventually leads to higher sub threshold leakage
currents, which results in increased static power dissipation.

Gate tunneling effect

Short channel MOSFETs require very thin gate oxide to control the various short
channel effects. Such thin gate oxide layer consists of only four to five atomic layers and
electrons can easily tunnel through the thin oxide layer. The direct tunneling of electrons
across thin oxide eventually lead to gate oxide leakage current, which also increases the
power dissipation.
Hence tunneling current limit the further scaling of the oxide layer. To overcome this
problem, the conventional silicon dioxide is replaced with high dielectric constant (high
K) materials such as silicon nitride, hafnium oxide, etc.
The High-K material allows higher physical thickness than the conventional silicon
dioxide thickness for the same capacitance. Therefore, High-K materials decreases gate
tunneling and allows further scaling of MOS transistors.

Hot Carrier effect

The reduction of MOSFEET dimensions to achieve higher integration density and
performance increases lateral and vertical electric fields in the device.
The increased electric field increases the velocity of electrons and holes and hence their
kinetic energy.

6
 Electrons and holes with high kinetic energy are known as hot electrons and hot holes,
respectively. Due to high lateral and vertical electric field, hot electrons and holes strike
or penetrate into the oxide and get trapped at the Si-SiO2 interface as well as in the
oxide.
These trapped carriers modulate the threshold voltage of MOSFETs and degrade the
reliability.

7
Comparison of The MOSFET and The BJT

8
1) Operating conditions
We shall use active mode or active region to denote both active mode of operation of
BJT and saturation region mode of operation MOSFET.
The condition for operating in the active mode is very similar for two devices i.e. the
threshold voltage Vt of MOSFET and VBEOn in the BJT are almost same.
Both MOSFET and BJT to operate in active mode the voltage across the device must be
at least 0.2V 0.3V
Pinching off the channel in MOSFET at the drain end is very similar to reverse biasing
CBJ of BJT.
The asymmetry of BJT results in VBCOn and VBEOn being unequal, while the symmetrical
MOSFET the operative voltages at the source and drain ends of the channel are identical.

2) Current voltage characteristics

The square law control characteristics iD-VDS in the MOSFET should be contrasted
with exponential control characteristics iC-VBE of BJT.
The current IC can vary over wide range with in same BJT. In MOSFET the range of ID
is same device is much more limited.
Effects of device dimension on its currents
For BJT the control parameter is the area of emitter base junction AE which determine
the scale current IS. i.e. emitter area can be used to achieve current scaling
For MOSFET, the aspect ratio W/L can be designed in wide range. W/L is a very
significant MOS design parameter.
The channel length modulation in the MOSFET and base width modulation in BJT are
similar. In BJT VA is solely a process technology parameter and doesnt depend on
dimension of BJT where as in MOSFET VA = VA| L ie., VA| is process technology where
L is channel length.
The last important difference is the input current into the control terminal
The gate current of the MOSFET is zero ig = 0 and input resistance at gate is
practically infinite.
The BJT draws base current iB i.e. proportional to collector current i.e. iB = iC/
looking into this is a definite disadvantages of the BJT, in comparison to MOSFET.

9
 It is the infinite input resistance of MOSFET that has made possible analog and digital
circuit applications that are not feasible with BJT.

3) Low frequency small signal models

The small signal models of BJT and MOSFET is as shown

The low frequency models for the two devices are very similar except, for finite base
current of the BJT, which gives rise to in the hybrid model.
For both devices, the hybrid model indicates that the open circuit voltage gain
obtained from gate to drain (base to collector) with source (emitter)grounded is
The body effect in MOSFET gives raise to drain current component whereas the
body effect has no counterpart in the BJT.

4) The transconductance
For BJT gm depends only on the DC collector current iC. It is interesting that gm
doesnt depend on the geometry of BJT, and its dependence on EBJ area is only through
the effect of area on total collector current.
The dependence of gm on VBE is only through the fact that VBE determines the total
collector iC

i.e.

gm of MOSFET depends on iD, VOV and W/L ratio hence we use three different
formulas to express gm

10


5) Output resistance
The output resistance for both devices is determined by similar formulas

Thus both are inversely proportional to bias current, but the difference in nature and
magnitude of VA.

6) Input resistance

The input resistance of MOSFET is infinite whereas the BJT is given by .

7) Intrinsic gain
The intrinsic gain Ao of the BJT is the ratio of VA and VT. Thus Ao of a BJT is
independent of deice junction area and operating current.
Whereas for MOSFET intrinsic gain is given as

11
 From equation for given process technology parameter and and a given

device W/L the intrinsic gain inversely proportional to . This is illustrated as shown in the
figure.

8) High frequency operation:

The simplified high frequency equivalent circuit is as shown in the figure

The transition frequency ft of both MOSFET and BJT are very high. ft is a measure of
intrinsic bandwidth of transistor itself and doesnt take into account the effects of
capacitive load.

In both the cases ft is inversely proportional to the square of the critical dimensions of
device
From the expression of BJT it is clear that the ft is entirely process determined where
as in MOSFET ft is proportional to overdrive voltage.
Neglecting transistor capacitance, the voltage gain from gate to drain can be found as

12
 We have

Hence

Thus

Band width increases as bias current is increased

9) Design parameters
For BJT there are three design parameters iC , VBE and is of which two can be
selected by the designer.
iC is exponentially related to VBE and is very sensitive to the value of VBE.
It follows that for BJT there is one effective design parameter the collector current iC.
For MOSFETS there are four design parameter id , Vov L and W of which three
can be selected by the designer.

13
 For analog circuit the tradeoff is selecting value of L is between the higher speed of
operation.
Once values of L and Vov are selected the designer is left with the selection of the
value of id or W. For given process and selected values id is proportional to W/L
and has no bearing on intrinsic gain A0 and transition frequency ft.
The DC gain remains unchanged increasing W/L and corresponding iD increases the
bandwidth proportionally.

IC design current sources, current mirrors and current steering circuits

Biasing in integrated circuit design is based on the use of constant current sources.
On an IC with a number of amplifier stages a constant DC current (called reference
current) is generated at one location and is then replicated at various other locations for
biasing various amplifier stages through a process known as current steering.
This approach has an advantage that the effort expended on generating a predictable and
stable reference current usually utilizing a precision resistor to external to the chip need
not be repeated for every amplifier stages.

The basic MOSFET current source

The figure shows the circuit of a simple MOS constant current source

14
 The heart of circuit is transistor Q1, the drain of which is shorted to its gate, thereby
forcing it to operate in the saturation mode.

We neglect channel length modulation the drain current Q1 is supplied by VDD

through resistor R hence

Where current through R is considered to be the reference current of the current

source and is denoted IREF.
Now consider transistor Q2, it has same VGS as Q1 thus if we assume that it is
operating in saturation, its drain current which is output current Io.

Hence

( )

The above equation is known to be current gain or current transfer ratio.

The relationship between Io and IREF and the circuit simply replicates or mirrors
the reference current in the output terminal and hence the circuit composed of Q1 and
Q2 the name current mirror circuit.
The figure below depicts the current mirror circuit with input reference current
shown as being supplied by a current source for both simplicity and generality.

15
Effects of Vo on Io
We assumed Q2 to be in saturation. To ensure that Q2 is saturated the circuit to which
the drain is to be connected that must establish voltage Vo that satisfies the relationship.

or equivalently in terms of overdrive voltage

For simplicity consider identical devices Q1 and Q2. The drain current of Q2, Io will be
equal to the current of Q1, IREF at the value Vo that causes two devices to have same value VDS.
As Vo is increased above this value, Io will increase according to the incremental
output resistance ro2 of Q2 this is illustrated as shown in the figure which shows Io versus Vo

early voltge of Q2

Finally the current Iogiven as

MOS steering circuit

Once a constant current is generated it is replicated to provide DC bias currents for

various amplifier stages in an IC
Current mirror circuit can be used to implement this current steering function
The figure shows simple current steering circuit

16
 MOSFET Q1 together with R determine the reference current IREF transistor Q1,
Q2 and Q3 form a two output current mirror.

To ensure operation in saturation region the voltages at the drain of Q2 and Q3 are
constrained as follows
or

Where VOV1 is the overdrive voltage at which Q1, Q2 and Q3 are operating
The drain of Q2 and Q3 will have to remain higher than VSS by at least the
overdrive voltage.
From figure we see that current i3 is fed to the input side of a current mirror formed
by PMOS transistor Q4 and Q5 thus

Where I4 = I3 to keep Q5 in saturation its drain voltage should be

17
 Its important not that while Q2 pulls its current i2 from a load, Q5 pushes its
current i5 into a load thus Q5 is approximately called a current source where Q2
is called as current sink both current source and sinks are required.

BJT circuits

BJT current mirror work similar to MOS mirror however there are two differences
1) The non-zero base current of BJT causes an error in the current transfer ratio of
the bipolar mirror.
2) Current transfer ratio is determined by the relative areas of the E-B junction of
Q1 and Q2

The basic BJT current mirror is as shown

Consider the case when in sufficiently high so that we can neglect the base
currents
The reference current IREF is passed through the transistor Q1 and thus establishes
a voltage VBE which inurn applied in between base and emitter of transistor Q2
If Q2 is matched to Q1 more specifically if EBJ area of Q2 is same as Q1 the
collector current of Q2 will be equal to that of Q1 i.e.
Io = IREF
For this to happen Q2 must be operating in active mode which inturn is achieved as
long as collector voltage is higher than that of emitter.

18
 If current transfer ratio is other than unity say m we simply assume that the area of
EBJ of Q2 is m times that of Q1.
Io = m IREF
In general

Consider the effect of finite transistor for the case current transfer ratio is unity
and the transistor Q2 is matched to Q1 as shown in the figure

Equation at collector of Q1 yields

[ ]

Since

The current transfer ratio is given as

[ ]

As approaches current transfer ratio approaches unity.

The error in the current transfer ratio is significant. For instance for =100 results
in an 2% error in the current transfer ratio.

19
 The actual current transfer ratio is given as

[ ]

BJT mirror has a finite output resistance ro

Finally we can express output current of a BJT

[ ]

A simple current source

The basic BJT current mirror can be used to implement a simple current source as shown
in the figure

The reference current is

Where

20
 [ ]

The output resistance

Current steering

The current steering approach is used to generate bias current for different amplifier
stages. The current steering circuit is as shown in the figure.

The DC bias current is generated in the branch consist of transistor Q1 resistor R and
the transistor Q2

Assume all transistors have high and base current is negligibly small. The transistor
Q1 forms a current mirror with Q3 and thus Q3 will provide a constant current i1
equal to IREF.
Transistor Q3can supply this current to any load as long as the voltage that develops at
the collector doesnt exceed VCC, otherwise Q3 would enter the saturation.

21
 To generate a DC current twice the value of IRFF, two transistor Q5 and Q6each of
which is matched Q1 are connected in parallel and the combination forms a mirror with
Q1 thus I3= 2IREF where the junctional area of Q5 and Q6 are doubled that of Q1
this is done while fabricating ic.
Transistor Q4 forms a mirror with Q2 thus Q4 provides a constant I2 equal to IREF
In the circuit Q3 is called source and Q4 is called sink.
To generate a DC current thrice the value of IREF three transistors Q7 , Q8 and Q9
each of which is matched to Q2 are connected in parallel and combination forms a
mirror with Q2 thus in IC implementation Q7 , Q8 and Q9 can be replaced with a
transistor having junction area three times of Q2.

High frequency response General consideration

The various stages in IC cascade amplifier are directly coupled i.e. they do not utilize
large coupling capacitors.
The frequency response of these direct coupled or DC amplifier takes the general form
as shown in figure

The gain remains constant at its mid band compared to capacitively coupled amplifier
that uses bypass capacitors.
Direct coupled IC amplifiers do not suffer gain reduction at low frequencies.
The gain falls off at the higher frequency end due to internal capacitance of transistor.

22
High frequency gain function
By considering internal transistor capacitance the amplifier gain can be expressed as a
function of complex frequency variable S.
A(S) = AM FH(S)
Where AM is a mid-band gain, can be obtained by analyzing the amplifier equivalent
circuit, neglecting the effect of transistor internal capacitance.
Considering these capacitance into account the gain acquires factor FH(S), which can be
expressed in terms of poles and zeros
Hence

[( )( ) ( )]

( )( ) ( )

are positive numbers representing the frequency of the n real

numbers.
are positive, negative or infinite numbers representing the
frequency of the n real numbers.
If becomes unity then gain approaches unity.

Determining 3-DB frequency fH

The amplifier designer is practically interested in the part of the high frequency band.
This is because the designer need to estimate and if need to modify.
If one of the pole Wp1 is of much lower frequency than the other poles then this pole
has greatest effect on the value of WH and the amplifier is said to have dominant pole
response in such case

[ ]

Which is the transfer function of first order filter. It follows that if a dominant pole exists,
then the determination of WH is generally simplified.

If dominant pole doesnt exists the 3 DB frequency WH can be determined as follows

Consider we have two poles and zeros in high frequency band i.e.

23
 [( )( )]

[( )( )]

Substituting S=jW and squaring the magnitudes

[( )( )]

[( )( )]

[( )( )]

[( )( )]

[ ]

[ ]

Since WH is usually smaller than the frequencies of all poles and zeros we may neglect
the terms containing WH4 and solve for WH.

This relation can be extended to any number of poles and zeros

( ) ( )

Using open circuit time constant for the approximate determination of FH

Its not a simple matter to determine poles and zeros, by quick hand analysis. In such
cases an approximate value of fH can be obtained as follows we can represent FH(s) in
alternative form as

24
 [ ]
[ ]
Where a and b are related to the frequencies of zero and poles respectively.
The co efficient b1 is given as

( )

The value of b1 can be obtained by considering the various capacitances in the high
frequency equivalent circuit one at a time while reducing all other capacitance to zero.
To obtain contribution of capacitance Ci we reduce all other capacitance to zero, reduce
the input signal to zero and determine resistance Rin
This process is replaced for all other capacitance in the circuit. The value of b1 is
computed by summing individual time constant

If zeros are not dominant and if one of the poles say p1 is dominant then

| |
Millers theorem
The millers theorem refers to the process of creating equivalent circuit it asserts that a
floating impedance element, supplied by two voltages sources connected in series may
be splitted into two grounded elements with corresponding impedance
Consider the case as shown in the figure

25
 We have two circuit nodes labeled as (1) and (2) between impedance Z is connected
Node (1) and (2) are connected to other parts of the circuit as signified as broken lines
Assume voltage at node (2) is related to that at node(1) by
V2 = KV1
K- gain parameter
Hence according to miller theorem Z can replaced by two impedances Z1 connected
between node1 and ground and Z2 connected between node2 and ground.
Where

To keep the current unchanged in the equivalent circuit we must choose the value of Z1
so that it draws an equal current.

Similarly to keep the current into node2 unchanged we must choose the value of Z2 so
that

Millers equivalent circuit derived above is valid only as the rest of the circuit remains
unchanged.

26
27
28
 CHAPTER 3
SINGLE STAGE IC AMPLIFIER

The common - source circuit

The figure below shows the basic IC MOS amplifier with a grounded source MOS
transistor.

The drain resistor RD is replaced by a constant current source I and called as active
load.
The transistor Q1 is biased at ID = I and is operating in saturation region.
Small signal analysis is as shown in the figure below

From figure we see that

The maximum voltage gain available from a common source amplifier mainly intrinsic
gain of the MOSFET i.e.

1
CMOS implementation of the common source amplifier

The CMOS circuit implementation of the common source amplifier is as shown in the
figure

The Q2 and Q3 forms a current mirror circuits i.e. Q2 and Q3 are matched and thus
the I -V characteristics of the load device is as shown in figure

Thus by observing the graph we can come conclusion that Q2 behaves as a current
source when it operate in saturation.
When Q2 is operating in saturation it exhibits a finite incremental resistance r02 given
as
| |

Where IREF early voltage of Q2

2
 The figure below shows iD VDS characteristics of the amplifying transistor Q1 and
superimposed load curve on them i.e. i v curve in the figure (b) is flipped and shifted
VDD volts along the line.

The intersection of the each particular curve with the load curve gives corresponding
value of VDS1 which is equal to Vo.
Thus in this way we can obtain Vo - Vi characteristics. the resulting characteristics is as
shown in the figure

It has four distinct regions labeled as I II III and IV each one of is obtained from one of
the four combinations of the modes of operation of Q1 and Q2 which are also
indicated in diagram

3
 The region III in transfer characteristics curve is almost linear and very steep, indicating
large voltage gain.
In region III both amplifying transistor Q1 and the load transistor Q2 are operating in
saturation.
The end points of region III are A and B:
At A defined by , Q2 enters the triode region.
At B defined by , Q1 enters the triode region.
The small signal voltage gain is given as

( ) ( || )

The CMOS common source amplifier can be designed to provide voltage gains of 15 to
100
It exhibits a very high input resistance however its output resistance is also high.
The circuit is not affected by the body effect since the source terminals of both Q 1 and
Q2 are signal ground.
The circuit is usually part of a large amplifier circuit and negative feedback is utilized to
ensure that the circuit in fact operates in region III of the amplifier transfer
characteristics

The common emitter circuit

The active loaded common emitter amplifier shown in figure

4
 The small signal analysis is as shown in the figure

From figure we see that

However the intrinsic gain of the BJT is much higher than that of the MOSFET.
However this advantage is counter balance by the practically infinite input resistance of
the common source amplifier.

High frequency response of the common source and common emitter amplifier

The figure shows the high frequency response of the common source amplifier and
common emitter amplifier.

5
 The input signal form the source is represented by Vsig and Rsig, The bias resistor RG
or RB
RL represents the combination of actual load resistance and the output resistance of the
current source load. To avoid loss of gain the RL is the same order as ro. we can
combine RL and ro and denote it as RL|.
The load capacitance CL represents the total capacitance between drain and ground. It
includes both Cdb collector to substrate capacitance and the input capacitance of
succeeding amplifier stage.

Analysis Using Millers theorem

When Rsig is relatively large and CL is relatively small. Miller's theorem can be used
to obtain a quick but approximate estimate of the 3-dB frequency fH.
The figure shows the approximate equivalent circuit obtained for the CS case, from
which we see that the amplifier has a dominant pole formed by Rsig and Cin.

Thus we have

Where
|

The 3 dB frequency

i.e.

Where
|
( )

6
Analysis Using open circuit time constant
The method of open-circuit time constants can be applied to the CS equivalent circuit of
as illustrated in figure (b)

|
We see that the resistance seen by and is
The resistance seen by can be found by analyzing the circuit in above figure
with the result that
| |
( )
Thus the effective time-constant b, or H can be found as

| | |
[ ( ) ]
The 3 dB frequency

This approach yields a better estimate of .

7
Exact analysis

The approximate analysis provides insight about the limit in high- frequency gain of the
CS (and CE) amplifiers. Nevertheless, given that the circuit as shown in figure is
relatively simple, it will be good if we perform an exact analysis.

A node equation at the drain provides

( ) |

Which can be manipulated as

|
( )
|

A loop equation at the input yields

We have
( )
Hence
[ ( ) ]

|
[ ( )]
| | |
{[ ( )] ( ) } [( ) ]
( )

8
 The above transfer f u n c t i o n indicates t h a t the amplifier has a second-order
denominator, and hence two poles. Now, since the numerator is of the first order, it
follows that one of the two transmission zeros is at infinite frequency.
This is readily verifiable by noting that as s approaches , (V0 / Vsig) approaches zero.
The second zero is at

i.e. it is in the positive real axis of the s plane and has a frequency of WZ

Since gm is usually large and Cgd is usually small, fz is normally a very high
frequency and thus has negligible effect on the value of fH.
Finding the value of s at which V0= 0 that is, sz. The figure below shows the circuit at
S = sz. By definition, V0 = 0 and a node equation at D yields

Now, since Vgs is not zero, we can divide both sides by Vgs to obtain

We should note that in equation (A), as s goes toward zero, V0/Vsig approaches the
dc gain (-gmRL) as should be the case.
In the denominator polynomial, we observe that the coefficient of the s term is equal
to the effective time-constant H obtained using the open-circuit time-constants
method.
Denoting the frequencies of the two poles p1 and p2, we can express the denominator
polynomial D(s) as

9
 ( ) ( )( )

( ) ( )

Now if P2 >P1that is, the pole at PI is dominantwe can approximate D(s) as

( )

Equating the coefficients of the s term in denominator polynomial of Equation (A) to

that of the S term gives

| |
[ ( )] ( )
The above expression is identical to the result obtained using open-circuit time constants
and a little different from the result obtained using the Miller equivalence, the
difference being the term (C L+ Cgd)RL related to the capacitance at the output,
which was ignored in the original Miller derivation.
The frequency of the second pole is given as

| |
[ ( )] ( )
|
[( ) ]

The Common emitter amplifier

In the case of CE amplifier, the above formulae are straightaway adapted.

The Vsig and Rsig are modified to take into account the effect of rx and r.

Vsig = Vsig r / (Rsig + rx +r)

Rsig= r || (Rsig +rx)

10
 The DC gain is give as
AM = - (r)(gm RL) /(Rsig + rx +r)

Using millers theorem we obtain

Cin = C + C (1+ gm RL)

Correspondingly, the 3 dB frequency fH can be estimates as

fH = 1 /(2Cin Rsig )

Alternatively, using the method of open circuit time constant yields

H = C R + C R + CL RL
= C Rsig + C [(1+gm RL) Rsig + RL] + CL RL

From which fH can be estimated as

The exact analysis yields the following zero frequency

11
 Hence,

| | |
{[ ( ) ] ( ) }

| | |
{[ ( ) ] ( ) }
| |
[ ( ) ]

For

The situation when Rsig is low

In application where CS amplifier is fed a with low resistance signal source obviously
in such cases, the high frequency gain will no longer be limited by the interaction of the
source resistance and input capacitance. Rather, the high frequency limitation happens at
the amplifier output as we shown below
The figure shows the high frequency equivalent circuit of the common source amplifier
in the limiting case Rsig is zero

We have
|
[ ( )]
| | |
{[ ( )] ( ) } [( ) ]

12
 By substituting Rsig = 0 the above equation reduces to

|
[ ( )]
|
{( ) }
The high frequency response is now determined by a pole formed CL + Cgd together with
|
. Thus the 3 dB frequency is now given by

|
( )
To see how this pole is formed refer the figure below which shows the equivalent circuit
with input signal source set to zero. Observe the circuit reduces into capacitance (CL+Cgd)
|
in parallel with a resistance .

As we have seen above, the transfer-function zero is usually at a very high frequency
and thus does not play a significant role in shaping the high-frequency response. The
gain of the CS amplifier will therefore fall off at a rate of-6 dB/octave (-20 dB/decade)
and reaches unity (0 dB) at a frequency ft which is equal to the gain-bandwidth product.
| |
|
|
( )
Thus

|
( )
Figure shows a sketch of the high frequency gain of the CS amplifier.

13
The Common gate amplifier

The figure shows the basic IC MOS common-gate amplifier. The transistor has its
gate grounded and its drain connected to an active load, given as an ideal constant-
current source I.

The input signal source vsig with a generator resistance Rs is connected to the
source terminal. The MOSFET source is not connected to the substrate, hence the
substrate terminal, B, is shown explicitly and indicate that it is connected to the
lowest voltage in the circuit, i.e., to ground in this case.

14
 We may observe that except for showing the current-source I, which determines the dc
bias current ID of the transistor, no other bias detail is shown
In this case, we assume that the MOSFET is operating in the saturation region and
concentrate exclusively on its small-signal operation.

The body effect

Since the substrate (i.e. body) is not connected to the source, the body effect plays a role
in the operation of the common-gate amplifier. However, it turns out, that considering
the body effect in the analysis of the CG circuit is very simple.
The body terminal acts, as a second gate for the MOSFET. Thus, just as a signal voltage
vgs between the gate and the source gives rise to a drain current signal gmvgs, a signal
voltage vbs between the body and the source gives rise to a drain current signal
gmbvbs. Thus the drain signal current becomes (gmvgs + gmbvbs) where the body
transconductance gmb is a small fraction of gm ; gmb = gm and = 0.1 to 0.2.
Since in the CG circuit both the gate and the body terminals are connected to ground,
vbs = vgs, and the signal current in the drain becomes (gm + gmb)vgs. It follows that
the body effect in the common-gate circuit can be fully accounted for by simply
replacing gm of the MOSFET by (gm + gmb). As an example, Figure below shows
the MOSFET T-model modified in this way.

15
Small-Signal Analysis

The small-signal analysis of the CG amplifier can be performed either on an equivalent

circuit obtained by replacing the MOSFET with its T model of Figure(b) or directly
with model used implicitly.
The second approach is opted in order to gain greater insight into circuit operation. The
below figure shows the CG circuit prepared for small-signal analysis.

We have extracted ro of the MOSFET and shown it separately from the device. As well
as we have indicated the resistance 1/ (gm+gmb), which appears in effect between gate
and source looking into the source. A resistance RL is shown at the output.
The circuit of figure is analyzed to determine the various parameters that characterize
the CG amplifier. The CG amplifier is not a unilateral circuit; the resistance ro
connects the output node to the input node. As a result we should expect the amplifier
input resistance Rin to depend on RL and the output resistance Rout to depend on Rs.

16
Input resistance

Consider the circuit as shown in the figure

To determine the input resistance Rin, we must find a way to express Ii in terms of Vi.
Inspection of the circuit in Figure reveals a key observation. The input current Ii splits
at the source node into two components: the source current i = (gm + gmb) Vi and the
current through r0, iro These two components combine at the drain to constitute the
current Io supplied to RL, thus Io = Ii, and vo = Io RL= Ii RL. Now we can write at the
source node as
( ) ( )
And express iro as

( )

Equation (1) and (2) can be combined to yield

17
 ( )

( )

From which input resistance Rin can be found as

( )
Observe that , reduces to which is indeed the input resistance
( )

with r0 neglected.
When r0 is taken into account, this value of input resistance is obtained
approximately only for RL = 0. For the usual case of RL = ro, Rin = 2/(gm + gmb).
Interestingly, for large values of RL approaching infinity, Rin = .

Operation with RL =

The figure below shows the CG amplifier with R L removed i.e. RL = and the amplifier
is operating with open circuited

18
 We see that Io = 0, Ii must also be zero the current i in the source terminal i = (gm +
gmb)Vi simply flows through ro and back to the source node
It follows that the input resistance with no load Ri is infinite i.e Rin = .
We can also determine the open circuit voltage gain Avo between the input source and
output drain terminal as follows:

( )
Thus
( ) ( )
We observe that Avo differs from intrinsic gain of the MOSFET in two minor respects
1) There is an addition term of unity
2) gmb is added to gm typically Avo is 10% or 20% larger than Ao.
Unlike CS amplifier the CG amplifier is non- inverting.
W.K.T

( )
( )

Using equation (1) and (2) we have

( )

Since ( ) equation (3) reduces to

( )
This expression says that taking ro into account adds a component (RL/Ao) to the
input resistance.
Also When ii = 0 in the circuit Vi = Vsig and the open circuit overall voltage gain
Vo/Vsig will be equal to Avo
( )

19
Voltage gain

The voltage gains Av and Gv of the loaded CG amplifier of figure (as shown below)
can be obtained on the fact that io = ii and express Vo as

( )

The voltage Vi can be expressed in terms as ii as

( )
Dividing equation (1) by (2) we have

( )

We have

( )

Substituting equation (4) in (3) We have

20
 In a similar way we derive an expression for Gv

( )
Thus

( )

Substituting equation (4) in (5) We have

Recalling Gvo as Avo we can express Gv as

Output resistance

There are two different output resistances

1) Ro, which is the output resistance when vi is set to zero.
Since R0 is the output resistance when the amplifier is fed with an ideal source
Vi it follows that it is the applicable output resistance for determining A v from Avo.

( )

2) Rout which is the output resistance when vsig is set to zero.

Rout is the output resistance when the amplifier is fed with vsig and its resistance
Rs; so it is the applicable output resistance for determining Gv from Gvo.

21
 ( )

Returning to the circuit in Figure, we see by inspection that

A verification of this result is achieved by substituting Ro = ro in Equation (1) and

comparing it with resulting expression of Av ,

Which is identical.
An expression for Rout can be derived using the circuit as shown in the figure, where a
test voltage Vs is applied at the output and find the corresponding current ix and from
figure we can see that current through Rs is equal to ix thus
( )
From the circuit we can write Vx as
[ ( ) ( )
Equation (2) and (3) can be combined to eliminate V and obtain Vx in terms of ix
and hence
[ ( ) ( )
We can also express as
( )
We see by inspection

A verification of this result is achieved by substituting of equation (6) in equation

(2) and comparing it with resulting expression of Gv ,

Which is identical.
A first interpretation, immediately available from Equation (6), is that the CG transistor
increases the output resistance by adding to ro a component Avo Rs. In many cases
the latter component would dominate, and one can think of the CG MOSFET as
multiplying the resistance Rs in its source by Avo, which is approximately equal to gmRo.

22
 This impedance transformation action of the CG MOSFET is illustrated in Figure and
is a key to number of applications of the CG circuit.

One such application involves the use of the CG amplifier as a current buffer. Figure
below shows an equivalent circuit that is suitable for such an application. It can be
shown that the overall short-circuit current gain Gis is given by

( )

Proof :
We know that

23
 When RL = 0 we have

The near unity gain together with low input resistance and high output resistance are all
characteristics of a goof current buffer
Yet another interpretation of the formula for Rout can be obtained by expressing
Equation (5) in the form
[ ( )
In the expression the second term dominates enabling the following approximation as

[ ( )

Thus placing a resistance Rs in the source lead, results in multiplying the transistor
output resistance ro by a factor (1+gmRs).

High frequency response

The Figure shows the CG amplifier with the MOSFET internal capacitances Cgs and
C g d indicated. For generality, a capacitance CL is included at the output node to
represent the input capacitance of a succeeding amplifier stage. Capacitance CL also
includes the MOSFET capacitance Cdb. Note the CL appears in effect in parallel
with Cgd. Therefore, in the following discussion we will lump the two capacitances
together.

24
 It is important to note that each of the three capacitances in the circuit of figure has a
grounded node. Hence none of the capacitances undergoes the Miller-multiplication
effect seen in the CS stage. It follows that the CG circuit can be designed to have a much
wider bandwidth than that of the CS circuit, especially when the resistance of the signal
generator is large
Analysis of the circuit in figure is greatly simplified if r o can be neglected. In such a
case the input side is isolated from the output side, and the high-frequency equivalent
circuit takes the form shown in Figure (b). We immediately observe that there are two
poles: one at the input side with a frequency fp1

( || )

And the other at the output side with a frequency fp2

( )

25
 The relative locations of the two poles will depend on the specific situation. However,
fp2 is usually lower than fp1; thus fp2 can be dominant. The important point to note is that
both fp1and fp2 are usually much higher than the frequency of the dominant input pole in
the CS stage.
In situations when ro has to be taken into account (because Rs and R L are large),
the method of open-circuit time constants can be employed to obtain an estimate for the
3-dB frequency fH ,Figure shows the circuits for determining the resistances Rgs
R g d seen by Cgs and (Cgd + CL), respectively. By inspection we obtain

||

And
||
Which can be used to obtained

[ ( ) ]

26
The common base amplifier

Analysis of the common-base amplifier resembles that of the common-gate circuit

with one major difference: The BJT has a finite , and its base conducts signal current,
which gives rise to the resistance r between base and emitter, looking into the base.
The figure (a) shows the basic circuit for the active-loaded common- base amplifier
without any details of biasing.

Resistance RL represents the of load resistance, if any, and the output resistance of the
current source that realizes the active load I.
The figure shows the small-signal analysis performed directly on the circuit with the T
model of the BJT used implicitly. The analysis is very similar to that for the MOS case
except that, as a result of the finite base current, vi /r, the current io is related to ii by

27
 It can be shown that, neglecting the input resistance at the emitter Rin is given by
( )

( )
Setting = , We observe that the expression above reduces to that of the MOS case
Expect that gmb = 0 note that for = , =1, and re = / , with slight

approximation we have
( )
( )
( )
Setting ro = yields Rin = re. Also, for RL = 0, R i n = re. The value of Rin increases
as RL is raised, reaching a maximum of ( + 1 ) re = r for R L = , that is, with the

amplifier operating open-circuited For RL/( + 1) < ro, Equation (1) can be
approximated as

Where Ao is the intrinsic gain

The open circuit gain and input resistance can be easily found from the figure

Which is equal to that of the MOSFET.

28
 The input resistance with no load is given by
i = r
The output resistance is given by
Ro = ro
The output resistance including the source resistance Re can be found by analysis of the
circuit in figure
|
( )
Where
|
||

The above formula is very similar to that of the MOS case. There are two differences gmb
|
is missing and second || replaces Rs.
The above equation can also be expressed in terms of the open circuit voltage gain Avo
as
|

Another usefull form of Rout can be expressed as

|
( )
In the above expression the second term is much larger than first resulting in the
approximate expression
|
( )

29
 The inclusion of an emitter resistance Re increases the CB output resistance by a
factor (1 + gmR'e). Thus, as Re is increased from 0 to , the output resistance
increases from ro to (1 +gmr)r0 = (1 + )r0 = r0. This upper limit on the value of
Rout dictated by the finite of the BJT, has no counterpart in the MOS case and will
have important implications for circuit design. We note that for Re < r, the above

expression can be approximated by

( )
A usefull summary of the formulas for Rin and Rout is provided in figure

The results above can be used to obtain the overall voltage gain

( )

Where

30
The cascode amplifier

By placing a common gate (common base) amplifier stage in cascade with a common
source (common emitter) amplifier stage a very usefull and versatile amplifier circuit
results it is known as cascode amplifier.
The basic idea behind the cascode amplifier is to combine the high input resistance and
large transconductance achieved in a common-source (common-emitter) amplifier
with the current-buffering property and the superior high-frequency response of the
common- gate (common-base) circuit.
The cascode amplifier can be designed to obtain a wider bandwidth but equal dc gain as
compared to the common-source (common-emitter) amplifier. Alternatively, it can be
designed to increase the dc gain while leaving the gain- bandwidth product unchanged.

The MOS cascode

The figure below shows the MOS cascode amplifier

Here transistor Q1 is connected in the common-source configuration and provides its

output to the input terminal (i.e., source) of transistor Q2.
Transistor Q2 has a constant dc voltage, VBias, applied to its gate. Thus the signal voltage
at the gate of Q2 is zero, and Q2 is operating as a CG amplifier with a constant-current
load, I.

1
 Both Q1 and Q2 will be operating at DC drain currents equal to I. Feedback in the overall
circuit that incorporates the cascode amplifier establishes an appropriate dc voltage at
the gate of Q1 so that its drain current is equal to I.
The value of VBias has to be chosen so that both Q1 and Q2 operate in the saturation
region at all times.

Small signal analysis

The cascode circuit is as shown in the figure

In response to the input signal voltage V i the common-source transistor Q1

conducts a current signal g m 1 v i in its drain terminal and feeds it to the source
terminal of the common-gate transistor Q2 called the cascode transistor.
Transistor Q2 passes the signal current g m 1 v i on to its drain, where it is supplied to
a load resistance RL at a very high output resistance, R o u t . The cascode transistor
Q2 acts in effect as a buffer, presenting a low input resistance to the drain of Q1 and
providing a high resistance at the amplifier output.

2
Characteristic parameters

The figure shows the cascode circuit prepared for small- signal analysis and with a
resistance RL shown at the output.

RL is assumed to include the output resistance of current source I as well as an

actual load resistance, if any.
The figure also indicates various input and output resistances obtained using the results
of the analysis of the CS and CG amplifiers.
Note that the CS transistor Q1 provides the cascode amplifier with an infinite input
resistance. Also, at the drain of Q1 looking "downward, we see the output resistance
of the CS transistor Q1, ro1. Looking "upward," we see the input resistance of the CG
transistor Q2,

Where
( ) ( )

Thus the total resistance between the drain of Q1 and ground is

[ ]

3
From above figure, the output resistance of the cascode amplifier, Rout, is given by
( )

Substituting equation (1) in (2)

[( ) ]
This may be approximated as
[ ]
Thus the cascode transistor increases the level of output resistance by a factor equal to its
intrinsic gain, from of the CS amplifier to .
when a signal source vsig with an internal resistance Rsig is connected to the input, the
infinite input resistance of the amplifier causes.

Thus

Also note that the amplifier is unilateral thus

The open circuit voltage gain of the cascode amplifier can be easily determined
from the circuit in below Figure, which shows the amplifier operating with the output
open circuited. Since will be infinite, the gain of the CS stage Q1 will be

4
 The signal Vo1 will be amplified by the open circuit voltage gain AVo2 of the CG
transistor Q2 to obtain

Thus

For the usual case of equal intrinsic gains becomes

( )
Thus cascoding increases the magnitude of the open circuit voltage gain from A0 of the
CS amplifier to Ao2

Expression for the short circuit transconductance Gm of the cascode amplifier

From the definition of equivalent circuit
( )

We have
( )
And
R0 = Rout
Also
( )
Substituting (3) and (2) in (1)

[( ) ]
[( ) ]

This confirms the value obtained earlier in the qualitative analysis.

5
The operation of the cascode amplifier is now clear:

In response to Vi the CS transistor provides a drain current which the CG

transistor passes on to RL and, in the process, increases the output resistance by
Ao. It is the increase in Rout to Aoro that increases the open-circuit voltage gain to

(gm)(Aor0) = A2o .
Figure provides a useful summary of the operation: Two output equivalent circuits are
shown in Figure (a) and (b), and an equivalent circuit for determining the voltage gain of
the CS stage Q1 is presented in Figure (c). The voltage gain Av can be found from
either of the two equivalent circuits in Figure (a) and (b), using that in From Fig. (c)
gives

We see that if we are to realize the large gain of which the cascode is capable, resistance
RL should be large or at least it should be of the order Aoro for RL = Aoro

For RL = Aoro , Av = .

The gain of the CS stage is important because its value determines the miller effect in
that stage. From the equivalent circuit in figure (c) negating gmb

[ ( )]

6
 For

[ ( )]

Thus we see that when RL is large and the cascode amplifier is realizing a
substantial gain, a good part of the gain is obtained in the CS stage. This is not good
news considering the Miller effect,
To keep the gain of the CS stage relatively low. RL has to be lowered. For instance,
for RL = ro indicates that

[ ( )]

Unfortunately, however, in the case the DC gain of the cascode is drastically reduced, as
can be seen by substituting RL = ro in the below equation

We have

i.e. the gain of the cascode becomes equal to that realized in a single CS stage this mean
that the cascode configuration is not usefull.

Frequency response of the MOS cascode

The figure shows the cascode amplifier with all transistor internal capacitances indicated
also included is a capacitance CL at the output node to represent the combination of
Cdb2 the input capacitance of a succeeding amplifier stage (if any ) and a load
capacitance (if any)
Note that Cdb1 and Cgs2 appear in parallel, and we shall combine them in the
following analysis similarly, CL and Cgd2 appear in parallel and will be combined.

7
 The easiest and in fact quite insightful approach to determining the 3 dB frequency fH
is to employ the open circuit time constants method.

1. Capacitance Cgs1 sees a resistance Rsig

2. Capacitance Cgd1 sees a resistance Rgd1 which can be obtained as we have

( )
The above equation can be written as
( )

Where .
3. Capacitance (Cdb1 + Cgs2) sees a resistance Rd1.
4. Capacitance (CL + Cgd2) sees a resistance (RL||Rout).

With the resistance determined the effective time constant H can be computed as

[( ) ] ( ) (
)( )

And 3 dB frequency fH as

8
To see what limits the high-frequency gain of the MOS cascode amplifier, we rewrite the
equation as

[( ) ] ( ) (
)( )

In the case of a large Rsig, the first term can dominate, especially if the Miller
multiplier (1 +gm1Rd1) is large.

This in turn happens when the load resistance R L is large (of the order of Aoro),
causing Rin2 to be large and requiring the first stage, Q1 to provide a large proportion
of the gain.
It follows that when Rsig is large, to extend the bandwidth we have to lower RL to
the order of r0. This in turn lowers Rin2 and hence Rdl and renders the Miller
effect insignificant
However, the dc gain of the cascode will then be A0. Thus, while the dc gain will
be the same as (or a little higher than) that achieved in a CS amplifier, the bandwidth
will be greater.
In the case when Rsig is small, the Miller effect in Q1, will not be of concern. A
large value of RL (on the order of A0ro) can then be used to realize the large dc
gain possible with a cascode amplifier that is, a dc gain on the order of . It indicates
that in this case the third term will usually be dominant.
Consider the case Rsig = 0, and assume that the middle term is much smaller than the
third term. It follows that
( )( )
And the 3 dB frequency becomes

( )( )
Which is of the same form as the formula for the CS amplifier with Rsig = 0. Here,
however, (RLII Rout) is larger by a factor of about A0 compared to RL in CS amplifier.
Thus the fH of the cascode will be lower than that of the CS amplifier by the
same factor A0.

9
 Figure shows a sketch of the frequency response of the cascode and of the
corresponding common-source amplifier.

We observe that in this case cascoding increases the dc gain by a factor Ao while
keeping the unity-gain frequency unchanged at

( )
Difference between common source amplifier and cascode

Common Source Cascode

Circuit

DC gain -

f3db
( ) ( )

( ) ( )

10
The BJT cascode
The Figure (a) shows the BJT cascode amplifier. The circuit is very similar to the MOS
cascode, and the small-signal analysis follows in a similar way, as shown in Figure (b).

The various input and output resistances have been shown. Unlike the MOSFET cascode,
which has an infinite input resistance, the BJT cascode has an input resistance of .
The formula for Rin2 is the one we found in the analysis of the common- base circuit,
given as
( )

( )
The output resistance is given as

The open-circuit voltage gain A v o and the no-load input resistance Ri can be found
from the circuit in Figure (c) in which the output is open-circuited.

11
 Observe that R i n 2 = which is usually much smaller than ro1. As a result the total
resistance between the collector of Q1 and ground is approximately .
Thus the voltage gain realized in the CE transistor Q1 is .
Recalling that the open-circuit voltage gain of a CB amplifier is ( ) .
We see that voltage gain is

Putting all of these results together we obtain for the BJT cascode amplifier the
equivalent circuit shown in figure (a)

We note that compared to the common-emitter amplifier, cascoding increases both the
open-circuit voltage gain and the output resistance by a factor equal to the transistor .
This should be contrasted with the factor A0 encountered in the MOS cascode. The
equivalent circuit can be easily converted to the transconductance form shown in
Figure (b).

12
 It shows that the short-circuit transconductance Gm of the cascode amplifier is equal to
the transconductance gm of the BJTs.
This should have been expected since Q1 provides a current g m 1 v i to the emitter
of the cascode transistor Q2 which in turn passes the current on (assuming 2 =1) to its
collector and to the load resistance R L.
In the process the cascode transistor raises the resistance level from ro at the collector of
Q1 to r0 at the collector of Q2. This is the by now familiar current buffering
action of the common base emitter.
The voltage gain of the CE transistor Q1 can be determined from the equivalent
circuit in figure (c).

The resistance between the collector of Q1 and ground is the parallel equivalent of the
output resistance of Q1, ro
The input resistance of the CB transistor, Q2 via., Rin2. Note that for RL < ro the latter
reduces to re, However, Rin2 increases as RL is increased.
The particular interest is the value of Rin2 obtained for RL = ro, namely Rin2 = . It

follows that for this value of RL the CE stage has a voltage gain of /2.
Finally, in Figure (d) the circuit and the formulas for determining the high-frequency
response of the bipolar cascade are given.

13
A cascode current source

We know that to realize the high voltage gain of which the cascode amplifier is capable
the load resistance RL must be at least of the order of A o r o , for the MOSFET
cascode or ro for the bipolar cascode.
However, that RL includes the output resistance of the circuit which implements the
current-source load I. This implies that the current-source must have output resistance
that is at least A o r o for the MOS case (ro for the BJT case).
This means that the simple current-source circuits studied earlier cannot be considered,
since their output resistances are equal to ro. Fortunately, there is a conceptually simple
and effective solution namely, applying the cascoding principle to the current-source
implementation. This is illustrated in Figure

14
 Where
Q1 is the current-source transistor and
Q2 is the cascode transistor.
VBIAS1, is a DC voltage that is chosen so that Q1 provides the required value
of I.
VBIAS2 is chosen to keep Q2 and Q1, in saturation at all times.
While the resistance looking into the drain of Q1 is ro1, the cascode transistor
Q2 multiplies this resistance by (gm2ro2) and provides an output resistance for the
current source given approximately by
( )
Similar arrangement can be used in the bipolar case also.

Double cascoding

The essence of the operation of the MOS cascode is that the CG cascode transistor Q2
multiplies the resistance in its source, which is of the CS transistor Q1, by its intrinsic
gain to provide an output resistance .
It follows that we can increase the output resistance further by adding another level
of cascoding, as shown in Figure

15
 Here another CG transistor Q3 is added, and this results in increased output resistance by
a factor Ao3. Thus the output resistance of this double-cascode amplifier is . An
additional bias voltage has to be generated for the additional cascode transistor Q3.
A drawback of double cascoding is that an additional transistor is now stacked between
the power supply rails.
Since we are now dealing with output resistances on the order of , the current
source I will also need to be implemented using a double cascode which adds yet one
more transistor to the stack. It is appropriate to recall that in modern CMOS process
technologies VDD is only a bit more than 1V.
Note that, since the largest output resistance possible in a bipolar cascode is , adding
another level of cascoding does not provide any advantage.

The folded cascode

To avoid the problem of stacking a large number of transistors across a low-

voltage power supply, one can use a PMOS transistor for the cascode device, as
shown in Figure

Here as before, the NMOS transistor Q1 is operating in the CS configuration, but the
CG stage is implemented using the PMOS transistor Q2.

16
 An additional current-source I2 is needed to bias Q2 and provide it with its active
load. Note that Q1 is now operating at a bias current of (I1 I2).
Finally, a DC voltage VBIAS is needed to provide an appropriate dc level for the gate of
the cascode transistor Q2. Its value has to be selected so that Q2 and Q1 operate
in the saturation region
The small-signal operation of the circuit in Figure is similar to that of the NMOS
cascode. The difference here is that the signal current gmvi is folded down and made
to flow into the source terminal of Q2, which gives the circuit the name folded cascode.
The folded cascode is a very popular building block in CMOS amplifiers.

BiCMOS cascode

The circuit designer can combine bipolar and MOS transistors in circuit configurations
that take advantage of the unique features of each.
As an example, shown in figure shows two possibilities for the BiCMOS
implementation of the cascode amplifier.
In the circuit of Figure (a) a MOSFET is used for the input device, thus providing the
cascode with an infinite input resistance. On the other hand, a bipolar transistor is used
for the cascode device thus providing a larger output resistance than possible with a
MOSFET cascode.

17
 This is because of the BJT is usually larger than Ao of the MOSFET and because ro
of the BJT is much larger than ro of modern submicron MOSFETs.
The bipolar CB transistor provides a lower input resistance Rin2 than is usually
obtained with a CG transistor, especially when R L is low. The result is a lower total
resistance between the drain of Q1 and ground and hence a reduced Miller effect in
Q1.
The circuit in Figure (b) utilizes a MOSFET to implement the second level of
cascoding in a bipolar cascode amplifier.

The need for a MOSFET stems from the fact that while the maximum possible output
resistance obtained with a BJT is ro, there is no such limit with the MOSFET, and
indeed, Q3 raises the output resistance by the factor Ao3

18
 CHAPTER 5
FEEDBACK
Introduction
Harold black, an electronics engineer with western electric company invented the
feedback amplifier in 1928.

It is impossible to think electronics circuits without some form of feedback either

implicit or explicit

Feedback can be classified as

Positive
Negative

In amplifier design negative feedback is applied to effect one or more of the

following properties

1) Desensitize the gain

The value of gain is less dependent on the parameters of the amplifier
elements
2) Reduce nonlinear distortions
i.e make the output proportional to the input.
3) Reduce the effect of noise
Minimize the contribution to the output of unwanted electrical signal
generated either by the circuit components themselves or by extraneous interference.
4) Control the input and output impedances
Raising or lowering of the input and output impedances by the selection of an
appropriate feedback topology.
5) Extend the bandwidth of amplifier

All the desirable properties above are obtained at the expense of a reduction in gain

The general feedback structure

Figure shows the basic structure amplifier which is signal flow diagram.
 The quantities X can represent either a voltage or a current signal.
The open loop amplifier has a gain A thus its output xo is related to its input xi
by

The output Xo is fed to the load as well as to a feedback network which produces a
sample of the output Xf
Xf is related to Xo By the feedback factor .

i.e.
The feedback signal Xf is subtracted from the source Xs which is the input to the
amplifier circuit
i.e.
The source, load and the feedback network do not load the amplifier i.e. gain A does
not depend on any of these three networks.
The gain of the feedback

The quantity A is loop gain.

For feedback to be negative the loop gain A should be positive i.e. the feedback
should have the same sign as Xs.
 The resulting is a smaller difference Xi indicates that for positive Athe gain with
feedback Af will be smaller than the open loop gain A by the quantity 1+A
which is called amount of feedback.
If A 1 then Af = 1/ the gain is dependent on outer feedback network.
We also have

For A 1 we see that Xf = Xs i.e. the signal Xi reduces to almost zero. Thus if
large amount of negative feedback is employed the feedback X f becomes an almost
identical replica of input signal Xs
The differencing circuit is also referred to be a compression circuit or mixer.
An expression of Xi

For A 1 Xi becomes very small.

Properties of negative feedback

Gain densensitivity

A higher reduction in the gain of the basic amplifier will cause a lesser reduction in
the gain of the closed loop amplifier.

Assume is constant

We have

( )

Differentiating

( )
( )

Dividing (2) by (1)

 ( )

Shows that percentage change in Af is smaller than percentage change in A by the

amount of feedback (1+A) known as densensitivity factor.

Bandwidth extension

Consider an amplifier whose high frequency response is characterized by a single

pole its gain at mid and high frequencies can be expressed as

( ) ( )

Where
AM --- mid-band gain

WH----- upper 3 dB frequency

Application of negative feedback with frequency independent factor results in

closed loop gain Af(s) as

( )
( ) ( )
( )

Substituting (1) in (2) and on amplification

( )
( )
( )

Where

( )

( )

It can be seen that upper 3 dB frequency is increased by a factor equal to the amount
of feedback
 Similarly for a dominant low frequency pole the feedback amplifier will have a lower
3 dB frequency WLf

The amplifier gain is increased by the same factor by which mid band gain is
decreased this is illustrated as shown.

Noise reduction

Negative feedback can be employed to reduce the noise or inferences in an amplifier

or more precisely, to increase the signal to noise ratio.

The noise reduction process is possible only under certain conditions

Consider the situation illustrated as shown in the figure

 The figure shows the amplifier with gain A1 an input signal Vs and noise or
interferences Vn

It is assumed that for some reason this amplifier suffers from noise and that the noise
is introduced at the input of the amplifier.

The signal to noise ratio as

Consider the next circuit as shown in the figure

In the above figure we will assume another amplifier stage with gain A2 that doesnt
suffer from noise problem.

i.e. the amplifier A1 is precede by the clean amplifier A2 and negative feedback
around the overall cascade.

The output voltage of the above circuit is given as

( )

Thus the signal to noise ratio at the output becomes

 Which is A2 times higher than in the original case. Hence the improvement in
signal to noise ratio by the application of feedback is possible only if one precede the noisy
stage by a noise free stage.

Reduction in nonlinear distortion

The figure below shows the piecewise linear characteristics of an amplifier (A) with
voltage gain changing from 1000 to 100 and then to 0.

This nonlinear transfer characteristics will result in generating a large amount of

nonlinear distortion.

The amplifier transfer characteristics can be considerably linearized through the

application of negative feedback. Thus large changes in open loop gain gives rise to much
smaller corresponding changes in the closed loop gain.

Four basic feedback topologies

Based on the quantity to be amplified and on the desired form of output (voltage or
current) amplifiers can be classified into four categories.

Voltage amplifiers

Voltage amplifiers are intended to amplify an input voltage signal and provide an
output voltage signal.
 The voltage amplifier is essentially a voltage controlled voltage source.
The input impedance is required to be high and output impedance to be low.
Since signal source is voltage it is convenient to represent it in turns of thevenins
equivalent circuit.
The feedback network should sample the output voltage and can be mixed with
source voltage in series.
The voltage amplifier is known as voltage mixing voltage sampling as shown in the
figure
Because of series connect ion at the input and parallel connection at the output it is
also known as series shunt feedback.
This topology stabilizes the voltage gain also results in higher input resistance
because of series connection and lower output resistance because of parallel
connection.

Current amplifiers

The input signal is current and thus the signal source is represented in Norton
equivalent.
 The feedback networks should sample the output current and can be mixed with the
input in series.
The current amplifier is also known as current mixing current sampling topology as
shown in figure.
Because of parallel connection at input and series connection at the output this
feedback topology is also called shunt series feedback.
The topology stabilizes the current gain also results in lower input resistance because
of parallel connection and higher output resistance because of series connection.

An example for current amplifier is as shown in the figure

The biasing details are not shown in the figure.

The current being sampled is not the output current but the equal current flowing
from the source of Q2.
For the feedback to be negative the loop gain should be positive.
Let current Is increases hence gate voltage Q1 increases and thus drain current
will also increases.
Thus the gate voltage of Q2 decreases hence Io decreases.
From feedback network we see that if Io decreases If increases and hence feedback
is negative.
Transconductance amplifier
In transconductance amplifier the input signal is a voltage and the output signal is a
current.

The amplifier is also known as voltage mixing current sampling as shown in the
figure.
Because of the presence of series connection at both input and output this feedback
topology is also known as series - series feedback.

An example for transconductance amplifier is as shown in the figure.

Transresistance amplifier

In transresistance amplifier the input signal is current and the output signal is voltage.

The amplifier is also known as current mixing voltage sampling.

Because of the presence of parallel connection at both the input and output side the
feedback topology is also known as shunt - shunt topology

An example for transresistance amplifier is as shown in the figure

The series shunt feedback amplifier

The ideal structure feedback amplifier is as shown in the figure

It consists of a unilateral open loop amplifier (the A circuit) and an ideal voltage
mixing voltage sampling feedback network (the circuit).
The A circuit has an input resistance of Ri a voltage gain A and output resistance
Ro the source and load resistance have been included in A circuit.
The circuit doesnt load the A circuit i.e. connecting the circuit will not vary
A i.e. defined as

Open loop gain:

Closed loop gain is given as

The equivalent circuit is as shown

Here and represents input and output resistance with feedback

( )

i.e. the negative feedback increases the input resistance by a factor equal to the
amount of feedback.
It can be generalized as

Zif (s) = Zi (s) [1 + A(s)(s)]

To find output resistance Rof consider the circuit as shown in the figure
 ( )

(2)

For VS = 0

Substituting Vi in equation (2) we have

Thus

( )

Substituting (3) in equation (2) we have

i.e. negative feedback reduces the output resistance by a factor equal to amount of feedback

This can be generalized as

( )
( ) ( )

The practical situation

In practical case the series shunt feedback will not be an ideal voltage controlled voltage
source, rather the feedback network is usually resistive and hence the amplifier affecting
the values of A Ri and Ro.
In addition the source and load resistance will effect these three parameters.
The ideal structural of amplifier is as shown in figure below

Rif - input feedback resistance. Rof output feedback resistance

Rin input resistance of A circuit Rout output resistance of A circuit

 The two port feedback in terms of h parameters is illustrated in figure:
The choice of h parameter is based on the fact that this is the only parameter that
represents the feedback network by a series network at port1 and parallel network at
port2.

The current source h21I1 represents the forward transmission of feedback network.
Since the feedback network is usually formed from passive elements its forward
transmission can be neglected when compared to forward transmission of amplifier.

Hence
| | | |

Hence omitting the controlled source altogether.

By including h11 and h22 with basic amplifier we obtain the circuit as shown which is
very similar to that of ideal circuit
 The loading effect of the feedback network on the basic amplifier is represented as h11
and h22
h11 is the impedance looking in port 1 of the feedback network with port 2 short
circuited, since port 2 feedback network is connected in shunt with the output port of the
amplifier short circuiting port 2 destroys the feedback.
Similarly h22 is admittance looking into port 2 of feedback network with port 1 open
circuited since port 1 feedback network connected in series with the amplifier input open
circuiting port 1 destroys the feedback.

Determination of
equal to h12 of feedback network, hence

Apply voltage to port 2 of the feedback network and measure the voltage at port 1 and
should be found with port 1 open circuit
The actual input and output resistance of the feedback amplifier that can be determined as
Note:

Summary

Where R11 is obtained as

Where R22 is obtained as

is obtained as

Determining the loop gain:

Consider the general feedback amplifier as shown in the figure:

Let the external source xs be set to zero
Open the feedback loop by breaking the connection of xo to the feedback network and
apply test signal xt.
 The output at feedback is given as:

The input of the basic amplifier is

The output of the basic amplifier is

Once we break the feedback loop it should be terminated by impedance equal to that seen
before the loop.
Consider the conceptual feedback loop as shown
 If we break loop at XX| and apply a test voltage Vt to the terminal left of XX|.
The terminal at the right of XX| should be loaded with an impedance Zt as shown in the
figure

Hence

Also in terms of current

Alternative approach to find A

This method is particularly usefull when it is not easy to determine the terminal
impedance Zt.
As before the loop is broken at a convenient point then the open circuit transfer function
is determined (Toc) as shown in the figure and short circuit transfer function is determined
to obtain loop gain (A) as

Where
Ex: Determination of loop gain
The feedback loop is as shown in the figure

The simple equivalent circuit model is as shown

Breaking the circuit and adding a test voltage Vt we have the circuit as shown
 The return voltage can be calculated as

{ || ( )||( ) |} ||( )
{ || ( )||( |} ||( )

Finally finding Vr we can calculate

Loop gain is also called loop transmission L(s) or L(jw).

The stability problem

Transfer function of the feedback amplifier

The open loop transfer function given as: A(s)

The feedback transfer function given as: (s)
The closed loop transfer function is given as: Af(s)
Hence
( )
( )
( ) ( )
Assume that the amplifier is direct coupled with constant DC gain Ao
Also assume that at low frequencies (s) reduces to a constant value thus at low
frequency A(s) (s) becomes a constant.
At high frequencies S = jw
( )
( )
( ) ( )

Loop gain
( ) ( ) ( )

=| ( ) ( )|
Stability of the closed loop transfer function

1. For loop gain smaller than unity at w180

Becomes positive feedback.
Closed loop gain becomes larger than open loop gain.
The feedback amplifier is stable.
2. For loop gain equal to unity
It follows that Af(jw) will be infinite
The amplifier will have output for zero input (oscillation)
3. For loop gain longer than unity at w180
Oscillation with growing amplitude at the output.

Nyquist plot
A plot used to evaluate the stability of feedback amplifier.

Plot the loop gain versus frequency on the complex plane.

The radical distance is |A| the angle is the phase angle .
The solid line plot is for positive frequencies.
The A plot for negative frequencies is indicated in broken lines.
The nyquist plot intersects the negative real axis at W180.
If intersection occurs to the left of point (-1, 0) the loop gain is greater than unity and
amplifier is unstable.
If intersection occurs to the right of the point (-1, 0) the amplifier is stable.
If nyquist plot encircles the point (-1, 0) then also the amplifier will be unstable.
Effects of feedback on the amplifier poles

Stability and pole location

Consider the equation as

( ) ( )

If pole should lie in the left half of the S plane then the o will be negative and the
oscillation will delay exponentially towards zero.
If on the other hand the poles are in the right half the plane then the o will be positive
and the oscillation will grow exponentially.
Finally if poles are on the jw axis then the o will be zero and oscillation will be
sustained as shown in the figure.
Poles of the feedback amplifier

The characteristics equation of feedback loop is given as

( ) ( )

The feedback amplifier poles are obtained by solving the characteristics equation

Amplifier with a single pole response

Open loop transfer function is characterized by a single pole

( )

Closed loop transfer function given by

( )
( )
( )

Feedback moves the pole along the negative real axis to a frequency

( )

This process is as shown in the figure

 The figure below shows bode plots for |A| and |Af|

Note at low frequencies the difference between plot is 20 log(1+ ) whereas the two
curves coincide at high frequencies.
Hence for frequencies ( )

We have

( ) ( )

Hence the figure illustrates that bandwidth is extended by feedback at the cost of
reduction in gain.
Since the pole of the closed loop amplifier never enters the right half of the S plane the
single pole amplifier is stable for any value of thus unconditionally stable.

Amplifier with two poles response

Open loop transfer function is characterized by two real poles

( )
( )( )

Closed loop poles are obtained from ( ( ) leads to

( ) ( ) ( )

The plot of poles versus is called root locus diagram

 From the root locus diagram we see that this amplifier is unconditionally stable because
the poles never enters the right half plane.
The characteristics equation of second order network is given as

( )

Where

The normalized gain of a two pole feedback amplifier for various values of Q

Comparing (1) and (2) we obtain Q factor for the poles of the feedback amplifier as

( )
Amplifier with three or more poles

The figure shows the root locus diagram for a feedback amplifier whose open loop
response is characterized by three poles.

As A0 increased the poles become complex conjugate poles and enters the right half of
the S plane, thus causing the amplifier to become unstable.
Reducing A0 below the critical value causes the nyquist plot to shrink and thus
intersect the negative real axis to the right of (-1, 0) point indicating stable performance.
Increasing A0 above critical point or value causes the nyquist plot to expand and thus
indicating unstable performance.
Alternatively we can state that there exists minimum value for the closed loop gain Afo
below which the amplifier is unstable.
There exists a maximum value of above which the amplifier is unstable.
 CHAPTER 7
DIGITAL IC TECHNIQUES AND LOGIC CIRCUITS
The figure below shows the major IC technologies and logic circuit families that are
currently in use

Each logic circuit family offers a unique set of advantage and disadvantage

The selection of the family is based on such considerations, as logic flexibility, speed
of operation, availability of complex functions, noise immunity, operating temperature range
power dissipation cost.

CMOS
CMOS technology is most widely used dominant technology, it is mainly because of
lower power dissipation, high package density than an BJT device,.
The high input impedance of the MOS transistor allows the designer to use charge
storage as a means for the temporary storage of information this technique cannot be
used in bipolar circuits.
The feature size of MOS transistor has decreased this provides very tight packaging
and correspondingly very high levels of integration
COMPLEMENTARY CMOS is used in VLSI logic and memory circuit design
CMOS logic circuit utilizes dynamic technique to obtain faster circuit.
BIPOLAR
There are to two logic circuit families based on BJT are
1. TTL transistor transistor logic.
2. ECL Emitter coupled logic.
TTL or T2L was for many years the most widely used logic circuit family. It declined
due to the advent of VLSI era.
However the manufacturers introduced low power and high speed versions BJTs
The higher speed of operation are made possible by preventing the BJT from
saturating and thus avoiding slow turn off.
Schottky diodes are used in TTL newer versions, now a days TTL logic family is not
used.
ECL is the basic element used in differential BJT pair, ECL is basically a current
steering logic and correspondingly also called current mode logic.
ECL occupies more area and power dissipation is more.

BICMOS
Bi CMOS combines low power dissipation CMOS and high speed Bi polar
technology
Digital and analog circuits can be implemented using Bi CMOS.
More complex process technology is required to develop high performance memory
chips.

GALLIUM ARSENIDE
Very high speed of operation can be obtained using Ga-As technology. Due to the
high Carrier mobility. Ga-As technology is one of the emerging technologies has
great potential.

Logic circuit characterization

The following parameters are used to characterize the operation and performance of logic
circuit family

1. Noise margins
 2. Propogation delay
3. Power dissipation
4. Delay power product
5. Silicon area
6. Fan in fan out

Noise margin
Noise margin is the allowable input gate voltage so that output will not be affected.
The figure shows voltage transfer characteristics of inverter and it defines four
parameter VOH, VOL, VIL, and VIH and also Vm or Vth

Thus the noise margins NMH and NML given as

NMH = VOH - VIH
NML = VIL VOL
For an ideal inverter
NMH = NML = VDD/2
Propagation delay
The propagation delay of basic inverter circuit is as shown in the figure

The propagation delay of an inverter is given as

( )

Where

Power dissipation
In digital circuit design power dissipation is one of the important issue. The power
dissipation per gate and per memory cell should be less. This is particularly in battery
operated equipment such as cellular phones and PDAs.
There are two types of power dissipations in logic gate
1. Static
2. Dynamic
 Static power refers to the power that the gate dissipates in the absence of switching
action.
Dynamic power on other hand occurs only when gate is switched. An inverter operated
from a power supply VDD and driving a load capacitance C dissipate power PD

Where, f frequency of the inverter.

Delay power product

Circuit designers are mainly interested in developing a high speed combined with low
power dissipation circuits. Unfortunately these two requirements are often in conflict
I.e. if one attempts to reduce power dissipation by decreasing supply voltage or
supply current or both, the current driving capability of the gate reduces, this in turn takes
longer time to charge and discharge the load and thereby increase in delay hence delay power
product is defined as

Where
And

Silicon area
The ultimate aim of designing digital VLSI circuit is to minimize Si area, such that
large number of gates per chip can be achieved by decreasing the area of single gate.
Area reduction occurs in three different ways:
Advancement in processing technology enables reduction of the minimum device
size.
Through advancement in circuit design techniques.
Through carefull chip layout.

Fan in and Fan out

The fan in of a gate is the number of its inputs. Thus a four input NOR gate has a fan
in of four
The Fan - out is the maximum number of similar gates that a gate van drive.
If the BJT inverter Fan out is increased VOH and NMH is reduced.
Styles of digital system design
The approach to design digital system consists of assembling the system using
standard IC packages.
The advent of VLSI, has helped the system designers with more power full off the
shelf components such as microprocessors and memory chips, has made possible
alternative design styles.
The circuit designers opt for implementing part or all of the system using one or
more custom VLSI chips.
IC design technology is usually economically justified only when the production
volume is large.
An intermediate approach known as semicustom design utilize gate arrays and chips
A more recently available type of gate array known as field programmable gate array.
FPGA provide a very convenient means for the digital system designers to
implement complex logic function of VLSI.

Design Abstraction
Consider the process of designing a digital system using off the shelf packages of
logic gates.
The designer consults data sheets to determine the input and output characteristics of
the gates, their Fan - in, Fan out limitations and so on.
In connecting gates the designer need to follow set of rules specified by
manufacturers data sheet.
The designer doesnt need to consider the circuit inside the gate package, in effect the
circuit has been abstracted in the form of block that can be used as components this
generally simplifies system design.
Circuit blocks are designed, characterized and stored in a library as standard cells
these cells can be used by a IC designer to assemble a larger subsystem.
Simulation and other programs are required at any level of design abstraction which
helps design process as automated as possible.
Spice is employed in circuit simulation, other software tools are utilized at other
levels and in other phases of design process.
Design and performance analysis of the CMOS inverter
Circuit structure
The inverter circuit is as shown in the figure below

The structure consists of a pair of complementary MOSFETS switched by the input

voltage Vi
The source of each device is connected to its body (not shown in the figure)
eliminating body effect.
The threshold voltages Vtn and Vtp are equal in magnitude i.e. | | | |
The inverter circuit can be represented by a pair of switch as shown in he figure each
switch is modeled by a finite on resistance i.e. source drain resistance of respective
transistor given as

Static operation
With VI = 0V, Vo = VOH = VDD and the output node is connected to VDD through the
resistance of the pull up transistor QP.
With VI = 1V, Vo = VOL = 0 and the output node is connected to ground through the
resistance of the pull down transistor Qn.
In the steady state no direct current path between VDD and ground, and the static current
and the static power dissipation are both zero.
 The voltage transfer characteristics of the inverter is as shown in the figure

CMOS inverter can be made to switch at the mid-point of the logic swing o to VDD i.e. VDD/2
the switching threshold Vth is given by
| |

| |
Where and

For

If then matching is achieved by

If the inverter is required to drive a relatively large capacitance load the transistor are
made wider however to conserve chip area most of the inverter would have minimum
size.
Inverter are given as
( ) ( )
The area for minimum size transistor is given as
||
Dynamic operation
The propagation delay of the inverter is usually determined under the condition that it
is driving an identical inverter which is as shown in the figure

The circuit consists of transistor Q1 and Q2 which is driven by low impedance source
VI and loaded by inverter comprising of Q3 and Q4 with required capacitance as
shown
An exact paper and pen analysis is complicat4ed to yield usefull design in sight.
Hence we wish to replace all the capacitances attached to the circuit, specifically
replacing the capacitance attached to the inverter output node with a single
capacitance.
Considering the contribution of each of the capacitance in figure as
The gate drain capacitance of Q1 Cgd1 can be replaced by an equivalent
capacitance between the output node and ground by 2Cgd1. This is due to
miller effect. Same applies for gate drain capacitance of Q2 Cgd2 replaced as
2Cgd2.
The drain body capacitance Cdb1 and Cdb2 has a constant voltage. Cdb1
and Cdb2 can be replaced with equal capacitance between output node and
ground.
 Since second inverter doesnt switch states we will assume the input
capacitances Q3 and Q4 remain approximately constant and equal to the total
gate capacitance.

The last capacitance of C is the wiring capacitance CW which simply adds to the
value of C
Hence total capacitance:

To determine
The circuit is as shown in the figure

In figure (a) when VI goes high and QN discharge C from its initial voltage VDD to
the final value of 0
Initially QN will be operating in saturation region
 i.e.

At t = 0 the current expression is given as

|
( )

Att = 0 QN will be operating in triode region the current expression is given as

i.e.

At t = 0 the current expression is given as

|
( ) [ ]

The average discharge current

| [ ]

And discharge interval computes as

|
( )

Note Simplification:
Using Vt = 0.2 VDD in equation (2) we have
|
[ ]

|
[( ) ]

|
[( )]

|
( ) [ ]
 Simplifying equation (1) we have
|
( )

|
( )

|
( )

Substituting (5) and (6) in (3) we get

|
{ ( ) [ ]}
|
|
{ ( ) [ ]}
|

Substituting (7) in (4) we get

|
{ ( ) [ ]}

|
( )

Finally propagation delay is given as

( )

Observations:
The two components of tp can be equalized by selecting (W/L) ratio to be equalize
Kn and Kp i.e. by matching Qn and Qp.
tp is proportional to C the designer should strive to reduce C . This is achieved
by using the minimum possible channel length and by minimizing wiring and other
parasitic capacitance.
Larger transconductance parameter results in shorter propagation delay.
Larger (W/L) ratio results in shorter propagation delay.
Larger supply voltage results in shorter propagation delay.
Dynamic power dissipation
The dynamic power dissipation is given as

Where f is the frequency at which gate is switched

If C is as an effective means for reducing dynamic power dissipation
The case of lower power voltage also reduces power dissipation.

CMOS logic circuits

Basic Structure
Let us consider the basic structure of an inverter
The inverter consists of an PMOS pull up transistor and NMOS pull down transistor
Hence the CMOS logic gate consists of two networks
Pull down network (PDN) constructed of NMOS transistors.
Pull up network (PUN) constructed of PMOS transistors.
The two networks are operated by the input variables in a complementary fashion.
Consider the network as shown in the figure

Thus for the three input gate operated by the input variables in a complementary
fashion
The PDN will conduct for all input combination that require a low output y = 0 and
then pull the output node down to ground causing a zero output, at that same time
PUN will be off and no direct path exists.
 On the other hand all input combinations that call for a high output will have the
PUN to conduct i.e. the PUN will then pull the output node to VDD at the same time
PDN will be cutoff.
PDN comprises of NMOS transistors and since an NMOS transistor conduct when
the signal at its gate is high the PDN is activated when the input s are high
PUN comprises of PMOS transistors and a PMOS transistors conducts when the
input signal at its gate is low thus PUN is activated when the input are low.

Examples of PDN
Consider the circuits as shown in the figure

We observe that QA will conduct when A is high and

will then pull the output node down to ground i.e. y = 0.
Similarly QB conducts and pulls Y down when B is
high which can be expressed as

The PDN will conduct when A and B are

both high simultaneously, thus Y will be low when
A is high and B is high.

The PDN will conduct and cause Y to be

low when A is high or B and C are both high
thus we have


Examples of PUN
Consider the circuits as shown in the figure

The pull up network will conduct and cause

Y to be high if A is low or B is low thus

The pull up network will conduct and cause Y

to be high only when A and B are both low thus

The pull up network will conduct and cause

Y to be high only when A is low or if Band C
are both low thus

Alternative circuit symbols for MOSFETs.

The symbols are as shown in the figure

A PMOS transistor with a circle indicates that gate terminal is intended to indicate
that the signal at gate has to be low.
The drain is the terminal that is at higher voltage in NMOS transistor.

The two input NOR gate

We first consider the CMOS gate that realizes the two input NOR function.i.e.

Truth table

A B
0 0 1
0 1 0
1 0 0
1 1 0
 Y should be low when A is high or B is high thus PDN
Consists of two parallel NMOS devices.
Y should be high when A and B both are low, the PUN consists of two series
PMOS devices with A and B as inputs.
Putting the PDN and the PUN together gives rise to CMOS NOR gate.

The two input NAND gate

We first consider the CMOS gate that realizes the two input NAND function i.e.

Truth table

A B
0 0 1
0 1 1
1 0 1
1 1 0

If Y to be low both A and B should be high, thus PDN simply comprises two
NMOS transistors in series.
If Y to be high either of the input should e low thus PUN simply comprises of two
PMOS transistor in parallel.

Complex gates
There are few important gates that are complex but find extensive use in digital
systems. These are AND-OR-INVERTER (AOI) and OR-AND-INVERTER (OAI)
gates.
AOI and OAI functions can be implemented with just one gate level transistor.
It is interesting to see that AOI and OAI gates are essentially representation of SOP
(sum of products) and POS (product of sum ) expressions of functions.
Consider the logic function:
1)
Here AB and CD are two AND functions and their sum is the OR function,
which is finally inverted. Thus F can be implemented as an AOI gate.
The figure below shows the CMOS realization of an AOI gate and its logic
equivalent circuit along with the truth table.
2)

Here A+B and C+D are two OR functions and their product is the AND
function, which is finally inverted. Thus F can be implemented as an OAI gate.
The figure below shows the CMOS realization of OAI gate and its logic
equivalent circuit along with the truth table.
3)

The PDN is easily obtained since is a function of the uncomplemented

variables.
To obtain PUN we need to express Y in terms of the complemented variables.
We do this through repeated application of Demorgans law as follows




The figure below shows the CMOS realization of the circuit.

4)
The PUN is easily obtained since Y is a function of the complemented variables.
To obtain PDN we need to express Y in terms of as uncomplemented variables.
We do this through repeated application of Demorgans law as follows.








Hence the CMOS realization of the circuit is as shown in the figure

Other way of PDN can also we considered i.e. by inverting the XNOR function we
obtain XOR function i.e. in turn we expressing Y in terms of as uncomplemented
variables.

Considering an inversion we obtain XOR nothing but , Hence we have


Hence the CMOS realization of the circuit is as shown in the figure
Observations
The PDN can be most directly synthesized by expressing as a function of
uncomplemented variables. If complemented variables appear in the expression additional
inverters will be required.
The PUN can be most directly synthesized by expressing Y as a function of
complemented variables and then applying the uncomplemented variable to the gates of the
PMOS transistor. If complemented variables appear in the expression additional inverters are
required.
From the CMOS circuits considered thus far we observe that the PDN and the PUN
are dual networks: where a series branch exists in one, a parallel branch exists in the other.
Thus, we can obtain one from the other a process that can be simpler.

Transistor Sizing
Once CMOS circuit is generated the only significant step remaining in the design is
to decide (W/L) ratios for all the devices.
These ratios are selected to provide the gate with current driving capability.
Let and where n is usually 1.5 to 2 and for matched
design p = ( .

W/L ratio is based on the fact that the on resistance of a MOSFET is inversely
proportional to (W/L).
Thus if (W/L)1 , (W/L)2 are connected in series the equivalent series resistance
obtained adding the on resistances.
i.e.

( ) ( )

[ ]
( ) ( )
 [ ]
( )

( )

[( ) ( ) ]

Similarly if the transistors are connected in parallel with (W/L) ratios of ( ) ( )

results in

( ) ( ) ( )

Example:
Thus if (W/L) ratio of a two transistors is 4 then

Connected in series ( )

Connected in parallel( ) .

Consider four input NOR gate as shown in the figure

 PDN is obtained when only one of the NMOS transistor is conducting hence we
select (W/L) ratio of each NMOS transistor to be equal to that of the NMOS transistor
of basic inverter which is as indicated in the figure as n.
For PUN when all inputs are low, the four series PMOS transistor will conduct, since
the equivalent be of that of each PMOS device we should select the W/L ratio of
PMOS transistor to be four times that of the PMOS transistor of basic inverter which
is indicated in the figure as 4P.

Similarly considering the NAND gate we have

For PDN since the equivalent be of that of each NMOS device we should select
the W/L ratio of NMOS transistor to be four times that of the NMOS transistor of
basic inverter which is indicated in the figure as 4n.
PUN is obtained when only one of the PMOS transistor is conducting hence we
select (W/L) ratio of each PMOS transistor to be equal to that of the PMOS transistor
of basic inverter which is as indicated in the figure as p.
Effects of Fan in and Fan out
Each additional input to the CMOS gate requires two additional transistors i.e. one for
PMOS and other for NMOS.
The additional transistor in CMOS not only increases chip area but also increases the
effective capacitance per gate and in turn propagation delay.
The size scaling method, described will however preserve the current driving
capability.
If tp increases then it imposes a practical limit on the Fan- in and Fan out, if a
higher number of inputs are required means a clever design should be employed to
realize the functions.
Thus although CMOS have many disadvantage it does suffer from increased
complexity when Fan in and Fan out are increased i.e. chip area and propagation
delay is increased.

Pass transistor logic

Single approach for implementing logic functions utilizes series and parallel
combinations of switches that are controlled by input logic variables to connect the
input and output nodes
Each switch can be implemented either by a single NMOS transistor or a pair of
CMOS transitory connected what is known as CMOS transmission gate.
This form of logic utilizes MOS transistors in the series path from input to output to
pass or block signal transmission known as pass transistor logic.
An essential design requirement
An essential requirement in the design of PTL circuits is ensuring that every circuit
node has at all times a low resistance to VDD and ground.
Consider the circuit as shown in the figure

Switch S1 is used to form the AND function of its controlling B and A at the
output of CMOS inverter.
The output Y of the PTL circuit is as shown connected to the input of another
inverter.
If B is high S1 closes and Y=A, i.e. Y will be then connected to either to VDD

through Q2 or to ground through Q1

When B goes low and S1 opens, node Y becomes high impedance node, if

initially Vy is zero it will remain so, if Vy was high at VDD, this voltage is

maintained by the charge on the C but only for a time and finally diminishes to zero.

In case the circuit can no longer be considered as a static combinational logic circuit.

This problem can be solved by establishing for node Y a low resistance path that is

activated when B goes low which is as shown in the figure.

 Here another switch S2 controlled by B is connected between Y and ground.

When B goes low S2 closes and establishes a low resistance path between Y and

ground.

Operation with NMOS transistor as switch

PTL circuit with single NMOS transistor results in a simple circuit with small area

and small node capacitances.

Consider the circuit as shown in figure

 Here NMOS transistor Q is used to implement a switch connecting the input node

with output node.

The switch is shown in the closed state with the control signal applied to gate being at

high state i.e. VDD.

As the input voltage Vi goes high at t=0 initially we assume that output voltage is

zero, the transistor operates in saturation mode and delivers current id the transistor

operates in saturation mode and delivers current id

i.e. [ ]

Where

[ ]

The high output voltage will not be equal to VDD rather it will be lower by Vt i.e.

VDD Vt.

Figure shows NMOS switch circuit when Vi brought down to zero.

Assume initially Vo = VDD thus the transistor operates at saturation

i.e. [ ]
 Since source is now at zero volts (note source and drain has interchanged roles), the

C discharge continuously and transistor enters the triode region later C gets fully

discharged and transistor provides VOL = 0V.

The use of CMOS transmission gates as switches

The TG utilizes a pair of complementary transistors connected in parallel which acts

as an excellent switch providing bidirectional current flow.

It exhibits on resistances that remain constant for wide range of input voltage.

The figure below shows the transmission gate switch in the on position with input

Vi rising to VDD.

A time t = 0 assume that initial output voltage is zero we see QN will be operating in

saturation providing

[ ]

Where

[ ]

However transistor QP operates with VSG = VDD and initially in saturation

[ ]
 The total capacitor charging current is the sum of iDN and iDP, Qp will enter to triode

region at V0 = |Vtp|, but will continue to conduct until C is fully charged.

The figure below shows the transmission gate switch in the on position with input

Vi goes to low.

QN and QP interchange roles when Vo falls below Vtp transistor Qp will cease

conduction where Vtp is given as

[ ]

Transistor Qn however conducts until C is fully discharged i.e. Vo = VOL = 0V.

We conclude that transmission gates provides far superior performance than single

NMOS switches. The disadvantage is increased circuit complexity, area, and

capacitance.

Pass transistor logic examples

1) Two to one multiplexer:

The Figure below shows a PTL realization of Two to one multiplexer

Depending on the logic value of C either A or B is connected to the output Y.

The circuit realizes thee Boolean function

2) XOR

The figure below shows a PTL realization of XOR function

The circuit utilizes four transistors in the TG and another four for two inverters

needed to generate the complements A and B i.e. is a total of eight transistors is used.

Note that 12 transistors are needed in the realization with complementary CMOS.
3) AND & NAND function Complementary pass transistor logic (CPL)

The figure below shows a PTL realization of AND & NAND functions

It uses NMOS switches with low or zero threshold

Observe that both input variables and their complements are employed so that the

circuit generates both Boolean functions thus this form of circuit is known as CPL.

The circuit consists of two identical network of pass transistors with the

corresponding transistor gate controlled by the same signal (B and ). The input to

the PTL however are complemented A and B for the first network and It uses

for the second. The circuit realizes both the AND and NAND functions.

Dynamic logic circuits

CMOS excels in nearly every performance category

It is easy to design.

It has maximum possible logic swing.

It is robust from a noise immunity stand point.

Dissipates no static power.

Designed to provide equal low to high and high to low propagation delays.
 Its main disadvantage is the requirement of two transistor per gate by which the area

of chip increases, and thereby increasing the total capacitance and correspondingly

propagation delay and dynamic power dissipation.

Basic principle:

The figure below shows the basic dynamic logic gate

It consists of a PDN that realizes the logic function in exactly the same way as the

PDN of a CMOS gate or PSEUDO NMOS gate.

Here we have two switches in series that are periodically operated by clock signal

whose waveform is as shown in the figure.

When is low Qp is turned on and the circuit is said to be in pre-charge phase

when is high Qp is off and QC turns on and the circuit is in evaluation phase.

CL denotes the load capacitance.

 During pre-charge Qp conducts and charges capacitance CL so that at the end of

pre-charge interval the voltage at the point Y is equal to VDD also during pre-

charge the inputs A, B and C are allowed to change and settle to their proper values

observe that Qn is off no path to ground exists.

During Evaluation phase Qp is off and Qn is turned on now if the input combination

is one that corresponds to a high output, the PDN does not conduct and remains high

at VDD.

If the combination of input is one that corresponds to low output the appropriate

NMOS transistors will conduct and establishes a path between the output node and

ground through the on transistor Qn thus CL will be discharged through the PDN.

Non ideal effect

1) Noise margin :
Since during the evaluation phase the NMOS transistors begin to conduct for Vi = Vtn
and thus the logic margins will be

2) Output voltage decay due to leakage effects

In the absence of a path to ground through PDN, the output voltage will
ideally remain at VDD. This however is based on the assumption that the
charge on CL will remain intact.
In practice, there will be leakage current that will cause C L to slowly
discharge. The principle source of leakage is the reverse current of the reverse
biased junction between the drain diffusion of transistors connected to the
output node and substrate. Thus the circuit can malfunction if the clock is
operating at a very low frequency and the output node is not refreshed
periodically.
3) Charge sharing
There is another and often serious way for CL to lose some of its charge
consider the following figure

The figure shows transistor Q1 and Q2 the two top transistors of the PDN
together with the pre-charge transistor Qp.
At the beginning of the evaluation phase after Qp has turned off and with
CL charged to VDD.
We assume that at the gate Q1 we have a high signal whereas at the gate of
Q2 the signal is low. We can easily see that Q1 will turn on and its drain
current iD1 will flow as indicated.
Thus iD1 will discharge CL and charge C1 although eventually iD1 will
reduce to zero, CL will have lost some of its charge, which will have been
transferred to C1 this phenomenon is known as charge sharing.
 Consider the situation depicted in figure where two single input dynamic logic gates
are connected in cascade. During the pre-charge phase CL1 and CL2 will be charged through
Qp1 and Qp2 respectively.

Now consider evaluation phase for the case of high input A obviously, the correct
result will be Y1 low and Y2 is high. As the evaluation begins Q1 turns on and CL1
begins to discharge simultaneously, Q2 turns on and CL2 also begins to discharge,
however by that time CL2 will have lost a significant amount of its charge. It is important to
note that in dynamic logic once charge has been lost it cannot be recovered.

Dominos CMOS logic

Dominos CMOS logic is a form of dynamic logic that results in cascadable gates.
Which is as shown in the figure.
 We observe that it is simply the basic dynamic logic gate with a static inverter
connected to its output.
Operation of the gate is straightforward during pre - charge X will be raised to
VDD and the gate output Y will be 0V. During evaluation depending on the
combination of the input variables either X will remain high and thus the output Y
will remain low or X will be brought down to 0V and the output Y will rise to
VDD thus during evaluation the output either remain low or makes only one low to
high transition.

Consider the situation as shown in the figure where we show Domino gates connected in
cascade. For simplicity, we show single input gates.

At the end of pre-charge, X1 will be at VDD, Y1 will be at 0V, X2 will be at VDD,

Y2 will beat 0V,
As the preceding case, assume A is high at the beginning of evaluation. Thus
goes up, capacitor CL1 will begin discharging pulling X1 down. Meanwhile, the low input
at the gate of Q2 keeps Q2 off, and CL2 remains fully charged.
When VX1 falls below the threshold voltage of inverter I1, Y1 will go up turning on Q2
on, which in turn begins to discharge CL2 and pulls X2 low. Eventually, Y2 rises to VDD.
From this we see that because the output of the domino gate is low at the beginning of
evaluation, no premature capacitor discharge will occur in the subsequent gate in the cascade.